Split (1)

train · 101k rows

content stringlengths 1 1.04M ⌀
library verilog; use verilog.vl_types.all; entity hazard_detect is port( rst_b : in vl_logic; mask_of_real_read_reg: in vl_logic_vector(2 downto 0); read_reg_num : in vl_logic; IDEX_rd_we : in vl_logic; EXMEM_rd_we : in vl_logic; IDEX_rd_num : in vl_logic_vector(3 downto 0); EXMEM_rd_num : in vl_logic_vector(3 downto 0); stall : out vl_logic; IFID_Write : out vl_logic; PCWrite : out vl_logic ); end hazard_detect;
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c Y2O4fk1xOw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV FIedseAJGSJjdgeT43M= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c Y2O4fk1xOw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV FIedseAJGSJjdgeT43M= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c Y2O4fk1xOw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV FIedseAJGSJjdgeT43M= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block bHuGx6phwwi065A2gw0E1Tqc2OLDUoohEHY7mOoJcUQwvr9OEJ4yz01Uls3wx2UOc24N+ANXe8aM YdyfwspjYSBviz8nI/XUT5fPMjNbtL8HFChLorcX+K00Sc+A9m1I9+5W+Wd6GLSKBCVYKnWRn9Os rc68y/GTowadTW08aEEccqOavDD8XG+R6gQqGpi5C8xq75oqBRmE5yNpxpBXxQRz9mmAsJcZ773H BpObF8UUngkYlRzDjfxz3vzf6lVAPrLm55l1zEsel1LRtdqlRT8kBTrz1kke43v4c6xNv0u+i1Y0 dvxmNCEmLNrwBuVbcA8l6Jjp0k0WZScEgrEOCA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 4sCk5d4E+rPjLUhUiUrzCNkXo2ztvWgfU4Ic3n3YDGHZzWC7cjzTKSJroiCXwtIaQEIL5FpdrGOo eHf9JlqikZvG/pLSpSZr6BTZioOpsjgI4CJq9n0wGhpyClKm24hGzYEPH8AkBs4wVmgt4sOHvyYc mYqTUQDFFlehrx6Wh0E= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block cjjanW9F+fseEMt2SDd6R3KYZVrfLHKeq8ULFHbP0E7BiwY4Vkec6zVJkc5FOAAhZdR5Ywc2FOnS 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c Y2O4fk1xOw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV FIedseAJGSJjdgeT43M= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block bHuGx6phwwi065A2gw0E1Tqc2OLDUoohEHY7mOoJcUQwvr9OEJ4yz01Uls3wx2UOc24N+ANXe8aM YdyfwspjYSBviz8nI/XUT5fPMjNbtL8HFChLorcX+K00Sc+A9m1I9+5W+Wd6GLSKBCVYKnWRn9Os rc68y/GTowadTW08aEEccqOavDD8XG+R6gQqGpi5C8xq75oqBRmE5yNpxpBXxQRz9mmAsJcZ773H BpObF8UUngkYlRzDjfxz3vzf6lVAPrLm55l1zEsel1LRtdqlRT8kBTrz1kke43v4c6xNv0u+i1Y0 dvxmNCEmLNrwBuVbcA8l6Jjp0k0WZScEgrEOCA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 4sCk5d4E+rPjLUhUiUrzCNkXo2ztvWgfU4Ic3n3YDGHZzWC7cjzTKSJroiCXwtIaQEIL5FpdrGOo eHf9JlqikZvG/pLSpSZr6BTZioOpsjgI4CJq9n0wGhpyClKm24hGzYEPH8AkBs4wVmgt4sOHvyYc mYqTUQDFFlehrx6Wh0E= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block cjjanW9F+fseEMt2SDd6R3KYZVrfLHKeq8ULFHbP0E7BiwY4Vkec6zVJkc5FOAAhZdR5Ywc2FOnS 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c Y2O4fk1xOw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV FIedseAJGSJjdgeT43M= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c Y2O4fk1xOw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV FIedseAJGSJjdgeT43M= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block bHuGx6phwwi065A2gw0E1Tqc2OLDUoohEHY7mOoJcUQwvr9OEJ4yz01Uls3wx2UOc24N+ANXe8aM YdyfwspjYSBviz8nI/XUT5fPMjNbtL8HFChLorcX+K00Sc+A9m1I9+5W+Wd6GLSKBCVYKnWRn9Os rc68y/GTowadTW08aEEccqOavDD8XG+R6gQqGpi5C8xq75oqBRmE5yNpxpBXxQRz9mmAsJcZ773H BpObF8UUngkYlRzDjfxz3vzf6lVAPrLm55l1zEsel1LRtdqlRT8kBTrz1kke43v4c6xNv0u+i1Y0 dvxmNCEmLNrwBuVbcA8l6Jjp0k0WZScEgrEOCA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 4sCk5d4E+rPjLUhUiUrzCNkXo2ztvWgfU4Ic3n3YDGHZzWC7cjzTKSJroiCXwtIaQEIL5FpdrGOo eHf9JlqikZvG/pLSpSZr6BTZioOpsjgI4CJq9n0wGhpyClKm24hGzYEPH8AkBs4wVmgt4sOHvyYc mYqTUQDFFlehrx6Wh0E= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block cjjanW9F+fseEMt2SDd6R3KYZVrfLHKeq8ULFHbP0E7BiwY4Vkec6zVJkc5FOAAhZdR5Ywc2FOnS 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-- ------------------------------------------------------------- -- -- Entity Declaration for inst_1_e -- -- Generated -- by: wig -- on: Wed Nov 30 06:48:17 2005 -- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../generic.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_1_e-e.vhd,v 1.3 2005/11/30 14:04:05 wig Exp $ -- $Date: 2005/11/30 14:04:05 $ -- $Log: inst_1_e-e.vhd,v $ -- Revision 1.3 2005/11/30 14:04:05 wig -- Updated testcase references -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.42 , wilfried.gaensheimer@micronas.com -- (C) 2003,2005 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/enty -- -- -- Start of Generated Entity inst_1_e -- entity inst_1_e is -- Generics: generic( -- Generated Generics for Entity inst_1_e FOO : integer -- Generic generator, value __W_NODEFAULT -- End of Generated Generics for Entity inst_1_e ); -- Generated Port Declaration: -- No Generated Port for Entity inst_1_e end inst_1_e; -- -- End of Generated Entity inst_1_e -- -- --!End of Entity/ies -- --------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity MAGIC_global is PORT ( ADDRESS_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0); DATA_TO_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0); W_EN : IN STD_LOGIC; CLK : IN STD_LOGIC; RESET_n : IN STD_LOGIC; DATA_OUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); DATA_OUT_B : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); DATA_OUT_C : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); DATA_OUT_0 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); DATA_OUT_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); C0_STALL : OUT STD_LOGIC; C1_STALL : OUT STD_LOGIC; CORE_IDENT : OUT STD_LOGIC; IO_ENABLE : IN STD_LOGIC ); end; architecture magic of MAGIC_global is component SETUP_global PORT( CLK : IN STD_LOGIC; ADDRESS_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0); W_EN : IN STD_LOGIC; RESET_n : IN STD_LOGIC; STALL : OUT STD_LOGIC; HAZARD : IN STD_LOGIC; ram_0_port_a : OUT STD_LOGIC_VECTOR (11 downto 0); ram_0_port_b : OUT STD_LOGIC_VECTOR (11 downto 0); ram_0_wren_a : OUT STD_LOGIC; ram_0_wren_b : OUT STD_LOGIC; ram_1_port_a : OUT STD_LOGIC_VECTOR (11 downto 0); ram_1_port_b : OUT STD_LOGIC_VECTOR (11 downto 0); ram_1_wren_a : OUT STD_LOGIC; ram_1_wren_b : OUT STD_LOGIC; ram_2_port_a : OUT STD_LOGIC_VECTOR (11 downto 0); ram_2_port_b : OUT STD_LOGIC_VECTOR (11 downto 0); ram_2_wren_a : OUT STD_LOGIC; ram_2_wren_b : OUT STD_LOGIC; ram_3_port_a : OUT STD_LOGIC_VECTOR (11 downto 0); ram_3_port_b : OUT STD_LOGIC_VECTOR (11 downto 0); ram_3_wren_a : OUT STD_LOGIC; ram_3_wren_b : OUT STD_LOGIC; ram_4_port_a : OUT STD_LOGIC_VECTOR (11 downto 0); ram_4_port_b : OUT STD_LOGIC_VECTOR (11 downto 0); ram_4_wren_a : OUT STD_LOGIC; ram_4_wren_b : OUT STD_LOGIC; ram_5_port_a : OUT STD_LOGIC_VECTOR (11 downto 0); ram_5_port_b : OUT STD_LOGIC_VECTOR (11 downto 0); ram_5_wren_a : OUT STD_LOGIC; ram_5_wren_b : OUT STD_LOGIC; ram_6_port_a : OUT STD_LOGIC_VECTOR (11 downto 0); ram_6_port_b : OUT STD_LOGIC_VECTOR (11 downto 0); ram_6_wren_a : OUT STD_LOGIC; ram_6_wren_b : OUT STD_LOGIC; ram_7_port_a : OUT STD_LOGIC_VECTOR (11 downto 0); ram_7_port_b : OUT STD_LOGIC_VECTOR (11 downto 0); ram_7_wren_a : OUT STD_LOGIC; ram_7_wren_b : OUT STD_LOGIC; ram_0_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); ram_1_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); ram_2_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); ram_3_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); ram_4_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); ram_5_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); ram_6_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); ram_7_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) ); end component; component ROUTE_global PORT( hazard : IN STD_LOGIC; hazard_advanced : IN STD_LOGIC; CLK : IN STD_LOGIC; RESET_n : IN STD_LOGIC; ram_0_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_0_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_1_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_1_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_2_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_2_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_3_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_3_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_4_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_4_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_5_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_5_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_6_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_6_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_7_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_7_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_0_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0); ram_1_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0); ram_2_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0); ram_3_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0); ram_4_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0); ram_5_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0); ram_6_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0); ram_7_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0); OUTPUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); OUTPUT_B : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); OUTPUT_C : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); OUTPUT_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); OUTPUT_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); end component; component RAM_0_global PORT ( aclr : IN STD_LOGIC; address_a : IN STD_LOGIC_VECTOR (11 downto 0); address_b : IN STD_LOGIC_VECTOR (11 downto 0); clock : IN STD_LOGIC; data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); wren_a : IN STD_LOGIC; wren_b : IN STD_LOGIC; q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); end component; component RAM_1_global PORT ( aclr : IN STD_LOGIC; address_a : IN STD_LOGIC_VECTOR (11 downto 0); address_b : IN STD_LOGIC_VECTOR (11 downto 0); clock : IN STD_LOGIC; data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); wren_a : IN STD_LOGIC; wren_b : IN STD_LOGIC; q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); end component; component RAM_2_global PORT ( aclr : IN STD_LOGIC; address_a : IN STD_LOGIC_VECTOR (11 downto 0); address_b : IN STD_LOGIC_VECTOR (11 downto 0); clock : IN STD_LOGIC; data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); wren_a : IN STD_LOGIC; wren_b : IN STD_LOGIC; q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); end component; component RAM_3_global PORT ( aclr : IN STD_LOGIC; address_a : IN STD_LOGIC_VECTOR (11 downto 0); address_b : IN STD_LOGIC_VECTOR (11 downto 0); clock : IN STD_LOGIC; data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); wren_a : IN STD_LOGIC; wren_b : IN STD_LOGIC; q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); end component; component RAM_4_global PORT ( aclr : IN STD_LOGIC; address_a : IN STD_LOGIC_VECTOR (11 downto 0); address_b : IN STD_LOGIC_VECTOR (11 downto 0); clock : IN STD_LOGIC; data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); wren_a : IN STD_LOGIC; wren_b : IN STD_LOGIC; q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); end component; component RAM_5_global PORT ( aclr : IN STD_LOGIC; address_a : IN STD_LOGIC_VECTOR (11 downto 0); address_b : IN STD_LOGIC_VECTOR (11 downto 0); clock : IN STD_LOGIC; data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); wren_a : IN STD_LOGIC; wren_b : IN STD_LOGIC; q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); end component; component RAM_6_global PORT ( aclr : IN STD_LOGIC; address_a : IN STD_LOGIC_VECTOR (11 downto 0); address_b : IN STD_LOGIC_VECTOR (11 downto 0); clock : IN STD_LOGIC; data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); wren_a : IN STD_LOGIC; wren_b : IN STD_LOGIC; q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); end component; component RAM_7_global PORT ( aclr : IN STD_LOGIC; address_a : IN STD_LOGIC_VECTOR (11 downto 0); address_b : IN STD_LOGIC_VECTOR (11 downto 0); clock : IN STD_LOGIC; data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); wren_a : IN STD_LOGIC; wren_b : IN STD_LOGIC; q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); end component; signal address_a_sig : std_logic_vector (31 downto 0); signal address_b_sig : std_logic_vector (31 downto 0); signal address_c_sig : std_logic_vector (31 downto 0); signal address_0_sig : std_logic_vector (31 downto 0); signal address_1_sig : std_logic_vector (31 downto 0); signal address_w_sig : std_logic_vector (31 downto 0); signal data_to_w_sig : std_logic_vector (31 downto 0); signal w_en_sig : std_logic; signal RESET : std_logic; signal stall_flag : std_logic; signal hazard : std_logic; signal hazard_w_io : std_logic; signal io_buffer_en : std_logic; signal ram_0_port_a : std_logic_vector (11 downto 0); signal ram_0_port_b : std_logic_vector (11 downto 0); signal ram_0_wren_a : std_logic; signal ram_0_wren_b : std_logic; signal ram_1_port_a : std_logic_vector (11 downto 0); signal ram_1_port_b : std_logic_vector (11 downto 0); signal ram_1_wren_a : std_logic; signal ram_1_wren_b : std_logic; signal ram_2_port_a : std_logic_vector (11 downto 0); signal ram_2_port_b : std_logic_vector (11 downto 0); signal ram_2_wren_a : std_logic; signal ram_2_wren_b : std_logic; signal ram_3_port_a : std_logic_vector (11 downto 0); signal ram_3_port_b : std_logic_vector (11 downto 0); signal ram_3_wren_a : std_logic; signal ram_3_wren_b : std_logic; signal ram_4_port_a : std_logic_vector (11 downto 0); signal ram_4_port_b : std_logic_vector (11 downto 0); signal ram_4_wren_a : std_logic; signal ram_4_wren_b : std_logic; signal ram_5_port_a : std_logic_vector (11 downto 0); signal ram_5_port_b : std_logic_vector (11 downto 0); signal ram_5_wren_a : std_logic; signal ram_5_wren_b : std_logic; signal ram_6_port_a : std_logic_vector (11 downto 0); signal ram_6_port_b : std_logic_vector (11 downto 0); signal ram_6_wren_a : std_logic; signal ram_6_wren_b : std_logic; signal ram_7_port_a : std_logic_vector (11 downto 0); signal ram_7_port_b : std_logic_vector (11 downto 0); signal ram_7_wren_a : std_logic; signal ram_7_wren_b : std_logic; signal ram_0_sel_vector : std_logic_vector(9 downto 0); signal ram_1_sel_vector : std_logic_vector(9 downto 0); signal ram_2_sel_vector : std_logic_vector(9 downto 0); signal ram_3_sel_vector : std_logic_vector(9 downto 0); signal ram_4_sel_vector : std_logic_vector(9 downto 0); signal ram_5_sel_vector : std_logic_vector(9 downto 0); signal ram_6_sel_vector : std_logic_vector(9 downto 0); signal ram_7_sel_vector : std_logic_vector(9 downto 0); signal ram_0_sel : std_logic_vector(9 downto 0); signal ram_1_sel : std_logic_vector(9 downto 0); signal ram_2_sel : std_logic_vector(9 downto 0); signal ram_3_sel : std_logic_vector(9 downto 0); signal ram_4_sel : std_logic_vector(9 downto 0); signal ram_5_sel : std_logic_vector(9 downto 0); signal ram_6_sel : std_logic_vector(9 downto 0); signal ram_7_sel : std_logic_vector(9 downto 0); signal ram_0_out_a : std_logic_vector (31 downto 0); signal ram_0_out_b : std_logic_vector (31 downto 0); signal ram_1_out_a : std_logic_vector (31 downto 0); signal ram_1_out_b : std_logic_vector (31 downto 0); signal ram_2_out_a : std_logic_vector (31 downto 0); signal ram_2_out_b : std_logic_vector (31 downto 0); signal ram_3_out_a : std_logic_vector (31 downto 0); signal ram_3_out_b : std_logic_vector (31 downto 0); signal ram_4_out_a : std_logic_vector (31 downto 0); signal ram_4_out_b : std_logic_vector (31 downto 0); signal ram_5_out_a : std_logic_vector (31 downto 0); signal ram_5_out_b : std_logic_vector (31 downto 0); signal ram_6_out_a : std_logic_vector (31 downto 0); signal ram_6_out_b : std_logic_vector (31 downto 0); signal ram_7_out_a : std_logic_vector (31 downto 0); signal ram_7_out_b : std_logic_vector (31 downto 0); signal output_a : std_logic_vector (31 downto 0); signal output_b : std_logic_vector (31 downto 0); signal output_c : std_logic_vector (31 downto 0); signal output_0 : std_logic_vector (31 downto 0); signal output_1 : std_logic_vector (31 downto 0); signal stall : std_logic; signal hold : std_logic; signal core_id : std_logic; signal c0_stall_sig : std_logic; signal c1_stall_sig : std_logic; signal hazard_advanced : std_logic; -- begin input_control : SETUP_global PORT MAP ( CLK => CLK, ADDRESS_A => address_a_sig, ADDRESS_B => address_b_sig, ADDRESS_C => address_c_sig, ADDRESS_0 => address_0_sig, ADDRESS_1 => address_1_sig, ADDRESS_W => address_w_sig, W_EN => w_en_sig, RESET_n => RESET_n, STALL => stall_flag, HAZARD => hazard, ram_0_port_a => ram_0_port_a, ram_0_port_b => ram_0_port_b, ram_0_wren_a => ram_0_wren_a, ram_0_wren_b => ram_0_wren_b, ram_1_port_a => ram_1_port_a, ram_1_port_b => ram_1_port_b, ram_1_wren_a => ram_1_wren_a, ram_1_wren_b => ram_1_wren_b, ram_2_port_a => ram_2_port_a, ram_2_port_b => ram_2_port_b, ram_2_wren_a => ram_2_wren_a, ram_2_wren_b => ram_2_wren_b, ram_3_port_a => ram_3_port_a, ram_3_port_b => ram_3_port_b, ram_3_wren_a => ram_3_wren_a, ram_3_wren_b => ram_3_wren_b, ram_4_port_a => ram_4_port_a, ram_4_port_b => ram_4_port_b, ram_4_wren_a => ram_4_wren_a, ram_4_wren_b => ram_4_wren_b, ram_5_port_a => ram_5_port_a, ram_5_port_b => ram_5_port_b, ram_5_wren_a => ram_5_wren_a, ram_5_wren_b => ram_5_wren_b, ram_6_port_a => ram_6_port_a, ram_6_port_b => ram_6_port_b, ram_6_wren_a => ram_6_wren_a, ram_6_wren_b => ram_6_wren_b, ram_7_port_a => ram_7_port_a, ram_7_port_b => ram_7_port_b, ram_7_wren_a => ram_7_wren_a, ram_7_wren_b => ram_7_wren_b, ram_0_sel_vector => ram_0_sel_vector, ram_1_sel_vector => ram_1_sel_vector, ram_2_sel_vector => ram_2_sel_vector, ram_3_sel_vector => ram_3_sel_vector, ram_4_sel_vector => ram_4_sel_vector, ram_5_sel_vector => ram_5_sel_vector, ram_6_sel_vector => ram_6_sel_vector, ram_7_sel_vector => ram_7_sel_vector ); RAM_0_inst : RAM_0_global PORT MAP ( aclr => RESET, address_a => ram_0_port_a, address_b => ram_0_port_b, clock => CLK, data_a => data_to_w_sig, data_b => data_to_w_sig, wren_a => ram_0_wren_a, wren_b => ram_0_wren_b, q_a => ram_0_out_a, q_b => ram_0_out_b ); RAM_1_inst : RAM_1_global PORT MAP ( aclr => RESET, address_a => ram_1_port_a, address_b => ram_1_port_b, clock => CLK, data_a => data_to_w_sig, data_b => data_to_w_sig, wren_a => ram_1_wren_a, wren_b => ram_1_wren_b, q_a => ram_1_out_a, q_b => ram_1_out_b ); RAM_2_inst : RAM_2_global PORT MAP ( aclr => RESET, address_a => ram_2_port_a, address_b => ram_2_port_b, clock => CLK, data_a => data_to_w_sig, data_b => data_to_w_sig, wren_a => ram_2_wren_a, wren_b => ram_2_wren_b, q_a => ram_2_out_a, q_b => ram_2_out_b ); RAM_3_inst : RAM_3_global PORT MAP ( aclr => RESET, address_a => ram_3_port_a, address_b => ram_3_port_b, clock => CLK, data_a => data_to_w_sig, data_b => data_to_w_sig, wren_a => ram_3_wren_a, wren_b => ram_3_wren_b, q_a => ram_3_out_a, q_b => ram_3_out_b ); RAM_4_inst : RAM_4_global PORT MAP ( aclr => RESET, address_a => ram_4_port_a, address_b => ram_4_port_b, clock => CLK, data_a => data_to_w_sig, data_b => data_to_w_sig, wren_a => ram_4_wren_a, wren_b => ram_4_wren_b, q_a => ram_4_out_a, q_b => ram_4_out_b ); RAM_5_inst : RAM_5_global PORT MAP ( aclr => RESET, address_a => ram_5_port_a, address_b => ram_5_port_b, clock => CLK, data_a => data_to_w_sig, data_b => data_to_w_sig, wren_a => ram_5_wren_a, wren_b => ram_5_wren_b, q_a => ram_5_out_a, q_b => ram_5_out_b ); RAM_6_inst : RAM_6_global PORT MAP ( aclr => RESET, address_a => ram_6_port_a, address_b => ram_6_port_b, clock => CLK, data_a => data_to_w_sig, data_b => data_to_w_sig, wren_a => ram_6_wren_a, wren_b => ram_6_wren_b, q_a => ram_6_out_a, q_b => ram_6_out_b ); RAM_7_inst : RAM_7_global PORT MAP ( aclr => RESET, address_a => ram_7_port_a, address_b => ram_7_port_b, clock => CLK, data_a => data_to_w_sig, data_b => data_to_w_sig, wren_a => ram_7_wren_a, wren_b => ram_7_wren_b, q_a => ram_7_out_a, q_b => ram_7_out_b ); output_control : ROUTE_global PORT MAP ( CLK => CLK, RESET_n => RESET_n, hazard => hazard_w_io, hazard_advanced => hazard_advanced, ram_0_out_a => ram_0_out_a, ram_0_out_b => ram_0_out_b, ram_1_out_a => ram_1_out_a, ram_1_out_b => ram_1_out_b, ram_2_out_a => ram_2_out_a, ram_2_out_b => ram_2_out_b, ram_3_out_a => ram_3_out_a, ram_3_out_b => ram_3_out_b, ram_4_out_a => ram_4_out_a, ram_4_out_b => ram_4_out_b, ram_5_out_a => ram_5_out_a, ram_5_out_b => ram_5_out_b, ram_6_out_a => ram_6_out_a, ram_6_out_b => ram_6_out_b, ram_7_out_a => ram_7_out_a, ram_7_out_b => ram_7_out_b, ram_0_sel_vector => ram_0_sel, ram_1_sel_vector => ram_1_sel, ram_2_sel_vector => ram_2_sel, ram_3_sel_vector => ram_3_sel, ram_4_sel_vector => ram_4_sel, ram_5_sel_vector => ram_5_sel, ram_6_sel_vector => ram_6_sel, ram_7_sel_vector => ram_7_sel, OUTPUT_A => output_a, OUTPUT_B => output_b, OUTPUT_C => output_c, OUTPUT_0 => output_0, OUTPUT_1 => output_1 ); -- latch_outputs : process (CLK, RESET_n) begin -- if (RESET_n = '0') then -- DATA_OUT_A <= "00000000000000000000000000000000"; -- DATA_OUT_B <= "00000000000000000000000000000000"; -- DATA_OUT_C <= "00000000000000000000000000000000"; -- DATA_OUT_0 <= "00000000000000000000000000000000"; -- DATA_OUT_1 <= "00000000000000000000000000000000"; -- elsif (rising_edge(CLK)) then -- DATA_OUT_A <= output_a; -- DATA_OUT_B <= output_b; -- DATA_OUT_C <= output_c; -- DATA_OUT_0 <= output_0; -- DATA_OUT_1 <= output_1; -- end if; -- end process; --******above latching used for testing******** DATA_OUT_A <= output_a; DATA_OUT_B <= output_b; DATA_OUT_C <= output_c; DATA_OUT_0 <= output_0; DATA_OUT_1 <= output_1; latch_vectors : process (CLK, RESET_n) begin if (RESET_n = '0') then ram_0_sel <= "0000000000"; ram_1_sel <= "0000000000"; ram_2_sel <= "0000000000"; ram_3_sel <= "0000000000"; ram_4_sel <= "0000000000"; ram_5_sel <= "0000000000"; ram_6_sel <= "0000000000"; ram_7_sel <= "0000000000"; hazard <= '0'; elsif (rising_edge(CLK)) then ram_0_sel <= ram_0_sel_vector; ram_1_sel <= ram_1_sel_vector; ram_2_sel <= ram_2_sel_vector; ram_3_sel <= ram_3_sel_vector; ram_4_sel <= ram_4_sel_vector; ram_5_sel <= ram_5_sel_vector; ram_6_sel <= ram_6_sel_vector; ram_7_sel <= ram_7_sel_vector; hazard <= stall_flag; end if; end process; -- latch_inputs : process (CLK, RESET_n) begin -- if (RESET_n = '0') then -- address_a_sig <= "00000000000000000000000000000000"; -- address_b_sig <= "00000000000000000000000000000000"; -- address_c_sig <= "00000000000000000000000000000000"; -- address_0_sig <= "00000000000000000000000000000000"; -- address_1_sig <= "00000000000000000000000000000000"; -- address_w_sig <= "00000000000000000000000000000000"; -- data_to_w_sig <= "00000000000000000000000000000000"; -- w_en_sig <= '0'; -- elsif (rising_edge(CLK)) then -- address_a_sig <= ADDRESS_A; -- address_b_sig <= ADDRESS_B; -- address_c_sig <= ADDRESS_C; -- address_0_sig <= ADDRESS_0; -- address_1_sig <= ADDRESS_1; -- address_w_sig <= ADDRESS_W; -- data_to_w_sig <= DATA_TO_W; -- w_en_sig <= W_EN; -- end if; -- end process; --****above latching used for testing************* address_a_sig <= ADDRESS_A; address_b_sig <= ADDRESS_B; address_c_sig <= ADDRESS_C; address_0_sig <= ADDRESS_0; address_1_sig <= ADDRESS_1; address_w_sig <= ADDRESS_W; data_to_w_sig <= DATA_TO_W; w_en_sig <= W_EN; RESET <= not RESET_n; stall <= stall_flag or hazard_w_io; --maybe without io hold <= c0_stall_sig and c1_stall_sig; C0_STALL <= (not core_id) or c0_stall_sig; --flipped not statement C1_STALL <= (core_id) or c1_stall_sig; --between these two lines CORE_IDENT <= core_id; hazard_w_io <= hazard or io_buffer_en; hazard_advanced <= hazard_w_io or stall_flag; id_gen : process (CLK, RESET_n, hold) begin if (RESET_n = '0') then core_id <= '0'; elsif (rising_edge(CLK)) then if (hold = '0' and IO_ENABLE = '0') then core_id <= not core_id; end if; end if; end process; override_io : process (CLK, RESET_n) begin if (RESET_n = '0') then io_buffer_en <= '0'; elsif (rising_edge(CLK)) then io_buffer_en <= IO_ENABLE; end if; end process; stalling : process (core_id, stall_flag, stall) begin if (core_id = '0' and stall = '1') then c0_stall_sig <= stall; c1_stall_sig <= stall_flag; elsif (core_id = '1' and stall = '1') then c0_stall_sig <= stall_flag; c1_stall_sig <= stall; else c0_stall_sig <= '0'; c1_stall_sig <= '0'; end if; end process; end;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity MAGIC_global is PORT ( ADDRESS_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0); DATA_TO_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0); W_EN : IN STD_LOGIC; CLK : IN STD_LOGIC; RESET_n : IN STD_LOGIC; DATA_OUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); DATA_OUT_B : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); DATA_OUT_C : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); DATA_OUT_0 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); DATA_OUT_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); C0_STALL : OUT STD_LOGIC; C1_STALL : OUT STD_LOGIC; CORE_IDENT : OUT STD_LOGIC; IO_ENABLE : IN STD_LOGIC ); end; architecture magic of MAGIC_global is component SETUP_global PORT( CLK : IN STD_LOGIC; ADDRESS_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ADDRESS_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0); W_EN : IN STD_LOGIC; RESET_n : IN STD_LOGIC; STALL : OUT STD_LOGIC; HAZARD : IN STD_LOGIC; ram_0_port_a : OUT STD_LOGIC_VECTOR (11 downto 0); ram_0_port_b : OUT STD_LOGIC_VECTOR (11 downto 0); ram_0_wren_a : OUT STD_LOGIC; ram_0_wren_b : OUT STD_LOGIC; ram_1_port_a : OUT STD_LOGIC_VECTOR (11 downto 0); ram_1_port_b : OUT STD_LOGIC_VECTOR (11 downto 0); ram_1_wren_a : OUT STD_LOGIC; ram_1_wren_b : OUT STD_LOGIC; ram_2_port_a : OUT STD_LOGIC_VECTOR (11 downto 0); ram_2_port_b : OUT STD_LOGIC_VECTOR (11 downto 0); ram_2_wren_a : OUT STD_LOGIC; ram_2_wren_b : OUT STD_LOGIC; ram_3_port_a : OUT STD_LOGIC_VECTOR (11 downto 0); ram_3_port_b : OUT STD_LOGIC_VECTOR (11 downto 0); ram_3_wren_a : OUT STD_LOGIC; ram_3_wren_b : OUT STD_LOGIC; ram_4_port_a : OUT STD_LOGIC_VECTOR (11 downto 0); ram_4_port_b : OUT STD_LOGIC_VECTOR (11 downto 0); ram_4_wren_a : OUT STD_LOGIC; ram_4_wren_b : OUT STD_LOGIC; ram_5_port_a : OUT STD_LOGIC_VECTOR (11 downto 0); ram_5_port_b : OUT STD_LOGIC_VECTOR (11 downto 0); ram_5_wren_a : OUT STD_LOGIC; ram_5_wren_b : OUT STD_LOGIC; ram_6_port_a : OUT STD_LOGIC_VECTOR (11 downto 0); ram_6_port_b : OUT STD_LOGIC_VECTOR (11 downto 0); ram_6_wren_a : OUT STD_LOGIC; ram_6_wren_b : OUT STD_LOGIC; ram_7_port_a : OUT STD_LOGIC_VECTOR (11 downto 0); ram_7_port_b : OUT STD_LOGIC_VECTOR (11 downto 0); ram_7_wren_a : OUT STD_LOGIC; ram_7_wren_b : OUT STD_LOGIC; ram_0_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); ram_1_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); ram_2_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); ram_3_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); ram_4_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); ram_5_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); ram_6_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); ram_7_sel_vector : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) ); end component; component ROUTE_global PORT( hazard : IN STD_LOGIC; hazard_advanced : IN STD_LOGIC; CLK : IN STD_LOGIC; RESET_n : IN STD_LOGIC; ram_0_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_0_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_1_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_1_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_2_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_2_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_3_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_3_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_4_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_4_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_5_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_5_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_6_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_6_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_7_out_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_7_out_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); ram_0_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0); ram_1_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0); ram_2_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0); ram_3_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0); ram_4_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0); ram_5_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0); ram_6_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0); ram_7_sel_vector : IN STD_LOGIC_VECTOR (9 downto 0); OUTPUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); OUTPUT_B : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); OUTPUT_C : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); OUTPUT_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); OUTPUT_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); end component; component RAM_0_global PORT ( aclr : IN STD_LOGIC; address_a : IN STD_LOGIC_VECTOR (11 downto 0); address_b : IN STD_LOGIC_VECTOR (11 downto 0); clock : IN STD_LOGIC; data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); wren_a : IN STD_LOGIC; wren_b : IN STD_LOGIC; q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); end component; component RAM_1_global PORT ( aclr : IN STD_LOGIC; address_a : IN STD_LOGIC_VECTOR (11 downto 0); address_b : IN STD_LOGIC_VECTOR (11 downto 0); clock : IN STD_LOGIC; data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); wren_a : IN STD_LOGIC; wren_b : IN STD_LOGIC; q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); end component; component RAM_2_global PORT ( aclr : IN STD_LOGIC; address_a : IN STD_LOGIC_VECTOR (11 downto 0); address_b : IN STD_LOGIC_VECTOR (11 downto 0); clock : IN STD_LOGIC; data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); wren_a : IN STD_LOGIC; wren_b : IN STD_LOGIC; q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); end component; component RAM_3_global PORT ( aclr : IN STD_LOGIC; address_a : IN STD_LOGIC_VECTOR (11 downto 0); address_b : IN STD_LOGIC_VECTOR (11 downto 0); clock : IN STD_LOGIC; data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); wren_a : IN STD_LOGIC; wren_b : IN STD_LOGIC; q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); end component; component RAM_4_global PORT ( aclr : IN STD_LOGIC; address_a : IN STD_LOGIC_VECTOR (11 downto 0); address_b : IN STD_LOGIC_VECTOR (11 downto 0); clock : IN STD_LOGIC; data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); wren_a : IN STD_LOGIC; wren_b : IN STD_LOGIC; q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); end component; component RAM_5_global PORT ( aclr : IN STD_LOGIC; address_a : IN STD_LOGIC_VECTOR (11 downto 0); address_b : IN STD_LOGIC_VECTOR (11 downto 0); clock : IN STD_LOGIC; data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); wren_a : IN STD_LOGIC; wren_b : IN STD_LOGIC; q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); end component; component RAM_6_global PORT ( aclr : IN STD_LOGIC; address_a : IN STD_LOGIC_VECTOR (11 downto 0); address_b : IN STD_LOGIC_VECTOR (11 downto 0); clock : IN STD_LOGIC; data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); wren_a : IN STD_LOGIC; wren_b : IN STD_LOGIC; q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); end component; component RAM_7_global PORT ( aclr : IN STD_LOGIC; address_a : IN STD_LOGIC_VECTOR (11 downto 0); address_b : IN STD_LOGIC_VECTOR (11 downto 0); clock : IN STD_LOGIC; data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); wren_a : IN STD_LOGIC; wren_b : IN STD_LOGIC; q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); end component; signal address_a_sig : std_logic_vector (31 downto 0); signal address_b_sig : std_logic_vector (31 downto 0); signal address_c_sig : std_logic_vector (31 downto 0); signal address_0_sig : std_logic_vector (31 downto 0); signal address_1_sig : std_logic_vector (31 downto 0); signal address_w_sig : std_logic_vector (31 downto 0); signal data_to_w_sig : std_logic_vector (31 downto 0); signal w_en_sig : std_logic; signal RESET : std_logic; signal stall_flag : std_logic; signal hazard : std_logic; signal hazard_w_io : std_logic; signal io_buffer_en : std_logic; signal ram_0_port_a : std_logic_vector (11 downto 0); signal ram_0_port_b : std_logic_vector (11 downto 0); signal ram_0_wren_a : std_logic; signal ram_0_wren_b : std_logic; signal ram_1_port_a : std_logic_vector (11 downto 0); signal ram_1_port_b : std_logic_vector (11 downto 0); signal ram_1_wren_a : std_logic; signal ram_1_wren_b : std_logic; signal ram_2_port_a : std_logic_vector (11 downto 0); signal ram_2_port_b : std_logic_vector (11 downto 0); signal ram_2_wren_a : std_logic; signal ram_2_wren_b : std_logic; signal ram_3_port_a : std_logic_vector (11 downto 0); signal ram_3_port_b : std_logic_vector (11 downto 0); signal ram_3_wren_a : std_logic; signal ram_3_wren_b : std_logic; signal ram_4_port_a : std_logic_vector (11 downto 0); signal ram_4_port_b : std_logic_vector (11 downto 0); signal ram_4_wren_a : std_logic; signal ram_4_wren_b : std_logic; signal ram_5_port_a : std_logic_vector (11 downto 0); signal ram_5_port_b : std_logic_vector (11 downto 0); signal ram_5_wren_a : std_logic; signal ram_5_wren_b : std_logic; signal ram_6_port_a : std_logic_vector (11 downto 0); signal ram_6_port_b : std_logic_vector (11 downto 0); signal ram_6_wren_a : std_logic; signal ram_6_wren_b : std_logic; signal ram_7_port_a : std_logic_vector (11 downto 0); signal ram_7_port_b : std_logic_vector (11 downto 0); signal ram_7_wren_a : std_logic; signal ram_7_wren_b : std_logic; signal ram_0_sel_vector : std_logic_vector(9 downto 0); signal ram_1_sel_vector : std_logic_vector(9 downto 0); signal ram_2_sel_vector : std_logic_vector(9 downto 0); signal ram_3_sel_vector : std_logic_vector(9 downto 0); signal ram_4_sel_vector : std_logic_vector(9 downto 0); signal ram_5_sel_vector : std_logic_vector(9 downto 0); signal ram_6_sel_vector : std_logic_vector(9 downto 0); signal ram_7_sel_vector : std_logic_vector(9 downto 0); signal ram_0_sel : std_logic_vector(9 downto 0); signal ram_1_sel : std_logic_vector(9 downto 0); signal ram_2_sel : std_logic_vector(9 downto 0); signal ram_3_sel : std_logic_vector(9 downto 0); signal ram_4_sel : std_logic_vector(9 downto 0); signal ram_5_sel : std_logic_vector(9 downto 0); signal ram_6_sel : std_logic_vector(9 downto 0); signal ram_7_sel : std_logic_vector(9 downto 0); signal ram_0_out_a : std_logic_vector (31 downto 0); signal ram_0_out_b : std_logic_vector (31 downto 0); signal ram_1_out_a : std_logic_vector (31 downto 0); signal ram_1_out_b : std_logic_vector (31 downto 0); signal ram_2_out_a : std_logic_vector (31 downto 0); signal ram_2_out_b : std_logic_vector (31 downto 0); signal ram_3_out_a : std_logic_vector (31 downto 0); signal ram_3_out_b : std_logic_vector (31 downto 0); signal ram_4_out_a : std_logic_vector (31 downto 0); signal ram_4_out_b : std_logic_vector (31 downto 0); signal ram_5_out_a : std_logic_vector (31 downto 0); signal ram_5_out_b : std_logic_vector (31 downto 0); signal ram_6_out_a : std_logic_vector (31 downto 0); signal ram_6_out_b : std_logic_vector (31 downto 0); signal ram_7_out_a : std_logic_vector (31 downto 0); signal ram_7_out_b : std_logic_vector (31 downto 0); signal output_a : std_logic_vector (31 downto 0); signal output_b : std_logic_vector (31 downto 0); signal output_c : std_logic_vector (31 downto 0); signal output_0 : std_logic_vector (31 downto 0); signal output_1 : std_logic_vector (31 downto 0); signal stall : std_logic; signal hold : std_logic; signal core_id : std_logic; signal c0_stall_sig : std_logic; signal c1_stall_sig : std_logic; signal hazard_advanced : std_logic; -- begin input_control : SETUP_global PORT MAP ( CLK => CLK, ADDRESS_A => address_a_sig, ADDRESS_B => address_b_sig, ADDRESS_C => address_c_sig, ADDRESS_0 => address_0_sig, ADDRESS_1 => address_1_sig, ADDRESS_W => address_w_sig, W_EN => w_en_sig, RESET_n => RESET_n, STALL => stall_flag, HAZARD => hazard, ram_0_port_a => ram_0_port_a, ram_0_port_b => ram_0_port_b, ram_0_wren_a => ram_0_wren_a, ram_0_wren_b => ram_0_wren_b, ram_1_port_a => ram_1_port_a, ram_1_port_b => ram_1_port_b, ram_1_wren_a => ram_1_wren_a, ram_1_wren_b => ram_1_wren_b, ram_2_port_a => ram_2_port_a, ram_2_port_b => ram_2_port_b, ram_2_wren_a => ram_2_wren_a, ram_2_wren_b => ram_2_wren_b, ram_3_port_a => ram_3_port_a, ram_3_port_b => ram_3_port_b, ram_3_wren_a => ram_3_wren_a, ram_3_wren_b => ram_3_wren_b, ram_4_port_a => ram_4_port_a, ram_4_port_b => ram_4_port_b, ram_4_wren_a => ram_4_wren_a, ram_4_wren_b => ram_4_wren_b, ram_5_port_a => ram_5_port_a, ram_5_port_b => ram_5_port_b, ram_5_wren_a => ram_5_wren_a, ram_5_wren_b => ram_5_wren_b, ram_6_port_a => ram_6_port_a, ram_6_port_b => ram_6_port_b, ram_6_wren_a => ram_6_wren_a, ram_6_wren_b => ram_6_wren_b, ram_7_port_a => ram_7_port_a, ram_7_port_b => ram_7_port_b, ram_7_wren_a => ram_7_wren_a, ram_7_wren_b => ram_7_wren_b, ram_0_sel_vector => ram_0_sel_vector, ram_1_sel_vector => ram_1_sel_vector, ram_2_sel_vector => ram_2_sel_vector, ram_3_sel_vector => ram_3_sel_vector, ram_4_sel_vector => ram_4_sel_vector, ram_5_sel_vector => ram_5_sel_vector, ram_6_sel_vector => ram_6_sel_vector, ram_7_sel_vector => ram_7_sel_vector ); RAM_0_inst : RAM_0_global PORT MAP ( aclr => RESET, address_a => ram_0_port_a, address_b => ram_0_port_b, clock => CLK, data_a => data_to_w_sig, data_b => data_to_w_sig, wren_a => ram_0_wren_a, wren_b => ram_0_wren_b, q_a => ram_0_out_a, q_b => ram_0_out_b ); RAM_1_inst : RAM_1_global PORT MAP ( aclr => RESET, address_a => ram_1_port_a, address_b => ram_1_port_b, clock => CLK, data_a => data_to_w_sig, data_b => data_to_w_sig, wren_a => ram_1_wren_a, wren_b => ram_1_wren_b, q_a => ram_1_out_a, q_b => ram_1_out_b ); RAM_2_inst : RAM_2_global PORT MAP ( aclr => RESET, address_a => ram_2_port_a, address_b => ram_2_port_b, clock => CLK, data_a => data_to_w_sig, data_b => data_to_w_sig, wren_a => ram_2_wren_a, wren_b => ram_2_wren_b, q_a => ram_2_out_a, q_b => ram_2_out_b ); RAM_3_inst : RAM_3_global PORT MAP ( aclr => RESET, address_a => ram_3_port_a, address_b => ram_3_port_b, clock => CLK, data_a => data_to_w_sig, data_b => data_to_w_sig, wren_a => ram_3_wren_a, wren_b => ram_3_wren_b, q_a => ram_3_out_a, q_b => ram_3_out_b ); RAM_4_inst : RAM_4_global PORT MAP ( aclr => RESET, address_a => ram_4_port_a, address_b => ram_4_port_b, clock => CLK, data_a => data_to_w_sig, data_b => data_to_w_sig, wren_a => ram_4_wren_a, wren_b => ram_4_wren_b, q_a => ram_4_out_a, q_b => ram_4_out_b ); RAM_5_inst : RAM_5_global PORT MAP ( aclr => RESET, address_a => ram_5_port_a, address_b => ram_5_port_b, clock => CLK, data_a => data_to_w_sig, data_b => data_to_w_sig, wren_a => ram_5_wren_a, wren_b => ram_5_wren_b, q_a => ram_5_out_a, q_b => ram_5_out_b ); RAM_6_inst : RAM_6_global PORT MAP ( aclr => RESET, address_a => ram_6_port_a, address_b => ram_6_port_b, clock => CLK, data_a => data_to_w_sig, data_b => data_to_w_sig, wren_a => ram_6_wren_a, wren_b => ram_6_wren_b, q_a => ram_6_out_a, q_b => ram_6_out_b ); RAM_7_inst : RAM_7_global PORT MAP ( aclr => RESET, address_a => ram_7_port_a, address_b => ram_7_port_b, clock => CLK, data_a => data_to_w_sig, data_b => data_to_w_sig, wren_a => ram_7_wren_a, wren_b => ram_7_wren_b, q_a => ram_7_out_a, q_b => ram_7_out_b ); output_control : ROUTE_global PORT MAP ( CLK => CLK, RESET_n => RESET_n, hazard => hazard_w_io, hazard_advanced => hazard_advanced, ram_0_out_a => ram_0_out_a, ram_0_out_b => ram_0_out_b, ram_1_out_a => ram_1_out_a, ram_1_out_b => ram_1_out_b, ram_2_out_a => ram_2_out_a, ram_2_out_b => ram_2_out_b, ram_3_out_a => ram_3_out_a, ram_3_out_b => ram_3_out_b, ram_4_out_a => ram_4_out_a, ram_4_out_b => ram_4_out_b, ram_5_out_a => ram_5_out_a, ram_5_out_b => ram_5_out_b, ram_6_out_a => ram_6_out_a, ram_6_out_b => ram_6_out_b, ram_7_out_a => ram_7_out_a, ram_7_out_b => ram_7_out_b, ram_0_sel_vector => ram_0_sel, ram_1_sel_vector => ram_1_sel, ram_2_sel_vector => ram_2_sel, ram_3_sel_vector => ram_3_sel, ram_4_sel_vector => ram_4_sel, ram_5_sel_vector => ram_5_sel, ram_6_sel_vector => ram_6_sel, ram_7_sel_vector => ram_7_sel, OUTPUT_A => output_a, OUTPUT_B => output_b, OUTPUT_C => output_c, OUTPUT_0 => output_0, OUTPUT_1 => output_1 ); -- latch_outputs : process (CLK, RESET_n) begin -- if (RESET_n = '0') then -- DATA_OUT_A <= "00000000000000000000000000000000"; -- DATA_OUT_B <= "00000000000000000000000000000000"; -- DATA_OUT_C <= "00000000000000000000000000000000"; -- DATA_OUT_0 <= "00000000000000000000000000000000"; -- DATA_OUT_1 <= "00000000000000000000000000000000"; -- elsif (rising_edge(CLK)) then -- DATA_OUT_A <= output_a; -- DATA_OUT_B <= output_b; -- DATA_OUT_C <= output_c; -- DATA_OUT_0 <= output_0; -- DATA_OUT_1 <= output_1; -- end if; -- end process; --******above latching used for testing******** DATA_OUT_A <= output_a; DATA_OUT_B <= output_b; DATA_OUT_C <= output_c; DATA_OUT_0 <= output_0; DATA_OUT_1 <= output_1; latch_vectors : process (CLK, RESET_n) begin if (RESET_n = '0') then ram_0_sel <= "0000000000"; ram_1_sel <= "0000000000"; ram_2_sel <= "0000000000"; ram_3_sel <= "0000000000"; ram_4_sel <= "0000000000"; ram_5_sel <= "0000000000"; ram_6_sel <= "0000000000"; ram_7_sel <= "0000000000"; hazard <= '0'; elsif (rising_edge(CLK)) then ram_0_sel <= ram_0_sel_vector; ram_1_sel <= ram_1_sel_vector; ram_2_sel <= ram_2_sel_vector; ram_3_sel <= ram_3_sel_vector; ram_4_sel <= ram_4_sel_vector; ram_5_sel <= ram_5_sel_vector; ram_6_sel <= ram_6_sel_vector; ram_7_sel <= ram_7_sel_vector; hazard <= stall_flag; end if; end process; -- latch_inputs : process (CLK, RESET_n) begin -- if (RESET_n = '0') then -- address_a_sig <= "00000000000000000000000000000000"; -- address_b_sig <= "00000000000000000000000000000000"; -- address_c_sig <= "00000000000000000000000000000000"; -- address_0_sig <= "00000000000000000000000000000000"; -- address_1_sig <= "00000000000000000000000000000000"; -- address_w_sig <= "00000000000000000000000000000000"; -- data_to_w_sig <= "00000000000000000000000000000000"; -- w_en_sig <= '0'; -- elsif (rising_edge(CLK)) then -- address_a_sig <= ADDRESS_A; -- address_b_sig <= ADDRESS_B; -- address_c_sig <= ADDRESS_C; -- address_0_sig <= ADDRESS_0; -- address_1_sig <= ADDRESS_1; -- address_w_sig <= ADDRESS_W; -- data_to_w_sig <= DATA_TO_W; -- w_en_sig <= W_EN; -- end if; -- end process; --****above latching used for testing************* address_a_sig <= ADDRESS_A; address_b_sig <= ADDRESS_B; address_c_sig <= ADDRESS_C; address_0_sig <= ADDRESS_0; address_1_sig <= ADDRESS_1; address_w_sig <= ADDRESS_W; data_to_w_sig <= DATA_TO_W; w_en_sig <= W_EN; RESET <= not RESET_n; stall <= stall_flag or hazard_w_io; --maybe without io hold <= c0_stall_sig and c1_stall_sig; C0_STALL <= (not core_id) or c0_stall_sig; --flipped not statement C1_STALL <= (core_id) or c1_stall_sig; --between these two lines CORE_IDENT <= core_id; hazard_w_io <= hazard or io_buffer_en; hazard_advanced <= hazard_w_io or stall_flag; id_gen : process (CLK, RESET_n, hold) begin if (RESET_n = '0') then core_id <= '0'; elsif (rising_edge(CLK)) then if (hold = '0' and IO_ENABLE = '0') then core_id <= not core_id; end if; end if; end process; override_io : process (CLK, RESET_n) begin if (RESET_n = '0') then io_buffer_en <= '0'; elsif (rising_edge(CLK)) then io_buffer_en <= IO_ENABLE; end if; end process; stalling : process (core_id, stall_flag, stall) begin if (core_id = '0' and stall = '1') then c0_stall_sig <= stall; c1_stall_sig <= stall_flag; elsif (core_id = '1' and stall = '1') then c0_stall_sig <= stall_flag; c1_stall_sig <= stall; else c0_stall_sig <= '0'; c1_stall_sig <= '0'; end if; end process; end;
entity arrayop1 is end entity; architecture test of arrayop1 is begin p1: process is variable x : bit_vector(1 to 3); begin assert x < "000"; wait; end process; end architecture;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:user:axi_compression:1.0 -- IP Revision: 29 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY design_1_axi_compression_0_0 IS PORT ( s00_axi_awaddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0); s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s00_axi_awvalid : IN STD_LOGIC; s00_axi_awready : OUT STD_LOGIC; s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s00_axi_wvalid : IN STD_LOGIC; s00_axi_wready : OUT STD_LOGIC; s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s00_axi_bvalid : OUT STD_LOGIC; s00_axi_bready : IN STD_LOGIC; s00_axi_araddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0); s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s00_axi_arvalid : IN STD_LOGIC; s00_axi_arready : OUT STD_LOGIC; s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s00_axi_rvalid : OUT STD_LOGIC; s00_axi_rready : IN STD_LOGIC; s00_axi_aclk : IN STD_LOGIC; s00_axi_aresetn : IN STD_LOGIC ); END design_1_axi_compression_0_0; ARCHITECTURE design_1_axi_compression_0_0_arch OF design_1_axi_compression_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_compression_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT axi_compression_v1_0 IS GENERIC ( C_S00_AXI_DATA_WIDTH : INTEGER; -- Width of S_AXI data bus C_S00_AXI_ADDR_WIDTH : INTEGER -- Width of S_AXI address bus ); PORT ( s00_axi_awaddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0); s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s00_axi_awvalid : IN STD_LOGIC; s00_axi_awready : OUT STD_LOGIC; s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s00_axi_wvalid : IN STD_LOGIC; s00_axi_wready : OUT STD_LOGIC; s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s00_axi_bvalid : OUT STD_LOGIC; s00_axi_bready : IN STD_LOGIC; s00_axi_araddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0); s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s00_axi_arvalid : IN STD_LOGIC; s00_axi_arready : OUT STD_LOGIC; s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s00_axi_rvalid : OUT STD_LOGIC; s00_axi_rready : IN STD_LOGIC; s00_axi_aclk : IN STD_LOGIC; s00_axi_aresetn : IN STD_LOGIC ); END COMPONENT axi_compression_v1_0; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT"; ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WDATA"; ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WVALID"; ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI WREADY"; ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BRESP"; ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BVALID"; ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI BREADY"; ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT"; ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RDATA"; ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RRESP"; ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S00_AXI RREADY"; ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S00_AXI_RST RST"; BEGIN U0 : axi_compression_v1_0 GENERIC MAP ( C_S00_AXI_DATA_WIDTH => 32, C_S00_AXI_ADDR_WIDTH => 6 ) PORT MAP ( s00_axi_awaddr => s00_axi_awaddr, s00_axi_awprot => s00_axi_awprot, s00_axi_awvalid => s00_axi_awvalid, s00_axi_awready => s00_axi_awready, s00_axi_wdata => s00_axi_wdata, s00_axi_wstrb => s00_axi_wstrb, s00_axi_wvalid => s00_axi_wvalid, s00_axi_wready => s00_axi_wready, s00_axi_bresp => s00_axi_bresp, s00_axi_bvalid => s00_axi_bvalid, s00_axi_bready => s00_axi_bready, s00_axi_araddr => s00_axi_araddr, s00_axi_arprot => s00_axi_arprot, s00_axi_arvalid => s00_axi_arvalid, s00_axi_arready => s00_axi_arready, s00_axi_rdata => s00_axi_rdata, s00_axi_rresp => s00_axi_rresp, s00_axi_rvalid => s00_axi_rvalid, s00_axi_rready => s00_axi_rready, s00_axi_aclk => s00_axi_aclk, s00_axi_aresetn => s00_axi_aresetn ); END design_1_axi_compression_0_0_arch;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- Copyright (C) 2015, Cobham Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: ahbtbp -- File: ahbtbp.vhd -- Author: Nils-Johan Wessman - Gaisler Research -- Description: AHB Testbench package ------------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; use grlib.devices.all; package ahbtbp is type ahbtbm_ctrl_type is record delay : std_logic_vector(7 downto 0); dbgl : integer; reset : std_logic; use128 : integer; end record; type ahbtbm_access_type is record haddr : std_logic_vector(31 downto 0); hdata : std_logic_vector(31 downto 0); hdata128 : std_logic_vector(127 downto 0); htrans : std_logic_vector(1 downto 0); hburst : std_logic_vector(2 downto 0); hsize : std_logic_vector(2 downto 0); hprot : std_logic_vector(3 downto 0); hwrite : std_logic; ctrl : ahbtbm_ctrl_type; end record; type ahbtbm_status_type is record err : std_logic; ecount : std_logic_vector(15 downto 0); eaddr : std_logic_vector(31 downto 0); edatac : std_logic_vector(31 downto 0); edatar : std_logic_vector(31 downto 0); hresp : std_logic_vector(1 downto 0); end record; type ahbtbm_access_array_type is array (0 to 1) of ahbtbm_access_type; type ahbtbm_ctrl_in_type is record ac : ahbtbm_access_type; end record; type ahbtbm_ctrl_out_type is record rst : std_logic; clk : std_logic; update : std_logic; dvalid : std_logic; hrdata : std_logic_vector(31 downto 0); hrdata128 : std_logic_vector(127 downto 0); status : ahbtbm_status_type; end record; type ahbtb_ctrl_type is record i : ahbtbm_ctrl_in_type; o : ahbtbm_ctrl_out_type; end record; constant ac_idle : ahbtbm_access_type := (haddr => x"00000000", hdata => x"00000000", hdata128 => x"00000000000000000000000000000000", htrans => "00", hburst =>"000", hsize => "000", hprot => "0000", hwrite => '0', ctrl => (delay => x"00", dbgl => 100, reset =>'0', use128 => 0)); constant ctrli_idle : ahbtbm_ctrl_in_type :=(ac => ac_idle); constant ctrlo_nodrive : ahbtbm_ctrl_out_type :=(rst => 'H', clk => 'H', update => 'H', dvalid => 'H', hrdata => (others => 'H'), hrdata128 => (others => 'H'), status => (err => 'H', ecount => (others => 'H'), eaddr => (others => 'H'), edatac => (others => 'H'), edatar => (others => 'H'), hresp => (others => 'H'))); impure function ptime return string; -- pragma translate_off ----------------------------------------------------------------------------- -- AHB testbench Master ----------------------------------------------------------------------------- component ahbtbm is generic ( hindex : integer := 0; hirq : integer := 0; venid : integer := 0; devid : integer := 0; version : integer := 0; chprot : integer := 3; incaddr : integer := 0); port ( rst : in std_ulogic; clk : in std_ulogic; ctrli : in ahbtbm_ctrl_in_type; ctrlo : out ahbtbm_ctrl_out_type; ahbmi : in ahb_mst_in_type; ahbmo : out ahb_mst_out_type ); end component; ----------------------------------------------------------------------------- -- AHB testbench Slave ----------------------------------------------------------------------------- component ahbtbs is generic ( hindex : integer := 0; haddr : integer := 0; hmask : integer := 16#fff#; tech : integer := 0; kbytes : integer := 1); port ( rst : in std_ulogic; clk : in std_ulogic; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type ); end component; ----------------------------------------------------------------------------- -- dprint (Debug print) ----------------------------------------------------------------------------- procedure dprint( constant doprint : in boolean := true; constant s : in string); procedure dprint( constant s : in string); ----------------------------------------------------------------------------- -- AMBATB Init ----------------------------------------------------------------------------- procedure ahbtbminit( signal ctrl : inout ahbtb_ctrl_type); ----------------------------------------------------------------------------- -- AMBATB DONE ----------------------------------------------------------------------------- procedure ahbtbmdone( constant stop: in integer; signal ctrl : inout ahbtb_ctrl_type); ----------------------------------------------------------------------------- -- AMBATB Idle ----------------------------------------------------------------------------- procedure ahbtbmidle( constant sync: in boolean; signal ctrl : inout ahbtb_ctrl_type); ----------------------------------------------------------------------------- -- AMBA AHB write access ----------------------------------------------------------------------------- procedure ahbwrite( constant address : in std_logic_vector(31 downto 0); constant data : in std_logic_vector(31 downto 0); constant size : in std_logic_vector(1 downto 0); constant debug : in integer; constant appidle : in boolean; signal ctrl : inout ahbtb_ctrl_type); ----------------------------------------------------------------------------- -- AMBA AHB write access (htrans) ----------------------------------------------------------------------------- procedure ahbwrite( constant address : in std_logic_vector(31 downto 0); constant data : in std_logic_vector(31 downto 0); constant size : in std_logic_vector(1 downto 0); constant htrans : in std_logic_vector(1 downto 0); constant hburst : in std_logic; constant debug : in integer; constant appidle : in boolean; signal ctrl : inout ahbtb_ctrl_type); ----------------------------------------------------------------------------- -- AMBA AHB write access (htrans,hprot) ----------------------------------------------------------------------------- procedure ahbwrite( constant address : in std_logic_vector(31 downto 0); constant data : in std_logic_vector(31 downto 0); constant size : in std_logic_vector(1 downto 0); constant htrans : in std_logic_vector(1 downto 0); constant hburst : in std_logic; constant debug : in integer; constant appidle : in boolean; constant hprot : in std_logic_vector(3 downto 0); signal ctrl : inout ahbtb_ctrl_type); ----------------------------------------------------------------------------- -- AMBA AHB write access (Inc Burst) ----------------------------------------------------------------------------- procedure ahbwrite( constant address : in std_logic_vector(31 downto 0); constant data : in std_logic_vector(31 downto 0); constant size : in std_logic_vector(1 downto 0); constant count : in integer; constant debug : in integer; signal ctrl : inout ahbtb_ctrl_type); ----------------------------------------------------------------------------- -- AMBA AHB read access ----------------------------------------------------------------------------- procedure ahbread( constant address : in std_logic_vector(31 downto 0); -- Address constant data : in std_logic_vector(31 downto 0); -- Data constant size : in std_logic_vector(1 downto 0); constant debug : in integer; constant appidle : in boolean; signal ctrl : inout ahbtb_ctrl_type); ----------------------------------------------------------------------------- -- AMBA AHB read access (htrans) ----------------------------------------------------------------------------- procedure ahbread( constant address : in std_logic_vector(31 downto 0); -- Address constant data : in std_logic_vector(31 downto 0); -- Data constant size : in std_logic_vector(1 downto 0); constant htrans : in std_logic_vector(1 downto 0); constant hburst : in std_logic; constant debug : in integer; constant appidle : in boolean; signal ctrl : inout ahbtb_ctrl_type); ----------------------------------------------------------------------------- -- AMBA AHB read access (htrans,hprot) ----------------------------------------------------------------------------- procedure ahbread( constant address : in std_logic_vector(31 downto 0); -- Address constant data : in std_logic_vector(31 downto 0); -- Data constant size : in std_logic_vector(1 downto 0); constant htrans : in std_logic_vector(1 downto 0); constant hburst : in std_logic; constant debug : in integer; constant appidle : in boolean; constant hprot : in std_logic_vector(3 downto 0); signal ctrl : inout ahbtb_ctrl_type); ----------------------------------------------------------------------------- -- AMBA AHB read access (Inc Burst) ----------------------------------------------------------------------------- procedure ahbread( constant address : in std_logic_vector(31 downto 0); -- Start address constant data : in std_logic_vector(31 downto 0); -- Start data constant size : in std_logic_vector(1 downto 0); constant count : in integer; constant debug : in integer; signal ctrl : inout ahbtb_ctrl_type); ----------------------------------------------------------------------------- -- AMBA AHB(128) write access (htrans) ----------------------------------------------------------------------------- procedure ahb128write( constant address : in std_logic_vector(31 downto 0); constant data : in std_logic_vector(127 downto 0); constant size : in std_logic_vector(2 downto 0); constant htrans : in std_logic_vector(1 downto 0); constant hburst : in std_logic; constant debug : in integer; constant appidle : in boolean; signal ctrl : inout ahbtb_ctrl_type); ----------------------------------------------------------------------------- -- AMBA AHB(128) write access (htrans,hprot) ----------------------------------------------------------------------------- procedure ahb128write( constant address : in std_logic_vector(31 downto 0); constant data : in std_logic_vector(127 downto 0); constant size : in std_logic_vector(2 downto 0); constant htrans : in std_logic_vector(1 downto 0); constant hburst : in std_logic; constant debug : in integer; constant appidle : in boolean; constant hprot : in std_logic_vector(3 downto 0); signal ctrl : inout ahbtb_ctrl_type); ----------------------------------------------------------------------------- -- AMBA AHB(128) read access (htrans) ----------------------------------------------------------------------------- procedure ahb128read( constant address : in std_logic_vector(31 downto 0); -- Address constant data : in std_logic_vector(127 downto 0); -- Data constant size : in std_logic_vector(2 downto 0); constant htrans : in std_logic_vector(1 downto 0); constant hburst : in std_logic; constant debug : in integer; constant appidle : in boolean; signal ctrl : inout ahbtb_ctrl_type); ----------------------------------------------------------------------------- -- AMBA AHB(128) read access (htrans,hprot) ----------------------------------------------------------------------------- procedure ahb128read( constant address : in std_logic_vector(31 downto 0); -- Address constant data : in std_logic_vector(127 downto 0); -- Data constant size : in std_logic_vector(2 downto 0); constant htrans : in std_logic_vector(1 downto 0); constant hburst : in std_logic; constant debug : in integer; constant appidle : in boolean; constant hprot : in std_logic_vector(3 downto 0); signal ctrl : inout ahbtb_ctrl_type); ----------------------------------------------------------------------------- -- AMBA AHB(64) write access (htrans) ----------------------------------------------------------------------------- procedure ahb64write( constant address : in std_logic_vector(31 downto 0); constant data : in std_logic_vector(63 downto 0); constant size : in std_logic_vector(2 downto 0); constant htrans : in std_logic_vector(1 downto 0); constant hburst : in std_logic; constant debug : in integer; constant appidle : in boolean; signal ctrl : inout ahbtb_ctrl_type); ----------------------------------------------------------------------------- -- AMBA AHB(64) write access (htrans,hprot) ----------------------------------------------------------------------------- procedure ahb64write( constant address : in std_logic_vector(31 downto 0); constant data : in std_logic_vector(63 downto 0); constant size : in std_logic_vector(2 downto 0); constant htrans : in std_logic_vector(1 downto 0); constant hburst : in std_logic; constant debug : in integer; constant appidle : in boolean; constant hprot : in std_logic_vector(3 downto 0); signal ctrl : inout ahbtb_ctrl_type); ----------------------------------------------------------------------------- -- AMBA AHB(64) read access (htrans) ----------------------------------------------------------------------------- procedure ahb64read( constant address : in std_logic_vector(31 downto 0); -- Address constant data : in std_logic_vector(63 downto 0); -- Data constant size : in std_logic_vector(2 downto 0); constant htrans : in std_logic_vector(1 downto 0); constant hburst : in std_logic; constant debug : in integer; constant appidle : in boolean; signal ctrl : inout ahbtb_ctrl_type); ----------------------------------------------------------------------------- -- AMBA AHB(64) read access (htrans,hprot) ----------------------------------------------------------------------------- procedure ahb64read( constant address : in std_logic_vector(31 downto 0); -- Address constant data : in std_logic_vector(63 downto 0); -- Data constant size : in std_logic_vector(2 downto 0); constant htrans : in std_logic_vector(1 downto 0); constant hburst : in std_logic; constant debug : in integer; constant appidle : in boolean; constant hprot : in std_logic_vector(3 downto 0); signal ctrl : inout ahbtb_ctrl_type); end ahbtbp; package body ahbtbp is impure function ptime return string is variable s : string(1 to 20); variable length : integer := tost(NOW / 1 ns)'length; begin s(1 to length + 9) :="Time: " & tost(NOW / 1 ns) & "ns "; return s(1 to length + 9); end function ptime; ----------------------------------------------------------------------------- -- dprint (Debug print) ----------------------------------------------------------------------------- procedure dprint( constant doprint : in boolean := true; constant s : in string) is begin if doprint = true then print(s); end if; end procedure dprint; procedure dprint( constant s : in string) is begin print(s); end procedure dprint; ----------------------------------------------------------------------------- -- AHBTB init ----------------------------------------------------------------------------- procedure ahbtbminit( signal ctrl : inout ahbtb_ctrl_type) is begin ctrl.o <= ctrlo_nodrive; ctrl.i <= ctrli_idle; --ctrli.ac.hburst <= "000"; ctrli.ac.hsize <= "010"; --ctrli.ac.haddr <= x"00000000"; ctrli.ac.hdata <= x"00000000"; --ctrli.ac.htrans <= "00"; ctrli.ac.hwrite <= '0'; wait until ctrl.o.rst = '1'; print("********************************************************"); print(" AHBTBM Testbench Init"); print("******************************************************"); end procedure ahbtbminit; ----------------------------------------------------------------------------- -- AMBTB DONE ----------------------------------------------------------------------------- procedure ahbtbmdone( constant stop: in integer; signal ctrl : inout ahbtb_ctrl_type) is begin --ctrl.o <= ctrlo_nodrive; wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i <= ctrli_idle; wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); print("******************************************************"); print(" AHBTBM Testbench Done"); print("********************************************************"); wait for 100 ns; assert stop = 0 report "ahbtb testbench done!" severity FAILURE; end procedure ahbtbmdone; ----------------------------------------------------------------------------- -- AMBTB Idle ----------------------------------------------------------------------------- procedure ahbtbmidle( constant sync: in boolean; signal ctrl : inout ahbtb_ctrl_type) is begin --ctrl.o <= ctrlo_nodrive; wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i <= ctrli_idle; if sync = true then wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); end if; end procedure ahbtbmidle; ----------------------------------------------------------------------------- -- AMBA AHB write access ----------------------------------------------------------------------------- procedure ahbwrite( constant address : in std_logic_vector(31 downto 0); constant data : in std_logic_vector(31 downto 0); constant size : in std_logic_vector(1 downto 0); constant debug : in integer; constant appidle : in boolean; signal ctrl : inout ahbtb_ctrl_type) is begin --ctrl.o <= ctrlo_nodrive; wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i.ac.ctrl.use128 <= 0; ctrl.i.ac.ctrl.dbgl <= debug; ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size; ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data; ctrl.i.ac.htrans <= "10"; ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hprot <= "1110"; if appidle = true then wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i <= ctrli_idle; end if; end procedure ahbwrite; ----------------------------------------------------------------------------- -- AMBA AHB write access (htrans) ----------------------------------------------------------------------------- procedure ahbwrite( constant address : in std_logic_vector(31 downto 0); constant data : in std_logic_vector(31 downto 0); constant size : in std_logic_vector(1 downto 0); constant htrans : in std_logic_vector(1 downto 0); constant hburst : in std_logic; constant debug : in integer; constant appidle : in boolean; signal ctrl : inout ahbtb_ctrl_type) is begin --ctrl.o <= ctrlo_nodrive; wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i.ac.ctrl.use128 <= 0; ctrl.i.ac.ctrl.dbgl <= debug; ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size; ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data; ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "00" & hburst; ctrl.i.ac.hprot <= "1110"; if appidle = true then wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i <= ctrli_idle; end if; end procedure ahbwrite; ----------------------------------------------------------------------------- -- AMBA AHB write access (Inc Burst) ----------------------------------------------------------------------------- procedure ahbwrite( constant address : in std_logic_vector(31 downto 0); constant data : in std_logic_vector(31 downto 0); constant size : in std_logic_vector(1 downto 0); constant count : in integer; constant debug : in integer; signal ctrl : inout ahbtb_ctrl_type) is variable vaddr : std_logic_vector(31 downto 0); variable vdata : std_logic_vector(31 downto 0); variable vhtrans : std_logic_vector(1 downto 0); begin --ctrl.o <= ctrlo_nodrive; vaddr := address; vdata := data; vhtrans := "10"; wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i.ac.ctrl.use128 <= 0; ctrl.i.ac.ctrl.dbgl <= debug; ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size; ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "001"; ctrl.i.ac.hprot <= "1110"; for i in 0 to count - 1 loop ctrl.i.ac.haddr <= vaddr; ctrl.i.ac.hdata <= vdata; ctrl.i.ac.htrans <= vhtrans; wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); vaddr := vaddr + x"4"; vdata := vdata + 1; vhtrans := "11"; end loop; ctrl.i <= ctrli_idle; end procedure ahbwrite; ----------------------------------------------------------------------------- -- AMBA AHB write access (htrans,hprot) ----------------------------------------------------------------------------- procedure ahbwrite( constant address : in std_logic_vector(31 downto 0); constant data : in std_logic_vector(31 downto 0); constant size : in std_logic_vector(1 downto 0); constant htrans : in std_logic_vector(1 downto 0); constant hburst : in std_logic; constant debug : in integer; constant appidle : in boolean; constant hprot : in std_logic_vector(3 downto 0); signal ctrl : inout ahbtb_ctrl_type) is begin --ctrl.o <= ctrlo_nodrive; wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i.ac.ctrl.use128 <= 0; ctrl.i.ac.ctrl.dbgl <= debug; ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size; ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data; ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "00" & hburst; ctrl.i.ac.hprot <= hprot; if appidle = true then wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i <= ctrli_idle; end if; end procedure ahbwrite; ----------------------------------------------------------------------------- -- AMBA AHB read access ----------------------------------------------------------------------------- procedure ahbread( constant address : in std_logic_vector(31 downto 0); constant data : in std_logic_vector(31 downto 0); constant size : in std_logic_vector(1 downto 0); constant debug : in integer; constant appidle : in boolean; signal ctrl : inout ahbtb_ctrl_type) is begin --ctrl.o <= ctrlo_nodrive; wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i.ac.ctrl.use128 <= 0; ctrl.i.ac.ctrl.dbgl <= debug; ctrl.i.ac.hsize <= '0' & size; ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data; ctrl.i.ac.htrans <= "10"; ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hprot <= "1110"; if appidle = true then wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i <= ctrli_idle; end if; end procedure ahbread; ----------------------------------------------------------------------------- -- AMBA AHB read access (htrans) ----------------------------------------------------------------------------- procedure ahbread( constant address : in std_logic_vector(31 downto 0); constant data : in std_logic_vector(31 downto 0); constant size : in std_logic_vector(1 downto 0); constant htrans : in std_logic_vector(1 downto 0); constant hburst : in std_logic; constant debug : in integer; constant appidle : in boolean; signal ctrl : inout ahbtb_ctrl_type) is begin --ctrl.o <= ctrlo_nodrive; wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i.ac.ctrl.use128 <= 0; ctrl.i.ac.ctrl.dbgl <= debug; ctrl.i.ac.hsize <= '0' & size; ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data; ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "00" & hburst; ctrl.i.ac.hprot <= "1110"; if appidle = true then wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i <= ctrli_idle; end if; end procedure ahbread; ----------------------------------------------------------------------------- -- AMBA AHB read access (Inc Burst) ----------------------------------------------------------------------------- procedure ahbread( constant address : in std_logic_vector(31 downto 0); constant data : in std_logic_vector(31 downto 0); constant size : in std_logic_vector(1 downto 0); constant count : in integer; constant debug : in integer; signal ctrl : inout ahbtb_ctrl_type) is variable vaddr : std_logic_vector(31 downto 0); variable vdata : std_logic_vector(31 downto 0); variable vhtrans : std_logic_vector(1 downto 0); begin --ctrl.o <= ctrlo_nodrive; vaddr := address; vdata := data; vhtrans := "10"; wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i.ac.ctrl.use128 <= 0; ctrl.i.ac.ctrl.dbgl <= debug; ctrl.i.ac.hburst <= "000"; ctrl.i.ac.hsize <= '0' & size; ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "001"; ctrl.i.ac.hprot <= "1110"; for i in 0 to count - 1 loop ctrl.i.ac.haddr <= vaddr; ctrl.i.ac.hdata <= vdata; ctrl.i.ac.htrans <= vhtrans; wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); vaddr := vaddr + x"4"; vdata := vdata + 1; vhtrans := "11"; end loop; ctrl.i <= ctrli_idle; end procedure ahbread; ----------------------------------------------------------------------------- -- AMBA AHB read access (htrans) ----------------------------------------------------------------------------- procedure ahbread( constant address : in std_logic_vector(31 downto 0); constant data : in std_logic_vector(31 downto 0); constant size : in std_logic_vector(1 downto 0); constant htrans : in std_logic_vector(1 downto 0); constant hburst : in std_logic; constant debug : in integer; constant appidle : in boolean; constant hprot : in std_logic_vector(3 downto 0); signal ctrl : inout ahbtb_ctrl_type) is begin --ctrl.o <= ctrlo_nodrive; wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i.ac.ctrl.use128 <= 0; ctrl.i.ac.ctrl.dbgl <= debug; ctrl.i.ac.hsize <= '0' & size; ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata <= data; ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "00" & hburst; ctrl.i.ac.hprot <= hprot; if appidle = true then wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i <= ctrli_idle; end if; end procedure ahbread; ----------------------------------------------------------------------------- -- AMBA AHB(128) write access (htrans) ----------------------------------------------------------------------------- procedure ahb128write( constant address : in std_logic_vector(31 downto 0); constant data : in std_logic_vector(127 downto 0); constant size : in std_logic_vector(2 downto 0); constant htrans : in std_logic_vector(1 downto 0); constant hburst : in std_logic; constant debug : in integer; constant appidle : in boolean; signal ctrl : inout ahbtb_ctrl_type) is begin --ctrl.o <= ctrlo_nodrive; wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i.ac.ctrl.use128 <= 1; ctrl.i.ac.ctrl.dbgl <= debug; ctrl.i.ac.hsize <= size; ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data; ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "00" & hburst; ctrl.i.ac.hprot <= "1110"; if appidle = true then wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i <= ctrli_idle; end if; end procedure ahb128write; ----------------------------------------------------------------------------- -- AMBA AHB(128) write access (htrans,hprot) ----------------------------------------------------------------------------- procedure ahb128write( constant address : in std_logic_vector(31 downto 0); constant data : in std_logic_vector(127 downto 0); constant size : in std_logic_vector(2 downto 0); constant htrans : in std_logic_vector(1 downto 0); constant hburst : in std_logic; constant debug : in integer; constant appidle : in boolean; constant hprot : in std_logic_vector(3 downto 0); signal ctrl : inout ahbtb_ctrl_type) is begin --ctrl.o <= ctrlo_nodrive; wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i.ac.ctrl.use128 <= 1; ctrl.i.ac.ctrl.dbgl <= debug; ctrl.i.ac.hsize <= size; ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data; ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "00" & hburst; ctrl.i.ac.hprot <= hprot; if appidle = true then wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i <= ctrli_idle; end if; end procedure ahb128write; ----------------------------------------------------------------------------- -- AMBA AHB(128) read access (htrans) ----------------------------------------------------------------------------- procedure ahb128read( constant address : in std_logic_vector(31 downto 0); constant data : in std_logic_vector(127 downto 0); constant size : in std_logic_vector(2 downto 0); constant htrans : in std_logic_vector(1 downto 0); constant hburst : in std_logic; constant debug : in integer; constant appidle : in boolean; signal ctrl : inout ahbtb_ctrl_type) is begin --ctrl.o <= ctrlo_nodrive; wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i.ac.ctrl.use128 <= 1; ctrl.i.ac.ctrl.dbgl <= debug; ctrl.i.ac.hsize <= size; ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data; ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "00" & hburst; ctrl.i.ac.hprot <= "1110"; if appidle = true then wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i <= ctrli_idle; end if; end procedure ahb128read; ----------------------------------------------------------------------------- -- AMBA AHB(128) read access (htrans,hprot) ----------------------------------------------------------------------------- procedure ahb128read( constant address : in std_logic_vector(31 downto 0); constant data : in std_logic_vector(127 downto 0); constant size : in std_logic_vector(2 downto 0); constant htrans : in std_logic_vector(1 downto 0); constant hburst : in std_logic; constant debug : in integer; constant appidle : in boolean; constant hprot : in std_logic_vector(3 downto 0); signal ctrl : inout ahbtb_ctrl_type) is begin --ctrl.o <= ctrlo_nodrive; wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i.ac.ctrl.use128 <= 1; ctrl.i.ac.ctrl.dbgl <= debug; ctrl.i.ac.hsize <= size; ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data; ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "00" & hburst; ctrl.i.ac.hprot <= hprot; if appidle = true then wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i <= ctrli_idle; end if; end procedure ahb128read; ----------------------------------------------------------------------------- -- AMBA AHB(64) write access (htrans) ----------------------------------------------------------------------------- procedure ahb64write( constant address : in std_logic_vector(31 downto 0); constant data : in std_logic_vector(63 downto 0); constant size : in std_logic_vector(2 downto 0); constant htrans : in std_logic_vector(1 downto 0); constant hburst : in std_logic; constant debug : in integer; constant appidle : in boolean; signal ctrl : inout ahbtb_ctrl_type) is begin --ctrl.o <= ctrlo_nodrive; wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i.ac.ctrl.use128 <= 1; ctrl.i.ac.ctrl.dbgl <= debug; ctrl.i.ac.hsize <= size; ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data; ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "00" & hburst; ctrl.i.ac.hprot <= "1110"; if appidle = true then wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i <= ctrli_idle; end if; end procedure ahb64write; ----------------------------------------------------------------------------- -- AMBA AHB(64) write access (htrans,hprot) ----------------------------------------------------------------------------- procedure ahb64write( constant address : in std_logic_vector(31 downto 0); constant data : in std_logic_vector(63 downto 0); constant size : in std_logic_vector(2 downto 0); constant htrans : in std_logic_vector(1 downto 0); constant hburst : in std_logic; constant debug : in integer; constant appidle : in boolean; constant hprot : in std_logic_vector(3 downto 0); signal ctrl : inout ahbtb_ctrl_type) is begin --ctrl.o <= ctrlo_nodrive; wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i.ac.ctrl.use128 <= 1; ctrl.i.ac.ctrl.dbgl <= debug; ctrl.i.ac.hsize <= size; ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data; ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '1'; ctrl.i.ac.hburst <= "00" & hburst; ctrl.i.ac.hprot <= hprot; if appidle = true then wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i <= ctrli_idle; end if; end procedure ahb64write; ----------------------------------------------------------------------------- -- AMBA AHB(64) read access (htrans) ----------------------------------------------------------------------------- procedure ahb64read( constant address : in std_logic_vector(31 downto 0); constant data : in std_logic_vector(63 downto 0); constant size : in std_logic_vector(2 downto 0); constant htrans : in std_logic_vector(1 downto 0); constant hburst : in std_logic; constant debug : in integer; constant appidle : in boolean; signal ctrl : inout ahbtb_ctrl_type) is begin --ctrl.o <= ctrlo_nodrive; wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i.ac.ctrl.use128 <= 1; ctrl.i.ac.ctrl.dbgl <= debug; ctrl.i.ac.hsize <= size; ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data; ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "00" & hburst; ctrl.i.ac.hprot <= "1110"; if appidle = true then wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i <= ctrli_idle; end if; end procedure ahb64read; ----------------------------------------------------------------------------- -- AMBA AHB(64) read access (htrans,hprot) ----------------------------------------------------------------------------- procedure ahb64read( constant address : in std_logic_vector(31 downto 0); constant data : in std_logic_vector(63 downto 0); constant size : in std_logic_vector(2 downto 0); constant htrans : in std_logic_vector(1 downto 0); constant hburst : in std_logic; constant debug : in integer; constant appidle : in boolean; constant hprot : in std_logic_vector(3 downto 0); signal ctrl : inout ahbtb_ctrl_type) is begin --ctrl.o <= ctrlo_nodrive; wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i.ac.ctrl.use128 <= 1; ctrl.i.ac.ctrl.dbgl <= debug; ctrl.i.ac.hsize <= size; ctrl.i.ac.haddr <= address; ctrl.i.ac.hdata128 <= data & data; ctrl.i.ac.htrans <= htrans; ctrl.i.ac.hwrite <= '0'; ctrl.i.ac.hburst <= "00" & hburst; ctrl.i.ac.hprot <= hprot; if appidle = true then wait until ctrl.o.update = '1' and rising_edge(ctrl.o.clk); ctrl.i <= ctrli_idle; end if; end procedure ahb64read; -- pragma translate_on end ahbtbp;
entity array1 is end entity; architecture test of array1 is function func return bit_vector; begin process is begin assert func = "10"; wait; end process; end architecture;
entity array1 is end entity; architecture test of array1 is function func return bit_vector; begin process is begin assert func = "10"; wait; end process; end architecture;
entity array1 is end entity; architecture test of array1 is function func return bit_vector; begin process is begin assert func = "10"; wait; end process; end architecture;
entity array1 is end entity; architecture test of array1 is function func return bit_vector; begin process is begin assert func = "10"; wait; end process; end architecture;
----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Release Version 13.1 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from fp_sqrt_double_s5 -- VHDL created on Tue Apr 9 15:17:30 2013 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; entity fp_sqrt_double_s5 is port ( a : in std_logic_vector(63 downto 0); en : in std_logic_vector(0 downto 0); q : out std_logic_vector(63 downto 0); clk : in std_logic; areset : in std_logic ); end; architecture normal of fp_sqrt_double_s5 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstAllOWE_uid9_fpSqrtTest_q : std_logic_vector (10 downto 0); signal cstAllZWF_uid10_fpSqrtTest_q : std_logic_vector (51 downto 0); signal cstAllZWE_uid11_fpSqrtTest_q : std_logic_vector (10 downto 0); signal sBias_uid25_fpSqrtTest_q : std_logic_vector (10 downto 0); signal sBiasM1_uid28_fpSqrtTest_q : std_logic_vector (10 downto 0); signal expRMux_uid33_fpSqrtTest_s : std_logic_vector (0 downto 0); signal expRMux_uid33_fpSqrtTest_q : std_logic_vector (10 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_a : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_b : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_q : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_a : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_b : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_q : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_a : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_b : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_q : std_logic_vector(0 downto 0); signal fracSel_uid47_fpSqrtTest_q : std_logic_vector(1 downto 0); signal fracNaN_uid52_fpSqrtTest_q : std_logic_vector (51 downto 0); signal negZero_uid56_fpSqrtTest_a : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_b : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_q : std_logic_vector(0 downto 0); signal rndBit_uid93_sqrtPolynomialEvaluator_q : std_logic_vector (1 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a : std_logic_vector (16 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 : std_logic_vector (33 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr : SIGNED (34 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a : std_logic_vector (23 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 : std_logic_vector (49 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr : SIGNED (50 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q : std_logic_vector (49 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a : std_logic_vector (32 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 : std_logic_vector (67 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr : SIGNED (68 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q : std_logic_vector (67 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector (26 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 : std_logic_vector (53 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr : SIGNED (54 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (53 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid59_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid60_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid62_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid63_sqrtTableGenerator_lutmem_ia : std_logic_vector (8 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_iq : std_logic_vector (8 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_q : std_logic_vector (8 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC2_uid65_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC3_uid67_sqrtTableGenerator_lutmem_ia : std_logic_vector (32 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_iq : std_logic_vector (32 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_q : std_logic_vector (32 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC4_uid69_sqrtTableGenerator_lutmem_ia : std_logic_vector (23 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_iq : std_logic_vector (23 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_q : std_logic_vector (23 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC5_uid71_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0); type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type; attribute preserve : boolean; attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : signal is true; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type is array(0 to 1) of SIGNED(17 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type; attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : signal is true; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type is array(0 to 1) of SIGNED(18 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type is array(0 to 1) of SIGNED(36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type; signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s0 : std_logic_vector(36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q : std_logic_vector (36 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr : UNSIGNED (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr : UNSIGNED (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr : SIGNED (54 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr : SIGNED (54 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a : std_logic_vector(84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b : std_logic_vector(84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o : std_logic_vector (84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q : std_logic_vector (83 downto 0); signal reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q : std_logic_vector (0 downto 0); signal reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q : std_logic_vector (0 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0); signal reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q : std_logic_vector (8 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q : std_logic_vector (16 downto 0); signal reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q : std_logic_vector (16 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0); signal reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0); signal reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q : std_logic_vector (25 downto 0); signal reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0); signal reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0); signal reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q : std_logic_vector (34 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q : std_logic_vector (39 downto 0); signal reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q : std_logic_vector (17 downto 0); signal reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q : std_logic_vector (17 downto 0); signal reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q : std_logic_vector (16 downto 0); signal reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q : std_logic_vector (17 downto 0); signal reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q : std_logic_vector (26 downto 0); signal reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q : std_logic_vector (50 downto 0); signal reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q : std_logic_vector (42 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q : std_logic_vector (53 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0); signal reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q : std_logic_vector (16 downto 0); signal reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q : std_logic_vector (56 downto 0); signal reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q : std_logic_vector (49 downto 0); signal reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q : std_logic_vector (1 downto 0); signal reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q : std_logic_vector (51 downto 0); signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q : std_logic_vector (51 downto 0); signal ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q : std_logic_vector (0 downto 0); signal ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q : std_logic_vector (10 downto 0); signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q : std_logic_vector (55 downto 0); signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q : std_logic_vector (53 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0); signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q : std_logic_vector (51 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 : std_logic; signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq : std_logic; signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : signal is true; signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 : std_logic; signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : signal is true; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 : std_logic; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i : unsigned(4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq : std_logic; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q : std_logic_vector (5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : signal is true; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true; signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic; signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 : std_logic; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq : std_logic; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a : std_logic_vector(56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b : std_logic_vector(56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o : std_logic_vector (56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q : std_logic_vector (55 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal expX_uid6_fpSqrtTest_in : std_logic_vector (62 downto 0); signal expX_uid6_fpSqrtTest_b : std_logic_vector (10 downto 0); signal fracX_uid7_fpSqrtTest_in : std_logic_vector (51 downto 0); signal fracX_uid7_fpSqrtTest_b : std_logic_vector (51 downto 0); signal signX_uid8_fpSqrtTest_in : std_logic_vector (63 downto 0); signal signX_uid8_fpSqrtTest_b : std_logic_vector (0 downto 0); signal expXIsZero_uid13_fpSqrtTest_a : std_logic_vector(10 downto 0); signal expXIsZero_uid13_fpSqrtTest_b : std_logic_vector(10 downto 0); signal expXIsZero_uid13_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid15_fpSqrtTest_a : std_logic_vector(10 downto 0); signal expXIsMax_uid15_fpSqrtTest_b : std_logic_vector(10 downto 0); signal expXIsMax_uid15_fpSqrtTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid17_fpSqrtTest_a : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSqrtTest_b : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSqrtTest_q : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expEvenSig_uid26_fpSqrtTest_a : std_logic_vector(11 downto 0); signal expEvenSig_uid26_fpSqrtTest_b : std_logic_vector(11 downto 0); signal expEvenSig_uid26_fpSqrtTest_o : std_logic_vector (11 downto 0); signal expEvenSig_uid26_fpSqrtTest_q : std_logic_vector (11 downto 0); signal expOddSig_uid29_fpSqrtTest_a : std_logic_vector(11 downto 0); signal expOddSig_uid29_fpSqrtTest_b : std_logic_vector(11 downto 0); signal expOddSig_uid29_fpSqrtTest_o : std_logic_vector (11 downto 0); signal expOddSig_uid29_fpSqrtTest_q : std_logic_vector (11 downto 0); signal excRNaN_uid44_fpSqrtTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expRPostExc_uid51_fpSqrtTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid51_fpSqrtTest_q : std_logic_vector (10 downto 0); signal fracRPostExc_uid55_fpSqrtTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid55_fpSqrtTest_q : std_logic_vector (51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_a : std_logic_vector(51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_b : std_logic_vector(51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_o : std_logic_vector (51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_q : std_logic_vector (51 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_a : std_logic_vector(57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_b : std_logic_vector(57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_o : std_logic_vector (57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_q : std_logic_vector (57 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal join_uid45_fpSqrtTest_q : std_logic_vector (2 downto 0); signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0); signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in : std_logic_vector (49 downto 0); signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in : std_logic_vector (67 downto 0); signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (33 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q : std_logic_vector (53 downto 0); signal os_uid64_sqrtTableGenerator_q : std_logic_vector (48 downto 0); signal os_uid61_sqrtTableGenerator_q : std_logic_vector (56 downto 0); signal s5_uid99_uid102_sqrtPolynomialEvaluator_q : std_logic_vector (59 downto 0); signal FracX44dto0_uid37_fpSqrtTest_in : std_logic_vector (44 downto 0); signal FracX44dto0_uid37_fpSqrtTest_b : std_logic_vector (44 downto 0); signal fracSelIn_uid46_fpSqrtTest_q : std_logic_vector (3 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int : std_logic_vector (82 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q : std_logic_vector (82 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int : std_logic_vector (107 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q : std_logic_vector (107 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0); signal RSqrt_uid57_fpSqrtTest_q : std_logic_vector (63 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a : std_logic_vector(5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b : std_logic_vector(5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q : std_logic_vector(0 downto 0); signal yT4_uid91_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT4_uid91_sqrtPolynomialEvaluator_b : std_logic_vector (39 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b : std_logic_vector (26 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a : std_logic_vector(3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b : std_logic_vector(3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal expX0_uid31_fpSqrtTest_in : std_logic_vector (0 downto 0); signal expX0_uid31_fpSqrtTest_b : std_logic_vector (0 downto 0); signal fracXAddr_uid35_fpSqrtTest_in : std_logic_vector (51 downto 0); signal fracXAddr_uid35_fpSqrtTest_b : std_logic_vector (6 downto 0); signal InvSignX_uid40_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvSignX_uid40_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid22_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid22_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expREven_uid27_fpSqrtTest_in : std_logic_vector (11 downto 0); signal expREven_uid27_fpSqrtTest_b : std_logic_vector (10 downto 0); signal expROdd_uid30_fpSqrtTest_in : std_logic_vector (11 downto 0); signal expROdd_uid30_fpSqrtTest_b : std_logic_vector (10 downto 0); signal s4_uid96_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0); signal s4_uid96_sqrtPolynomialEvaluator_b : std_logic_vector (50 downto 0); signal lowRangeB_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid76_sqrtPolynomialEvaluator_in : std_logic_vector (17 downto 0); signal highBBits_uid76_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal lowRangeB_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid82_sqrtPolynomialEvaluator_in : std_logic_vector (26 downto 0); signal highBBits_uid82_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0); signal lowRangeB_uid87_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid87_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid88_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0); signal highBBits_uid88_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0); signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (5 downto 0); signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (5 downto 0); signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (34 downto 0); signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (28 downto 0); signal cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q : std_logic_vector (50 downto 0); signal fracR_uid39_fpSqrtTest_in : std_logic_vector (56 downto 0); signal fracR_uid39_fpSqrtTest_b : std_logic_vector (51 downto 0); signal yT1_uid73_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT1_uid73_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal yT2_uid79_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT2_uid79_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0); signal yT3_uid85_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT3_uid85_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a : std_logic_vector(108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b : std_logic_vector(108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o : std_logic_vector (108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q : std_logic_vector (108 downto 0); signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0); signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0); signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0); signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0); signal expOddSelect_uid32_fpSqrtTest_a : std_logic_vector(0 downto 0); signal expOddSelect_uid32_fpSqrtTest_q : std_logic_vector(0 downto 0); signal addrTable_uid36_fpSqrtTest_q : std_logic_vector (7 downto 0); signal exc_N_uid20_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_N_uid20_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_N_uid20_fpSqrtTest_q : std_logic_vector(0 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b : std_logic_vector (26 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_a : std_logic_vector(24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_b : std_logic_vector(24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_o : std_logic_vector (24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_q : std_logic_vector (24 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_a : std_logic_vector(33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_b : std_logic_vector(33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_o : std_logic_vector (33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_a : std_logic_vector(40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_b : std_logic_vector(40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_o : std_logic_vector (40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_q : std_logic_vector (40 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector(54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector(54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o : std_logic_vector (54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (54 downto 0); signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in : std_logic_vector (95 downto 0); signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b : std_logic_vector (51 downto 0); signal pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (16 downto 0); signal InvExc_N_uid21_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid21_fpSqrtTest_q : std_logic_vector(0 downto 0); signal s1_uid75_uid78_sqrtPolynomialEvaluator_q : std_logic_vector (25 downto 0); signal s2_uid81_uid84_sqrtPolynomialEvaluator_q : std_logic_vector (34 downto 0); signal s3_uid87_uid90_sqrtPolynomialEvaluator_q : std_logic_vector (41 downto 0); signal add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (60 downto 0); signal lowRangeB_uid99_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0); signal lowRangeB_uid99_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0); signal highBBits_uid100_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0); signal highBBits_uid100_sqrtPolynomialEvaluator_b : std_logic_vector (49 downto 0); signal exc_R_uid24_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_c : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_q : std_logic_vector(0 downto 0); signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0); signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (14 downto 0); signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (14 downto 0); signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0); signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (59 downto 0); signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (42 downto 0); signal spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (15 downto 0); signal pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (17 downto 0); begin --VCC(CONSTANT,1) VCC_q <= "1"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable(LOGICAL,408) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q <= not ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor(LOGICAL,435) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q <= not (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a or ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top(CONSTANT,431) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q <= "011000"; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp(LOGICAL,432) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q <= "1" when ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a = ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b else "0"; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg(REG,433) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q; END IF; END IF; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena(REG,436) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd(LOGICAL,437) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b <= en; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a and ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b; --signX_uid8_fpSqrtTest(BITSELECT,7)@0 signX_uid8_fpSqrtTest_in <= a; signX_uid8_fpSqrtTest_b <= signX_uid8_fpSqrtTest_in(63 downto 63); --cstAllZWE_uid11_fpSqrtTest(CONSTANT,10) cstAllZWE_uid11_fpSqrtTest_q <= "00000000000"; --expX_uid6_fpSqrtTest(BITSELECT,5)@0 expX_uid6_fpSqrtTest_in <= a(62 downto 0); expX_uid6_fpSqrtTest_b <= expX_uid6_fpSqrtTest_in(62 downto 52); --expXIsZero_uid13_fpSqrtTest(LOGICAL,12)@0 expXIsZero_uid13_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b; expXIsZero_uid13_fpSqrtTest_b <= cstAllZWE_uid11_fpSqrtTest_q; expXIsZero_uid13_fpSqrtTest_q <= "1" when expXIsZero_uid13_fpSqrtTest_a = expXIsZero_uid13_fpSqrtTest_b else "0"; --negZero_uid56_fpSqrtTest(LOGICAL,55)@0 negZero_uid56_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q; negZero_uid56_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; negZero_uid56_fpSqrtTest_q_i <= negZero_uid56_fpSqrtTest_a and negZero_uid56_fpSqrtTest_b; negZero_uid56_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => negZero_uid56_fpSqrtTest_q, xin => negZero_uid56_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg(DELAY,425) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => negZero_uid56_fpSqrtTest_q, xout => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt(COUNTER,427) -- every=1, low=0, high=24, step=1, init=1 ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i = 23 THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '1'; ELSE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i - 24; ELSE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i,5)); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg(REG,428) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q; END IF; END IF; END PROCESS; --xIn(GPIN,3)@0 --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux(MUX,429) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s <= en; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux: PROCESS (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q) BEGIN CASE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s IS WHEN "0" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q; WHEN "1" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q; WHEN OTHERS => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem(DUALMEM,426) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 25, width_b => 1, widthad_b => 5, numwords_b => 25, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq, address_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa, data_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia ); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 <= areset; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq(0 downto 0); --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor(LOGICAL,422) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q <= not (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a or ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top(CONSTANT,405) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q <= "010111"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp(LOGICAL,406) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q <= "1" when ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a = ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b else "0"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg(REG,407) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena(REG,423) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q = "1") THEN ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd(LOGICAL,424) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b <= en; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a and ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b; --cstAllOWE_uid9_fpSqrtTest(CONSTANT,8) cstAllOWE_uid9_fpSqrtTest_q <= "11111111111"; --sBiasM1_uid28_fpSqrtTest(CONSTANT,27) sBiasM1_uid28_fpSqrtTest_q <= "01111111110"; --expOddSig_uid29_fpSqrtTest(ADD,28)@0 expOddSig_uid29_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b); expOddSig_uid29_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBiasM1_uid28_fpSqrtTest_q); expOddSig_uid29_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid29_fpSqrtTest_a) + UNSIGNED(expOddSig_uid29_fpSqrtTest_b)); expOddSig_uid29_fpSqrtTest_q <= expOddSig_uid29_fpSqrtTest_o(11 downto 0); --expROdd_uid30_fpSqrtTest(BITSELECT,29)@0 expROdd_uid30_fpSqrtTest_in <= expOddSig_uid29_fpSqrtTest_q; expROdd_uid30_fpSqrtTest_b <= expROdd_uid30_fpSqrtTest_in(11 downto 1); --sBias_uid25_fpSqrtTest(CONSTANT,24) sBias_uid25_fpSqrtTest_q <= "01111111111"; --expEvenSig_uid26_fpSqrtTest(ADD,25)@0 expEvenSig_uid26_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b); expEvenSig_uid26_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBias_uid25_fpSqrtTest_q); expEvenSig_uid26_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid26_fpSqrtTest_a) + UNSIGNED(expEvenSig_uid26_fpSqrtTest_b)); expEvenSig_uid26_fpSqrtTest_q <= expEvenSig_uid26_fpSqrtTest_o(11 downto 0); --expREven_uid27_fpSqrtTest(BITSELECT,26)@0 expREven_uid27_fpSqrtTest_in <= expEvenSig_uid26_fpSqrtTest_q; expREven_uid27_fpSqrtTest_b <= expREven_uid27_fpSqrtTest_in(11 downto 1); --expX0_uid31_fpSqrtTest(BITSELECT,30)@0 expX0_uid31_fpSqrtTest_in <= expX_uid6_fpSqrtTest_b(0 downto 0); expX0_uid31_fpSqrtTest_b <= expX0_uid31_fpSqrtTest_in(0 downto 0); --expOddSelect_uid32_fpSqrtTest(LOGICAL,31)@0 expOddSelect_uid32_fpSqrtTest_a <= expX0_uid31_fpSqrtTest_b; expOddSelect_uid32_fpSqrtTest_q <= not expOddSelect_uid32_fpSqrtTest_a; --expRMux_uid33_fpSqrtTest(MUX,32)@0 expRMux_uid33_fpSqrtTest_s <= expOddSelect_uid32_fpSqrtTest_q; expRMux_uid33_fpSqrtTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRMux_uid33_fpSqrtTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE expRMux_uid33_fpSqrtTest_s IS WHEN "0" => expRMux_uid33_fpSqrtTest_q <= expREven_uid27_fpSqrtTest_b; WHEN "1" => expRMux_uid33_fpSqrtTest_q <= expROdd_uid30_fpSqrtTest_b; WHEN OTHERS => expRMux_uid33_fpSqrtTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d(DELAY,248)@1 ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => expRMux_uid33_fpSqrtTest_q, xout => ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, ena => en(0), clk => clk, aclr => areset ); --ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b(DELAY,245)@0 ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signX_uid8_fpSqrtTest_b, xout => ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset ); --cstAllZWF_uid10_fpSqrtTest(CONSTANT,9) cstAllZWF_uid10_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000000"; --fracX_uid7_fpSqrtTest(BITSELECT,6)@0 fracX_uid7_fpSqrtTest_in <= a(51 downto 0); fracX_uid7_fpSqrtTest_b <= fracX_uid7_fpSqrtTest_in(51 downto 0); --fracXIsZero_uid17_fpSqrtTest(LOGICAL,16)@0 fracXIsZero_uid17_fpSqrtTest_a <= fracX_uid7_fpSqrtTest_b; fracXIsZero_uid17_fpSqrtTest_b <= cstAllZWF_uid10_fpSqrtTest_q; fracXIsZero_uid17_fpSqrtTest_q <= "1" when fracXIsZero_uid17_fpSqrtTest_a = fracXIsZero_uid17_fpSqrtTest_b else "0"; --InvFracXIsZero_uid19_fpSqrtTest(LOGICAL,18)@0 InvFracXIsZero_uid19_fpSqrtTest_a <= fracXIsZero_uid17_fpSqrtTest_q; InvFracXIsZero_uid19_fpSqrtTest_q <= not InvFracXIsZero_uid19_fpSqrtTest_a; --expXIsMax_uid15_fpSqrtTest(LOGICAL,14)@0 expXIsMax_uid15_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b; expXIsMax_uid15_fpSqrtTest_b <= cstAllOWE_uid9_fpSqrtTest_q; expXIsMax_uid15_fpSqrtTest_q <= "1" when expXIsMax_uid15_fpSqrtTest_a = expXIsMax_uid15_fpSqrtTest_b else "0"; --exc_N_uid20_fpSqrtTest(LOGICAL,19)@0 exc_N_uid20_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q; exc_N_uid20_fpSqrtTest_b <= InvFracXIsZero_uid19_fpSqrtTest_q; exc_N_uid20_fpSqrtTest_q <= exc_N_uid20_fpSqrtTest_a and exc_N_uid20_fpSqrtTest_b; --InvExc_N_uid21_fpSqrtTest(LOGICAL,20)@0 InvExc_N_uid21_fpSqrtTest_a <= exc_N_uid20_fpSqrtTest_q; InvExc_N_uid21_fpSqrtTest_q <= not InvExc_N_uid21_fpSqrtTest_a; --exc_I_uid18_fpSqrtTest(LOGICAL,17)@0 exc_I_uid18_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q; exc_I_uid18_fpSqrtTest_b <= fracXIsZero_uid17_fpSqrtTest_q; exc_I_uid18_fpSqrtTest_q <= exc_I_uid18_fpSqrtTest_a and exc_I_uid18_fpSqrtTest_b; --InvExc_I_uid22_fpSqrtTest(LOGICAL,21)@0 InvExc_I_uid22_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; InvExc_I_uid22_fpSqrtTest_q <= not InvExc_I_uid22_fpSqrtTest_a; --InvExpXIsZero_uid23_fpSqrtTest(LOGICAL,22)@0 InvExpXIsZero_uid23_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q; InvExpXIsZero_uid23_fpSqrtTest_q <= not InvExpXIsZero_uid23_fpSqrtTest_a; --exc_R_uid24_fpSqrtTest(LOGICAL,23)@0 exc_R_uid24_fpSqrtTest_a <= InvExpXIsZero_uid23_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_b <= InvExc_I_uid22_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_c <= InvExc_N_uid21_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_q <= exc_R_uid24_fpSqrtTest_a and exc_R_uid24_fpSqrtTest_b and exc_R_uid24_fpSqrtTest_c; --minReg_uid42_fpSqrtTest(LOGICAL,41)@0 minReg_uid42_fpSqrtTest_a <= exc_R_uid24_fpSqrtTest_q; minReg_uid42_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; minReg_uid42_fpSqrtTest_q_i <= minReg_uid42_fpSqrtTest_a and minReg_uid42_fpSqrtTest_b; minReg_uid42_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => minReg_uid42_fpSqrtTest_q, xin => minReg_uid42_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --minInf_uid43_fpSqrtTest(LOGICAL,42)@0 minInf_uid43_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; minInf_uid43_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; minInf_uid43_fpSqrtTest_q_i <= minInf_uid43_fpSqrtTest_a and minInf_uid43_fpSqrtTest_b; minInf_uid43_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => minInf_uid43_fpSqrtTest_q, xin => minInf_uid43_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1(REG,155)@0 reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= exc_N_uid20_fpSqrtTest_q; END IF; END IF; END PROCESS; --excRNaN_uid44_fpSqrtTest(LOGICAL,43)@1 excRNaN_uid44_fpSqrtTest_a <= reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q; excRNaN_uid44_fpSqrtTest_b <= minInf_uid43_fpSqrtTest_q; excRNaN_uid44_fpSqrtTest_c <= minReg_uid42_fpSqrtTest_q; excRNaN_uid44_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_a or excRNaN_uid44_fpSqrtTest_b or excRNaN_uid44_fpSqrtTest_c; --InvSignX_uid40_fpSqrtTest(LOGICAL,39)@0 InvSignX_uid40_fpSqrtTest_a <= signX_uid8_fpSqrtTest_b; InvSignX_uid40_fpSqrtTest_q <= not InvSignX_uid40_fpSqrtTest_a; --inInfAndNotNeg_uid41_fpSqrtTest(LOGICAL,40)@0 inInfAndNotNeg_uid41_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; inInfAndNotNeg_uid41_fpSqrtTest_b <= InvSignX_uid40_fpSqrtTest_q; inInfAndNotNeg_uid41_fpSqrtTest_q_i <= inInfAndNotNeg_uid41_fpSqrtTest_a and inInfAndNotNeg_uid41_fpSqrtTest_b; inInfAndNotNeg_uid41_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => inInfAndNotNeg_uid41_fpSqrtTest_q, xin => inInfAndNotNeg_uid41_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0(REG,156)@0 reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= expXIsZero_uid13_fpSqrtTest_q; END IF; END IF; END PROCESS; --join_uid45_fpSqrtTest(BITJOIN,44)@1 join_uid45_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_q & inInfAndNotNeg_uid41_fpSqrtTest_q & reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q; --fracSelIn_uid46_fpSqrtTest(BITJOIN,45)@1 fracSelIn_uid46_fpSqrtTest_q <= ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q & join_uid45_fpSqrtTest_q; --fracSel_uid47_fpSqrtTest(LOOKUP,46)@1 fracSel_uid47_fpSqrtTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracSel_uid47_fpSqrtTest_q <= "01"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN CASE (fracSelIn_uid46_fpSqrtTest_q) IS WHEN "0000" => fracSel_uid47_fpSqrtTest_q <= "01"; WHEN "0001" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0010" => fracSel_uid47_fpSqrtTest_q <= "10"; WHEN "0011" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0100" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "0101" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0110" => fracSel_uid47_fpSqrtTest_q <= "10"; WHEN "0111" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "1000" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1001" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "1010" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1011" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1100" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1101" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1110" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1111" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN OTHERS => fracSel_uid47_fpSqrtTest_q <= (others => '-'); END CASE; END IF; END IF; END PROCESS; --expRPostExc_uid51_fpSqrtTest(MUX,50)@2 expRPostExc_uid51_fpSqrtTest_s <= fracSel_uid47_fpSqrtTest_q; expRPostExc_uid51_fpSqrtTest: PROCESS (expRPostExc_uid51_fpSqrtTest_s, en, cstAllZWE_uid11_fpSqrtTest_q, ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, cstAllOWE_uid9_fpSqrtTest_q, cstAllOWE_uid9_fpSqrtTest_q) BEGIN CASE expRPostExc_uid51_fpSqrtTest_s IS WHEN "00" => expRPostExc_uid51_fpSqrtTest_q <= cstAllZWE_uid11_fpSqrtTest_q; WHEN "01" => expRPostExc_uid51_fpSqrtTest_q <= ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q; WHEN "10" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q; WHEN "11" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q; WHEN OTHERS => expRPostExc_uid51_fpSqrtTest_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg(DELAY,412) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => expRPostExc_uid51_fpSqrtTest_q, xout => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt(COUNTER,401) -- every=1, low=0, high=23, step=1, init=1 ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i = 22 THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '1'; ELSE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i - 23; ELSE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i,5)); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg(REG,402) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux(MUX,403) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux: PROCESS (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q) BEGIN CASE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s IS WHEN "0" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; WHEN "1" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q; WHEN OTHERS => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem(DUALMEM,413) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 5, numwords_a => 24, width_b => 11, widthad_b => 5, numwords_b => 24, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq, address_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa, data_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia ); ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 <= areset; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq(10 downto 0); --fracNaN_uid52_fpSqrtTest(CONSTANT,51) fracNaN_uid52_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000001"; --fracXAddr_uid35_fpSqrtTest(BITSELECT,34)@0 fracXAddr_uid35_fpSqrtTest_in <= fracX_uid7_fpSqrtTest_b; fracXAddr_uid35_fpSqrtTest_b <= fracXAddr_uid35_fpSqrtTest_in(51 downto 45); --addrTable_uid36_fpSqrtTest(BITJOIN,35)@0 addrTable_uid36_fpSqrtTest_q <= expOddSelect_uid32_fpSqrtTest_q & fracXAddr_uid35_fpSqrtTest_b; --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0(REG,161)@0 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= addrTable_uid36_fpSqrtTest_q; END IF; END IF; END PROCESS; --memoryC5_uid71_sqrtTableGenerator_lutmem(DUALMEM,139)@1 memoryC5_uid71_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC5_uid71_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC5_uid71_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q; memoryC5_uid71_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 17, widthad_a => 8, numwords_a => 256, width_b => 17, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC5_uid71_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC5_uid71_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC5_uid71_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC5_uid71_sqrtTableGenerator_lutmem_iq, address_a => memoryC5_uid71_sqrtTableGenerator_lutmem_aa, data_a => memoryC5_uid71_sqrtTableGenerator_lutmem_ia ); memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC5_uid71_sqrtTableGenerator_lutmem_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_iq(16 downto 0); --reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1(REG,163)@3 reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg(DELAY,398) ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg : dspba_delay GENERIC MAP ( width => 52, depth => 1 ) PORT MAP ( xin => fracX_uid7_fpSqrtTest_b, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a(DELAY,229)@0 ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a : dspba_delay GENERIC MAP ( width => 52, depth => 2 ) PORT MAP ( xin => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset ); --FracX44dto0_uid37_fpSqrtTest(BITSELECT,36)@3 FracX44dto0_uid37_fpSqrtTest_in <= ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q(44 downto 0); FracX44dto0_uid37_fpSqrtTest_b <= FracX44dto0_uid37_fpSqrtTest_in(44 downto 0); --yT1_uid73_sqrtPolynomialEvaluator(BITSELECT,72)@3 yT1_uid73_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT1_uid73_sqrtPolynomialEvaluator_b <= yT1_uid73_sqrtPolynomialEvaluator_in(44 downto 28); --reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0(REG,162)@3 reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= yT1_uid73_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator(MULT,103)@4 prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a),18)) * SIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr,34)); END IF; END IF; END PROCESS; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator(BITSELECT,104)@7 prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in(33 downto 16); --highBBits_uid76_sqrtPolynomialEvaluator(BITSELECT,75)@7 highBBits_uid76_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b; highBBits_uid76_sqrtPolynomialEvaluator_b <= highBBits_uid76_sqrtPolynomialEvaluator_in(17 downto 1); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a(DELAY,363)@0 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0(REG,164)@3 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q; END IF; END IF; END PROCESS; --memoryC4_uid69_sqrtTableGenerator_lutmem(DUALMEM,138)@4 memoryC4_uid69_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC4_uid69_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC4_uid69_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q; memoryC4_uid69_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 8, numwords_a => 256, width_b => 24, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC4_uid69_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC4_uid69_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC4_uid69_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC4_uid69_sqrtTableGenerator_lutmem_iq, address_a => memoryC4_uid69_sqrtTableGenerator_lutmem_aa, data_a => memoryC4_uid69_sqrtTableGenerator_lutmem_ia ); memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC4_uid69_sqrtTableGenerator_lutmem_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_iq(23 downto 0); --reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0(REG,165)@6 reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid77_sqrtPolynomialEvaluator(ADD,76)@7 sumAHighB_uid77_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((24 downto 24 => reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q(23)) & reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q); sumAHighB_uid77_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((24 downto 17 => highBBits_uid76_sqrtPolynomialEvaluator_b(16)) & highBBits_uid76_sqrtPolynomialEvaluator_b); sumAHighB_uid77_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_b)); sumAHighB_uid77_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_o(24 downto 0); --lowRangeB_uid75_sqrtPolynomialEvaluator(BITSELECT,74)@7 lowRangeB_uid75_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid75_sqrtPolynomialEvaluator_b <= lowRangeB_uid75_sqrtPolynomialEvaluator_in(0 downto 0); --s1_uid75_uid78_sqrtPolynomialEvaluator(BITJOIN,77)@7 s1_uid75_uid78_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_q & lowRangeB_uid75_sqrtPolynomialEvaluator_b; --reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1(REG,167)@7 reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= s1_uid75_uid78_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor(LOGICAL,459) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a or ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg(REG,457) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= VCC_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena(REG,460) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,461) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b <= en; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b; --yT2_uid79_sqrtPolynomialEvaluator(BITSELECT,78)@3 yT2_uid79_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT2_uid79_sqrtPolynomialEvaluator_b <= yT2_uid79_sqrtPolynomialEvaluator_in(44 downto 21); --reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0(REG,166)@3 reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= yT2_uid79_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg(DELAY,451) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg : dspba_delay GENERIC MAP ( width => 24, depth => 1 ) PORT MAP ( xin => reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q, xout => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,453) -- every=1, low=0, high=1, step=1, init=1 ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i,1)); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg(REG,454) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,455) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q) BEGIN CASE ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s IS WHEN "0" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q; WHEN "1" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,452) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 1, numwords_a => 2, width_b => 24, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq, address_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa, data_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia ); ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq(23 downto 0); --prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator(MULT,106)@8 prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a),25)) * SIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr,50)); END IF; END IF; END PROCESS; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator(BITSELECT,107)@11 prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in(49 downto 23); --highBBits_uid82_sqrtPolynomialEvaluator(BITSELECT,81)@11 highBBits_uid82_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b; highBBits_uid82_sqrtPolynomialEvaluator_b <= highBBits_uid82_sqrtPolynomialEvaluator_in(26 downto 1); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor(LOGICAL,485) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,481) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q <= "0100"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,482) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b else "0"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg(REG,483) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena(REG,486) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,487) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg(DELAY,462) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q, xout => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,477) -- every=1, low=0, high=4, step=1, init=1 ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 3 THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 4; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,3)); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,478) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,479) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q) BEGIN CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q; WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,476) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 5, width_b => 8, widthad_b => 3, numwords_b => 5, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq, address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa, data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia ); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0); --memoryC3_uid67_sqrtTableGenerator_lutmem(DUALMEM,137)@8 memoryC3_uid67_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC3_uid67_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC3_uid67_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q; memoryC3_uid67_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 33, widthad_a => 8, numwords_a => 256, width_b => 33, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC3_uid67_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC3_uid67_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC3_uid67_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC3_uid67_sqrtTableGenerator_lutmem_iq, address_a => memoryC3_uid67_sqrtTableGenerator_lutmem_aa, data_a => memoryC3_uid67_sqrtTableGenerator_lutmem_ia ); memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC3_uid67_sqrtTableGenerator_lutmem_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_iq(32 downto 0); --reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0(REG,169)@10 reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid83_sqrtPolynomialEvaluator(ADD,82)@11 sumAHighB_uid83_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((33 downto 33 => reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q(32)) & reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q); sumAHighB_uid83_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((33 downto 26 => highBBits_uid82_sqrtPolynomialEvaluator_b(25)) & highBBits_uid82_sqrtPolynomialEvaluator_b); sumAHighB_uid83_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_b)); sumAHighB_uid83_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_o(33 downto 0); --lowRangeB_uid81_sqrtPolynomialEvaluator(BITSELECT,80)@11 lowRangeB_uid81_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid81_sqrtPolynomialEvaluator_b <= lowRangeB_uid81_sqrtPolynomialEvaluator_in(0 downto 0); --s2_uid81_uid84_sqrtPolynomialEvaluator(BITJOIN,83)@11 s2_uid81_uid84_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_q & lowRangeB_uid81_sqrtPolynomialEvaluator_b; --reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1(REG,171)@11 reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= s2_uid81_uid84_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor(LOGICAL,524) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q <= not (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a or ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top(CONSTANT,520) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q <= "0101"; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp(LOGICAL,521) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q <= "1" when ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a = ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b else "0"; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg(REG,522) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena(REG,525) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd(LOGICAL,526) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b <= en; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a and ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b; --yT3_uid85_sqrtPolynomialEvaluator(BITSELECT,84)@3 yT3_uid85_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT3_uid85_sqrtPolynomialEvaluator_b <= yT3_uid85_sqrtPolynomialEvaluator_in(44 downto 12); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg(DELAY,514) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg : dspba_delay GENERIC MAP ( width => 33, depth => 1 ) PORT MAP ( xin => yT3_uid85_sqrtPolynomialEvaluator_b, xout => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt(COUNTER,516) -- every=1, low=0, high=5, step=1, init=1 ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i = 4 THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i - 5; ELSE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i,3)); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg(REG,517) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux(MUX,518) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s <= en; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux: PROCESS (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q) BEGIN CASE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s IS WHEN "0" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; WHEN "1" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem(DUALMEM,515) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 33, widthad_a => 3, numwords_a => 6, width_b => 33, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq, address_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa, data_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia ); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 <= areset; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq(32 downto 0); --reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0(REG,170)@11 reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q; END IF; END IF; END PROCESS; --prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator(MULT,109)@12 prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a),34)) * SIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr,68)); END IF; END IF; END PROCESS; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator(BITSELECT,110)@15 prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in(67 downto 34); --highBBits_uid88_sqrtPolynomialEvaluator(BITSELECT,87)@15 highBBits_uid88_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b; highBBits_uid88_sqrtPolynomialEvaluator_b <= highBBits_uid88_sqrtPolynomialEvaluator_in(33 downto 1); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,537) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,533) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01000"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,534) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b else "0"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,535) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,538) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,539) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,501) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,529) -- every=1, low=0, high=8, step=1, init=1 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 7 THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1'; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 8; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4)); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,530) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,531) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q) BEGIN CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,528) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 9, width_b => 8, widthad_b => 4, numwords_b => 9, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0(REG,172)@11 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC2_uid65_sqrtTableGenerator_lutmem(DUALMEM,136)@12 memoryC2_uid65_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC2_uid65_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC2_uid65_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q; memoryC2_uid65_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC2_uid65_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid65_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid65_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid65_sqrtTableGenerator_lutmem_iq, address_a => memoryC2_uid65_sqrtTableGenerator_lutmem_aa, data_a => memoryC2_uid65_sqrtTableGenerator_lutmem_ia ); memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC2_uid65_sqrtTableGenerator_lutmem_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0(REG,173)@14 reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid89_sqrtPolynomialEvaluator(ADD,88)@15 sumAHighB_uid89_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q(39)) & reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q); sumAHighB_uid89_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((40 downto 33 => highBBits_uid88_sqrtPolynomialEvaluator_b(32)) & highBBits_uid88_sqrtPolynomialEvaluator_b); sumAHighB_uid89_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_b)); sumAHighB_uid89_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_o(40 downto 0); --lowRangeB_uid87_sqrtPolynomialEvaluator(BITSELECT,86)@15 lowRangeB_uid87_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid87_sqrtPolynomialEvaluator_b <= lowRangeB_uid87_sqrtPolynomialEvaluator_in(0 downto 0); --s3_uid87_uid90_sqrtPolynomialEvaluator(BITJOIN,89)@15 s3_uid87_uid90_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_q & lowRangeB_uid87_sqrtPolynomialEvaluator_b; --yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,118)@15 yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q; yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 24); --reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9(REG,177)@15 reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor(LOGICAL,448) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top(CONSTANT,444) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q <= "01001"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp(LOGICAL,445) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b else "0"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg(REG,446) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena(REG,449) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,450) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg(DELAY,438) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => FracX44dto0_uid37_fpSqrtTest_b, xout => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,440) -- every=1, low=0, high=9, step=1, init=1 ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 8 THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1'; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 9; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i,4)); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg(REG,441) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,442) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q) BEGIN CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s IS WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q; WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q; WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,439) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 10, width_b => 45, widthad_b => 4, numwords_b => 10, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0, clock1 => clk, address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq, address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa, data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia ); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq(44 downto 0); --yT4_uid91_sqrtPolynomialEvaluator(BITSELECT,90)@15 yT4_uid91_sqrtPolynomialEvaluator_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q; yT4_uid91_sqrtPolynomialEvaluator_b <= yT4_uid91_sqrtPolynomialEvaluator_in(44 downto 5); --xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,117)@15 xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b(12 downto 0); xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in(12 downto 0); --GND(CONSTANT,0) GND_q <= "0"; --pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,120)@15 pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7(REG,176)@15 reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,116)@15 yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q(14 downto 0); yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b <= yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in(14 downto 0); --spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,119)@15 spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q <= GND_q & yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b; --pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,121)@15 pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q <= spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q & STD_LOGIC_VECTOR((1 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6(REG,175)@15 reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,115)@15 xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b; xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 22); --reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4(REG,174)@15 reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma(CHAINMULTADD,140)@16 multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0),19)); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1),19)); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0) <= RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0),38) + RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1),38); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a <= (others => (others => '0')); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c <= (others => (others => '0')); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q),18); IF (en = "1") THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0); END IF; END IF; END PROCESS; multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_delay : dspba_delay GENERIC MAP (width => 37, depth => 1) PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q, clk => clk, aclr => areset); --multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,123)@19 multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q; multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in(36 downto 2); --highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,125)@19 highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b; highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b <= highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in(34 downto 6); --yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,113)@15 yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q; yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 15); --reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1(REG,179)@15 reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,112)@15 xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b; xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 13); --reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0(REG,178)@15 reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator(MULT,114)@16 topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a),28)) * SIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= (others => '0'); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= (others => '0'); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr,54)); END IF; END IF; END PROCESS; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator(ADD,126)@19 sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q(53)) & topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b(28)) & highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b)); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o(54 downto 0); --lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,124)@19 lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b(5 downto 0); lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b <= lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in(5 downto 0); --add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,127)@19 add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q & lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b; --R_uid129_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,128)@19 R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in <= add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q(59 downto 0); R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in(59 downto 17); --reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1(REG,181)@19 reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= "0000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,511) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,507) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01100"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,508) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b else "0"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,509) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,512) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,513) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,503) -- every=1, low=0, high=12, step=1, init=1 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 11 THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1'; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 12; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4)); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,504) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,505) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q) BEGIN CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,502) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 13, width_b => 8, widthad_b => 4, numwords_b => 13, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0(REG,157)@15 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC1_uid63_sqrtTableGenerator_lutmem(DUALMEM,135)@16 memoryC1_uid63_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid63_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid63_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q; memoryC1_uid63_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 9, widthad_a => 8, numwords_a => 256, width_b => 9, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC1_uid63_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid63_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid63_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid63_sqrtTableGenerator_lutmem_iq, address_a => memoryC1_uid63_sqrtTableGenerator_lutmem_aa, data_a => memoryC1_uid63_sqrtTableGenerator_lutmem_ia ); memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC1_uid63_sqrtTableGenerator_lutmem_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_iq(8 downto 0); --reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1(REG,160)@18 reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= "000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --memoryC1_uid62_sqrtTableGenerator_lutmem(DUALMEM,134)@16 memoryC1_uid62_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid62_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid62_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q; memoryC1_uid62_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC1_uid62_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid62_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid62_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid62_sqrtTableGenerator_lutmem_iq, address_a => memoryC1_uid62_sqrtTableGenerator_lutmem_aa, data_a => memoryC1_uid62_sqrtTableGenerator_lutmem_ia ); memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC1_uid62_sqrtTableGenerator_lutmem_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0(REG,159)@18 reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --os_uid64_sqrtTableGenerator(BITJOIN,63)@19 os_uid64_sqrtTableGenerator_q <= reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q & reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q; --rndBit_uid93_sqrtPolynomialEvaluator(CONSTANT,92) rndBit_uid93_sqrtPolynomialEvaluator_q <= "01"; --cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator(BITJOIN,93)@19 cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q <= os_uid64_sqrtTableGenerator_q & rndBit_uid93_sqrtPolynomialEvaluator_q; --reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0(REG,180)@19 reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ts4_uid95_sqrtPolynomialEvaluator(ADD,94)@20 ts4_uid95_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((51 downto 51 => reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q(50)) & reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q); ts4_uid95_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((51 downto 43 => reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q(42)) & reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q); ts4_uid95_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid95_sqrtPolynomialEvaluator_a) + SIGNED(ts4_uid95_sqrtPolynomialEvaluator_b)); ts4_uid95_sqrtPolynomialEvaluator_q <= ts4_uid95_sqrtPolynomialEvaluator_o(51 downto 0); --s4_uid96_sqrtPolynomialEvaluator(BITSELECT,95)@20 s4_uid96_sqrtPolynomialEvaluator_in <= ts4_uid95_sqrtPolynomialEvaluator_q; s4_uid96_sqrtPolynomialEvaluator_b <= s4_uid96_sqrtPolynomialEvaluator_in(51 downto 1); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1(BITSELECT,144)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in <= STD_LOGIC_VECTOR((53 downto 51 => s4_uid96_sqrtPolynomialEvaluator_b(50)) & s4_uid96_sqrtPolynomialEvaluator_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in(53 downto 27); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1(REG,187)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor(LOGICAL,498) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top(CONSTANT,494) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q <= "01110"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp(LOGICAL,495) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b else "0"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg(REG,496) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena(REG,499) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd(LOGICAL,500) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt(COUNTER,490) -- every=1, low=0, high=14, step=1, init=1 ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i = 13 THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '1'; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i - 14; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i,4)); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg(REG,491) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux(MUX,492) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q) BEGIN CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s IS WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q; WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q; WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem(DUALMEM,489) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 15, width_b => 45, widthad_b => 4, numwords_b => 15, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq, address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa, data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia ); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 <= areset; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq(44 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1(BITSELECT,142)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in <= STD_LOGIC_VECTOR("000000000" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in(53 downto 27); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0(REG,184)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1(MULT,148)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr,54)); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1; END IF; END IF; END PROCESS; --ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a(DELAY,349)@24 ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a : dspba_delay GENERIC MAP ( width => 54, depth => 2 ) PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q, ena => en(0), clk => clk, aclr => areset ); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2(BITSHIFT,152)@26 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q & "000000000000000000000000000000000000000000000000000000"; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int(107 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0(BITSELECT,141)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q(26 downto 0); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in(26 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0(REG,182)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1(MULT,147)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr,54)); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0(BITSELECT,143)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in <= s4_uid96_sqrtPolynomialEvaluator_b(26 downto 0); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in(26 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1(REG,183)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0(MULT,146)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0(ADD,149)@24 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR('0' & "00" & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR((56 downto 54 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q(53)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b)); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o(55 downto 0); --ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a(DELAY,348)@24 ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a : dspba_delay GENERIC MAP ( width => 56, depth => 1 ) PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q, ena => en(0), clk => clk, aclr => areset ); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1(BITSHIFT,151)@25 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q & "000000000000000000000000000"; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int(82 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0(MULT,145)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0(BITSHIFT,150)@24 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int(53 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0(REG,188)@24 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0(ADD,153)@25 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q(82)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b)); END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o(83 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0(ADD,154)@26 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a <= STD_LOGIC_VECTOR((108 downto 84 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q(83)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b <= STD_LOGIC_VECTOR((108 downto 108 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q(107)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b)); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o(108 downto 0); --prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator(BITSELECT,130)@26 prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q(95 downto 0); prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in(95 downto 44); --highBBits_uid100_sqrtPolynomialEvaluator(BITSELECT,99)@26 highBBits_uid100_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b; highBBits_uid100_sqrtPolynomialEvaluator_b <= highBBits_uid100_sqrtPolynomialEvaluator_in(51 downto 2); --reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1(REG,196)@26 reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= highBBits_uid100_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor(LOGICAL,472) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,468) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q <= "010011"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,469) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b else "0"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg(REG,470) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena(REG,473) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,474) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,464) -- every=1, low=0, high=19, step=1, init=1 ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 18 THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 19; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,5)); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,465) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,466) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q) BEGIN CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,463) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 5, numwords_a => 20, width_b => 8, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq, address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa, data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia ); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0); --memoryC0_uid60_sqrtTableGenerator_lutmem(DUALMEM,133)@23 memoryC0_uid60_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid60_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid60_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q; memoryC0_uid60_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 17, widthad_a => 8, numwords_a => 256, width_b => 17, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC0_uid60_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid60_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid60_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid60_sqrtTableGenerator_lutmem_iq, address_a => memoryC0_uid60_sqrtTableGenerator_lutmem_aa, data_a => memoryC0_uid60_sqrtTableGenerator_lutmem_ia ); memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC0_uid60_sqrtTableGenerator_lutmem_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_iq(16 downto 0); --reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1(REG,194)@25 reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,550) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,551) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,552) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,541) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 5, numwords_a => 20, width_b => 8, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0(REG,191)@22 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC0_uid59_sqrtTableGenerator_lutmem(DUALMEM,132)@23 memoryC0_uid59_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid59_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid59_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q; memoryC0_uid59_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC0_uid59_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid59_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid59_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid59_sqrtTableGenerator_lutmem_iq, address_a => memoryC0_uid59_sqrtTableGenerator_lutmem_aa, data_a => memoryC0_uid59_sqrtTableGenerator_lutmem_ia ); memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC0_uid59_sqrtTableGenerator_lutmem_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0(REG,193)@25 reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --os_uid61_sqrtTableGenerator(BITJOIN,60)@26 os_uid61_sqrtTableGenerator_q <= reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q & reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q; --reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0(REG,195)@26 reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= os_uid61_sqrtTableGenerator_q; END IF; END IF; END PROCESS; --sumAHighB_uid101_sqrtPolynomialEvaluator(ADD,100)@27 sumAHighB_uid101_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((57 downto 57 => reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q(56)) & reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q); sumAHighB_uid101_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((57 downto 50 => reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q(49)) & reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q); sumAHighB_uid101_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_b)); sumAHighB_uid101_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_o(57 downto 0); --lowRangeB_uid99_sqrtPolynomialEvaluator(BITSELECT,98)@26 lowRangeB_uid99_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b(1 downto 0); lowRangeB_uid99_sqrtPolynomialEvaluator_b <= lowRangeB_uid99_sqrtPolynomialEvaluator_in(1 downto 0); --reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0(REG,197)@26 reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= lowRangeB_uid99_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --s5_uid99_uid102_sqrtPolynomialEvaluator(BITJOIN,101)@27 s5_uid99_uid102_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_q & reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q; --fracR_uid39_fpSqrtTest(BITSELECT,38)@27 fracR_uid39_fpSqrtTest_in <= s5_uid99_uid102_sqrtPolynomialEvaluator_q(56 downto 0); fracR_uid39_fpSqrtTest_b <= fracR_uid39_fpSqrtTest_in(56 downto 5); --reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3(REG,198)@27 reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= "0000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= fracR_uid39_fpSqrtTest_b; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor(LOGICAL,409) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q <= not (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a or ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena(REG,410) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd(LOGICAL,411) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a and ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg(DELAY,399) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => fracSel_uid47_fpSqrtTest_q, xout => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem(DUALMEM,400) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 2, widthad_a => 5, numwords_a => 24, width_b => 2, widthad_b => 5, numwords_b => 24, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq, address_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa, data_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia ); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 <= areset; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq(1 downto 0); --fracRPostExc_uid55_fpSqrtTest(MUX,54)@28 fracRPostExc_uid55_fpSqrtTest_s <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q; fracRPostExc_uid55_fpSqrtTest: PROCESS (fracRPostExc_uid55_fpSqrtTest_s, en, cstAllZWF_uid10_fpSqrtTest_q, reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q, cstAllZWF_uid10_fpSqrtTest_q, fracNaN_uid52_fpSqrtTest_q) BEGIN CASE fracRPostExc_uid55_fpSqrtTest_s IS WHEN "00" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q; WHEN "01" => fracRPostExc_uid55_fpSqrtTest_q <= reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q; WHEN "10" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q; WHEN "11" => fracRPostExc_uid55_fpSqrtTest_q <= fracNaN_uid52_fpSqrtTest_q; WHEN OTHERS => fracRPostExc_uid55_fpSqrtTest_q <= (others => '0'); END CASE; END PROCESS; --RSqrt_uid57_fpSqrtTest(BITJOIN,56)@28 RSqrt_uid57_fpSqrtTest_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q & ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q & fracRPostExc_uid55_fpSqrtTest_q; --xOut(GPOUT,4)@28 q <= RSqrt_uid57_fpSqrtTest_q; end normal;
----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Release Version 13.1 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from fp_sqrt_double_s5 -- VHDL created on Tue Apr 9 15:17:30 2013 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; entity fp_sqrt_double_s5 is port ( a : in std_logic_vector(63 downto 0); en : in std_logic_vector(0 downto 0); q : out std_logic_vector(63 downto 0); clk : in std_logic; areset : in std_logic ); end; architecture normal of fp_sqrt_double_s5 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstAllOWE_uid9_fpSqrtTest_q : std_logic_vector (10 downto 0); signal cstAllZWF_uid10_fpSqrtTest_q : std_logic_vector (51 downto 0); signal cstAllZWE_uid11_fpSqrtTest_q : std_logic_vector (10 downto 0); signal sBias_uid25_fpSqrtTest_q : std_logic_vector (10 downto 0); signal sBiasM1_uid28_fpSqrtTest_q : std_logic_vector (10 downto 0); signal expRMux_uid33_fpSqrtTest_s : std_logic_vector (0 downto 0); signal expRMux_uid33_fpSqrtTest_q : std_logic_vector (10 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_a : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_b : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_q : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_a : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_b : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_q : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_a : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_b : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_q : std_logic_vector(0 downto 0); signal fracSel_uid47_fpSqrtTest_q : std_logic_vector(1 downto 0); signal fracNaN_uid52_fpSqrtTest_q : std_logic_vector (51 downto 0); signal negZero_uid56_fpSqrtTest_a : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_b : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_q : std_logic_vector(0 downto 0); signal rndBit_uid93_sqrtPolynomialEvaluator_q : std_logic_vector (1 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a : std_logic_vector (16 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 : std_logic_vector (33 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr : SIGNED (34 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a : std_logic_vector (23 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 : std_logic_vector (49 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr : SIGNED (50 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q : std_logic_vector (49 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a : std_logic_vector (32 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 : std_logic_vector (67 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr : SIGNED (68 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q : std_logic_vector (67 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector (26 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 : std_logic_vector (53 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr : SIGNED (54 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (53 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid59_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid60_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid62_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid63_sqrtTableGenerator_lutmem_ia : std_logic_vector (8 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_iq : std_logic_vector (8 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_q : std_logic_vector (8 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC2_uid65_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC3_uid67_sqrtTableGenerator_lutmem_ia : std_logic_vector (32 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_iq : std_logic_vector (32 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_q : std_logic_vector (32 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC4_uid69_sqrtTableGenerator_lutmem_ia : std_logic_vector (23 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_iq : std_logic_vector (23 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_q : std_logic_vector (23 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC5_uid71_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0); type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type; attribute preserve : boolean; attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : signal is true; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type is array(0 to 1) of SIGNED(17 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type; attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : signal is true; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type is array(0 to 1) of SIGNED(18 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type is array(0 to 1) of SIGNED(36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type; signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s0 : std_logic_vector(36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q : std_logic_vector (36 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr : UNSIGNED (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr : UNSIGNED (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr : SIGNED (54 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr : SIGNED (54 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a : std_logic_vector(84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b : std_logic_vector(84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o : std_logic_vector (84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q : std_logic_vector (83 downto 0); signal reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q : std_logic_vector (0 downto 0); signal reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q : std_logic_vector (0 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0); signal reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q : std_logic_vector (8 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q : std_logic_vector (16 downto 0); signal reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q : std_logic_vector (16 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0); signal reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0); signal reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q : std_logic_vector (25 downto 0); signal reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0); signal reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0); signal reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q : std_logic_vector (34 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q : std_logic_vector (39 downto 0); signal reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q : std_logic_vector (17 downto 0); signal reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q : std_logic_vector (17 downto 0); signal reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q : std_logic_vector (16 downto 0); signal reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q : std_logic_vector (17 downto 0); signal reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q : std_logic_vector (26 downto 0); signal reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q : std_logic_vector (50 downto 0); signal reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q : std_logic_vector (42 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q : std_logic_vector (53 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0); signal reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q : std_logic_vector (16 downto 0); signal reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q : std_logic_vector (56 downto 0); signal reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q : std_logic_vector (49 downto 0); signal reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q : std_logic_vector (1 downto 0); signal reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q : std_logic_vector (51 downto 0); signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q : std_logic_vector (51 downto 0); signal ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q : std_logic_vector (0 downto 0); signal ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q : std_logic_vector (10 downto 0); signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q : std_logic_vector (55 downto 0); signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q : std_logic_vector (53 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0); signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q : std_logic_vector (51 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 : std_logic; signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq : std_logic; signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : signal is true; signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 : std_logic; signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : signal is true; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 : std_logic; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i : unsigned(4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq : std_logic; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q : std_logic_vector (5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : signal is true; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true; signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic; signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 : std_logic; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq : std_logic; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a : std_logic_vector(56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b : std_logic_vector(56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o : std_logic_vector (56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q : std_logic_vector (55 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal expX_uid6_fpSqrtTest_in : std_logic_vector (62 downto 0); signal expX_uid6_fpSqrtTest_b : std_logic_vector (10 downto 0); signal fracX_uid7_fpSqrtTest_in : std_logic_vector (51 downto 0); signal fracX_uid7_fpSqrtTest_b : std_logic_vector (51 downto 0); signal signX_uid8_fpSqrtTest_in : std_logic_vector (63 downto 0); signal signX_uid8_fpSqrtTest_b : std_logic_vector (0 downto 0); signal expXIsZero_uid13_fpSqrtTest_a : std_logic_vector(10 downto 0); signal expXIsZero_uid13_fpSqrtTest_b : std_logic_vector(10 downto 0); signal expXIsZero_uid13_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid15_fpSqrtTest_a : std_logic_vector(10 downto 0); signal expXIsMax_uid15_fpSqrtTest_b : std_logic_vector(10 downto 0); signal expXIsMax_uid15_fpSqrtTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid17_fpSqrtTest_a : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSqrtTest_b : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSqrtTest_q : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expEvenSig_uid26_fpSqrtTest_a : std_logic_vector(11 downto 0); signal expEvenSig_uid26_fpSqrtTest_b : std_logic_vector(11 downto 0); signal expEvenSig_uid26_fpSqrtTest_o : std_logic_vector (11 downto 0); signal expEvenSig_uid26_fpSqrtTest_q : std_logic_vector (11 downto 0); signal expOddSig_uid29_fpSqrtTest_a : std_logic_vector(11 downto 0); signal expOddSig_uid29_fpSqrtTest_b : std_logic_vector(11 downto 0); signal expOddSig_uid29_fpSqrtTest_o : std_logic_vector (11 downto 0); signal expOddSig_uid29_fpSqrtTest_q : std_logic_vector (11 downto 0); signal excRNaN_uid44_fpSqrtTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expRPostExc_uid51_fpSqrtTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid51_fpSqrtTest_q : std_logic_vector (10 downto 0); signal fracRPostExc_uid55_fpSqrtTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid55_fpSqrtTest_q : std_logic_vector (51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_a : std_logic_vector(51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_b : std_logic_vector(51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_o : std_logic_vector (51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_q : std_logic_vector (51 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_a : std_logic_vector(57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_b : std_logic_vector(57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_o : std_logic_vector (57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_q : std_logic_vector (57 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal join_uid45_fpSqrtTest_q : std_logic_vector (2 downto 0); signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0); signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in : std_logic_vector (49 downto 0); signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in : std_logic_vector (67 downto 0); signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (33 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q : std_logic_vector (53 downto 0); signal os_uid64_sqrtTableGenerator_q : std_logic_vector (48 downto 0); signal os_uid61_sqrtTableGenerator_q : std_logic_vector (56 downto 0); signal s5_uid99_uid102_sqrtPolynomialEvaluator_q : std_logic_vector (59 downto 0); signal FracX44dto0_uid37_fpSqrtTest_in : std_logic_vector (44 downto 0); signal FracX44dto0_uid37_fpSqrtTest_b : std_logic_vector (44 downto 0); signal fracSelIn_uid46_fpSqrtTest_q : std_logic_vector (3 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int : std_logic_vector (82 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q : std_logic_vector (82 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int : std_logic_vector (107 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q : std_logic_vector (107 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0); signal RSqrt_uid57_fpSqrtTest_q : std_logic_vector (63 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a : std_logic_vector(5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b : std_logic_vector(5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q : std_logic_vector(0 downto 0); signal yT4_uid91_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT4_uid91_sqrtPolynomialEvaluator_b : std_logic_vector (39 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b : std_logic_vector (26 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a : std_logic_vector(3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b : std_logic_vector(3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal expX0_uid31_fpSqrtTest_in : std_logic_vector (0 downto 0); signal expX0_uid31_fpSqrtTest_b : std_logic_vector (0 downto 0); signal fracXAddr_uid35_fpSqrtTest_in : std_logic_vector (51 downto 0); signal fracXAddr_uid35_fpSqrtTest_b : std_logic_vector (6 downto 0); signal InvSignX_uid40_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvSignX_uid40_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid22_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid22_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expREven_uid27_fpSqrtTest_in : std_logic_vector (11 downto 0); signal expREven_uid27_fpSqrtTest_b : std_logic_vector (10 downto 0); signal expROdd_uid30_fpSqrtTest_in : std_logic_vector (11 downto 0); signal expROdd_uid30_fpSqrtTest_b : std_logic_vector (10 downto 0); signal s4_uid96_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0); signal s4_uid96_sqrtPolynomialEvaluator_b : std_logic_vector (50 downto 0); signal lowRangeB_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid76_sqrtPolynomialEvaluator_in : std_logic_vector (17 downto 0); signal highBBits_uid76_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal lowRangeB_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid82_sqrtPolynomialEvaluator_in : std_logic_vector (26 downto 0); signal highBBits_uid82_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0); signal lowRangeB_uid87_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid87_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid88_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0); signal highBBits_uid88_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0); signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (5 downto 0); signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (5 downto 0); signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (34 downto 0); signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (28 downto 0); signal cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q : std_logic_vector (50 downto 0); signal fracR_uid39_fpSqrtTest_in : std_logic_vector (56 downto 0); signal fracR_uid39_fpSqrtTest_b : std_logic_vector (51 downto 0); signal yT1_uid73_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT1_uid73_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal yT2_uid79_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT2_uid79_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0); signal yT3_uid85_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT3_uid85_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a : std_logic_vector(108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b : std_logic_vector(108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o : std_logic_vector (108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q : std_logic_vector (108 downto 0); signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0); signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0); signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0); signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0); signal expOddSelect_uid32_fpSqrtTest_a : std_logic_vector(0 downto 0); signal expOddSelect_uid32_fpSqrtTest_q : std_logic_vector(0 downto 0); signal addrTable_uid36_fpSqrtTest_q : std_logic_vector (7 downto 0); signal exc_N_uid20_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_N_uid20_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_N_uid20_fpSqrtTest_q : std_logic_vector(0 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b : std_logic_vector (26 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_a : std_logic_vector(24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_b : std_logic_vector(24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_o : std_logic_vector (24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_q : std_logic_vector (24 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_a : std_logic_vector(33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_b : std_logic_vector(33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_o : std_logic_vector (33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_a : std_logic_vector(40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_b : std_logic_vector(40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_o : std_logic_vector (40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_q : std_logic_vector (40 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector(54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector(54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o : std_logic_vector (54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (54 downto 0); signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in : std_logic_vector (95 downto 0); signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b : std_logic_vector (51 downto 0); signal pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (16 downto 0); signal InvExc_N_uid21_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid21_fpSqrtTest_q : std_logic_vector(0 downto 0); signal s1_uid75_uid78_sqrtPolynomialEvaluator_q : std_logic_vector (25 downto 0); signal s2_uid81_uid84_sqrtPolynomialEvaluator_q : std_logic_vector (34 downto 0); signal s3_uid87_uid90_sqrtPolynomialEvaluator_q : std_logic_vector (41 downto 0); signal add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (60 downto 0); signal lowRangeB_uid99_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0); signal lowRangeB_uid99_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0); signal highBBits_uid100_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0); signal highBBits_uid100_sqrtPolynomialEvaluator_b : std_logic_vector (49 downto 0); signal exc_R_uid24_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_c : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_q : std_logic_vector(0 downto 0); signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0); signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (14 downto 0); signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (14 downto 0); signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0); signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (59 downto 0); signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (42 downto 0); signal spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (15 downto 0); signal pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (17 downto 0); begin --VCC(CONSTANT,1) VCC_q <= "1"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable(LOGICAL,408) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q <= not ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor(LOGICAL,435) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q <= not (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a or ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top(CONSTANT,431) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q <= "011000"; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp(LOGICAL,432) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q <= "1" when ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a = ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b else "0"; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg(REG,433) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q; END IF; END IF; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena(REG,436) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd(LOGICAL,437) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b <= en; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a and ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b; --signX_uid8_fpSqrtTest(BITSELECT,7)@0 signX_uid8_fpSqrtTest_in <= a; signX_uid8_fpSqrtTest_b <= signX_uid8_fpSqrtTest_in(63 downto 63); --cstAllZWE_uid11_fpSqrtTest(CONSTANT,10) cstAllZWE_uid11_fpSqrtTest_q <= "00000000000"; --expX_uid6_fpSqrtTest(BITSELECT,5)@0 expX_uid6_fpSqrtTest_in <= a(62 downto 0); expX_uid6_fpSqrtTest_b <= expX_uid6_fpSqrtTest_in(62 downto 52); --expXIsZero_uid13_fpSqrtTest(LOGICAL,12)@0 expXIsZero_uid13_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b; expXIsZero_uid13_fpSqrtTest_b <= cstAllZWE_uid11_fpSqrtTest_q; expXIsZero_uid13_fpSqrtTest_q <= "1" when expXIsZero_uid13_fpSqrtTest_a = expXIsZero_uid13_fpSqrtTest_b else "0"; --negZero_uid56_fpSqrtTest(LOGICAL,55)@0 negZero_uid56_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q; negZero_uid56_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; negZero_uid56_fpSqrtTest_q_i <= negZero_uid56_fpSqrtTest_a and negZero_uid56_fpSqrtTest_b; negZero_uid56_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => negZero_uid56_fpSqrtTest_q, xin => negZero_uid56_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg(DELAY,425) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => negZero_uid56_fpSqrtTest_q, xout => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt(COUNTER,427) -- every=1, low=0, high=24, step=1, init=1 ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i = 23 THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '1'; ELSE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i - 24; ELSE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i,5)); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg(REG,428) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q; END IF; END IF; END PROCESS; --xIn(GPIN,3)@0 --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux(MUX,429) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s <= en; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux: PROCESS (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q) BEGIN CASE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s IS WHEN "0" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q; WHEN "1" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q; WHEN OTHERS => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem(DUALMEM,426) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 25, width_b => 1, widthad_b => 5, numwords_b => 25, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq, address_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa, data_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia ); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 <= areset; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq(0 downto 0); --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor(LOGICAL,422) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q <= not (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a or ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top(CONSTANT,405) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q <= "010111"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp(LOGICAL,406) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q <= "1" when ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a = ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b else "0"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg(REG,407) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena(REG,423) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q = "1") THEN ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd(LOGICAL,424) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b <= en; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a and ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b; --cstAllOWE_uid9_fpSqrtTest(CONSTANT,8) cstAllOWE_uid9_fpSqrtTest_q <= "11111111111"; --sBiasM1_uid28_fpSqrtTest(CONSTANT,27) sBiasM1_uid28_fpSqrtTest_q <= "01111111110"; --expOddSig_uid29_fpSqrtTest(ADD,28)@0 expOddSig_uid29_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b); expOddSig_uid29_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBiasM1_uid28_fpSqrtTest_q); expOddSig_uid29_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid29_fpSqrtTest_a) + UNSIGNED(expOddSig_uid29_fpSqrtTest_b)); expOddSig_uid29_fpSqrtTest_q <= expOddSig_uid29_fpSqrtTest_o(11 downto 0); --expROdd_uid30_fpSqrtTest(BITSELECT,29)@0 expROdd_uid30_fpSqrtTest_in <= expOddSig_uid29_fpSqrtTest_q; expROdd_uid30_fpSqrtTest_b <= expROdd_uid30_fpSqrtTest_in(11 downto 1); --sBias_uid25_fpSqrtTest(CONSTANT,24) sBias_uid25_fpSqrtTest_q <= "01111111111"; --expEvenSig_uid26_fpSqrtTest(ADD,25)@0 expEvenSig_uid26_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b); expEvenSig_uid26_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBias_uid25_fpSqrtTest_q); expEvenSig_uid26_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid26_fpSqrtTest_a) + UNSIGNED(expEvenSig_uid26_fpSqrtTest_b)); expEvenSig_uid26_fpSqrtTest_q <= expEvenSig_uid26_fpSqrtTest_o(11 downto 0); --expREven_uid27_fpSqrtTest(BITSELECT,26)@0 expREven_uid27_fpSqrtTest_in <= expEvenSig_uid26_fpSqrtTest_q; expREven_uid27_fpSqrtTest_b <= expREven_uid27_fpSqrtTest_in(11 downto 1); --expX0_uid31_fpSqrtTest(BITSELECT,30)@0 expX0_uid31_fpSqrtTest_in <= expX_uid6_fpSqrtTest_b(0 downto 0); expX0_uid31_fpSqrtTest_b <= expX0_uid31_fpSqrtTest_in(0 downto 0); --expOddSelect_uid32_fpSqrtTest(LOGICAL,31)@0 expOddSelect_uid32_fpSqrtTest_a <= expX0_uid31_fpSqrtTest_b; expOddSelect_uid32_fpSqrtTest_q <= not expOddSelect_uid32_fpSqrtTest_a; --expRMux_uid33_fpSqrtTest(MUX,32)@0 expRMux_uid33_fpSqrtTest_s <= expOddSelect_uid32_fpSqrtTest_q; expRMux_uid33_fpSqrtTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRMux_uid33_fpSqrtTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE expRMux_uid33_fpSqrtTest_s IS WHEN "0" => expRMux_uid33_fpSqrtTest_q <= expREven_uid27_fpSqrtTest_b; WHEN "1" => expRMux_uid33_fpSqrtTest_q <= expROdd_uid30_fpSqrtTest_b; WHEN OTHERS => expRMux_uid33_fpSqrtTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d(DELAY,248)@1 ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => expRMux_uid33_fpSqrtTest_q, xout => ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, ena => en(0), clk => clk, aclr => areset ); --ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b(DELAY,245)@0 ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signX_uid8_fpSqrtTest_b, xout => ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset ); --cstAllZWF_uid10_fpSqrtTest(CONSTANT,9) cstAllZWF_uid10_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000000"; --fracX_uid7_fpSqrtTest(BITSELECT,6)@0 fracX_uid7_fpSqrtTest_in <= a(51 downto 0); fracX_uid7_fpSqrtTest_b <= fracX_uid7_fpSqrtTest_in(51 downto 0); --fracXIsZero_uid17_fpSqrtTest(LOGICAL,16)@0 fracXIsZero_uid17_fpSqrtTest_a <= fracX_uid7_fpSqrtTest_b; fracXIsZero_uid17_fpSqrtTest_b <= cstAllZWF_uid10_fpSqrtTest_q; fracXIsZero_uid17_fpSqrtTest_q <= "1" when fracXIsZero_uid17_fpSqrtTest_a = fracXIsZero_uid17_fpSqrtTest_b else "0"; --InvFracXIsZero_uid19_fpSqrtTest(LOGICAL,18)@0 InvFracXIsZero_uid19_fpSqrtTest_a <= fracXIsZero_uid17_fpSqrtTest_q; InvFracXIsZero_uid19_fpSqrtTest_q <= not InvFracXIsZero_uid19_fpSqrtTest_a; --expXIsMax_uid15_fpSqrtTest(LOGICAL,14)@0 expXIsMax_uid15_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b; expXIsMax_uid15_fpSqrtTest_b <= cstAllOWE_uid9_fpSqrtTest_q; expXIsMax_uid15_fpSqrtTest_q <= "1" when expXIsMax_uid15_fpSqrtTest_a = expXIsMax_uid15_fpSqrtTest_b else "0"; --exc_N_uid20_fpSqrtTest(LOGICAL,19)@0 exc_N_uid20_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q; exc_N_uid20_fpSqrtTest_b <= InvFracXIsZero_uid19_fpSqrtTest_q; exc_N_uid20_fpSqrtTest_q <= exc_N_uid20_fpSqrtTest_a and exc_N_uid20_fpSqrtTest_b; --InvExc_N_uid21_fpSqrtTest(LOGICAL,20)@0 InvExc_N_uid21_fpSqrtTest_a <= exc_N_uid20_fpSqrtTest_q; InvExc_N_uid21_fpSqrtTest_q <= not InvExc_N_uid21_fpSqrtTest_a; --exc_I_uid18_fpSqrtTest(LOGICAL,17)@0 exc_I_uid18_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q; exc_I_uid18_fpSqrtTest_b <= fracXIsZero_uid17_fpSqrtTest_q; exc_I_uid18_fpSqrtTest_q <= exc_I_uid18_fpSqrtTest_a and exc_I_uid18_fpSqrtTest_b; --InvExc_I_uid22_fpSqrtTest(LOGICAL,21)@0 InvExc_I_uid22_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; InvExc_I_uid22_fpSqrtTest_q <= not InvExc_I_uid22_fpSqrtTest_a; --InvExpXIsZero_uid23_fpSqrtTest(LOGICAL,22)@0 InvExpXIsZero_uid23_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q; InvExpXIsZero_uid23_fpSqrtTest_q <= not InvExpXIsZero_uid23_fpSqrtTest_a; --exc_R_uid24_fpSqrtTest(LOGICAL,23)@0 exc_R_uid24_fpSqrtTest_a <= InvExpXIsZero_uid23_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_b <= InvExc_I_uid22_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_c <= InvExc_N_uid21_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_q <= exc_R_uid24_fpSqrtTest_a and exc_R_uid24_fpSqrtTest_b and exc_R_uid24_fpSqrtTest_c; --minReg_uid42_fpSqrtTest(LOGICAL,41)@0 minReg_uid42_fpSqrtTest_a <= exc_R_uid24_fpSqrtTest_q; minReg_uid42_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; minReg_uid42_fpSqrtTest_q_i <= minReg_uid42_fpSqrtTest_a and minReg_uid42_fpSqrtTest_b; minReg_uid42_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => minReg_uid42_fpSqrtTest_q, xin => minReg_uid42_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --minInf_uid43_fpSqrtTest(LOGICAL,42)@0 minInf_uid43_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; minInf_uid43_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; minInf_uid43_fpSqrtTest_q_i <= minInf_uid43_fpSqrtTest_a and minInf_uid43_fpSqrtTest_b; minInf_uid43_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => minInf_uid43_fpSqrtTest_q, xin => minInf_uid43_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1(REG,155)@0 reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= exc_N_uid20_fpSqrtTest_q; END IF; END IF; END PROCESS; --excRNaN_uid44_fpSqrtTest(LOGICAL,43)@1 excRNaN_uid44_fpSqrtTest_a <= reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q; excRNaN_uid44_fpSqrtTest_b <= minInf_uid43_fpSqrtTest_q; excRNaN_uid44_fpSqrtTest_c <= minReg_uid42_fpSqrtTest_q; excRNaN_uid44_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_a or excRNaN_uid44_fpSqrtTest_b or excRNaN_uid44_fpSqrtTest_c; --InvSignX_uid40_fpSqrtTest(LOGICAL,39)@0 InvSignX_uid40_fpSqrtTest_a <= signX_uid8_fpSqrtTest_b; InvSignX_uid40_fpSqrtTest_q <= not InvSignX_uid40_fpSqrtTest_a; --inInfAndNotNeg_uid41_fpSqrtTest(LOGICAL,40)@0 inInfAndNotNeg_uid41_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; inInfAndNotNeg_uid41_fpSqrtTest_b <= InvSignX_uid40_fpSqrtTest_q; inInfAndNotNeg_uid41_fpSqrtTest_q_i <= inInfAndNotNeg_uid41_fpSqrtTest_a and inInfAndNotNeg_uid41_fpSqrtTest_b; inInfAndNotNeg_uid41_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => inInfAndNotNeg_uid41_fpSqrtTest_q, xin => inInfAndNotNeg_uid41_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0(REG,156)@0 reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= expXIsZero_uid13_fpSqrtTest_q; END IF; END IF; END PROCESS; --join_uid45_fpSqrtTest(BITJOIN,44)@1 join_uid45_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_q & inInfAndNotNeg_uid41_fpSqrtTest_q & reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q; --fracSelIn_uid46_fpSqrtTest(BITJOIN,45)@1 fracSelIn_uid46_fpSqrtTest_q <= ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q & join_uid45_fpSqrtTest_q; --fracSel_uid47_fpSqrtTest(LOOKUP,46)@1 fracSel_uid47_fpSqrtTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracSel_uid47_fpSqrtTest_q <= "01"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN CASE (fracSelIn_uid46_fpSqrtTest_q) IS WHEN "0000" => fracSel_uid47_fpSqrtTest_q <= "01"; WHEN "0001" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0010" => fracSel_uid47_fpSqrtTest_q <= "10"; WHEN "0011" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0100" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "0101" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0110" => fracSel_uid47_fpSqrtTest_q <= "10"; WHEN "0111" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "1000" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1001" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "1010" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1011" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1100" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1101" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1110" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1111" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN OTHERS => fracSel_uid47_fpSqrtTest_q <= (others => '-'); END CASE; END IF; END IF; END PROCESS; --expRPostExc_uid51_fpSqrtTest(MUX,50)@2 expRPostExc_uid51_fpSqrtTest_s <= fracSel_uid47_fpSqrtTest_q; expRPostExc_uid51_fpSqrtTest: PROCESS (expRPostExc_uid51_fpSqrtTest_s, en, cstAllZWE_uid11_fpSqrtTest_q, ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, cstAllOWE_uid9_fpSqrtTest_q, cstAllOWE_uid9_fpSqrtTest_q) BEGIN CASE expRPostExc_uid51_fpSqrtTest_s IS WHEN "00" => expRPostExc_uid51_fpSqrtTest_q <= cstAllZWE_uid11_fpSqrtTest_q; WHEN "01" => expRPostExc_uid51_fpSqrtTest_q <= ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q; WHEN "10" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q; WHEN "11" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q; WHEN OTHERS => expRPostExc_uid51_fpSqrtTest_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg(DELAY,412) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => expRPostExc_uid51_fpSqrtTest_q, xout => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt(COUNTER,401) -- every=1, low=0, high=23, step=1, init=1 ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i = 22 THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '1'; ELSE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i - 23; ELSE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i,5)); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg(REG,402) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux(MUX,403) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux: PROCESS (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q) BEGIN CASE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s IS WHEN "0" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; WHEN "1" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q; WHEN OTHERS => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem(DUALMEM,413) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 5, numwords_a => 24, width_b => 11, widthad_b => 5, numwords_b => 24, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq, address_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa, data_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia ); ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 <= areset; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq(10 downto 0); --fracNaN_uid52_fpSqrtTest(CONSTANT,51) fracNaN_uid52_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000001"; --fracXAddr_uid35_fpSqrtTest(BITSELECT,34)@0 fracXAddr_uid35_fpSqrtTest_in <= fracX_uid7_fpSqrtTest_b; fracXAddr_uid35_fpSqrtTest_b <= fracXAddr_uid35_fpSqrtTest_in(51 downto 45); --addrTable_uid36_fpSqrtTest(BITJOIN,35)@0 addrTable_uid36_fpSqrtTest_q <= expOddSelect_uid32_fpSqrtTest_q & fracXAddr_uid35_fpSqrtTest_b; --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0(REG,161)@0 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= addrTable_uid36_fpSqrtTest_q; END IF; END IF; END PROCESS; --memoryC5_uid71_sqrtTableGenerator_lutmem(DUALMEM,139)@1 memoryC5_uid71_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC5_uid71_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC5_uid71_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q; memoryC5_uid71_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 17, widthad_a => 8, numwords_a => 256, width_b => 17, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC5_uid71_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC5_uid71_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC5_uid71_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC5_uid71_sqrtTableGenerator_lutmem_iq, address_a => memoryC5_uid71_sqrtTableGenerator_lutmem_aa, data_a => memoryC5_uid71_sqrtTableGenerator_lutmem_ia ); memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC5_uid71_sqrtTableGenerator_lutmem_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_iq(16 downto 0); --reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1(REG,163)@3 reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg(DELAY,398) ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg : dspba_delay GENERIC MAP ( width => 52, depth => 1 ) PORT MAP ( xin => fracX_uid7_fpSqrtTest_b, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a(DELAY,229)@0 ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a : dspba_delay GENERIC MAP ( width => 52, depth => 2 ) PORT MAP ( xin => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset ); --FracX44dto0_uid37_fpSqrtTest(BITSELECT,36)@3 FracX44dto0_uid37_fpSqrtTest_in <= ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q(44 downto 0); FracX44dto0_uid37_fpSqrtTest_b <= FracX44dto0_uid37_fpSqrtTest_in(44 downto 0); --yT1_uid73_sqrtPolynomialEvaluator(BITSELECT,72)@3 yT1_uid73_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT1_uid73_sqrtPolynomialEvaluator_b <= yT1_uid73_sqrtPolynomialEvaluator_in(44 downto 28); --reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0(REG,162)@3 reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= yT1_uid73_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator(MULT,103)@4 prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a),18)) * SIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr,34)); END IF; END IF; END PROCESS; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator(BITSELECT,104)@7 prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in(33 downto 16); --highBBits_uid76_sqrtPolynomialEvaluator(BITSELECT,75)@7 highBBits_uid76_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b; highBBits_uid76_sqrtPolynomialEvaluator_b <= highBBits_uid76_sqrtPolynomialEvaluator_in(17 downto 1); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a(DELAY,363)@0 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0(REG,164)@3 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q; END IF; END IF; END PROCESS; --memoryC4_uid69_sqrtTableGenerator_lutmem(DUALMEM,138)@4 memoryC4_uid69_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC4_uid69_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC4_uid69_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q; memoryC4_uid69_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 8, numwords_a => 256, width_b => 24, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC4_uid69_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC4_uid69_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC4_uid69_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC4_uid69_sqrtTableGenerator_lutmem_iq, address_a => memoryC4_uid69_sqrtTableGenerator_lutmem_aa, data_a => memoryC4_uid69_sqrtTableGenerator_lutmem_ia ); memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC4_uid69_sqrtTableGenerator_lutmem_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_iq(23 downto 0); --reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0(REG,165)@6 reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid77_sqrtPolynomialEvaluator(ADD,76)@7 sumAHighB_uid77_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((24 downto 24 => reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q(23)) & reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q); sumAHighB_uid77_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((24 downto 17 => highBBits_uid76_sqrtPolynomialEvaluator_b(16)) & highBBits_uid76_sqrtPolynomialEvaluator_b); sumAHighB_uid77_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_b)); sumAHighB_uid77_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_o(24 downto 0); --lowRangeB_uid75_sqrtPolynomialEvaluator(BITSELECT,74)@7 lowRangeB_uid75_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid75_sqrtPolynomialEvaluator_b <= lowRangeB_uid75_sqrtPolynomialEvaluator_in(0 downto 0); --s1_uid75_uid78_sqrtPolynomialEvaluator(BITJOIN,77)@7 s1_uid75_uid78_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_q & lowRangeB_uid75_sqrtPolynomialEvaluator_b; --reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1(REG,167)@7 reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= s1_uid75_uid78_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor(LOGICAL,459) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a or ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg(REG,457) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= VCC_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena(REG,460) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,461) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b <= en; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b; --yT2_uid79_sqrtPolynomialEvaluator(BITSELECT,78)@3 yT2_uid79_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT2_uid79_sqrtPolynomialEvaluator_b <= yT2_uid79_sqrtPolynomialEvaluator_in(44 downto 21); --reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0(REG,166)@3 reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= yT2_uid79_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg(DELAY,451) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg : dspba_delay GENERIC MAP ( width => 24, depth => 1 ) PORT MAP ( xin => reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q, xout => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,453) -- every=1, low=0, high=1, step=1, init=1 ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i,1)); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg(REG,454) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,455) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q) BEGIN CASE ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s IS WHEN "0" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q; WHEN "1" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,452) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 1, numwords_a => 2, width_b => 24, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq, address_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa, data_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia ); ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq(23 downto 0); --prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator(MULT,106)@8 prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a),25)) * SIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr,50)); END IF; END IF; END PROCESS; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator(BITSELECT,107)@11 prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in(49 downto 23); --highBBits_uid82_sqrtPolynomialEvaluator(BITSELECT,81)@11 highBBits_uid82_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b; highBBits_uid82_sqrtPolynomialEvaluator_b <= highBBits_uid82_sqrtPolynomialEvaluator_in(26 downto 1); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor(LOGICAL,485) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,481) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q <= "0100"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,482) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b else "0"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg(REG,483) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena(REG,486) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,487) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg(DELAY,462) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q, xout => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,477) -- every=1, low=0, high=4, step=1, init=1 ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 3 THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 4; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,3)); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,478) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,479) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q) BEGIN CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q; WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,476) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 5, width_b => 8, widthad_b => 3, numwords_b => 5, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq, address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa, data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia ); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0); --memoryC3_uid67_sqrtTableGenerator_lutmem(DUALMEM,137)@8 memoryC3_uid67_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC3_uid67_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC3_uid67_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q; memoryC3_uid67_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 33, widthad_a => 8, numwords_a => 256, width_b => 33, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC3_uid67_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC3_uid67_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC3_uid67_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC3_uid67_sqrtTableGenerator_lutmem_iq, address_a => memoryC3_uid67_sqrtTableGenerator_lutmem_aa, data_a => memoryC3_uid67_sqrtTableGenerator_lutmem_ia ); memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC3_uid67_sqrtTableGenerator_lutmem_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_iq(32 downto 0); --reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0(REG,169)@10 reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid83_sqrtPolynomialEvaluator(ADD,82)@11 sumAHighB_uid83_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((33 downto 33 => reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q(32)) & reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q); sumAHighB_uid83_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((33 downto 26 => highBBits_uid82_sqrtPolynomialEvaluator_b(25)) & highBBits_uid82_sqrtPolynomialEvaluator_b); sumAHighB_uid83_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_b)); sumAHighB_uid83_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_o(33 downto 0); --lowRangeB_uid81_sqrtPolynomialEvaluator(BITSELECT,80)@11 lowRangeB_uid81_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid81_sqrtPolynomialEvaluator_b <= lowRangeB_uid81_sqrtPolynomialEvaluator_in(0 downto 0); --s2_uid81_uid84_sqrtPolynomialEvaluator(BITJOIN,83)@11 s2_uid81_uid84_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_q & lowRangeB_uid81_sqrtPolynomialEvaluator_b; --reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1(REG,171)@11 reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= s2_uid81_uid84_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor(LOGICAL,524) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q <= not (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a or ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top(CONSTANT,520) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q <= "0101"; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp(LOGICAL,521) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q <= "1" when ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a = ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b else "0"; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg(REG,522) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena(REG,525) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd(LOGICAL,526) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b <= en; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a and ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b; --yT3_uid85_sqrtPolynomialEvaluator(BITSELECT,84)@3 yT3_uid85_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT3_uid85_sqrtPolynomialEvaluator_b <= yT3_uid85_sqrtPolynomialEvaluator_in(44 downto 12); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg(DELAY,514) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg : dspba_delay GENERIC MAP ( width => 33, depth => 1 ) PORT MAP ( xin => yT3_uid85_sqrtPolynomialEvaluator_b, xout => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt(COUNTER,516) -- every=1, low=0, high=5, step=1, init=1 ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i = 4 THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i - 5; ELSE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i,3)); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg(REG,517) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux(MUX,518) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s <= en; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux: PROCESS (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q) BEGIN CASE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s IS WHEN "0" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; WHEN "1" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem(DUALMEM,515) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 33, widthad_a => 3, numwords_a => 6, width_b => 33, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq, address_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa, data_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia ); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 <= areset; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq(32 downto 0); --reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0(REG,170)@11 reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q; END IF; END IF; END PROCESS; --prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator(MULT,109)@12 prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a),34)) * SIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr,68)); END IF; END IF; END PROCESS; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator(BITSELECT,110)@15 prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in(67 downto 34); --highBBits_uid88_sqrtPolynomialEvaluator(BITSELECT,87)@15 highBBits_uid88_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b; highBBits_uid88_sqrtPolynomialEvaluator_b <= highBBits_uid88_sqrtPolynomialEvaluator_in(33 downto 1); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,537) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,533) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01000"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,534) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b else "0"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,535) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,538) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,539) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,501) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,529) -- every=1, low=0, high=8, step=1, init=1 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 7 THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1'; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 8; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4)); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,530) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,531) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q) BEGIN CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,528) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 9, width_b => 8, widthad_b => 4, numwords_b => 9, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0(REG,172)@11 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC2_uid65_sqrtTableGenerator_lutmem(DUALMEM,136)@12 memoryC2_uid65_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC2_uid65_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC2_uid65_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q; memoryC2_uid65_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC2_uid65_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid65_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid65_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid65_sqrtTableGenerator_lutmem_iq, address_a => memoryC2_uid65_sqrtTableGenerator_lutmem_aa, data_a => memoryC2_uid65_sqrtTableGenerator_lutmem_ia ); memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC2_uid65_sqrtTableGenerator_lutmem_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0(REG,173)@14 reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid89_sqrtPolynomialEvaluator(ADD,88)@15 sumAHighB_uid89_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q(39)) & reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q); sumAHighB_uid89_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((40 downto 33 => highBBits_uid88_sqrtPolynomialEvaluator_b(32)) & highBBits_uid88_sqrtPolynomialEvaluator_b); sumAHighB_uid89_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_b)); sumAHighB_uid89_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_o(40 downto 0); --lowRangeB_uid87_sqrtPolynomialEvaluator(BITSELECT,86)@15 lowRangeB_uid87_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid87_sqrtPolynomialEvaluator_b <= lowRangeB_uid87_sqrtPolynomialEvaluator_in(0 downto 0); --s3_uid87_uid90_sqrtPolynomialEvaluator(BITJOIN,89)@15 s3_uid87_uid90_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_q & lowRangeB_uid87_sqrtPolynomialEvaluator_b; --yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,118)@15 yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q; yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 24); --reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9(REG,177)@15 reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor(LOGICAL,448) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top(CONSTANT,444) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q <= "01001"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp(LOGICAL,445) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b else "0"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg(REG,446) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena(REG,449) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,450) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg(DELAY,438) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => FracX44dto0_uid37_fpSqrtTest_b, xout => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,440) -- every=1, low=0, high=9, step=1, init=1 ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 8 THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1'; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 9; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i,4)); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg(REG,441) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,442) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q) BEGIN CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s IS WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q; WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q; WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,439) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 10, width_b => 45, widthad_b => 4, numwords_b => 10, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0, clock1 => clk, address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq, address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa, data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia ); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq(44 downto 0); --yT4_uid91_sqrtPolynomialEvaluator(BITSELECT,90)@15 yT4_uid91_sqrtPolynomialEvaluator_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q; yT4_uid91_sqrtPolynomialEvaluator_b <= yT4_uid91_sqrtPolynomialEvaluator_in(44 downto 5); --xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,117)@15 xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b(12 downto 0); xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in(12 downto 0); --GND(CONSTANT,0) GND_q <= "0"; --pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,120)@15 pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7(REG,176)@15 reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,116)@15 yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q(14 downto 0); yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b <= yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in(14 downto 0); --spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,119)@15 spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q <= GND_q & yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b; --pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,121)@15 pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q <= spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q & STD_LOGIC_VECTOR((1 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6(REG,175)@15 reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,115)@15 xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b; xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 22); --reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4(REG,174)@15 reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma(CHAINMULTADD,140)@16 multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0),19)); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1),19)); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0) <= RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0),38) + RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1),38); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a <= (others => (others => '0')); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c <= (others => (others => '0')); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q),18); IF (en = "1") THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0); END IF; END IF; END PROCESS; multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_delay : dspba_delay GENERIC MAP (width => 37, depth => 1) PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q, clk => clk, aclr => areset); --multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,123)@19 multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q; multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in(36 downto 2); --highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,125)@19 highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b; highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b <= highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in(34 downto 6); --yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,113)@15 yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q; yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 15); --reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1(REG,179)@15 reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,112)@15 xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b; xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 13); --reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0(REG,178)@15 reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator(MULT,114)@16 topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a),28)) * SIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= (others => '0'); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= (others => '0'); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr,54)); END IF; END IF; END PROCESS; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator(ADD,126)@19 sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q(53)) & topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b(28)) & highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b)); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o(54 downto 0); --lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,124)@19 lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b(5 downto 0); lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b <= lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in(5 downto 0); --add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,127)@19 add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q & lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b; --R_uid129_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,128)@19 R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in <= add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q(59 downto 0); R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in(59 downto 17); --reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1(REG,181)@19 reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= "0000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,511) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,507) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01100"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,508) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b else "0"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,509) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,512) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,513) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,503) -- every=1, low=0, high=12, step=1, init=1 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 11 THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1'; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 12; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4)); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,504) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,505) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q) BEGIN CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,502) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 13, width_b => 8, widthad_b => 4, numwords_b => 13, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0(REG,157)@15 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC1_uid63_sqrtTableGenerator_lutmem(DUALMEM,135)@16 memoryC1_uid63_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid63_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid63_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q; memoryC1_uid63_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 9, widthad_a => 8, numwords_a => 256, width_b => 9, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC1_uid63_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid63_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid63_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid63_sqrtTableGenerator_lutmem_iq, address_a => memoryC1_uid63_sqrtTableGenerator_lutmem_aa, data_a => memoryC1_uid63_sqrtTableGenerator_lutmem_ia ); memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC1_uid63_sqrtTableGenerator_lutmem_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_iq(8 downto 0); --reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1(REG,160)@18 reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= "000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --memoryC1_uid62_sqrtTableGenerator_lutmem(DUALMEM,134)@16 memoryC1_uid62_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid62_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid62_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q; memoryC1_uid62_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC1_uid62_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid62_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid62_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid62_sqrtTableGenerator_lutmem_iq, address_a => memoryC1_uid62_sqrtTableGenerator_lutmem_aa, data_a => memoryC1_uid62_sqrtTableGenerator_lutmem_ia ); memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC1_uid62_sqrtTableGenerator_lutmem_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0(REG,159)@18 reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --os_uid64_sqrtTableGenerator(BITJOIN,63)@19 os_uid64_sqrtTableGenerator_q <= reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q & reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q; --rndBit_uid93_sqrtPolynomialEvaluator(CONSTANT,92) rndBit_uid93_sqrtPolynomialEvaluator_q <= "01"; --cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator(BITJOIN,93)@19 cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q <= os_uid64_sqrtTableGenerator_q & rndBit_uid93_sqrtPolynomialEvaluator_q; --reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0(REG,180)@19 reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ts4_uid95_sqrtPolynomialEvaluator(ADD,94)@20 ts4_uid95_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((51 downto 51 => reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q(50)) & reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q); ts4_uid95_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((51 downto 43 => reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q(42)) & reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q); ts4_uid95_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid95_sqrtPolynomialEvaluator_a) + SIGNED(ts4_uid95_sqrtPolynomialEvaluator_b)); ts4_uid95_sqrtPolynomialEvaluator_q <= ts4_uid95_sqrtPolynomialEvaluator_o(51 downto 0); --s4_uid96_sqrtPolynomialEvaluator(BITSELECT,95)@20 s4_uid96_sqrtPolynomialEvaluator_in <= ts4_uid95_sqrtPolynomialEvaluator_q; s4_uid96_sqrtPolynomialEvaluator_b <= s4_uid96_sqrtPolynomialEvaluator_in(51 downto 1); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1(BITSELECT,144)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in <= STD_LOGIC_VECTOR((53 downto 51 => s4_uid96_sqrtPolynomialEvaluator_b(50)) & s4_uid96_sqrtPolynomialEvaluator_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in(53 downto 27); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1(REG,187)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor(LOGICAL,498) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top(CONSTANT,494) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q <= "01110"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp(LOGICAL,495) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b else "0"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg(REG,496) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena(REG,499) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd(LOGICAL,500) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt(COUNTER,490) -- every=1, low=0, high=14, step=1, init=1 ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i = 13 THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '1'; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i - 14; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i,4)); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg(REG,491) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux(MUX,492) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q) BEGIN CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s IS WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q; WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q; WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem(DUALMEM,489) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 15, width_b => 45, widthad_b => 4, numwords_b => 15, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq, address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa, data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia ); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 <= areset; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq(44 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1(BITSELECT,142)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in <= STD_LOGIC_VECTOR("000000000" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in(53 downto 27); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0(REG,184)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1(MULT,148)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr,54)); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1; END IF; END IF; END PROCESS; --ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a(DELAY,349)@24 ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a : dspba_delay GENERIC MAP ( width => 54, depth => 2 ) PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q, ena => en(0), clk => clk, aclr => areset ); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2(BITSHIFT,152)@26 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q & "000000000000000000000000000000000000000000000000000000"; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int(107 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0(BITSELECT,141)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q(26 downto 0); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in(26 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0(REG,182)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1(MULT,147)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr,54)); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0(BITSELECT,143)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in <= s4_uid96_sqrtPolynomialEvaluator_b(26 downto 0); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in(26 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1(REG,183)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0(MULT,146)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0(ADD,149)@24 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR('0' & "00" & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR((56 downto 54 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q(53)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b)); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o(55 downto 0); --ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a(DELAY,348)@24 ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a : dspba_delay GENERIC MAP ( width => 56, depth => 1 ) PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q, ena => en(0), clk => clk, aclr => areset ); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1(BITSHIFT,151)@25 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q & "000000000000000000000000000"; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int(82 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0(MULT,145)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0(BITSHIFT,150)@24 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int(53 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0(REG,188)@24 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0(ADD,153)@25 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q(82)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b)); END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o(83 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0(ADD,154)@26 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a <= STD_LOGIC_VECTOR((108 downto 84 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q(83)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b <= STD_LOGIC_VECTOR((108 downto 108 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q(107)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b)); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o(108 downto 0); --prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator(BITSELECT,130)@26 prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q(95 downto 0); prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in(95 downto 44); --highBBits_uid100_sqrtPolynomialEvaluator(BITSELECT,99)@26 highBBits_uid100_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b; highBBits_uid100_sqrtPolynomialEvaluator_b <= highBBits_uid100_sqrtPolynomialEvaluator_in(51 downto 2); --reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1(REG,196)@26 reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= highBBits_uid100_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor(LOGICAL,472) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,468) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q <= "010011"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,469) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b else "0"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg(REG,470) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena(REG,473) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,474) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,464) -- every=1, low=0, high=19, step=1, init=1 ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 18 THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 19; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,5)); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,465) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,466) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q) BEGIN CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,463) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 5, numwords_a => 20, width_b => 8, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq, address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa, data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia ); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0); --memoryC0_uid60_sqrtTableGenerator_lutmem(DUALMEM,133)@23 memoryC0_uid60_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid60_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid60_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q; memoryC0_uid60_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 17, widthad_a => 8, numwords_a => 256, width_b => 17, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC0_uid60_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid60_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid60_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid60_sqrtTableGenerator_lutmem_iq, address_a => memoryC0_uid60_sqrtTableGenerator_lutmem_aa, data_a => memoryC0_uid60_sqrtTableGenerator_lutmem_ia ); memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC0_uid60_sqrtTableGenerator_lutmem_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_iq(16 downto 0); --reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1(REG,194)@25 reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,550) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,551) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,552) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,541) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 5, numwords_a => 20, width_b => 8, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0(REG,191)@22 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC0_uid59_sqrtTableGenerator_lutmem(DUALMEM,132)@23 memoryC0_uid59_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid59_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid59_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q; memoryC0_uid59_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC0_uid59_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid59_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid59_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid59_sqrtTableGenerator_lutmem_iq, address_a => memoryC0_uid59_sqrtTableGenerator_lutmem_aa, data_a => memoryC0_uid59_sqrtTableGenerator_lutmem_ia ); memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC0_uid59_sqrtTableGenerator_lutmem_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0(REG,193)@25 reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --os_uid61_sqrtTableGenerator(BITJOIN,60)@26 os_uid61_sqrtTableGenerator_q <= reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q & reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q; --reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0(REG,195)@26 reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= os_uid61_sqrtTableGenerator_q; END IF; END IF; END PROCESS; --sumAHighB_uid101_sqrtPolynomialEvaluator(ADD,100)@27 sumAHighB_uid101_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((57 downto 57 => reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q(56)) & reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q); sumAHighB_uid101_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((57 downto 50 => reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q(49)) & reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q); sumAHighB_uid101_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_b)); sumAHighB_uid101_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_o(57 downto 0); --lowRangeB_uid99_sqrtPolynomialEvaluator(BITSELECT,98)@26 lowRangeB_uid99_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b(1 downto 0); lowRangeB_uid99_sqrtPolynomialEvaluator_b <= lowRangeB_uid99_sqrtPolynomialEvaluator_in(1 downto 0); --reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0(REG,197)@26 reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= lowRangeB_uid99_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --s5_uid99_uid102_sqrtPolynomialEvaluator(BITJOIN,101)@27 s5_uid99_uid102_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_q & reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q; --fracR_uid39_fpSqrtTest(BITSELECT,38)@27 fracR_uid39_fpSqrtTest_in <= s5_uid99_uid102_sqrtPolynomialEvaluator_q(56 downto 0); fracR_uid39_fpSqrtTest_b <= fracR_uid39_fpSqrtTest_in(56 downto 5); --reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3(REG,198)@27 reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= "0000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= fracR_uid39_fpSqrtTest_b; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor(LOGICAL,409) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q <= not (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a or ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena(REG,410) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd(LOGICAL,411) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a and ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg(DELAY,399) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => fracSel_uid47_fpSqrtTest_q, xout => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem(DUALMEM,400) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 2, widthad_a => 5, numwords_a => 24, width_b => 2, widthad_b => 5, numwords_b => 24, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq, address_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa, data_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia ); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 <= areset; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq(1 downto 0); --fracRPostExc_uid55_fpSqrtTest(MUX,54)@28 fracRPostExc_uid55_fpSqrtTest_s <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q; fracRPostExc_uid55_fpSqrtTest: PROCESS (fracRPostExc_uid55_fpSqrtTest_s, en, cstAllZWF_uid10_fpSqrtTest_q, reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q, cstAllZWF_uid10_fpSqrtTest_q, fracNaN_uid52_fpSqrtTest_q) BEGIN CASE fracRPostExc_uid55_fpSqrtTest_s IS WHEN "00" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q; WHEN "01" => fracRPostExc_uid55_fpSqrtTest_q <= reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q; WHEN "10" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q; WHEN "11" => fracRPostExc_uid55_fpSqrtTest_q <= fracNaN_uid52_fpSqrtTest_q; WHEN OTHERS => fracRPostExc_uid55_fpSqrtTest_q <= (others => '0'); END CASE; END PROCESS; --RSqrt_uid57_fpSqrtTest(BITJOIN,56)@28 RSqrt_uid57_fpSqrtTest_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q & ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q & fracRPostExc_uid55_fpSqrtTest_q; --xOut(GPOUT,4)@28 q <= RSqrt_uid57_fpSqrtTest_q; end normal;
----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Release Version 13.1 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from fp_sqrt_double_s5 -- VHDL created on Tue Apr 9 15:17:30 2013 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; entity fp_sqrt_double_s5 is port ( a : in std_logic_vector(63 downto 0); en : in std_logic_vector(0 downto 0); q : out std_logic_vector(63 downto 0); clk : in std_logic; areset : in std_logic ); end; architecture normal of fp_sqrt_double_s5 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstAllOWE_uid9_fpSqrtTest_q : std_logic_vector (10 downto 0); signal cstAllZWF_uid10_fpSqrtTest_q : std_logic_vector (51 downto 0); signal cstAllZWE_uid11_fpSqrtTest_q : std_logic_vector (10 downto 0); signal sBias_uid25_fpSqrtTest_q : std_logic_vector (10 downto 0); signal sBiasM1_uid28_fpSqrtTest_q : std_logic_vector (10 downto 0); signal expRMux_uid33_fpSqrtTest_s : std_logic_vector (0 downto 0); signal expRMux_uid33_fpSqrtTest_q : std_logic_vector (10 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_a : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_b : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_q : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_a : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_b : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_q : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_a : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_b : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_q : std_logic_vector(0 downto 0); signal fracSel_uid47_fpSqrtTest_q : std_logic_vector(1 downto 0); signal fracNaN_uid52_fpSqrtTest_q : std_logic_vector (51 downto 0); signal negZero_uid56_fpSqrtTest_a : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_b : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_q : std_logic_vector(0 downto 0); signal rndBit_uid93_sqrtPolynomialEvaluator_q : std_logic_vector (1 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a : std_logic_vector (16 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 : std_logic_vector (33 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr : SIGNED (34 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a : std_logic_vector (23 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 : std_logic_vector (49 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr : SIGNED (50 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q : std_logic_vector (49 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a : std_logic_vector (32 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 : std_logic_vector (67 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr : SIGNED (68 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q : std_logic_vector (67 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector (26 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 : std_logic_vector (53 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr : SIGNED (54 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (53 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid59_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid60_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid62_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid63_sqrtTableGenerator_lutmem_ia : std_logic_vector (8 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_iq : std_logic_vector (8 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_q : std_logic_vector (8 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC2_uid65_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC3_uid67_sqrtTableGenerator_lutmem_ia : std_logic_vector (32 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_iq : std_logic_vector (32 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_q : std_logic_vector (32 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC4_uid69_sqrtTableGenerator_lutmem_ia : std_logic_vector (23 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_iq : std_logic_vector (23 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_q : std_logic_vector (23 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC5_uid71_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0); type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type; attribute preserve : boolean; attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : signal is true; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type is array(0 to 1) of SIGNED(17 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type; attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : signal is true; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type is array(0 to 1) of SIGNED(18 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type is array(0 to 1) of SIGNED(36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type; signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s0 : std_logic_vector(36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q : std_logic_vector (36 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr : UNSIGNED (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr : UNSIGNED (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr : SIGNED (54 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr : SIGNED (54 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a : std_logic_vector(84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b : std_logic_vector(84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o : std_logic_vector (84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q : std_logic_vector (83 downto 0); signal reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q : std_logic_vector (0 downto 0); signal reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q : std_logic_vector (0 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0); signal reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q : std_logic_vector (8 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q : std_logic_vector (16 downto 0); signal reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q : std_logic_vector (16 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0); signal reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0); signal reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q : std_logic_vector (25 downto 0); signal reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0); signal reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0); signal reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q : std_logic_vector (34 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q : std_logic_vector (39 downto 0); signal reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q : std_logic_vector (17 downto 0); signal reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q : std_logic_vector (17 downto 0); signal reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q : std_logic_vector (16 downto 0); signal reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q : std_logic_vector (17 downto 0); signal reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q : std_logic_vector (26 downto 0); signal reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q : std_logic_vector (50 downto 0); signal reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q : std_logic_vector (42 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q : std_logic_vector (53 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0); signal reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q : std_logic_vector (16 downto 0); signal reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q : std_logic_vector (56 downto 0); signal reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q : std_logic_vector (49 downto 0); signal reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q : std_logic_vector (1 downto 0); signal reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q : std_logic_vector (51 downto 0); signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q : std_logic_vector (51 downto 0); signal ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q : std_logic_vector (0 downto 0); signal ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q : std_logic_vector (10 downto 0); signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q : std_logic_vector (55 downto 0); signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q : std_logic_vector (53 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0); signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q : std_logic_vector (51 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 : std_logic; signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq : std_logic; signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : signal is true; signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 : std_logic; signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : signal is true; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 : std_logic; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i : unsigned(4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq : std_logic; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q : std_logic_vector (5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : signal is true; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true; signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic; signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 : std_logic; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq : std_logic; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a : std_logic_vector(56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b : std_logic_vector(56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o : std_logic_vector (56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q : std_logic_vector (55 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal expX_uid6_fpSqrtTest_in : std_logic_vector (62 downto 0); signal expX_uid6_fpSqrtTest_b : std_logic_vector (10 downto 0); signal fracX_uid7_fpSqrtTest_in : std_logic_vector (51 downto 0); signal fracX_uid7_fpSqrtTest_b : std_logic_vector (51 downto 0); signal signX_uid8_fpSqrtTest_in : std_logic_vector (63 downto 0); signal signX_uid8_fpSqrtTest_b : std_logic_vector (0 downto 0); signal expXIsZero_uid13_fpSqrtTest_a : std_logic_vector(10 downto 0); signal expXIsZero_uid13_fpSqrtTest_b : std_logic_vector(10 downto 0); signal expXIsZero_uid13_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid15_fpSqrtTest_a : std_logic_vector(10 downto 0); signal expXIsMax_uid15_fpSqrtTest_b : std_logic_vector(10 downto 0); signal expXIsMax_uid15_fpSqrtTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid17_fpSqrtTest_a : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSqrtTest_b : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSqrtTest_q : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expEvenSig_uid26_fpSqrtTest_a : std_logic_vector(11 downto 0); signal expEvenSig_uid26_fpSqrtTest_b : std_logic_vector(11 downto 0); signal expEvenSig_uid26_fpSqrtTest_o : std_logic_vector (11 downto 0); signal expEvenSig_uid26_fpSqrtTest_q : std_logic_vector (11 downto 0); signal expOddSig_uid29_fpSqrtTest_a : std_logic_vector(11 downto 0); signal expOddSig_uid29_fpSqrtTest_b : std_logic_vector(11 downto 0); signal expOddSig_uid29_fpSqrtTest_o : std_logic_vector (11 downto 0); signal expOddSig_uid29_fpSqrtTest_q : std_logic_vector (11 downto 0); signal excRNaN_uid44_fpSqrtTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expRPostExc_uid51_fpSqrtTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid51_fpSqrtTest_q : std_logic_vector (10 downto 0); signal fracRPostExc_uid55_fpSqrtTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid55_fpSqrtTest_q : std_logic_vector (51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_a : std_logic_vector(51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_b : std_logic_vector(51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_o : std_logic_vector (51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_q : std_logic_vector (51 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_a : std_logic_vector(57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_b : std_logic_vector(57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_o : std_logic_vector (57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_q : std_logic_vector (57 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal join_uid45_fpSqrtTest_q : std_logic_vector (2 downto 0); signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0); signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in : std_logic_vector (49 downto 0); signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in : std_logic_vector (67 downto 0); signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (33 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q : std_logic_vector (53 downto 0); signal os_uid64_sqrtTableGenerator_q : std_logic_vector (48 downto 0); signal os_uid61_sqrtTableGenerator_q : std_logic_vector (56 downto 0); signal s5_uid99_uid102_sqrtPolynomialEvaluator_q : std_logic_vector (59 downto 0); signal FracX44dto0_uid37_fpSqrtTest_in : std_logic_vector (44 downto 0); signal FracX44dto0_uid37_fpSqrtTest_b : std_logic_vector (44 downto 0); signal fracSelIn_uid46_fpSqrtTest_q : std_logic_vector (3 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int : std_logic_vector (82 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q : std_logic_vector (82 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int : std_logic_vector (107 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q : std_logic_vector (107 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0); signal RSqrt_uid57_fpSqrtTest_q : std_logic_vector (63 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a : std_logic_vector(5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b : std_logic_vector(5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q : std_logic_vector(0 downto 0); signal yT4_uid91_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT4_uid91_sqrtPolynomialEvaluator_b : std_logic_vector (39 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b : std_logic_vector (26 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a : std_logic_vector(3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b : std_logic_vector(3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal expX0_uid31_fpSqrtTest_in : std_logic_vector (0 downto 0); signal expX0_uid31_fpSqrtTest_b : std_logic_vector (0 downto 0); signal fracXAddr_uid35_fpSqrtTest_in : std_logic_vector (51 downto 0); signal fracXAddr_uid35_fpSqrtTest_b : std_logic_vector (6 downto 0); signal InvSignX_uid40_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvSignX_uid40_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid22_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid22_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expREven_uid27_fpSqrtTest_in : std_logic_vector (11 downto 0); signal expREven_uid27_fpSqrtTest_b : std_logic_vector (10 downto 0); signal expROdd_uid30_fpSqrtTest_in : std_logic_vector (11 downto 0); signal expROdd_uid30_fpSqrtTest_b : std_logic_vector (10 downto 0); signal s4_uid96_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0); signal s4_uid96_sqrtPolynomialEvaluator_b : std_logic_vector (50 downto 0); signal lowRangeB_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid76_sqrtPolynomialEvaluator_in : std_logic_vector (17 downto 0); signal highBBits_uid76_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal lowRangeB_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid82_sqrtPolynomialEvaluator_in : std_logic_vector (26 downto 0); signal highBBits_uid82_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0); signal lowRangeB_uid87_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid87_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid88_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0); signal highBBits_uid88_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0); signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (5 downto 0); signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (5 downto 0); signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (34 downto 0); signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (28 downto 0); signal cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q : std_logic_vector (50 downto 0); signal fracR_uid39_fpSqrtTest_in : std_logic_vector (56 downto 0); signal fracR_uid39_fpSqrtTest_b : std_logic_vector (51 downto 0); signal yT1_uid73_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT1_uid73_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal yT2_uid79_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT2_uid79_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0); signal yT3_uid85_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT3_uid85_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a : std_logic_vector(108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b : std_logic_vector(108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o : std_logic_vector (108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q : std_logic_vector (108 downto 0); signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0); signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0); signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0); signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0); signal expOddSelect_uid32_fpSqrtTest_a : std_logic_vector(0 downto 0); signal expOddSelect_uid32_fpSqrtTest_q : std_logic_vector(0 downto 0); signal addrTable_uid36_fpSqrtTest_q : std_logic_vector (7 downto 0); signal exc_N_uid20_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_N_uid20_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_N_uid20_fpSqrtTest_q : std_logic_vector(0 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b : std_logic_vector (26 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_a : std_logic_vector(24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_b : std_logic_vector(24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_o : std_logic_vector (24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_q : std_logic_vector (24 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_a : std_logic_vector(33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_b : std_logic_vector(33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_o : std_logic_vector (33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_a : std_logic_vector(40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_b : std_logic_vector(40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_o : std_logic_vector (40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_q : std_logic_vector (40 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector(54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector(54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o : std_logic_vector (54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (54 downto 0); signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in : std_logic_vector (95 downto 0); signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b : std_logic_vector (51 downto 0); signal pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (16 downto 0); signal InvExc_N_uid21_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid21_fpSqrtTest_q : std_logic_vector(0 downto 0); signal s1_uid75_uid78_sqrtPolynomialEvaluator_q : std_logic_vector (25 downto 0); signal s2_uid81_uid84_sqrtPolynomialEvaluator_q : std_logic_vector (34 downto 0); signal s3_uid87_uid90_sqrtPolynomialEvaluator_q : std_logic_vector (41 downto 0); signal add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (60 downto 0); signal lowRangeB_uid99_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0); signal lowRangeB_uid99_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0); signal highBBits_uid100_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0); signal highBBits_uid100_sqrtPolynomialEvaluator_b : std_logic_vector (49 downto 0); signal exc_R_uid24_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_c : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_q : std_logic_vector(0 downto 0); signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0); signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (14 downto 0); signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (14 downto 0); signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0); signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (59 downto 0); signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (42 downto 0); signal spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (15 downto 0); signal pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (17 downto 0); begin --VCC(CONSTANT,1) VCC_q <= "1"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable(LOGICAL,408) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q <= not ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor(LOGICAL,435) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q <= not (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a or ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top(CONSTANT,431) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q <= "011000"; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp(LOGICAL,432) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q <= "1" when ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a = ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b else "0"; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg(REG,433) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q; END IF; END IF; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena(REG,436) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd(LOGICAL,437) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b <= en; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a and ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b; --signX_uid8_fpSqrtTest(BITSELECT,7)@0 signX_uid8_fpSqrtTest_in <= a; signX_uid8_fpSqrtTest_b <= signX_uid8_fpSqrtTest_in(63 downto 63); --cstAllZWE_uid11_fpSqrtTest(CONSTANT,10) cstAllZWE_uid11_fpSqrtTest_q <= "00000000000"; --expX_uid6_fpSqrtTest(BITSELECT,5)@0 expX_uid6_fpSqrtTest_in <= a(62 downto 0); expX_uid6_fpSqrtTest_b <= expX_uid6_fpSqrtTest_in(62 downto 52); --expXIsZero_uid13_fpSqrtTest(LOGICAL,12)@0 expXIsZero_uid13_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b; expXIsZero_uid13_fpSqrtTest_b <= cstAllZWE_uid11_fpSqrtTest_q; expXIsZero_uid13_fpSqrtTest_q <= "1" when expXIsZero_uid13_fpSqrtTest_a = expXIsZero_uid13_fpSqrtTest_b else "0"; --negZero_uid56_fpSqrtTest(LOGICAL,55)@0 negZero_uid56_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q; negZero_uid56_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; negZero_uid56_fpSqrtTest_q_i <= negZero_uid56_fpSqrtTest_a and negZero_uid56_fpSqrtTest_b; negZero_uid56_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => negZero_uid56_fpSqrtTest_q, xin => negZero_uid56_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg(DELAY,425) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => negZero_uid56_fpSqrtTest_q, xout => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt(COUNTER,427) -- every=1, low=0, high=24, step=1, init=1 ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i = 23 THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '1'; ELSE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i - 24; ELSE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i,5)); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg(REG,428) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q; END IF; END IF; END PROCESS; --xIn(GPIN,3)@0 --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux(MUX,429) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s <= en; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux: PROCESS (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q) BEGIN CASE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s IS WHEN "0" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q; WHEN "1" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q; WHEN OTHERS => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem(DUALMEM,426) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 25, width_b => 1, widthad_b => 5, numwords_b => 25, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq, address_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa, data_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia ); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 <= areset; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq(0 downto 0); --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor(LOGICAL,422) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q <= not (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a or ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top(CONSTANT,405) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q <= "010111"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp(LOGICAL,406) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q <= "1" when ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a = ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b else "0"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg(REG,407) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena(REG,423) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q = "1") THEN ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd(LOGICAL,424) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b <= en; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a and ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b; --cstAllOWE_uid9_fpSqrtTest(CONSTANT,8) cstAllOWE_uid9_fpSqrtTest_q <= "11111111111"; --sBiasM1_uid28_fpSqrtTest(CONSTANT,27) sBiasM1_uid28_fpSqrtTest_q <= "01111111110"; --expOddSig_uid29_fpSqrtTest(ADD,28)@0 expOddSig_uid29_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b); expOddSig_uid29_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBiasM1_uid28_fpSqrtTest_q); expOddSig_uid29_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid29_fpSqrtTest_a) + UNSIGNED(expOddSig_uid29_fpSqrtTest_b)); expOddSig_uid29_fpSqrtTest_q <= expOddSig_uid29_fpSqrtTest_o(11 downto 0); --expROdd_uid30_fpSqrtTest(BITSELECT,29)@0 expROdd_uid30_fpSqrtTest_in <= expOddSig_uid29_fpSqrtTest_q; expROdd_uid30_fpSqrtTest_b <= expROdd_uid30_fpSqrtTest_in(11 downto 1); --sBias_uid25_fpSqrtTest(CONSTANT,24) sBias_uid25_fpSqrtTest_q <= "01111111111"; --expEvenSig_uid26_fpSqrtTest(ADD,25)@0 expEvenSig_uid26_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b); expEvenSig_uid26_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBias_uid25_fpSqrtTest_q); expEvenSig_uid26_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid26_fpSqrtTest_a) + UNSIGNED(expEvenSig_uid26_fpSqrtTest_b)); expEvenSig_uid26_fpSqrtTest_q <= expEvenSig_uid26_fpSqrtTest_o(11 downto 0); --expREven_uid27_fpSqrtTest(BITSELECT,26)@0 expREven_uid27_fpSqrtTest_in <= expEvenSig_uid26_fpSqrtTest_q; expREven_uid27_fpSqrtTest_b <= expREven_uid27_fpSqrtTest_in(11 downto 1); --expX0_uid31_fpSqrtTest(BITSELECT,30)@0 expX0_uid31_fpSqrtTest_in <= expX_uid6_fpSqrtTest_b(0 downto 0); expX0_uid31_fpSqrtTest_b <= expX0_uid31_fpSqrtTest_in(0 downto 0); --expOddSelect_uid32_fpSqrtTest(LOGICAL,31)@0 expOddSelect_uid32_fpSqrtTest_a <= expX0_uid31_fpSqrtTest_b; expOddSelect_uid32_fpSqrtTest_q <= not expOddSelect_uid32_fpSqrtTest_a; --expRMux_uid33_fpSqrtTest(MUX,32)@0 expRMux_uid33_fpSqrtTest_s <= expOddSelect_uid32_fpSqrtTest_q; expRMux_uid33_fpSqrtTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRMux_uid33_fpSqrtTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE expRMux_uid33_fpSqrtTest_s IS WHEN "0" => expRMux_uid33_fpSqrtTest_q <= expREven_uid27_fpSqrtTest_b; WHEN "1" => expRMux_uid33_fpSqrtTest_q <= expROdd_uid30_fpSqrtTest_b; WHEN OTHERS => expRMux_uid33_fpSqrtTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d(DELAY,248)@1 ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => expRMux_uid33_fpSqrtTest_q, xout => ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, ena => en(0), clk => clk, aclr => areset ); --ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b(DELAY,245)@0 ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signX_uid8_fpSqrtTest_b, xout => ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset ); --cstAllZWF_uid10_fpSqrtTest(CONSTANT,9) cstAllZWF_uid10_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000000"; --fracX_uid7_fpSqrtTest(BITSELECT,6)@0 fracX_uid7_fpSqrtTest_in <= a(51 downto 0); fracX_uid7_fpSqrtTest_b <= fracX_uid7_fpSqrtTest_in(51 downto 0); --fracXIsZero_uid17_fpSqrtTest(LOGICAL,16)@0 fracXIsZero_uid17_fpSqrtTest_a <= fracX_uid7_fpSqrtTest_b; fracXIsZero_uid17_fpSqrtTest_b <= cstAllZWF_uid10_fpSqrtTest_q; fracXIsZero_uid17_fpSqrtTest_q <= "1" when fracXIsZero_uid17_fpSqrtTest_a = fracXIsZero_uid17_fpSqrtTest_b else "0"; --InvFracXIsZero_uid19_fpSqrtTest(LOGICAL,18)@0 InvFracXIsZero_uid19_fpSqrtTest_a <= fracXIsZero_uid17_fpSqrtTest_q; InvFracXIsZero_uid19_fpSqrtTest_q <= not InvFracXIsZero_uid19_fpSqrtTest_a; --expXIsMax_uid15_fpSqrtTest(LOGICAL,14)@0 expXIsMax_uid15_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b; expXIsMax_uid15_fpSqrtTest_b <= cstAllOWE_uid9_fpSqrtTest_q; expXIsMax_uid15_fpSqrtTest_q <= "1" when expXIsMax_uid15_fpSqrtTest_a = expXIsMax_uid15_fpSqrtTest_b else "0"; --exc_N_uid20_fpSqrtTest(LOGICAL,19)@0 exc_N_uid20_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q; exc_N_uid20_fpSqrtTest_b <= InvFracXIsZero_uid19_fpSqrtTest_q; exc_N_uid20_fpSqrtTest_q <= exc_N_uid20_fpSqrtTest_a and exc_N_uid20_fpSqrtTest_b; --InvExc_N_uid21_fpSqrtTest(LOGICAL,20)@0 InvExc_N_uid21_fpSqrtTest_a <= exc_N_uid20_fpSqrtTest_q; InvExc_N_uid21_fpSqrtTest_q <= not InvExc_N_uid21_fpSqrtTest_a; --exc_I_uid18_fpSqrtTest(LOGICAL,17)@0 exc_I_uid18_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q; exc_I_uid18_fpSqrtTest_b <= fracXIsZero_uid17_fpSqrtTest_q; exc_I_uid18_fpSqrtTest_q <= exc_I_uid18_fpSqrtTest_a and exc_I_uid18_fpSqrtTest_b; --InvExc_I_uid22_fpSqrtTest(LOGICAL,21)@0 InvExc_I_uid22_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; InvExc_I_uid22_fpSqrtTest_q <= not InvExc_I_uid22_fpSqrtTest_a; --InvExpXIsZero_uid23_fpSqrtTest(LOGICAL,22)@0 InvExpXIsZero_uid23_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q; InvExpXIsZero_uid23_fpSqrtTest_q <= not InvExpXIsZero_uid23_fpSqrtTest_a; --exc_R_uid24_fpSqrtTest(LOGICAL,23)@0 exc_R_uid24_fpSqrtTest_a <= InvExpXIsZero_uid23_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_b <= InvExc_I_uid22_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_c <= InvExc_N_uid21_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_q <= exc_R_uid24_fpSqrtTest_a and exc_R_uid24_fpSqrtTest_b and exc_R_uid24_fpSqrtTest_c; --minReg_uid42_fpSqrtTest(LOGICAL,41)@0 minReg_uid42_fpSqrtTest_a <= exc_R_uid24_fpSqrtTest_q; minReg_uid42_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; minReg_uid42_fpSqrtTest_q_i <= minReg_uid42_fpSqrtTest_a and minReg_uid42_fpSqrtTest_b; minReg_uid42_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => minReg_uid42_fpSqrtTest_q, xin => minReg_uid42_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --minInf_uid43_fpSqrtTest(LOGICAL,42)@0 minInf_uid43_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; minInf_uid43_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; minInf_uid43_fpSqrtTest_q_i <= minInf_uid43_fpSqrtTest_a and minInf_uid43_fpSqrtTest_b; minInf_uid43_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => minInf_uid43_fpSqrtTest_q, xin => minInf_uid43_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1(REG,155)@0 reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= exc_N_uid20_fpSqrtTest_q; END IF; END IF; END PROCESS; --excRNaN_uid44_fpSqrtTest(LOGICAL,43)@1 excRNaN_uid44_fpSqrtTest_a <= reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q; excRNaN_uid44_fpSqrtTest_b <= minInf_uid43_fpSqrtTest_q; excRNaN_uid44_fpSqrtTest_c <= minReg_uid42_fpSqrtTest_q; excRNaN_uid44_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_a or excRNaN_uid44_fpSqrtTest_b or excRNaN_uid44_fpSqrtTest_c; --InvSignX_uid40_fpSqrtTest(LOGICAL,39)@0 InvSignX_uid40_fpSqrtTest_a <= signX_uid8_fpSqrtTest_b; InvSignX_uid40_fpSqrtTest_q <= not InvSignX_uid40_fpSqrtTest_a; --inInfAndNotNeg_uid41_fpSqrtTest(LOGICAL,40)@0 inInfAndNotNeg_uid41_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; inInfAndNotNeg_uid41_fpSqrtTest_b <= InvSignX_uid40_fpSqrtTest_q; inInfAndNotNeg_uid41_fpSqrtTest_q_i <= inInfAndNotNeg_uid41_fpSqrtTest_a and inInfAndNotNeg_uid41_fpSqrtTest_b; inInfAndNotNeg_uid41_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => inInfAndNotNeg_uid41_fpSqrtTest_q, xin => inInfAndNotNeg_uid41_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0(REG,156)@0 reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= expXIsZero_uid13_fpSqrtTest_q; END IF; END IF; END PROCESS; --join_uid45_fpSqrtTest(BITJOIN,44)@1 join_uid45_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_q & inInfAndNotNeg_uid41_fpSqrtTest_q & reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q; --fracSelIn_uid46_fpSqrtTest(BITJOIN,45)@1 fracSelIn_uid46_fpSqrtTest_q <= ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q & join_uid45_fpSqrtTest_q; --fracSel_uid47_fpSqrtTest(LOOKUP,46)@1 fracSel_uid47_fpSqrtTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracSel_uid47_fpSqrtTest_q <= "01"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN CASE (fracSelIn_uid46_fpSqrtTest_q) IS WHEN "0000" => fracSel_uid47_fpSqrtTest_q <= "01"; WHEN "0001" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0010" => fracSel_uid47_fpSqrtTest_q <= "10"; WHEN "0011" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0100" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "0101" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0110" => fracSel_uid47_fpSqrtTest_q <= "10"; WHEN "0111" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "1000" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1001" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "1010" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1011" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1100" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1101" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1110" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1111" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN OTHERS => fracSel_uid47_fpSqrtTest_q <= (others => '-'); END CASE; END IF; END IF; END PROCESS; --expRPostExc_uid51_fpSqrtTest(MUX,50)@2 expRPostExc_uid51_fpSqrtTest_s <= fracSel_uid47_fpSqrtTest_q; expRPostExc_uid51_fpSqrtTest: PROCESS (expRPostExc_uid51_fpSqrtTest_s, en, cstAllZWE_uid11_fpSqrtTest_q, ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, cstAllOWE_uid9_fpSqrtTest_q, cstAllOWE_uid9_fpSqrtTest_q) BEGIN CASE expRPostExc_uid51_fpSqrtTest_s IS WHEN "00" => expRPostExc_uid51_fpSqrtTest_q <= cstAllZWE_uid11_fpSqrtTest_q; WHEN "01" => expRPostExc_uid51_fpSqrtTest_q <= ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q; WHEN "10" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q; WHEN "11" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q; WHEN OTHERS => expRPostExc_uid51_fpSqrtTest_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg(DELAY,412) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => expRPostExc_uid51_fpSqrtTest_q, xout => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt(COUNTER,401) -- every=1, low=0, high=23, step=1, init=1 ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i = 22 THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '1'; ELSE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i - 23; ELSE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i,5)); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg(REG,402) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux(MUX,403) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux: PROCESS (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q) BEGIN CASE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s IS WHEN "0" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; WHEN "1" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q; WHEN OTHERS => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem(DUALMEM,413) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 5, numwords_a => 24, width_b => 11, widthad_b => 5, numwords_b => 24, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq, address_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa, data_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia ); ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 <= areset; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq(10 downto 0); --fracNaN_uid52_fpSqrtTest(CONSTANT,51) fracNaN_uid52_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000001"; --fracXAddr_uid35_fpSqrtTest(BITSELECT,34)@0 fracXAddr_uid35_fpSqrtTest_in <= fracX_uid7_fpSqrtTest_b; fracXAddr_uid35_fpSqrtTest_b <= fracXAddr_uid35_fpSqrtTest_in(51 downto 45); --addrTable_uid36_fpSqrtTest(BITJOIN,35)@0 addrTable_uid36_fpSqrtTest_q <= expOddSelect_uid32_fpSqrtTest_q & fracXAddr_uid35_fpSqrtTest_b; --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0(REG,161)@0 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= addrTable_uid36_fpSqrtTest_q; END IF; END IF; END PROCESS; --memoryC5_uid71_sqrtTableGenerator_lutmem(DUALMEM,139)@1 memoryC5_uid71_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC5_uid71_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC5_uid71_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q; memoryC5_uid71_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 17, widthad_a => 8, numwords_a => 256, width_b => 17, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC5_uid71_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC5_uid71_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC5_uid71_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC5_uid71_sqrtTableGenerator_lutmem_iq, address_a => memoryC5_uid71_sqrtTableGenerator_lutmem_aa, data_a => memoryC5_uid71_sqrtTableGenerator_lutmem_ia ); memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC5_uid71_sqrtTableGenerator_lutmem_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_iq(16 downto 0); --reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1(REG,163)@3 reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg(DELAY,398) ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg : dspba_delay GENERIC MAP ( width => 52, depth => 1 ) PORT MAP ( xin => fracX_uid7_fpSqrtTest_b, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a(DELAY,229)@0 ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a : dspba_delay GENERIC MAP ( width => 52, depth => 2 ) PORT MAP ( xin => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset ); --FracX44dto0_uid37_fpSqrtTest(BITSELECT,36)@3 FracX44dto0_uid37_fpSqrtTest_in <= ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q(44 downto 0); FracX44dto0_uid37_fpSqrtTest_b <= FracX44dto0_uid37_fpSqrtTest_in(44 downto 0); --yT1_uid73_sqrtPolynomialEvaluator(BITSELECT,72)@3 yT1_uid73_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT1_uid73_sqrtPolynomialEvaluator_b <= yT1_uid73_sqrtPolynomialEvaluator_in(44 downto 28); --reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0(REG,162)@3 reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= yT1_uid73_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator(MULT,103)@4 prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a),18)) * SIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr,34)); END IF; END IF; END PROCESS; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator(BITSELECT,104)@7 prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in(33 downto 16); --highBBits_uid76_sqrtPolynomialEvaluator(BITSELECT,75)@7 highBBits_uid76_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b; highBBits_uid76_sqrtPolynomialEvaluator_b <= highBBits_uid76_sqrtPolynomialEvaluator_in(17 downto 1); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a(DELAY,363)@0 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0(REG,164)@3 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q; END IF; END IF; END PROCESS; --memoryC4_uid69_sqrtTableGenerator_lutmem(DUALMEM,138)@4 memoryC4_uid69_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC4_uid69_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC4_uid69_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q; memoryC4_uid69_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 8, numwords_a => 256, width_b => 24, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC4_uid69_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC4_uid69_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC4_uid69_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC4_uid69_sqrtTableGenerator_lutmem_iq, address_a => memoryC4_uid69_sqrtTableGenerator_lutmem_aa, data_a => memoryC4_uid69_sqrtTableGenerator_lutmem_ia ); memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC4_uid69_sqrtTableGenerator_lutmem_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_iq(23 downto 0); --reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0(REG,165)@6 reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid77_sqrtPolynomialEvaluator(ADD,76)@7 sumAHighB_uid77_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((24 downto 24 => reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q(23)) & reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q); sumAHighB_uid77_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((24 downto 17 => highBBits_uid76_sqrtPolynomialEvaluator_b(16)) & highBBits_uid76_sqrtPolynomialEvaluator_b); sumAHighB_uid77_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_b)); sumAHighB_uid77_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_o(24 downto 0); --lowRangeB_uid75_sqrtPolynomialEvaluator(BITSELECT,74)@7 lowRangeB_uid75_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid75_sqrtPolynomialEvaluator_b <= lowRangeB_uid75_sqrtPolynomialEvaluator_in(0 downto 0); --s1_uid75_uid78_sqrtPolynomialEvaluator(BITJOIN,77)@7 s1_uid75_uid78_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_q & lowRangeB_uid75_sqrtPolynomialEvaluator_b; --reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1(REG,167)@7 reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= s1_uid75_uid78_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor(LOGICAL,459) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a or ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg(REG,457) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= VCC_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena(REG,460) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,461) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b <= en; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b; --yT2_uid79_sqrtPolynomialEvaluator(BITSELECT,78)@3 yT2_uid79_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT2_uid79_sqrtPolynomialEvaluator_b <= yT2_uid79_sqrtPolynomialEvaluator_in(44 downto 21); --reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0(REG,166)@3 reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= yT2_uid79_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg(DELAY,451) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg : dspba_delay GENERIC MAP ( width => 24, depth => 1 ) PORT MAP ( xin => reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q, xout => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,453) -- every=1, low=0, high=1, step=1, init=1 ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i,1)); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg(REG,454) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,455) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q) BEGIN CASE ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s IS WHEN "0" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q; WHEN "1" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,452) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 1, numwords_a => 2, width_b => 24, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq, address_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa, data_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia ); ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq(23 downto 0); --prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator(MULT,106)@8 prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a),25)) * SIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr,50)); END IF; END IF; END PROCESS; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator(BITSELECT,107)@11 prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in(49 downto 23); --highBBits_uid82_sqrtPolynomialEvaluator(BITSELECT,81)@11 highBBits_uid82_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b; highBBits_uid82_sqrtPolynomialEvaluator_b <= highBBits_uid82_sqrtPolynomialEvaluator_in(26 downto 1); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor(LOGICAL,485) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,481) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q <= "0100"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,482) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b else "0"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg(REG,483) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena(REG,486) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,487) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg(DELAY,462) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q, xout => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,477) -- every=1, low=0, high=4, step=1, init=1 ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 3 THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 4; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,3)); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,478) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,479) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q) BEGIN CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q; WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,476) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 5, width_b => 8, widthad_b => 3, numwords_b => 5, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq, address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa, data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia ); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0); --memoryC3_uid67_sqrtTableGenerator_lutmem(DUALMEM,137)@8 memoryC3_uid67_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC3_uid67_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC3_uid67_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q; memoryC3_uid67_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 33, widthad_a => 8, numwords_a => 256, width_b => 33, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC3_uid67_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC3_uid67_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC3_uid67_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC3_uid67_sqrtTableGenerator_lutmem_iq, address_a => memoryC3_uid67_sqrtTableGenerator_lutmem_aa, data_a => memoryC3_uid67_sqrtTableGenerator_lutmem_ia ); memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC3_uid67_sqrtTableGenerator_lutmem_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_iq(32 downto 0); --reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0(REG,169)@10 reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid83_sqrtPolynomialEvaluator(ADD,82)@11 sumAHighB_uid83_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((33 downto 33 => reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q(32)) & reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q); sumAHighB_uid83_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((33 downto 26 => highBBits_uid82_sqrtPolynomialEvaluator_b(25)) & highBBits_uid82_sqrtPolynomialEvaluator_b); sumAHighB_uid83_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_b)); sumAHighB_uid83_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_o(33 downto 0); --lowRangeB_uid81_sqrtPolynomialEvaluator(BITSELECT,80)@11 lowRangeB_uid81_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid81_sqrtPolynomialEvaluator_b <= lowRangeB_uid81_sqrtPolynomialEvaluator_in(0 downto 0); --s2_uid81_uid84_sqrtPolynomialEvaluator(BITJOIN,83)@11 s2_uid81_uid84_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_q & lowRangeB_uid81_sqrtPolynomialEvaluator_b; --reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1(REG,171)@11 reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= s2_uid81_uid84_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor(LOGICAL,524) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q <= not (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a or ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top(CONSTANT,520) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q <= "0101"; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp(LOGICAL,521) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q <= "1" when ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a = ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b else "0"; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg(REG,522) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena(REG,525) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd(LOGICAL,526) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b <= en; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a and ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b; --yT3_uid85_sqrtPolynomialEvaluator(BITSELECT,84)@3 yT3_uid85_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT3_uid85_sqrtPolynomialEvaluator_b <= yT3_uid85_sqrtPolynomialEvaluator_in(44 downto 12); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg(DELAY,514) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg : dspba_delay GENERIC MAP ( width => 33, depth => 1 ) PORT MAP ( xin => yT3_uid85_sqrtPolynomialEvaluator_b, xout => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt(COUNTER,516) -- every=1, low=0, high=5, step=1, init=1 ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i = 4 THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i - 5; ELSE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i,3)); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg(REG,517) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux(MUX,518) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s <= en; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux: PROCESS (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q) BEGIN CASE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s IS WHEN "0" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; WHEN "1" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem(DUALMEM,515) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 33, widthad_a => 3, numwords_a => 6, width_b => 33, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq, address_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa, data_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia ); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 <= areset; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq(32 downto 0); --reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0(REG,170)@11 reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q; END IF; END IF; END PROCESS; --prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator(MULT,109)@12 prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a),34)) * SIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr,68)); END IF; END IF; END PROCESS; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator(BITSELECT,110)@15 prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in(67 downto 34); --highBBits_uid88_sqrtPolynomialEvaluator(BITSELECT,87)@15 highBBits_uid88_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b; highBBits_uid88_sqrtPolynomialEvaluator_b <= highBBits_uid88_sqrtPolynomialEvaluator_in(33 downto 1); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,537) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,533) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01000"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,534) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b else "0"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,535) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,538) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,539) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,501) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,529) -- every=1, low=0, high=8, step=1, init=1 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 7 THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1'; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 8; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4)); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,530) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,531) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q) BEGIN CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,528) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 9, width_b => 8, widthad_b => 4, numwords_b => 9, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0(REG,172)@11 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC2_uid65_sqrtTableGenerator_lutmem(DUALMEM,136)@12 memoryC2_uid65_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC2_uid65_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC2_uid65_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q; memoryC2_uid65_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC2_uid65_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid65_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid65_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid65_sqrtTableGenerator_lutmem_iq, address_a => memoryC2_uid65_sqrtTableGenerator_lutmem_aa, data_a => memoryC2_uid65_sqrtTableGenerator_lutmem_ia ); memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC2_uid65_sqrtTableGenerator_lutmem_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0(REG,173)@14 reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid89_sqrtPolynomialEvaluator(ADD,88)@15 sumAHighB_uid89_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q(39)) & reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q); sumAHighB_uid89_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((40 downto 33 => highBBits_uid88_sqrtPolynomialEvaluator_b(32)) & highBBits_uid88_sqrtPolynomialEvaluator_b); sumAHighB_uid89_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_b)); sumAHighB_uid89_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_o(40 downto 0); --lowRangeB_uid87_sqrtPolynomialEvaluator(BITSELECT,86)@15 lowRangeB_uid87_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid87_sqrtPolynomialEvaluator_b <= lowRangeB_uid87_sqrtPolynomialEvaluator_in(0 downto 0); --s3_uid87_uid90_sqrtPolynomialEvaluator(BITJOIN,89)@15 s3_uid87_uid90_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_q & lowRangeB_uid87_sqrtPolynomialEvaluator_b; --yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,118)@15 yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q; yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 24); --reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9(REG,177)@15 reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor(LOGICAL,448) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top(CONSTANT,444) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q <= "01001"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp(LOGICAL,445) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b else "0"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg(REG,446) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena(REG,449) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,450) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg(DELAY,438) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => FracX44dto0_uid37_fpSqrtTest_b, xout => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,440) -- every=1, low=0, high=9, step=1, init=1 ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 8 THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1'; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 9; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i,4)); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg(REG,441) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,442) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q) BEGIN CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s IS WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q; WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q; WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,439) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 10, width_b => 45, widthad_b => 4, numwords_b => 10, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0, clock1 => clk, address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq, address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa, data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia ); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq(44 downto 0); --yT4_uid91_sqrtPolynomialEvaluator(BITSELECT,90)@15 yT4_uid91_sqrtPolynomialEvaluator_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q; yT4_uid91_sqrtPolynomialEvaluator_b <= yT4_uid91_sqrtPolynomialEvaluator_in(44 downto 5); --xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,117)@15 xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b(12 downto 0); xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in(12 downto 0); --GND(CONSTANT,0) GND_q <= "0"; --pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,120)@15 pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7(REG,176)@15 reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,116)@15 yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q(14 downto 0); yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b <= yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in(14 downto 0); --spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,119)@15 spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q <= GND_q & yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b; --pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,121)@15 pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q <= spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q & STD_LOGIC_VECTOR((1 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6(REG,175)@15 reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,115)@15 xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b; xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 22); --reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4(REG,174)@15 reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma(CHAINMULTADD,140)@16 multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0),19)); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1),19)); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0) <= RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0),38) + RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1),38); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a <= (others => (others => '0')); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c <= (others => (others => '0')); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q),18); IF (en = "1") THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0); END IF; END IF; END PROCESS; multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_delay : dspba_delay GENERIC MAP (width => 37, depth => 1) PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q, clk => clk, aclr => areset); --multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,123)@19 multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q; multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in(36 downto 2); --highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,125)@19 highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b; highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b <= highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in(34 downto 6); --yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,113)@15 yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q; yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 15); --reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1(REG,179)@15 reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,112)@15 xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b; xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 13); --reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0(REG,178)@15 reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator(MULT,114)@16 topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a),28)) * SIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= (others => '0'); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= (others => '0'); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr,54)); END IF; END IF; END PROCESS; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator(ADD,126)@19 sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q(53)) & topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b(28)) & highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b)); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o(54 downto 0); --lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,124)@19 lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b(5 downto 0); lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b <= lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in(5 downto 0); --add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,127)@19 add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q & lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b; --R_uid129_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,128)@19 R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in <= add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q(59 downto 0); R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in(59 downto 17); --reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1(REG,181)@19 reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= "0000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,511) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,507) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01100"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,508) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b else "0"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,509) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,512) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,513) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,503) -- every=1, low=0, high=12, step=1, init=1 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 11 THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1'; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 12; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4)); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,504) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,505) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q) BEGIN CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,502) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 13, width_b => 8, widthad_b => 4, numwords_b => 13, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0(REG,157)@15 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC1_uid63_sqrtTableGenerator_lutmem(DUALMEM,135)@16 memoryC1_uid63_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid63_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid63_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q; memoryC1_uid63_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 9, widthad_a => 8, numwords_a => 256, width_b => 9, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC1_uid63_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid63_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid63_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid63_sqrtTableGenerator_lutmem_iq, address_a => memoryC1_uid63_sqrtTableGenerator_lutmem_aa, data_a => memoryC1_uid63_sqrtTableGenerator_lutmem_ia ); memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC1_uid63_sqrtTableGenerator_lutmem_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_iq(8 downto 0); --reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1(REG,160)@18 reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= "000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --memoryC1_uid62_sqrtTableGenerator_lutmem(DUALMEM,134)@16 memoryC1_uid62_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid62_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid62_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q; memoryC1_uid62_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC1_uid62_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid62_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid62_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid62_sqrtTableGenerator_lutmem_iq, address_a => memoryC1_uid62_sqrtTableGenerator_lutmem_aa, data_a => memoryC1_uid62_sqrtTableGenerator_lutmem_ia ); memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC1_uid62_sqrtTableGenerator_lutmem_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0(REG,159)@18 reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --os_uid64_sqrtTableGenerator(BITJOIN,63)@19 os_uid64_sqrtTableGenerator_q <= reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q & reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q; --rndBit_uid93_sqrtPolynomialEvaluator(CONSTANT,92) rndBit_uid93_sqrtPolynomialEvaluator_q <= "01"; --cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator(BITJOIN,93)@19 cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q <= os_uid64_sqrtTableGenerator_q & rndBit_uid93_sqrtPolynomialEvaluator_q; --reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0(REG,180)@19 reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ts4_uid95_sqrtPolynomialEvaluator(ADD,94)@20 ts4_uid95_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((51 downto 51 => reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q(50)) & reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q); ts4_uid95_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((51 downto 43 => reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q(42)) & reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q); ts4_uid95_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid95_sqrtPolynomialEvaluator_a) + SIGNED(ts4_uid95_sqrtPolynomialEvaluator_b)); ts4_uid95_sqrtPolynomialEvaluator_q <= ts4_uid95_sqrtPolynomialEvaluator_o(51 downto 0); --s4_uid96_sqrtPolynomialEvaluator(BITSELECT,95)@20 s4_uid96_sqrtPolynomialEvaluator_in <= ts4_uid95_sqrtPolynomialEvaluator_q; s4_uid96_sqrtPolynomialEvaluator_b <= s4_uid96_sqrtPolynomialEvaluator_in(51 downto 1); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1(BITSELECT,144)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in <= STD_LOGIC_VECTOR((53 downto 51 => s4_uid96_sqrtPolynomialEvaluator_b(50)) & s4_uid96_sqrtPolynomialEvaluator_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in(53 downto 27); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1(REG,187)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor(LOGICAL,498) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top(CONSTANT,494) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q <= "01110"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp(LOGICAL,495) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b else "0"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg(REG,496) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena(REG,499) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd(LOGICAL,500) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt(COUNTER,490) -- every=1, low=0, high=14, step=1, init=1 ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i = 13 THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '1'; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i - 14; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i,4)); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg(REG,491) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux(MUX,492) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q) BEGIN CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s IS WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q; WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q; WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem(DUALMEM,489) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 15, width_b => 45, widthad_b => 4, numwords_b => 15, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq, address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa, data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia ); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 <= areset; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq(44 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1(BITSELECT,142)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in <= STD_LOGIC_VECTOR("000000000" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in(53 downto 27); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0(REG,184)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1(MULT,148)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr,54)); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1; END IF; END IF; END PROCESS; --ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a(DELAY,349)@24 ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a : dspba_delay GENERIC MAP ( width => 54, depth => 2 ) PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q, ena => en(0), clk => clk, aclr => areset ); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2(BITSHIFT,152)@26 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q & "000000000000000000000000000000000000000000000000000000"; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int(107 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0(BITSELECT,141)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q(26 downto 0); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in(26 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0(REG,182)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1(MULT,147)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr,54)); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0(BITSELECT,143)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in <= s4_uid96_sqrtPolynomialEvaluator_b(26 downto 0); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in(26 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1(REG,183)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0(MULT,146)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0(ADD,149)@24 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR('0' & "00" & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR((56 downto 54 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q(53)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b)); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o(55 downto 0); --ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a(DELAY,348)@24 ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a : dspba_delay GENERIC MAP ( width => 56, depth => 1 ) PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q, ena => en(0), clk => clk, aclr => areset ); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1(BITSHIFT,151)@25 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q & "000000000000000000000000000"; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int(82 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0(MULT,145)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0(BITSHIFT,150)@24 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int(53 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0(REG,188)@24 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0(ADD,153)@25 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q(82)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b)); END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o(83 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0(ADD,154)@26 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a <= STD_LOGIC_VECTOR((108 downto 84 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q(83)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b <= STD_LOGIC_VECTOR((108 downto 108 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q(107)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b)); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o(108 downto 0); --prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator(BITSELECT,130)@26 prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q(95 downto 0); prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in(95 downto 44); --highBBits_uid100_sqrtPolynomialEvaluator(BITSELECT,99)@26 highBBits_uid100_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b; highBBits_uid100_sqrtPolynomialEvaluator_b <= highBBits_uid100_sqrtPolynomialEvaluator_in(51 downto 2); --reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1(REG,196)@26 reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= highBBits_uid100_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor(LOGICAL,472) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,468) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q <= "010011"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,469) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b else "0"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg(REG,470) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena(REG,473) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,474) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,464) -- every=1, low=0, high=19, step=1, init=1 ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 18 THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 19; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,5)); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,465) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,466) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q) BEGIN CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,463) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 5, numwords_a => 20, width_b => 8, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq, address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa, data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia ); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0); --memoryC0_uid60_sqrtTableGenerator_lutmem(DUALMEM,133)@23 memoryC0_uid60_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid60_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid60_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q; memoryC0_uid60_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 17, widthad_a => 8, numwords_a => 256, width_b => 17, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC0_uid60_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid60_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid60_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid60_sqrtTableGenerator_lutmem_iq, address_a => memoryC0_uid60_sqrtTableGenerator_lutmem_aa, data_a => memoryC0_uid60_sqrtTableGenerator_lutmem_ia ); memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC0_uid60_sqrtTableGenerator_lutmem_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_iq(16 downto 0); --reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1(REG,194)@25 reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,550) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,551) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,552) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,541) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 5, numwords_a => 20, width_b => 8, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0(REG,191)@22 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC0_uid59_sqrtTableGenerator_lutmem(DUALMEM,132)@23 memoryC0_uid59_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid59_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid59_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q; memoryC0_uid59_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC0_uid59_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid59_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid59_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid59_sqrtTableGenerator_lutmem_iq, address_a => memoryC0_uid59_sqrtTableGenerator_lutmem_aa, data_a => memoryC0_uid59_sqrtTableGenerator_lutmem_ia ); memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC0_uid59_sqrtTableGenerator_lutmem_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0(REG,193)@25 reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --os_uid61_sqrtTableGenerator(BITJOIN,60)@26 os_uid61_sqrtTableGenerator_q <= reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q & reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q; --reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0(REG,195)@26 reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= os_uid61_sqrtTableGenerator_q; END IF; END IF; END PROCESS; --sumAHighB_uid101_sqrtPolynomialEvaluator(ADD,100)@27 sumAHighB_uid101_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((57 downto 57 => reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q(56)) & reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q); sumAHighB_uid101_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((57 downto 50 => reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q(49)) & reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q); sumAHighB_uid101_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_b)); sumAHighB_uid101_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_o(57 downto 0); --lowRangeB_uid99_sqrtPolynomialEvaluator(BITSELECT,98)@26 lowRangeB_uid99_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b(1 downto 0); lowRangeB_uid99_sqrtPolynomialEvaluator_b <= lowRangeB_uid99_sqrtPolynomialEvaluator_in(1 downto 0); --reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0(REG,197)@26 reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= lowRangeB_uid99_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --s5_uid99_uid102_sqrtPolynomialEvaluator(BITJOIN,101)@27 s5_uid99_uid102_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_q & reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q; --fracR_uid39_fpSqrtTest(BITSELECT,38)@27 fracR_uid39_fpSqrtTest_in <= s5_uid99_uid102_sqrtPolynomialEvaluator_q(56 downto 0); fracR_uid39_fpSqrtTest_b <= fracR_uid39_fpSqrtTest_in(56 downto 5); --reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3(REG,198)@27 reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= "0000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= fracR_uid39_fpSqrtTest_b; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor(LOGICAL,409) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q <= not (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a or ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena(REG,410) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd(LOGICAL,411) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a and ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg(DELAY,399) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => fracSel_uid47_fpSqrtTest_q, xout => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem(DUALMEM,400) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 2, widthad_a => 5, numwords_a => 24, width_b => 2, widthad_b => 5, numwords_b => 24, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq, address_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa, data_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia ); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 <= areset; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq(1 downto 0); --fracRPostExc_uid55_fpSqrtTest(MUX,54)@28 fracRPostExc_uid55_fpSqrtTest_s <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q; fracRPostExc_uid55_fpSqrtTest: PROCESS (fracRPostExc_uid55_fpSqrtTest_s, en, cstAllZWF_uid10_fpSqrtTest_q, reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q, cstAllZWF_uid10_fpSqrtTest_q, fracNaN_uid52_fpSqrtTest_q) BEGIN CASE fracRPostExc_uid55_fpSqrtTest_s IS WHEN "00" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q; WHEN "01" => fracRPostExc_uid55_fpSqrtTest_q <= reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q; WHEN "10" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q; WHEN "11" => fracRPostExc_uid55_fpSqrtTest_q <= fracNaN_uid52_fpSqrtTest_q; WHEN OTHERS => fracRPostExc_uid55_fpSqrtTest_q <= (others => '0'); END CASE; END PROCESS; --RSqrt_uid57_fpSqrtTest(BITJOIN,56)@28 RSqrt_uid57_fpSqrtTest_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q & ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q & fracRPostExc_uid55_fpSqrtTest_q; --xOut(GPOUT,4)@28 q <= RSqrt_uid57_fpSqrtTest_q; end normal;
----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Release Version 13.1 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from fp_sqrt_double_s5 -- VHDL created on Tue Apr 9 15:17:30 2013 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; entity fp_sqrt_double_s5 is port ( a : in std_logic_vector(63 downto 0); en : in std_logic_vector(0 downto 0); q : out std_logic_vector(63 downto 0); clk : in std_logic; areset : in std_logic ); end; architecture normal of fp_sqrt_double_s5 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstAllOWE_uid9_fpSqrtTest_q : std_logic_vector (10 downto 0); signal cstAllZWF_uid10_fpSqrtTest_q : std_logic_vector (51 downto 0); signal cstAllZWE_uid11_fpSqrtTest_q : std_logic_vector (10 downto 0); signal sBias_uid25_fpSqrtTest_q : std_logic_vector (10 downto 0); signal sBiasM1_uid28_fpSqrtTest_q : std_logic_vector (10 downto 0); signal expRMux_uid33_fpSqrtTest_s : std_logic_vector (0 downto 0); signal expRMux_uid33_fpSqrtTest_q : std_logic_vector (10 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_a : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_b : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_q : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_a : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_b : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_q : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_a : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_b : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_q : std_logic_vector(0 downto 0); signal fracSel_uid47_fpSqrtTest_q : std_logic_vector(1 downto 0); signal fracNaN_uid52_fpSqrtTest_q : std_logic_vector (51 downto 0); signal negZero_uid56_fpSqrtTest_a : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_b : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_q : std_logic_vector(0 downto 0); signal rndBit_uid93_sqrtPolynomialEvaluator_q : std_logic_vector (1 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a : std_logic_vector (16 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 : std_logic_vector (33 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr : SIGNED (34 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a : std_logic_vector (23 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 : std_logic_vector (49 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr : SIGNED (50 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q : std_logic_vector (49 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a : std_logic_vector (32 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 : std_logic_vector (67 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr : SIGNED (68 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q : std_logic_vector (67 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector (26 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 : std_logic_vector (53 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr : SIGNED (54 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (53 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid59_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid60_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid62_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid63_sqrtTableGenerator_lutmem_ia : std_logic_vector (8 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_iq : std_logic_vector (8 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_q : std_logic_vector (8 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC2_uid65_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC3_uid67_sqrtTableGenerator_lutmem_ia : std_logic_vector (32 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_iq : std_logic_vector (32 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_q : std_logic_vector (32 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC4_uid69_sqrtTableGenerator_lutmem_ia : std_logic_vector (23 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_iq : std_logic_vector (23 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_q : std_logic_vector (23 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC5_uid71_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0); type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type; attribute preserve : boolean; attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : signal is true; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type is array(0 to 1) of SIGNED(17 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type; attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : signal is true; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type is array(0 to 1) of SIGNED(18 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type is array(0 to 1) of SIGNED(36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type; signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s0 : std_logic_vector(36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q : std_logic_vector (36 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr : UNSIGNED (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr : UNSIGNED (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr : SIGNED (54 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr : SIGNED (54 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a : std_logic_vector(84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b : std_logic_vector(84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o : std_logic_vector (84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q : std_logic_vector (83 downto 0); signal reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q : std_logic_vector (0 downto 0); signal reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q : std_logic_vector (0 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0); signal reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q : std_logic_vector (8 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q : std_logic_vector (16 downto 0); signal reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q : std_logic_vector (16 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0); signal reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0); signal reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q : std_logic_vector (25 downto 0); signal reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0); signal reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0); signal reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q : std_logic_vector (34 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q : std_logic_vector (39 downto 0); signal reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q : std_logic_vector (17 downto 0); signal reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q : std_logic_vector (17 downto 0); signal reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q : std_logic_vector (16 downto 0); signal reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q : std_logic_vector (17 downto 0); signal reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q : std_logic_vector (26 downto 0); signal reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q : std_logic_vector (50 downto 0); signal reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q : std_logic_vector (42 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q : std_logic_vector (53 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0); signal reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q : std_logic_vector (16 downto 0); signal reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q : std_logic_vector (56 downto 0); signal reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q : std_logic_vector (49 downto 0); signal reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q : std_logic_vector (1 downto 0); signal reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q : std_logic_vector (51 downto 0); signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q : std_logic_vector (51 downto 0); signal ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q : std_logic_vector (0 downto 0); signal ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q : std_logic_vector (10 downto 0); signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q : std_logic_vector (55 downto 0); signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q : std_logic_vector (53 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0); signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q : std_logic_vector (51 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 : std_logic; signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq : std_logic; signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : signal is true; signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 : std_logic; signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : signal is true; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 : std_logic; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i : unsigned(4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq : std_logic; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q : std_logic_vector (5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : signal is true; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true; signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic; signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 : std_logic; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq : std_logic; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a : std_logic_vector(56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b : std_logic_vector(56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o : std_logic_vector (56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q : std_logic_vector (55 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal expX_uid6_fpSqrtTest_in : std_logic_vector (62 downto 0); signal expX_uid6_fpSqrtTest_b : std_logic_vector (10 downto 0); signal fracX_uid7_fpSqrtTest_in : std_logic_vector (51 downto 0); signal fracX_uid7_fpSqrtTest_b : std_logic_vector (51 downto 0); signal signX_uid8_fpSqrtTest_in : std_logic_vector (63 downto 0); signal signX_uid8_fpSqrtTest_b : std_logic_vector (0 downto 0); signal expXIsZero_uid13_fpSqrtTest_a : std_logic_vector(10 downto 0); signal expXIsZero_uid13_fpSqrtTest_b : std_logic_vector(10 downto 0); signal expXIsZero_uid13_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid15_fpSqrtTest_a : std_logic_vector(10 downto 0); signal expXIsMax_uid15_fpSqrtTest_b : std_logic_vector(10 downto 0); signal expXIsMax_uid15_fpSqrtTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid17_fpSqrtTest_a : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSqrtTest_b : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSqrtTest_q : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expEvenSig_uid26_fpSqrtTest_a : std_logic_vector(11 downto 0); signal expEvenSig_uid26_fpSqrtTest_b : std_logic_vector(11 downto 0); signal expEvenSig_uid26_fpSqrtTest_o : std_logic_vector (11 downto 0); signal expEvenSig_uid26_fpSqrtTest_q : std_logic_vector (11 downto 0); signal expOddSig_uid29_fpSqrtTest_a : std_logic_vector(11 downto 0); signal expOddSig_uid29_fpSqrtTest_b : std_logic_vector(11 downto 0); signal expOddSig_uid29_fpSqrtTest_o : std_logic_vector (11 downto 0); signal expOddSig_uid29_fpSqrtTest_q : std_logic_vector (11 downto 0); signal excRNaN_uid44_fpSqrtTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expRPostExc_uid51_fpSqrtTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid51_fpSqrtTest_q : std_logic_vector (10 downto 0); signal fracRPostExc_uid55_fpSqrtTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid55_fpSqrtTest_q : std_logic_vector (51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_a : std_logic_vector(51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_b : std_logic_vector(51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_o : std_logic_vector (51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_q : std_logic_vector (51 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_a : std_logic_vector(57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_b : std_logic_vector(57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_o : std_logic_vector (57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_q : std_logic_vector (57 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal join_uid45_fpSqrtTest_q : std_logic_vector (2 downto 0); signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0); signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in : std_logic_vector (49 downto 0); signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in : std_logic_vector (67 downto 0); signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (33 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q : std_logic_vector (53 downto 0); signal os_uid64_sqrtTableGenerator_q : std_logic_vector (48 downto 0); signal os_uid61_sqrtTableGenerator_q : std_logic_vector (56 downto 0); signal s5_uid99_uid102_sqrtPolynomialEvaluator_q : std_logic_vector (59 downto 0); signal FracX44dto0_uid37_fpSqrtTest_in : std_logic_vector (44 downto 0); signal FracX44dto0_uid37_fpSqrtTest_b : std_logic_vector (44 downto 0); signal fracSelIn_uid46_fpSqrtTest_q : std_logic_vector (3 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int : std_logic_vector (82 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q : std_logic_vector (82 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int : std_logic_vector (107 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q : std_logic_vector (107 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0); signal RSqrt_uid57_fpSqrtTest_q : std_logic_vector (63 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a : std_logic_vector(5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b : std_logic_vector(5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q : std_logic_vector(0 downto 0); signal yT4_uid91_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT4_uid91_sqrtPolynomialEvaluator_b : std_logic_vector (39 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b : std_logic_vector (26 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a : std_logic_vector(3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b : std_logic_vector(3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal expX0_uid31_fpSqrtTest_in : std_logic_vector (0 downto 0); signal expX0_uid31_fpSqrtTest_b : std_logic_vector (0 downto 0); signal fracXAddr_uid35_fpSqrtTest_in : std_logic_vector (51 downto 0); signal fracXAddr_uid35_fpSqrtTest_b : std_logic_vector (6 downto 0); signal InvSignX_uid40_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvSignX_uid40_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid22_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid22_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expREven_uid27_fpSqrtTest_in : std_logic_vector (11 downto 0); signal expREven_uid27_fpSqrtTest_b : std_logic_vector (10 downto 0); signal expROdd_uid30_fpSqrtTest_in : std_logic_vector (11 downto 0); signal expROdd_uid30_fpSqrtTest_b : std_logic_vector (10 downto 0); signal s4_uid96_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0); signal s4_uid96_sqrtPolynomialEvaluator_b : std_logic_vector (50 downto 0); signal lowRangeB_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid76_sqrtPolynomialEvaluator_in : std_logic_vector (17 downto 0); signal highBBits_uid76_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal lowRangeB_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid82_sqrtPolynomialEvaluator_in : std_logic_vector (26 downto 0); signal highBBits_uid82_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0); signal lowRangeB_uid87_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid87_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid88_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0); signal highBBits_uid88_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0); signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (5 downto 0); signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (5 downto 0); signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (34 downto 0); signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (28 downto 0); signal cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q : std_logic_vector (50 downto 0); signal fracR_uid39_fpSqrtTest_in : std_logic_vector (56 downto 0); signal fracR_uid39_fpSqrtTest_b : std_logic_vector (51 downto 0); signal yT1_uid73_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT1_uid73_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal yT2_uid79_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT2_uid79_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0); signal yT3_uid85_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT3_uid85_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a : std_logic_vector(108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b : std_logic_vector(108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o : std_logic_vector (108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q : std_logic_vector (108 downto 0); signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0); signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0); signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0); signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0); signal expOddSelect_uid32_fpSqrtTest_a : std_logic_vector(0 downto 0); signal expOddSelect_uid32_fpSqrtTest_q : std_logic_vector(0 downto 0); signal addrTable_uid36_fpSqrtTest_q : std_logic_vector (7 downto 0); signal exc_N_uid20_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_N_uid20_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_N_uid20_fpSqrtTest_q : std_logic_vector(0 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b : std_logic_vector (26 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_a : std_logic_vector(24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_b : std_logic_vector(24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_o : std_logic_vector (24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_q : std_logic_vector (24 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_a : std_logic_vector(33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_b : std_logic_vector(33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_o : std_logic_vector (33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_a : std_logic_vector(40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_b : std_logic_vector(40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_o : std_logic_vector (40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_q : std_logic_vector (40 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector(54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector(54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o : std_logic_vector (54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (54 downto 0); signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in : std_logic_vector (95 downto 0); signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b : std_logic_vector (51 downto 0); signal pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (16 downto 0); signal InvExc_N_uid21_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid21_fpSqrtTest_q : std_logic_vector(0 downto 0); signal s1_uid75_uid78_sqrtPolynomialEvaluator_q : std_logic_vector (25 downto 0); signal s2_uid81_uid84_sqrtPolynomialEvaluator_q : std_logic_vector (34 downto 0); signal s3_uid87_uid90_sqrtPolynomialEvaluator_q : std_logic_vector (41 downto 0); signal add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (60 downto 0); signal lowRangeB_uid99_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0); signal lowRangeB_uid99_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0); signal highBBits_uid100_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0); signal highBBits_uid100_sqrtPolynomialEvaluator_b : std_logic_vector (49 downto 0); signal exc_R_uid24_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_c : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_q : std_logic_vector(0 downto 0); signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0); signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (14 downto 0); signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (14 downto 0); signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0); signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (59 downto 0); signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (42 downto 0); signal spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (15 downto 0); signal pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (17 downto 0); begin --VCC(CONSTANT,1) VCC_q <= "1"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable(LOGICAL,408) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q <= not ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor(LOGICAL,435) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q <= not (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a or ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top(CONSTANT,431) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q <= "011000"; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp(LOGICAL,432) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q <= "1" when ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a = ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b else "0"; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg(REG,433) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q; END IF; END IF; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena(REG,436) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd(LOGICAL,437) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b <= en; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a and ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b; --signX_uid8_fpSqrtTest(BITSELECT,7)@0 signX_uid8_fpSqrtTest_in <= a; signX_uid8_fpSqrtTest_b <= signX_uid8_fpSqrtTest_in(63 downto 63); --cstAllZWE_uid11_fpSqrtTest(CONSTANT,10) cstAllZWE_uid11_fpSqrtTest_q <= "00000000000"; --expX_uid6_fpSqrtTest(BITSELECT,5)@0 expX_uid6_fpSqrtTest_in <= a(62 downto 0); expX_uid6_fpSqrtTest_b <= expX_uid6_fpSqrtTest_in(62 downto 52); --expXIsZero_uid13_fpSqrtTest(LOGICAL,12)@0 expXIsZero_uid13_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b; expXIsZero_uid13_fpSqrtTest_b <= cstAllZWE_uid11_fpSqrtTest_q; expXIsZero_uid13_fpSqrtTest_q <= "1" when expXIsZero_uid13_fpSqrtTest_a = expXIsZero_uid13_fpSqrtTest_b else "0"; --negZero_uid56_fpSqrtTest(LOGICAL,55)@0 negZero_uid56_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q; negZero_uid56_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; negZero_uid56_fpSqrtTest_q_i <= negZero_uid56_fpSqrtTest_a and negZero_uid56_fpSqrtTest_b; negZero_uid56_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => negZero_uid56_fpSqrtTest_q, xin => negZero_uid56_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg(DELAY,425) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => negZero_uid56_fpSqrtTest_q, xout => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt(COUNTER,427) -- every=1, low=0, high=24, step=1, init=1 ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i = 23 THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '1'; ELSE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i - 24; ELSE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i,5)); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg(REG,428) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q; END IF; END IF; END PROCESS; --xIn(GPIN,3)@0 --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux(MUX,429) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s <= en; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux: PROCESS (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q) BEGIN CASE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s IS WHEN "0" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q; WHEN "1" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q; WHEN OTHERS => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem(DUALMEM,426) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 25, width_b => 1, widthad_b => 5, numwords_b => 25, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq, address_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa, data_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia ); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 <= areset; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq(0 downto 0); --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor(LOGICAL,422) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q <= not (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a or ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top(CONSTANT,405) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q <= "010111"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp(LOGICAL,406) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q <= "1" when ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a = ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b else "0"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg(REG,407) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena(REG,423) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q = "1") THEN ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd(LOGICAL,424) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b <= en; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a and ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b; --cstAllOWE_uid9_fpSqrtTest(CONSTANT,8) cstAllOWE_uid9_fpSqrtTest_q <= "11111111111"; --sBiasM1_uid28_fpSqrtTest(CONSTANT,27) sBiasM1_uid28_fpSqrtTest_q <= "01111111110"; --expOddSig_uid29_fpSqrtTest(ADD,28)@0 expOddSig_uid29_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b); expOddSig_uid29_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBiasM1_uid28_fpSqrtTest_q); expOddSig_uid29_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid29_fpSqrtTest_a) + UNSIGNED(expOddSig_uid29_fpSqrtTest_b)); expOddSig_uid29_fpSqrtTest_q <= expOddSig_uid29_fpSqrtTest_o(11 downto 0); --expROdd_uid30_fpSqrtTest(BITSELECT,29)@0 expROdd_uid30_fpSqrtTest_in <= expOddSig_uid29_fpSqrtTest_q; expROdd_uid30_fpSqrtTest_b <= expROdd_uid30_fpSqrtTest_in(11 downto 1); --sBias_uid25_fpSqrtTest(CONSTANT,24) sBias_uid25_fpSqrtTest_q <= "01111111111"; --expEvenSig_uid26_fpSqrtTest(ADD,25)@0 expEvenSig_uid26_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b); expEvenSig_uid26_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBias_uid25_fpSqrtTest_q); expEvenSig_uid26_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid26_fpSqrtTest_a) + UNSIGNED(expEvenSig_uid26_fpSqrtTest_b)); expEvenSig_uid26_fpSqrtTest_q <= expEvenSig_uid26_fpSqrtTest_o(11 downto 0); --expREven_uid27_fpSqrtTest(BITSELECT,26)@0 expREven_uid27_fpSqrtTest_in <= expEvenSig_uid26_fpSqrtTest_q; expREven_uid27_fpSqrtTest_b <= expREven_uid27_fpSqrtTest_in(11 downto 1); --expX0_uid31_fpSqrtTest(BITSELECT,30)@0 expX0_uid31_fpSqrtTest_in <= expX_uid6_fpSqrtTest_b(0 downto 0); expX0_uid31_fpSqrtTest_b <= expX0_uid31_fpSqrtTest_in(0 downto 0); --expOddSelect_uid32_fpSqrtTest(LOGICAL,31)@0 expOddSelect_uid32_fpSqrtTest_a <= expX0_uid31_fpSqrtTest_b; expOddSelect_uid32_fpSqrtTest_q <= not expOddSelect_uid32_fpSqrtTest_a; --expRMux_uid33_fpSqrtTest(MUX,32)@0 expRMux_uid33_fpSqrtTest_s <= expOddSelect_uid32_fpSqrtTest_q; expRMux_uid33_fpSqrtTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRMux_uid33_fpSqrtTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE expRMux_uid33_fpSqrtTest_s IS WHEN "0" => expRMux_uid33_fpSqrtTest_q <= expREven_uid27_fpSqrtTest_b; WHEN "1" => expRMux_uid33_fpSqrtTest_q <= expROdd_uid30_fpSqrtTest_b; WHEN OTHERS => expRMux_uid33_fpSqrtTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d(DELAY,248)@1 ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => expRMux_uid33_fpSqrtTest_q, xout => ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, ena => en(0), clk => clk, aclr => areset ); --ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b(DELAY,245)@0 ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signX_uid8_fpSqrtTest_b, xout => ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset ); --cstAllZWF_uid10_fpSqrtTest(CONSTANT,9) cstAllZWF_uid10_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000000"; --fracX_uid7_fpSqrtTest(BITSELECT,6)@0 fracX_uid7_fpSqrtTest_in <= a(51 downto 0); fracX_uid7_fpSqrtTest_b <= fracX_uid7_fpSqrtTest_in(51 downto 0); --fracXIsZero_uid17_fpSqrtTest(LOGICAL,16)@0 fracXIsZero_uid17_fpSqrtTest_a <= fracX_uid7_fpSqrtTest_b; fracXIsZero_uid17_fpSqrtTest_b <= cstAllZWF_uid10_fpSqrtTest_q; fracXIsZero_uid17_fpSqrtTest_q <= "1" when fracXIsZero_uid17_fpSqrtTest_a = fracXIsZero_uid17_fpSqrtTest_b else "0"; --InvFracXIsZero_uid19_fpSqrtTest(LOGICAL,18)@0 InvFracXIsZero_uid19_fpSqrtTest_a <= fracXIsZero_uid17_fpSqrtTest_q; InvFracXIsZero_uid19_fpSqrtTest_q <= not InvFracXIsZero_uid19_fpSqrtTest_a; --expXIsMax_uid15_fpSqrtTest(LOGICAL,14)@0 expXIsMax_uid15_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b; expXIsMax_uid15_fpSqrtTest_b <= cstAllOWE_uid9_fpSqrtTest_q; expXIsMax_uid15_fpSqrtTest_q <= "1" when expXIsMax_uid15_fpSqrtTest_a = expXIsMax_uid15_fpSqrtTest_b else "0"; --exc_N_uid20_fpSqrtTest(LOGICAL,19)@0 exc_N_uid20_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q; exc_N_uid20_fpSqrtTest_b <= InvFracXIsZero_uid19_fpSqrtTest_q; exc_N_uid20_fpSqrtTest_q <= exc_N_uid20_fpSqrtTest_a and exc_N_uid20_fpSqrtTest_b; --InvExc_N_uid21_fpSqrtTest(LOGICAL,20)@0 InvExc_N_uid21_fpSqrtTest_a <= exc_N_uid20_fpSqrtTest_q; InvExc_N_uid21_fpSqrtTest_q <= not InvExc_N_uid21_fpSqrtTest_a; --exc_I_uid18_fpSqrtTest(LOGICAL,17)@0 exc_I_uid18_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q; exc_I_uid18_fpSqrtTest_b <= fracXIsZero_uid17_fpSqrtTest_q; exc_I_uid18_fpSqrtTest_q <= exc_I_uid18_fpSqrtTest_a and exc_I_uid18_fpSqrtTest_b; --InvExc_I_uid22_fpSqrtTest(LOGICAL,21)@0 InvExc_I_uid22_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; InvExc_I_uid22_fpSqrtTest_q <= not InvExc_I_uid22_fpSqrtTest_a; --InvExpXIsZero_uid23_fpSqrtTest(LOGICAL,22)@0 InvExpXIsZero_uid23_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q; InvExpXIsZero_uid23_fpSqrtTest_q <= not InvExpXIsZero_uid23_fpSqrtTest_a; --exc_R_uid24_fpSqrtTest(LOGICAL,23)@0 exc_R_uid24_fpSqrtTest_a <= InvExpXIsZero_uid23_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_b <= InvExc_I_uid22_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_c <= InvExc_N_uid21_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_q <= exc_R_uid24_fpSqrtTest_a and exc_R_uid24_fpSqrtTest_b and exc_R_uid24_fpSqrtTest_c; --minReg_uid42_fpSqrtTest(LOGICAL,41)@0 minReg_uid42_fpSqrtTest_a <= exc_R_uid24_fpSqrtTest_q; minReg_uid42_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; minReg_uid42_fpSqrtTest_q_i <= minReg_uid42_fpSqrtTest_a and minReg_uid42_fpSqrtTest_b; minReg_uid42_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => minReg_uid42_fpSqrtTest_q, xin => minReg_uid42_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --minInf_uid43_fpSqrtTest(LOGICAL,42)@0 minInf_uid43_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; minInf_uid43_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; minInf_uid43_fpSqrtTest_q_i <= minInf_uid43_fpSqrtTest_a and minInf_uid43_fpSqrtTest_b; minInf_uid43_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => minInf_uid43_fpSqrtTest_q, xin => minInf_uid43_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1(REG,155)@0 reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= exc_N_uid20_fpSqrtTest_q; END IF; END IF; END PROCESS; --excRNaN_uid44_fpSqrtTest(LOGICAL,43)@1 excRNaN_uid44_fpSqrtTest_a <= reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q; excRNaN_uid44_fpSqrtTest_b <= minInf_uid43_fpSqrtTest_q; excRNaN_uid44_fpSqrtTest_c <= minReg_uid42_fpSqrtTest_q; excRNaN_uid44_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_a or excRNaN_uid44_fpSqrtTest_b or excRNaN_uid44_fpSqrtTest_c; --InvSignX_uid40_fpSqrtTest(LOGICAL,39)@0 InvSignX_uid40_fpSqrtTest_a <= signX_uid8_fpSqrtTest_b; InvSignX_uid40_fpSqrtTest_q <= not InvSignX_uid40_fpSqrtTest_a; --inInfAndNotNeg_uid41_fpSqrtTest(LOGICAL,40)@0 inInfAndNotNeg_uid41_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; inInfAndNotNeg_uid41_fpSqrtTest_b <= InvSignX_uid40_fpSqrtTest_q; inInfAndNotNeg_uid41_fpSqrtTest_q_i <= inInfAndNotNeg_uid41_fpSqrtTest_a and inInfAndNotNeg_uid41_fpSqrtTest_b; inInfAndNotNeg_uid41_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => inInfAndNotNeg_uid41_fpSqrtTest_q, xin => inInfAndNotNeg_uid41_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0(REG,156)@0 reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= expXIsZero_uid13_fpSqrtTest_q; END IF; END IF; END PROCESS; --join_uid45_fpSqrtTest(BITJOIN,44)@1 join_uid45_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_q & inInfAndNotNeg_uid41_fpSqrtTest_q & reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q; --fracSelIn_uid46_fpSqrtTest(BITJOIN,45)@1 fracSelIn_uid46_fpSqrtTest_q <= ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q & join_uid45_fpSqrtTest_q; --fracSel_uid47_fpSqrtTest(LOOKUP,46)@1 fracSel_uid47_fpSqrtTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracSel_uid47_fpSqrtTest_q <= "01"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN CASE (fracSelIn_uid46_fpSqrtTest_q) IS WHEN "0000" => fracSel_uid47_fpSqrtTest_q <= "01"; WHEN "0001" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0010" => fracSel_uid47_fpSqrtTest_q <= "10"; WHEN "0011" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0100" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "0101" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0110" => fracSel_uid47_fpSqrtTest_q <= "10"; WHEN "0111" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "1000" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1001" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "1010" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1011" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1100" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1101" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1110" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1111" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN OTHERS => fracSel_uid47_fpSqrtTest_q <= (others => '-'); END CASE; END IF; END IF; END PROCESS; --expRPostExc_uid51_fpSqrtTest(MUX,50)@2 expRPostExc_uid51_fpSqrtTest_s <= fracSel_uid47_fpSqrtTest_q; expRPostExc_uid51_fpSqrtTest: PROCESS (expRPostExc_uid51_fpSqrtTest_s, en, cstAllZWE_uid11_fpSqrtTest_q, ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, cstAllOWE_uid9_fpSqrtTest_q, cstAllOWE_uid9_fpSqrtTest_q) BEGIN CASE expRPostExc_uid51_fpSqrtTest_s IS WHEN "00" => expRPostExc_uid51_fpSqrtTest_q <= cstAllZWE_uid11_fpSqrtTest_q; WHEN "01" => expRPostExc_uid51_fpSqrtTest_q <= ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q; WHEN "10" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q; WHEN "11" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q; WHEN OTHERS => expRPostExc_uid51_fpSqrtTest_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg(DELAY,412) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => expRPostExc_uid51_fpSqrtTest_q, xout => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt(COUNTER,401) -- every=1, low=0, high=23, step=1, init=1 ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i = 22 THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '1'; ELSE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i - 23; ELSE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i,5)); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg(REG,402) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux(MUX,403) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux: PROCESS (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q) BEGIN CASE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s IS WHEN "0" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; WHEN "1" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q; WHEN OTHERS => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem(DUALMEM,413) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 5, numwords_a => 24, width_b => 11, widthad_b => 5, numwords_b => 24, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq, address_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa, data_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia ); ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 <= areset; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq(10 downto 0); --fracNaN_uid52_fpSqrtTest(CONSTANT,51) fracNaN_uid52_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000001"; --fracXAddr_uid35_fpSqrtTest(BITSELECT,34)@0 fracXAddr_uid35_fpSqrtTest_in <= fracX_uid7_fpSqrtTest_b; fracXAddr_uid35_fpSqrtTest_b <= fracXAddr_uid35_fpSqrtTest_in(51 downto 45); --addrTable_uid36_fpSqrtTest(BITJOIN,35)@0 addrTable_uid36_fpSqrtTest_q <= expOddSelect_uid32_fpSqrtTest_q & fracXAddr_uid35_fpSqrtTest_b; --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0(REG,161)@0 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= addrTable_uid36_fpSqrtTest_q; END IF; END IF; END PROCESS; --memoryC5_uid71_sqrtTableGenerator_lutmem(DUALMEM,139)@1 memoryC5_uid71_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC5_uid71_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC5_uid71_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q; memoryC5_uid71_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 17, widthad_a => 8, numwords_a => 256, width_b => 17, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC5_uid71_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC5_uid71_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC5_uid71_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC5_uid71_sqrtTableGenerator_lutmem_iq, address_a => memoryC5_uid71_sqrtTableGenerator_lutmem_aa, data_a => memoryC5_uid71_sqrtTableGenerator_lutmem_ia ); memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC5_uid71_sqrtTableGenerator_lutmem_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_iq(16 downto 0); --reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1(REG,163)@3 reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg(DELAY,398) ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg : dspba_delay GENERIC MAP ( width => 52, depth => 1 ) PORT MAP ( xin => fracX_uid7_fpSqrtTest_b, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a(DELAY,229)@0 ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a : dspba_delay GENERIC MAP ( width => 52, depth => 2 ) PORT MAP ( xin => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset ); --FracX44dto0_uid37_fpSqrtTest(BITSELECT,36)@3 FracX44dto0_uid37_fpSqrtTest_in <= ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q(44 downto 0); FracX44dto0_uid37_fpSqrtTest_b <= FracX44dto0_uid37_fpSqrtTest_in(44 downto 0); --yT1_uid73_sqrtPolynomialEvaluator(BITSELECT,72)@3 yT1_uid73_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT1_uid73_sqrtPolynomialEvaluator_b <= yT1_uid73_sqrtPolynomialEvaluator_in(44 downto 28); --reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0(REG,162)@3 reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= yT1_uid73_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator(MULT,103)@4 prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a),18)) * SIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr,34)); END IF; END IF; END PROCESS; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator(BITSELECT,104)@7 prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in(33 downto 16); --highBBits_uid76_sqrtPolynomialEvaluator(BITSELECT,75)@7 highBBits_uid76_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b; highBBits_uid76_sqrtPolynomialEvaluator_b <= highBBits_uid76_sqrtPolynomialEvaluator_in(17 downto 1); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a(DELAY,363)@0 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0(REG,164)@3 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q; END IF; END IF; END PROCESS; --memoryC4_uid69_sqrtTableGenerator_lutmem(DUALMEM,138)@4 memoryC4_uid69_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC4_uid69_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC4_uid69_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q; memoryC4_uid69_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 8, numwords_a => 256, width_b => 24, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC4_uid69_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC4_uid69_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC4_uid69_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC4_uid69_sqrtTableGenerator_lutmem_iq, address_a => memoryC4_uid69_sqrtTableGenerator_lutmem_aa, data_a => memoryC4_uid69_sqrtTableGenerator_lutmem_ia ); memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC4_uid69_sqrtTableGenerator_lutmem_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_iq(23 downto 0); --reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0(REG,165)@6 reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid77_sqrtPolynomialEvaluator(ADD,76)@7 sumAHighB_uid77_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((24 downto 24 => reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q(23)) & reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q); sumAHighB_uid77_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((24 downto 17 => highBBits_uid76_sqrtPolynomialEvaluator_b(16)) & highBBits_uid76_sqrtPolynomialEvaluator_b); sumAHighB_uid77_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_b)); sumAHighB_uid77_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_o(24 downto 0); --lowRangeB_uid75_sqrtPolynomialEvaluator(BITSELECT,74)@7 lowRangeB_uid75_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid75_sqrtPolynomialEvaluator_b <= lowRangeB_uid75_sqrtPolynomialEvaluator_in(0 downto 0); --s1_uid75_uid78_sqrtPolynomialEvaluator(BITJOIN,77)@7 s1_uid75_uid78_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_q & lowRangeB_uid75_sqrtPolynomialEvaluator_b; --reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1(REG,167)@7 reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= s1_uid75_uid78_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor(LOGICAL,459) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a or ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg(REG,457) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= VCC_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena(REG,460) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,461) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b <= en; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b; --yT2_uid79_sqrtPolynomialEvaluator(BITSELECT,78)@3 yT2_uid79_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT2_uid79_sqrtPolynomialEvaluator_b <= yT2_uid79_sqrtPolynomialEvaluator_in(44 downto 21); --reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0(REG,166)@3 reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= yT2_uid79_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg(DELAY,451) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg : dspba_delay GENERIC MAP ( width => 24, depth => 1 ) PORT MAP ( xin => reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q, xout => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,453) -- every=1, low=0, high=1, step=1, init=1 ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i,1)); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg(REG,454) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,455) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q) BEGIN CASE ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s IS WHEN "0" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q; WHEN "1" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,452) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 1, numwords_a => 2, width_b => 24, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq, address_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa, data_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia ); ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq(23 downto 0); --prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator(MULT,106)@8 prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a),25)) * SIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr,50)); END IF; END IF; END PROCESS; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator(BITSELECT,107)@11 prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in(49 downto 23); --highBBits_uid82_sqrtPolynomialEvaluator(BITSELECT,81)@11 highBBits_uid82_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b; highBBits_uid82_sqrtPolynomialEvaluator_b <= highBBits_uid82_sqrtPolynomialEvaluator_in(26 downto 1); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor(LOGICAL,485) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,481) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q <= "0100"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,482) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b else "0"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg(REG,483) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena(REG,486) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,487) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg(DELAY,462) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q, xout => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,477) -- every=1, low=0, high=4, step=1, init=1 ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 3 THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 4; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,3)); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,478) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,479) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q) BEGIN CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q; WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,476) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 5, width_b => 8, widthad_b => 3, numwords_b => 5, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq, address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa, data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia ); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0); --memoryC3_uid67_sqrtTableGenerator_lutmem(DUALMEM,137)@8 memoryC3_uid67_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC3_uid67_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC3_uid67_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q; memoryC3_uid67_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 33, widthad_a => 8, numwords_a => 256, width_b => 33, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC3_uid67_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC3_uid67_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC3_uid67_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC3_uid67_sqrtTableGenerator_lutmem_iq, address_a => memoryC3_uid67_sqrtTableGenerator_lutmem_aa, data_a => memoryC3_uid67_sqrtTableGenerator_lutmem_ia ); memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC3_uid67_sqrtTableGenerator_lutmem_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_iq(32 downto 0); --reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0(REG,169)@10 reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid83_sqrtPolynomialEvaluator(ADD,82)@11 sumAHighB_uid83_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((33 downto 33 => reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q(32)) & reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q); sumAHighB_uid83_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((33 downto 26 => highBBits_uid82_sqrtPolynomialEvaluator_b(25)) & highBBits_uid82_sqrtPolynomialEvaluator_b); sumAHighB_uid83_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_b)); sumAHighB_uid83_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_o(33 downto 0); --lowRangeB_uid81_sqrtPolynomialEvaluator(BITSELECT,80)@11 lowRangeB_uid81_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid81_sqrtPolynomialEvaluator_b <= lowRangeB_uid81_sqrtPolynomialEvaluator_in(0 downto 0); --s2_uid81_uid84_sqrtPolynomialEvaluator(BITJOIN,83)@11 s2_uid81_uid84_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_q & lowRangeB_uid81_sqrtPolynomialEvaluator_b; --reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1(REG,171)@11 reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= s2_uid81_uid84_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor(LOGICAL,524) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q <= not (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a or ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top(CONSTANT,520) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q <= "0101"; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp(LOGICAL,521) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q <= "1" when ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a = ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b else "0"; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg(REG,522) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena(REG,525) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd(LOGICAL,526) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b <= en; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a and ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b; --yT3_uid85_sqrtPolynomialEvaluator(BITSELECT,84)@3 yT3_uid85_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT3_uid85_sqrtPolynomialEvaluator_b <= yT3_uid85_sqrtPolynomialEvaluator_in(44 downto 12); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg(DELAY,514) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg : dspba_delay GENERIC MAP ( width => 33, depth => 1 ) PORT MAP ( xin => yT3_uid85_sqrtPolynomialEvaluator_b, xout => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt(COUNTER,516) -- every=1, low=0, high=5, step=1, init=1 ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i = 4 THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i - 5; ELSE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i,3)); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg(REG,517) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux(MUX,518) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s <= en; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux: PROCESS (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q) BEGIN CASE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s IS WHEN "0" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; WHEN "1" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem(DUALMEM,515) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 33, widthad_a => 3, numwords_a => 6, width_b => 33, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq, address_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa, data_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia ); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 <= areset; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq(32 downto 0); --reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0(REG,170)@11 reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q; END IF; END IF; END PROCESS; --prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator(MULT,109)@12 prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a),34)) * SIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr,68)); END IF; END IF; END PROCESS; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator(BITSELECT,110)@15 prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in(67 downto 34); --highBBits_uid88_sqrtPolynomialEvaluator(BITSELECT,87)@15 highBBits_uid88_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b; highBBits_uid88_sqrtPolynomialEvaluator_b <= highBBits_uid88_sqrtPolynomialEvaluator_in(33 downto 1); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,537) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,533) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01000"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,534) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b else "0"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,535) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,538) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,539) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,501) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,529) -- every=1, low=0, high=8, step=1, init=1 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 7 THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1'; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 8; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4)); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,530) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,531) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q) BEGIN CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,528) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 9, width_b => 8, widthad_b => 4, numwords_b => 9, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0(REG,172)@11 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC2_uid65_sqrtTableGenerator_lutmem(DUALMEM,136)@12 memoryC2_uid65_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC2_uid65_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC2_uid65_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q; memoryC2_uid65_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC2_uid65_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid65_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid65_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid65_sqrtTableGenerator_lutmem_iq, address_a => memoryC2_uid65_sqrtTableGenerator_lutmem_aa, data_a => memoryC2_uid65_sqrtTableGenerator_lutmem_ia ); memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC2_uid65_sqrtTableGenerator_lutmem_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0(REG,173)@14 reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid89_sqrtPolynomialEvaluator(ADD,88)@15 sumAHighB_uid89_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q(39)) & reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q); sumAHighB_uid89_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((40 downto 33 => highBBits_uid88_sqrtPolynomialEvaluator_b(32)) & highBBits_uid88_sqrtPolynomialEvaluator_b); sumAHighB_uid89_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_b)); sumAHighB_uid89_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_o(40 downto 0); --lowRangeB_uid87_sqrtPolynomialEvaluator(BITSELECT,86)@15 lowRangeB_uid87_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid87_sqrtPolynomialEvaluator_b <= lowRangeB_uid87_sqrtPolynomialEvaluator_in(0 downto 0); --s3_uid87_uid90_sqrtPolynomialEvaluator(BITJOIN,89)@15 s3_uid87_uid90_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_q & lowRangeB_uid87_sqrtPolynomialEvaluator_b; --yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,118)@15 yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q; yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 24); --reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9(REG,177)@15 reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor(LOGICAL,448) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top(CONSTANT,444) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q <= "01001"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp(LOGICAL,445) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b else "0"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg(REG,446) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena(REG,449) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,450) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg(DELAY,438) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => FracX44dto0_uid37_fpSqrtTest_b, xout => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,440) -- every=1, low=0, high=9, step=1, init=1 ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 8 THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1'; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 9; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i,4)); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg(REG,441) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,442) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q) BEGIN CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s IS WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q; WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q; WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,439) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 10, width_b => 45, widthad_b => 4, numwords_b => 10, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0, clock1 => clk, address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq, address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa, data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia ); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq(44 downto 0); --yT4_uid91_sqrtPolynomialEvaluator(BITSELECT,90)@15 yT4_uid91_sqrtPolynomialEvaluator_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q; yT4_uid91_sqrtPolynomialEvaluator_b <= yT4_uid91_sqrtPolynomialEvaluator_in(44 downto 5); --xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,117)@15 xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b(12 downto 0); xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in(12 downto 0); --GND(CONSTANT,0) GND_q <= "0"; --pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,120)@15 pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7(REG,176)@15 reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,116)@15 yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q(14 downto 0); yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b <= yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in(14 downto 0); --spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,119)@15 spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q <= GND_q & yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b; --pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,121)@15 pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q <= spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q & STD_LOGIC_VECTOR((1 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6(REG,175)@15 reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,115)@15 xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b; xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 22); --reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4(REG,174)@15 reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma(CHAINMULTADD,140)@16 multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0),19)); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1),19)); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0) <= RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0),38) + RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1),38); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a <= (others => (others => '0')); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c <= (others => (others => '0')); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q),18); IF (en = "1") THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0); END IF; END IF; END PROCESS; multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_delay : dspba_delay GENERIC MAP (width => 37, depth => 1) PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q, clk => clk, aclr => areset); --multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,123)@19 multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q; multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in(36 downto 2); --highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,125)@19 highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b; highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b <= highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in(34 downto 6); --yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,113)@15 yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q; yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 15); --reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1(REG,179)@15 reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,112)@15 xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b; xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 13); --reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0(REG,178)@15 reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator(MULT,114)@16 topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a),28)) * SIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= (others => '0'); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= (others => '0'); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr,54)); END IF; END IF; END PROCESS; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator(ADD,126)@19 sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q(53)) & topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b(28)) & highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b)); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o(54 downto 0); --lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,124)@19 lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b(5 downto 0); lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b <= lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in(5 downto 0); --add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,127)@19 add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q & lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b; --R_uid129_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,128)@19 R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in <= add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q(59 downto 0); R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in(59 downto 17); --reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1(REG,181)@19 reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= "0000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,511) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,507) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01100"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,508) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b else "0"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,509) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,512) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,513) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,503) -- every=1, low=0, high=12, step=1, init=1 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 11 THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1'; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 12; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4)); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,504) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,505) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q) BEGIN CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,502) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 13, width_b => 8, widthad_b => 4, numwords_b => 13, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0(REG,157)@15 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC1_uid63_sqrtTableGenerator_lutmem(DUALMEM,135)@16 memoryC1_uid63_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid63_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid63_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q; memoryC1_uid63_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 9, widthad_a => 8, numwords_a => 256, width_b => 9, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC1_uid63_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid63_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid63_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid63_sqrtTableGenerator_lutmem_iq, address_a => memoryC1_uid63_sqrtTableGenerator_lutmem_aa, data_a => memoryC1_uid63_sqrtTableGenerator_lutmem_ia ); memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC1_uid63_sqrtTableGenerator_lutmem_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_iq(8 downto 0); --reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1(REG,160)@18 reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= "000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --memoryC1_uid62_sqrtTableGenerator_lutmem(DUALMEM,134)@16 memoryC1_uid62_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid62_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid62_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q; memoryC1_uid62_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC1_uid62_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid62_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid62_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid62_sqrtTableGenerator_lutmem_iq, address_a => memoryC1_uid62_sqrtTableGenerator_lutmem_aa, data_a => memoryC1_uid62_sqrtTableGenerator_lutmem_ia ); memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC1_uid62_sqrtTableGenerator_lutmem_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0(REG,159)@18 reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --os_uid64_sqrtTableGenerator(BITJOIN,63)@19 os_uid64_sqrtTableGenerator_q <= reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q & reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q; --rndBit_uid93_sqrtPolynomialEvaluator(CONSTANT,92) rndBit_uid93_sqrtPolynomialEvaluator_q <= "01"; --cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator(BITJOIN,93)@19 cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q <= os_uid64_sqrtTableGenerator_q & rndBit_uid93_sqrtPolynomialEvaluator_q; --reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0(REG,180)@19 reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ts4_uid95_sqrtPolynomialEvaluator(ADD,94)@20 ts4_uid95_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((51 downto 51 => reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q(50)) & reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q); ts4_uid95_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((51 downto 43 => reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q(42)) & reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q); ts4_uid95_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid95_sqrtPolynomialEvaluator_a) + SIGNED(ts4_uid95_sqrtPolynomialEvaluator_b)); ts4_uid95_sqrtPolynomialEvaluator_q <= ts4_uid95_sqrtPolynomialEvaluator_o(51 downto 0); --s4_uid96_sqrtPolynomialEvaluator(BITSELECT,95)@20 s4_uid96_sqrtPolynomialEvaluator_in <= ts4_uid95_sqrtPolynomialEvaluator_q; s4_uid96_sqrtPolynomialEvaluator_b <= s4_uid96_sqrtPolynomialEvaluator_in(51 downto 1); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1(BITSELECT,144)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in <= STD_LOGIC_VECTOR((53 downto 51 => s4_uid96_sqrtPolynomialEvaluator_b(50)) & s4_uid96_sqrtPolynomialEvaluator_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in(53 downto 27); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1(REG,187)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor(LOGICAL,498) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top(CONSTANT,494) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q <= "01110"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp(LOGICAL,495) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b else "0"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg(REG,496) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena(REG,499) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd(LOGICAL,500) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt(COUNTER,490) -- every=1, low=0, high=14, step=1, init=1 ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i = 13 THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '1'; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i - 14; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i,4)); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg(REG,491) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux(MUX,492) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q) BEGIN CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s IS WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q; WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q; WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem(DUALMEM,489) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 15, width_b => 45, widthad_b => 4, numwords_b => 15, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq, address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa, data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia ); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 <= areset; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq(44 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1(BITSELECT,142)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in <= STD_LOGIC_VECTOR("000000000" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in(53 downto 27); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0(REG,184)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1(MULT,148)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr,54)); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1; END IF; END IF; END PROCESS; --ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a(DELAY,349)@24 ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a : dspba_delay GENERIC MAP ( width => 54, depth => 2 ) PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q, ena => en(0), clk => clk, aclr => areset ); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2(BITSHIFT,152)@26 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q & "000000000000000000000000000000000000000000000000000000"; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int(107 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0(BITSELECT,141)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q(26 downto 0); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in(26 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0(REG,182)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1(MULT,147)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr,54)); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0(BITSELECT,143)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in <= s4_uid96_sqrtPolynomialEvaluator_b(26 downto 0); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in(26 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1(REG,183)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0(MULT,146)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0(ADD,149)@24 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR('0' & "00" & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR((56 downto 54 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q(53)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b)); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o(55 downto 0); --ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a(DELAY,348)@24 ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a : dspba_delay GENERIC MAP ( width => 56, depth => 1 ) PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q, ena => en(0), clk => clk, aclr => areset ); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1(BITSHIFT,151)@25 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q & "000000000000000000000000000"; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int(82 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0(MULT,145)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0(BITSHIFT,150)@24 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int(53 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0(REG,188)@24 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0(ADD,153)@25 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q(82)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b)); END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o(83 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0(ADD,154)@26 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a <= STD_LOGIC_VECTOR((108 downto 84 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q(83)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b <= STD_LOGIC_VECTOR((108 downto 108 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q(107)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b)); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o(108 downto 0); --prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator(BITSELECT,130)@26 prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q(95 downto 0); prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in(95 downto 44); --highBBits_uid100_sqrtPolynomialEvaluator(BITSELECT,99)@26 highBBits_uid100_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b; highBBits_uid100_sqrtPolynomialEvaluator_b <= highBBits_uid100_sqrtPolynomialEvaluator_in(51 downto 2); --reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1(REG,196)@26 reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= highBBits_uid100_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor(LOGICAL,472) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,468) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q <= "010011"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,469) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b else "0"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg(REG,470) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena(REG,473) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,474) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,464) -- every=1, low=0, high=19, step=1, init=1 ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 18 THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 19; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,5)); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,465) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,466) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q) BEGIN CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,463) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 5, numwords_a => 20, width_b => 8, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq, address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa, data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia ); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0); --memoryC0_uid60_sqrtTableGenerator_lutmem(DUALMEM,133)@23 memoryC0_uid60_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid60_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid60_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q; memoryC0_uid60_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 17, widthad_a => 8, numwords_a => 256, width_b => 17, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC0_uid60_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid60_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid60_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid60_sqrtTableGenerator_lutmem_iq, address_a => memoryC0_uid60_sqrtTableGenerator_lutmem_aa, data_a => memoryC0_uid60_sqrtTableGenerator_lutmem_ia ); memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC0_uid60_sqrtTableGenerator_lutmem_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_iq(16 downto 0); --reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1(REG,194)@25 reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,550) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,551) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,552) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,541) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 5, numwords_a => 20, width_b => 8, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0(REG,191)@22 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC0_uid59_sqrtTableGenerator_lutmem(DUALMEM,132)@23 memoryC0_uid59_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid59_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid59_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q; memoryC0_uid59_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC0_uid59_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid59_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid59_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid59_sqrtTableGenerator_lutmem_iq, address_a => memoryC0_uid59_sqrtTableGenerator_lutmem_aa, data_a => memoryC0_uid59_sqrtTableGenerator_lutmem_ia ); memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC0_uid59_sqrtTableGenerator_lutmem_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0(REG,193)@25 reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --os_uid61_sqrtTableGenerator(BITJOIN,60)@26 os_uid61_sqrtTableGenerator_q <= reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q & reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q; --reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0(REG,195)@26 reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= os_uid61_sqrtTableGenerator_q; END IF; END IF; END PROCESS; --sumAHighB_uid101_sqrtPolynomialEvaluator(ADD,100)@27 sumAHighB_uid101_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((57 downto 57 => reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q(56)) & reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q); sumAHighB_uid101_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((57 downto 50 => reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q(49)) & reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q); sumAHighB_uid101_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_b)); sumAHighB_uid101_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_o(57 downto 0); --lowRangeB_uid99_sqrtPolynomialEvaluator(BITSELECT,98)@26 lowRangeB_uid99_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b(1 downto 0); lowRangeB_uid99_sqrtPolynomialEvaluator_b <= lowRangeB_uid99_sqrtPolynomialEvaluator_in(1 downto 0); --reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0(REG,197)@26 reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= lowRangeB_uid99_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --s5_uid99_uid102_sqrtPolynomialEvaluator(BITJOIN,101)@27 s5_uid99_uid102_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_q & reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q; --fracR_uid39_fpSqrtTest(BITSELECT,38)@27 fracR_uid39_fpSqrtTest_in <= s5_uid99_uid102_sqrtPolynomialEvaluator_q(56 downto 0); fracR_uid39_fpSqrtTest_b <= fracR_uid39_fpSqrtTest_in(56 downto 5); --reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3(REG,198)@27 reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= "0000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= fracR_uid39_fpSqrtTest_b; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor(LOGICAL,409) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q <= not (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a or ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena(REG,410) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd(LOGICAL,411) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a and ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg(DELAY,399) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => fracSel_uid47_fpSqrtTest_q, xout => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem(DUALMEM,400) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 2, widthad_a => 5, numwords_a => 24, width_b => 2, widthad_b => 5, numwords_b => 24, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq, address_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa, data_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia ); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 <= areset; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq(1 downto 0); --fracRPostExc_uid55_fpSqrtTest(MUX,54)@28 fracRPostExc_uid55_fpSqrtTest_s <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q; fracRPostExc_uid55_fpSqrtTest: PROCESS (fracRPostExc_uid55_fpSqrtTest_s, en, cstAllZWF_uid10_fpSqrtTest_q, reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q, cstAllZWF_uid10_fpSqrtTest_q, fracNaN_uid52_fpSqrtTest_q) BEGIN CASE fracRPostExc_uid55_fpSqrtTest_s IS WHEN "00" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q; WHEN "01" => fracRPostExc_uid55_fpSqrtTest_q <= reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q; WHEN "10" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q; WHEN "11" => fracRPostExc_uid55_fpSqrtTest_q <= fracNaN_uid52_fpSqrtTest_q; WHEN OTHERS => fracRPostExc_uid55_fpSqrtTest_q <= (others => '0'); END CASE; END PROCESS; --RSqrt_uid57_fpSqrtTest(BITJOIN,56)@28 RSqrt_uid57_fpSqrtTest_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q & ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q & fracRPostExc_uid55_fpSqrtTest_q; --xOut(GPOUT,4)@28 q <= RSqrt_uid57_fpSqrtTest_q; end normal;
----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Release Version 13.1 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from fp_sqrt_double_s5 -- VHDL created on Tue Apr 9 15:17:30 2013 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; entity fp_sqrt_double_s5 is port ( a : in std_logic_vector(63 downto 0); en : in std_logic_vector(0 downto 0); q : out std_logic_vector(63 downto 0); clk : in std_logic; areset : in std_logic ); end; architecture normal of fp_sqrt_double_s5 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstAllOWE_uid9_fpSqrtTest_q : std_logic_vector (10 downto 0); signal cstAllZWF_uid10_fpSqrtTest_q : std_logic_vector (51 downto 0); signal cstAllZWE_uid11_fpSqrtTest_q : std_logic_vector (10 downto 0); signal sBias_uid25_fpSqrtTest_q : std_logic_vector (10 downto 0); signal sBiasM1_uid28_fpSqrtTest_q : std_logic_vector (10 downto 0); signal expRMux_uid33_fpSqrtTest_s : std_logic_vector (0 downto 0); signal expRMux_uid33_fpSqrtTest_q : std_logic_vector (10 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_a : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_b : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_q : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_a : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_b : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_q : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_a : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_b : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_q : std_logic_vector(0 downto 0); signal fracSel_uid47_fpSqrtTest_q : std_logic_vector(1 downto 0); signal fracNaN_uid52_fpSqrtTest_q : std_logic_vector (51 downto 0); signal negZero_uid56_fpSqrtTest_a : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_b : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_q : std_logic_vector(0 downto 0); signal rndBit_uid93_sqrtPolynomialEvaluator_q : std_logic_vector (1 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a : std_logic_vector (16 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 : std_logic_vector (33 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr : SIGNED (34 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a : std_logic_vector (23 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 : std_logic_vector (49 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr : SIGNED (50 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q : std_logic_vector (49 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a : std_logic_vector (32 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 : std_logic_vector (67 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr : SIGNED (68 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q : std_logic_vector (67 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector (26 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 : std_logic_vector (53 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr : SIGNED (54 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (53 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid59_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid60_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid62_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid63_sqrtTableGenerator_lutmem_ia : std_logic_vector (8 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_iq : std_logic_vector (8 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_q : std_logic_vector (8 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC2_uid65_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC3_uid67_sqrtTableGenerator_lutmem_ia : std_logic_vector (32 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_iq : std_logic_vector (32 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_q : std_logic_vector (32 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC4_uid69_sqrtTableGenerator_lutmem_ia : std_logic_vector (23 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_iq : std_logic_vector (23 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_q : std_logic_vector (23 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC5_uid71_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0); type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type; attribute preserve : boolean; attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : signal is true; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type is array(0 to 1) of SIGNED(17 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type; attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : signal is true; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type is array(0 to 1) of SIGNED(18 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type is array(0 to 1) of SIGNED(36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type; signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s0 : std_logic_vector(36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q : std_logic_vector (36 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr : UNSIGNED (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr : UNSIGNED (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr : SIGNED (54 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr : SIGNED (54 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a : std_logic_vector(84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b : std_logic_vector(84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o : std_logic_vector (84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q : std_logic_vector (83 downto 0); signal reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q : std_logic_vector (0 downto 0); signal reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q : std_logic_vector (0 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0); signal reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q : std_logic_vector (8 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q : std_logic_vector (16 downto 0); signal reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q : std_logic_vector (16 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0); signal reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0); signal reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q : std_logic_vector (25 downto 0); signal reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0); signal reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0); signal reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q : std_logic_vector (34 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q : std_logic_vector (39 downto 0); signal reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q : std_logic_vector (17 downto 0); signal reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q : std_logic_vector (17 downto 0); signal reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q : std_logic_vector (16 downto 0); signal reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q : std_logic_vector (17 downto 0); signal reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q : std_logic_vector (26 downto 0); signal reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q : std_logic_vector (50 downto 0); signal reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q : std_logic_vector (42 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q : std_logic_vector (53 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0); signal reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q : std_logic_vector (16 downto 0); signal reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q : std_logic_vector (56 downto 0); signal reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q : std_logic_vector (49 downto 0); signal reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q : std_logic_vector (1 downto 0); signal reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q : std_logic_vector (51 downto 0); signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q : std_logic_vector (51 downto 0); signal ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q : std_logic_vector (0 downto 0); signal ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q : std_logic_vector (10 downto 0); signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q : std_logic_vector (55 downto 0); signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q : std_logic_vector (53 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0); signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q : std_logic_vector (51 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 : std_logic; signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq : std_logic; signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : signal is true; signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 : std_logic; signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : signal is true; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 : std_logic; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i : unsigned(4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq : std_logic; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q : std_logic_vector (5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : signal is true; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true; signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic; signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 : std_logic; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq : std_logic; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a : std_logic_vector(56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b : std_logic_vector(56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o : std_logic_vector (56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q : std_logic_vector (55 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal expX_uid6_fpSqrtTest_in : std_logic_vector (62 downto 0); signal expX_uid6_fpSqrtTest_b : std_logic_vector (10 downto 0); signal fracX_uid7_fpSqrtTest_in : std_logic_vector (51 downto 0); signal fracX_uid7_fpSqrtTest_b : std_logic_vector (51 downto 0); signal signX_uid8_fpSqrtTest_in : std_logic_vector (63 downto 0); signal signX_uid8_fpSqrtTest_b : std_logic_vector (0 downto 0); signal expXIsZero_uid13_fpSqrtTest_a : std_logic_vector(10 downto 0); signal expXIsZero_uid13_fpSqrtTest_b : std_logic_vector(10 downto 0); signal expXIsZero_uid13_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid15_fpSqrtTest_a : std_logic_vector(10 downto 0); signal expXIsMax_uid15_fpSqrtTest_b : std_logic_vector(10 downto 0); signal expXIsMax_uid15_fpSqrtTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid17_fpSqrtTest_a : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSqrtTest_b : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSqrtTest_q : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expEvenSig_uid26_fpSqrtTest_a : std_logic_vector(11 downto 0); signal expEvenSig_uid26_fpSqrtTest_b : std_logic_vector(11 downto 0); signal expEvenSig_uid26_fpSqrtTest_o : std_logic_vector (11 downto 0); signal expEvenSig_uid26_fpSqrtTest_q : std_logic_vector (11 downto 0); signal expOddSig_uid29_fpSqrtTest_a : std_logic_vector(11 downto 0); signal expOddSig_uid29_fpSqrtTest_b : std_logic_vector(11 downto 0); signal expOddSig_uid29_fpSqrtTest_o : std_logic_vector (11 downto 0); signal expOddSig_uid29_fpSqrtTest_q : std_logic_vector (11 downto 0); signal excRNaN_uid44_fpSqrtTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expRPostExc_uid51_fpSqrtTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid51_fpSqrtTest_q : std_logic_vector (10 downto 0); signal fracRPostExc_uid55_fpSqrtTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid55_fpSqrtTest_q : std_logic_vector (51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_a : std_logic_vector(51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_b : std_logic_vector(51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_o : std_logic_vector (51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_q : std_logic_vector (51 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_a : std_logic_vector(57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_b : std_logic_vector(57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_o : std_logic_vector (57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_q : std_logic_vector (57 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal join_uid45_fpSqrtTest_q : std_logic_vector (2 downto 0); signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0); signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in : std_logic_vector (49 downto 0); signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in : std_logic_vector (67 downto 0); signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (33 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q : std_logic_vector (53 downto 0); signal os_uid64_sqrtTableGenerator_q : std_logic_vector (48 downto 0); signal os_uid61_sqrtTableGenerator_q : std_logic_vector (56 downto 0); signal s5_uid99_uid102_sqrtPolynomialEvaluator_q : std_logic_vector (59 downto 0); signal FracX44dto0_uid37_fpSqrtTest_in : std_logic_vector (44 downto 0); signal FracX44dto0_uid37_fpSqrtTest_b : std_logic_vector (44 downto 0); signal fracSelIn_uid46_fpSqrtTest_q : std_logic_vector (3 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int : std_logic_vector (82 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q : std_logic_vector (82 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int : std_logic_vector (107 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q : std_logic_vector (107 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0); signal RSqrt_uid57_fpSqrtTest_q : std_logic_vector (63 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a : std_logic_vector(5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b : std_logic_vector(5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q : std_logic_vector(0 downto 0); signal yT4_uid91_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT4_uid91_sqrtPolynomialEvaluator_b : std_logic_vector (39 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b : std_logic_vector (26 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a : std_logic_vector(3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b : std_logic_vector(3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal expX0_uid31_fpSqrtTest_in : std_logic_vector (0 downto 0); signal expX0_uid31_fpSqrtTest_b : std_logic_vector (0 downto 0); signal fracXAddr_uid35_fpSqrtTest_in : std_logic_vector (51 downto 0); signal fracXAddr_uid35_fpSqrtTest_b : std_logic_vector (6 downto 0); signal InvSignX_uid40_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvSignX_uid40_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid22_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid22_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expREven_uid27_fpSqrtTest_in : std_logic_vector (11 downto 0); signal expREven_uid27_fpSqrtTest_b : std_logic_vector (10 downto 0); signal expROdd_uid30_fpSqrtTest_in : std_logic_vector (11 downto 0); signal expROdd_uid30_fpSqrtTest_b : std_logic_vector (10 downto 0); signal s4_uid96_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0); signal s4_uid96_sqrtPolynomialEvaluator_b : std_logic_vector (50 downto 0); signal lowRangeB_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid76_sqrtPolynomialEvaluator_in : std_logic_vector (17 downto 0); signal highBBits_uid76_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal lowRangeB_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid82_sqrtPolynomialEvaluator_in : std_logic_vector (26 downto 0); signal highBBits_uid82_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0); signal lowRangeB_uid87_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid87_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid88_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0); signal highBBits_uid88_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0); signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (5 downto 0); signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (5 downto 0); signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (34 downto 0); signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (28 downto 0); signal cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q : std_logic_vector (50 downto 0); signal fracR_uid39_fpSqrtTest_in : std_logic_vector (56 downto 0); signal fracR_uid39_fpSqrtTest_b : std_logic_vector (51 downto 0); signal yT1_uid73_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT1_uid73_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal yT2_uid79_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT2_uid79_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0); signal yT3_uid85_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT3_uid85_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a : std_logic_vector(108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b : std_logic_vector(108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o : std_logic_vector (108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q : std_logic_vector (108 downto 0); signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0); signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0); signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0); signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0); signal expOddSelect_uid32_fpSqrtTest_a : std_logic_vector(0 downto 0); signal expOddSelect_uid32_fpSqrtTest_q : std_logic_vector(0 downto 0); signal addrTable_uid36_fpSqrtTest_q : std_logic_vector (7 downto 0); signal exc_N_uid20_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_N_uid20_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_N_uid20_fpSqrtTest_q : std_logic_vector(0 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b : std_logic_vector (26 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_a : std_logic_vector(24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_b : std_logic_vector(24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_o : std_logic_vector (24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_q : std_logic_vector (24 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_a : std_logic_vector(33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_b : std_logic_vector(33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_o : std_logic_vector (33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_a : std_logic_vector(40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_b : std_logic_vector(40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_o : std_logic_vector (40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_q : std_logic_vector (40 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector(54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector(54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o : std_logic_vector (54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (54 downto 0); signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in : std_logic_vector (95 downto 0); signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b : std_logic_vector (51 downto 0); signal pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (16 downto 0); signal InvExc_N_uid21_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid21_fpSqrtTest_q : std_logic_vector(0 downto 0); signal s1_uid75_uid78_sqrtPolynomialEvaluator_q : std_logic_vector (25 downto 0); signal s2_uid81_uid84_sqrtPolynomialEvaluator_q : std_logic_vector (34 downto 0); signal s3_uid87_uid90_sqrtPolynomialEvaluator_q : std_logic_vector (41 downto 0); signal add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (60 downto 0); signal lowRangeB_uid99_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0); signal lowRangeB_uid99_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0); signal highBBits_uid100_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0); signal highBBits_uid100_sqrtPolynomialEvaluator_b : std_logic_vector (49 downto 0); signal exc_R_uid24_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_c : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_q : std_logic_vector(0 downto 0); signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0); signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (14 downto 0); signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (14 downto 0); signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0); signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (59 downto 0); signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (42 downto 0); signal spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (15 downto 0); signal pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (17 downto 0); begin --VCC(CONSTANT,1) VCC_q <= "1"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable(LOGICAL,408) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q <= not ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor(LOGICAL,435) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q <= not (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a or ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top(CONSTANT,431) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q <= "011000"; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp(LOGICAL,432) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q <= "1" when ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a = ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b else "0"; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg(REG,433) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q; END IF; END IF; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena(REG,436) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd(LOGICAL,437) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b <= en; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a and ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b; --signX_uid8_fpSqrtTest(BITSELECT,7)@0 signX_uid8_fpSqrtTest_in <= a; signX_uid8_fpSqrtTest_b <= signX_uid8_fpSqrtTest_in(63 downto 63); --cstAllZWE_uid11_fpSqrtTest(CONSTANT,10) cstAllZWE_uid11_fpSqrtTest_q <= "00000000000"; --expX_uid6_fpSqrtTest(BITSELECT,5)@0 expX_uid6_fpSqrtTest_in <= a(62 downto 0); expX_uid6_fpSqrtTest_b <= expX_uid6_fpSqrtTest_in(62 downto 52); --expXIsZero_uid13_fpSqrtTest(LOGICAL,12)@0 expXIsZero_uid13_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b; expXIsZero_uid13_fpSqrtTest_b <= cstAllZWE_uid11_fpSqrtTest_q; expXIsZero_uid13_fpSqrtTest_q <= "1" when expXIsZero_uid13_fpSqrtTest_a = expXIsZero_uid13_fpSqrtTest_b else "0"; --negZero_uid56_fpSqrtTest(LOGICAL,55)@0 negZero_uid56_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q; negZero_uid56_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; negZero_uid56_fpSqrtTest_q_i <= negZero_uid56_fpSqrtTest_a and negZero_uid56_fpSqrtTest_b; negZero_uid56_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => negZero_uid56_fpSqrtTest_q, xin => negZero_uid56_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg(DELAY,425) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => negZero_uid56_fpSqrtTest_q, xout => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt(COUNTER,427) -- every=1, low=0, high=24, step=1, init=1 ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i = 23 THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '1'; ELSE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i - 24; ELSE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i,5)); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg(REG,428) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q; END IF; END IF; END PROCESS; --xIn(GPIN,3)@0 --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux(MUX,429) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s <= en; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux: PROCESS (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q) BEGIN CASE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s IS WHEN "0" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q; WHEN "1" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q; WHEN OTHERS => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem(DUALMEM,426) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 25, width_b => 1, widthad_b => 5, numwords_b => 25, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq, address_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa, data_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia ); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 <= areset; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq(0 downto 0); --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor(LOGICAL,422) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q <= not (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a or ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top(CONSTANT,405) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q <= "010111"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp(LOGICAL,406) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q <= "1" when ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a = ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b else "0"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg(REG,407) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena(REG,423) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q = "1") THEN ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd(LOGICAL,424) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b <= en; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a and ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b; --cstAllOWE_uid9_fpSqrtTest(CONSTANT,8) cstAllOWE_uid9_fpSqrtTest_q <= "11111111111"; --sBiasM1_uid28_fpSqrtTest(CONSTANT,27) sBiasM1_uid28_fpSqrtTest_q <= "01111111110"; --expOddSig_uid29_fpSqrtTest(ADD,28)@0 expOddSig_uid29_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b); expOddSig_uid29_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBiasM1_uid28_fpSqrtTest_q); expOddSig_uid29_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid29_fpSqrtTest_a) + UNSIGNED(expOddSig_uid29_fpSqrtTest_b)); expOddSig_uid29_fpSqrtTest_q <= expOddSig_uid29_fpSqrtTest_o(11 downto 0); --expROdd_uid30_fpSqrtTest(BITSELECT,29)@0 expROdd_uid30_fpSqrtTest_in <= expOddSig_uid29_fpSqrtTest_q; expROdd_uid30_fpSqrtTest_b <= expROdd_uid30_fpSqrtTest_in(11 downto 1); --sBias_uid25_fpSqrtTest(CONSTANT,24) sBias_uid25_fpSqrtTest_q <= "01111111111"; --expEvenSig_uid26_fpSqrtTest(ADD,25)@0 expEvenSig_uid26_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b); expEvenSig_uid26_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBias_uid25_fpSqrtTest_q); expEvenSig_uid26_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid26_fpSqrtTest_a) + UNSIGNED(expEvenSig_uid26_fpSqrtTest_b)); expEvenSig_uid26_fpSqrtTest_q <= expEvenSig_uid26_fpSqrtTest_o(11 downto 0); --expREven_uid27_fpSqrtTest(BITSELECT,26)@0 expREven_uid27_fpSqrtTest_in <= expEvenSig_uid26_fpSqrtTest_q; expREven_uid27_fpSqrtTest_b <= expREven_uid27_fpSqrtTest_in(11 downto 1); --expX0_uid31_fpSqrtTest(BITSELECT,30)@0 expX0_uid31_fpSqrtTest_in <= expX_uid6_fpSqrtTest_b(0 downto 0); expX0_uid31_fpSqrtTest_b <= expX0_uid31_fpSqrtTest_in(0 downto 0); --expOddSelect_uid32_fpSqrtTest(LOGICAL,31)@0 expOddSelect_uid32_fpSqrtTest_a <= expX0_uid31_fpSqrtTest_b; expOddSelect_uid32_fpSqrtTest_q <= not expOddSelect_uid32_fpSqrtTest_a; --expRMux_uid33_fpSqrtTest(MUX,32)@0 expRMux_uid33_fpSqrtTest_s <= expOddSelect_uid32_fpSqrtTest_q; expRMux_uid33_fpSqrtTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRMux_uid33_fpSqrtTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE expRMux_uid33_fpSqrtTest_s IS WHEN "0" => expRMux_uid33_fpSqrtTest_q <= expREven_uid27_fpSqrtTest_b; WHEN "1" => expRMux_uid33_fpSqrtTest_q <= expROdd_uid30_fpSqrtTest_b; WHEN OTHERS => expRMux_uid33_fpSqrtTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d(DELAY,248)@1 ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => expRMux_uid33_fpSqrtTest_q, xout => ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, ena => en(0), clk => clk, aclr => areset ); --ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b(DELAY,245)@0 ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signX_uid8_fpSqrtTest_b, xout => ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset ); --cstAllZWF_uid10_fpSqrtTest(CONSTANT,9) cstAllZWF_uid10_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000000"; --fracX_uid7_fpSqrtTest(BITSELECT,6)@0 fracX_uid7_fpSqrtTest_in <= a(51 downto 0); fracX_uid7_fpSqrtTest_b <= fracX_uid7_fpSqrtTest_in(51 downto 0); --fracXIsZero_uid17_fpSqrtTest(LOGICAL,16)@0 fracXIsZero_uid17_fpSqrtTest_a <= fracX_uid7_fpSqrtTest_b; fracXIsZero_uid17_fpSqrtTest_b <= cstAllZWF_uid10_fpSqrtTest_q; fracXIsZero_uid17_fpSqrtTest_q <= "1" when fracXIsZero_uid17_fpSqrtTest_a = fracXIsZero_uid17_fpSqrtTest_b else "0"; --InvFracXIsZero_uid19_fpSqrtTest(LOGICAL,18)@0 InvFracXIsZero_uid19_fpSqrtTest_a <= fracXIsZero_uid17_fpSqrtTest_q; InvFracXIsZero_uid19_fpSqrtTest_q <= not InvFracXIsZero_uid19_fpSqrtTest_a; --expXIsMax_uid15_fpSqrtTest(LOGICAL,14)@0 expXIsMax_uid15_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b; expXIsMax_uid15_fpSqrtTest_b <= cstAllOWE_uid9_fpSqrtTest_q; expXIsMax_uid15_fpSqrtTest_q <= "1" when expXIsMax_uid15_fpSqrtTest_a = expXIsMax_uid15_fpSqrtTest_b else "0"; --exc_N_uid20_fpSqrtTest(LOGICAL,19)@0 exc_N_uid20_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q; exc_N_uid20_fpSqrtTest_b <= InvFracXIsZero_uid19_fpSqrtTest_q; exc_N_uid20_fpSqrtTest_q <= exc_N_uid20_fpSqrtTest_a and exc_N_uid20_fpSqrtTest_b; --InvExc_N_uid21_fpSqrtTest(LOGICAL,20)@0 InvExc_N_uid21_fpSqrtTest_a <= exc_N_uid20_fpSqrtTest_q; InvExc_N_uid21_fpSqrtTest_q <= not InvExc_N_uid21_fpSqrtTest_a; --exc_I_uid18_fpSqrtTest(LOGICAL,17)@0 exc_I_uid18_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q; exc_I_uid18_fpSqrtTest_b <= fracXIsZero_uid17_fpSqrtTest_q; exc_I_uid18_fpSqrtTest_q <= exc_I_uid18_fpSqrtTest_a and exc_I_uid18_fpSqrtTest_b; --InvExc_I_uid22_fpSqrtTest(LOGICAL,21)@0 InvExc_I_uid22_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; InvExc_I_uid22_fpSqrtTest_q <= not InvExc_I_uid22_fpSqrtTest_a; --InvExpXIsZero_uid23_fpSqrtTest(LOGICAL,22)@0 InvExpXIsZero_uid23_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q; InvExpXIsZero_uid23_fpSqrtTest_q <= not InvExpXIsZero_uid23_fpSqrtTest_a; --exc_R_uid24_fpSqrtTest(LOGICAL,23)@0 exc_R_uid24_fpSqrtTest_a <= InvExpXIsZero_uid23_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_b <= InvExc_I_uid22_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_c <= InvExc_N_uid21_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_q <= exc_R_uid24_fpSqrtTest_a and exc_R_uid24_fpSqrtTest_b and exc_R_uid24_fpSqrtTest_c; --minReg_uid42_fpSqrtTest(LOGICAL,41)@0 minReg_uid42_fpSqrtTest_a <= exc_R_uid24_fpSqrtTest_q; minReg_uid42_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; minReg_uid42_fpSqrtTest_q_i <= minReg_uid42_fpSqrtTest_a and minReg_uid42_fpSqrtTest_b; minReg_uid42_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => minReg_uid42_fpSqrtTest_q, xin => minReg_uid42_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --minInf_uid43_fpSqrtTest(LOGICAL,42)@0 minInf_uid43_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; minInf_uid43_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; minInf_uid43_fpSqrtTest_q_i <= minInf_uid43_fpSqrtTest_a and minInf_uid43_fpSqrtTest_b; minInf_uid43_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => minInf_uid43_fpSqrtTest_q, xin => minInf_uid43_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1(REG,155)@0 reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= exc_N_uid20_fpSqrtTest_q; END IF; END IF; END PROCESS; --excRNaN_uid44_fpSqrtTest(LOGICAL,43)@1 excRNaN_uid44_fpSqrtTest_a <= reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q; excRNaN_uid44_fpSqrtTest_b <= minInf_uid43_fpSqrtTest_q; excRNaN_uid44_fpSqrtTest_c <= minReg_uid42_fpSqrtTest_q; excRNaN_uid44_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_a or excRNaN_uid44_fpSqrtTest_b or excRNaN_uid44_fpSqrtTest_c; --InvSignX_uid40_fpSqrtTest(LOGICAL,39)@0 InvSignX_uid40_fpSqrtTest_a <= signX_uid8_fpSqrtTest_b; InvSignX_uid40_fpSqrtTest_q <= not InvSignX_uid40_fpSqrtTest_a; --inInfAndNotNeg_uid41_fpSqrtTest(LOGICAL,40)@0 inInfAndNotNeg_uid41_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; inInfAndNotNeg_uid41_fpSqrtTest_b <= InvSignX_uid40_fpSqrtTest_q; inInfAndNotNeg_uid41_fpSqrtTest_q_i <= inInfAndNotNeg_uid41_fpSqrtTest_a and inInfAndNotNeg_uid41_fpSqrtTest_b; inInfAndNotNeg_uid41_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => inInfAndNotNeg_uid41_fpSqrtTest_q, xin => inInfAndNotNeg_uid41_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0(REG,156)@0 reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= expXIsZero_uid13_fpSqrtTest_q; END IF; END IF; END PROCESS; --join_uid45_fpSqrtTest(BITJOIN,44)@1 join_uid45_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_q & inInfAndNotNeg_uid41_fpSqrtTest_q & reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q; --fracSelIn_uid46_fpSqrtTest(BITJOIN,45)@1 fracSelIn_uid46_fpSqrtTest_q <= ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q & join_uid45_fpSqrtTest_q; --fracSel_uid47_fpSqrtTest(LOOKUP,46)@1 fracSel_uid47_fpSqrtTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracSel_uid47_fpSqrtTest_q <= "01"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN CASE (fracSelIn_uid46_fpSqrtTest_q) IS WHEN "0000" => fracSel_uid47_fpSqrtTest_q <= "01"; WHEN "0001" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0010" => fracSel_uid47_fpSqrtTest_q <= "10"; WHEN "0011" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0100" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "0101" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0110" => fracSel_uid47_fpSqrtTest_q <= "10"; WHEN "0111" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "1000" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1001" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "1010" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1011" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1100" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1101" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1110" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1111" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN OTHERS => fracSel_uid47_fpSqrtTest_q <= (others => '-'); END CASE; END IF; END IF; END PROCESS; --expRPostExc_uid51_fpSqrtTest(MUX,50)@2 expRPostExc_uid51_fpSqrtTest_s <= fracSel_uid47_fpSqrtTest_q; expRPostExc_uid51_fpSqrtTest: PROCESS (expRPostExc_uid51_fpSqrtTest_s, en, cstAllZWE_uid11_fpSqrtTest_q, ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, cstAllOWE_uid9_fpSqrtTest_q, cstAllOWE_uid9_fpSqrtTest_q) BEGIN CASE expRPostExc_uid51_fpSqrtTest_s IS WHEN "00" => expRPostExc_uid51_fpSqrtTest_q <= cstAllZWE_uid11_fpSqrtTest_q; WHEN "01" => expRPostExc_uid51_fpSqrtTest_q <= ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q; WHEN "10" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q; WHEN "11" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q; WHEN OTHERS => expRPostExc_uid51_fpSqrtTest_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg(DELAY,412) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => expRPostExc_uid51_fpSqrtTest_q, xout => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt(COUNTER,401) -- every=1, low=0, high=23, step=1, init=1 ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i = 22 THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '1'; ELSE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i - 23; ELSE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i,5)); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg(REG,402) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux(MUX,403) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux: PROCESS (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q) BEGIN CASE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s IS WHEN "0" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; WHEN "1" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q; WHEN OTHERS => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem(DUALMEM,413) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 5, numwords_a => 24, width_b => 11, widthad_b => 5, numwords_b => 24, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq, address_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa, data_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia ); ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 <= areset; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq(10 downto 0); --fracNaN_uid52_fpSqrtTest(CONSTANT,51) fracNaN_uid52_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000001"; --fracXAddr_uid35_fpSqrtTest(BITSELECT,34)@0 fracXAddr_uid35_fpSqrtTest_in <= fracX_uid7_fpSqrtTest_b; fracXAddr_uid35_fpSqrtTest_b <= fracXAddr_uid35_fpSqrtTest_in(51 downto 45); --addrTable_uid36_fpSqrtTest(BITJOIN,35)@0 addrTable_uid36_fpSqrtTest_q <= expOddSelect_uid32_fpSqrtTest_q & fracXAddr_uid35_fpSqrtTest_b; --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0(REG,161)@0 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= addrTable_uid36_fpSqrtTest_q; END IF; END IF; END PROCESS; --memoryC5_uid71_sqrtTableGenerator_lutmem(DUALMEM,139)@1 memoryC5_uid71_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC5_uid71_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC5_uid71_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q; memoryC5_uid71_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 17, widthad_a => 8, numwords_a => 256, width_b => 17, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC5_uid71_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC5_uid71_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC5_uid71_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC5_uid71_sqrtTableGenerator_lutmem_iq, address_a => memoryC5_uid71_sqrtTableGenerator_lutmem_aa, data_a => memoryC5_uid71_sqrtTableGenerator_lutmem_ia ); memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC5_uid71_sqrtTableGenerator_lutmem_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_iq(16 downto 0); --reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1(REG,163)@3 reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg(DELAY,398) ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg : dspba_delay GENERIC MAP ( width => 52, depth => 1 ) PORT MAP ( xin => fracX_uid7_fpSqrtTest_b, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a(DELAY,229)@0 ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a : dspba_delay GENERIC MAP ( width => 52, depth => 2 ) PORT MAP ( xin => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset ); --FracX44dto0_uid37_fpSqrtTest(BITSELECT,36)@3 FracX44dto0_uid37_fpSqrtTest_in <= ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q(44 downto 0); FracX44dto0_uid37_fpSqrtTest_b <= FracX44dto0_uid37_fpSqrtTest_in(44 downto 0); --yT1_uid73_sqrtPolynomialEvaluator(BITSELECT,72)@3 yT1_uid73_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT1_uid73_sqrtPolynomialEvaluator_b <= yT1_uid73_sqrtPolynomialEvaluator_in(44 downto 28); --reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0(REG,162)@3 reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= yT1_uid73_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator(MULT,103)@4 prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a),18)) * SIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr,34)); END IF; END IF; END PROCESS; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator(BITSELECT,104)@7 prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in(33 downto 16); --highBBits_uid76_sqrtPolynomialEvaluator(BITSELECT,75)@7 highBBits_uid76_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b; highBBits_uid76_sqrtPolynomialEvaluator_b <= highBBits_uid76_sqrtPolynomialEvaluator_in(17 downto 1); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a(DELAY,363)@0 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0(REG,164)@3 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q; END IF; END IF; END PROCESS; --memoryC4_uid69_sqrtTableGenerator_lutmem(DUALMEM,138)@4 memoryC4_uid69_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC4_uid69_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC4_uid69_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q; memoryC4_uid69_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 8, numwords_a => 256, width_b => 24, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC4_uid69_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC4_uid69_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC4_uid69_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC4_uid69_sqrtTableGenerator_lutmem_iq, address_a => memoryC4_uid69_sqrtTableGenerator_lutmem_aa, data_a => memoryC4_uid69_sqrtTableGenerator_lutmem_ia ); memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC4_uid69_sqrtTableGenerator_lutmem_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_iq(23 downto 0); --reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0(REG,165)@6 reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid77_sqrtPolynomialEvaluator(ADD,76)@7 sumAHighB_uid77_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((24 downto 24 => reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q(23)) & reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q); sumAHighB_uid77_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((24 downto 17 => highBBits_uid76_sqrtPolynomialEvaluator_b(16)) & highBBits_uid76_sqrtPolynomialEvaluator_b); sumAHighB_uid77_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_b)); sumAHighB_uid77_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_o(24 downto 0); --lowRangeB_uid75_sqrtPolynomialEvaluator(BITSELECT,74)@7 lowRangeB_uid75_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid75_sqrtPolynomialEvaluator_b <= lowRangeB_uid75_sqrtPolynomialEvaluator_in(0 downto 0); --s1_uid75_uid78_sqrtPolynomialEvaluator(BITJOIN,77)@7 s1_uid75_uid78_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_q & lowRangeB_uid75_sqrtPolynomialEvaluator_b; --reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1(REG,167)@7 reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= s1_uid75_uid78_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor(LOGICAL,459) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a or ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg(REG,457) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= VCC_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena(REG,460) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,461) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b <= en; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b; --yT2_uid79_sqrtPolynomialEvaluator(BITSELECT,78)@3 yT2_uid79_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT2_uid79_sqrtPolynomialEvaluator_b <= yT2_uid79_sqrtPolynomialEvaluator_in(44 downto 21); --reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0(REG,166)@3 reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= yT2_uid79_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg(DELAY,451) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg : dspba_delay GENERIC MAP ( width => 24, depth => 1 ) PORT MAP ( xin => reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q, xout => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,453) -- every=1, low=0, high=1, step=1, init=1 ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i,1)); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg(REG,454) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,455) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q) BEGIN CASE ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s IS WHEN "0" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q; WHEN "1" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,452) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 1, numwords_a => 2, width_b => 24, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq, address_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa, data_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia ); ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq(23 downto 0); --prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator(MULT,106)@8 prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a),25)) * SIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr,50)); END IF; END IF; END PROCESS; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator(BITSELECT,107)@11 prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in(49 downto 23); --highBBits_uid82_sqrtPolynomialEvaluator(BITSELECT,81)@11 highBBits_uid82_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b; highBBits_uid82_sqrtPolynomialEvaluator_b <= highBBits_uid82_sqrtPolynomialEvaluator_in(26 downto 1); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor(LOGICAL,485) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,481) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q <= "0100"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,482) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b else "0"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg(REG,483) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena(REG,486) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,487) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg(DELAY,462) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q, xout => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,477) -- every=1, low=0, high=4, step=1, init=1 ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 3 THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 4; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,3)); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,478) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,479) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q) BEGIN CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q; WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,476) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 5, width_b => 8, widthad_b => 3, numwords_b => 5, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq, address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa, data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia ); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0); --memoryC3_uid67_sqrtTableGenerator_lutmem(DUALMEM,137)@8 memoryC3_uid67_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC3_uid67_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC3_uid67_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q; memoryC3_uid67_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 33, widthad_a => 8, numwords_a => 256, width_b => 33, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC3_uid67_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC3_uid67_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC3_uid67_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC3_uid67_sqrtTableGenerator_lutmem_iq, address_a => memoryC3_uid67_sqrtTableGenerator_lutmem_aa, data_a => memoryC3_uid67_sqrtTableGenerator_lutmem_ia ); memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC3_uid67_sqrtTableGenerator_lutmem_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_iq(32 downto 0); --reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0(REG,169)@10 reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid83_sqrtPolynomialEvaluator(ADD,82)@11 sumAHighB_uid83_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((33 downto 33 => reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q(32)) & reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q); sumAHighB_uid83_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((33 downto 26 => highBBits_uid82_sqrtPolynomialEvaluator_b(25)) & highBBits_uid82_sqrtPolynomialEvaluator_b); sumAHighB_uid83_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_b)); sumAHighB_uid83_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_o(33 downto 0); --lowRangeB_uid81_sqrtPolynomialEvaluator(BITSELECT,80)@11 lowRangeB_uid81_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid81_sqrtPolynomialEvaluator_b <= lowRangeB_uid81_sqrtPolynomialEvaluator_in(0 downto 0); --s2_uid81_uid84_sqrtPolynomialEvaluator(BITJOIN,83)@11 s2_uid81_uid84_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_q & lowRangeB_uid81_sqrtPolynomialEvaluator_b; --reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1(REG,171)@11 reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= s2_uid81_uid84_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor(LOGICAL,524) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q <= not (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a or ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top(CONSTANT,520) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q <= "0101"; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp(LOGICAL,521) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q <= "1" when ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a = ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b else "0"; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg(REG,522) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena(REG,525) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd(LOGICAL,526) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b <= en; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a and ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b; --yT3_uid85_sqrtPolynomialEvaluator(BITSELECT,84)@3 yT3_uid85_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT3_uid85_sqrtPolynomialEvaluator_b <= yT3_uid85_sqrtPolynomialEvaluator_in(44 downto 12); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg(DELAY,514) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg : dspba_delay GENERIC MAP ( width => 33, depth => 1 ) PORT MAP ( xin => yT3_uid85_sqrtPolynomialEvaluator_b, xout => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt(COUNTER,516) -- every=1, low=0, high=5, step=1, init=1 ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i = 4 THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i - 5; ELSE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i,3)); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg(REG,517) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux(MUX,518) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s <= en; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux: PROCESS (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q) BEGIN CASE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s IS WHEN "0" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; WHEN "1" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem(DUALMEM,515) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 33, widthad_a => 3, numwords_a => 6, width_b => 33, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq, address_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa, data_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia ); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 <= areset; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq(32 downto 0); --reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0(REG,170)@11 reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q; END IF; END IF; END PROCESS; --prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator(MULT,109)@12 prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a),34)) * SIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr,68)); END IF; END IF; END PROCESS; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator(BITSELECT,110)@15 prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in(67 downto 34); --highBBits_uid88_sqrtPolynomialEvaluator(BITSELECT,87)@15 highBBits_uid88_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b; highBBits_uid88_sqrtPolynomialEvaluator_b <= highBBits_uid88_sqrtPolynomialEvaluator_in(33 downto 1); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,537) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,533) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01000"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,534) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b else "0"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,535) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,538) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,539) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,501) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,529) -- every=1, low=0, high=8, step=1, init=1 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 7 THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1'; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 8; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4)); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,530) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,531) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q) BEGIN CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,528) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 9, width_b => 8, widthad_b => 4, numwords_b => 9, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0(REG,172)@11 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC2_uid65_sqrtTableGenerator_lutmem(DUALMEM,136)@12 memoryC2_uid65_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC2_uid65_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC2_uid65_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q; memoryC2_uid65_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC2_uid65_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid65_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid65_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid65_sqrtTableGenerator_lutmem_iq, address_a => memoryC2_uid65_sqrtTableGenerator_lutmem_aa, data_a => memoryC2_uid65_sqrtTableGenerator_lutmem_ia ); memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC2_uid65_sqrtTableGenerator_lutmem_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0(REG,173)@14 reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid89_sqrtPolynomialEvaluator(ADD,88)@15 sumAHighB_uid89_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q(39)) & reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q); sumAHighB_uid89_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((40 downto 33 => highBBits_uid88_sqrtPolynomialEvaluator_b(32)) & highBBits_uid88_sqrtPolynomialEvaluator_b); sumAHighB_uid89_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_b)); sumAHighB_uid89_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_o(40 downto 0); --lowRangeB_uid87_sqrtPolynomialEvaluator(BITSELECT,86)@15 lowRangeB_uid87_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid87_sqrtPolynomialEvaluator_b <= lowRangeB_uid87_sqrtPolynomialEvaluator_in(0 downto 0); --s3_uid87_uid90_sqrtPolynomialEvaluator(BITJOIN,89)@15 s3_uid87_uid90_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_q & lowRangeB_uid87_sqrtPolynomialEvaluator_b; --yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,118)@15 yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q; yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 24); --reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9(REG,177)@15 reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor(LOGICAL,448) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top(CONSTANT,444) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q <= "01001"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp(LOGICAL,445) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b else "0"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg(REG,446) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena(REG,449) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,450) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg(DELAY,438) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => FracX44dto0_uid37_fpSqrtTest_b, xout => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,440) -- every=1, low=0, high=9, step=1, init=1 ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 8 THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1'; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 9; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i,4)); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg(REG,441) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,442) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q) BEGIN CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s IS WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q; WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q; WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,439) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 10, width_b => 45, widthad_b => 4, numwords_b => 10, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0, clock1 => clk, address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq, address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa, data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia ); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq(44 downto 0); --yT4_uid91_sqrtPolynomialEvaluator(BITSELECT,90)@15 yT4_uid91_sqrtPolynomialEvaluator_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q; yT4_uid91_sqrtPolynomialEvaluator_b <= yT4_uid91_sqrtPolynomialEvaluator_in(44 downto 5); --xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,117)@15 xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b(12 downto 0); xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in(12 downto 0); --GND(CONSTANT,0) GND_q <= "0"; --pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,120)@15 pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7(REG,176)@15 reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,116)@15 yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q(14 downto 0); yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b <= yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in(14 downto 0); --spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,119)@15 spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q <= GND_q & yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b; --pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,121)@15 pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q <= spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q & STD_LOGIC_VECTOR((1 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6(REG,175)@15 reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,115)@15 xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b; xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 22); --reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4(REG,174)@15 reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma(CHAINMULTADD,140)@16 multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0),19)); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1),19)); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0) <= RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0),38) + RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1),38); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a <= (others => (others => '0')); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c <= (others => (others => '0')); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q),18); IF (en = "1") THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0); END IF; END IF; END PROCESS; multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_delay : dspba_delay GENERIC MAP (width => 37, depth => 1) PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q, clk => clk, aclr => areset); --multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,123)@19 multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q; multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in(36 downto 2); --highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,125)@19 highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b; highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b <= highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in(34 downto 6); --yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,113)@15 yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q; yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 15); --reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1(REG,179)@15 reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,112)@15 xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b; xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 13); --reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0(REG,178)@15 reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator(MULT,114)@16 topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a),28)) * SIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= (others => '0'); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= (others => '0'); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr,54)); END IF; END IF; END PROCESS; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator(ADD,126)@19 sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q(53)) & topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b(28)) & highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b)); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o(54 downto 0); --lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,124)@19 lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b(5 downto 0); lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b <= lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in(5 downto 0); --add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,127)@19 add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q & lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b; --R_uid129_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,128)@19 R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in <= add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q(59 downto 0); R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in(59 downto 17); --reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1(REG,181)@19 reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= "0000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,511) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,507) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01100"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,508) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b else "0"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,509) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,512) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,513) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,503) -- every=1, low=0, high=12, step=1, init=1 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 11 THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1'; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 12; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4)); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,504) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,505) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q) BEGIN CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,502) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 13, width_b => 8, widthad_b => 4, numwords_b => 13, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0(REG,157)@15 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC1_uid63_sqrtTableGenerator_lutmem(DUALMEM,135)@16 memoryC1_uid63_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid63_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid63_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q; memoryC1_uid63_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 9, widthad_a => 8, numwords_a => 256, width_b => 9, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC1_uid63_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid63_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid63_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid63_sqrtTableGenerator_lutmem_iq, address_a => memoryC1_uid63_sqrtTableGenerator_lutmem_aa, data_a => memoryC1_uid63_sqrtTableGenerator_lutmem_ia ); memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC1_uid63_sqrtTableGenerator_lutmem_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_iq(8 downto 0); --reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1(REG,160)@18 reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= "000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --memoryC1_uid62_sqrtTableGenerator_lutmem(DUALMEM,134)@16 memoryC1_uid62_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid62_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid62_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q; memoryC1_uid62_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC1_uid62_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid62_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid62_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid62_sqrtTableGenerator_lutmem_iq, address_a => memoryC1_uid62_sqrtTableGenerator_lutmem_aa, data_a => memoryC1_uid62_sqrtTableGenerator_lutmem_ia ); memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC1_uid62_sqrtTableGenerator_lutmem_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0(REG,159)@18 reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --os_uid64_sqrtTableGenerator(BITJOIN,63)@19 os_uid64_sqrtTableGenerator_q <= reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q & reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q; --rndBit_uid93_sqrtPolynomialEvaluator(CONSTANT,92) rndBit_uid93_sqrtPolynomialEvaluator_q <= "01"; --cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator(BITJOIN,93)@19 cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q <= os_uid64_sqrtTableGenerator_q & rndBit_uid93_sqrtPolynomialEvaluator_q; --reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0(REG,180)@19 reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ts4_uid95_sqrtPolynomialEvaluator(ADD,94)@20 ts4_uid95_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((51 downto 51 => reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q(50)) & reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q); ts4_uid95_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((51 downto 43 => reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q(42)) & reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q); ts4_uid95_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid95_sqrtPolynomialEvaluator_a) + SIGNED(ts4_uid95_sqrtPolynomialEvaluator_b)); ts4_uid95_sqrtPolynomialEvaluator_q <= ts4_uid95_sqrtPolynomialEvaluator_o(51 downto 0); --s4_uid96_sqrtPolynomialEvaluator(BITSELECT,95)@20 s4_uid96_sqrtPolynomialEvaluator_in <= ts4_uid95_sqrtPolynomialEvaluator_q; s4_uid96_sqrtPolynomialEvaluator_b <= s4_uid96_sqrtPolynomialEvaluator_in(51 downto 1); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1(BITSELECT,144)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in <= STD_LOGIC_VECTOR((53 downto 51 => s4_uid96_sqrtPolynomialEvaluator_b(50)) & s4_uid96_sqrtPolynomialEvaluator_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in(53 downto 27); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1(REG,187)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor(LOGICAL,498) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top(CONSTANT,494) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q <= "01110"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp(LOGICAL,495) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b else "0"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg(REG,496) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena(REG,499) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd(LOGICAL,500) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt(COUNTER,490) -- every=1, low=0, high=14, step=1, init=1 ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i = 13 THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '1'; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i - 14; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i,4)); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg(REG,491) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux(MUX,492) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q) BEGIN CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s IS WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q; WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q; WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem(DUALMEM,489) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 15, width_b => 45, widthad_b => 4, numwords_b => 15, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq, address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa, data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia ); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 <= areset; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq(44 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1(BITSELECT,142)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in <= STD_LOGIC_VECTOR("000000000" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in(53 downto 27); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0(REG,184)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1(MULT,148)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr,54)); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1; END IF; END IF; END PROCESS; --ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a(DELAY,349)@24 ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a : dspba_delay GENERIC MAP ( width => 54, depth => 2 ) PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q, ena => en(0), clk => clk, aclr => areset ); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2(BITSHIFT,152)@26 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q & "000000000000000000000000000000000000000000000000000000"; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int(107 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0(BITSELECT,141)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q(26 downto 0); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in(26 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0(REG,182)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1(MULT,147)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr,54)); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0(BITSELECT,143)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in <= s4_uid96_sqrtPolynomialEvaluator_b(26 downto 0); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in(26 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1(REG,183)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0(MULT,146)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0(ADD,149)@24 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR('0' & "00" & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR((56 downto 54 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q(53)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b)); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o(55 downto 0); --ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a(DELAY,348)@24 ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a : dspba_delay GENERIC MAP ( width => 56, depth => 1 ) PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q, ena => en(0), clk => clk, aclr => areset ); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1(BITSHIFT,151)@25 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q & "000000000000000000000000000"; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int(82 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0(MULT,145)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0(BITSHIFT,150)@24 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int(53 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0(REG,188)@24 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0(ADD,153)@25 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q(82)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b)); END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o(83 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0(ADD,154)@26 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a <= STD_LOGIC_VECTOR((108 downto 84 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q(83)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b <= STD_LOGIC_VECTOR((108 downto 108 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q(107)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b)); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o(108 downto 0); --prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator(BITSELECT,130)@26 prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q(95 downto 0); prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in(95 downto 44); --highBBits_uid100_sqrtPolynomialEvaluator(BITSELECT,99)@26 highBBits_uid100_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b; highBBits_uid100_sqrtPolynomialEvaluator_b <= highBBits_uid100_sqrtPolynomialEvaluator_in(51 downto 2); --reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1(REG,196)@26 reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= highBBits_uid100_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor(LOGICAL,472) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,468) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q <= "010011"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,469) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b else "0"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg(REG,470) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena(REG,473) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,474) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,464) -- every=1, low=0, high=19, step=1, init=1 ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 18 THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 19; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,5)); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,465) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,466) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q) BEGIN CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,463) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 5, numwords_a => 20, width_b => 8, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq, address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa, data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia ); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0); --memoryC0_uid60_sqrtTableGenerator_lutmem(DUALMEM,133)@23 memoryC0_uid60_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid60_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid60_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q; memoryC0_uid60_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 17, widthad_a => 8, numwords_a => 256, width_b => 17, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC0_uid60_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid60_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid60_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid60_sqrtTableGenerator_lutmem_iq, address_a => memoryC0_uid60_sqrtTableGenerator_lutmem_aa, data_a => memoryC0_uid60_sqrtTableGenerator_lutmem_ia ); memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC0_uid60_sqrtTableGenerator_lutmem_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_iq(16 downto 0); --reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1(REG,194)@25 reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,550) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,551) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,552) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,541) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 5, numwords_a => 20, width_b => 8, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0(REG,191)@22 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC0_uid59_sqrtTableGenerator_lutmem(DUALMEM,132)@23 memoryC0_uid59_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid59_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid59_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q; memoryC0_uid59_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC0_uid59_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid59_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid59_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid59_sqrtTableGenerator_lutmem_iq, address_a => memoryC0_uid59_sqrtTableGenerator_lutmem_aa, data_a => memoryC0_uid59_sqrtTableGenerator_lutmem_ia ); memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC0_uid59_sqrtTableGenerator_lutmem_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0(REG,193)@25 reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --os_uid61_sqrtTableGenerator(BITJOIN,60)@26 os_uid61_sqrtTableGenerator_q <= reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q & reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q; --reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0(REG,195)@26 reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= os_uid61_sqrtTableGenerator_q; END IF; END IF; END PROCESS; --sumAHighB_uid101_sqrtPolynomialEvaluator(ADD,100)@27 sumAHighB_uid101_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((57 downto 57 => reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q(56)) & reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q); sumAHighB_uid101_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((57 downto 50 => reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q(49)) & reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q); sumAHighB_uid101_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_b)); sumAHighB_uid101_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_o(57 downto 0); --lowRangeB_uid99_sqrtPolynomialEvaluator(BITSELECT,98)@26 lowRangeB_uid99_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b(1 downto 0); lowRangeB_uid99_sqrtPolynomialEvaluator_b <= lowRangeB_uid99_sqrtPolynomialEvaluator_in(1 downto 0); --reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0(REG,197)@26 reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= lowRangeB_uid99_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --s5_uid99_uid102_sqrtPolynomialEvaluator(BITJOIN,101)@27 s5_uid99_uid102_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_q & reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q; --fracR_uid39_fpSqrtTest(BITSELECT,38)@27 fracR_uid39_fpSqrtTest_in <= s5_uid99_uid102_sqrtPolynomialEvaluator_q(56 downto 0); fracR_uid39_fpSqrtTest_b <= fracR_uid39_fpSqrtTest_in(56 downto 5); --reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3(REG,198)@27 reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= "0000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= fracR_uid39_fpSqrtTest_b; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor(LOGICAL,409) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q <= not (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a or ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena(REG,410) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd(LOGICAL,411) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a and ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg(DELAY,399) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => fracSel_uid47_fpSqrtTest_q, xout => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem(DUALMEM,400) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 2, widthad_a => 5, numwords_a => 24, width_b => 2, widthad_b => 5, numwords_b => 24, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq, address_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa, data_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia ); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 <= areset; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq(1 downto 0); --fracRPostExc_uid55_fpSqrtTest(MUX,54)@28 fracRPostExc_uid55_fpSqrtTest_s <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q; fracRPostExc_uid55_fpSqrtTest: PROCESS (fracRPostExc_uid55_fpSqrtTest_s, en, cstAllZWF_uid10_fpSqrtTest_q, reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q, cstAllZWF_uid10_fpSqrtTest_q, fracNaN_uid52_fpSqrtTest_q) BEGIN CASE fracRPostExc_uid55_fpSqrtTest_s IS WHEN "00" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q; WHEN "01" => fracRPostExc_uid55_fpSqrtTest_q <= reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q; WHEN "10" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q; WHEN "11" => fracRPostExc_uid55_fpSqrtTest_q <= fracNaN_uid52_fpSqrtTest_q; WHEN OTHERS => fracRPostExc_uid55_fpSqrtTest_q <= (others => '0'); END CASE; END PROCESS; --RSqrt_uid57_fpSqrtTest(BITJOIN,56)@28 RSqrt_uid57_fpSqrtTest_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q & ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q & fracRPostExc_uid55_fpSqrtTest_q; --xOut(GPOUT,4)@28 q <= RSqrt_uid57_fpSqrtTest_q; end normal;
----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Release Version 13.1 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from fp_sqrt_double_s5 -- VHDL created on Tue Apr 9 15:17:30 2013 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; entity fp_sqrt_double_s5 is port ( a : in std_logic_vector(63 downto 0); en : in std_logic_vector(0 downto 0); q : out std_logic_vector(63 downto 0); clk : in std_logic; areset : in std_logic ); end; architecture normal of fp_sqrt_double_s5 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstAllOWE_uid9_fpSqrtTest_q : std_logic_vector (10 downto 0); signal cstAllZWF_uid10_fpSqrtTest_q : std_logic_vector (51 downto 0); signal cstAllZWE_uid11_fpSqrtTest_q : std_logic_vector (10 downto 0); signal sBias_uid25_fpSqrtTest_q : std_logic_vector (10 downto 0); signal sBiasM1_uid28_fpSqrtTest_q : std_logic_vector (10 downto 0); signal expRMux_uid33_fpSqrtTest_s : std_logic_vector (0 downto 0); signal expRMux_uid33_fpSqrtTest_q : std_logic_vector (10 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_a : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_b : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_q : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_a : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_b : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_q : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_a : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_b : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_q : std_logic_vector(0 downto 0); signal fracSel_uid47_fpSqrtTest_q : std_logic_vector(1 downto 0); signal fracNaN_uid52_fpSqrtTest_q : std_logic_vector (51 downto 0); signal negZero_uid56_fpSqrtTest_a : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_b : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_q : std_logic_vector(0 downto 0); signal rndBit_uid93_sqrtPolynomialEvaluator_q : std_logic_vector (1 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a : std_logic_vector (16 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 : std_logic_vector (33 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr : SIGNED (34 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a : std_logic_vector (23 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 : std_logic_vector (49 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr : SIGNED (50 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q : std_logic_vector (49 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a : std_logic_vector (32 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 : std_logic_vector (67 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr : SIGNED (68 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q : std_logic_vector (67 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector (26 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 : std_logic_vector (53 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr : SIGNED (54 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (53 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid59_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid60_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid62_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid63_sqrtTableGenerator_lutmem_ia : std_logic_vector (8 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_iq : std_logic_vector (8 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_q : std_logic_vector (8 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC2_uid65_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC3_uid67_sqrtTableGenerator_lutmem_ia : std_logic_vector (32 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_iq : std_logic_vector (32 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_q : std_logic_vector (32 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC4_uid69_sqrtTableGenerator_lutmem_ia : std_logic_vector (23 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_iq : std_logic_vector (23 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_q : std_logic_vector (23 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC5_uid71_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0); type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type; attribute preserve : boolean; attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : signal is true; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type is array(0 to 1) of SIGNED(17 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type; attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : signal is true; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type is array(0 to 1) of SIGNED(18 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type is array(0 to 1) of SIGNED(36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type; signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s0 : std_logic_vector(36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q : std_logic_vector (36 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr : UNSIGNED (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr : UNSIGNED (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr : SIGNED (54 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr : SIGNED (54 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a : std_logic_vector(84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b : std_logic_vector(84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o : std_logic_vector (84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q : std_logic_vector (83 downto 0); signal reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q : std_logic_vector (0 downto 0); signal reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q : std_logic_vector (0 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0); signal reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q : std_logic_vector (8 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q : std_logic_vector (16 downto 0); signal reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q : std_logic_vector (16 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0); signal reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0); signal reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q : std_logic_vector (25 downto 0); signal reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0); signal reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0); signal reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q : std_logic_vector (34 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q : std_logic_vector (39 downto 0); signal reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q : std_logic_vector (17 downto 0); signal reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q : std_logic_vector (17 downto 0); signal reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q : std_logic_vector (16 downto 0); signal reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q : std_logic_vector (17 downto 0); signal reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q : std_logic_vector (26 downto 0); signal reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q : std_logic_vector (50 downto 0); signal reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q : std_logic_vector (42 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q : std_logic_vector (53 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0); signal reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q : std_logic_vector (16 downto 0); signal reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q : std_logic_vector (56 downto 0); signal reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q : std_logic_vector (49 downto 0); signal reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q : std_logic_vector (1 downto 0); signal reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q : std_logic_vector (51 downto 0); signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q : std_logic_vector (51 downto 0); signal ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q : std_logic_vector (0 downto 0); signal ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q : std_logic_vector (10 downto 0); signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q : std_logic_vector (55 downto 0); signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q : std_logic_vector (53 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0); signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q : std_logic_vector (51 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 : std_logic; signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq : std_logic; signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : signal is true; signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 : std_logic; signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : signal is true; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 : std_logic; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i : unsigned(4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq : std_logic; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q : std_logic_vector (5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : signal is true; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true; signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic; signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 : std_logic; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq : std_logic; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a : std_logic_vector(56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b : std_logic_vector(56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o : std_logic_vector (56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q : std_logic_vector (55 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal expX_uid6_fpSqrtTest_in : std_logic_vector (62 downto 0); signal expX_uid6_fpSqrtTest_b : std_logic_vector (10 downto 0); signal fracX_uid7_fpSqrtTest_in : std_logic_vector (51 downto 0); signal fracX_uid7_fpSqrtTest_b : std_logic_vector (51 downto 0); signal signX_uid8_fpSqrtTest_in : std_logic_vector (63 downto 0); signal signX_uid8_fpSqrtTest_b : std_logic_vector (0 downto 0); signal expXIsZero_uid13_fpSqrtTest_a : std_logic_vector(10 downto 0); signal expXIsZero_uid13_fpSqrtTest_b : std_logic_vector(10 downto 0); signal expXIsZero_uid13_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid15_fpSqrtTest_a : std_logic_vector(10 downto 0); signal expXIsMax_uid15_fpSqrtTest_b : std_logic_vector(10 downto 0); signal expXIsMax_uid15_fpSqrtTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid17_fpSqrtTest_a : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSqrtTest_b : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSqrtTest_q : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expEvenSig_uid26_fpSqrtTest_a : std_logic_vector(11 downto 0); signal expEvenSig_uid26_fpSqrtTest_b : std_logic_vector(11 downto 0); signal expEvenSig_uid26_fpSqrtTest_o : std_logic_vector (11 downto 0); signal expEvenSig_uid26_fpSqrtTest_q : std_logic_vector (11 downto 0); signal expOddSig_uid29_fpSqrtTest_a : std_logic_vector(11 downto 0); signal expOddSig_uid29_fpSqrtTest_b : std_logic_vector(11 downto 0); signal expOddSig_uid29_fpSqrtTest_o : std_logic_vector (11 downto 0); signal expOddSig_uid29_fpSqrtTest_q : std_logic_vector (11 downto 0); signal excRNaN_uid44_fpSqrtTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expRPostExc_uid51_fpSqrtTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid51_fpSqrtTest_q : std_logic_vector (10 downto 0); signal fracRPostExc_uid55_fpSqrtTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid55_fpSqrtTest_q : std_logic_vector (51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_a : std_logic_vector(51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_b : std_logic_vector(51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_o : std_logic_vector (51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_q : std_logic_vector (51 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_a : std_logic_vector(57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_b : std_logic_vector(57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_o : std_logic_vector (57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_q : std_logic_vector (57 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal join_uid45_fpSqrtTest_q : std_logic_vector (2 downto 0); signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0); signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in : std_logic_vector (49 downto 0); signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in : std_logic_vector (67 downto 0); signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (33 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q : std_logic_vector (53 downto 0); signal os_uid64_sqrtTableGenerator_q : std_logic_vector (48 downto 0); signal os_uid61_sqrtTableGenerator_q : std_logic_vector (56 downto 0); signal s5_uid99_uid102_sqrtPolynomialEvaluator_q : std_logic_vector (59 downto 0); signal FracX44dto0_uid37_fpSqrtTest_in : std_logic_vector (44 downto 0); signal FracX44dto0_uid37_fpSqrtTest_b : std_logic_vector (44 downto 0); signal fracSelIn_uid46_fpSqrtTest_q : std_logic_vector (3 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int : std_logic_vector (82 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q : std_logic_vector (82 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int : std_logic_vector (107 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q : std_logic_vector (107 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0); signal RSqrt_uid57_fpSqrtTest_q : std_logic_vector (63 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a : std_logic_vector(5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b : std_logic_vector(5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q : std_logic_vector(0 downto 0); signal yT4_uid91_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT4_uid91_sqrtPolynomialEvaluator_b : std_logic_vector (39 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b : std_logic_vector (26 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a : std_logic_vector(3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b : std_logic_vector(3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal expX0_uid31_fpSqrtTest_in : std_logic_vector (0 downto 0); signal expX0_uid31_fpSqrtTest_b : std_logic_vector (0 downto 0); signal fracXAddr_uid35_fpSqrtTest_in : std_logic_vector (51 downto 0); signal fracXAddr_uid35_fpSqrtTest_b : std_logic_vector (6 downto 0); signal InvSignX_uid40_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvSignX_uid40_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid22_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid22_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expREven_uid27_fpSqrtTest_in : std_logic_vector (11 downto 0); signal expREven_uid27_fpSqrtTest_b : std_logic_vector (10 downto 0); signal expROdd_uid30_fpSqrtTest_in : std_logic_vector (11 downto 0); signal expROdd_uid30_fpSqrtTest_b : std_logic_vector (10 downto 0); signal s4_uid96_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0); signal s4_uid96_sqrtPolynomialEvaluator_b : std_logic_vector (50 downto 0); signal lowRangeB_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid76_sqrtPolynomialEvaluator_in : std_logic_vector (17 downto 0); signal highBBits_uid76_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal lowRangeB_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid82_sqrtPolynomialEvaluator_in : std_logic_vector (26 downto 0); signal highBBits_uid82_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0); signal lowRangeB_uid87_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid87_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid88_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0); signal highBBits_uid88_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0); signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (5 downto 0); signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (5 downto 0); signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (34 downto 0); signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (28 downto 0); signal cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q : std_logic_vector (50 downto 0); signal fracR_uid39_fpSqrtTest_in : std_logic_vector (56 downto 0); signal fracR_uid39_fpSqrtTest_b : std_logic_vector (51 downto 0); signal yT1_uid73_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT1_uid73_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal yT2_uid79_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT2_uid79_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0); signal yT3_uid85_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT3_uid85_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a : std_logic_vector(108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b : std_logic_vector(108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o : std_logic_vector (108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q : std_logic_vector (108 downto 0); signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0); signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0); signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0); signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0); signal expOddSelect_uid32_fpSqrtTest_a : std_logic_vector(0 downto 0); signal expOddSelect_uid32_fpSqrtTest_q : std_logic_vector(0 downto 0); signal addrTable_uid36_fpSqrtTest_q : std_logic_vector (7 downto 0); signal exc_N_uid20_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_N_uid20_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_N_uid20_fpSqrtTest_q : std_logic_vector(0 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b : std_logic_vector (26 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_a : std_logic_vector(24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_b : std_logic_vector(24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_o : std_logic_vector (24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_q : std_logic_vector (24 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_a : std_logic_vector(33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_b : std_logic_vector(33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_o : std_logic_vector (33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_a : std_logic_vector(40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_b : std_logic_vector(40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_o : std_logic_vector (40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_q : std_logic_vector (40 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector(54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector(54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o : std_logic_vector (54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (54 downto 0); signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in : std_logic_vector (95 downto 0); signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b : std_logic_vector (51 downto 0); signal pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (16 downto 0); signal InvExc_N_uid21_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid21_fpSqrtTest_q : std_logic_vector(0 downto 0); signal s1_uid75_uid78_sqrtPolynomialEvaluator_q : std_logic_vector (25 downto 0); signal s2_uid81_uid84_sqrtPolynomialEvaluator_q : std_logic_vector (34 downto 0); signal s3_uid87_uid90_sqrtPolynomialEvaluator_q : std_logic_vector (41 downto 0); signal add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (60 downto 0); signal lowRangeB_uid99_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0); signal lowRangeB_uid99_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0); signal highBBits_uid100_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0); signal highBBits_uid100_sqrtPolynomialEvaluator_b : std_logic_vector (49 downto 0); signal exc_R_uid24_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_c : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_q : std_logic_vector(0 downto 0); signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0); signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (14 downto 0); signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (14 downto 0); signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0); signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (59 downto 0); signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (42 downto 0); signal spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (15 downto 0); signal pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (17 downto 0); begin --VCC(CONSTANT,1) VCC_q <= "1"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable(LOGICAL,408) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q <= not ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor(LOGICAL,435) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q <= not (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a or ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top(CONSTANT,431) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q <= "011000"; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp(LOGICAL,432) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q <= "1" when ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a = ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b else "0"; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg(REG,433) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q; END IF; END IF; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena(REG,436) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd(LOGICAL,437) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b <= en; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a and ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b; --signX_uid8_fpSqrtTest(BITSELECT,7)@0 signX_uid8_fpSqrtTest_in <= a; signX_uid8_fpSqrtTest_b <= signX_uid8_fpSqrtTest_in(63 downto 63); --cstAllZWE_uid11_fpSqrtTest(CONSTANT,10) cstAllZWE_uid11_fpSqrtTest_q <= "00000000000"; --expX_uid6_fpSqrtTest(BITSELECT,5)@0 expX_uid6_fpSqrtTest_in <= a(62 downto 0); expX_uid6_fpSqrtTest_b <= expX_uid6_fpSqrtTest_in(62 downto 52); --expXIsZero_uid13_fpSqrtTest(LOGICAL,12)@0 expXIsZero_uid13_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b; expXIsZero_uid13_fpSqrtTest_b <= cstAllZWE_uid11_fpSqrtTest_q; expXIsZero_uid13_fpSqrtTest_q <= "1" when expXIsZero_uid13_fpSqrtTest_a = expXIsZero_uid13_fpSqrtTest_b else "0"; --negZero_uid56_fpSqrtTest(LOGICAL,55)@0 negZero_uid56_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q; negZero_uid56_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; negZero_uid56_fpSqrtTest_q_i <= negZero_uid56_fpSqrtTest_a and negZero_uid56_fpSqrtTest_b; negZero_uid56_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => negZero_uid56_fpSqrtTest_q, xin => negZero_uid56_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg(DELAY,425) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => negZero_uid56_fpSqrtTest_q, xout => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt(COUNTER,427) -- every=1, low=0, high=24, step=1, init=1 ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i = 23 THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '1'; ELSE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i - 24; ELSE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i,5)); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg(REG,428) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q; END IF; END IF; END PROCESS; --xIn(GPIN,3)@0 --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux(MUX,429) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s <= en; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux: PROCESS (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q) BEGIN CASE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s IS WHEN "0" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q; WHEN "1" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q; WHEN OTHERS => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem(DUALMEM,426) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 25, width_b => 1, widthad_b => 5, numwords_b => 25, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq, address_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa, data_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia ); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 <= areset; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq(0 downto 0); --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor(LOGICAL,422) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q <= not (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a or ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top(CONSTANT,405) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q <= "010111"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp(LOGICAL,406) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q <= "1" when ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a = ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b else "0"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg(REG,407) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena(REG,423) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q = "1") THEN ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd(LOGICAL,424) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b <= en; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a and ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b; --cstAllOWE_uid9_fpSqrtTest(CONSTANT,8) cstAllOWE_uid9_fpSqrtTest_q <= "11111111111"; --sBiasM1_uid28_fpSqrtTest(CONSTANT,27) sBiasM1_uid28_fpSqrtTest_q <= "01111111110"; --expOddSig_uid29_fpSqrtTest(ADD,28)@0 expOddSig_uid29_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b); expOddSig_uid29_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBiasM1_uid28_fpSqrtTest_q); expOddSig_uid29_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid29_fpSqrtTest_a) + UNSIGNED(expOddSig_uid29_fpSqrtTest_b)); expOddSig_uid29_fpSqrtTest_q <= expOddSig_uid29_fpSqrtTest_o(11 downto 0); --expROdd_uid30_fpSqrtTest(BITSELECT,29)@0 expROdd_uid30_fpSqrtTest_in <= expOddSig_uid29_fpSqrtTest_q; expROdd_uid30_fpSqrtTest_b <= expROdd_uid30_fpSqrtTest_in(11 downto 1); --sBias_uid25_fpSqrtTest(CONSTANT,24) sBias_uid25_fpSqrtTest_q <= "01111111111"; --expEvenSig_uid26_fpSqrtTest(ADD,25)@0 expEvenSig_uid26_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b); expEvenSig_uid26_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBias_uid25_fpSqrtTest_q); expEvenSig_uid26_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid26_fpSqrtTest_a) + UNSIGNED(expEvenSig_uid26_fpSqrtTest_b)); expEvenSig_uid26_fpSqrtTest_q <= expEvenSig_uid26_fpSqrtTest_o(11 downto 0); --expREven_uid27_fpSqrtTest(BITSELECT,26)@0 expREven_uid27_fpSqrtTest_in <= expEvenSig_uid26_fpSqrtTest_q; expREven_uid27_fpSqrtTest_b <= expREven_uid27_fpSqrtTest_in(11 downto 1); --expX0_uid31_fpSqrtTest(BITSELECT,30)@0 expX0_uid31_fpSqrtTest_in <= expX_uid6_fpSqrtTest_b(0 downto 0); expX0_uid31_fpSqrtTest_b <= expX0_uid31_fpSqrtTest_in(0 downto 0); --expOddSelect_uid32_fpSqrtTest(LOGICAL,31)@0 expOddSelect_uid32_fpSqrtTest_a <= expX0_uid31_fpSqrtTest_b; expOddSelect_uid32_fpSqrtTest_q <= not expOddSelect_uid32_fpSqrtTest_a; --expRMux_uid33_fpSqrtTest(MUX,32)@0 expRMux_uid33_fpSqrtTest_s <= expOddSelect_uid32_fpSqrtTest_q; expRMux_uid33_fpSqrtTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRMux_uid33_fpSqrtTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE expRMux_uid33_fpSqrtTest_s IS WHEN "0" => expRMux_uid33_fpSqrtTest_q <= expREven_uid27_fpSqrtTest_b; WHEN "1" => expRMux_uid33_fpSqrtTest_q <= expROdd_uid30_fpSqrtTest_b; WHEN OTHERS => expRMux_uid33_fpSqrtTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d(DELAY,248)@1 ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => expRMux_uid33_fpSqrtTest_q, xout => ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, ena => en(0), clk => clk, aclr => areset ); --ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b(DELAY,245)@0 ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signX_uid8_fpSqrtTest_b, xout => ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset ); --cstAllZWF_uid10_fpSqrtTest(CONSTANT,9) cstAllZWF_uid10_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000000"; --fracX_uid7_fpSqrtTest(BITSELECT,6)@0 fracX_uid7_fpSqrtTest_in <= a(51 downto 0); fracX_uid7_fpSqrtTest_b <= fracX_uid7_fpSqrtTest_in(51 downto 0); --fracXIsZero_uid17_fpSqrtTest(LOGICAL,16)@0 fracXIsZero_uid17_fpSqrtTest_a <= fracX_uid7_fpSqrtTest_b; fracXIsZero_uid17_fpSqrtTest_b <= cstAllZWF_uid10_fpSqrtTest_q; fracXIsZero_uid17_fpSqrtTest_q <= "1" when fracXIsZero_uid17_fpSqrtTest_a = fracXIsZero_uid17_fpSqrtTest_b else "0"; --InvFracXIsZero_uid19_fpSqrtTest(LOGICAL,18)@0 InvFracXIsZero_uid19_fpSqrtTest_a <= fracXIsZero_uid17_fpSqrtTest_q; InvFracXIsZero_uid19_fpSqrtTest_q <= not InvFracXIsZero_uid19_fpSqrtTest_a; --expXIsMax_uid15_fpSqrtTest(LOGICAL,14)@0 expXIsMax_uid15_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b; expXIsMax_uid15_fpSqrtTest_b <= cstAllOWE_uid9_fpSqrtTest_q; expXIsMax_uid15_fpSqrtTest_q <= "1" when expXIsMax_uid15_fpSqrtTest_a = expXIsMax_uid15_fpSqrtTest_b else "0"; --exc_N_uid20_fpSqrtTest(LOGICAL,19)@0 exc_N_uid20_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q; exc_N_uid20_fpSqrtTest_b <= InvFracXIsZero_uid19_fpSqrtTest_q; exc_N_uid20_fpSqrtTest_q <= exc_N_uid20_fpSqrtTest_a and exc_N_uid20_fpSqrtTest_b; --InvExc_N_uid21_fpSqrtTest(LOGICAL,20)@0 InvExc_N_uid21_fpSqrtTest_a <= exc_N_uid20_fpSqrtTest_q; InvExc_N_uid21_fpSqrtTest_q <= not InvExc_N_uid21_fpSqrtTest_a; --exc_I_uid18_fpSqrtTest(LOGICAL,17)@0 exc_I_uid18_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q; exc_I_uid18_fpSqrtTest_b <= fracXIsZero_uid17_fpSqrtTest_q; exc_I_uid18_fpSqrtTest_q <= exc_I_uid18_fpSqrtTest_a and exc_I_uid18_fpSqrtTest_b; --InvExc_I_uid22_fpSqrtTest(LOGICAL,21)@0 InvExc_I_uid22_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; InvExc_I_uid22_fpSqrtTest_q <= not InvExc_I_uid22_fpSqrtTest_a; --InvExpXIsZero_uid23_fpSqrtTest(LOGICAL,22)@0 InvExpXIsZero_uid23_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q; InvExpXIsZero_uid23_fpSqrtTest_q <= not InvExpXIsZero_uid23_fpSqrtTest_a; --exc_R_uid24_fpSqrtTest(LOGICAL,23)@0 exc_R_uid24_fpSqrtTest_a <= InvExpXIsZero_uid23_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_b <= InvExc_I_uid22_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_c <= InvExc_N_uid21_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_q <= exc_R_uid24_fpSqrtTest_a and exc_R_uid24_fpSqrtTest_b and exc_R_uid24_fpSqrtTest_c; --minReg_uid42_fpSqrtTest(LOGICAL,41)@0 minReg_uid42_fpSqrtTest_a <= exc_R_uid24_fpSqrtTest_q; minReg_uid42_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; minReg_uid42_fpSqrtTest_q_i <= minReg_uid42_fpSqrtTest_a and minReg_uid42_fpSqrtTest_b; minReg_uid42_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => minReg_uid42_fpSqrtTest_q, xin => minReg_uid42_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --minInf_uid43_fpSqrtTest(LOGICAL,42)@0 minInf_uid43_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; minInf_uid43_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; minInf_uid43_fpSqrtTest_q_i <= minInf_uid43_fpSqrtTest_a and minInf_uid43_fpSqrtTest_b; minInf_uid43_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => minInf_uid43_fpSqrtTest_q, xin => minInf_uid43_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1(REG,155)@0 reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= exc_N_uid20_fpSqrtTest_q; END IF; END IF; END PROCESS; --excRNaN_uid44_fpSqrtTest(LOGICAL,43)@1 excRNaN_uid44_fpSqrtTest_a <= reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q; excRNaN_uid44_fpSqrtTest_b <= minInf_uid43_fpSqrtTest_q; excRNaN_uid44_fpSqrtTest_c <= minReg_uid42_fpSqrtTest_q; excRNaN_uid44_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_a or excRNaN_uid44_fpSqrtTest_b or excRNaN_uid44_fpSqrtTest_c; --InvSignX_uid40_fpSqrtTest(LOGICAL,39)@0 InvSignX_uid40_fpSqrtTest_a <= signX_uid8_fpSqrtTest_b; InvSignX_uid40_fpSqrtTest_q <= not InvSignX_uid40_fpSqrtTest_a; --inInfAndNotNeg_uid41_fpSqrtTest(LOGICAL,40)@0 inInfAndNotNeg_uid41_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; inInfAndNotNeg_uid41_fpSqrtTest_b <= InvSignX_uid40_fpSqrtTest_q; inInfAndNotNeg_uid41_fpSqrtTest_q_i <= inInfAndNotNeg_uid41_fpSqrtTest_a and inInfAndNotNeg_uid41_fpSqrtTest_b; inInfAndNotNeg_uid41_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => inInfAndNotNeg_uid41_fpSqrtTest_q, xin => inInfAndNotNeg_uid41_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0(REG,156)@0 reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= expXIsZero_uid13_fpSqrtTest_q; END IF; END IF; END PROCESS; --join_uid45_fpSqrtTest(BITJOIN,44)@1 join_uid45_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_q & inInfAndNotNeg_uid41_fpSqrtTest_q & reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q; --fracSelIn_uid46_fpSqrtTest(BITJOIN,45)@1 fracSelIn_uid46_fpSqrtTest_q <= ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q & join_uid45_fpSqrtTest_q; --fracSel_uid47_fpSqrtTest(LOOKUP,46)@1 fracSel_uid47_fpSqrtTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracSel_uid47_fpSqrtTest_q <= "01"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN CASE (fracSelIn_uid46_fpSqrtTest_q) IS WHEN "0000" => fracSel_uid47_fpSqrtTest_q <= "01"; WHEN "0001" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0010" => fracSel_uid47_fpSqrtTest_q <= "10"; WHEN "0011" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0100" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "0101" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0110" => fracSel_uid47_fpSqrtTest_q <= "10"; WHEN "0111" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "1000" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1001" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "1010" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1011" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1100" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1101" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1110" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1111" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN OTHERS => fracSel_uid47_fpSqrtTest_q <= (others => '-'); END CASE; END IF; END IF; END PROCESS; --expRPostExc_uid51_fpSqrtTest(MUX,50)@2 expRPostExc_uid51_fpSqrtTest_s <= fracSel_uid47_fpSqrtTest_q; expRPostExc_uid51_fpSqrtTest: PROCESS (expRPostExc_uid51_fpSqrtTest_s, en, cstAllZWE_uid11_fpSqrtTest_q, ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, cstAllOWE_uid9_fpSqrtTest_q, cstAllOWE_uid9_fpSqrtTest_q) BEGIN CASE expRPostExc_uid51_fpSqrtTest_s IS WHEN "00" => expRPostExc_uid51_fpSqrtTest_q <= cstAllZWE_uid11_fpSqrtTest_q; WHEN "01" => expRPostExc_uid51_fpSqrtTest_q <= ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q; WHEN "10" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q; WHEN "11" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q; WHEN OTHERS => expRPostExc_uid51_fpSqrtTest_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg(DELAY,412) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => expRPostExc_uid51_fpSqrtTest_q, xout => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt(COUNTER,401) -- every=1, low=0, high=23, step=1, init=1 ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i = 22 THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '1'; ELSE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i - 23; ELSE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i,5)); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg(REG,402) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux(MUX,403) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux: PROCESS (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q) BEGIN CASE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s IS WHEN "0" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; WHEN "1" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q; WHEN OTHERS => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem(DUALMEM,413) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 5, numwords_a => 24, width_b => 11, widthad_b => 5, numwords_b => 24, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq, address_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa, data_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia ); ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 <= areset; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq(10 downto 0); --fracNaN_uid52_fpSqrtTest(CONSTANT,51) fracNaN_uid52_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000001"; --fracXAddr_uid35_fpSqrtTest(BITSELECT,34)@0 fracXAddr_uid35_fpSqrtTest_in <= fracX_uid7_fpSqrtTest_b; fracXAddr_uid35_fpSqrtTest_b <= fracXAddr_uid35_fpSqrtTest_in(51 downto 45); --addrTable_uid36_fpSqrtTest(BITJOIN,35)@0 addrTable_uid36_fpSqrtTest_q <= expOddSelect_uid32_fpSqrtTest_q & fracXAddr_uid35_fpSqrtTest_b; --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0(REG,161)@0 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= addrTable_uid36_fpSqrtTest_q; END IF; END IF; END PROCESS; --memoryC5_uid71_sqrtTableGenerator_lutmem(DUALMEM,139)@1 memoryC5_uid71_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC5_uid71_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC5_uid71_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q; memoryC5_uid71_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 17, widthad_a => 8, numwords_a => 256, width_b => 17, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC5_uid71_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC5_uid71_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC5_uid71_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC5_uid71_sqrtTableGenerator_lutmem_iq, address_a => memoryC5_uid71_sqrtTableGenerator_lutmem_aa, data_a => memoryC5_uid71_sqrtTableGenerator_lutmem_ia ); memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC5_uid71_sqrtTableGenerator_lutmem_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_iq(16 downto 0); --reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1(REG,163)@3 reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg(DELAY,398) ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg : dspba_delay GENERIC MAP ( width => 52, depth => 1 ) PORT MAP ( xin => fracX_uid7_fpSqrtTest_b, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a(DELAY,229)@0 ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a : dspba_delay GENERIC MAP ( width => 52, depth => 2 ) PORT MAP ( xin => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset ); --FracX44dto0_uid37_fpSqrtTest(BITSELECT,36)@3 FracX44dto0_uid37_fpSqrtTest_in <= ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q(44 downto 0); FracX44dto0_uid37_fpSqrtTest_b <= FracX44dto0_uid37_fpSqrtTest_in(44 downto 0); --yT1_uid73_sqrtPolynomialEvaluator(BITSELECT,72)@3 yT1_uid73_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT1_uid73_sqrtPolynomialEvaluator_b <= yT1_uid73_sqrtPolynomialEvaluator_in(44 downto 28); --reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0(REG,162)@3 reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= yT1_uid73_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator(MULT,103)@4 prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a),18)) * SIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr,34)); END IF; END IF; END PROCESS; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator(BITSELECT,104)@7 prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in(33 downto 16); --highBBits_uid76_sqrtPolynomialEvaluator(BITSELECT,75)@7 highBBits_uid76_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b; highBBits_uid76_sqrtPolynomialEvaluator_b <= highBBits_uid76_sqrtPolynomialEvaluator_in(17 downto 1); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a(DELAY,363)@0 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0(REG,164)@3 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q; END IF; END IF; END PROCESS; --memoryC4_uid69_sqrtTableGenerator_lutmem(DUALMEM,138)@4 memoryC4_uid69_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC4_uid69_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC4_uid69_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q; memoryC4_uid69_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 8, numwords_a => 256, width_b => 24, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC4_uid69_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC4_uid69_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC4_uid69_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC4_uid69_sqrtTableGenerator_lutmem_iq, address_a => memoryC4_uid69_sqrtTableGenerator_lutmem_aa, data_a => memoryC4_uid69_sqrtTableGenerator_lutmem_ia ); memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC4_uid69_sqrtTableGenerator_lutmem_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_iq(23 downto 0); --reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0(REG,165)@6 reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid77_sqrtPolynomialEvaluator(ADD,76)@7 sumAHighB_uid77_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((24 downto 24 => reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q(23)) & reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q); sumAHighB_uid77_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((24 downto 17 => highBBits_uid76_sqrtPolynomialEvaluator_b(16)) & highBBits_uid76_sqrtPolynomialEvaluator_b); sumAHighB_uid77_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_b)); sumAHighB_uid77_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_o(24 downto 0); --lowRangeB_uid75_sqrtPolynomialEvaluator(BITSELECT,74)@7 lowRangeB_uid75_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid75_sqrtPolynomialEvaluator_b <= lowRangeB_uid75_sqrtPolynomialEvaluator_in(0 downto 0); --s1_uid75_uid78_sqrtPolynomialEvaluator(BITJOIN,77)@7 s1_uid75_uid78_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_q & lowRangeB_uid75_sqrtPolynomialEvaluator_b; --reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1(REG,167)@7 reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= s1_uid75_uid78_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor(LOGICAL,459) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a or ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg(REG,457) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= VCC_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena(REG,460) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,461) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b <= en; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b; --yT2_uid79_sqrtPolynomialEvaluator(BITSELECT,78)@3 yT2_uid79_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT2_uid79_sqrtPolynomialEvaluator_b <= yT2_uid79_sqrtPolynomialEvaluator_in(44 downto 21); --reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0(REG,166)@3 reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= yT2_uid79_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg(DELAY,451) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg : dspba_delay GENERIC MAP ( width => 24, depth => 1 ) PORT MAP ( xin => reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q, xout => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,453) -- every=1, low=0, high=1, step=1, init=1 ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i,1)); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg(REG,454) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,455) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q) BEGIN CASE ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s IS WHEN "0" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q; WHEN "1" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,452) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 1, numwords_a => 2, width_b => 24, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq, address_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa, data_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia ); ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq(23 downto 0); --prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator(MULT,106)@8 prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a),25)) * SIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr,50)); END IF; END IF; END PROCESS; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator(BITSELECT,107)@11 prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in(49 downto 23); --highBBits_uid82_sqrtPolynomialEvaluator(BITSELECT,81)@11 highBBits_uid82_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b; highBBits_uid82_sqrtPolynomialEvaluator_b <= highBBits_uid82_sqrtPolynomialEvaluator_in(26 downto 1); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor(LOGICAL,485) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,481) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q <= "0100"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,482) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b else "0"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg(REG,483) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena(REG,486) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,487) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg(DELAY,462) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q, xout => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,477) -- every=1, low=0, high=4, step=1, init=1 ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 3 THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 4; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,3)); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,478) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,479) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q) BEGIN CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q; WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,476) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 5, width_b => 8, widthad_b => 3, numwords_b => 5, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq, address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa, data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia ); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0); --memoryC3_uid67_sqrtTableGenerator_lutmem(DUALMEM,137)@8 memoryC3_uid67_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC3_uid67_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC3_uid67_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q; memoryC3_uid67_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 33, widthad_a => 8, numwords_a => 256, width_b => 33, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC3_uid67_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC3_uid67_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC3_uid67_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC3_uid67_sqrtTableGenerator_lutmem_iq, address_a => memoryC3_uid67_sqrtTableGenerator_lutmem_aa, data_a => memoryC3_uid67_sqrtTableGenerator_lutmem_ia ); memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC3_uid67_sqrtTableGenerator_lutmem_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_iq(32 downto 0); --reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0(REG,169)@10 reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid83_sqrtPolynomialEvaluator(ADD,82)@11 sumAHighB_uid83_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((33 downto 33 => reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q(32)) & reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q); sumAHighB_uid83_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((33 downto 26 => highBBits_uid82_sqrtPolynomialEvaluator_b(25)) & highBBits_uid82_sqrtPolynomialEvaluator_b); sumAHighB_uid83_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_b)); sumAHighB_uid83_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_o(33 downto 0); --lowRangeB_uid81_sqrtPolynomialEvaluator(BITSELECT,80)@11 lowRangeB_uid81_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid81_sqrtPolynomialEvaluator_b <= lowRangeB_uid81_sqrtPolynomialEvaluator_in(0 downto 0); --s2_uid81_uid84_sqrtPolynomialEvaluator(BITJOIN,83)@11 s2_uid81_uid84_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_q & lowRangeB_uid81_sqrtPolynomialEvaluator_b; --reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1(REG,171)@11 reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= s2_uid81_uid84_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor(LOGICAL,524) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q <= not (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a or ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top(CONSTANT,520) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q <= "0101"; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp(LOGICAL,521) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q <= "1" when ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a = ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b else "0"; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg(REG,522) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena(REG,525) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd(LOGICAL,526) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b <= en; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a and ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b; --yT3_uid85_sqrtPolynomialEvaluator(BITSELECT,84)@3 yT3_uid85_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT3_uid85_sqrtPolynomialEvaluator_b <= yT3_uid85_sqrtPolynomialEvaluator_in(44 downto 12); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg(DELAY,514) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg : dspba_delay GENERIC MAP ( width => 33, depth => 1 ) PORT MAP ( xin => yT3_uid85_sqrtPolynomialEvaluator_b, xout => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt(COUNTER,516) -- every=1, low=0, high=5, step=1, init=1 ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i = 4 THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i - 5; ELSE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i,3)); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg(REG,517) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux(MUX,518) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s <= en; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux: PROCESS (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q) BEGIN CASE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s IS WHEN "0" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; WHEN "1" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem(DUALMEM,515) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 33, widthad_a => 3, numwords_a => 6, width_b => 33, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq, address_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa, data_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia ); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 <= areset; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq(32 downto 0); --reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0(REG,170)@11 reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q; END IF; END IF; END PROCESS; --prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator(MULT,109)@12 prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a),34)) * SIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr,68)); END IF; END IF; END PROCESS; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator(BITSELECT,110)@15 prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in(67 downto 34); --highBBits_uid88_sqrtPolynomialEvaluator(BITSELECT,87)@15 highBBits_uid88_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b; highBBits_uid88_sqrtPolynomialEvaluator_b <= highBBits_uid88_sqrtPolynomialEvaluator_in(33 downto 1); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,537) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,533) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01000"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,534) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b else "0"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,535) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,538) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,539) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,501) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,529) -- every=1, low=0, high=8, step=1, init=1 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 7 THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1'; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 8; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4)); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,530) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,531) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q) BEGIN CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,528) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 9, width_b => 8, widthad_b => 4, numwords_b => 9, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0(REG,172)@11 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC2_uid65_sqrtTableGenerator_lutmem(DUALMEM,136)@12 memoryC2_uid65_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC2_uid65_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC2_uid65_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q; memoryC2_uid65_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC2_uid65_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid65_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid65_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid65_sqrtTableGenerator_lutmem_iq, address_a => memoryC2_uid65_sqrtTableGenerator_lutmem_aa, data_a => memoryC2_uid65_sqrtTableGenerator_lutmem_ia ); memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC2_uid65_sqrtTableGenerator_lutmem_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0(REG,173)@14 reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid89_sqrtPolynomialEvaluator(ADD,88)@15 sumAHighB_uid89_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q(39)) & reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q); sumAHighB_uid89_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((40 downto 33 => highBBits_uid88_sqrtPolynomialEvaluator_b(32)) & highBBits_uid88_sqrtPolynomialEvaluator_b); sumAHighB_uid89_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_b)); sumAHighB_uid89_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_o(40 downto 0); --lowRangeB_uid87_sqrtPolynomialEvaluator(BITSELECT,86)@15 lowRangeB_uid87_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid87_sqrtPolynomialEvaluator_b <= lowRangeB_uid87_sqrtPolynomialEvaluator_in(0 downto 0); --s3_uid87_uid90_sqrtPolynomialEvaluator(BITJOIN,89)@15 s3_uid87_uid90_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_q & lowRangeB_uid87_sqrtPolynomialEvaluator_b; --yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,118)@15 yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q; yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 24); --reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9(REG,177)@15 reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor(LOGICAL,448) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top(CONSTANT,444) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q <= "01001"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp(LOGICAL,445) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b else "0"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg(REG,446) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena(REG,449) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,450) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg(DELAY,438) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => FracX44dto0_uid37_fpSqrtTest_b, xout => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,440) -- every=1, low=0, high=9, step=1, init=1 ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 8 THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1'; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 9; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i,4)); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg(REG,441) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,442) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q) BEGIN CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s IS WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q; WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q; WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,439) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 10, width_b => 45, widthad_b => 4, numwords_b => 10, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0, clock1 => clk, address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq, address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa, data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia ); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq(44 downto 0); --yT4_uid91_sqrtPolynomialEvaluator(BITSELECT,90)@15 yT4_uid91_sqrtPolynomialEvaluator_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q; yT4_uid91_sqrtPolynomialEvaluator_b <= yT4_uid91_sqrtPolynomialEvaluator_in(44 downto 5); --xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,117)@15 xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b(12 downto 0); xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in(12 downto 0); --GND(CONSTANT,0) GND_q <= "0"; --pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,120)@15 pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7(REG,176)@15 reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,116)@15 yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q(14 downto 0); yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b <= yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in(14 downto 0); --spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,119)@15 spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q <= GND_q & yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b; --pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,121)@15 pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q <= spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q & STD_LOGIC_VECTOR((1 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6(REG,175)@15 reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,115)@15 xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b; xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 22); --reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4(REG,174)@15 reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma(CHAINMULTADD,140)@16 multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0),19)); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1),19)); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0) <= RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0),38) + RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1),38); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a <= (others => (others => '0')); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c <= (others => (others => '0')); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q),18); IF (en = "1") THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0); END IF; END IF; END PROCESS; multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_delay : dspba_delay GENERIC MAP (width => 37, depth => 1) PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q, clk => clk, aclr => areset); --multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,123)@19 multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q; multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in(36 downto 2); --highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,125)@19 highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b; highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b <= highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in(34 downto 6); --yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,113)@15 yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q; yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 15); --reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1(REG,179)@15 reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,112)@15 xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b; xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 13); --reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0(REG,178)@15 reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator(MULT,114)@16 topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a),28)) * SIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= (others => '0'); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= (others => '0'); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr,54)); END IF; END IF; END PROCESS; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator(ADD,126)@19 sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q(53)) & topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b(28)) & highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b)); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o(54 downto 0); --lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,124)@19 lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b(5 downto 0); lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b <= lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in(5 downto 0); --add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,127)@19 add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q & lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b; --R_uid129_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,128)@19 R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in <= add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q(59 downto 0); R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in(59 downto 17); --reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1(REG,181)@19 reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= "0000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,511) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,507) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01100"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,508) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b else "0"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,509) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,512) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,513) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,503) -- every=1, low=0, high=12, step=1, init=1 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 11 THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1'; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 12; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4)); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,504) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,505) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q) BEGIN CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,502) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 13, width_b => 8, widthad_b => 4, numwords_b => 13, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0(REG,157)@15 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC1_uid63_sqrtTableGenerator_lutmem(DUALMEM,135)@16 memoryC1_uid63_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid63_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid63_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q; memoryC1_uid63_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 9, widthad_a => 8, numwords_a => 256, width_b => 9, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC1_uid63_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid63_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid63_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid63_sqrtTableGenerator_lutmem_iq, address_a => memoryC1_uid63_sqrtTableGenerator_lutmem_aa, data_a => memoryC1_uid63_sqrtTableGenerator_lutmem_ia ); memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC1_uid63_sqrtTableGenerator_lutmem_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_iq(8 downto 0); --reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1(REG,160)@18 reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= "000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --memoryC1_uid62_sqrtTableGenerator_lutmem(DUALMEM,134)@16 memoryC1_uid62_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid62_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid62_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q; memoryC1_uid62_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC1_uid62_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid62_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid62_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid62_sqrtTableGenerator_lutmem_iq, address_a => memoryC1_uid62_sqrtTableGenerator_lutmem_aa, data_a => memoryC1_uid62_sqrtTableGenerator_lutmem_ia ); memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC1_uid62_sqrtTableGenerator_lutmem_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0(REG,159)@18 reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --os_uid64_sqrtTableGenerator(BITJOIN,63)@19 os_uid64_sqrtTableGenerator_q <= reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q & reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q; --rndBit_uid93_sqrtPolynomialEvaluator(CONSTANT,92) rndBit_uid93_sqrtPolynomialEvaluator_q <= "01"; --cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator(BITJOIN,93)@19 cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q <= os_uid64_sqrtTableGenerator_q & rndBit_uid93_sqrtPolynomialEvaluator_q; --reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0(REG,180)@19 reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ts4_uid95_sqrtPolynomialEvaluator(ADD,94)@20 ts4_uid95_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((51 downto 51 => reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q(50)) & reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q); ts4_uid95_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((51 downto 43 => reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q(42)) & reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q); ts4_uid95_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid95_sqrtPolynomialEvaluator_a) + SIGNED(ts4_uid95_sqrtPolynomialEvaluator_b)); ts4_uid95_sqrtPolynomialEvaluator_q <= ts4_uid95_sqrtPolynomialEvaluator_o(51 downto 0); --s4_uid96_sqrtPolynomialEvaluator(BITSELECT,95)@20 s4_uid96_sqrtPolynomialEvaluator_in <= ts4_uid95_sqrtPolynomialEvaluator_q; s4_uid96_sqrtPolynomialEvaluator_b <= s4_uid96_sqrtPolynomialEvaluator_in(51 downto 1); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1(BITSELECT,144)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in <= STD_LOGIC_VECTOR((53 downto 51 => s4_uid96_sqrtPolynomialEvaluator_b(50)) & s4_uid96_sqrtPolynomialEvaluator_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in(53 downto 27); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1(REG,187)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor(LOGICAL,498) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top(CONSTANT,494) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q <= "01110"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp(LOGICAL,495) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b else "0"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg(REG,496) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena(REG,499) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd(LOGICAL,500) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt(COUNTER,490) -- every=1, low=0, high=14, step=1, init=1 ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i = 13 THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '1'; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i - 14; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i,4)); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg(REG,491) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux(MUX,492) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q) BEGIN CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s IS WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q; WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q; WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem(DUALMEM,489) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 15, width_b => 45, widthad_b => 4, numwords_b => 15, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq, address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa, data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia ); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 <= areset; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq(44 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1(BITSELECT,142)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in <= STD_LOGIC_VECTOR("000000000" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in(53 downto 27); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0(REG,184)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1(MULT,148)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr,54)); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1; END IF; END IF; END PROCESS; --ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a(DELAY,349)@24 ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a : dspba_delay GENERIC MAP ( width => 54, depth => 2 ) PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q, ena => en(0), clk => clk, aclr => areset ); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2(BITSHIFT,152)@26 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q & "000000000000000000000000000000000000000000000000000000"; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int(107 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0(BITSELECT,141)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q(26 downto 0); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in(26 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0(REG,182)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1(MULT,147)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr,54)); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0(BITSELECT,143)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in <= s4_uid96_sqrtPolynomialEvaluator_b(26 downto 0); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in(26 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1(REG,183)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0(MULT,146)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0(ADD,149)@24 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR('0' & "00" & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR((56 downto 54 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q(53)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b)); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o(55 downto 0); --ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a(DELAY,348)@24 ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a : dspba_delay GENERIC MAP ( width => 56, depth => 1 ) PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q, ena => en(0), clk => clk, aclr => areset ); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1(BITSHIFT,151)@25 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q & "000000000000000000000000000"; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int(82 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0(MULT,145)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0(BITSHIFT,150)@24 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int(53 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0(REG,188)@24 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0(ADD,153)@25 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q(82)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b)); END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o(83 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0(ADD,154)@26 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a <= STD_LOGIC_VECTOR((108 downto 84 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q(83)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b <= STD_LOGIC_VECTOR((108 downto 108 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q(107)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b)); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o(108 downto 0); --prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator(BITSELECT,130)@26 prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q(95 downto 0); prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in(95 downto 44); --highBBits_uid100_sqrtPolynomialEvaluator(BITSELECT,99)@26 highBBits_uid100_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b; highBBits_uid100_sqrtPolynomialEvaluator_b <= highBBits_uid100_sqrtPolynomialEvaluator_in(51 downto 2); --reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1(REG,196)@26 reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= highBBits_uid100_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor(LOGICAL,472) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,468) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q <= "010011"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,469) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b else "0"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg(REG,470) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena(REG,473) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,474) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,464) -- every=1, low=0, high=19, step=1, init=1 ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 18 THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 19; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,5)); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,465) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,466) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q) BEGIN CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,463) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 5, numwords_a => 20, width_b => 8, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq, address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa, data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia ); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0); --memoryC0_uid60_sqrtTableGenerator_lutmem(DUALMEM,133)@23 memoryC0_uid60_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid60_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid60_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q; memoryC0_uid60_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 17, widthad_a => 8, numwords_a => 256, width_b => 17, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC0_uid60_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid60_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid60_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid60_sqrtTableGenerator_lutmem_iq, address_a => memoryC0_uid60_sqrtTableGenerator_lutmem_aa, data_a => memoryC0_uid60_sqrtTableGenerator_lutmem_ia ); memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC0_uid60_sqrtTableGenerator_lutmem_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_iq(16 downto 0); --reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1(REG,194)@25 reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,550) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,551) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,552) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,541) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 5, numwords_a => 20, width_b => 8, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0(REG,191)@22 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC0_uid59_sqrtTableGenerator_lutmem(DUALMEM,132)@23 memoryC0_uid59_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid59_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid59_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q; memoryC0_uid59_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC0_uid59_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid59_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid59_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid59_sqrtTableGenerator_lutmem_iq, address_a => memoryC0_uid59_sqrtTableGenerator_lutmem_aa, data_a => memoryC0_uid59_sqrtTableGenerator_lutmem_ia ); memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC0_uid59_sqrtTableGenerator_lutmem_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0(REG,193)@25 reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --os_uid61_sqrtTableGenerator(BITJOIN,60)@26 os_uid61_sqrtTableGenerator_q <= reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q & reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q; --reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0(REG,195)@26 reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= os_uid61_sqrtTableGenerator_q; END IF; END IF; END PROCESS; --sumAHighB_uid101_sqrtPolynomialEvaluator(ADD,100)@27 sumAHighB_uid101_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((57 downto 57 => reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q(56)) & reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q); sumAHighB_uid101_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((57 downto 50 => reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q(49)) & reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q); sumAHighB_uid101_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_b)); sumAHighB_uid101_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_o(57 downto 0); --lowRangeB_uid99_sqrtPolynomialEvaluator(BITSELECT,98)@26 lowRangeB_uid99_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b(1 downto 0); lowRangeB_uid99_sqrtPolynomialEvaluator_b <= lowRangeB_uid99_sqrtPolynomialEvaluator_in(1 downto 0); --reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0(REG,197)@26 reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= lowRangeB_uid99_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --s5_uid99_uid102_sqrtPolynomialEvaluator(BITJOIN,101)@27 s5_uid99_uid102_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_q & reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q; --fracR_uid39_fpSqrtTest(BITSELECT,38)@27 fracR_uid39_fpSqrtTest_in <= s5_uid99_uid102_sqrtPolynomialEvaluator_q(56 downto 0); fracR_uid39_fpSqrtTest_b <= fracR_uid39_fpSqrtTest_in(56 downto 5); --reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3(REG,198)@27 reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= "0000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= fracR_uid39_fpSqrtTest_b; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor(LOGICAL,409) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q <= not (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a or ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena(REG,410) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd(LOGICAL,411) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a and ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg(DELAY,399) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => fracSel_uid47_fpSqrtTest_q, xout => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem(DUALMEM,400) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 2, widthad_a => 5, numwords_a => 24, width_b => 2, widthad_b => 5, numwords_b => 24, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq, address_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa, data_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia ); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 <= areset; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq(1 downto 0); --fracRPostExc_uid55_fpSqrtTest(MUX,54)@28 fracRPostExc_uid55_fpSqrtTest_s <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q; fracRPostExc_uid55_fpSqrtTest: PROCESS (fracRPostExc_uid55_fpSqrtTest_s, en, cstAllZWF_uid10_fpSqrtTest_q, reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q, cstAllZWF_uid10_fpSqrtTest_q, fracNaN_uid52_fpSqrtTest_q) BEGIN CASE fracRPostExc_uid55_fpSqrtTest_s IS WHEN "00" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q; WHEN "01" => fracRPostExc_uid55_fpSqrtTest_q <= reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q; WHEN "10" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q; WHEN "11" => fracRPostExc_uid55_fpSqrtTest_q <= fracNaN_uid52_fpSqrtTest_q; WHEN OTHERS => fracRPostExc_uid55_fpSqrtTest_q <= (others => '0'); END CASE; END PROCESS; --RSqrt_uid57_fpSqrtTest(BITJOIN,56)@28 RSqrt_uid57_fpSqrtTest_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q & ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q & fracRPostExc_uid55_fpSqrtTest_q; --xOut(GPOUT,4)@28 q <= RSqrt_uid57_fpSqrtTest_q; end normal;
----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Release Version 13.1 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from fp_sqrt_double_s5 -- VHDL created on Tue Apr 9 15:17:30 2013 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; entity fp_sqrt_double_s5 is port ( a : in std_logic_vector(63 downto 0); en : in std_logic_vector(0 downto 0); q : out std_logic_vector(63 downto 0); clk : in std_logic; areset : in std_logic ); end; architecture normal of fp_sqrt_double_s5 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstAllOWE_uid9_fpSqrtTest_q : std_logic_vector (10 downto 0); signal cstAllZWF_uid10_fpSqrtTest_q : std_logic_vector (51 downto 0); signal cstAllZWE_uid11_fpSqrtTest_q : std_logic_vector (10 downto 0); signal sBias_uid25_fpSqrtTest_q : std_logic_vector (10 downto 0); signal sBiasM1_uid28_fpSqrtTest_q : std_logic_vector (10 downto 0); signal expRMux_uid33_fpSqrtTest_s : std_logic_vector (0 downto 0); signal expRMux_uid33_fpSqrtTest_q : std_logic_vector (10 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_a : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_b : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_q : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_a : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_b : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_q : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_a : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_b : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_q : std_logic_vector(0 downto 0); signal fracSel_uid47_fpSqrtTest_q : std_logic_vector(1 downto 0); signal fracNaN_uid52_fpSqrtTest_q : std_logic_vector (51 downto 0); signal negZero_uid56_fpSqrtTest_a : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_b : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_q : std_logic_vector(0 downto 0); signal rndBit_uid93_sqrtPolynomialEvaluator_q : std_logic_vector (1 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a : std_logic_vector (16 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 : std_logic_vector (33 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr : SIGNED (34 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a : std_logic_vector (23 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 : std_logic_vector (49 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr : SIGNED (50 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q : std_logic_vector (49 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a : std_logic_vector (32 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 : std_logic_vector (67 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr : SIGNED (68 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q : std_logic_vector (67 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector (26 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 : std_logic_vector (53 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr : SIGNED (54 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (53 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid59_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid60_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid62_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid63_sqrtTableGenerator_lutmem_ia : std_logic_vector (8 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_iq : std_logic_vector (8 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_q : std_logic_vector (8 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC2_uid65_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC3_uid67_sqrtTableGenerator_lutmem_ia : std_logic_vector (32 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_iq : std_logic_vector (32 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_q : std_logic_vector (32 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC4_uid69_sqrtTableGenerator_lutmem_ia : std_logic_vector (23 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_iq : std_logic_vector (23 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_q : std_logic_vector (23 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC5_uid71_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0); type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type; attribute preserve : boolean; attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : signal is true; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type is array(0 to 1) of SIGNED(17 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type; attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : signal is true; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type is array(0 to 1) of SIGNED(18 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type is array(0 to 1) of SIGNED(36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type; signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s0 : std_logic_vector(36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q : std_logic_vector (36 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr : UNSIGNED (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr : UNSIGNED (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr : SIGNED (54 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr : SIGNED (54 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a : std_logic_vector(84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b : std_logic_vector(84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o : std_logic_vector (84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q : std_logic_vector (83 downto 0); signal reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q : std_logic_vector (0 downto 0); signal reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q : std_logic_vector (0 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0); signal reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q : std_logic_vector (8 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q : std_logic_vector (16 downto 0); signal reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q : std_logic_vector (16 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0); signal reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0); signal reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q : std_logic_vector (25 downto 0); signal reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0); signal reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0); signal reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q : std_logic_vector (34 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q : std_logic_vector (39 downto 0); signal reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q : std_logic_vector (17 downto 0); signal reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q : std_logic_vector (17 downto 0); signal reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q : std_logic_vector (16 downto 0); signal reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q : std_logic_vector (17 downto 0); signal reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q : std_logic_vector (26 downto 0); signal reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q : std_logic_vector (50 downto 0); signal reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q : std_logic_vector (42 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q : std_logic_vector (53 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0); signal reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q : std_logic_vector (16 downto 0); signal reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q : std_logic_vector (56 downto 0); signal reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q : std_logic_vector (49 downto 0); signal reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q : std_logic_vector (1 downto 0); signal reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q : std_logic_vector (51 downto 0); signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q : std_logic_vector (51 downto 0); signal ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q : std_logic_vector (0 downto 0); signal ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q : std_logic_vector (10 downto 0); signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q : std_logic_vector (55 downto 0); signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q : std_logic_vector (53 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0); signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q : std_logic_vector (51 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 : std_logic; signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq : std_logic; signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : signal is true; signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 : std_logic; signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : signal is true; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 : std_logic; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i : unsigned(4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq : std_logic; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q : std_logic_vector (5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : signal is true; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true; signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic; signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 : std_logic; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq : std_logic; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a : std_logic_vector(56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b : std_logic_vector(56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o : std_logic_vector (56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q : std_logic_vector (55 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal expX_uid6_fpSqrtTest_in : std_logic_vector (62 downto 0); signal expX_uid6_fpSqrtTest_b : std_logic_vector (10 downto 0); signal fracX_uid7_fpSqrtTest_in : std_logic_vector (51 downto 0); signal fracX_uid7_fpSqrtTest_b : std_logic_vector (51 downto 0); signal signX_uid8_fpSqrtTest_in : std_logic_vector (63 downto 0); signal signX_uid8_fpSqrtTest_b : std_logic_vector (0 downto 0); signal expXIsZero_uid13_fpSqrtTest_a : std_logic_vector(10 downto 0); signal expXIsZero_uid13_fpSqrtTest_b : std_logic_vector(10 downto 0); signal expXIsZero_uid13_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid15_fpSqrtTest_a : std_logic_vector(10 downto 0); signal expXIsMax_uid15_fpSqrtTest_b : std_logic_vector(10 downto 0); signal expXIsMax_uid15_fpSqrtTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid17_fpSqrtTest_a : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSqrtTest_b : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSqrtTest_q : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expEvenSig_uid26_fpSqrtTest_a : std_logic_vector(11 downto 0); signal expEvenSig_uid26_fpSqrtTest_b : std_logic_vector(11 downto 0); signal expEvenSig_uid26_fpSqrtTest_o : std_logic_vector (11 downto 0); signal expEvenSig_uid26_fpSqrtTest_q : std_logic_vector (11 downto 0); signal expOddSig_uid29_fpSqrtTest_a : std_logic_vector(11 downto 0); signal expOddSig_uid29_fpSqrtTest_b : std_logic_vector(11 downto 0); signal expOddSig_uid29_fpSqrtTest_o : std_logic_vector (11 downto 0); signal expOddSig_uid29_fpSqrtTest_q : std_logic_vector (11 downto 0); signal excRNaN_uid44_fpSqrtTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expRPostExc_uid51_fpSqrtTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid51_fpSqrtTest_q : std_logic_vector (10 downto 0); signal fracRPostExc_uid55_fpSqrtTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid55_fpSqrtTest_q : std_logic_vector (51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_a : std_logic_vector(51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_b : std_logic_vector(51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_o : std_logic_vector (51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_q : std_logic_vector (51 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_a : std_logic_vector(57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_b : std_logic_vector(57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_o : std_logic_vector (57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_q : std_logic_vector (57 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal join_uid45_fpSqrtTest_q : std_logic_vector (2 downto 0); signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0); signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in : std_logic_vector (49 downto 0); signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in : std_logic_vector (67 downto 0); signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (33 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q : std_logic_vector (53 downto 0); signal os_uid64_sqrtTableGenerator_q : std_logic_vector (48 downto 0); signal os_uid61_sqrtTableGenerator_q : std_logic_vector (56 downto 0); signal s5_uid99_uid102_sqrtPolynomialEvaluator_q : std_logic_vector (59 downto 0); signal FracX44dto0_uid37_fpSqrtTest_in : std_logic_vector (44 downto 0); signal FracX44dto0_uid37_fpSqrtTest_b : std_logic_vector (44 downto 0); signal fracSelIn_uid46_fpSqrtTest_q : std_logic_vector (3 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int : std_logic_vector (82 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q : std_logic_vector (82 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int : std_logic_vector (107 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q : std_logic_vector (107 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0); signal RSqrt_uid57_fpSqrtTest_q : std_logic_vector (63 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a : std_logic_vector(5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b : std_logic_vector(5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q : std_logic_vector(0 downto 0); signal yT4_uid91_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT4_uid91_sqrtPolynomialEvaluator_b : std_logic_vector (39 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b : std_logic_vector (26 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a : std_logic_vector(3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b : std_logic_vector(3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal expX0_uid31_fpSqrtTest_in : std_logic_vector (0 downto 0); signal expX0_uid31_fpSqrtTest_b : std_logic_vector (0 downto 0); signal fracXAddr_uid35_fpSqrtTest_in : std_logic_vector (51 downto 0); signal fracXAddr_uid35_fpSqrtTest_b : std_logic_vector (6 downto 0); signal InvSignX_uid40_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvSignX_uid40_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid22_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid22_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expREven_uid27_fpSqrtTest_in : std_logic_vector (11 downto 0); signal expREven_uid27_fpSqrtTest_b : std_logic_vector (10 downto 0); signal expROdd_uid30_fpSqrtTest_in : std_logic_vector (11 downto 0); signal expROdd_uid30_fpSqrtTest_b : std_logic_vector (10 downto 0); signal s4_uid96_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0); signal s4_uid96_sqrtPolynomialEvaluator_b : std_logic_vector (50 downto 0); signal lowRangeB_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid76_sqrtPolynomialEvaluator_in : std_logic_vector (17 downto 0); signal highBBits_uid76_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal lowRangeB_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid82_sqrtPolynomialEvaluator_in : std_logic_vector (26 downto 0); signal highBBits_uid82_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0); signal lowRangeB_uid87_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid87_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid88_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0); signal highBBits_uid88_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0); signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (5 downto 0); signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (5 downto 0); signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (34 downto 0); signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (28 downto 0); signal cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q : std_logic_vector (50 downto 0); signal fracR_uid39_fpSqrtTest_in : std_logic_vector (56 downto 0); signal fracR_uid39_fpSqrtTest_b : std_logic_vector (51 downto 0); signal yT1_uid73_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT1_uid73_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal yT2_uid79_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT2_uid79_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0); signal yT3_uid85_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT3_uid85_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a : std_logic_vector(108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b : std_logic_vector(108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o : std_logic_vector (108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q : std_logic_vector (108 downto 0); signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0); signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0); signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0); signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0); signal expOddSelect_uid32_fpSqrtTest_a : std_logic_vector(0 downto 0); signal expOddSelect_uid32_fpSqrtTest_q : std_logic_vector(0 downto 0); signal addrTable_uid36_fpSqrtTest_q : std_logic_vector (7 downto 0); signal exc_N_uid20_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_N_uid20_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_N_uid20_fpSqrtTest_q : std_logic_vector(0 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b : std_logic_vector (26 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_a : std_logic_vector(24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_b : std_logic_vector(24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_o : std_logic_vector (24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_q : std_logic_vector (24 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_a : std_logic_vector(33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_b : std_logic_vector(33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_o : std_logic_vector (33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_a : std_logic_vector(40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_b : std_logic_vector(40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_o : std_logic_vector (40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_q : std_logic_vector (40 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector(54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector(54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o : std_logic_vector (54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (54 downto 0); signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in : std_logic_vector (95 downto 0); signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b : std_logic_vector (51 downto 0); signal pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (16 downto 0); signal InvExc_N_uid21_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid21_fpSqrtTest_q : std_logic_vector(0 downto 0); signal s1_uid75_uid78_sqrtPolynomialEvaluator_q : std_logic_vector (25 downto 0); signal s2_uid81_uid84_sqrtPolynomialEvaluator_q : std_logic_vector (34 downto 0); signal s3_uid87_uid90_sqrtPolynomialEvaluator_q : std_logic_vector (41 downto 0); signal add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (60 downto 0); signal lowRangeB_uid99_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0); signal lowRangeB_uid99_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0); signal highBBits_uid100_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0); signal highBBits_uid100_sqrtPolynomialEvaluator_b : std_logic_vector (49 downto 0); signal exc_R_uid24_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_c : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_q : std_logic_vector(0 downto 0); signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0); signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (14 downto 0); signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (14 downto 0); signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0); signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (59 downto 0); signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (42 downto 0); signal spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (15 downto 0); signal pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (17 downto 0); begin --VCC(CONSTANT,1) VCC_q <= "1"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable(LOGICAL,408) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q <= not ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor(LOGICAL,435) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q <= not (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a or ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top(CONSTANT,431) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q <= "011000"; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp(LOGICAL,432) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q <= "1" when ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a = ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b else "0"; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg(REG,433) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q; END IF; END IF; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena(REG,436) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd(LOGICAL,437) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b <= en; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a and ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b; --signX_uid8_fpSqrtTest(BITSELECT,7)@0 signX_uid8_fpSqrtTest_in <= a; signX_uid8_fpSqrtTest_b <= signX_uid8_fpSqrtTest_in(63 downto 63); --cstAllZWE_uid11_fpSqrtTest(CONSTANT,10) cstAllZWE_uid11_fpSqrtTest_q <= "00000000000"; --expX_uid6_fpSqrtTest(BITSELECT,5)@0 expX_uid6_fpSqrtTest_in <= a(62 downto 0); expX_uid6_fpSqrtTest_b <= expX_uid6_fpSqrtTest_in(62 downto 52); --expXIsZero_uid13_fpSqrtTest(LOGICAL,12)@0 expXIsZero_uid13_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b; expXIsZero_uid13_fpSqrtTest_b <= cstAllZWE_uid11_fpSqrtTest_q; expXIsZero_uid13_fpSqrtTest_q <= "1" when expXIsZero_uid13_fpSqrtTest_a = expXIsZero_uid13_fpSqrtTest_b else "0"; --negZero_uid56_fpSqrtTest(LOGICAL,55)@0 negZero_uid56_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q; negZero_uid56_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; negZero_uid56_fpSqrtTest_q_i <= negZero_uid56_fpSqrtTest_a and negZero_uid56_fpSqrtTest_b; negZero_uid56_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => negZero_uid56_fpSqrtTest_q, xin => negZero_uid56_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg(DELAY,425) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => negZero_uid56_fpSqrtTest_q, xout => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt(COUNTER,427) -- every=1, low=0, high=24, step=1, init=1 ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i = 23 THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '1'; ELSE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i - 24; ELSE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i,5)); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg(REG,428) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q; END IF; END IF; END PROCESS; --xIn(GPIN,3)@0 --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux(MUX,429) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s <= en; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux: PROCESS (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q) BEGIN CASE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s IS WHEN "0" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q; WHEN "1" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q; WHEN OTHERS => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem(DUALMEM,426) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 25, width_b => 1, widthad_b => 5, numwords_b => 25, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq, address_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa, data_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia ); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 <= areset; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq(0 downto 0); --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor(LOGICAL,422) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q <= not (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a or ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top(CONSTANT,405) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q <= "010111"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp(LOGICAL,406) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q <= "1" when ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a = ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b else "0"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg(REG,407) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena(REG,423) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q = "1") THEN ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd(LOGICAL,424) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b <= en; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a and ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b; --cstAllOWE_uid9_fpSqrtTest(CONSTANT,8) cstAllOWE_uid9_fpSqrtTest_q <= "11111111111"; --sBiasM1_uid28_fpSqrtTest(CONSTANT,27) sBiasM1_uid28_fpSqrtTest_q <= "01111111110"; --expOddSig_uid29_fpSqrtTest(ADD,28)@0 expOddSig_uid29_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b); expOddSig_uid29_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBiasM1_uid28_fpSqrtTest_q); expOddSig_uid29_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid29_fpSqrtTest_a) + UNSIGNED(expOddSig_uid29_fpSqrtTest_b)); expOddSig_uid29_fpSqrtTest_q <= expOddSig_uid29_fpSqrtTest_o(11 downto 0); --expROdd_uid30_fpSqrtTest(BITSELECT,29)@0 expROdd_uid30_fpSqrtTest_in <= expOddSig_uid29_fpSqrtTest_q; expROdd_uid30_fpSqrtTest_b <= expROdd_uid30_fpSqrtTest_in(11 downto 1); --sBias_uid25_fpSqrtTest(CONSTANT,24) sBias_uid25_fpSqrtTest_q <= "01111111111"; --expEvenSig_uid26_fpSqrtTest(ADD,25)@0 expEvenSig_uid26_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b); expEvenSig_uid26_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBias_uid25_fpSqrtTest_q); expEvenSig_uid26_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid26_fpSqrtTest_a) + UNSIGNED(expEvenSig_uid26_fpSqrtTest_b)); expEvenSig_uid26_fpSqrtTest_q <= expEvenSig_uid26_fpSqrtTest_o(11 downto 0); --expREven_uid27_fpSqrtTest(BITSELECT,26)@0 expREven_uid27_fpSqrtTest_in <= expEvenSig_uid26_fpSqrtTest_q; expREven_uid27_fpSqrtTest_b <= expREven_uid27_fpSqrtTest_in(11 downto 1); --expX0_uid31_fpSqrtTest(BITSELECT,30)@0 expX0_uid31_fpSqrtTest_in <= expX_uid6_fpSqrtTest_b(0 downto 0); expX0_uid31_fpSqrtTest_b <= expX0_uid31_fpSqrtTest_in(0 downto 0); --expOddSelect_uid32_fpSqrtTest(LOGICAL,31)@0 expOddSelect_uid32_fpSqrtTest_a <= expX0_uid31_fpSqrtTest_b; expOddSelect_uid32_fpSqrtTest_q <= not expOddSelect_uid32_fpSqrtTest_a; --expRMux_uid33_fpSqrtTest(MUX,32)@0 expRMux_uid33_fpSqrtTest_s <= expOddSelect_uid32_fpSqrtTest_q; expRMux_uid33_fpSqrtTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRMux_uid33_fpSqrtTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE expRMux_uid33_fpSqrtTest_s IS WHEN "0" => expRMux_uid33_fpSqrtTest_q <= expREven_uid27_fpSqrtTest_b; WHEN "1" => expRMux_uid33_fpSqrtTest_q <= expROdd_uid30_fpSqrtTest_b; WHEN OTHERS => expRMux_uid33_fpSqrtTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d(DELAY,248)@1 ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => expRMux_uid33_fpSqrtTest_q, xout => ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, ena => en(0), clk => clk, aclr => areset ); --ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b(DELAY,245)@0 ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signX_uid8_fpSqrtTest_b, xout => ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset ); --cstAllZWF_uid10_fpSqrtTest(CONSTANT,9) cstAllZWF_uid10_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000000"; --fracX_uid7_fpSqrtTest(BITSELECT,6)@0 fracX_uid7_fpSqrtTest_in <= a(51 downto 0); fracX_uid7_fpSqrtTest_b <= fracX_uid7_fpSqrtTest_in(51 downto 0); --fracXIsZero_uid17_fpSqrtTest(LOGICAL,16)@0 fracXIsZero_uid17_fpSqrtTest_a <= fracX_uid7_fpSqrtTest_b; fracXIsZero_uid17_fpSqrtTest_b <= cstAllZWF_uid10_fpSqrtTest_q; fracXIsZero_uid17_fpSqrtTest_q <= "1" when fracXIsZero_uid17_fpSqrtTest_a = fracXIsZero_uid17_fpSqrtTest_b else "0"; --InvFracXIsZero_uid19_fpSqrtTest(LOGICAL,18)@0 InvFracXIsZero_uid19_fpSqrtTest_a <= fracXIsZero_uid17_fpSqrtTest_q; InvFracXIsZero_uid19_fpSqrtTest_q <= not InvFracXIsZero_uid19_fpSqrtTest_a; --expXIsMax_uid15_fpSqrtTest(LOGICAL,14)@0 expXIsMax_uid15_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b; expXIsMax_uid15_fpSqrtTest_b <= cstAllOWE_uid9_fpSqrtTest_q; expXIsMax_uid15_fpSqrtTest_q <= "1" when expXIsMax_uid15_fpSqrtTest_a = expXIsMax_uid15_fpSqrtTest_b else "0"; --exc_N_uid20_fpSqrtTest(LOGICAL,19)@0 exc_N_uid20_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q; exc_N_uid20_fpSqrtTest_b <= InvFracXIsZero_uid19_fpSqrtTest_q; exc_N_uid20_fpSqrtTest_q <= exc_N_uid20_fpSqrtTest_a and exc_N_uid20_fpSqrtTest_b; --InvExc_N_uid21_fpSqrtTest(LOGICAL,20)@0 InvExc_N_uid21_fpSqrtTest_a <= exc_N_uid20_fpSqrtTest_q; InvExc_N_uid21_fpSqrtTest_q <= not InvExc_N_uid21_fpSqrtTest_a; --exc_I_uid18_fpSqrtTest(LOGICAL,17)@0 exc_I_uid18_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q; exc_I_uid18_fpSqrtTest_b <= fracXIsZero_uid17_fpSqrtTest_q; exc_I_uid18_fpSqrtTest_q <= exc_I_uid18_fpSqrtTest_a and exc_I_uid18_fpSqrtTest_b; --InvExc_I_uid22_fpSqrtTest(LOGICAL,21)@0 InvExc_I_uid22_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; InvExc_I_uid22_fpSqrtTest_q <= not InvExc_I_uid22_fpSqrtTest_a; --InvExpXIsZero_uid23_fpSqrtTest(LOGICAL,22)@0 InvExpXIsZero_uid23_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q; InvExpXIsZero_uid23_fpSqrtTest_q <= not InvExpXIsZero_uid23_fpSqrtTest_a; --exc_R_uid24_fpSqrtTest(LOGICAL,23)@0 exc_R_uid24_fpSqrtTest_a <= InvExpXIsZero_uid23_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_b <= InvExc_I_uid22_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_c <= InvExc_N_uid21_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_q <= exc_R_uid24_fpSqrtTest_a and exc_R_uid24_fpSqrtTest_b and exc_R_uid24_fpSqrtTest_c; --minReg_uid42_fpSqrtTest(LOGICAL,41)@0 minReg_uid42_fpSqrtTest_a <= exc_R_uid24_fpSqrtTest_q; minReg_uid42_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; minReg_uid42_fpSqrtTest_q_i <= minReg_uid42_fpSqrtTest_a and minReg_uid42_fpSqrtTest_b; minReg_uid42_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => minReg_uid42_fpSqrtTest_q, xin => minReg_uid42_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --minInf_uid43_fpSqrtTest(LOGICAL,42)@0 minInf_uid43_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; minInf_uid43_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; minInf_uid43_fpSqrtTest_q_i <= minInf_uid43_fpSqrtTest_a and minInf_uid43_fpSqrtTest_b; minInf_uid43_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => minInf_uid43_fpSqrtTest_q, xin => minInf_uid43_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1(REG,155)@0 reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= exc_N_uid20_fpSqrtTest_q; END IF; END IF; END PROCESS; --excRNaN_uid44_fpSqrtTest(LOGICAL,43)@1 excRNaN_uid44_fpSqrtTest_a <= reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q; excRNaN_uid44_fpSqrtTest_b <= minInf_uid43_fpSqrtTest_q; excRNaN_uid44_fpSqrtTest_c <= minReg_uid42_fpSqrtTest_q; excRNaN_uid44_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_a or excRNaN_uid44_fpSqrtTest_b or excRNaN_uid44_fpSqrtTest_c; --InvSignX_uid40_fpSqrtTest(LOGICAL,39)@0 InvSignX_uid40_fpSqrtTest_a <= signX_uid8_fpSqrtTest_b; InvSignX_uid40_fpSqrtTest_q <= not InvSignX_uid40_fpSqrtTest_a; --inInfAndNotNeg_uid41_fpSqrtTest(LOGICAL,40)@0 inInfAndNotNeg_uid41_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; inInfAndNotNeg_uid41_fpSqrtTest_b <= InvSignX_uid40_fpSqrtTest_q; inInfAndNotNeg_uid41_fpSqrtTest_q_i <= inInfAndNotNeg_uid41_fpSqrtTest_a and inInfAndNotNeg_uid41_fpSqrtTest_b; inInfAndNotNeg_uid41_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => inInfAndNotNeg_uid41_fpSqrtTest_q, xin => inInfAndNotNeg_uid41_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0(REG,156)@0 reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= expXIsZero_uid13_fpSqrtTest_q; END IF; END IF; END PROCESS; --join_uid45_fpSqrtTest(BITJOIN,44)@1 join_uid45_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_q & inInfAndNotNeg_uid41_fpSqrtTest_q & reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q; --fracSelIn_uid46_fpSqrtTest(BITJOIN,45)@1 fracSelIn_uid46_fpSqrtTest_q <= ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q & join_uid45_fpSqrtTest_q; --fracSel_uid47_fpSqrtTest(LOOKUP,46)@1 fracSel_uid47_fpSqrtTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracSel_uid47_fpSqrtTest_q <= "01"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN CASE (fracSelIn_uid46_fpSqrtTest_q) IS WHEN "0000" => fracSel_uid47_fpSqrtTest_q <= "01"; WHEN "0001" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0010" => fracSel_uid47_fpSqrtTest_q <= "10"; WHEN "0011" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0100" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "0101" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0110" => fracSel_uid47_fpSqrtTest_q <= "10"; WHEN "0111" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "1000" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1001" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "1010" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1011" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1100" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1101" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1110" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1111" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN OTHERS => fracSel_uid47_fpSqrtTest_q <= (others => '-'); END CASE; END IF; END IF; END PROCESS; --expRPostExc_uid51_fpSqrtTest(MUX,50)@2 expRPostExc_uid51_fpSqrtTest_s <= fracSel_uid47_fpSqrtTest_q; expRPostExc_uid51_fpSqrtTest: PROCESS (expRPostExc_uid51_fpSqrtTest_s, en, cstAllZWE_uid11_fpSqrtTest_q, ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, cstAllOWE_uid9_fpSqrtTest_q, cstAllOWE_uid9_fpSqrtTest_q) BEGIN CASE expRPostExc_uid51_fpSqrtTest_s IS WHEN "00" => expRPostExc_uid51_fpSqrtTest_q <= cstAllZWE_uid11_fpSqrtTest_q; WHEN "01" => expRPostExc_uid51_fpSqrtTest_q <= ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q; WHEN "10" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q; WHEN "11" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q; WHEN OTHERS => expRPostExc_uid51_fpSqrtTest_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg(DELAY,412) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => expRPostExc_uid51_fpSqrtTest_q, xout => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt(COUNTER,401) -- every=1, low=0, high=23, step=1, init=1 ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i = 22 THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '1'; ELSE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i - 23; ELSE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i,5)); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg(REG,402) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux(MUX,403) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux: PROCESS (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q) BEGIN CASE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s IS WHEN "0" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; WHEN "1" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q; WHEN OTHERS => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem(DUALMEM,413) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 5, numwords_a => 24, width_b => 11, widthad_b => 5, numwords_b => 24, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq, address_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa, data_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia ); ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 <= areset; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq(10 downto 0); --fracNaN_uid52_fpSqrtTest(CONSTANT,51) fracNaN_uid52_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000001"; --fracXAddr_uid35_fpSqrtTest(BITSELECT,34)@0 fracXAddr_uid35_fpSqrtTest_in <= fracX_uid7_fpSqrtTest_b; fracXAddr_uid35_fpSqrtTest_b <= fracXAddr_uid35_fpSqrtTest_in(51 downto 45); --addrTable_uid36_fpSqrtTest(BITJOIN,35)@0 addrTable_uid36_fpSqrtTest_q <= expOddSelect_uid32_fpSqrtTest_q & fracXAddr_uid35_fpSqrtTest_b; --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0(REG,161)@0 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= addrTable_uid36_fpSqrtTest_q; END IF; END IF; END PROCESS; --memoryC5_uid71_sqrtTableGenerator_lutmem(DUALMEM,139)@1 memoryC5_uid71_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC5_uid71_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC5_uid71_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q; memoryC5_uid71_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 17, widthad_a => 8, numwords_a => 256, width_b => 17, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC5_uid71_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC5_uid71_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC5_uid71_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC5_uid71_sqrtTableGenerator_lutmem_iq, address_a => memoryC5_uid71_sqrtTableGenerator_lutmem_aa, data_a => memoryC5_uid71_sqrtTableGenerator_lutmem_ia ); memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC5_uid71_sqrtTableGenerator_lutmem_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_iq(16 downto 0); --reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1(REG,163)@3 reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg(DELAY,398) ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg : dspba_delay GENERIC MAP ( width => 52, depth => 1 ) PORT MAP ( xin => fracX_uid7_fpSqrtTest_b, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a(DELAY,229)@0 ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a : dspba_delay GENERIC MAP ( width => 52, depth => 2 ) PORT MAP ( xin => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset ); --FracX44dto0_uid37_fpSqrtTest(BITSELECT,36)@3 FracX44dto0_uid37_fpSqrtTest_in <= ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q(44 downto 0); FracX44dto0_uid37_fpSqrtTest_b <= FracX44dto0_uid37_fpSqrtTest_in(44 downto 0); --yT1_uid73_sqrtPolynomialEvaluator(BITSELECT,72)@3 yT1_uid73_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT1_uid73_sqrtPolynomialEvaluator_b <= yT1_uid73_sqrtPolynomialEvaluator_in(44 downto 28); --reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0(REG,162)@3 reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= yT1_uid73_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator(MULT,103)@4 prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a),18)) * SIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr,34)); END IF; END IF; END PROCESS; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator(BITSELECT,104)@7 prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in(33 downto 16); --highBBits_uid76_sqrtPolynomialEvaluator(BITSELECT,75)@7 highBBits_uid76_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b; highBBits_uid76_sqrtPolynomialEvaluator_b <= highBBits_uid76_sqrtPolynomialEvaluator_in(17 downto 1); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a(DELAY,363)@0 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0(REG,164)@3 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q; END IF; END IF; END PROCESS; --memoryC4_uid69_sqrtTableGenerator_lutmem(DUALMEM,138)@4 memoryC4_uid69_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC4_uid69_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC4_uid69_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q; memoryC4_uid69_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 8, numwords_a => 256, width_b => 24, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC4_uid69_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC4_uid69_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC4_uid69_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC4_uid69_sqrtTableGenerator_lutmem_iq, address_a => memoryC4_uid69_sqrtTableGenerator_lutmem_aa, data_a => memoryC4_uid69_sqrtTableGenerator_lutmem_ia ); memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC4_uid69_sqrtTableGenerator_lutmem_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_iq(23 downto 0); --reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0(REG,165)@6 reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid77_sqrtPolynomialEvaluator(ADD,76)@7 sumAHighB_uid77_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((24 downto 24 => reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q(23)) & reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q); sumAHighB_uid77_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((24 downto 17 => highBBits_uid76_sqrtPolynomialEvaluator_b(16)) & highBBits_uid76_sqrtPolynomialEvaluator_b); sumAHighB_uid77_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_b)); sumAHighB_uid77_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_o(24 downto 0); --lowRangeB_uid75_sqrtPolynomialEvaluator(BITSELECT,74)@7 lowRangeB_uid75_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid75_sqrtPolynomialEvaluator_b <= lowRangeB_uid75_sqrtPolynomialEvaluator_in(0 downto 0); --s1_uid75_uid78_sqrtPolynomialEvaluator(BITJOIN,77)@7 s1_uid75_uid78_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_q & lowRangeB_uid75_sqrtPolynomialEvaluator_b; --reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1(REG,167)@7 reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= s1_uid75_uid78_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor(LOGICAL,459) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a or ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg(REG,457) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= VCC_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena(REG,460) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,461) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b <= en; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b; --yT2_uid79_sqrtPolynomialEvaluator(BITSELECT,78)@3 yT2_uid79_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT2_uid79_sqrtPolynomialEvaluator_b <= yT2_uid79_sqrtPolynomialEvaluator_in(44 downto 21); --reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0(REG,166)@3 reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= yT2_uid79_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg(DELAY,451) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg : dspba_delay GENERIC MAP ( width => 24, depth => 1 ) PORT MAP ( xin => reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q, xout => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,453) -- every=1, low=0, high=1, step=1, init=1 ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i,1)); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg(REG,454) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,455) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q) BEGIN CASE ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s IS WHEN "0" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q; WHEN "1" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,452) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 1, numwords_a => 2, width_b => 24, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq, address_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa, data_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia ); ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq(23 downto 0); --prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator(MULT,106)@8 prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a),25)) * SIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr,50)); END IF; END IF; END PROCESS; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator(BITSELECT,107)@11 prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in(49 downto 23); --highBBits_uid82_sqrtPolynomialEvaluator(BITSELECT,81)@11 highBBits_uid82_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b; highBBits_uid82_sqrtPolynomialEvaluator_b <= highBBits_uid82_sqrtPolynomialEvaluator_in(26 downto 1); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor(LOGICAL,485) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,481) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q <= "0100"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,482) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b else "0"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg(REG,483) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena(REG,486) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,487) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg(DELAY,462) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q, xout => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,477) -- every=1, low=0, high=4, step=1, init=1 ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 3 THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 4; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,3)); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,478) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,479) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q) BEGIN CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q; WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,476) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 5, width_b => 8, widthad_b => 3, numwords_b => 5, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq, address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa, data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia ); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0); --memoryC3_uid67_sqrtTableGenerator_lutmem(DUALMEM,137)@8 memoryC3_uid67_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC3_uid67_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC3_uid67_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q; memoryC3_uid67_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 33, widthad_a => 8, numwords_a => 256, width_b => 33, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC3_uid67_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC3_uid67_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC3_uid67_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC3_uid67_sqrtTableGenerator_lutmem_iq, address_a => memoryC3_uid67_sqrtTableGenerator_lutmem_aa, data_a => memoryC3_uid67_sqrtTableGenerator_lutmem_ia ); memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC3_uid67_sqrtTableGenerator_lutmem_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_iq(32 downto 0); --reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0(REG,169)@10 reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid83_sqrtPolynomialEvaluator(ADD,82)@11 sumAHighB_uid83_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((33 downto 33 => reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q(32)) & reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q); sumAHighB_uid83_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((33 downto 26 => highBBits_uid82_sqrtPolynomialEvaluator_b(25)) & highBBits_uid82_sqrtPolynomialEvaluator_b); sumAHighB_uid83_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_b)); sumAHighB_uid83_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_o(33 downto 0); --lowRangeB_uid81_sqrtPolynomialEvaluator(BITSELECT,80)@11 lowRangeB_uid81_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid81_sqrtPolynomialEvaluator_b <= lowRangeB_uid81_sqrtPolynomialEvaluator_in(0 downto 0); --s2_uid81_uid84_sqrtPolynomialEvaluator(BITJOIN,83)@11 s2_uid81_uid84_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_q & lowRangeB_uid81_sqrtPolynomialEvaluator_b; --reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1(REG,171)@11 reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= s2_uid81_uid84_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor(LOGICAL,524) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q <= not (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a or ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top(CONSTANT,520) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q <= "0101"; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp(LOGICAL,521) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q <= "1" when ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a = ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b else "0"; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg(REG,522) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena(REG,525) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd(LOGICAL,526) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b <= en; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a and ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b; --yT3_uid85_sqrtPolynomialEvaluator(BITSELECT,84)@3 yT3_uid85_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT3_uid85_sqrtPolynomialEvaluator_b <= yT3_uid85_sqrtPolynomialEvaluator_in(44 downto 12); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg(DELAY,514) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg : dspba_delay GENERIC MAP ( width => 33, depth => 1 ) PORT MAP ( xin => yT3_uid85_sqrtPolynomialEvaluator_b, xout => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt(COUNTER,516) -- every=1, low=0, high=5, step=1, init=1 ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i = 4 THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i - 5; ELSE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i,3)); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg(REG,517) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux(MUX,518) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s <= en; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux: PROCESS (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q) BEGIN CASE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s IS WHEN "0" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; WHEN "1" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem(DUALMEM,515) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 33, widthad_a => 3, numwords_a => 6, width_b => 33, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq, address_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa, data_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia ); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 <= areset; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq(32 downto 0); --reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0(REG,170)@11 reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q; END IF; END IF; END PROCESS; --prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator(MULT,109)@12 prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a),34)) * SIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr,68)); END IF; END IF; END PROCESS; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator(BITSELECT,110)@15 prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in(67 downto 34); --highBBits_uid88_sqrtPolynomialEvaluator(BITSELECT,87)@15 highBBits_uid88_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b; highBBits_uid88_sqrtPolynomialEvaluator_b <= highBBits_uid88_sqrtPolynomialEvaluator_in(33 downto 1); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,537) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,533) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01000"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,534) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b else "0"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,535) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,538) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,539) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,501) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,529) -- every=1, low=0, high=8, step=1, init=1 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 7 THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1'; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 8; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4)); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,530) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,531) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q) BEGIN CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,528) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 9, width_b => 8, widthad_b => 4, numwords_b => 9, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0(REG,172)@11 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC2_uid65_sqrtTableGenerator_lutmem(DUALMEM,136)@12 memoryC2_uid65_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC2_uid65_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC2_uid65_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q; memoryC2_uid65_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC2_uid65_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid65_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid65_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid65_sqrtTableGenerator_lutmem_iq, address_a => memoryC2_uid65_sqrtTableGenerator_lutmem_aa, data_a => memoryC2_uid65_sqrtTableGenerator_lutmem_ia ); memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC2_uid65_sqrtTableGenerator_lutmem_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0(REG,173)@14 reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid89_sqrtPolynomialEvaluator(ADD,88)@15 sumAHighB_uid89_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q(39)) & reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q); sumAHighB_uid89_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((40 downto 33 => highBBits_uid88_sqrtPolynomialEvaluator_b(32)) & highBBits_uid88_sqrtPolynomialEvaluator_b); sumAHighB_uid89_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_b)); sumAHighB_uid89_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_o(40 downto 0); --lowRangeB_uid87_sqrtPolynomialEvaluator(BITSELECT,86)@15 lowRangeB_uid87_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid87_sqrtPolynomialEvaluator_b <= lowRangeB_uid87_sqrtPolynomialEvaluator_in(0 downto 0); --s3_uid87_uid90_sqrtPolynomialEvaluator(BITJOIN,89)@15 s3_uid87_uid90_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_q & lowRangeB_uid87_sqrtPolynomialEvaluator_b; --yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,118)@15 yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q; yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 24); --reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9(REG,177)@15 reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor(LOGICAL,448) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top(CONSTANT,444) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q <= "01001"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp(LOGICAL,445) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b else "0"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg(REG,446) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena(REG,449) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,450) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg(DELAY,438) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => FracX44dto0_uid37_fpSqrtTest_b, xout => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,440) -- every=1, low=0, high=9, step=1, init=1 ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 8 THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1'; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 9; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i,4)); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg(REG,441) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,442) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q) BEGIN CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s IS WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q; WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q; WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,439) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 10, width_b => 45, widthad_b => 4, numwords_b => 10, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0, clock1 => clk, address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq, address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa, data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia ); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq(44 downto 0); --yT4_uid91_sqrtPolynomialEvaluator(BITSELECT,90)@15 yT4_uid91_sqrtPolynomialEvaluator_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q; yT4_uid91_sqrtPolynomialEvaluator_b <= yT4_uid91_sqrtPolynomialEvaluator_in(44 downto 5); --xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,117)@15 xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b(12 downto 0); xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in(12 downto 0); --GND(CONSTANT,0) GND_q <= "0"; --pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,120)@15 pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7(REG,176)@15 reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,116)@15 yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q(14 downto 0); yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b <= yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in(14 downto 0); --spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,119)@15 spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q <= GND_q & yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b; --pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,121)@15 pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q <= spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q & STD_LOGIC_VECTOR((1 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6(REG,175)@15 reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,115)@15 xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b; xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 22); --reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4(REG,174)@15 reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma(CHAINMULTADD,140)@16 multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0),19)); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1),19)); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0) <= RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0),38) + RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1),38); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a <= (others => (others => '0')); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c <= (others => (others => '0')); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q),18); IF (en = "1") THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0); END IF; END IF; END PROCESS; multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_delay : dspba_delay GENERIC MAP (width => 37, depth => 1) PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q, clk => clk, aclr => areset); --multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,123)@19 multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q; multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in(36 downto 2); --highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,125)@19 highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b; highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b <= highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in(34 downto 6); --yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,113)@15 yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q; yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 15); --reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1(REG,179)@15 reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,112)@15 xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b; xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 13); --reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0(REG,178)@15 reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator(MULT,114)@16 topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a),28)) * SIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= (others => '0'); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= (others => '0'); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr,54)); END IF; END IF; END PROCESS; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator(ADD,126)@19 sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q(53)) & topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b(28)) & highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b)); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o(54 downto 0); --lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,124)@19 lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b(5 downto 0); lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b <= lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in(5 downto 0); --add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,127)@19 add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q & lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b; --R_uid129_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,128)@19 R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in <= add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q(59 downto 0); R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in(59 downto 17); --reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1(REG,181)@19 reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= "0000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,511) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,507) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01100"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,508) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b else "0"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,509) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,512) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,513) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,503) -- every=1, low=0, high=12, step=1, init=1 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 11 THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1'; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 12; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4)); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,504) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,505) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q) BEGIN CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,502) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 13, width_b => 8, widthad_b => 4, numwords_b => 13, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0(REG,157)@15 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC1_uid63_sqrtTableGenerator_lutmem(DUALMEM,135)@16 memoryC1_uid63_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid63_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid63_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q; memoryC1_uid63_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 9, widthad_a => 8, numwords_a => 256, width_b => 9, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC1_uid63_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid63_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid63_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid63_sqrtTableGenerator_lutmem_iq, address_a => memoryC1_uid63_sqrtTableGenerator_lutmem_aa, data_a => memoryC1_uid63_sqrtTableGenerator_lutmem_ia ); memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC1_uid63_sqrtTableGenerator_lutmem_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_iq(8 downto 0); --reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1(REG,160)@18 reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= "000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --memoryC1_uid62_sqrtTableGenerator_lutmem(DUALMEM,134)@16 memoryC1_uid62_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid62_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid62_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q; memoryC1_uid62_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC1_uid62_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid62_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid62_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid62_sqrtTableGenerator_lutmem_iq, address_a => memoryC1_uid62_sqrtTableGenerator_lutmem_aa, data_a => memoryC1_uid62_sqrtTableGenerator_lutmem_ia ); memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC1_uid62_sqrtTableGenerator_lutmem_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0(REG,159)@18 reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --os_uid64_sqrtTableGenerator(BITJOIN,63)@19 os_uid64_sqrtTableGenerator_q <= reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q & reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q; --rndBit_uid93_sqrtPolynomialEvaluator(CONSTANT,92) rndBit_uid93_sqrtPolynomialEvaluator_q <= "01"; --cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator(BITJOIN,93)@19 cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q <= os_uid64_sqrtTableGenerator_q & rndBit_uid93_sqrtPolynomialEvaluator_q; --reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0(REG,180)@19 reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ts4_uid95_sqrtPolynomialEvaluator(ADD,94)@20 ts4_uid95_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((51 downto 51 => reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q(50)) & reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q); ts4_uid95_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((51 downto 43 => reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q(42)) & reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q); ts4_uid95_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid95_sqrtPolynomialEvaluator_a) + SIGNED(ts4_uid95_sqrtPolynomialEvaluator_b)); ts4_uid95_sqrtPolynomialEvaluator_q <= ts4_uid95_sqrtPolynomialEvaluator_o(51 downto 0); --s4_uid96_sqrtPolynomialEvaluator(BITSELECT,95)@20 s4_uid96_sqrtPolynomialEvaluator_in <= ts4_uid95_sqrtPolynomialEvaluator_q; s4_uid96_sqrtPolynomialEvaluator_b <= s4_uid96_sqrtPolynomialEvaluator_in(51 downto 1); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1(BITSELECT,144)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in <= STD_LOGIC_VECTOR((53 downto 51 => s4_uid96_sqrtPolynomialEvaluator_b(50)) & s4_uid96_sqrtPolynomialEvaluator_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in(53 downto 27); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1(REG,187)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor(LOGICAL,498) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top(CONSTANT,494) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q <= "01110"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp(LOGICAL,495) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b else "0"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg(REG,496) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena(REG,499) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd(LOGICAL,500) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt(COUNTER,490) -- every=1, low=0, high=14, step=1, init=1 ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i = 13 THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '1'; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i - 14; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i,4)); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg(REG,491) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux(MUX,492) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q) BEGIN CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s IS WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q; WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q; WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem(DUALMEM,489) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 15, width_b => 45, widthad_b => 4, numwords_b => 15, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq, address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa, data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia ); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 <= areset; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq(44 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1(BITSELECT,142)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in <= STD_LOGIC_VECTOR("000000000" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in(53 downto 27); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0(REG,184)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1(MULT,148)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr,54)); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1; END IF; END IF; END PROCESS; --ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a(DELAY,349)@24 ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a : dspba_delay GENERIC MAP ( width => 54, depth => 2 ) PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q, ena => en(0), clk => clk, aclr => areset ); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2(BITSHIFT,152)@26 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q & "000000000000000000000000000000000000000000000000000000"; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int(107 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0(BITSELECT,141)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q(26 downto 0); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in(26 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0(REG,182)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1(MULT,147)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr,54)); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0(BITSELECT,143)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in <= s4_uid96_sqrtPolynomialEvaluator_b(26 downto 0); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in(26 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1(REG,183)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0(MULT,146)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0(ADD,149)@24 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR('0' & "00" & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR((56 downto 54 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q(53)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b)); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o(55 downto 0); --ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a(DELAY,348)@24 ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a : dspba_delay GENERIC MAP ( width => 56, depth => 1 ) PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q, ena => en(0), clk => clk, aclr => areset ); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1(BITSHIFT,151)@25 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q & "000000000000000000000000000"; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int(82 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0(MULT,145)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0(BITSHIFT,150)@24 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int(53 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0(REG,188)@24 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0(ADD,153)@25 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q(82)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b)); END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o(83 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0(ADD,154)@26 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a <= STD_LOGIC_VECTOR((108 downto 84 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q(83)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b <= STD_LOGIC_VECTOR((108 downto 108 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q(107)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b)); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o(108 downto 0); --prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator(BITSELECT,130)@26 prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q(95 downto 0); prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in(95 downto 44); --highBBits_uid100_sqrtPolynomialEvaluator(BITSELECT,99)@26 highBBits_uid100_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b; highBBits_uid100_sqrtPolynomialEvaluator_b <= highBBits_uid100_sqrtPolynomialEvaluator_in(51 downto 2); --reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1(REG,196)@26 reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= highBBits_uid100_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor(LOGICAL,472) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,468) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q <= "010011"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,469) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b else "0"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg(REG,470) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena(REG,473) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,474) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,464) -- every=1, low=0, high=19, step=1, init=1 ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 18 THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 19; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,5)); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,465) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,466) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q) BEGIN CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,463) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 5, numwords_a => 20, width_b => 8, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq, address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa, data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia ); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0); --memoryC0_uid60_sqrtTableGenerator_lutmem(DUALMEM,133)@23 memoryC0_uid60_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid60_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid60_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q; memoryC0_uid60_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 17, widthad_a => 8, numwords_a => 256, width_b => 17, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC0_uid60_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid60_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid60_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid60_sqrtTableGenerator_lutmem_iq, address_a => memoryC0_uid60_sqrtTableGenerator_lutmem_aa, data_a => memoryC0_uid60_sqrtTableGenerator_lutmem_ia ); memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC0_uid60_sqrtTableGenerator_lutmem_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_iq(16 downto 0); --reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1(REG,194)@25 reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,550) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,551) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,552) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,541) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 5, numwords_a => 20, width_b => 8, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0(REG,191)@22 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC0_uid59_sqrtTableGenerator_lutmem(DUALMEM,132)@23 memoryC0_uid59_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid59_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid59_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q; memoryC0_uid59_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC0_uid59_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid59_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid59_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid59_sqrtTableGenerator_lutmem_iq, address_a => memoryC0_uid59_sqrtTableGenerator_lutmem_aa, data_a => memoryC0_uid59_sqrtTableGenerator_lutmem_ia ); memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC0_uid59_sqrtTableGenerator_lutmem_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0(REG,193)@25 reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --os_uid61_sqrtTableGenerator(BITJOIN,60)@26 os_uid61_sqrtTableGenerator_q <= reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q & reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q; --reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0(REG,195)@26 reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= os_uid61_sqrtTableGenerator_q; END IF; END IF; END PROCESS; --sumAHighB_uid101_sqrtPolynomialEvaluator(ADD,100)@27 sumAHighB_uid101_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((57 downto 57 => reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q(56)) & reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q); sumAHighB_uid101_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((57 downto 50 => reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q(49)) & reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q); sumAHighB_uid101_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_b)); sumAHighB_uid101_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_o(57 downto 0); --lowRangeB_uid99_sqrtPolynomialEvaluator(BITSELECT,98)@26 lowRangeB_uid99_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b(1 downto 0); lowRangeB_uid99_sqrtPolynomialEvaluator_b <= lowRangeB_uid99_sqrtPolynomialEvaluator_in(1 downto 0); --reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0(REG,197)@26 reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= lowRangeB_uid99_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --s5_uid99_uid102_sqrtPolynomialEvaluator(BITJOIN,101)@27 s5_uid99_uid102_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_q & reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q; --fracR_uid39_fpSqrtTest(BITSELECT,38)@27 fracR_uid39_fpSqrtTest_in <= s5_uid99_uid102_sqrtPolynomialEvaluator_q(56 downto 0); fracR_uid39_fpSqrtTest_b <= fracR_uid39_fpSqrtTest_in(56 downto 5); --reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3(REG,198)@27 reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= "0000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= fracR_uid39_fpSqrtTest_b; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor(LOGICAL,409) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q <= not (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a or ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena(REG,410) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd(LOGICAL,411) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a and ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg(DELAY,399) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => fracSel_uid47_fpSqrtTest_q, xout => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem(DUALMEM,400) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 2, widthad_a => 5, numwords_a => 24, width_b => 2, widthad_b => 5, numwords_b => 24, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq, address_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa, data_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia ); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 <= areset; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq(1 downto 0); --fracRPostExc_uid55_fpSqrtTest(MUX,54)@28 fracRPostExc_uid55_fpSqrtTest_s <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q; fracRPostExc_uid55_fpSqrtTest: PROCESS (fracRPostExc_uid55_fpSqrtTest_s, en, cstAllZWF_uid10_fpSqrtTest_q, reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q, cstAllZWF_uid10_fpSqrtTest_q, fracNaN_uid52_fpSqrtTest_q) BEGIN CASE fracRPostExc_uid55_fpSqrtTest_s IS WHEN "00" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q; WHEN "01" => fracRPostExc_uid55_fpSqrtTest_q <= reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q; WHEN "10" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q; WHEN "11" => fracRPostExc_uid55_fpSqrtTest_q <= fracNaN_uid52_fpSqrtTest_q; WHEN OTHERS => fracRPostExc_uid55_fpSqrtTest_q <= (others => '0'); END CASE; END PROCESS; --RSqrt_uid57_fpSqrtTest(BITJOIN,56)@28 RSqrt_uid57_fpSqrtTest_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q & ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q & fracRPostExc_uid55_fpSqrtTest_q; --xOut(GPOUT,4)@28 q <= RSqrt_uid57_fpSqrtTest_q; end normal;
----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Release Version 13.1 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from fp_sqrt_double_s5 -- VHDL created on Tue Apr 9 15:17:30 2013 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; entity fp_sqrt_double_s5 is port ( a : in std_logic_vector(63 downto 0); en : in std_logic_vector(0 downto 0); q : out std_logic_vector(63 downto 0); clk : in std_logic; areset : in std_logic ); end; architecture normal of fp_sqrt_double_s5 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstAllOWE_uid9_fpSqrtTest_q : std_logic_vector (10 downto 0); signal cstAllZWF_uid10_fpSqrtTest_q : std_logic_vector (51 downto 0); signal cstAllZWE_uid11_fpSqrtTest_q : std_logic_vector (10 downto 0); signal sBias_uid25_fpSqrtTest_q : std_logic_vector (10 downto 0); signal sBiasM1_uid28_fpSqrtTest_q : std_logic_vector (10 downto 0); signal expRMux_uid33_fpSqrtTest_s : std_logic_vector (0 downto 0); signal expRMux_uid33_fpSqrtTest_q : std_logic_vector (10 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_a : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_b : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_q : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_a : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_b : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_q : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_a : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_b : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_q : std_logic_vector(0 downto 0); signal fracSel_uid47_fpSqrtTest_q : std_logic_vector(1 downto 0); signal fracNaN_uid52_fpSqrtTest_q : std_logic_vector (51 downto 0); signal negZero_uid56_fpSqrtTest_a : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_b : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_q : std_logic_vector(0 downto 0); signal rndBit_uid93_sqrtPolynomialEvaluator_q : std_logic_vector (1 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a : std_logic_vector (16 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 : std_logic_vector (33 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr : SIGNED (34 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a : std_logic_vector (23 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 : std_logic_vector (49 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr : SIGNED (50 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q : std_logic_vector (49 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a : std_logic_vector (32 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 : std_logic_vector (67 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr : SIGNED (68 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q : std_logic_vector (67 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector (26 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 : std_logic_vector (53 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr : SIGNED (54 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (53 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid59_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid60_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid62_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid63_sqrtTableGenerator_lutmem_ia : std_logic_vector (8 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_iq : std_logic_vector (8 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_q : std_logic_vector (8 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC2_uid65_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC3_uid67_sqrtTableGenerator_lutmem_ia : std_logic_vector (32 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_iq : std_logic_vector (32 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_q : std_logic_vector (32 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC4_uid69_sqrtTableGenerator_lutmem_ia : std_logic_vector (23 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_iq : std_logic_vector (23 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_q : std_logic_vector (23 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC5_uid71_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0); type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type; attribute preserve : boolean; attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : signal is true; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type is array(0 to 1) of SIGNED(17 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type; attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : signal is true; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type is array(0 to 1) of SIGNED(18 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type is array(0 to 1) of SIGNED(36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type; signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s0 : std_logic_vector(36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q : std_logic_vector (36 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr : UNSIGNED (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr : UNSIGNED (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr : SIGNED (54 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr : SIGNED (54 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a : std_logic_vector(84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b : std_logic_vector(84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o : std_logic_vector (84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q : std_logic_vector (83 downto 0); signal reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q : std_logic_vector (0 downto 0); signal reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q : std_logic_vector (0 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0); signal reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q : std_logic_vector (8 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q : std_logic_vector (16 downto 0); signal reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q : std_logic_vector (16 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0); signal reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0); signal reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q : std_logic_vector (25 downto 0); signal reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0); signal reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0); signal reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q : std_logic_vector (34 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q : std_logic_vector (39 downto 0); signal reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q : std_logic_vector (17 downto 0); signal reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q : std_logic_vector (17 downto 0); signal reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q : std_logic_vector (16 downto 0); signal reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q : std_logic_vector (17 downto 0); signal reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q : std_logic_vector (26 downto 0); signal reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q : std_logic_vector (50 downto 0); signal reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q : std_logic_vector (42 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q : std_logic_vector (53 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0); signal reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q : std_logic_vector (16 downto 0); signal reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q : std_logic_vector (56 downto 0); signal reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q : std_logic_vector (49 downto 0); signal reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q : std_logic_vector (1 downto 0); signal reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q : std_logic_vector (51 downto 0); signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q : std_logic_vector (51 downto 0); signal ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q : std_logic_vector (0 downto 0); signal ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q : std_logic_vector (10 downto 0); signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q : std_logic_vector (55 downto 0); signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q : std_logic_vector (53 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0); signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q : std_logic_vector (51 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 : std_logic; signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq : std_logic; signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : signal is true; signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 : std_logic; signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : signal is true; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 : std_logic; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i : unsigned(4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq : std_logic; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q : std_logic_vector (5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : signal is true; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true; signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic; signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 : std_logic; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq : std_logic; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a : std_logic_vector(56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b : std_logic_vector(56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o : std_logic_vector (56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q : std_logic_vector (55 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal expX_uid6_fpSqrtTest_in : std_logic_vector (62 downto 0); signal expX_uid6_fpSqrtTest_b : std_logic_vector (10 downto 0); signal fracX_uid7_fpSqrtTest_in : std_logic_vector (51 downto 0); signal fracX_uid7_fpSqrtTest_b : std_logic_vector (51 downto 0); signal signX_uid8_fpSqrtTest_in : std_logic_vector (63 downto 0); signal signX_uid8_fpSqrtTest_b : std_logic_vector (0 downto 0); signal expXIsZero_uid13_fpSqrtTest_a : std_logic_vector(10 downto 0); signal expXIsZero_uid13_fpSqrtTest_b : std_logic_vector(10 downto 0); signal expXIsZero_uid13_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid15_fpSqrtTest_a : std_logic_vector(10 downto 0); signal expXIsMax_uid15_fpSqrtTest_b : std_logic_vector(10 downto 0); signal expXIsMax_uid15_fpSqrtTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid17_fpSqrtTest_a : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSqrtTest_b : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSqrtTest_q : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expEvenSig_uid26_fpSqrtTest_a : std_logic_vector(11 downto 0); signal expEvenSig_uid26_fpSqrtTest_b : std_logic_vector(11 downto 0); signal expEvenSig_uid26_fpSqrtTest_o : std_logic_vector (11 downto 0); signal expEvenSig_uid26_fpSqrtTest_q : std_logic_vector (11 downto 0); signal expOddSig_uid29_fpSqrtTest_a : std_logic_vector(11 downto 0); signal expOddSig_uid29_fpSqrtTest_b : std_logic_vector(11 downto 0); signal expOddSig_uid29_fpSqrtTest_o : std_logic_vector (11 downto 0); signal expOddSig_uid29_fpSqrtTest_q : std_logic_vector (11 downto 0); signal excRNaN_uid44_fpSqrtTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expRPostExc_uid51_fpSqrtTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid51_fpSqrtTest_q : std_logic_vector (10 downto 0); signal fracRPostExc_uid55_fpSqrtTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid55_fpSqrtTest_q : std_logic_vector (51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_a : std_logic_vector(51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_b : std_logic_vector(51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_o : std_logic_vector (51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_q : std_logic_vector (51 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_a : std_logic_vector(57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_b : std_logic_vector(57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_o : std_logic_vector (57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_q : std_logic_vector (57 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal join_uid45_fpSqrtTest_q : std_logic_vector (2 downto 0); signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0); signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in : std_logic_vector (49 downto 0); signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in : std_logic_vector (67 downto 0); signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (33 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q : std_logic_vector (53 downto 0); signal os_uid64_sqrtTableGenerator_q : std_logic_vector (48 downto 0); signal os_uid61_sqrtTableGenerator_q : std_logic_vector (56 downto 0); signal s5_uid99_uid102_sqrtPolynomialEvaluator_q : std_logic_vector (59 downto 0); signal FracX44dto0_uid37_fpSqrtTest_in : std_logic_vector (44 downto 0); signal FracX44dto0_uid37_fpSqrtTest_b : std_logic_vector (44 downto 0); signal fracSelIn_uid46_fpSqrtTest_q : std_logic_vector (3 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int : std_logic_vector (82 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q : std_logic_vector (82 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int : std_logic_vector (107 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q : std_logic_vector (107 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0); signal RSqrt_uid57_fpSqrtTest_q : std_logic_vector (63 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a : std_logic_vector(5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b : std_logic_vector(5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q : std_logic_vector(0 downto 0); signal yT4_uid91_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT4_uid91_sqrtPolynomialEvaluator_b : std_logic_vector (39 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b : std_logic_vector (26 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a : std_logic_vector(3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b : std_logic_vector(3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal expX0_uid31_fpSqrtTest_in : std_logic_vector (0 downto 0); signal expX0_uid31_fpSqrtTest_b : std_logic_vector (0 downto 0); signal fracXAddr_uid35_fpSqrtTest_in : std_logic_vector (51 downto 0); signal fracXAddr_uid35_fpSqrtTest_b : std_logic_vector (6 downto 0); signal InvSignX_uid40_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvSignX_uid40_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid22_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid22_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expREven_uid27_fpSqrtTest_in : std_logic_vector (11 downto 0); signal expREven_uid27_fpSqrtTest_b : std_logic_vector (10 downto 0); signal expROdd_uid30_fpSqrtTest_in : std_logic_vector (11 downto 0); signal expROdd_uid30_fpSqrtTest_b : std_logic_vector (10 downto 0); signal s4_uid96_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0); signal s4_uid96_sqrtPolynomialEvaluator_b : std_logic_vector (50 downto 0); signal lowRangeB_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid76_sqrtPolynomialEvaluator_in : std_logic_vector (17 downto 0); signal highBBits_uid76_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal lowRangeB_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid82_sqrtPolynomialEvaluator_in : std_logic_vector (26 downto 0); signal highBBits_uid82_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0); signal lowRangeB_uid87_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid87_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid88_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0); signal highBBits_uid88_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0); signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (5 downto 0); signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (5 downto 0); signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (34 downto 0); signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (28 downto 0); signal cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q : std_logic_vector (50 downto 0); signal fracR_uid39_fpSqrtTest_in : std_logic_vector (56 downto 0); signal fracR_uid39_fpSqrtTest_b : std_logic_vector (51 downto 0); signal yT1_uid73_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT1_uid73_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal yT2_uid79_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT2_uid79_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0); signal yT3_uid85_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT3_uid85_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a : std_logic_vector(108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b : std_logic_vector(108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o : std_logic_vector (108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q : std_logic_vector (108 downto 0); signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0); signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0); signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0); signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0); signal expOddSelect_uid32_fpSqrtTest_a : std_logic_vector(0 downto 0); signal expOddSelect_uid32_fpSqrtTest_q : std_logic_vector(0 downto 0); signal addrTable_uid36_fpSqrtTest_q : std_logic_vector (7 downto 0); signal exc_N_uid20_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_N_uid20_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_N_uid20_fpSqrtTest_q : std_logic_vector(0 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b : std_logic_vector (26 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_a : std_logic_vector(24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_b : std_logic_vector(24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_o : std_logic_vector (24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_q : std_logic_vector (24 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_a : std_logic_vector(33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_b : std_logic_vector(33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_o : std_logic_vector (33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_a : std_logic_vector(40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_b : std_logic_vector(40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_o : std_logic_vector (40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_q : std_logic_vector (40 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector(54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector(54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o : std_logic_vector (54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (54 downto 0); signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in : std_logic_vector (95 downto 0); signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b : std_logic_vector (51 downto 0); signal pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (16 downto 0); signal InvExc_N_uid21_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid21_fpSqrtTest_q : std_logic_vector(0 downto 0); signal s1_uid75_uid78_sqrtPolynomialEvaluator_q : std_logic_vector (25 downto 0); signal s2_uid81_uid84_sqrtPolynomialEvaluator_q : std_logic_vector (34 downto 0); signal s3_uid87_uid90_sqrtPolynomialEvaluator_q : std_logic_vector (41 downto 0); signal add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (60 downto 0); signal lowRangeB_uid99_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0); signal lowRangeB_uid99_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0); signal highBBits_uid100_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0); signal highBBits_uid100_sqrtPolynomialEvaluator_b : std_logic_vector (49 downto 0); signal exc_R_uid24_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_c : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_q : std_logic_vector(0 downto 0); signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0); signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (14 downto 0); signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (14 downto 0); signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0); signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (59 downto 0); signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (42 downto 0); signal spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (15 downto 0); signal pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (17 downto 0); begin --VCC(CONSTANT,1) VCC_q <= "1"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable(LOGICAL,408) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q <= not ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor(LOGICAL,435) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q <= not (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a or ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top(CONSTANT,431) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q <= "011000"; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp(LOGICAL,432) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q <= "1" when ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a = ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b else "0"; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg(REG,433) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q; END IF; END IF; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena(REG,436) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd(LOGICAL,437) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b <= en; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a and ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b; --signX_uid8_fpSqrtTest(BITSELECT,7)@0 signX_uid8_fpSqrtTest_in <= a; signX_uid8_fpSqrtTest_b <= signX_uid8_fpSqrtTest_in(63 downto 63); --cstAllZWE_uid11_fpSqrtTest(CONSTANT,10) cstAllZWE_uid11_fpSqrtTest_q <= "00000000000"; --expX_uid6_fpSqrtTest(BITSELECT,5)@0 expX_uid6_fpSqrtTest_in <= a(62 downto 0); expX_uid6_fpSqrtTest_b <= expX_uid6_fpSqrtTest_in(62 downto 52); --expXIsZero_uid13_fpSqrtTest(LOGICAL,12)@0 expXIsZero_uid13_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b; expXIsZero_uid13_fpSqrtTest_b <= cstAllZWE_uid11_fpSqrtTest_q; expXIsZero_uid13_fpSqrtTest_q <= "1" when expXIsZero_uid13_fpSqrtTest_a = expXIsZero_uid13_fpSqrtTest_b else "0"; --negZero_uid56_fpSqrtTest(LOGICAL,55)@0 negZero_uid56_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q; negZero_uid56_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; negZero_uid56_fpSqrtTest_q_i <= negZero_uid56_fpSqrtTest_a and negZero_uid56_fpSqrtTest_b; negZero_uid56_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => negZero_uid56_fpSqrtTest_q, xin => negZero_uid56_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg(DELAY,425) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => negZero_uid56_fpSqrtTest_q, xout => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt(COUNTER,427) -- every=1, low=0, high=24, step=1, init=1 ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i = 23 THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '1'; ELSE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i - 24; ELSE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i,5)); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg(REG,428) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q; END IF; END IF; END PROCESS; --xIn(GPIN,3)@0 --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux(MUX,429) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s <= en; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux: PROCESS (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q) BEGIN CASE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s IS WHEN "0" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q; WHEN "1" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q; WHEN OTHERS => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem(DUALMEM,426) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 25, width_b => 1, widthad_b => 5, numwords_b => 25, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq, address_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa, data_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia ); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 <= areset; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq(0 downto 0); --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor(LOGICAL,422) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q <= not (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a or ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top(CONSTANT,405) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q <= "010111"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp(LOGICAL,406) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q <= "1" when ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a = ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b else "0"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg(REG,407) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena(REG,423) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q = "1") THEN ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd(LOGICAL,424) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b <= en; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a and ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b; --cstAllOWE_uid9_fpSqrtTest(CONSTANT,8) cstAllOWE_uid9_fpSqrtTest_q <= "11111111111"; --sBiasM1_uid28_fpSqrtTest(CONSTANT,27) sBiasM1_uid28_fpSqrtTest_q <= "01111111110"; --expOddSig_uid29_fpSqrtTest(ADD,28)@0 expOddSig_uid29_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b); expOddSig_uid29_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBiasM1_uid28_fpSqrtTest_q); expOddSig_uid29_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid29_fpSqrtTest_a) + UNSIGNED(expOddSig_uid29_fpSqrtTest_b)); expOddSig_uid29_fpSqrtTest_q <= expOddSig_uid29_fpSqrtTest_o(11 downto 0); --expROdd_uid30_fpSqrtTest(BITSELECT,29)@0 expROdd_uid30_fpSqrtTest_in <= expOddSig_uid29_fpSqrtTest_q; expROdd_uid30_fpSqrtTest_b <= expROdd_uid30_fpSqrtTest_in(11 downto 1); --sBias_uid25_fpSqrtTest(CONSTANT,24) sBias_uid25_fpSqrtTest_q <= "01111111111"; --expEvenSig_uid26_fpSqrtTest(ADD,25)@0 expEvenSig_uid26_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b); expEvenSig_uid26_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBias_uid25_fpSqrtTest_q); expEvenSig_uid26_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid26_fpSqrtTest_a) + UNSIGNED(expEvenSig_uid26_fpSqrtTest_b)); expEvenSig_uid26_fpSqrtTest_q <= expEvenSig_uid26_fpSqrtTest_o(11 downto 0); --expREven_uid27_fpSqrtTest(BITSELECT,26)@0 expREven_uid27_fpSqrtTest_in <= expEvenSig_uid26_fpSqrtTest_q; expREven_uid27_fpSqrtTest_b <= expREven_uid27_fpSqrtTest_in(11 downto 1); --expX0_uid31_fpSqrtTest(BITSELECT,30)@0 expX0_uid31_fpSqrtTest_in <= expX_uid6_fpSqrtTest_b(0 downto 0); expX0_uid31_fpSqrtTest_b <= expX0_uid31_fpSqrtTest_in(0 downto 0); --expOddSelect_uid32_fpSqrtTest(LOGICAL,31)@0 expOddSelect_uid32_fpSqrtTest_a <= expX0_uid31_fpSqrtTest_b; expOddSelect_uid32_fpSqrtTest_q <= not expOddSelect_uid32_fpSqrtTest_a; --expRMux_uid33_fpSqrtTest(MUX,32)@0 expRMux_uid33_fpSqrtTest_s <= expOddSelect_uid32_fpSqrtTest_q; expRMux_uid33_fpSqrtTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRMux_uid33_fpSqrtTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE expRMux_uid33_fpSqrtTest_s IS WHEN "0" => expRMux_uid33_fpSqrtTest_q <= expREven_uid27_fpSqrtTest_b; WHEN "1" => expRMux_uid33_fpSqrtTest_q <= expROdd_uid30_fpSqrtTest_b; WHEN OTHERS => expRMux_uid33_fpSqrtTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d(DELAY,248)@1 ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => expRMux_uid33_fpSqrtTest_q, xout => ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, ena => en(0), clk => clk, aclr => areset ); --ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b(DELAY,245)@0 ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signX_uid8_fpSqrtTest_b, xout => ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset ); --cstAllZWF_uid10_fpSqrtTest(CONSTANT,9) cstAllZWF_uid10_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000000"; --fracX_uid7_fpSqrtTest(BITSELECT,6)@0 fracX_uid7_fpSqrtTest_in <= a(51 downto 0); fracX_uid7_fpSqrtTest_b <= fracX_uid7_fpSqrtTest_in(51 downto 0); --fracXIsZero_uid17_fpSqrtTest(LOGICAL,16)@0 fracXIsZero_uid17_fpSqrtTest_a <= fracX_uid7_fpSqrtTest_b; fracXIsZero_uid17_fpSqrtTest_b <= cstAllZWF_uid10_fpSqrtTest_q; fracXIsZero_uid17_fpSqrtTest_q <= "1" when fracXIsZero_uid17_fpSqrtTest_a = fracXIsZero_uid17_fpSqrtTest_b else "0"; --InvFracXIsZero_uid19_fpSqrtTest(LOGICAL,18)@0 InvFracXIsZero_uid19_fpSqrtTest_a <= fracXIsZero_uid17_fpSqrtTest_q; InvFracXIsZero_uid19_fpSqrtTest_q <= not InvFracXIsZero_uid19_fpSqrtTest_a; --expXIsMax_uid15_fpSqrtTest(LOGICAL,14)@0 expXIsMax_uid15_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b; expXIsMax_uid15_fpSqrtTest_b <= cstAllOWE_uid9_fpSqrtTest_q; expXIsMax_uid15_fpSqrtTest_q <= "1" when expXIsMax_uid15_fpSqrtTest_a = expXIsMax_uid15_fpSqrtTest_b else "0"; --exc_N_uid20_fpSqrtTest(LOGICAL,19)@0 exc_N_uid20_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q; exc_N_uid20_fpSqrtTest_b <= InvFracXIsZero_uid19_fpSqrtTest_q; exc_N_uid20_fpSqrtTest_q <= exc_N_uid20_fpSqrtTest_a and exc_N_uid20_fpSqrtTest_b; --InvExc_N_uid21_fpSqrtTest(LOGICAL,20)@0 InvExc_N_uid21_fpSqrtTest_a <= exc_N_uid20_fpSqrtTest_q; InvExc_N_uid21_fpSqrtTest_q <= not InvExc_N_uid21_fpSqrtTest_a; --exc_I_uid18_fpSqrtTest(LOGICAL,17)@0 exc_I_uid18_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q; exc_I_uid18_fpSqrtTest_b <= fracXIsZero_uid17_fpSqrtTest_q; exc_I_uid18_fpSqrtTest_q <= exc_I_uid18_fpSqrtTest_a and exc_I_uid18_fpSqrtTest_b; --InvExc_I_uid22_fpSqrtTest(LOGICAL,21)@0 InvExc_I_uid22_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; InvExc_I_uid22_fpSqrtTest_q <= not InvExc_I_uid22_fpSqrtTest_a; --InvExpXIsZero_uid23_fpSqrtTest(LOGICAL,22)@0 InvExpXIsZero_uid23_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q; InvExpXIsZero_uid23_fpSqrtTest_q <= not InvExpXIsZero_uid23_fpSqrtTest_a; --exc_R_uid24_fpSqrtTest(LOGICAL,23)@0 exc_R_uid24_fpSqrtTest_a <= InvExpXIsZero_uid23_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_b <= InvExc_I_uid22_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_c <= InvExc_N_uid21_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_q <= exc_R_uid24_fpSqrtTest_a and exc_R_uid24_fpSqrtTest_b and exc_R_uid24_fpSqrtTest_c; --minReg_uid42_fpSqrtTest(LOGICAL,41)@0 minReg_uid42_fpSqrtTest_a <= exc_R_uid24_fpSqrtTest_q; minReg_uid42_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; minReg_uid42_fpSqrtTest_q_i <= minReg_uid42_fpSqrtTest_a and minReg_uid42_fpSqrtTest_b; minReg_uid42_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => minReg_uid42_fpSqrtTest_q, xin => minReg_uid42_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --minInf_uid43_fpSqrtTest(LOGICAL,42)@0 minInf_uid43_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; minInf_uid43_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; minInf_uid43_fpSqrtTest_q_i <= minInf_uid43_fpSqrtTest_a and minInf_uid43_fpSqrtTest_b; minInf_uid43_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => minInf_uid43_fpSqrtTest_q, xin => minInf_uid43_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1(REG,155)@0 reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= exc_N_uid20_fpSqrtTest_q; END IF; END IF; END PROCESS; --excRNaN_uid44_fpSqrtTest(LOGICAL,43)@1 excRNaN_uid44_fpSqrtTest_a <= reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q; excRNaN_uid44_fpSqrtTest_b <= minInf_uid43_fpSqrtTest_q; excRNaN_uid44_fpSqrtTest_c <= minReg_uid42_fpSqrtTest_q; excRNaN_uid44_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_a or excRNaN_uid44_fpSqrtTest_b or excRNaN_uid44_fpSqrtTest_c; --InvSignX_uid40_fpSqrtTest(LOGICAL,39)@0 InvSignX_uid40_fpSqrtTest_a <= signX_uid8_fpSqrtTest_b; InvSignX_uid40_fpSqrtTest_q <= not InvSignX_uid40_fpSqrtTest_a; --inInfAndNotNeg_uid41_fpSqrtTest(LOGICAL,40)@0 inInfAndNotNeg_uid41_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; inInfAndNotNeg_uid41_fpSqrtTest_b <= InvSignX_uid40_fpSqrtTest_q; inInfAndNotNeg_uid41_fpSqrtTest_q_i <= inInfAndNotNeg_uid41_fpSqrtTest_a and inInfAndNotNeg_uid41_fpSqrtTest_b; inInfAndNotNeg_uid41_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => inInfAndNotNeg_uid41_fpSqrtTest_q, xin => inInfAndNotNeg_uid41_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0(REG,156)@0 reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= expXIsZero_uid13_fpSqrtTest_q; END IF; END IF; END PROCESS; --join_uid45_fpSqrtTest(BITJOIN,44)@1 join_uid45_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_q & inInfAndNotNeg_uid41_fpSqrtTest_q & reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q; --fracSelIn_uid46_fpSqrtTest(BITJOIN,45)@1 fracSelIn_uid46_fpSqrtTest_q <= ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q & join_uid45_fpSqrtTest_q; --fracSel_uid47_fpSqrtTest(LOOKUP,46)@1 fracSel_uid47_fpSqrtTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracSel_uid47_fpSqrtTest_q <= "01"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN CASE (fracSelIn_uid46_fpSqrtTest_q) IS WHEN "0000" => fracSel_uid47_fpSqrtTest_q <= "01"; WHEN "0001" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0010" => fracSel_uid47_fpSqrtTest_q <= "10"; WHEN "0011" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0100" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "0101" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0110" => fracSel_uid47_fpSqrtTest_q <= "10"; WHEN "0111" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "1000" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1001" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "1010" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1011" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1100" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1101" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1110" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1111" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN OTHERS => fracSel_uid47_fpSqrtTest_q <= (others => '-'); END CASE; END IF; END IF; END PROCESS; --expRPostExc_uid51_fpSqrtTest(MUX,50)@2 expRPostExc_uid51_fpSqrtTest_s <= fracSel_uid47_fpSqrtTest_q; expRPostExc_uid51_fpSqrtTest: PROCESS (expRPostExc_uid51_fpSqrtTest_s, en, cstAllZWE_uid11_fpSqrtTest_q, ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, cstAllOWE_uid9_fpSqrtTest_q, cstAllOWE_uid9_fpSqrtTest_q) BEGIN CASE expRPostExc_uid51_fpSqrtTest_s IS WHEN "00" => expRPostExc_uid51_fpSqrtTest_q <= cstAllZWE_uid11_fpSqrtTest_q; WHEN "01" => expRPostExc_uid51_fpSqrtTest_q <= ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q; WHEN "10" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q; WHEN "11" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q; WHEN OTHERS => expRPostExc_uid51_fpSqrtTest_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg(DELAY,412) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => expRPostExc_uid51_fpSqrtTest_q, xout => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt(COUNTER,401) -- every=1, low=0, high=23, step=1, init=1 ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i = 22 THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '1'; ELSE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i - 23; ELSE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i,5)); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg(REG,402) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux(MUX,403) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux: PROCESS (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q) BEGIN CASE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s IS WHEN "0" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; WHEN "1" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q; WHEN OTHERS => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem(DUALMEM,413) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 5, numwords_a => 24, width_b => 11, widthad_b => 5, numwords_b => 24, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq, address_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa, data_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia ); ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 <= areset; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq(10 downto 0); --fracNaN_uid52_fpSqrtTest(CONSTANT,51) fracNaN_uid52_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000001"; --fracXAddr_uid35_fpSqrtTest(BITSELECT,34)@0 fracXAddr_uid35_fpSqrtTest_in <= fracX_uid7_fpSqrtTest_b; fracXAddr_uid35_fpSqrtTest_b <= fracXAddr_uid35_fpSqrtTest_in(51 downto 45); --addrTable_uid36_fpSqrtTest(BITJOIN,35)@0 addrTable_uid36_fpSqrtTest_q <= expOddSelect_uid32_fpSqrtTest_q & fracXAddr_uid35_fpSqrtTest_b; --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0(REG,161)@0 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= addrTable_uid36_fpSqrtTest_q; END IF; END IF; END PROCESS; --memoryC5_uid71_sqrtTableGenerator_lutmem(DUALMEM,139)@1 memoryC5_uid71_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC5_uid71_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC5_uid71_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q; memoryC5_uid71_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 17, widthad_a => 8, numwords_a => 256, width_b => 17, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC5_uid71_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC5_uid71_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC5_uid71_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC5_uid71_sqrtTableGenerator_lutmem_iq, address_a => memoryC5_uid71_sqrtTableGenerator_lutmem_aa, data_a => memoryC5_uid71_sqrtTableGenerator_lutmem_ia ); memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC5_uid71_sqrtTableGenerator_lutmem_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_iq(16 downto 0); --reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1(REG,163)@3 reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg(DELAY,398) ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg : dspba_delay GENERIC MAP ( width => 52, depth => 1 ) PORT MAP ( xin => fracX_uid7_fpSqrtTest_b, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a(DELAY,229)@0 ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a : dspba_delay GENERIC MAP ( width => 52, depth => 2 ) PORT MAP ( xin => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset ); --FracX44dto0_uid37_fpSqrtTest(BITSELECT,36)@3 FracX44dto0_uid37_fpSqrtTest_in <= ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q(44 downto 0); FracX44dto0_uid37_fpSqrtTest_b <= FracX44dto0_uid37_fpSqrtTest_in(44 downto 0); --yT1_uid73_sqrtPolynomialEvaluator(BITSELECT,72)@3 yT1_uid73_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT1_uid73_sqrtPolynomialEvaluator_b <= yT1_uid73_sqrtPolynomialEvaluator_in(44 downto 28); --reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0(REG,162)@3 reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= yT1_uid73_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator(MULT,103)@4 prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a),18)) * SIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr,34)); END IF; END IF; END PROCESS; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator(BITSELECT,104)@7 prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in(33 downto 16); --highBBits_uid76_sqrtPolynomialEvaluator(BITSELECT,75)@7 highBBits_uid76_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b; highBBits_uid76_sqrtPolynomialEvaluator_b <= highBBits_uid76_sqrtPolynomialEvaluator_in(17 downto 1); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a(DELAY,363)@0 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0(REG,164)@3 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q; END IF; END IF; END PROCESS; --memoryC4_uid69_sqrtTableGenerator_lutmem(DUALMEM,138)@4 memoryC4_uid69_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC4_uid69_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC4_uid69_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q; memoryC4_uid69_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 8, numwords_a => 256, width_b => 24, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC4_uid69_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC4_uid69_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC4_uid69_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC4_uid69_sqrtTableGenerator_lutmem_iq, address_a => memoryC4_uid69_sqrtTableGenerator_lutmem_aa, data_a => memoryC4_uid69_sqrtTableGenerator_lutmem_ia ); memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC4_uid69_sqrtTableGenerator_lutmem_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_iq(23 downto 0); --reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0(REG,165)@6 reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid77_sqrtPolynomialEvaluator(ADD,76)@7 sumAHighB_uid77_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((24 downto 24 => reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q(23)) & reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q); sumAHighB_uid77_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((24 downto 17 => highBBits_uid76_sqrtPolynomialEvaluator_b(16)) & highBBits_uid76_sqrtPolynomialEvaluator_b); sumAHighB_uid77_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_b)); sumAHighB_uid77_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_o(24 downto 0); --lowRangeB_uid75_sqrtPolynomialEvaluator(BITSELECT,74)@7 lowRangeB_uid75_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid75_sqrtPolynomialEvaluator_b <= lowRangeB_uid75_sqrtPolynomialEvaluator_in(0 downto 0); --s1_uid75_uid78_sqrtPolynomialEvaluator(BITJOIN,77)@7 s1_uid75_uid78_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_q & lowRangeB_uid75_sqrtPolynomialEvaluator_b; --reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1(REG,167)@7 reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= s1_uid75_uid78_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor(LOGICAL,459) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a or ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg(REG,457) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= VCC_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena(REG,460) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,461) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b <= en; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b; --yT2_uid79_sqrtPolynomialEvaluator(BITSELECT,78)@3 yT2_uid79_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT2_uid79_sqrtPolynomialEvaluator_b <= yT2_uid79_sqrtPolynomialEvaluator_in(44 downto 21); --reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0(REG,166)@3 reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= yT2_uid79_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg(DELAY,451) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg : dspba_delay GENERIC MAP ( width => 24, depth => 1 ) PORT MAP ( xin => reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q, xout => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,453) -- every=1, low=0, high=1, step=1, init=1 ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i,1)); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg(REG,454) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,455) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q) BEGIN CASE ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s IS WHEN "0" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q; WHEN "1" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,452) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 1, numwords_a => 2, width_b => 24, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq, address_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa, data_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia ); ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq(23 downto 0); --prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator(MULT,106)@8 prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a),25)) * SIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr,50)); END IF; END IF; END PROCESS; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator(BITSELECT,107)@11 prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in(49 downto 23); --highBBits_uid82_sqrtPolynomialEvaluator(BITSELECT,81)@11 highBBits_uid82_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b; highBBits_uid82_sqrtPolynomialEvaluator_b <= highBBits_uid82_sqrtPolynomialEvaluator_in(26 downto 1); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor(LOGICAL,485) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,481) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q <= "0100"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,482) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b else "0"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg(REG,483) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena(REG,486) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,487) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg(DELAY,462) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q, xout => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,477) -- every=1, low=0, high=4, step=1, init=1 ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 3 THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 4; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,3)); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,478) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,479) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q) BEGIN CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q; WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,476) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 5, width_b => 8, widthad_b => 3, numwords_b => 5, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq, address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa, data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia ); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0); --memoryC3_uid67_sqrtTableGenerator_lutmem(DUALMEM,137)@8 memoryC3_uid67_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC3_uid67_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC3_uid67_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q; memoryC3_uid67_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 33, widthad_a => 8, numwords_a => 256, width_b => 33, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC3_uid67_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC3_uid67_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC3_uid67_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC3_uid67_sqrtTableGenerator_lutmem_iq, address_a => memoryC3_uid67_sqrtTableGenerator_lutmem_aa, data_a => memoryC3_uid67_sqrtTableGenerator_lutmem_ia ); memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC3_uid67_sqrtTableGenerator_lutmem_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_iq(32 downto 0); --reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0(REG,169)@10 reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid83_sqrtPolynomialEvaluator(ADD,82)@11 sumAHighB_uid83_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((33 downto 33 => reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q(32)) & reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q); sumAHighB_uid83_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((33 downto 26 => highBBits_uid82_sqrtPolynomialEvaluator_b(25)) & highBBits_uid82_sqrtPolynomialEvaluator_b); sumAHighB_uid83_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_b)); sumAHighB_uid83_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_o(33 downto 0); --lowRangeB_uid81_sqrtPolynomialEvaluator(BITSELECT,80)@11 lowRangeB_uid81_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid81_sqrtPolynomialEvaluator_b <= lowRangeB_uid81_sqrtPolynomialEvaluator_in(0 downto 0); --s2_uid81_uid84_sqrtPolynomialEvaluator(BITJOIN,83)@11 s2_uid81_uid84_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_q & lowRangeB_uid81_sqrtPolynomialEvaluator_b; --reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1(REG,171)@11 reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= s2_uid81_uid84_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor(LOGICAL,524) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q <= not (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a or ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top(CONSTANT,520) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q <= "0101"; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp(LOGICAL,521) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q <= "1" when ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a = ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b else "0"; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg(REG,522) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena(REG,525) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd(LOGICAL,526) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b <= en; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a and ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b; --yT3_uid85_sqrtPolynomialEvaluator(BITSELECT,84)@3 yT3_uid85_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT3_uid85_sqrtPolynomialEvaluator_b <= yT3_uid85_sqrtPolynomialEvaluator_in(44 downto 12); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg(DELAY,514) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg : dspba_delay GENERIC MAP ( width => 33, depth => 1 ) PORT MAP ( xin => yT3_uid85_sqrtPolynomialEvaluator_b, xout => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt(COUNTER,516) -- every=1, low=0, high=5, step=1, init=1 ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i = 4 THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i - 5; ELSE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i,3)); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg(REG,517) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux(MUX,518) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s <= en; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux: PROCESS (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q) BEGIN CASE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s IS WHEN "0" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; WHEN "1" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem(DUALMEM,515) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 33, widthad_a => 3, numwords_a => 6, width_b => 33, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq, address_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa, data_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia ); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 <= areset; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq(32 downto 0); --reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0(REG,170)@11 reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q; END IF; END IF; END PROCESS; --prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator(MULT,109)@12 prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a),34)) * SIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr,68)); END IF; END IF; END PROCESS; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator(BITSELECT,110)@15 prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in(67 downto 34); --highBBits_uid88_sqrtPolynomialEvaluator(BITSELECT,87)@15 highBBits_uid88_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b; highBBits_uid88_sqrtPolynomialEvaluator_b <= highBBits_uid88_sqrtPolynomialEvaluator_in(33 downto 1); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,537) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,533) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01000"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,534) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b else "0"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,535) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,538) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,539) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,501) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,529) -- every=1, low=0, high=8, step=1, init=1 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 7 THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1'; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 8; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4)); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,530) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,531) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q) BEGIN CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,528) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 9, width_b => 8, widthad_b => 4, numwords_b => 9, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0(REG,172)@11 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC2_uid65_sqrtTableGenerator_lutmem(DUALMEM,136)@12 memoryC2_uid65_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC2_uid65_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC2_uid65_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q; memoryC2_uid65_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC2_uid65_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid65_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid65_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid65_sqrtTableGenerator_lutmem_iq, address_a => memoryC2_uid65_sqrtTableGenerator_lutmem_aa, data_a => memoryC2_uid65_sqrtTableGenerator_lutmem_ia ); memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC2_uid65_sqrtTableGenerator_lutmem_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0(REG,173)@14 reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid89_sqrtPolynomialEvaluator(ADD,88)@15 sumAHighB_uid89_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q(39)) & reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q); sumAHighB_uid89_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((40 downto 33 => highBBits_uid88_sqrtPolynomialEvaluator_b(32)) & highBBits_uid88_sqrtPolynomialEvaluator_b); sumAHighB_uid89_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_b)); sumAHighB_uid89_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_o(40 downto 0); --lowRangeB_uid87_sqrtPolynomialEvaluator(BITSELECT,86)@15 lowRangeB_uid87_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid87_sqrtPolynomialEvaluator_b <= lowRangeB_uid87_sqrtPolynomialEvaluator_in(0 downto 0); --s3_uid87_uid90_sqrtPolynomialEvaluator(BITJOIN,89)@15 s3_uid87_uid90_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_q & lowRangeB_uid87_sqrtPolynomialEvaluator_b; --yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,118)@15 yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q; yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 24); --reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9(REG,177)@15 reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor(LOGICAL,448) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top(CONSTANT,444) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q <= "01001"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp(LOGICAL,445) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b else "0"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg(REG,446) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena(REG,449) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,450) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg(DELAY,438) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => FracX44dto0_uid37_fpSqrtTest_b, xout => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,440) -- every=1, low=0, high=9, step=1, init=1 ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 8 THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1'; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 9; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i,4)); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg(REG,441) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,442) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q) BEGIN CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s IS WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q; WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q; WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,439) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 10, width_b => 45, widthad_b => 4, numwords_b => 10, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0, clock1 => clk, address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq, address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa, data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia ); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq(44 downto 0); --yT4_uid91_sqrtPolynomialEvaluator(BITSELECT,90)@15 yT4_uid91_sqrtPolynomialEvaluator_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q; yT4_uid91_sqrtPolynomialEvaluator_b <= yT4_uid91_sqrtPolynomialEvaluator_in(44 downto 5); --xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,117)@15 xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b(12 downto 0); xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in(12 downto 0); --GND(CONSTANT,0) GND_q <= "0"; --pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,120)@15 pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7(REG,176)@15 reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,116)@15 yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q(14 downto 0); yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b <= yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in(14 downto 0); --spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,119)@15 spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q <= GND_q & yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b; --pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,121)@15 pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q <= spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q & STD_LOGIC_VECTOR((1 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6(REG,175)@15 reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,115)@15 xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b; xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 22); --reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4(REG,174)@15 reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma(CHAINMULTADD,140)@16 multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0),19)); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1),19)); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0) <= RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0),38) + RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1),38); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a <= (others => (others => '0')); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c <= (others => (others => '0')); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q),18); IF (en = "1") THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0); END IF; END IF; END PROCESS; multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_delay : dspba_delay GENERIC MAP (width => 37, depth => 1) PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q, clk => clk, aclr => areset); --multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,123)@19 multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q; multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in(36 downto 2); --highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,125)@19 highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b; highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b <= highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in(34 downto 6); --yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,113)@15 yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q; yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 15); --reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1(REG,179)@15 reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,112)@15 xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b; xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 13); --reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0(REG,178)@15 reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator(MULT,114)@16 topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a),28)) * SIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= (others => '0'); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= (others => '0'); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr,54)); END IF; END IF; END PROCESS; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator(ADD,126)@19 sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q(53)) & topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b(28)) & highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b)); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o(54 downto 0); --lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,124)@19 lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b(5 downto 0); lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b <= lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in(5 downto 0); --add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,127)@19 add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q & lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b; --R_uid129_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,128)@19 R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in <= add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q(59 downto 0); R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in(59 downto 17); --reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1(REG,181)@19 reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= "0000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,511) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,507) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01100"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,508) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b else "0"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,509) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,512) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,513) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,503) -- every=1, low=0, high=12, step=1, init=1 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 11 THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1'; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 12; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4)); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,504) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,505) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q) BEGIN CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,502) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 13, width_b => 8, widthad_b => 4, numwords_b => 13, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0(REG,157)@15 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC1_uid63_sqrtTableGenerator_lutmem(DUALMEM,135)@16 memoryC1_uid63_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid63_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid63_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q; memoryC1_uid63_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 9, widthad_a => 8, numwords_a => 256, width_b => 9, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC1_uid63_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid63_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid63_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid63_sqrtTableGenerator_lutmem_iq, address_a => memoryC1_uid63_sqrtTableGenerator_lutmem_aa, data_a => memoryC1_uid63_sqrtTableGenerator_lutmem_ia ); memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC1_uid63_sqrtTableGenerator_lutmem_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_iq(8 downto 0); --reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1(REG,160)@18 reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= "000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --memoryC1_uid62_sqrtTableGenerator_lutmem(DUALMEM,134)@16 memoryC1_uid62_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid62_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid62_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q; memoryC1_uid62_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC1_uid62_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid62_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid62_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid62_sqrtTableGenerator_lutmem_iq, address_a => memoryC1_uid62_sqrtTableGenerator_lutmem_aa, data_a => memoryC1_uid62_sqrtTableGenerator_lutmem_ia ); memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC1_uid62_sqrtTableGenerator_lutmem_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0(REG,159)@18 reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --os_uid64_sqrtTableGenerator(BITJOIN,63)@19 os_uid64_sqrtTableGenerator_q <= reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q & reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q; --rndBit_uid93_sqrtPolynomialEvaluator(CONSTANT,92) rndBit_uid93_sqrtPolynomialEvaluator_q <= "01"; --cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator(BITJOIN,93)@19 cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q <= os_uid64_sqrtTableGenerator_q & rndBit_uid93_sqrtPolynomialEvaluator_q; --reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0(REG,180)@19 reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ts4_uid95_sqrtPolynomialEvaluator(ADD,94)@20 ts4_uid95_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((51 downto 51 => reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q(50)) & reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q); ts4_uid95_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((51 downto 43 => reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q(42)) & reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q); ts4_uid95_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid95_sqrtPolynomialEvaluator_a) + SIGNED(ts4_uid95_sqrtPolynomialEvaluator_b)); ts4_uid95_sqrtPolynomialEvaluator_q <= ts4_uid95_sqrtPolynomialEvaluator_o(51 downto 0); --s4_uid96_sqrtPolynomialEvaluator(BITSELECT,95)@20 s4_uid96_sqrtPolynomialEvaluator_in <= ts4_uid95_sqrtPolynomialEvaluator_q; s4_uid96_sqrtPolynomialEvaluator_b <= s4_uid96_sqrtPolynomialEvaluator_in(51 downto 1); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1(BITSELECT,144)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in <= STD_LOGIC_VECTOR((53 downto 51 => s4_uid96_sqrtPolynomialEvaluator_b(50)) & s4_uid96_sqrtPolynomialEvaluator_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in(53 downto 27); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1(REG,187)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor(LOGICAL,498) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top(CONSTANT,494) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q <= "01110"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp(LOGICAL,495) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b else "0"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg(REG,496) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena(REG,499) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd(LOGICAL,500) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt(COUNTER,490) -- every=1, low=0, high=14, step=1, init=1 ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i = 13 THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '1'; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i - 14; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i,4)); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg(REG,491) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux(MUX,492) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q) BEGIN CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s IS WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q; WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q; WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem(DUALMEM,489) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 15, width_b => 45, widthad_b => 4, numwords_b => 15, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq, address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa, data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia ); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 <= areset; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq(44 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1(BITSELECT,142)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in <= STD_LOGIC_VECTOR("000000000" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in(53 downto 27); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0(REG,184)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1(MULT,148)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr,54)); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1; END IF; END IF; END PROCESS; --ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a(DELAY,349)@24 ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a : dspba_delay GENERIC MAP ( width => 54, depth => 2 ) PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q, ena => en(0), clk => clk, aclr => areset ); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2(BITSHIFT,152)@26 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q & "000000000000000000000000000000000000000000000000000000"; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int(107 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0(BITSELECT,141)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q(26 downto 0); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in(26 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0(REG,182)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1(MULT,147)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr,54)); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0(BITSELECT,143)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in <= s4_uid96_sqrtPolynomialEvaluator_b(26 downto 0); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in(26 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1(REG,183)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0(MULT,146)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0(ADD,149)@24 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR('0' & "00" & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR((56 downto 54 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q(53)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b)); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o(55 downto 0); --ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a(DELAY,348)@24 ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a : dspba_delay GENERIC MAP ( width => 56, depth => 1 ) PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q, ena => en(0), clk => clk, aclr => areset ); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1(BITSHIFT,151)@25 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q & "000000000000000000000000000"; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int(82 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0(MULT,145)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0(BITSHIFT,150)@24 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int(53 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0(REG,188)@24 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0(ADD,153)@25 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q(82)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b)); END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o(83 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0(ADD,154)@26 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a <= STD_LOGIC_VECTOR((108 downto 84 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q(83)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b <= STD_LOGIC_VECTOR((108 downto 108 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q(107)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b)); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o(108 downto 0); --prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator(BITSELECT,130)@26 prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q(95 downto 0); prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in(95 downto 44); --highBBits_uid100_sqrtPolynomialEvaluator(BITSELECT,99)@26 highBBits_uid100_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b; highBBits_uid100_sqrtPolynomialEvaluator_b <= highBBits_uid100_sqrtPolynomialEvaluator_in(51 downto 2); --reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1(REG,196)@26 reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= highBBits_uid100_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor(LOGICAL,472) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,468) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q <= "010011"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,469) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b else "0"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg(REG,470) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena(REG,473) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,474) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,464) -- every=1, low=0, high=19, step=1, init=1 ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 18 THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 19; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,5)); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,465) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,466) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q) BEGIN CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,463) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 5, numwords_a => 20, width_b => 8, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq, address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa, data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia ); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0); --memoryC0_uid60_sqrtTableGenerator_lutmem(DUALMEM,133)@23 memoryC0_uid60_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid60_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid60_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q; memoryC0_uid60_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 17, widthad_a => 8, numwords_a => 256, width_b => 17, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC0_uid60_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid60_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid60_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid60_sqrtTableGenerator_lutmem_iq, address_a => memoryC0_uid60_sqrtTableGenerator_lutmem_aa, data_a => memoryC0_uid60_sqrtTableGenerator_lutmem_ia ); memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC0_uid60_sqrtTableGenerator_lutmem_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_iq(16 downto 0); --reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1(REG,194)@25 reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,550) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,551) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,552) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,541) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 5, numwords_a => 20, width_b => 8, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0(REG,191)@22 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC0_uid59_sqrtTableGenerator_lutmem(DUALMEM,132)@23 memoryC0_uid59_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid59_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid59_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q; memoryC0_uid59_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC0_uid59_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid59_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid59_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid59_sqrtTableGenerator_lutmem_iq, address_a => memoryC0_uid59_sqrtTableGenerator_lutmem_aa, data_a => memoryC0_uid59_sqrtTableGenerator_lutmem_ia ); memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC0_uid59_sqrtTableGenerator_lutmem_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0(REG,193)@25 reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --os_uid61_sqrtTableGenerator(BITJOIN,60)@26 os_uid61_sqrtTableGenerator_q <= reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q & reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q; --reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0(REG,195)@26 reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= os_uid61_sqrtTableGenerator_q; END IF; END IF; END PROCESS; --sumAHighB_uid101_sqrtPolynomialEvaluator(ADD,100)@27 sumAHighB_uid101_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((57 downto 57 => reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q(56)) & reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q); sumAHighB_uid101_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((57 downto 50 => reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q(49)) & reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q); sumAHighB_uid101_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_b)); sumAHighB_uid101_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_o(57 downto 0); --lowRangeB_uid99_sqrtPolynomialEvaluator(BITSELECT,98)@26 lowRangeB_uid99_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b(1 downto 0); lowRangeB_uid99_sqrtPolynomialEvaluator_b <= lowRangeB_uid99_sqrtPolynomialEvaluator_in(1 downto 0); --reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0(REG,197)@26 reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= lowRangeB_uid99_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --s5_uid99_uid102_sqrtPolynomialEvaluator(BITJOIN,101)@27 s5_uid99_uid102_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_q & reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q; --fracR_uid39_fpSqrtTest(BITSELECT,38)@27 fracR_uid39_fpSqrtTest_in <= s5_uid99_uid102_sqrtPolynomialEvaluator_q(56 downto 0); fracR_uid39_fpSqrtTest_b <= fracR_uid39_fpSqrtTest_in(56 downto 5); --reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3(REG,198)@27 reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= "0000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= fracR_uid39_fpSqrtTest_b; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor(LOGICAL,409) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q <= not (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a or ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena(REG,410) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd(LOGICAL,411) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a and ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg(DELAY,399) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => fracSel_uid47_fpSqrtTest_q, xout => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem(DUALMEM,400) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 2, widthad_a => 5, numwords_a => 24, width_b => 2, widthad_b => 5, numwords_b => 24, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq, address_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa, data_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia ); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 <= areset; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq(1 downto 0); --fracRPostExc_uid55_fpSqrtTest(MUX,54)@28 fracRPostExc_uid55_fpSqrtTest_s <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q; fracRPostExc_uid55_fpSqrtTest: PROCESS (fracRPostExc_uid55_fpSqrtTest_s, en, cstAllZWF_uid10_fpSqrtTest_q, reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q, cstAllZWF_uid10_fpSqrtTest_q, fracNaN_uid52_fpSqrtTest_q) BEGIN CASE fracRPostExc_uid55_fpSqrtTest_s IS WHEN "00" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q; WHEN "01" => fracRPostExc_uid55_fpSqrtTest_q <= reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q; WHEN "10" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q; WHEN "11" => fracRPostExc_uid55_fpSqrtTest_q <= fracNaN_uid52_fpSqrtTest_q; WHEN OTHERS => fracRPostExc_uid55_fpSqrtTest_q <= (others => '0'); END CASE; END PROCESS; --RSqrt_uid57_fpSqrtTest(BITJOIN,56)@28 RSqrt_uid57_fpSqrtTest_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q & ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q & fracRPostExc_uid55_fpSqrtTest_q; --xOut(GPOUT,4)@28 q <= RSqrt_uid57_fpSqrtTest_q; end normal;
----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Release Version 13.1 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from fp_sqrt_double_s5 -- VHDL created on Tue Apr 9 15:17:30 2013 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; entity fp_sqrt_double_s5 is port ( a : in std_logic_vector(63 downto 0); en : in std_logic_vector(0 downto 0); q : out std_logic_vector(63 downto 0); clk : in std_logic; areset : in std_logic ); end; architecture normal of fp_sqrt_double_s5 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstAllOWE_uid9_fpSqrtTest_q : std_logic_vector (10 downto 0); signal cstAllZWF_uid10_fpSqrtTest_q : std_logic_vector (51 downto 0); signal cstAllZWE_uid11_fpSqrtTest_q : std_logic_vector (10 downto 0); signal sBias_uid25_fpSqrtTest_q : std_logic_vector (10 downto 0); signal sBiasM1_uid28_fpSqrtTest_q : std_logic_vector (10 downto 0); signal expRMux_uid33_fpSqrtTest_s : std_logic_vector (0 downto 0); signal expRMux_uid33_fpSqrtTest_q : std_logic_vector (10 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_a : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_b : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_q : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_a : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_b : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_q : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_a : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_b : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_q : std_logic_vector(0 downto 0); signal fracSel_uid47_fpSqrtTest_q : std_logic_vector(1 downto 0); signal fracNaN_uid52_fpSqrtTest_q : std_logic_vector (51 downto 0); signal negZero_uid56_fpSqrtTest_a : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_b : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_q : std_logic_vector(0 downto 0); signal rndBit_uid93_sqrtPolynomialEvaluator_q : std_logic_vector (1 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a : std_logic_vector (16 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 : std_logic_vector (33 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr : SIGNED (34 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a : std_logic_vector (23 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 : std_logic_vector (49 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr : SIGNED (50 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q : std_logic_vector (49 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a : std_logic_vector (32 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 : std_logic_vector (67 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr : SIGNED (68 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q : std_logic_vector (67 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector (26 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 : std_logic_vector (53 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr : SIGNED (54 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (53 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid59_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid60_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid62_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid63_sqrtTableGenerator_lutmem_ia : std_logic_vector (8 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_iq : std_logic_vector (8 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_q : std_logic_vector (8 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC2_uid65_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC3_uid67_sqrtTableGenerator_lutmem_ia : std_logic_vector (32 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_iq : std_logic_vector (32 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_q : std_logic_vector (32 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC4_uid69_sqrtTableGenerator_lutmem_ia : std_logic_vector (23 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_iq : std_logic_vector (23 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_q : std_logic_vector (23 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC5_uid71_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0); type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type; attribute preserve : boolean; attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : signal is true; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type is array(0 to 1) of SIGNED(17 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type; attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : signal is true; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type is array(0 to 1) of SIGNED(18 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type is array(0 to 1) of SIGNED(36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type; signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s0 : std_logic_vector(36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q : std_logic_vector (36 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr : UNSIGNED (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr : UNSIGNED (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr : SIGNED (54 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr : SIGNED (54 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a : std_logic_vector(84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b : std_logic_vector(84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o : std_logic_vector (84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q : std_logic_vector (83 downto 0); signal reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q : std_logic_vector (0 downto 0); signal reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q : std_logic_vector (0 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0); signal reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q : std_logic_vector (8 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q : std_logic_vector (16 downto 0); signal reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q : std_logic_vector (16 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0); signal reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0); signal reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q : std_logic_vector (25 downto 0); signal reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0); signal reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0); signal reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q : std_logic_vector (34 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q : std_logic_vector (39 downto 0); signal reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q : std_logic_vector (17 downto 0); signal reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q : std_logic_vector (17 downto 0); signal reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q : std_logic_vector (16 downto 0); signal reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q : std_logic_vector (17 downto 0); signal reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q : std_logic_vector (26 downto 0); signal reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q : std_logic_vector (50 downto 0); signal reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q : std_logic_vector (42 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q : std_logic_vector (53 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0); signal reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q : std_logic_vector (16 downto 0); signal reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q : std_logic_vector (56 downto 0); signal reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q : std_logic_vector (49 downto 0); signal reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q : std_logic_vector (1 downto 0); signal reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q : std_logic_vector (51 downto 0); signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q : std_logic_vector (51 downto 0); signal ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q : std_logic_vector (0 downto 0); signal ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q : std_logic_vector (10 downto 0); signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q : std_logic_vector (55 downto 0); signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q : std_logic_vector (53 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0); signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q : std_logic_vector (51 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 : std_logic; signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq : std_logic; signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : signal is true; signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 : std_logic; signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : signal is true; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 : std_logic; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i : unsigned(4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq : std_logic; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q : std_logic_vector (5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : signal is true; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true; signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic; signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 : std_logic; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq : std_logic; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a : std_logic_vector(56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b : std_logic_vector(56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o : std_logic_vector (56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q : std_logic_vector (55 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal expX_uid6_fpSqrtTest_in : std_logic_vector (62 downto 0); signal expX_uid6_fpSqrtTest_b : std_logic_vector (10 downto 0); signal fracX_uid7_fpSqrtTest_in : std_logic_vector (51 downto 0); signal fracX_uid7_fpSqrtTest_b : std_logic_vector (51 downto 0); signal signX_uid8_fpSqrtTest_in : std_logic_vector (63 downto 0); signal signX_uid8_fpSqrtTest_b : std_logic_vector (0 downto 0); signal expXIsZero_uid13_fpSqrtTest_a : std_logic_vector(10 downto 0); signal expXIsZero_uid13_fpSqrtTest_b : std_logic_vector(10 downto 0); signal expXIsZero_uid13_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid15_fpSqrtTest_a : std_logic_vector(10 downto 0); signal expXIsMax_uid15_fpSqrtTest_b : std_logic_vector(10 downto 0); signal expXIsMax_uid15_fpSqrtTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid17_fpSqrtTest_a : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSqrtTest_b : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSqrtTest_q : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expEvenSig_uid26_fpSqrtTest_a : std_logic_vector(11 downto 0); signal expEvenSig_uid26_fpSqrtTest_b : std_logic_vector(11 downto 0); signal expEvenSig_uid26_fpSqrtTest_o : std_logic_vector (11 downto 0); signal expEvenSig_uid26_fpSqrtTest_q : std_logic_vector (11 downto 0); signal expOddSig_uid29_fpSqrtTest_a : std_logic_vector(11 downto 0); signal expOddSig_uid29_fpSqrtTest_b : std_logic_vector(11 downto 0); signal expOddSig_uid29_fpSqrtTest_o : std_logic_vector (11 downto 0); signal expOddSig_uid29_fpSqrtTest_q : std_logic_vector (11 downto 0); signal excRNaN_uid44_fpSqrtTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expRPostExc_uid51_fpSqrtTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid51_fpSqrtTest_q : std_logic_vector (10 downto 0); signal fracRPostExc_uid55_fpSqrtTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid55_fpSqrtTest_q : std_logic_vector (51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_a : std_logic_vector(51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_b : std_logic_vector(51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_o : std_logic_vector (51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_q : std_logic_vector (51 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_a : std_logic_vector(57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_b : std_logic_vector(57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_o : std_logic_vector (57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_q : std_logic_vector (57 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal join_uid45_fpSqrtTest_q : std_logic_vector (2 downto 0); signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0); signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in : std_logic_vector (49 downto 0); signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in : std_logic_vector (67 downto 0); signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (33 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q : std_logic_vector (53 downto 0); signal os_uid64_sqrtTableGenerator_q : std_logic_vector (48 downto 0); signal os_uid61_sqrtTableGenerator_q : std_logic_vector (56 downto 0); signal s5_uid99_uid102_sqrtPolynomialEvaluator_q : std_logic_vector (59 downto 0); signal FracX44dto0_uid37_fpSqrtTest_in : std_logic_vector (44 downto 0); signal FracX44dto0_uid37_fpSqrtTest_b : std_logic_vector (44 downto 0); signal fracSelIn_uid46_fpSqrtTest_q : std_logic_vector (3 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int : std_logic_vector (82 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q : std_logic_vector (82 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int : std_logic_vector (107 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q : std_logic_vector (107 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0); signal RSqrt_uid57_fpSqrtTest_q : std_logic_vector (63 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a : std_logic_vector(5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b : std_logic_vector(5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q : std_logic_vector(0 downto 0); signal yT4_uid91_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT4_uid91_sqrtPolynomialEvaluator_b : std_logic_vector (39 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b : std_logic_vector (26 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a : std_logic_vector(3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b : std_logic_vector(3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal expX0_uid31_fpSqrtTest_in : std_logic_vector (0 downto 0); signal expX0_uid31_fpSqrtTest_b : std_logic_vector (0 downto 0); signal fracXAddr_uid35_fpSqrtTest_in : std_logic_vector (51 downto 0); signal fracXAddr_uid35_fpSqrtTest_b : std_logic_vector (6 downto 0); signal InvSignX_uid40_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvSignX_uid40_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid22_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid22_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expREven_uid27_fpSqrtTest_in : std_logic_vector (11 downto 0); signal expREven_uid27_fpSqrtTest_b : std_logic_vector (10 downto 0); signal expROdd_uid30_fpSqrtTest_in : std_logic_vector (11 downto 0); signal expROdd_uid30_fpSqrtTest_b : std_logic_vector (10 downto 0); signal s4_uid96_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0); signal s4_uid96_sqrtPolynomialEvaluator_b : std_logic_vector (50 downto 0); signal lowRangeB_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid76_sqrtPolynomialEvaluator_in : std_logic_vector (17 downto 0); signal highBBits_uid76_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal lowRangeB_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid82_sqrtPolynomialEvaluator_in : std_logic_vector (26 downto 0); signal highBBits_uid82_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0); signal lowRangeB_uid87_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid87_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid88_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0); signal highBBits_uid88_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0); signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (5 downto 0); signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (5 downto 0); signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (34 downto 0); signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (28 downto 0); signal cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q : std_logic_vector (50 downto 0); signal fracR_uid39_fpSqrtTest_in : std_logic_vector (56 downto 0); signal fracR_uid39_fpSqrtTest_b : std_logic_vector (51 downto 0); signal yT1_uid73_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT1_uid73_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal yT2_uid79_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT2_uid79_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0); signal yT3_uid85_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT3_uid85_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a : std_logic_vector(108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b : std_logic_vector(108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o : std_logic_vector (108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q : std_logic_vector (108 downto 0); signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0); signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0); signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0); signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0); signal expOddSelect_uid32_fpSqrtTest_a : std_logic_vector(0 downto 0); signal expOddSelect_uid32_fpSqrtTest_q : std_logic_vector(0 downto 0); signal addrTable_uid36_fpSqrtTest_q : std_logic_vector (7 downto 0); signal exc_N_uid20_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_N_uid20_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_N_uid20_fpSqrtTest_q : std_logic_vector(0 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b : std_logic_vector (26 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_a : std_logic_vector(24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_b : std_logic_vector(24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_o : std_logic_vector (24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_q : std_logic_vector (24 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_a : std_logic_vector(33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_b : std_logic_vector(33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_o : std_logic_vector (33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_a : std_logic_vector(40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_b : std_logic_vector(40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_o : std_logic_vector (40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_q : std_logic_vector (40 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector(54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector(54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o : std_logic_vector (54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (54 downto 0); signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in : std_logic_vector (95 downto 0); signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b : std_logic_vector (51 downto 0); signal pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (16 downto 0); signal InvExc_N_uid21_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid21_fpSqrtTest_q : std_logic_vector(0 downto 0); signal s1_uid75_uid78_sqrtPolynomialEvaluator_q : std_logic_vector (25 downto 0); signal s2_uid81_uid84_sqrtPolynomialEvaluator_q : std_logic_vector (34 downto 0); signal s3_uid87_uid90_sqrtPolynomialEvaluator_q : std_logic_vector (41 downto 0); signal add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (60 downto 0); signal lowRangeB_uid99_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0); signal lowRangeB_uid99_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0); signal highBBits_uid100_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0); signal highBBits_uid100_sqrtPolynomialEvaluator_b : std_logic_vector (49 downto 0); signal exc_R_uid24_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_c : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_q : std_logic_vector(0 downto 0); signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0); signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (14 downto 0); signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (14 downto 0); signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0); signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (59 downto 0); signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (42 downto 0); signal spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (15 downto 0); signal pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (17 downto 0); begin --VCC(CONSTANT,1) VCC_q <= "1"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable(LOGICAL,408) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q <= not ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor(LOGICAL,435) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q <= not (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a or ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top(CONSTANT,431) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q <= "011000"; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp(LOGICAL,432) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q <= "1" when ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a = ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b else "0"; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg(REG,433) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q; END IF; END IF; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena(REG,436) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd(LOGICAL,437) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b <= en; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a and ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b; --signX_uid8_fpSqrtTest(BITSELECT,7)@0 signX_uid8_fpSqrtTest_in <= a; signX_uid8_fpSqrtTest_b <= signX_uid8_fpSqrtTest_in(63 downto 63); --cstAllZWE_uid11_fpSqrtTest(CONSTANT,10) cstAllZWE_uid11_fpSqrtTest_q <= "00000000000"; --expX_uid6_fpSqrtTest(BITSELECT,5)@0 expX_uid6_fpSqrtTest_in <= a(62 downto 0); expX_uid6_fpSqrtTest_b <= expX_uid6_fpSqrtTest_in(62 downto 52); --expXIsZero_uid13_fpSqrtTest(LOGICAL,12)@0 expXIsZero_uid13_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b; expXIsZero_uid13_fpSqrtTest_b <= cstAllZWE_uid11_fpSqrtTest_q; expXIsZero_uid13_fpSqrtTest_q <= "1" when expXIsZero_uid13_fpSqrtTest_a = expXIsZero_uid13_fpSqrtTest_b else "0"; --negZero_uid56_fpSqrtTest(LOGICAL,55)@0 negZero_uid56_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q; negZero_uid56_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; negZero_uid56_fpSqrtTest_q_i <= negZero_uid56_fpSqrtTest_a and negZero_uid56_fpSqrtTest_b; negZero_uid56_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => negZero_uid56_fpSqrtTest_q, xin => negZero_uid56_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg(DELAY,425) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => negZero_uid56_fpSqrtTest_q, xout => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt(COUNTER,427) -- every=1, low=0, high=24, step=1, init=1 ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i = 23 THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '1'; ELSE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i - 24; ELSE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i,5)); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg(REG,428) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q; END IF; END IF; END PROCESS; --xIn(GPIN,3)@0 --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux(MUX,429) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s <= en; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux: PROCESS (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q) BEGIN CASE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s IS WHEN "0" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q; WHEN "1" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q; WHEN OTHERS => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem(DUALMEM,426) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 25, width_b => 1, widthad_b => 5, numwords_b => 25, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq, address_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa, data_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia ); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 <= areset; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq(0 downto 0); --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor(LOGICAL,422) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q <= not (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a or ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top(CONSTANT,405) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q <= "010111"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp(LOGICAL,406) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q <= "1" when ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a = ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b else "0"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg(REG,407) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena(REG,423) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q = "1") THEN ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd(LOGICAL,424) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b <= en; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a and ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b; --cstAllOWE_uid9_fpSqrtTest(CONSTANT,8) cstAllOWE_uid9_fpSqrtTest_q <= "11111111111"; --sBiasM1_uid28_fpSqrtTest(CONSTANT,27) sBiasM1_uid28_fpSqrtTest_q <= "01111111110"; --expOddSig_uid29_fpSqrtTest(ADD,28)@0 expOddSig_uid29_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b); expOddSig_uid29_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBiasM1_uid28_fpSqrtTest_q); expOddSig_uid29_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid29_fpSqrtTest_a) + UNSIGNED(expOddSig_uid29_fpSqrtTest_b)); expOddSig_uid29_fpSqrtTest_q <= expOddSig_uid29_fpSqrtTest_o(11 downto 0); --expROdd_uid30_fpSqrtTest(BITSELECT,29)@0 expROdd_uid30_fpSqrtTest_in <= expOddSig_uid29_fpSqrtTest_q; expROdd_uid30_fpSqrtTest_b <= expROdd_uid30_fpSqrtTest_in(11 downto 1); --sBias_uid25_fpSqrtTest(CONSTANT,24) sBias_uid25_fpSqrtTest_q <= "01111111111"; --expEvenSig_uid26_fpSqrtTest(ADD,25)@0 expEvenSig_uid26_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b); expEvenSig_uid26_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBias_uid25_fpSqrtTest_q); expEvenSig_uid26_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid26_fpSqrtTest_a) + UNSIGNED(expEvenSig_uid26_fpSqrtTest_b)); expEvenSig_uid26_fpSqrtTest_q <= expEvenSig_uid26_fpSqrtTest_o(11 downto 0); --expREven_uid27_fpSqrtTest(BITSELECT,26)@0 expREven_uid27_fpSqrtTest_in <= expEvenSig_uid26_fpSqrtTest_q; expREven_uid27_fpSqrtTest_b <= expREven_uid27_fpSqrtTest_in(11 downto 1); --expX0_uid31_fpSqrtTest(BITSELECT,30)@0 expX0_uid31_fpSqrtTest_in <= expX_uid6_fpSqrtTest_b(0 downto 0); expX0_uid31_fpSqrtTest_b <= expX0_uid31_fpSqrtTest_in(0 downto 0); --expOddSelect_uid32_fpSqrtTest(LOGICAL,31)@0 expOddSelect_uid32_fpSqrtTest_a <= expX0_uid31_fpSqrtTest_b; expOddSelect_uid32_fpSqrtTest_q <= not expOddSelect_uid32_fpSqrtTest_a; --expRMux_uid33_fpSqrtTest(MUX,32)@0 expRMux_uid33_fpSqrtTest_s <= expOddSelect_uid32_fpSqrtTest_q; expRMux_uid33_fpSqrtTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRMux_uid33_fpSqrtTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE expRMux_uid33_fpSqrtTest_s IS WHEN "0" => expRMux_uid33_fpSqrtTest_q <= expREven_uid27_fpSqrtTest_b; WHEN "1" => expRMux_uid33_fpSqrtTest_q <= expROdd_uid30_fpSqrtTest_b; WHEN OTHERS => expRMux_uid33_fpSqrtTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d(DELAY,248)@1 ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => expRMux_uid33_fpSqrtTest_q, xout => ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, ena => en(0), clk => clk, aclr => areset ); --ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b(DELAY,245)@0 ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signX_uid8_fpSqrtTest_b, xout => ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset ); --cstAllZWF_uid10_fpSqrtTest(CONSTANT,9) cstAllZWF_uid10_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000000"; --fracX_uid7_fpSqrtTest(BITSELECT,6)@0 fracX_uid7_fpSqrtTest_in <= a(51 downto 0); fracX_uid7_fpSqrtTest_b <= fracX_uid7_fpSqrtTest_in(51 downto 0); --fracXIsZero_uid17_fpSqrtTest(LOGICAL,16)@0 fracXIsZero_uid17_fpSqrtTest_a <= fracX_uid7_fpSqrtTest_b; fracXIsZero_uid17_fpSqrtTest_b <= cstAllZWF_uid10_fpSqrtTest_q; fracXIsZero_uid17_fpSqrtTest_q <= "1" when fracXIsZero_uid17_fpSqrtTest_a = fracXIsZero_uid17_fpSqrtTest_b else "0"; --InvFracXIsZero_uid19_fpSqrtTest(LOGICAL,18)@0 InvFracXIsZero_uid19_fpSqrtTest_a <= fracXIsZero_uid17_fpSqrtTest_q; InvFracXIsZero_uid19_fpSqrtTest_q <= not InvFracXIsZero_uid19_fpSqrtTest_a; --expXIsMax_uid15_fpSqrtTest(LOGICAL,14)@0 expXIsMax_uid15_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b; expXIsMax_uid15_fpSqrtTest_b <= cstAllOWE_uid9_fpSqrtTest_q; expXIsMax_uid15_fpSqrtTest_q <= "1" when expXIsMax_uid15_fpSqrtTest_a = expXIsMax_uid15_fpSqrtTest_b else "0"; --exc_N_uid20_fpSqrtTest(LOGICAL,19)@0 exc_N_uid20_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q; exc_N_uid20_fpSqrtTest_b <= InvFracXIsZero_uid19_fpSqrtTest_q; exc_N_uid20_fpSqrtTest_q <= exc_N_uid20_fpSqrtTest_a and exc_N_uid20_fpSqrtTest_b; --InvExc_N_uid21_fpSqrtTest(LOGICAL,20)@0 InvExc_N_uid21_fpSqrtTest_a <= exc_N_uid20_fpSqrtTest_q; InvExc_N_uid21_fpSqrtTest_q <= not InvExc_N_uid21_fpSqrtTest_a; --exc_I_uid18_fpSqrtTest(LOGICAL,17)@0 exc_I_uid18_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q; exc_I_uid18_fpSqrtTest_b <= fracXIsZero_uid17_fpSqrtTest_q; exc_I_uid18_fpSqrtTest_q <= exc_I_uid18_fpSqrtTest_a and exc_I_uid18_fpSqrtTest_b; --InvExc_I_uid22_fpSqrtTest(LOGICAL,21)@0 InvExc_I_uid22_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; InvExc_I_uid22_fpSqrtTest_q <= not InvExc_I_uid22_fpSqrtTest_a; --InvExpXIsZero_uid23_fpSqrtTest(LOGICAL,22)@0 InvExpXIsZero_uid23_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q; InvExpXIsZero_uid23_fpSqrtTest_q <= not InvExpXIsZero_uid23_fpSqrtTest_a; --exc_R_uid24_fpSqrtTest(LOGICAL,23)@0 exc_R_uid24_fpSqrtTest_a <= InvExpXIsZero_uid23_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_b <= InvExc_I_uid22_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_c <= InvExc_N_uid21_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_q <= exc_R_uid24_fpSqrtTest_a and exc_R_uid24_fpSqrtTest_b and exc_R_uid24_fpSqrtTest_c; --minReg_uid42_fpSqrtTest(LOGICAL,41)@0 minReg_uid42_fpSqrtTest_a <= exc_R_uid24_fpSqrtTest_q; minReg_uid42_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; minReg_uid42_fpSqrtTest_q_i <= minReg_uid42_fpSqrtTest_a and minReg_uid42_fpSqrtTest_b; minReg_uid42_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => minReg_uid42_fpSqrtTest_q, xin => minReg_uid42_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --minInf_uid43_fpSqrtTest(LOGICAL,42)@0 minInf_uid43_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; minInf_uid43_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; minInf_uid43_fpSqrtTest_q_i <= minInf_uid43_fpSqrtTest_a and minInf_uid43_fpSqrtTest_b; minInf_uid43_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => minInf_uid43_fpSqrtTest_q, xin => minInf_uid43_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1(REG,155)@0 reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= exc_N_uid20_fpSqrtTest_q; END IF; END IF; END PROCESS; --excRNaN_uid44_fpSqrtTest(LOGICAL,43)@1 excRNaN_uid44_fpSqrtTest_a <= reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q; excRNaN_uid44_fpSqrtTest_b <= minInf_uid43_fpSqrtTest_q; excRNaN_uid44_fpSqrtTest_c <= minReg_uid42_fpSqrtTest_q; excRNaN_uid44_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_a or excRNaN_uid44_fpSqrtTest_b or excRNaN_uid44_fpSqrtTest_c; --InvSignX_uid40_fpSqrtTest(LOGICAL,39)@0 InvSignX_uid40_fpSqrtTest_a <= signX_uid8_fpSqrtTest_b; InvSignX_uid40_fpSqrtTest_q <= not InvSignX_uid40_fpSqrtTest_a; --inInfAndNotNeg_uid41_fpSqrtTest(LOGICAL,40)@0 inInfAndNotNeg_uid41_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; inInfAndNotNeg_uid41_fpSqrtTest_b <= InvSignX_uid40_fpSqrtTest_q; inInfAndNotNeg_uid41_fpSqrtTest_q_i <= inInfAndNotNeg_uid41_fpSqrtTest_a and inInfAndNotNeg_uid41_fpSqrtTest_b; inInfAndNotNeg_uid41_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => inInfAndNotNeg_uid41_fpSqrtTest_q, xin => inInfAndNotNeg_uid41_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0(REG,156)@0 reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= expXIsZero_uid13_fpSqrtTest_q; END IF; END IF; END PROCESS; --join_uid45_fpSqrtTest(BITJOIN,44)@1 join_uid45_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_q & inInfAndNotNeg_uid41_fpSqrtTest_q & reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q; --fracSelIn_uid46_fpSqrtTest(BITJOIN,45)@1 fracSelIn_uid46_fpSqrtTest_q <= ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q & join_uid45_fpSqrtTest_q; --fracSel_uid47_fpSqrtTest(LOOKUP,46)@1 fracSel_uid47_fpSqrtTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracSel_uid47_fpSqrtTest_q <= "01"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN CASE (fracSelIn_uid46_fpSqrtTest_q) IS WHEN "0000" => fracSel_uid47_fpSqrtTest_q <= "01"; WHEN "0001" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0010" => fracSel_uid47_fpSqrtTest_q <= "10"; WHEN "0011" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0100" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "0101" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0110" => fracSel_uid47_fpSqrtTest_q <= "10"; WHEN "0111" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "1000" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1001" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "1010" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1011" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1100" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1101" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1110" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1111" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN OTHERS => fracSel_uid47_fpSqrtTest_q <= (others => '-'); END CASE; END IF; END IF; END PROCESS; --expRPostExc_uid51_fpSqrtTest(MUX,50)@2 expRPostExc_uid51_fpSqrtTest_s <= fracSel_uid47_fpSqrtTest_q; expRPostExc_uid51_fpSqrtTest: PROCESS (expRPostExc_uid51_fpSqrtTest_s, en, cstAllZWE_uid11_fpSqrtTest_q, ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, cstAllOWE_uid9_fpSqrtTest_q, cstAllOWE_uid9_fpSqrtTest_q) BEGIN CASE expRPostExc_uid51_fpSqrtTest_s IS WHEN "00" => expRPostExc_uid51_fpSqrtTest_q <= cstAllZWE_uid11_fpSqrtTest_q; WHEN "01" => expRPostExc_uid51_fpSqrtTest_q <= ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q; WHEN "10" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q; WHEN "11" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q; WHEN OTHERS => expRPostExc_uid51_fpSqrtTest_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg(DELAY,412) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => expRPostExc_uid51_fpSqrtTest_q, xout => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt(COUNTER,401) -- every=1, low=0, high=23, step=1, init=1 ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i = 22 THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '1'; ELSE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i - 23; ELSE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i,5)); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg(REG,402) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux(MUX,403) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux: PROCESS (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q) BEGIN CASE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s IS WHEN "0" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; WHEN "1" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q; WHEN OTHERS => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem(DUALMEM,413) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 5, numwords_a => 24, width_b => 11, widthad_b => 5, numwords_b => 24, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq, address_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa, data_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia ); ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 <= areset; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq(10 downto 0); --fracNaN_uid52_fpSqrtTest(CONSTANT,51) fracNaN_uid52_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000001"; --fracXAddr_uid35_fpSqrtTest(BITSELECT,34)@0 fracXAddr_uid35_fpSqrtTest_in <= fracX_uid7_fpSqrtTest_b; fracXAddr_uid35_fpSqrtTest_b <= fracXAddr_uid35_fpSqrtTest_in(51 downto 45); --addrTable_uid36_fpSqrtTest(BITJOIN,35)@0 addrTable_uid36_fpSqrtTest_q <= expOddSelect_uid32_fpSqrtTest_q & fracXAddr_uid35_fpSqrtTest_b; --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0(REG,161)@0 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= addrTable_uid36_fpSqrtTest_q; END IF; END IF; END PROCESS; --memoryC5_uid71_sqrtTableGenerator_lutmem(DUALMEM,139)@1 memoryC5_uid71_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC5_uid71_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC5_uid71_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q; memoryC5_uid71_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 17, widthad_a => 8, numwords_a => 256, width_b => 17, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC5_uid71_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC5_uid71_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC5_uid71_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC5_uid71_sqrtTableGenerator_lutmem_iq, address_a => memoryC5_uid71_sqrtTableGenerator_lutmem_aa, data_a => memoryC5_uid71_sqrtTableGenerator_lutmem_ia ); memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC5_uid71_sqrtTableGenerator_lutmem_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_iq(16 downto 0); --reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1(REG,163)@3 reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg(DELAY,398) ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg : dspba_delay GENERIC MAP ( width => 52, depth => 1 ) PORT MAP ( xin => fracX_uid7_fpSqrtTest_b, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a(DELAY,229)@0 ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a : dspba_delay GENERIC MAP ( width => 52, depth => 2 ) PORT MAP ( xin => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset ); --FracX44dto0_uid37_fpSqrtTest(BITSELECT,36)@3 FracX44dto0_uid37_fpSqrtTest_in <= ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q(44 downto 0); FracX44dto0_uid37_fpSqrtTest_b <= FracX44dto0_uid37_fpSqrtTest_in(44 downto 0); --yT1_uid73_sqrtPolynomialEvaluator(BITSELECT,72)@3 yT1_uid73_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT1_uid73_sqrtPolynomialEvaluator_b <= yT1_uid73_sqrtPolynomialEvaluator_in(44 downto 28); --reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0(REG,162)@3 reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= yT1_uid73_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator(MULT,103)@4 prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a),18)) * SIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr,34)); END IF; END IF; END PROCESS; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator(BITSELECT,104)@7 prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in(33 downto 16); --highBBits_uid76_sqrtPolynomialEvaluator(BITSELECT,75)@7 highBBits_uid76_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b; highBBits_uid76_sqrtPolynomialEvaluator_b <= highBBits_uid76_sqrtPolynomialEvaluator_in(17 downto 1); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a(DELAY,363)@0 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0(REG,164)@3 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q; END IF; END IF; END PROCESS; --memoryC4_uid69_sqrtTableGenerator_lutmem(DUALMEM,138)@4 memoryC4_uid69_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC4_uid69_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC4_uid69_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q; memoryC4_uid69_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 8, numwords_a => 256, width_b => 24, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC4_uid69_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC4_uid69_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC4_uid69_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC4_uid69_sqrtTableGenerator_lutmem_iq, address_a => memoryC4_uid69_sqrtTableGenerator_lutmem_aa, data_a => memoryC4_uid69_sqrtTableGenerator_lutmem_ia ); memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC4_uid69_sqrtTableGenerator_lutmem_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_iq(23 downto 0); --reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0(REG,165)@6 reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid77_sqrtPolynomialEvaluator(ADD,76)@7 sumAHighB_uid77_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((24 downto 24 => reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q(23)) & reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q); sumAHighB_uid77_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((24 downto 17 => highBBits_uid76_sqrtPolynomialEvaluator_b(16)) & highBBits_uid76_sqrtPolynomialEvaluator_b); sumAHighB_uid77_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_b)); sumAHighB_uid77_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_o(24 downto 0); --lowRangeB_uid75_sqrtPolynomialEvaluator(BITSELECT,74)@7 lowRangeB_uid75_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid75_sqrtPolynomialEvaluator_b <= lowRangeB_uid75_sqrtPolynomialEvaluator_in(0 downto 0); --s1_uid75_uid78_sqrtPolynomialEvaluator(BITJOIN,77)@7 s1_uid75_uid78_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_q & lowRangeB_uid75_sqrtPolynomialEvaluator_b; --reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1(REG,167)@7 reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= s1_uid75_uid78_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor(LOGICAL,459) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a or ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg(REG,457) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= VCC_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena(REG,460) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,461) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b <= en; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b; --yT2_uid79_sqrtPolynomialEvaluator(BITSELECT,78)@3 yT2_uid79_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT2_uid79_sqrtPolynomialEvaluator_b <= yT2_uid79_sqrtPolynomialEvaluator_in(44 downto 21); --reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0(REG,166)@3 reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= yT2_uid79_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg(DELAY,451) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg : dspba_delay GENERIC MAP ( width => 24, depth => 1 ) PORT MAP ( xin => reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q, xout => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,453) -- every=1, low=0, high=1, step=1, init=1 ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i,1)); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg(REG,454) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,455) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q) BEGIN CASE ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s IS WHEN "0" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q; WHEN "1" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,452) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 1, numwords_a => 2, width_b => 24, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq, address_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa, data_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia ); ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq(23 downto 0); --prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator(MULT,106)@8 prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a),25)) * SIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr,50)); END IF; END IF; END PROCESS; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator(BITSELECT,107)@11 prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in(49 downto 23); --highBBits_uid82_sqrtPolynomialEvaluator(BITSELECT,81)@11 highBBits_uid82_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b; highBBits_uid82_sqrtPolynomialEvaluator_b <= highBBits_uid82_sqrtPolynomialEvaluator_in(26 downto 1); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor(LOGICAL,485) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,481) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q <= "0100"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,482) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b else "0"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg(REG,483) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena(REG,486) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,487) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg(DELAY,462) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q, xout => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,477) -- every=1, low=0, high=4, step=1, init=1 ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 3 THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 4; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,3)); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,478) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,479) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q) BEGIN CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q; WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,476) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 5, width_b => 8, widthad_b => 3, numwords_b => 5, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq, address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa, data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia ); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0); --memoryC3_uid67_sqrtTableGenerator_lutmem(DUALMEM,137)@8 memoryC3_uid67_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC3_uid67_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC3_uid67_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q; memoryC3_uid67_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 33, widthad_a => 8, numwords_a => 256, width_b => 33, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC3_uid67_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC3_uid67_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC3_uid67_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC3_uid67_sqrtTableGenerator_lutmem_iq, address_a => memoryC3_uid67_sqrtTableGenerator_lutmem_aa, data_a => memoryC3_uid67_sqrtTableGenerator_lutmem_ia ); memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC3_uid67_sqrtTableGenerator_lutmem_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_iq(32 downto 0); --reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0(REG,169)@10 reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid83_sqrtPolynomialEvaluator(ADD,82)@11 sumAHighB_uid83_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((33 downto 33 => reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q(32)) & reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q); sumAHighB_uid83_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((33 downto 26 => highBBits_uid82_sqrtPolynomialEvaluator_b(25)) & highBBits_uid82_sqrtPolynomialEvaluator_b); sumAHighB_uid83_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_b)); sumAHighB_uid83_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_o(33 downto 0); --lowRangeB_uid81_sqrtPolynomialEvaluator(BITSELECT,80)@11 lowRangeB_uid81_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid81_sqrtPolynomialEvaluator_b <= lowRangeB_uid81_sqrtPolynomialEvaluator_in(0 downto 0); --s2_uid81_uid84_sqrtPolynomialEvaluator(BITJOIN,83)@11 s2_uid81_uid84_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_q & lowRangeB_uid81_sqrtPolynomialEvaluator_b; --reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1(REG,171)@11 reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= s2_uid81_uid84_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor(LOGICAL,524) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q <= not (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a or ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top(CONSTANT,520) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q <= "0101"; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp(LOGICAL,521) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q <= "1" when ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a = ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b else "0"; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg(REG,522) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena(REG,525) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd(LOGICAL,526) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b <= en; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a and ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b; --yT3_uid85_sqrtPolynomialEvaluator(BITSELECT,84)@3 yT3_uid85_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT3_uid85_sqrtPolynomialEvaluator_b <= yT3_uid85_sqrtPolynomialEvaluator_in(44 downto 12); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg(DELAY,514) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg : dspba_delay GENERIC MAP ( width => 33, depth => 1 ) PORT MAP ( xin => yT3_uid85_sqrtPolynomialEvaluator_b, xout => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt(COUNTER,516) -- every=1, low=0, high=5, step=1, init=1 ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i = 4 THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i - 5; ELSE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i,3)); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg(REG,517) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux(MUX,518) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s <= en; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux: PROCESS (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q) BEGIN CASE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s IS WHEN "0" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; WHEN "1" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem(DUALMEM,515) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 33, widthad_a => 3, numwords_a => 6, width_b => 33, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq, address_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa, data_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia ); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 <= areset; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq(32 downto 0); --reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0(REG,170)@11 reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q; END IF; END IF; END PROCESS; --prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator(MULT,109)@12 prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a),34)) * SIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr,68)); END IF; END IF; END PROCESS; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator(BITSELECT,110)@15 prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in(67 downto 34); --highBBits_uid88_sqrtPolynomialEvaluator(BITSELECT,87)@15 highBBits_uid88_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b; highBBits_uid88_sqrtPolynomialEvaluator_b <= highBBits_uid88_sqrtPolynomialEvaluator_in(33 downto 1); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,537) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,533) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01000"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,534) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b else "0"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,535) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,538) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,539) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,501) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,529) -- every=1, low=0, high=8, step=1, init=1 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 7 THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1'; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 8; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4)); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,530) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,531) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q) BEGIN CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,528) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 9, width_b => 8, widthad_b => 4, numwords_b => 9, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0(REG,172)@11 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC2_uid65_sqrtTableGenerator_lutmem(DUALMEM,136)@12 memoryC2_uid65_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC2_uid65_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC2_uid65_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q; memoryC2_uid65_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC2_uid65_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid65_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid65_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid65_sqrtTableGenerator_lutmem_iq, address_a => memoryC2_uid65_sqrtTableGenerator_lutmem_aa, data_a => memoryC2_uid65_sqrtTableGenerator_lutmem_ia ); memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC2_uid65_sqrtTableGenerator_lutmem_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0(REG,173)@14 reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid89_sqrtPolynomialEvaluator(ADD,88)@15 sumAHighB_uid89_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q(39)) & reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q); sumAHighB_uid89_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((40 downto 33 => highBBits_uid88_sqrtPolynomialEvaluator_b(32)) & highBBits_uid88_sqrtPolynomialEvaluator_b); sumAHighB_uid89_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_b)); sumAHighB_uid89_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_o(40 downto 0); --lowRangeB_uid87_sqrtPolynomialEvaluator(BITSELECT,86)@15 lowRangeB_uid87_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid87_sqrtPolynomialEvaluator_b <= lowRangeB_uid87_sqrtPolynomialEvaluator_in(0 downto 0); --s3_uid87_uid90_sqrtPolynomialEvaluator(BITJOIN,89)@15 s3_uid87_uid90_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_q & lowRangeB_uid87_sqrtPolynomialEvaluator_b; --yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,118)@15 yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q; yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 24); --reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9(REG,177)@15 reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor(LOGICAL,448) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top(CONSTANT,444) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q <= "01001"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp(LOGICAL,445) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b else "0"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg(REG,446) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena(REG,449) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,450) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg(DELAY,438) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => FracX44dto0_uid37_fpSqrtTest_b, xout => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,440) -- every=1, low=0, high=9, step=1, init=1 ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 8 THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1'; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 9; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i,4)); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg(REG,441) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,442) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q) BEGIN CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s IS WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q; WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q; WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,439) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 10, width_b => 45, widthad_b => 4, numwords_b => 10, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0, clock1 => clk, address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq, address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa, data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia ); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq(44 downto 0); --yT4_uid91_sqrtPolynomialEvaluator(BITSELECT,90)@15 yT4_uid91_sqrtPolynomialEvaluator_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q; yT4_uid91_sqrtPolynomialEvaluator_b <= yT4_uid91_sqrtPolynomialEvaluator_in(44 downto 5); --xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,117)@15 xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b(12 downto 0); xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in(12 downto 0); --GND(CONSTANT,0) GND_q <= "0"; --pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,120)@15 pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7(REG,176)@15 reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,116)@15 yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q(14 downto 0); yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b <= yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in(14 downto 0); --spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,119)@15 spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q <= GND_q & yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b; --pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,121)@15 pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q <= spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q & STD_LOGIC_VECTOR((1 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6(REG,175)@15 reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,115)@15 xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b; xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 22); --reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4(REG,174)@15 reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma(CHAINMULTADD,140)@16 multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0),19)); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1),19)); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0) <= RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0),38) + RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1),38); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a <= (others => (others => '0')); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c <= (others => (others => '0')); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q),18); IF (en = "1") THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0); END IF; END IF; END PROCESS; multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_delay : dspba_delay GENERIC MAP (width => 37, depth => 1) PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q, clk => clk, aclr => areset); --multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,123)@19 multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q; multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in(36 downto 2); --highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,125)@19 highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b; highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b <= highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in(34 downto 6); --yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,113)@15 yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q; yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 15); --reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1(REG,179)@15 reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,112)@15 xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b; xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 13); --reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0(REG,178)@15 reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator(MULT,114)@16 topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a),28)) * SIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= (others => '0'); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= (others => '0'); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr,54)); END IF; END IF; END PROCESS; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator(ADD,126)@19 sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q(53)) & topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b(28)) & highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b)); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o(54 downto 0); --lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,124)@19 lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b(5 downto 0); lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b <= lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in(5 downto 0); --add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,127)@19 add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q & lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b; --R_uid129_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,128)@19 R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in <= add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q(59 downto 0); R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in(59 downto 17); --reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1(REG,181)@19 reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= "0000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,511) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,507) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01100"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,508) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b else "0"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,509) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,512) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,513) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,503) -- every=1, low=0, high=12, step=1, init=1 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 11 THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1'; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 12; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4)); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,504) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,505) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q) BEGIN CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,502) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 13, width_b => 8, widthad_b => 4, numwords_b => 13, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0(REG,157)@15 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC1_uid63_sqrtTableGenerator_lutmem(DUALMEM,135)@16 memoryC1_uid63_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid63_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid63_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q; memoryC1_uid63_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 9, widthad_a => 8, numwords_a => 256, width_b => 9, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC1_uid63_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid63_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid63_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid63_sqrtTableGenerator_lutmem_iq, address_a => memoryC1_uid63_sqrtTableGenerator_lutmem_aa, data_a => memoryC1_uid63_sqrtTableGenerator_lutmem_ia ); memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC1_uid63_sqrtTableGenerator_lutmem_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_iq(8 downto 0); --reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1(REG,160)@18 reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= "000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --memoryC1_uid62_sqrtTableGenerator_lutmem(DUALMEM,134)@16 memoryC1_uid62_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid62_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid62_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q; memoryC1_uid62_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC1_uid62_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid62_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid62_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid62_sqrtTableGenerator_lutmem_iq, address_a => memoryC1_uid62_sqrtTableGenerator_lutmem_aa, data_a => memoryC1_uid62_sqrtTableGenerator_lutmem_ia ); memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC1_uid62_sqrtTableGenerator_lutmem_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0(REG,159)@18 reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --os_uid64_sqrtTableGenerator(BITJOIN,63)@19 os_uid64_sqrtTableGenerator_q <= reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q & reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q; --rndBit_uid93_sqrtPolynomialEvaluator(CONSTANT,92) rndBit_uid93_sqrtPolynomialEvaluator_q <= "01"; --cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator(BITJOIN,93)@19 cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q <= os_uid64_sqrtTableGenerator_q & rndBit_uid93_sqrtPolynomialEvaluator_q; --reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0(REG,180)@19 reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ts4_uid95_sqrtPolynomialEvaluator(ADD,94)@20 ts4_uid95_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((51 downto 51 => reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q(50)) & reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q); ts4_uid95_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((51 downto 43 => reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q(42)) & reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q); ts4_uid95_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid95_sqrtPolynomialEvaluator_a) + SIGNED(ts4_uid95_sqrtPolynomialEvaluator_b)); ts4_uid95_sqrtPolynomialEvaluator_q <= ts4_uid95_sqrtPolynomialEvaluator_o(51 downto 0); --s4_uid96_sqrtPolynomialEvaluator(BITSELECT,95)@20 s4_uid96_sqrtPolynomialEvaluator_in <= ts4_uid95_sqrtPolynomialEvaluator_q; s4_uid96_sqrtPolynomialEvaluator_b <= s4_uid96_sqrtPolynomialEvaluator_in(51 downto 1); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1(BITSELECT,144)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in <= STD_LOGIC_VECTOR((53 downto 51 => s4_uid96_sqrtPolynomialEvaluator_b(50)) & s4_uid96_sqrtPolynomialEvaluator_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in(53 downto 27); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1(REG,187)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor(LOGICAL,498) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top(CONSTANT,494) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q <= "01110"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp(LOGICAL,495) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b else "0"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg(REG,496) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena(REG,499) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd(LOGICAL,500) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt(COUNTER,490) -- every=1, low=0, high=14, step=1, init=1 ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i = 13 THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '1'; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i - 14; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i,4)); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg(REG,491) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux(MUX,492) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q) BEGIN CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s IS WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q; WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q; WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem(DUALMEM,489) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 15, width_b => 45, widthad_b => 4, numwords_b => 15, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq, address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa, data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia ); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 <= areset; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq(44 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1(BITSELECT,142)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in <= STD_LOGIC_VECTOR("000000000" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in(53 downto 27); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0(REG,184)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1(MULT,148)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr,54)); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1; END IF; END IF; END PROCESS; --ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a(DELAY,349)@24 ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a : dspba_delay GENERIC MAP ( width => 54, depth => 2 ) PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q, ena => en(0), clk => clk, aclr => areset ); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2(BITSHIFT,152)@26 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q & "000000000000000000000000000000000000000000000000000000"; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int(107 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0(BITSELECT,141)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q(26 downto 0); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in(26 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0(REG,182)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1(MULT,147)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr,54)); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0(BITSELECT,143)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in <= s4_uid96_sqrtPolynomialEvaluator_b(26 downto 0); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in(26 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1(REG,183)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0(MULT,146)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0(ADD,149)@24 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR('0' & "00" & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR((56 downto 54 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q(53)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b)); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o(55 downto 0); --ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a(DELAY,348)@24 ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a : dspba_delay GENERIC MAP ( width => 56, depth => 1 ) PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q, ena => en(0), clk => clk, aclr => areset ); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1(BITSHIFT,151)@25 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q & "000000000000000000000000000"; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int(82 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0(MULT,145)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0(BITSHIFT,150)@24 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int(53 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0(REG,188)@24 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0(ADD,153)@25 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q(82)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b)); END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o(83 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0(ADD,154)@26 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a <= STD_LOGIC_VECTOR((108 downto 84 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q(83)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b <= STD_LOGIC_VECTOR((108 downto 108 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q(107)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b)); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o(108 downto 0); --prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator(BITSELECT,130)@26 prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q(95 downto 0); prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in(95 downto 44); --highBBits_uid100_sqrtPolynomialEvaluator(BITSELECT,99)@26 highBBits_uid100_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b; highBBits_uid100_sqrtPolynomialEvaluator_b <= highBBits_uid100_sqrtPolynomialEvaluator_in(51 downto 2); --reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1(REG,196)@26 reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= highBBits_uid100_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor(LOGICAL,472) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,468) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q <= "010011"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,469) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b else "0"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg(REG,470) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena(REG,473) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,474) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,464) -- every=1, low=0, high=19, step=1, init=1 ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 18 THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 19; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,5)); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,465) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,466) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q) BEGIN CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,463) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 5, numwords_a => 20, width_b => 8, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq, address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa, data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia ); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0); --memoryC0_uid60_sqrtTableGenerator_lutmem(DUALMEM,133)@23 memoryC0_uid60_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid60_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid60_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q; memoryC0_uid60_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 17, widthad_a => 8, numwords_a => 256, width_b => 17, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC0_uid60_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid60_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid60_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid60_sqrtTableGenerator_lutmem_iq, address_a => memoryC0_uid60_sqrtTableGenerator_lutmem_aa, data_a => memoryC0_uid60_sqrtTableGenerator_lutmem_ia ); memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC0_uid60_sqrtTableGenerator_lutmem_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_iq(16 downto 0); --reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1(REG,194)@25 reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,550) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,551) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,552) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,541) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 5, numwords_a => 20, width_b => 8, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0(REG,191)@22 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC0_uid59_sqrtTableGenerator_lutmem(DUALMEM,132)@23 memoryC0_uid59_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid59_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid59_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q; memoryC0_uid59_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC0_uid59_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid59_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid59_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid59_sqrtTableGenerator_lutmem_iq, address_a => memoryC0_uid59_sqrtTableGenerator_lutmem_aa, data_a => memoryC0_uid59_sqrtTableGenerator_lutmem_ia ); memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC0_uid59_sqrtTableGenerator_lutmem_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0(REG,193)@25 reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --os_uid61_sqrtTableGenerator(BITJOIN,60)@26 os_uid61_sqrtTableGenerator_q <= reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q & reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q; --reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0(REG,195)@26 reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= os_uid61_sqrtTableGenerator_q; END IF; END IF; END PROCESS; --sumAHighB_uid101_sqrtPolynomialEvaluator(ADD,100)@27 sumAHighB_uid101_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((57 downto 57 => reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q(56)) & reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q); sumAHighB_uid101_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((57 downto 50 => reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q(49)) & reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q); sumAHighB_uid101_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_b)); sumAHighB_uid101_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_o(57 downto 0); --lowRangeB_uid99_sqrtPolynomialEvaluator(BITSELECT,98)@26 lowRangeB_uid99_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b(1 downto 0); lowRangeB_uid99_sqrtPolynomialEvaluator_b <= lowRangeB_uid99_sqrtPolynomialEvaluator_in(1 downto 0); --reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0(REG,197)@26 reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= lowRangeB_uid99_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --s5_uid99_uid102_sqrtPolynomialEvaluator(BITJOIN,101)@27 s5_uid99_uid102_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_q & reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q; --fracR_uid39_fpSqrtTest(BITSELECT,38)@27 fracR_uid39_fpSqrtTest_in <= s5_uid99_uid102_sqrtPolynomialEvaluator_q(56 downto 0); fracR_uid39_fpSqrtTest_b <= fracR_uid39_fpSqrtTest_in(56 downto 5); --reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3(REG,198)@27 reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= "0000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= fracR_uid39_fpSqrtTest_b; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor(LOGICAL,409) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q <= not (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a or ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena(REG,410) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd(LOGICAL,411) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a and ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg(DELAY,399) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => fracSel_uid47_fpSqrtTest_q, xout => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem(DUALMEM,400) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 2, widthad_a => 5, numwords_a => 24, width_b => 2, widthad_b => 5, numwords_b => 24, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq, address_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa, data_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia ); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 <= areset; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq(1 downto 0); --fracRPostExc_uid55_fpSqrtTest(MUX,54)@28 fracRPostExc_uid55_fpSqrtTest_s <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q; fracRPostExc_uid55_fpSqrtTest: PROCESS (fracRPostExc_uid55_fpSqrtTest_s, en, cstAllZWF_uid10_fpSqrtTest_q, reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q, cstAllZWF_uid10_fpSqrtTest_q, fracNaN_uid52_fpSqrtTest_q) BEGIN CASE fracRPostExc_uid55_fpSqrtTest_s IS WHEN "00" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q; WHEN "01" => fracRPostExc_uid55_fpSqrtTest_q <= reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q; WHEN "10" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q; WHEN "11" => fracRPostExc_uid55_fpSqrtTest_q <= fracNaN_uid52_fpSqrtTest_q; WHEN OTHERS => fracRPostExc_uid55_fpSqrtTest_q <= (others => '0'); END CASE; END PROCESS; --RSqrt_uid57_fpSqrtTest(BITJOIN,56)@28 RSqrt_uid57_fpSqrtTest_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q & ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q & fracRPostExc_uid55_fpSqrtTest_q; --xOut(GPOUT,4)@28 q <= RSqrt_uid57_fpSqrtTest_q; end normal;
----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Release Version 13.1 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from fp_sqrt_double_s5 -- VHDL created on Tue Apr 9 15:17:30 2013 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; entity fp_sqrt_double_s5 is port ( a : in std_logic_vector(63 downto 0); en : in std_logic_vector(0 downto 0); q : out std_logic_vector(63 downto 0); clk : in std_logic; areset : in std_logic ); end; architecture normal of fp_sqrt_double_s5 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstAllOWE_uid9_fpSqrtTest_q : std_logic_vector (10 downto 0); signal cstAllZWF_uid10_fpSqrtTest_q : std_logic_vector (51 downto 0); signal cstAllZWE_uid11_fpSqrtTest_q : std_logic_vector (10 downto 0); signal sBias_uid25_fpSqrtTest_q : std_logic_vector (10 downto 0); signal sBiasM1_uid28_fpSqrtTest_q : std_logic_vector (10 downto 0); signal expRMux_uid33_fpSqrtTest_s : std_logic_vector (0 downto 0); signal expRMux_uid33_fpSqrtTest_q : std_logic_vector (10 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_a : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_b : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid41_fpSqrtTest_q : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_a : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_b : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal minReg_uid42_fpSqrtTest_q : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_a : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_b : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal minInf_uid43_fpSqrtTest_q : std_logic_vector(0 downto 0); signal fracSel_uid47_fpSqrtTest_q : std_logic_vector(1 downto 0); signal fracNaN_uid52_fpSqrtTest_q : std_logic_vector (51 downto 0); signal negZero_uid56_fpSqrtTest_a : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_b : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_q_i : std_logic_vector(0 downto 0); signal negZero_uid56_fpSqrtTest_q : std_logic_vector(0 downto 0); signal rndBit_uid93_sqrtPolynomialEvaluator_q : std_logic_vector (1 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a : std_logic_vector (16 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 : std_logic_vector (33 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr : SIGNED (34 downto 0); signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a : std_logic_vector (23 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 : std_logic_vector (49 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr : SIGNED (50 downto 0); signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q : std_logic_vector (49 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a : std_logic_vector (32 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 : std_logic_vector (67 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr : SIGNED (68 downto 0); signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q : std_logic_vector (67 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector (26 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 : std_logic_vector (53 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr : SIGNED (54 downto 0); signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (53 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid59_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC0_uid59_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid60_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0); signal memoryC0_uid60_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid62_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC1_uid62_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid63_sqrtTableGenerator_lutmem_ia : std_logic_vector (8 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_iq : std_logic_vector (8 downto 0); signal memoryC1_uid63_sqrtTableGenerator_lutmem_q : std_logic_vector (8 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC2_uid65_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0); signal memoryC2_uid65_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC3_uid67_sqrtTableGenerator_lutmem_ia : std_logic_vector (32 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_iq : std_logic_vector (32 downto 0); signal memoryC3_uid67_sqrtTableGenerator_lutmem_q : std_logic_vector (32 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC4_uid69_sqrtTableGenerator_lutmem_ia : std_logic_vector (23 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_iq : std_logic_vector (23 downto 0); signal memoryC4_uid69_sqrtTableGenerator_lutmem_q : std_logic_vector (23 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC5_uid71_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0); signal memoryC5_uid71_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0); type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type; attribute preserve : boolean; attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : signal is true; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type is array(0 to 1) of SIGNED(17 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type; attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : signal is true; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type is array(0 to 1) of SIGNED(18 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type is array(0 to 1) of SIGNED(36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type; type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type; signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s0 : std_logic_vector(36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q : std_logic_vector (36 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr : UNSIGNED (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr : UNSIGNED (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr : SIGNED (54 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr : SIGNED (54 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a : std_logic_vector(84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b : std_logic_vector(84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o : std_logic_vector (84 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q : std_logic_vector (83 downto 0); signal reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q : std_logic_vector (0 downto 0); signal reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q : std_logic_vector (0 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0); signal reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q : std_logic_vector (8 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q : std_logic_vector (16 downto 0); signal reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q : std_logic_vector (16 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0); signal reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0); signal reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q : std_logic_vector (25 downto 0); signal reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0); signal reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0); signal reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q : std_logic_vector (34 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q : std_logic_vector (39 downto 0); signal reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q : std_logic_vector (17 downto 0); signal reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q : std_logic_vector (17 downto 0); signal reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q : std_logic_vector (16 downto 0); signal reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q : std_logic_vector (17 downto 0); signal reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q : std_logic_vector (26 downto 0); signal reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q : std_logic_vector (50 downto 0); signal reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q : std_logic_vector (42 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q : std_logic_vector (26 downto 0); signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q : std_logic_vector (53 downto 0); signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0); signal reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q : std_logic_vector (16 downto 0); signal reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q : std_logic_vector (56 downto 0); signal reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q : std_logic_vector (49 downto 0); signal reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q : std_logic_vector (1 downto 0); signal reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q : std_logic_vector (51 downto 0); signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q : std_logic_vector (51 downto 0); signal ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q : std_logic_vector (0 downto 0); signal ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q : std_logic_vector (10 downto 0); signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q : std_logic_vector (55 downto 0); signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q : std_logic_vector (53 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0); signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q : std_logic_vector (51 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 : std_logic; signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q : std_logic_vector (1 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq : std_logic; signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : signal is true; signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 : std_logic; signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : signal is true; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 : std_logic; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i : unsigned(4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq : std_logic; signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q : std_logic_vector (5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : signal is true; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true; signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic; signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (23 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic; signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq : std_logic; signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 : std_logic; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q : std_logic_vector (32 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq : std_logic; signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a : std_logic_vector(56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b : std_logic_vector(56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o : std_logic_vector (56 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q : std_logic_vector (55 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal expX_uid6_fpSqrtTest_in : std_logic_vector (62 downto 0); signal expX_uid6_fpSqrtTest_b : std_logic_vector (10 downto 0); signal fracX_uid7_fpSqrtTest_in : std_logic_vector (51 downto 0); signal fracX_uid7_fpSqrtTest_b : std_logic_vector (51 downto 0); signal signX_uid8_fpSqrtTest_in : std_logic_vector (63 downto 0); signal signX_uid8_fpSqrtTest_b : std_logic_vector (0 downto 0); signal expXIsZero_uid13_fpSqrtTest_a : std_logic_vector(10 downto 0); signal expXIsZero_uid13_fpSqrtTest_b : std_logic_vector(10 downto 0); signal expXIsZero_uid13_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid15_fpSqrtTest_a : std_logic_vector(10 downto 0); signal expXIsMax_uid15_fpSqrtTest_b : std_logic_vector(10 downto 0); signal expXIsMax_uid15_fpSqrtTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid17_fpSqrtTest_a : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSqrtTest_b : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSqrtTest_q : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_I_uid18_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expEvenSig_uid26_fpSqrtTest_a : std_logic_vector(11 downto 0); signal expEvenSig_uid26_fpSqrtTest_b : std_logic_vector(11 downto 0); signal expEvenSig_uid26_fpSqrtTest_o : std_logic_vector (11 downto 0); signal expEvenSig_uid26_fpSqrtTest_q : std_logic_vector (11 downto 0); signal expOddSig_uid29_fpSqrtTest_a : std_logic_vector(11 downto 0); signal expOddSig_uid29_fpSqrtTest_b : std_logic_vector(11 downto 0); signal expOddSig_uid29_fpSqrtTest_o : std_logic_vector (11 downto 0); signal expOddSig_uid29_fpSqrtTest_q : std_logic_vector (11 downto 0); signal excRNaN_uid44_fpSqrtTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid44_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expRPostExc_uid51_fpSqrtTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid51_fpSqrtTest_q : std_logic_vector (10 downto 0); signal fracRPostExc_uid55_fpSqrtTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid55_fpSqrtTest_q : std_logic_vector (51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_a : std_logic_vector(51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_b : std_logic_vector(51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_o : std_logic_vector (51 downto 0); signal ts4_uid95_sqrtPolynomialEvaluator_q : std_logic_vector (51 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_a : std_logic_vector(57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_b : std_logic_vector(57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_o : std_logic_vector (57 downto 0); signal sumAHighB_uid101_sqrtPolynomialEvaluator_q : std_logic_vector (57 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal join_uid45_fpSqrtTest_q : std_logic_vector (2 downto 0); signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0); signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in : std_logic_vector (49 downto 0); signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in : std_logic_vector (67 downto 0); signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (33 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (36 downto 0); signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q : std_logic_vector (53 downto 0); signal os_uid64_sqrtTableGenerator_q : std_logic_vector (48 downto 0); signal os_uid61_sqrtTableGenerator_q : std_logic_vector (56 downto 0); signal s5_uid99_uid102_sqrtPolynomialEvaluator_q : std_logic_vector (59 downto 0); signal FracX44dto0_uid37_fpSqrtTest_in : std_logic_vector (44 downto 0); signal FracX44dto0_uid37_fpSqrtTest_b : std_logic_vector (44 downto 0); signal fracSelIn_uid46_fpSqrtTest_q : std_logic_vector (3 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int : std_logic_vector (82 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q : std_logic_vector (82 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int : std_logic_vector (107 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q : std_logic_vector (107 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0); signal RSqrt_uid57_fpSqrtTest_q : std_logic_vector (63 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a : std_logic_vector(5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b : std_logic_vector(5 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q : std_logic_vector(0 downto 0); signal yT4_uid91_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT4_uid91_sqrtPolynomialEvaluator_b : std_logic_vector (39 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(5 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(3 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b : std_logic_vector (26 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a : std_logic_vector(3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b : std_logic_vector(3 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal expX0_uid31_fpSqrtTest_in : std_logic_vector (0 downto 0); signal expX0_uid31_fpSqrtTest_b : std_logic_vector (0 downto 0); signal fracXAddr_uid35_fpSqrtTest_in : std_logic_vector (51 downto 0); signal fracXAddr_uid35_fpSqrtTest_b : std_logic_vector (6 downto 0); signal InvSignX_uid40_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvSignX_uid40_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSqrtTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid22_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid22_fpSqrtTest_q : std_logic_vector(0 downto 0); signal expREven_uid27_fpSqrtTest_in : std_logic_vector (11 downto 0); signal expREven_uid27_fpSqrtTest_b : std_logic_vector (10 downto 0); signal expROdd_uid30_fpSqrtTest_in : std_logic_vector (11 downto 0); signal expROdd_uid30_fpSqrtTest_b : std_logic_vector (10 downto 0); signal s4_uid96_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0); signal s4_uid96_sqrtPolynomialEvaluator_b : std_logic_vector (50 downto 0); signal lowRangeB_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid76_sqrtPolynomialEvaluator_in : std_logic_vector (17 downto 0); signal highBBits_uid76_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal lowRangeB_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid82_sqrtPolynomialEvaluator_in : std_logic_vector (26 downto 0); signal highBBits_uid82_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0); signal lowRangeB_uid87_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid87_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid88_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0); signal highBBits_uid88_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0); signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (5 downto 0); signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (5 downto 0); signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (34 downto 0); signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (28 downto 0); signal cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q : std_logic_vector (50 downto 0); signal fracR_uid39_fpSqrtTest_in : std_logic_vector (56 downto 0); signal fracR_uid39_fpSqrtTest_b : std_logic_vector (51 downto 0); signal yT1_uid73_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT1_uid73_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0); signal yT2_uid79_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT2_uid79_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0); signal yT3_uid85_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0); signal yT3_uid85_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a : std_logic_vector(108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b : std_logic_vector(108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o : std_logic_vector (108 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q : std_logic_vector (108 downto 0); signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0); signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0); signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0); signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0); signal expOddSelect_uid32_fpSqrtTest_a : std_logic_vector(0 downto 0); signal expOddSelect_uid32_fpSqrtTest_q : std_logic_vector(0 downto 0); signal addrTable_uid36_fpSqrtTest_q : std_logic_vector (7 downto 0); signal exc_N_uid20_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_N_uid20_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_N_uid20_fpSqrtTest_q : std_logic_vector(0 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b : std_logic_vector (26 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in : std_logic_vector (53 downto 0); signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b : std_logic_vector (26 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_a : std_logic_vector(24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_b : std_logic_vector(24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_o : std_logic_vector (24 downto 0); signal sumAHighB_uid77_sqrtPolynomialEvaluator_q : std_logic_vector (24 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_a : std_logic_vector(33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_b : std_logic_vector(33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_o : std_logic_vector (33 downto 0); signal sumAHighB_uid83_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_a : std_logic_vector(40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_b : std_logic_vector(40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_o : std_logic_vector (40 downto 0); signal sumAHighB_uid89_sqrtPolynomialEvaluator_q : std_logic_vector (40 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector(54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector(54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o : std_logic_vector (54 downto 0); signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (54 downto 0); signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in : std_logic_vector (95 downto 0); signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b : std_logic_vector (51 downto 0); signal pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (16 downto 0); signal InvExc_N_uid21_fpSqrtTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid21_fpSqrtTest_q : std_logic_vector(0 downto 0); signal s1_uid75_uid78_sqrtPolynomialEvaluator_q : std_logic_vector (25 downto 0); signal s2_uid81_uid84_sqrtPolynomialEvaluator_q : std_logic_vector (34 downto 0); signal s3_uid87_uid90_sqrtPolynomialEvaluator_q : std_logic_vector (41 downto 0); signal add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (60 downto 0); signal lowRangeB_uid99_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0); signal lowRangeB_uid99_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0); signal highBBits_uid100_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0); signal highBBits_uid100_sqrtPolynomialEvaluator_b : std_logic_vector (49 downto 0); signal exc_R_uid24_fpSqrtTest_a : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_b : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_c : std_logic_vector(0 downto 0); signal exc_R_uid24_fpSqrtTest_q : std_logic_vector(0 downto 0); signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0); signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0); signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (14 downto 0); signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (14 downto 0); signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0); signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0); signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (59 downto 0); signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (42 downto 0); signal spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (15 downto 0); signal pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (17 downto 0); begin --VCC(CONSTANT,1) VCC_q <= "1"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable(LOGICAL,408) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q <= not ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor(LOGICAL,435) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q <= not (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a or ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top(CONSTANT,431) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q <= "011000"; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp(LOGICAL,432) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q <= "1" when ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a = ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b else "0"; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg(REG,433) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q; END IF; END IF; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena(REG,436) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd(LOGICAL,437) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b <= en; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a and ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b; --signX_uid8_fpSqrtTest(BITSELECT,7)@0 signX_uid8_fpSqrtTest_in <= a; signX_uid8_fpSqrtTest_b <= signX_uid8_fpSqrtTest_in(63 downto 63); --cstAllZWE_uid11_fpSqrtTest(CONSTANT,10) cstAllZWE_uid11_fpSqrtTest_q <= "00000000000"; --expX_uid6_fpSqrtTest(BITSELECT,5)@0 expX_uid6_fpSqrtTest_in <= a(62 downto 0); expX_uid6_fpSqrtTest_b <= expX_uid6_fpSqrtTest_in(62 downto 52); --expXIsZero_uid13_fpSqrtTest(LOGICAL,12)@0 expXIsZero_uid13_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b; expXIsZero_uid13_fpSqrtTest_b <= cstAllZWE_uid11_fpSqrtTest_q; expXIsZero_uid13_fpSqrtTest_q <= "1" when expXIsZero_uid13_fpSqrtTest_a = expXIsZero_uid13_fpSqrtTest_b else "0"; --negZero_uid56_fpSqrtTest(LOGICAL,55)@0 negZero_uid56_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q; negZero_uid56_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; negZero_uid56_fpSqrtTest_q_i <= negZero_uid56_fpSqrtTest_a and negZero_uid56_fpSqrtTest_b; negZero_uid56_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => negZero_uid56_fpSqrtTest_q, xin => negZero_uid56_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg(DELAY,425) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => negZero_uid56_fpSqrtTest_q, xout => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt(COUNTER,427) -- every=1, low=0, high=24, step=1, init=1 ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i = 23 THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '1'; ELSE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i - 24; ELSE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i,5)); --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg(REG,428) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q; END IF; END IF; END PROCESS; --xIn(GPIN,3)@0 --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux(MUX,429) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s <= en; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux: PROCESS (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q) BEGIN CASE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s IS WHEN "0" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q; WHEN "1" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q; WHEN OTHERS => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem(DUALMEM,426) ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 25, width_b => 1, widthad_b => 5, numwords_b => 25, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq, address_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa, data_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia ); ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 <= areset; ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq(0 downto 0); --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor(LOGICAL,422) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q <= not (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a or ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top(CONSTANT,405) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q <= "010111"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp(LOGICAL,406) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q <= "1" when ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a = ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b else "0"; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg(REG,407) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena(REG,423) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q = "1") THEN ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd(LOGICAL,424) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b <= en; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a and ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b; --cstAllOWE_uid9_fpSqrtTest(CONSTANT,8) cstAllOWE_uid9_fpSqrtTest_q <= "11111111111"; --sBiasM1_uid28_fpSqrtTest(CONSTANT,27) sBiasM1_uid28_fpSqrtTest_q <= "01111111110"; --expOddSig_uid29_fpSqrtTest(ADD,28)@0 expOddSig_uid29_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b); expOddSig_uid29_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBiasM1_uid28_fpSqrtTest_q); expOddSig_uid29_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid29_fpSqrtTest_a) + UNSIGNED(expOddSig_uid29_fpSqrtTest_b)); expOddSig_uid29_fpSqrtTest_q <= expOddSig_uid29_fpSqrtTest_o(11 downto 0); --expROdd_uid30_fpSqrtTest(BITSELECT,29)@0 expROdd_uid30_fpSqrtTest_in <= expOddSig_uid29_fpSqrtTest_q; expROdd_uid30_fpSqrtTest_b <= expROdd_uid30_fpSqrtTest_in(11 downto 1); --sBias_uid25_fpSqrtTest(CONSTANT,24) sBias_uid25_fpSqrtTest_q <= "01111111111"; --expEvenSig_uid26_fpSqrtTest(ADD,25)@0 expEvenSig_uid26_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b); expEvenSig_uid26_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBias_uid25_fpSqrtTest_q); expEvenSig_uid26_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid26_fpSqrtTest_a) + UNSIGNED(expEvenSig_uid26_fpSqrtTest_b)); expEvenSig_uid26_fpSqrtTest_q <= expEvenSig_uid26_fpSqrtTest_o(11 downto 0); --expREven_uid27_fpSqrtTest(BITSELECT,26)@0 expREven_uid27_fpSqrtTest_in <= expEvenSig_uid26_fpSqrtTest_q; expREven_uid27_fpSqrtTest_b <= expREven_uid27_fpSqrtTest_in(11 downto 1); --expX0_uid31_fpSqrtTest(BITSELECT,30)@0 expX0_uid31_fpSqrtTest_in <= expX_uid6_fpSqrtTest_b(0 downto 0); expX0_uid31_fpSqrtTest_b <= expX0_uid31_fpSqrtTest_in(0 downto 0); --expOddSelect_uid32_fpSqrtTest(LOGICAL,31)@0 expOddSelect_uid32_fpSqrtTest_a <= expX0_uid31_fpSqrtTest_b; expOddSelect_uid32_fpSqrtTest_q <= not expOddSelect_uid32_fpSqrtTest_a; --expRMux_uid33_fpSqrtTest(MUX,32)@0 expRMux_uid33_fpSqrtTest_s <= expOddSelect_uid32_fpSqrtTest_q; expRMux_uid33_fpSqrtTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRMux_uid33_fpSqrtTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE expRMux_uid33_fpSqrtTest_s IS WHEN "0" => expRMux_uid33_fpSqrtTest_q <= expREven_uid27_fpSqrtTest_b; WHEN "1" => expRMux_uid33_fpSqrtTest_q <= expROdd_uid30_fpSqrtTest_b; WHEN OTHERS => expRMux_uid33_fpSqrtTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d(DELAY,248)@1 ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => expRMux_uid33_fpSqrtTest_q, xout => ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, ena => en(0), clk => clk, aclr => areset ); --ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b(DELAY,245)@0 ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signX_uid8_fpSqrtTest_b, xout => ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset ); --cstAllZWF_uid10_fpSqrtTest(CONSTANT,9) cstAllZWF_uid10_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000000"; --fracX_uid7_fpSqrtTest(BITSELECT,6)@0 fracX_uid7_fpSqrtTest_in <= a(51 downto 0); fracX_uid7_fpSqrtTest_b <= fracX_uid7_fpSqrtTest_in(51 downto 0); --fracXIsZero_uid17_fpSqrtTest(LOGICAL,16)@0 fracXIsZero_uid17_fpSqrtTest_a <= fracX_uid7_fpSqrtTest_b; fracXIsZero_uid17_fpSqrtTest_b <= cstAllZWF_uid10_fpSqrtTest_q; fracXIsZero_uid17_fpSqrtTest_q <= "1" when fracXIsZero_uid17_fpSqrtTest_a = fracXIsZero_uid17_fpSqrtTest_b else "0"; --InvFracXIsZero_uid19_fpSqrtTest(LOGICAL,18)@0 InvFracXIsZero_uid19_fpSqrtTest_a <= fracXIsZero_uid17_fpSqrtTest_q; InvFracXIsZero_uid19_fpSqrtTest_q <= not InvFracXIsZero_uid19_fpSqrtTest_a; --expXIsMax_uid15_fpSqrtTest(LOGICAL,14)@0 expXIsMax_uid15_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b; expXIsMax_uid15_fpSqrtTest_b <= cstAllOWE_uid9_fpSqrtTest_q; expXIsMax_uid15_fpSqrtTest_q <= "1" when expXIsMax_uid15_fpSqrtTest_a = expXIsMax_uid15_fpSqrtTest_b else "0"; --exc_N_uid20_fpSqrtTest(LOGICAL,19)@0 exc_N_uid20_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q; exc_N_uid20_fpSqrtTest_b <= InvFracXIsZero_uid19_fpSqrtTest_q; exc_N_uid20_fpSqrtTest_q <= exc_N_uid20_fpSqrtTest_a and exc_N_uid20_fpSqrtTest_b; --InvExc_N_uid21_fpSqrtTest(LOGICAL,20)@0 InvExc_N_uid21_fpSqrtTest_a <= exc_N_uid20_fpSqrtTest_q; InvExc_N_uid21_fpSqrtTest_q <= not InvExc_N_uid21_fpSqrtTest_a; --exc_I_uid18_fpSqrtTest(LOGICAL,17)@0 exc_I_uid18_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q; exc_I_uid18_fpSqrtTest_b <= fracXIsZero_uid17_fpSqrtTest_q; exc_I_uid18_fpSqrtTest_q <= exc_I_uid18_fpSqrtTest_a and exc_I_uid18_fpSqrtTest_b; --InvExc_I_uid22_fpSqrtTest(LOGICAL,21)@0 InvExc_I_uid22_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; InvExc_I_uid22_fpSqrtTest_q <= not InvExc_I_uid22_fpSqrtTest_a; --InvExpXIsZero_uid23_fpSqrtTest(LOGICAL,22)@0 InvExpXIsZero_uid23_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q; InvExpXIsZero_uid23_fpSqrtTest_q <= not InvExpXIsZero_uid23_fpSqrtTest_a; --exc_R_uid24_fpSqrtTest(LOGICAL,23)@0 exc_R_uid24_fpSqrtTest_a <= InvExpXIsZero_uid23_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_b <= InvExc_I_uid22_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_c <= InvExc_N_uid21_fpSqrtTest_q; exc_R_uid24_fpSqrtTest_q <= exc_R_uid24_fpSqrtTest_a and exc_R_uid24_fpSqrtTest_b and exc_R_uid24_fpSqrtTest_c; --minReg_uid42_fpSqrtTest(LOGICAL,41)@0 minReg_uid42_fpSqrtTest_a <= exc_R_uid24_fpSqrtTest_q; minReg_uid42_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; minReg_uid42_fpSqrtTest_q_i <= minReg_uid42_fpSqrtTest_a and minReg_uid42_fpSqrtTest_b; minReg_uid42_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => minReg_uid42_fpSqrtTest_q, xin => minReg_uid42_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --minInf_uid43_fpSqrtTest(LOGICAL,42)@0 minInf_uid43_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; minInf_uid43_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b; minInf_uid43_fpSqrtTest_q_i <= minInf_uid43_fpSqrtTest_a and minInf_uid43_fpSqrtTest_b; minInf_uid43_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => minInf_uid43_fpSqrtTest_q, xin => minInf_uid43_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1(REG,155)@0 reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= exc_N_uid20_fpSqrtTest_q; END IF; END IF; END PROCESS; --excRNaN_uid44_fpSqrtTest(LOGICAL,43)@1 excRNaN_uid44_fpSqrtTest_a <= reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q; excRNaN_uid44_fpSqrtTest_b <= minInf_uid43_fpSqrtTest_q; excRNaN_uid44_fpSqrtTest_c <= minReg_uid42_fpSqrtTest_q; excRNaN_uid44_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_a or excRNaN_uid44_fpSqrtTest_b or excRNaN_uid44_fpSqrtTest_c; --InvSignX_uid40_fpSqrtTest(LOGICAL,39)@0 InvSignX_uid40_fpSqrtTest_a <= signX_uid8_fpSqrtTest_b; InvSignX_uid40_fpSqrtTest_q <= not InvSignX_uid40_fpSqrtTest_a; --inInfAndNotNeg_uid41_fpSqrtTest(LOGICAL,40)@0 inInfAndNotNeg_uid41_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q; inInfAndNotNeg_uid41_fpSqrtTest_b <= InvSignX_uid40_fpSqrtTest_q; inInfAndNotNeg_uid41_fpSqrtTest_q_i <= inInfAndNotNeg_uid41_fpSqrtTest_a and inInfAndNotNeg_uid41_fpSqrtTest_b; inInfAndNotNeg_uid41_fpSqrtTest_delay : dspba_delay GENERIC MAP (width => 1, depth => 1) PORT MAP (xout => inInfAndNotNeg_uid41_fpSqrtTest_q, xin => inInfAndNotNeg_uid41_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset); --reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0(REG,156)@0 reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= expXIsZero_uid13_fpSqrtTest_q; END IF; END IF; END PROCESS; --join_uid45_fpSqrtTest(BITJOIN,44)@1 join_uid45_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_q & inInfAndNotNeg_uid41_fpSqrtTest_q & reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q; --fracSelIn_uid46_fpSqrtTest(BITJOIN,45)@1 fracSelIn_uid46_fpSqrtTest_q <= ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q & join_uid45_fpSqrtTest_q; --fracSel_uid47_fpSqrtTest(LOOKUP,46)@1 fracSel_uid47_fpSqrtTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracSel_uid47_fpSqrtTest_q <= "01"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN CASE (fracSelIn_uid46_fpSqrtTest_q) IS WHEN "0000" => fracSel_uid47_fpSqrtTest_q <= "01"; WHEN "0001" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0010" => fracSel_uid47_fpSqrtTest_q <= "10"; WHEN "0011" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0100" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "0101" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "0110" => fracSel_uid47_fpSqrtTest_q <= "10"; WHEN "0111" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "1000" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1001" => fracSel_uid47_fpSqrtTest_q <= "00"; WHEN "1010" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1011" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1100" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1101" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1110" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN "1111" => fracSel_uid47_fpSqrtTest_q <= "11"; WHEN OTHERS => fracSel_uid47_fpSqrtTest_q <= (others => '-'); END CASE; END IF; END IF; END PROCESS; --expRPostExc_uid51_fpSqrtTest(MUX,50)@2 expRPostExc_uid51_fpSqrtTest_s <= fracSel_uid47_fpSqrtTest_q; expRPostExc_uid51_fpSqrtTest: PROCESS (expRPostExc_uid51_fpSqrtTest_s, en, cstAllZWE_uid11_fpSqrtTest_q, ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, cstAllOWE_uid9_fpSqrtTest_q, cstAllOWE_uid9_fpSqrtTest_q) BEGIN CASE expRPostExc_uid51_fpSqrtTest_s IS WHEN "00" => expRPostExc_uid51_fpSqrtTest_q <= cstAllZWE_uid11_fpSqrtTest_q; WHEN "01" => expRPostExc_uid51_fpSqrtTest_q <= ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q; WHEN "10" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q; WHEN "11" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q; WHEN OTHERS => expRPostExc_uid51_fpSqrtTest_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg(DELAY,412) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => expRPostExc_uid51_fpSqrtTest_q, xout => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt(COUNTER,401) -- every=1, low=0, high=23, step=1, init=1 ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i = 22 THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '1'; ELSE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i - 23; ELSE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i,5)); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg(REG,402) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux(MUX,403) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux: PROCESS (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q) BEGIN CASE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s IS WHEN "0" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; WHEN "1" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q; WHEN OTHERS => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem(DUALMEM,413) ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 5, numwords_a => 24, width_b => 11, widthad_b => 5, numwords_b => 24, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq, address_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa, data_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia ); ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 <= areset; ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq(10 downto 0); --fracNaN_uid52_fpSqrtTest(CONSTANT,51) fracNaN_uid52_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000001"; --fracXAddr_uid35_fpSqrtTest(BITSELECT,34)@0 fracXAddr_uid35_fpSqrtTest_in <= fracX_uid7_fpSqrtTest_b; fracXAddr_uid35_fpSqrtTest_b <= fracXAddr_uid35_fpSqrtTest_in(51 downto 45); --addrTable_uid36_fpSqrtTest(BITJOIN,35)@0 addrTable_uid36_fpSqrtTest_q <= expOddSelect_uid32_fpSqrtTest_q & fracXAddr_uid35_fpSqrtTest_b; --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0(REG,161)@0 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= addrTable_uid36_fpSqrtTest_q; END IF; END IF; END PROCESS; --memoryC5_uid71_sqrtTableGenerator_lutmem(DUALMEM,139)@1 memoryC5_uid71_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC5_uid71_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC5_uid71_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q; memoryC5_uid71_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 17, widthad_a => 8, numwords_a => 256, width_b => 17, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC5_uid71_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC5_uid71_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC5_uid71_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC5_uid71_sqrtTableGenerator_lutmem_iq, address_a => memoryC5_uid71_sqrtTableGenerator_lutmem_aa, data_a => memoryC5_uid71_sqrtTableGenerator_lutmem_ia ); memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC5_uid71_sqrtTableGenerator_lutmem_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_iq(16 downto 0); --reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1(REG,163)@3 reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg(DELAY,398) ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg : dspba_delay GENERIC MAP ( width => 52, depth => 1 ) PORT MAP ( xin => fracX_uid7_fpSqrtTest_b, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a(DELAY,229)@0 ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a : dspba_delay GENERIC MAP ( width => 52, depth => 2 ) PORT MAP ( xin => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset ); --FracX44dto0_uid37_fpSqrtTest(BITSELECT,36)@3 FracX44dto0_uid37_fpSqrtTest_in <= ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q(44 downto 0); FracX44dto0_uid37_fpSqrtTest_b <= FracX44dto0_uid37_fpSqrtTest_in(44 downto 0); --yT1_uid73_sqrtPolynomialEvaluator(BITSELECT,72)@3 yT1_uid73_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT1_uid73_sqrtPolynomialEvaluator_b <= yT1_uid73_sqrtPolynomialEvaluator_in(44 downto 28); --reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0(REG,162)@3 reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= yT1_uid73_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator(MULT,103)@4 prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a),18)) * SIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr,34)); END IF; END IF; END PROCESS; prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator(BITSELECT,104)@7 prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in(33 downto 16); --highBBits_uid76_sqrtPolynomialEvaluator(BITSELECT,75)@7 highBBits_uid76_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b; highBBits_uid76_sqrtPolynomialEvaluator_b <= highBBits_uid76_sqrtPolynomialEvaluator_in(17 downto 1); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a(DELAY,363)@0 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0(REG,164)@3 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q; END IF; END IF; END PROCESS; --memoryC4_uid69_sqrtTableGenerator_lutmem(DUALMEM,138)@4 memoryC4_uid69_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC4_uid69_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC4_uid69_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q; memoryC4_uid69_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 8, numwords_a => 256, width_b => 24, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC4_uid69_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC4_uid69_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC4_uid69_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC4_uid69_sqrtTableGenerator_lutmem_iq, address_a => memoryC4_uid69_sqrtTableGenerator_lutmem_aa, data_a => memoryC4_uid69_sqrtTableGenerator_lutmem_ia ); memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC4_uid69_sqrtTableGenerator_lutmem_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_iq(23 downto 0); --reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0(REG,165)@6 reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid77_sqrtPolynomialEvaluator(ADD,76)@7 sumAHighB_uid77_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((24 downto 24 => reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q(23)) & reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q); sumAHighB_uid77_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((24 downto 17 => highBBits_uid76_sqrtPolynomialEvaluator_b(16)) & highBBits_uid76_sqrtPolynomialEvaluator_b); sumAHighB_uid77_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_b)); sumAHighB_uid77_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_o(24 downto 0); --lowRangeB_uid75_sqrtPolynomialEvaluator(BITSELECT,74)@7 lowRangeB_uid75_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid75_sqrtPolynomialEvaluator_b <= lowRangeB_uid75_sqrtPolynomialEvaluator_in(0 downto 0); --s1_uid75_uid78_sqrtPolynomialEvaluator(BITJOIN,77)@7 s1_uid75_uid78_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_q & lowRangeB_uid75_sqrtPolynomialEvaluator_b; --reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1(REG,167)@7 reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= s1_uid75_uid78_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor(LOGICAL,459) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a or ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg(REG,457) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= VCC_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena(REG,460) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,461) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b <= en; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b; --yT2_uid79_sqrtPolynomialEvaluator(BITSELECT,78)@3 yT2_uid79_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT2_uid79_sqrtPolynomialEvaluator_b <= yT2_uid79_sqrtPolynomialEvaluator_in(44 downto 21); --reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0(REG,166)@3 reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= yT2_uid79_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg(DELAY,451) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg : dspba_delay GENERIC MAP ( width => 24, depth => 1 ) PORT MAP ( xin => reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q, xout => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,453) -- every=1, low=0, high=1, step=1, init=1 ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i,1)); --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg(REG,454) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,455) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q) BEGIN CASE ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s IS WHEN "0" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q; WHEN "1" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,452) ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 1, numwords_a => 2, width_b => 24, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq, address_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa, data_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia ); ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset; ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq(23 downto 0); --prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator(MULT,106)@8 prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a),25)) * SIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr,50)); END IF; END IF; END PROCESS; prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator(BITSELECT,107)@11 prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in(49 downto 23); --highBBits_uid82_sqrtPolynomialEvaluator(BITSELECT,81)@11 highBBits_uid82_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b; highBBits_uid82_sqrtPolynomialEvaluator_b <= highBBits_uid82_sqrtPolynomialEvaluator_in(26 downto 1); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor(LOGICAL,485) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,481) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q <= "0100"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,482) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b else "0"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg(REG,483) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena(REG,486) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,487) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg(DELAY,462) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q, xout => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,477) -- every=1, low=0, high=4, step=1, init=1 ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 3 THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 4; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,3)); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,478) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,479) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q) BEGIN CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q; WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,476) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 5, width_b => 8, widthad_b => 3, numwords_b => 5, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq, address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa, data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia ); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0); --memoryC3_uid67_sqrtTableGenerator_lutmem(DUALMEM,137)@8 memoryC3_uid67_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC3_uid67_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC3_uid67_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q; memoryC3_uid67_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 33, widthad_a => 8, numwords_a => 256, width_b => 33, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC3_uid67_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC3_uid67_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC3_uid67_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC3_uid67_sqrtTableGenerator_lutmem_iq, address_a => memoryC3_uid67_sqrtTableGenerator_lutmem_aa, data_a => memoryC3_uid67_sqrtTableGenerator_lutmem_ia ); memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC3_uid67_sqrtTableGenerator_lutmem_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_iq(32 downto 0); --reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0(REG,169)@10 reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid83_sqrtPolynomialEvaluator(ADD,82)@11 sumAHighB_uid83_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((33 downto 33 => reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q(32)) & reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q); sumAHighB_uid83_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((33 downto 26 => highBBits_uid82_sqrtPolynomialEvaluator_b(25)) & highBBits_uid82_sqrtPolynomialEvaluator_b); sumAHighB_uid83_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_b)); sumAHighB_uid83_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_o(33 downto 0); --lowRangeB_uid81_sqrtPolynomialEvaluator(BITSELECT,80)@11 lowRangeB_uid81_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid81_sqrtPolynomialEvaluator_b <= lowRangeB_uid81_sqrtPolynomialEvaluator_in(0 downto 0); --s2_uid81_uid84_sqrtPolynomialEvaluator(BITJOIN,83)@11 s2_uid81_uid84_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_q & lowRangeB_uid81_sqrtPolynomialEvaluator_b; --reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1(REG,171)@11 reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= s2_uid81_uid84_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor(LOGICAL,524) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q <= not (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a or ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top(CONSTANT,520) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q <= "0101"; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp(LOGICAL,521) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q <= "1" when ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a = ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b else "0"; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg(REG,522) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena(REG,525) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd(LOGICAL,526) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b <= en; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a and ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b; --yT3_uid85_sqrtPolynomialEvaluator(BITSELECT,84)@3 yT3_uid85_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b; yT3_uid85_sqrtPolynomialEvaluator_b <= yT3_uid85_sqrtPolynomialEvaluator_in(44 downto 12); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg(DELAY,514) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg : dspba_delay GENERIC MAP ( width => 33, depth => 1 ) PORT MAP ( xin => yT3_uid85_sqrtPolynomialEvaluator_b, xout => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt(COUNTER,516) -- every=1, low=0, high=5, step=1, init=1 ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i = 4 THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i - 5; ELSE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i,3)); --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg(REG,517) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux(MUX,518) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s <= en; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux: PROCESS (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q) BEGIN CASE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s IS WHEN "0" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; WHEN "1" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem(DUALMEM,515) ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 33, widthad_a => 3, numwords_a => 6, width_b => 33, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq, address_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa, data_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia ); ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 <= areset; ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq(32 downto 0); --reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0(REG,170)@11 reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q; END IF; END IF; END PROCESS; --prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator(MULT,109)@12 prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a),34)) * SIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr,68)); END IF; END IF; END PROCESS; prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator(BITSELECT,110)@15 prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in(67 downto 34); --highBBits_uid88_sqrtPolynomialEvaluator(BITSELECT,87)@15 highBBits_uid88_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b; highBBits_uid88_sqrtPolynomialEvaluator_b <= highBBits_uid88_sqrtPolynomialEvaluator_in(33 downto 1); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,537) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,533) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01000"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,534) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b else "0"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,535) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,538) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,539) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,501) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,529) -- every=1, low=0, high=8, step=1, init=1 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 7 THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1'; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 8; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4)); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,530) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,531) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q) BEGIN CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,528) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 9, width_b => 8, widthad_b => 4, numwords_b => 9, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0(REG,172)@11 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC2_uid65_sqrtTableGenerator_lutmem(DUALMEM,136)@12 memoryC2_uid65_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC2_uid65_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC2_uid65_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q; memoryC2_uid65_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC2_uid65_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid65_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid65_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid65_sqrtTableGenerator_lutmem_iq, address_a => memoryC2_uid65_sqrtTableGenerator_lutmem_aa, data_a => memoryC2_uid65_sqrtTableGenerator_lutmem_ia ); memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC2_uid65_sqrtTableGenerator_lutmem_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0(REG,173)@14 reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid89_sqrtPolynomialEvaluator(ADD,88)@15 sumAHighB_uid89_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q(39)) & reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q); sumAHighB_uid89_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((40 downto 33 => highBBits_uid88_sqrtPolynomialEvaluator_b(32)) & highBBits_uid88_sqrtPolynomialEvaluator_b); sumAHighB_uid89_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_b)); sumAHighB_uid89_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_o(40 downto 0); --lowRangeB_uid87_sqrtPolynomialEvaluator(BITSELECT,86)@15 lowRangeB_uid87_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid87_sqrtPolynomialEvaluator_b <= lowRangeB_uid87_sqrtPolynomialEvaluator_in(0 downto 0); --s3_uid87_uid90_sqrtPolynomialEvaluator(BITJOIN,89)@15 s3_uid87_uid90_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_q & lowRangeB_uid87_sqrtPolynomialEvaluator_b; --yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,118)@15 yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q; yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 24); --reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9(REG,177)@15 reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor(LOGICAL,448) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top(CONSTANT,444) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q <= "01001"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp(LOGICAL,445) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b else "0"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg(REG,446) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena(REG,449) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,450) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg(DELAY,438) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => FracX44dto0_uid37_fpSqrtTest_b, xout => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,440) -- every=1, low=0, high=9, step=1, init=1 ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 8 THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1'; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 9; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i,4)); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg(REG,441) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,442) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q) BEGIN CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s IS WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q; WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q; WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,439) ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 10, width_b => 45, widthad_b => 4, numwords_b => 10, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0, clock1 => clk, address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq, address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa, data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia ); ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset; ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq(44 downto 0); --yT4_uid91_sqrtPolynomialEvaluator(BITSELECT,90)@15 yT4_uid91_sqrtPolynomialEvaluator_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q; yT4_uid91_sqrtPolynomialEvaluator_b <= yT4_uid91_sqrtPolynomialEvaluator_in(44 downto 5); --xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,117)@15 xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b(12 downto 0); xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in(12 downto 0); --GND(CONSTANT,0) GND_q <= "0"; --pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,120)@15 pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7(REG,176)@15 reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,116)@15 yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q(14 downto 0); yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b <= yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in(14 downto 0); --spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,119)@15 spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q <= GND_q & yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b; --pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,121)@15 pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q <= spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q & STD_LOGIC_VECTOR((1 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6(REG,175)@15 reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,115)@15 xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b; xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 22); --reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4(REG,174)@15 reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma(CHAINMULTADD,140)@16 multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0),19)); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1),19)); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0) <= RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0),38) + RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1),38); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a <= (others => (others => '0')); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c <= (others => (others => '0')); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q),18); multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q),18); IF (en = "1") THEN multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0); END IF; END IF; END PROCESS; multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_delay : dspba_delay GENERIC MAP (width => 37, depth => 1) PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q, clk => clk, aclr => areset); --multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,123)@19 multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q; multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in(36 downto 2); --highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,125)@19 highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b; highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b <= highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in(34 downto 6); --yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,113)@15 yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q; yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 15); --reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1(REG,179)@15 reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,112)@15 xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b; xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 13); --reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0(REG,178)@15 reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator(MULT,114)@16 topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a),28)) * SIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= (others => '0'); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= (others => '0'); topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr,54)); END IF; END IF; END PROCESS; topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator(ADD,126)@19 sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q(53)) & topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b(28)) & highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b)); sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o(54 downto 0); --lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,124)@19 lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b(5 downto 0); lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b <= lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in(5 downto 0); --add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,127)@19 add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q & lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b; --R_uid129_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,128)@19 R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in <= add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q(59 downto 0); R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in(59 downto 17); --reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1(REG,181)@19 reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= "0000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,511) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,507) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01100"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,508) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b else "0"; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,509) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,512) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,513) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,503) -- every=1, low=0, high=12, step=1, init=1 ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 11 THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1'; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 12; ELSE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4)); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,504) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,505) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q) BEGIN CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q; WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,502) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 13, width_b => 8, widthad_b => 4, numwords_b => 13, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0(REG,157)@15 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC1_uid63_sqrtTableGenerator_lutmem(DUALMEM,135)@16 memoryC1_uid63_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid63_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid63_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q; memoryC1_uid63_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 9, widthad_a => 8, numwords_a => 256, width_b => 9, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC1_uid63_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid63_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid63_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid63_sqrtTableGenerator_lutmem_iq, address_a => memoryC1_uid63_sqrtTableGenerator_lutmem_aa, data_a => memoryC1_uid63_sqrtTableGenerator_lutmem_ia ); memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC1_uid63_sqrtTableGenerator_lutmem_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_iq(8 downto 0); --reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1(REG,160)@18 reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= "000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --memoryC1_uid62_sqrtTableGenerator_lutmem(DUALMEM,134)@16 memoryC1_uid62_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid62_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid62_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q; memoryC1_uid62_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC1_uid62_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid62_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid62_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid62_sqrtTableGenerator_lutmem_iq, address_a => memoryC1_uid62_sqrtTableGenerator_lutmem_aa, data_a => memoryC1_uid62_sqrtTableGenerator_lutmem_ia ); memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC1_uid62_sqrtTableGenerator_lutmem_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0(REG,159)@18 reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --os_uid64_sqrtTableGenerator(BITJOIN,63)@19 os_uid64_sqrtTableGenerator_q <= reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q & reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q; --rndBit_uid93_sqrtPolynomialEvaluator(CONSTANT,92) rndBit_uid93_sqrtPolynomialEvaluator_q <= "01"; --cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator(BITJOIN,93)@19 cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q <= os_uid64_sqrtTableGenerator_q & rndBit_uid93_sqrtPolynomialEvaluator_q; --reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0(REG,180)@19 reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ts4_uid95_sqrtPolynomialEvaluator(ADD,94)@20 ts4_uid95_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((51 downto 51 => reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q(50)) & reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q); ts4_uid95_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((51 downto 43 => reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q(42)) & reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q); ts4_uid95_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid95_sqrtPolynomialEvaluator_a) + SIGNED(ts4_uid95_sqrtPolynomialEvaluator_b)); ts4_uid95_sqrtPolynomialEvaluator_q <= ts4_uid95_sqrtPolynomialEvaluator_o(51 downto 0); --s4_uid96_sqrtPolynomialEvaluator(BITSELECT,95)@20 s4_uid96_sqrtPolynomialEvaluator_in <= ts4_uid95_sqrtPolynomialEvaluator_q; s4_uid96_sqrtPolynomialEvaluator_b <= s4_uid96_sqrtPolynomialEvaluator_in(51 downto 1); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1(BITSELECT,144)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in <= STD_LOGIC_VECTOR((53 downto 51 => s4_uid96_sqrtPolynomialEvaluator_b(50)) & s4_uid96_sqrtPolynomialEvaluator_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in(53 downto 27); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1(REG,187)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor(LOGICAL,498) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top(CONSTANT,494) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q <= "01110"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp(LOGICAL,495) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b else "0"; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg(REG,496) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena(REG,499) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd(LOGICAL,500) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt(COUNTER,490) -- every=1, low=0, high=14, step=1, init=1 ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i = 13 THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '1'; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i - 14; ELSE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i,4)); --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg(REG,491) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux(MUX,492) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s <= en; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q) BEGIN CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s IS WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q; WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q; WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem(DUALMEM,489) ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 15, width_b => 45, widthad_b => 4, numwords_b => 15, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq, address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa, data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia ); ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 <= areset; ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq(44 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1(BITSELECT,142)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in <= STD_LOGIC_VECTOR("000000000" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in(53 downto 27); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0(REG,184)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1(MULT,148)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr,54)); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1; END IF; END IF; END PROCESS; --ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a(DELAY,349)@24 ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a : dspba_delay GENERIC MAP ( width => 54, depth => 2 ) PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q, ena => en(0), clk => clk, aclr => areset ); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2(BITSHIFT,152)@26 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q & "000000000000000000000000000000000000000000000000000000"; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int(107 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0(BITSELECT,141)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q(26 downto 0); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in(26 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0(REG,182)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1(MULT,147)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr,54)); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0(BITSELECT,143)@20 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in <= s4_uid96_sqrtPolynomialEvaluator_b(26 downto 0); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in(26 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1(REG,183)@20 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0(MULT,146)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0(ADD,149)@24 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR('0' & "00" & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR((56 downto 54 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q(53)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b)); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o(55 downto 0); --ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a(DELAY,348)@24 ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a : dspba_delay GENERIC MAP ( width => 56, depth => 1 ) PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q, ena => en(0), clk => clk, aclr => areset ); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1(BITSHIFT,151)@25 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q & "000000000000000000000000000"; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int(82 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0(MULT,145)@21 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= (others => '0'); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr); END IF; END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0(BITSHIFT,150)@24 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int(53 downto 0); --reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0(REG,188)@24 reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q; END IF; END IF; END PROCESS; --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0(ADD,153)@25 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q(82)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b)); END IF; END PROCESS; prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o(83 downto 0); --prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0(ADD,154)@26 prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a <= STD_LOGIC_VECTOR((108 downto 84 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q(83)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b <= STD_LOGIC_VECTOR((108 downto 108 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q(107)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b)); prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o(108 downto 0); --prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator(BITSELECT,130)@26 prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q(95 downto 0); prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in(95 downto 44); --highBBits_uid100_sqrtPolynomialEvaluator(BITSELECT,99)@26 highBBits_uid100_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b; highBBits_uid100_sqrtPolynomialEvaluator_b <= highBBits_uid100_sqrtPolynomialEvaluator_in(51 downto 2); --reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1(REG,196)@26 reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= highBBits_uid100_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor(LOGICAL,472) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,468) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q <= "010011"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,469) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b else "0"; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg(REG,470) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena(REG,473) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,474) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,464) -- every=1, low=0, high=19, step=1, init=1 ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 18 THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 19; ELSE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,5)); --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,465) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,466) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q) BEGIN CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,463) ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 5, numwords_a => 20, width_b => 8, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq, address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa, data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia ); ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset; ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0); --memoryC0_uid60_sqrtTableGenerator_lutmem(DUALMEM,133)@23 memoryC0_uid60_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid60_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid60_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q; memoryC0_uid60_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 17, widthad_a => 8, numwords_a => 256, width_b => 17, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC0_uid60_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid60_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid60_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid60_sqrtTableGenerator_lutmem_iq, address_a => memoryC0_uid60_sqrtTableGenerator_lutmem_aa, data_a => memoryC0_uid60_sqrtTableGenerator_lutmem_ia ); memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC0_uid60_sqrtTableGenerator_lutmem_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_iq(16 downto 0); --reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1(REG,194)@25 reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,550) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,551) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,552) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,541) ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 5, numwords_a => 20, width_b => 8, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0(REG,191)@22 reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC0_uid59_sqrtTableGenerator_lutmem(DUALMEM,132)@23 memoryC0_uid59_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid59_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid59_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q; memoryC0_uid59_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 256, width_b => 40, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_sqrt_double_s5_memoryC0_uid59_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid59_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid59_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid59_sqrtTableGenerator_lutmem_iq, address_a => memoryC0_uid59_sqrtTableGenerator_lutmem_aa, data_a => memoryC0_uid59_sqrtTableGenerator_lutmem_ia ); memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC0_uid59_sqrtTableGenerator_lutmem_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_iq(39 downto 0); --reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0(REG,193)@25 reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --os_uid61_sqrtTableGenerator(BITJOIN,60)@26 os_uid61_sqrtTableGenerator_q <= reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q & reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q; --reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0(REG,195)@26 reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= os_uid61_sqrtTableGenerator_q; END IF; END IF; END PROCESS; --sumAHighB_uid101_sqrtPolynomialEvaluator(ADD,100)@27 sumAHighB_uid101_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((57 downto 57 => reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q(56)) & reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q); sumAHighB_uid101_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((57 downto 50 => reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q(49)) & reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q); sumAHighB_uid101_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_b)); sumAHighB_uid101_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_o(57 downto 0); --lowRangeB_uid99_sqrtPolynomialEvaluator(BITSELECT,98)@26 lowRangeB_uid99_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b(1 downto 0); lowRangeB_uid99_sqrtPolynomialEvaluator_b <= lowRangeB_uid99_sqrtPolynomialEvaluator_in(1 downto 0); --reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0(REG,197)@26 reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= lowRangeB_uid99_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --s5_uid99_uid102_sqrtPolynomialEvaluator(BITJOIN,101)@27 s5_uid99_uid102_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_q & reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q; --fracR_uid39_fpSqrtTest(BITSELECT,38)@27 fracR_uid39_fpSqrtTest_in <= s5_uid99_uid102_sqrtPolynomialEvaluator_q(56 downto 0); fracR_uid39_fpSqrtTest_b <= fracR_uid39_fpSqrtTest_in(56 downto 5); --reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3(REG,198)@27 reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= "0000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= fracR_uid39_fpSqrtTest_b; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor(LOGICAL,409) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q <= not (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a or ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena(REG,410) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q = "1") THEN ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd(LOGICAL,411) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b <= en; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a and ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b; --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg(DELAY,399) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => fracSel_uid47_fpSqrtTest_q, xout => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem(DUALMEM,400) ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 2, widthad_a => 5, numwords_a => 24, width_b => 2, widthad_b => 5, numwords_b => 24, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq, address_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa, data_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia ); ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 <= areset; ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq(1 downto 0); --fracRPostExc_uid55_fpSqrtTest(MUX,54)@28 fracRPostExc_uid55_fpSqrtTest_s <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q; fracRPostExc_uid55_fpSqrtTest: PROCESS (fracRPostExc_uid55_fpSqrtTest_s, en, cstAllZWF_uid10_fpSqrtTest_q, reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q, cstAllZWF_uid10_fpSqrtTest_q, fracNaN_uid52_fpSqrtTest_q) BEGIN CASE fracRPostExc_uid55_fpSqrtTest_s IS WHEN "00" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q; WHEN "01" => fracRPostExc_uid55_fpSqrtTest_q <= reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q; WHEN "10" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q; WHEN "11" => fracRPostExc_uid55_fpSqrtTest_q <= fracNaN_uid52_fpSqrtTest_q; WHEN OTHERS => fracRPostExc_uid55_fpSqrtTest_q <= (others => '0'); END CASE; END PROCESS; --RSqrt_uid57_fpSqrtTest(BITJOIN,56)@28 RSqrt_uid57_fpSqrtTest_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q & ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q & fracRPostExc_uid55_fpSqrtTest_q; --xOut(GPOUT,4)@28 q <= RSqrt_uid57_fpSqrtTest_q; end normal;
--Módulo para definir instrução armazenada em determinado endereço de MI. A instrução irá seguir para display 7 segmentos library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity dec_mi is generic(N: integer := 7; M: integer := 32); port( clk : in std_logic; SW : in STD_LOGIC_VECTOR(N-1 downto 0); HEX0 : out STD_LOGIC_VECTOR(6 downto 0); HEX1 : out STD_LOGIC_VECTOR(6 downto 0); HEX2 : out STD_LOGIC_VECTOR(6 downto 0); HEX3 : out STD_LOGIC_VECTOR(6 downto 0); HEX4 : out STD_LOGIC_VECTOR(6 downto 0); HEX5 : out STD_LOGIC_VECTOR(6 downto 0); HEX6 : out STD_LOGIC_VECTOR(6 downto 0); HEX7 : out STD_LOGIC_VECTOR(6 downto 0) ); end; architecture dec_mi_arch of dec_mi is -- signals signal dout : STD_LOGIC_VECTOR(31 DOWNTO 0); begin i1 : entity work.mi generic map(N => N, M => M) port map ( address => SW, clk => clk, instruction => dout ); i2 : entity work.seven_seg_decoder port map ( data => dout(3 downto 0), segments => HEX0 ); i3 : entity work.seven_seg_decoder port map ( data => dout(7 downto 4), segments => HEX1 ); i4 : entity work.seven_seg_decoder port map ( data => dout(11 downto 8), segments => HEX2 ); i5 : entity work.seven_seg_decoder port map ( data => dout(15 downto 12), segments => HEX3 ); i6 : entity work.seven_seg_decoder port map ( data => dout(19 downto 16), segments => HEX4 ); i7 : entity work.seven_seg_decoder port map ( data => dout(23 downto 20), segments => HEX5 ); i8 : entity work.seven_seg_decoder port map ( data => dout(27 downto 24), segments => HEX6 ); i9 : entity work.seven_seg_decoder port map ( data => dout(31 downto 28), segments => HEX7 ); end;
--Módulo para definir instrução armazenada em determinado endereço de MI. A instrução irá seguir para display 7 segmentos library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity dec_mi is generic(N: integer := 7; M: integer := 32); port( clk : in std_logic; SW : in STD_LOGIC_VECTOR(N-1 downto 0); HEX0 : out STD_LOGIC_VECTOR(6 downto 0); HEX1 : out STD_LOGIC_VECTOR(6 downto 0); HEX2 : out STD_LOGIC_VECTOR(6 downto 0); HEX3 : out STD_LOGIC_VECTOR(6 downto 0); HEX4 : out STD_LOGIC_VECTOR(6 downto 0); HEX5 : out STD_LOGIC_VECTOR(6 downto 0); HEX6 : out STD_LOGIC_VECTOR(6 downto 0); HEX7 : out STD_LOGIC_VECTOR(6 downto 0) ); end; architecture dec_mi_arch of dec_mi is -- signals signal dout : STD_LOGIC_VECTOR(31 DOWNTO 0); begin i1 : entity work.mi generic map(N => N, M => M) port map ( address => SW, clk => clk, instruction => dout ); i2 : entity work.seven_seg_decoder port map ( data => dout(3 downto 0), segments => HEX0 ); i3 : entity work.seven_seg_decoder port map ( data => dout(7 downto 4), segments => HEX1 ); i4 : entity work.seven_seg_decoder port map ( data => dout(11 downto 8), segments => HEX2 ); i5 : entity work.seven_seg_decoder port map ( data => dout(15 downto 12), segments => HEX3 ); i6 : entity work.seven_seg_decoder port map ( data => dout(19 downto 16), segments => HEX4 ); i7 : entity work.seven_seg_decoder port map ( data => dout(23 downto 20), segments => HEX5 ); i8 : entity work.seven_seg_decoder port map ( data => dout(27 downto 24), segments => HEX6 ); i9 : entity work.seven_seg_decoder port map ( data => dout(31 downto 28), segments => HEX7 ); end;
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015 --Date : Thu Mar 10 15:45:23 2016 --Host : minmi running 64-bit elementary OS Freya --Command : generate_target system.bd --Design : system --Purpose : IP block netlist ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system is port ( DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_cas_n : inout STD_LOGIC; DDR_ck_n : inout STD_LOGIC; DDR_ck_p : inout STD_LOGIC; DDR_cke : inout STD_LOGIC; DDR_cs_n : inout STD_LOGIC; DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_odt : inout STD_LOGIC; DDR_ras_n : inout STD_LOGIC; DDR_reset_n : inout STD_LOGIC; DDR_we_n : inout STD_LOGIC; FIXED_IO_ddr_vrn : inout STD_LOGIC; FIXED_IO_ddr_vrp : inout STD_LOGIC; FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); FIXED_IO_ps_clk : inout STD_LOGIC; FIXED_IO_ps_porb : inout STD_LOGIC; FIXED_IO_ps_srstb : inout STD_LOGIC; hdmi_cec : in STD_LOGIC; hdmi_hpd : in STD_LOGIC; hdmi_out_en : out STD_LOGIC; sw0 : in STD_LOGIC; sw1 : in STD_LOGIC; sw2 : in STD_LOGIC; tmds : out STD_LOGIC_VECTOR ( 3 downto 0 ); tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 ) ); attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of system : entity is "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=9,numReposBlks=9,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,da_ps7_cnt=1,synth_mode=Global}"; attribute HW_HANDOFF : string; attribute HW_HANDOFF of system : entity is "system.hwdef"; end system; architecture STRUCTURE of system is component system_vga_color_test_0_0 is port ( clk_25 : in STD_LOGIC; xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 ); yaddr : in STD_LOGIC_VECTOR ( 9 downto 0 ); rgb : out STD_LOGIC_VECTOR ( 23 downto 0 ) ); end component system_vga_color_test_0_0; component system_vga_sync_0_0 is port ( clk_25 : in STD_LOGIC; rst : in STD_LOGIC; active : out STD_LOGIC; hsync : out STD_LOGIC; vsync : out STD_LOGIC; xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 ); yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 ) ); end component system_vga_sync_0_0; component system_zybo_hdmi_0_0 is port ( clk_125 : in STD_LOGIC; clk_25 : in STD_LOGIC; hsync : in STD_LOGIC; vsync : in STD_LOGIC; active : in STD_LOGIC; rgb : in STD_LOGIC_VECTOR ( 23 downto 0 ); tmds : out STD_LOGIC_VECTOR ( 3 downto 0 ); tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 ); hdmi_cec : in STD_LOGIC; hdmi_hpd : in STD_LOGIC; hdmi_out_en : out STD_LOGIC ); end component system_zybo_hdmi_0_0; component system_xlconstant_0_0 is port ( dout : out STD_LOGIC_VECTOR ( 0 to 0 ) ); end component system_xlconstant_0_0; component system_clk_wiz_0_0 is port ( clk_in1 : in STD_LOGIC; clk_out1 : out STD_LOGIC; resetn : in STD_LOGIC; locked : out STD_LOGIC ); end component system_clk_wiz_0_0; component system_processing_system7_0_0 is port ( SDIO0_WP : in STD_LOGIC; TTC0_WAVE0_OUT : out STD_LOGIC; TTC0_WAVE1_OUT : out STD_LOGIC; TTC0_WAVE2_OUT : out STD_LOGIC; USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); FCLK_CLK0 : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); end component system_processing_system7_0_0; component system_vga_gaussian_blur_0_0 is port ( en : in STD_LOGIC; clk_25 : in STD_LOGIC; active_in : in STD_LOGIC; hsync_in : in STD_LOGIC; vsync_in : in STD_LOGIC; xaddr_in : in STD_LOGIC_VECTOR ( 9 downto 0 ); yaddr_in : in STD_LOGIC_VECTOR ( 9 downto 0 ); rgb_in : in STD_LOGIC_VECTOR ( 23 downto 0 ); active_out : out STD_LOGIC; hsync_out : out STD_LOGIC; vsync_out : out STD_LOGIC; xaddr_out : out STD_LOGIC_VECTOR ( 9 downto 0 ); yaddr_out : out STD_LOGIC_VECTOR ( 9 downto 0 ); rgb_out : out STD_LOGIC_VECTOR ( 23 downto 0 ) ); end component system_vga_gaussian_blur_0_0; component system_vga_gaussian_blur_1_0 is port ( en : in STD_LOGIC; clk_25 : in STD_LOGIC; active_in : in STD_LOGIC; hsync_in : in STD_LOGIC; vsync_in : in STD_LOGIC; xaddr_in : in STD_LOGIC_VECTOR ( 9 downto 0 ); yaddr_in : in STD_LOGIC_VECTOR ( 9 downto 0 ); rgb_in : in STD_LOGIC_VECTOR ( 23 downto 0 ); active_out : out STD_LOGIC; hsync_out : out STD_LOGIC; vsync_out : out STD_LOGIC; xaddr_out : out STD_LOGIC_VECTOR ( 9 downto 0 ); yaddr_out : out STD_LOGIC_VECTOR ( 9 downto 0 ); rgb_out : out STD_LOGIC_VECTOR ( 23 downto 0 ) ); end component system_vga_gaussian_blur_1_0; component system_vga_gaussian_blur_2_0 is port ( en : in STD_LOGIC; clk_25 : in STD_LOGIC; active_in : in STD_LOGIC; hsync_in : in STD_LOGIC; vsync_in : in STD_LOGIC; xaddr_in : in STD_LOGIC_VECTOR ( 9 downto 0 ); yaddr_in : in STD_LOGIC_VECTOR ( 9 downto 0 ); rgb_in : in STD_LOGIC_VECTOR ( 23 downto 0 ); active_out : out STD_LOGIC; hsync_out : out STD_LOGIC; vsync_out : out STD_LOGIC; xaddr_out : out STD_LOGIC_VECTOR ( 9 downto 0 ); yaddr_out : out STD_LOGIC_VECTOR ( 9 downto 0 ); rgb_out : out STD_LOGIC_VECTOR ( 23 downto 0 ) ); end component system_vga_gaussian_blur_2_0; signal GND_dout : STD_LOGIC_VECTOR ( 0 to 0 ); signal Net : STD_LOGIC; signal en_1 : STD_LOGIC; signal en_1_1 : STD_LOGIC; signal en_2 : STD_LOGIC; signal hdmi_cec_1 : STD_LOGIC; signal hdmi_hpd_1 : STD_LOGIC; signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 ); signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 ); signal processing_system7_0_DDR_CAS_N : STD_LOGIC; signal processing_system7_0_DDR_CKE : STD_LOGIC; signal processing_system7_0_DDR_CK_N : STD_LOGIC; signal processing_system7_0_DDR_CK_P : STD_LOGIC; signal processing_system7_0_DDR_CS_N : STD_LOGIC; signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 ); signal processing_system7_0_DDR_ODT : STD_LOGIC; signal processing_system7_0_DDR_RAS_N : STD_LOGIC; signal processing_system7_0_DDR_RESET_N : STD_LOGIC; signal processing_system7_0_DDR_WE_N : STD_LOGIC; signal processing_system7_0_FCLK_CLK0 : STD_LOGIC; signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC; signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC; signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC; signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 ); signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC; signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC; signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC; signal vga_color_test_0_rgb : STD_LOGIC_VECTOR ( 23 downto 0 ); signal vga_gaussian_blur_0_active_out : STD_LOGIC; signal vga_gaussian_blur_0_hsync_out : STD_LOGIC; signal vga_gaussian_blur_0_rgb_out : STD_LOGIC_VECTOR ( 23 downto 0 ); signal vga_gaussian_blur_0_vsync_out : STD_LOGIC; signal vga_gaussian_blur_0_xaddr_out : STD_LOGIC_VECTOR ( 9 downto 0 ); signal vga_gaussian_blur_0_yaddr_out : STD_LOGIC_VECTOR ( 9 downto 0 ); signal vga_gaussian_blur_1_active_out : STD_LOGIC; signal vga_gaussian_blur_1_hsync_out : STD_LOGIC; signal vga_gaussian_blur_1_rgb_out : STD_LOGIC_VECTOR ( 23 downto 0 ); signal vga_gaussian_blur_1_vsync_out : STD_LOGIC; signal vga_gaussian_blur_1_xaddr_out : STD_LOGIC_VECTOR ( 9 downto 0 ); signal vga_gaussian_blur_1_yaddr_out : STD_LOGIC_VECTOR ( 9 downto 0 ); signal vga_gaussian_blur_2_active_out : STD_LOGIC; signal vga_gaussian_blur_2_hsync_out : STD_LOGIC; signal vga_gaussian_blur_2_rgb_out : STD_LOGIC_VECTOR ( 23 downto 0 ); signal vga_gaussian_blur_2_vsync_out : STD_LOGIC; signal vga_sync_0_active : STD_LOGIC; signal vga_sync_0_hsync : STD_LOGIC; signal vga_sync_0_vsync : STD_LOGIC; signal vga_sync_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 ); signal vga_sync_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 ); signal zybo_hdmi_0_hdmi_out_en : STD_LOGIC; signal zybo_hdmi_0_tmds : STD_LOGIC_VECTOR ( 3 downto 0 ); signal zybo_hdmi_0_tmdsb : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_clk_wiz_0_locked_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC; signal NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_vga_gaussian_blur_2_xaddr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 ); signal NLW_vga_gaussian_blur_2_yaddr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 ); begin en_1 <= sw0; en_1_1 <= sw2; en_2 <= sw1; hdmi_cec_1 <= hdmi_cec; hdmi_hpd_1 <= hdmi_hpd; hdmi_out_en <= zybo_hdmi_0_hdmi_out_en; tmds(3 downto 0) <= zybo_hdmi_0_tmds(3 downto 0); tmdsb(3 downto 0) <= zybo_hdmi_0_tmdsb(3 downto 0); GND: component system_xlconstant_0_0 port map ( dout(0) => GND_dout(0) ); clk_wiz_0: component system_clk_wiz_0_0 port map ( clk_in1 => processing_system7_0_FCLK_CLK0, clk_out1 => Net, locked => NLW_clk_wiz_0_locked_UNCONNECTED, resetn => processing_system7_0_FCLK_RESET0_N ); processing_system7_0: component system_processing_system7_0_0 port map ( DDR_Addr(14 downto 0) => DDR_addr(14 downto 0), DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0), DDR_CAS_n => DDR_cas_n, DDR_CKE => DDR_cke, DDR_CS_n => DDR_cs_n, DDR_Clk => DDR_ck_p, DDR_Clk_n => DDR_ck_n, DDR_DM(3 downto 0) => DDR_dm(3 downto 0), DDR_DQ(31 downto 0) => DDR_dq(31 downto 0), DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0), DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0), DDR_DRSTB => DDR_reset_n, DDR_ODT => DDR_odt, DDR_RAS_n => DDR_ras_n, DDR_VRN => FIXED_IO_ddr_vrn, DDR_VRP => FIXED_IO_ddr_vrp, DDR_WEB => DDR_we_n, FCLK_CLK0 => processing_system7_0_FCLK_CLK0, FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N, MIO(53 downto 0) => FIXED_IO_mio(53 downto 0), M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0, M_AXI_GP0_ARADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED(31 downto 0), M_AXI_GP0_ARBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED(1 downto 0), M_AXI_GP0_ARCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED(3 downto 0), M_AXI_GP0_ARID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED(11 downto 0), M_AXI_GP0_ARLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED(3 downto 0), M_AXI_GP0_ARLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED(1 downto 0), M_AXI_GP0_ARPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED(2 downto 0), M_AXI_GP0_ARQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED(3 downto 0), M_AXI_GP0_ARREADY => '0', M_AXI_GP0_ARSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED(2 downto 0), M_AXI_GP0_ARVALID => NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED, M_AXI_GP0_AWADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED(31 downto 0), M_AXI_GP0_AWBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED(1 downto 0), M_AXI_GP0_AWCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED(3 downto 0), M_AXI_GP0_AWID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED(11 downto 0), M_AXI_GP0_AWLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED(3 downto 0), M_AXI_GP0_AWLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED(1 downto 0), M_AXI_GP0_AWPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED(2 downto 0), M_AXI_GP0_AWQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED(3 downto 0), M_AXI_GP0_AWREADY => '0', M_AXI_GP0_AWSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED(2 downto 0), M_AXI_GP0_AWVALID => NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED, M_AXI_GP0_BID(11 downto 0) => B"000000000000", M_AXI_GP0_BREADY => NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED, M_AXI_GP0_BRESP(1 downto 0) => B"00", M_AXI_GP0_BVALID => '0', M_AXI_GP0_RDATA(31 downto 0) => B"00000000000000000000000000000000", M_AXI_GP0_RID(11 downto 0) => B"000000000000", M_AXI_GP0_RLAST => '0', M_AXI_GP0_RREADY => NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED, M_AXI_GP0_RRESP(1 downto 0) => B"00", M_AXI_GP0_RVALID => '0', M_AXI_GP0_WDATA(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED(31 downto 0), M_AXI_GP0_WID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED(11 downto 0), M_AXI_GP0_WLAST => NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED, M_AXI_GP0_WREADY => '0', M_AXI_GP0_WSTRB(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED(3 downto 0), M_AXI_GP0_WVALID => NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED, PS_CLK => FIXED_IO_ps_clk, PS_PORB => FIXED_IO_ps_porb, PS_SRSTB => FIXED_IO_ps_srstb, SDIO0_WP => '0', TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED, TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED, TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED, USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0), USB0_VBUS_PWRFAULT => '0', USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED ); vga_color_test_0: component system_vga_color_test_0_0 port map ( clk_25 => Net, rgb(23 downto 0) => vga_color_test_0_rgb(23 downto 0), xaddr(9 downto 0) => vga_sync_0_xaddr(9 downto 0), yaddr(9 downto 0) => vga_sync_0_yaddr(9 downto 0) ); vga_gaussian_blur_0: component system_vga_gaussian_blur_0_0 port map ( active_in => vga_sync_0_active, active_out => vga_gaussian_blur_0_active_out, clk_25 => Net, en => en_1, hsync_in => vga_sync_0_hsync, hsync_out => vga_gaussian_blur_0_hsync_out, rgb_in(23 downto 0) => vga_color_test_0_rgb(23 downto 0), rgb_out(23 downto 0) => vga_gaussian_blur_0_rgb_out(23 downto 0), vsync_in => vga_sync_0_vsync, vsync_out => vga_gaussian_blur_0_vsync_out, xaddr_in(9 downto 0) => vga_sync_0_xaddr(9 downto 0), xaddr_out(9 downto 0) => vga_gaussian_blur_0_xaddr_out(9 downto 0), yaddr_in(9 downto 0) => vga_sync_0_yaddr(9 downto 0), yaddr_out(9 downto 0) => vga_gaussian_blur_0_yaddr_out(9 downto 0) ); vga_gaussian_blur_1: component system_vga_gaussian_blur_1_0 port map ( active_in => vga_gaussian_blur_0_active_out, active_out => vga_gaussian_blur_1_active_out, clk_25 => Net, en => en_2, hsync_in => vga_gaussian_blur_0_hsync_out, hsync_out => vga_gaussian_blur_1_hsync_out, rgb_in(23 downto 0) => vga_gaussian_blur_0_rgb_out(23 downto 0), rgb_out(23 downto 0) => vga_gaussian_blur_1_rgb_out(23 downto 0), vsync_in => vga_gaussian_blur_0_vsync_out, vsync_out => vga_gaussian_blur_1_vsync_out, xaddr_in(9 downto 0) => vga_gaussian_blur_0_xaddr_out(9 downto 0), xaddr_out(9 downto 0) => vga_gaussian_blur_1_xaddr_out(9 downto 0), yaddr_in(9 downto 0) => vga_gaussian_blur_0_yaddr_out(9 downto 0), yaddr_out(9 downto 0) => vga_gaussian_blur_1_yaddr_out(9 downto 0) ); vga_gaussian_blur_2: component system_vga_gaussian_blur_2_0 port map ( active_in => vga_gaussian_blur_1_active_out, active_out => vga_gaussian_blur_2_active_out, clk_25 => Net, en => en_1_1, hsync_in => vga_gaussian_blur_1_hsync_out, hsync_out => vga_gaussian_blur_2_hsync_out, rgb_in(23 downto 0) => vga_gaussian_blur_1_rgb_out(23 downto 0), rgb_out(23 downto 0) => vga_gaussian_blur_2_rgb_out(23 downto 0), vsync_in => vga_gaussian_blur_1_vsync_out, vsync_out => vga_gaussian_blur_2_vsync_out, xaddr_in(9 downto 0) => vga_gaussian_blur_1_xaddr_out(9 downto 0), xaddr_out(9 downto 0) => NLW_vga_gaussian_blur_2_xaddr_out_UNCONNECTED(9 downto 0), yaddr_in(9 downto 0) => vga_gaussian_blur_1_yaddr_out(9 downto 0), yaddr_out(9 downto 0) => NLW_vga_gaussian_blur_2_yaddr_out_UNCONNECTED(9 downto 0) ); vga_sync_0: component system_vga_sync_0_0 port map ( active => vga_sync_0_active, clk_25 => Net, hsync => vga_sync_0_hsync, rst => GND_dout(0), vsync => vga_sync_0_vsync, xaddr(9 downto 0) => vga_sync_0_xaddr(9 downto 0), yaddr(9 downto 0) => vga_sync_0_yaddr(9 downto 0) ); zybo_hdmi_0: component system_zybo_hdmi_0_0 port map ( active => vga_gaussian_blur_2_active_out, clk_125 => processing_system7_0_FCLK_CLK0, clk_25 => Net, hdmi_cec => hdmi_cec_1, hdmi_hpd => hdmi_hpd_1, hdmi_out_en => zybo_hdmi_0_hdmi_out_en, hsync => vga_gaussian_blur_2_hsync_out, rgb(23 downto 0) => vga_gaussian_blur_2_rgb_out(23 downto 0), tmds(3 downto 0) => zybo_hdmi_0_tmds(3 downto 0), tmdsb(3 downto 0) => zybo_hdmi_0_tmdsb(3 downto 0), vsync => vga_gaussian_blur_2_vsync_out ); end STRUCTURE;
-- ------------------------------------------------------------- -- -- Entity Declaration for inst_ec_e -- -- Generated -- by: wig -- on: Mon Mar 22 13:27:43 2004 -- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_ec_e-e.vhd,v 1.1 2004/04/06 10:50:02 wig Exp $ -- $Date: 2004/04/06 10:50:02 $ -- $Log: inst_ec_e-e.vhd,v $ -- Revision 1.1 2004/04/06 10:50:02 wig -- Adding result/mde_tests -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp -- -- Generator: mix_0.pl Version: Revision: 1.26 , wilfried.gaensheimer@micronas.com -- (C) 2003 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/enty -- -- -- Start of Generated Entity inst_ec_e -- entity inst_ec_e is -- Generics: -- No Generated Generics for Entity inst_ec_e -- Generated Port Declaration: port( -- Generated Port for Entity inst_ec_e p_mix_nreset_gi : in std_ulogic; p_mix_nreset_s_gi : in std_ulogic; p_mix_v_select_5_0_gi : in std_ulogic_vector(5 downto 0); tpm_scani : in std_ulogic_vector(12 downto 0); tpm_scano : out std_ulogic_vector(12 downto 0) -- End of Generated Port for Entity inst_ec_e ); end inst_ec_e; -- -- End of Generated Entity inst_ec_e -- -- --!End of Entity/ies -- --------------------------------------------------------------
library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; entity mark1_nov is port( clock: in std_logic; input: in std_logic_vector(4 downto 0); output: out std_logic_vector(15 downto 0) ); end mark1_nov; architecture behaviour of mark1_nov is constant state1: std_logic_vector(3 downto 0) := "0100"; constant state2: std_logic_vector(3 downto 0) := "1000"; constant state3: std_logic_vector(3 downto 0) := "1011"; constant state4: std_logic_vector(3 downto 0) := "1100"; constant state5: std_logic_vector(3 downto 0) := "0001"; constant state6: std_logic_vector(3 downto 0) := "0011"; constant state7: std_logic_vector(3 downto 0) := "0000"; constant state8: std_logic_vector(3 downto 0) := "0010"; constant state9: std_logic_vector(3 downto 0) := "1101"; constant state10: std_logic_vector(3 downto 0) := "1010"; constant state11: std_logic_vector(3 downto 0) := "0111"; constant state12: std_logic_vector(3 downto 0) := "1001"; constant state13: std_logic_vector(3 downto 0) := "0101"; constant state14: std_logic_vector(3 downto 0) := "0110"; constant state0: std_logic_vector(3 downto 0) := "1110"; signal current_state, next_state: std_logic_vector(3 downto 0); begin process(clock) begin if rising_edge(clock) then current_state <= next_state; end if; end process; process(input, current_state) begin next_state <= "----"; output <= "----------------"; if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------"; else case current_state is when state1 => if std_match(input, "1----") then next_state <= state3; output <= "-11---1-00------"; end if; when state2 => if std_match(input, "1----") then next_state <= state0; output <= "-11---1-00------"; end if; when state3 => if std_match(input, "1----") then next_state <= state4; output <= "101---1-01------"; end if; when state4 => if std_match(input, "1-111") then next_state <= state13; output <= "-11---1-00------"; elsif std_match(input, "1-110") then next_state <= state10; output <= "-11---1-00------"; elsif std_match(input, "1-10-") then next_state <= state9; output <= "-11---1-00------"; elsif std_match(input, "1-011") then next_state <= state8; output <= "-11---1-00------"; elsif std_match(input, "1-010") then next_state <= state7; output <= "-11---1-00------"; elsif std_match(input, "1-001") then next_state <= state6; output <= "-11---1-00------"; elsif std_match(input, "1-000") then next_state <= state5; output <= "-11---1-00------"; end if; when state5 => if std_match(input, "1----") then next_state <= state14; output <= "0011--1-00------"; end if; when state6 => if std_match(input, "1----") then next_state <= state14; output <= "00100-0-00000011"; end if; when state7 => if std_match(input, "1----") then next_state <= state14; output <= "001---1100------"; end if; when state8 => if std_match(input, "1----") then next_state <= state14; output <= "010---1-00------"; end if; when state9 => if std_match(input, "1----") then next_state <= state14; output <= "001---1010000101"; end if; when state10 => if std_match(input, "1----") then next_state <= state11; output <= "-11---1-00100000"; end if; when state11 => if std_match(input, "10---") then next_state <= state13; output <= "-11---1-00------"; elsif std_match(input, "11---") then next_state <= state12; output <= "-11---1-00------"; end if; when state12 => if std_match(input, "1----") then next_state <= state13; output <= "-110110-00------"; end if; when state13 => if std_match(input, "1----") then next_state <= state14; output <= "-11---1-00------"; end if; when state14 => if std_match(input, "1----") then next_state <= state3; output <= "-110110-00------"; end if; when state0 => if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------"; end if; when others => next_state <= "----"; output <= "----------------"; end case; end if; end process; end behaviour;
library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; entity mark1_nov is port( clock: in std_logic; input: in std_logic_vector(4 downto 0); output: out std_logic_vector(15 downto 0) ); end mark1_nov; architecture behaviour of mark1_nov is constant state1: std_logic_vector(3 downto 0) := "0100"; constant state2: std_logic_vector(3 downto 0) := "1000"; constant state3: std_logic_vector(3 downto 0) := "1011"; constant state4: std_logic_vector(3 downto 0) := "1100"; constant state5: std_logic_vector(3 downto 0) := "0001"; constant state6: std_logic_vector(3 downto 0) := "0011"; constant state7: std_logic_vector(3 downto 0) := "0000"; constant state8: std_logic_vector(3 downto 0) := "0010"; constant state9: std_logic_vector(3 downto 0) := "1101"; constant state10: std_logic_vector(3 downto 0) := "1010"; constant state11: std_logic_vector(3 downto 0) := "0111"; constant state12: std_logic_vector(3 downto 0) := "1001"; constant state13: std_logic_vector(3 downto 0) := "0101"; constant state14: std_logic_vector(3 downto 0) := "0110"; constant state0: std_logic_vector(3 downto 0) := "1110"; signal current_state, next_state: std_logic_vector(3 downto 0); begin process(clock) begin if rising_edge(clock) then current_state <= next_state; end if; end process; process(input, current_state) begin next_state <= "----"; output <= "----------------"; if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------"; else case current_state is when state1 => if std_match(input, "1----") then next_state <= state3; output <= "-11---1-00------"; end if; when state2 => if std_match(input, "1----") then next_state <= state0; output <= "-11---1-00------"; end if; when state3 => if std_match(input, "1----") then next_state <= state4; output <= "101---1-01------"; end if; when state4 => if std_match(input, "1-111") then next_state <= state13; output <= "-11---1-00------"; elsif std_match(input, "1-110") then next_state <= state10; output <= "-11---1-00------"; elsif std_match(input, "1-10-") then next_state <= state9; output <= "-11---1-00------"; elsif std_match(input, "1-011") then next_state <= state8; output <= "-11---1-00------"; elsif std_match(input, "1-010") then next_state <= state7; output <= "-11---1-00------"; elsif std_match(input, "1-001") then next_state <= state6; output <= "-11---1-00------"; elsif std_match(input, "1-000") then next_state <= state5; output <= "-11---1-00------"; end if; when state5 => if std_match(input, "1----") then next_state <= state14; output <= "0011--1-00------"; end if; when state6 => if std_match(input, "1----") then next_state <= state14; output <= "00100-0-00000011"; end if; when state7 => if std_match(input, "1----") then next_state <= state14; output <= "001---1100------"; end if; when state8 => if std_match(input, "1----") then next_state <= state14; output <= "010---1-00------"; end if; when state9 => if std_match(input, "1----") then next_state <= state14; output <= "001---1010000101"; end if; when state10 => if std_match(input, "1----") then next_state <= state11; output <= "-11---1-00100000"; end if; when state11 => if std_match(input, "10---") then next_state <= state13; output <= "-11---1-00------"; elsif std_match(input, "11---") then next_state <= state12; output <= "-11---1-00------"; end if; when state12 => if std_match(input, "1----") then next_state <= state13; output <= "-110110-00------"; end if; when state13 => if std_match(input, "1----") then next_state <= state14; output <= "-11---1-00------"; end if; when state14 => if std_match(input, "1----") then next_state <= state3; output <= "-110110-00------"; end if; when state0 => if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------"; end if; when others => next_state <= "----"; output <= "----------------"; end case; end if; end process; end behaviour;
-- file: timer_tb.vhd -- -- (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------ -- Clocking wizard demonstration testbench ------------------------------------------------------------------------------ -- This demonstration testbench instantiates the example design for the -- clocking wizard. Input clocks are toggled, which cause the clocking -- network to lock and the counters to increment. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; use ieee.std_logic_textio.all; library std; use std.textio.all; library work; use work.all; entity timer_tb is end timer_tb; architecture test of timer_tb is -- Clock to Q delay of 100 ps constant TCQ : time := 100 ps; -- timescale is 1ps constant ONE_NS : time := 1 ns; -- how many cycles to run constant COUNT_PHASE : integer := 1024 + 1; -- we'll be using the period in many locations constant PER1 : time := 10.0 ns; -- Declare the input clock signals signal CLK_IN1 : std_logic := '1'; -- The high bits of the sampling counters signal COUNT : std_logic_vector(2 downto 1); signal COUNTER_RESET : std_logic := '0'; component timer_exdes generic ( TCQ : in time := 100 ps); port (-- Clock in ports CLK_IN1 : in std_logic; -- Reset that only drives logic in example design COUNTER_RESET : in std_logic; -- High bits of counters driven by clocks COUNT : out std_logic_vector(2 downto 1) ); end component; begin -- Input clock generation -------------------------------------- process begin CLK_IN1 <= not CLK_IN1; wait for (PER1/2); end process; -- Test sequence process begin -- can't probe into hierarchy, wait "some time" for lock wait for (PER120); COUNTER_RESET <= '1'; wait for (PER120); COUNTER_RESET <= '0'; wait for (PER1*COUNT_PHASE); report "Simulation Stopped." severity failure; wait; end process; -- Instantiation of the example design containing the clock -- network and sampling counters ----------------------------------------------------------- dut : timer_exdes generic map ( TCQ => TCQ) port map (-- Clock in ports CLK_IN1 => CLK_IN1, -- Reset for logic in example design COUNTER_RESET => COUNTER_RESET, -- High bits of the counters COUNT => COUNT); end test;
-- Library statements -- LIBRARY ieee; USE ieee.std_logic_1164.all; -- Entity declaration -- entity half_adder is port (a, b : in std_logic; sum, carry_out : out std_logic ); end dataflow_half_adder; -- Architecture -- architecture dataflow of half_adder is begin sum <= a xor b; carry_out <= a and b; end dataflow;
--generated by V2 synthesiser library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ssegDriver is port ( clk : in std_logic; rst : in std_logic; cathode_p : out std_logic_vector(7 downto 0); anode_p : out std_logic_vector(7 downto 0); digit1_p : in std_logic_vector(3 downto 0) := "0000"; digit2_p : in std_logic_vector(3 downto 0) := "0000"; digit3_p : in std_logic_vector(3 downto 0) := "0000"; digit4_p : in std_logic_vector(3 downto 0) := "0000"; digit5_p : in std_logic_vector(3 downto 0) := "0000"; digit6_p : in std_logic_vector(3 downto 0) := "0000"; digit7_p : in std_logic_vector(3 downto 0) := "0000"; digit8_p : in std_logic_vector(3 downto 0) := "0000" ); end ssegDriver; ------------------------------------------------ architecture behavioural of ssegDriver is signal digit_reg : std_logic_vector(31 downto 0); signal anode_reg : std_logic_vector(7 downto 0); signal digitout_reg : std_logic_vector(3 downto 0); signal digit_sel : std_logic_vector(2 downto 0); signal next_sel : std_logic_vector(2 downto 0); begin --Clock and set state machine process (clk, rst) begin if (rst = '1') then digit_reg <= "00000000000000000000000000000000"; digit_sel <= "000"; next_sel <= "000"; digitout_reg <= "0000"; anode_reg <= "11111111"; elsif (clk'event and clk = '1') then --latch digits into register on clock edge digit_reg(3 downto 0) <= digit1_p; digit_reg(7 downto 4) <= digit2_p; digit_reg(11 downto 8) <= digit3_p; digit_reg(15 downto 12) <= digit4_p; digit_reg(19 downto 16) <= digit5_p; digit_reg(23 downto 20) <= digit6_p; digit_reg(27 downto 24) <= digit7_p; digit_reg(31 downto 28) <= digit8_p; digit_sel <= next_sel; case digit_sel is when "000" => anode_reg <= "11111110"; digitout_reg <= digit_reg(3 downto 0); next_sel <= "001"; when "001" => anode_reg <= "11111101"; digitout_reg <= digit_reg(7 downto 4); digit_sel <= "010"; when "010" => anode_reg <= "11111011"; digitout_reg <= digit_reg(11 downto 8); next_sel <= "011"; when "011" => anode_reg <= "11110111"; digitout_reg <= digit_reg(15 downto 12); next_sel <= "100"; when "100" => anode_reg <= "11101111"; digitout_reg <= digit_reg(19 downto 16); next_sel <= "101"; when "101" => anode_reg <= "11011111"; digitout_reg <= digit_reg(23 downto 20); next_sel <= "110"; when "110" => anode_reg <= "10111111"; digitout_reg <= digit_reg(27 downto 24); next_sel <= "111"; when "111" => anode_reg <= "01111111"; digitout_reg <= digit_reg(31 downto 28); next_sel <= "000"; when others => anode_reg <= "11111111"; digitout_reg <= "0000"; next_sel <= "000"; end case; end if; end process; --Connect the Cathode values with digitout_reg select cathode_p <= "11000000"when "0000", -- 0 "11111001" when "0001", -- 1 "10100100" when "0010", -- 2 "10110000" when "0011", -- 3 "10011001" when "0100", -- 4 "10010010" when "0101", -- 5 "10000010" when "0110", -- 6 "11111000" when "0111", -- 7 "10000000" when "1000", -- 8 "10011000" when "1001", -- 9 "10001000" when "1010", -- A "10000011" when "1011", -- B "11000110" when "1100", -- C "10100001" when "1101", -- D "10000110" when "1110", -- E "10001110" when "1111"; -- F --Connect the Anode values anode_p <= anode_reg; end behavioural;
--generated by V2 synthesiser library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ssegDriver is port ( clk : in std_logic; rst : in std_logic; cathode_p : out std_logic_vector(7 downto 0); anode_p : out std_logic_vector(7 downto 0); digit1_p : in std_logic_vector(3 downto 0) := "0000"; digit2_p : in std_logic_vector(3 downto 0) := "0000"; digit3_p : in std_logic_vector(3 downto 0) := "0000"; digit4_p : in std_logic_vector(3 downto 0) := "0000"; digit5_p : in std_logic_vector(3 downto 0) := "0000"; digit6_p : in std_logic_vector(3 downto 0) := "0000"; digit7_p : in std_logic_vector(3 downto 0) := "0000"; digit8_p : in std_logic_vector(3 downto 0) := "0000" ); end ssegDriver; ------------------------------------------------ architecture behavioural of ssegDriver is signal digit_reg : std_logic_vector(31 downto 0); signal anode_reg : std_logic_vector(7 downto 0); signal digitout_reg : std_logic_vector(3 downto 0); signal digit_sel : std_logic_vector(2 downto 0); signal next_sel : std_logic_vector(2 downto 0); begin --Clock and set state machine process (clk, rst) begin if (rst = '1') then digit_reg <= "00000000000000000000000000000000"; digit_sel <= "000"; next_sel <= "000"; digitout_reg <= "0000"; anode_reg <= "11111111"; elsif (clk'event and clk = '1') then --latch digits into register on clock edge digit_reg(3 downto 0) <= digit1_p; digit_reg(7 downto 4) <= digit2_p; digit_reg(11 downto 8) <= digit3_p; digit_reg(15 downto 12) <= digit4_p; digit_reg(19 downto 16) <= digit5_p; digit_reg(23 downto 20) <= digit6_p; digit_reg(27 downto 24) <= digit7_p; digit_reg(31 downto 28) <= digit8_p; digit_sel <= next_sel; case digit_sel is when "000" => anode_reg <= "11111110"; digitout_reg <= digit_reg(3 downto 0); next_sel <= "001"; when "001" => anode_reg <= "11111101"; digitout_reg <= digit_reg(7 downto 4); digit_sel <= "010"; when "010" => anode_reg <= "11111011"; digitout_reg <= digit_reg(11 downto 8); next_sel <= "011"; when "011" => anode_reg <= "11110111"; digitout_reg <= digit_reg(15 downto 12); next_sel <= "100"; when "100" => anode_reg <= "11101111"; digitout_reg <= digit_reg(19 downto 16); next_sel <= "101"; when "101" => anode_reg <= "11011111"; digitout_reg <= digit_reg(23 downto 20); next_sel <= "110"; when "110" => anode_reg <= "10111111"; digitout_reg <= digit_reg(27 downto 24); next_sel <= "111"; when "111" => anode_reg <= "01111111"; digitout_reg <= digit_reg(31 downto 28); next_sel <= "000"; when others => anode_reg <= "11111111"; digitout_reg <= "0000"; next_sel <= "000"; end case; end if; end process; --Connect the Cathode values with digitout_reg select cathode_p <= "11000000"when "0000", -- 0 "11111001" when "0001", -- 1 "10100100" when "0010", -- 2 "10110000" when "0011", -- 3 "10011001" when "0100", -- 4 "10010010" when "0101", -- 5 "10000010" when "0110", -- 6 "11111000" when "0111", -- 7 "10000000" when "1000", -- 8 "10011000" when "1001", -- 9 "10001000" when "1010", -- A "10000011" when "1011", -- B "11000110" when "1100", -- C "10100001" when "1101", -- D "10000110" when "1110", -- E "10001110" when "1111"; -- F --Connect the Anode values anode_p <= anode_reg; end behavioural;
--generated by V2 synthesiser library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ssegDriver is port ( clk : in std_logic; rst : in std_logic; cathode_p : out std_logic_vector(7 downto 0); anode_p : out std_logic_vector(7 downto 0); digit1_p : in std_logic_vector(3 downto 0) := "0000"; digit2_p : in std_logic_vector(3 downto 0) := "0000"; digit3_p : in std_logic_vector(3 downto 0) := "0000"; digit4_p : in std_logic_vector(3 downto 0) := "0000"; digit5_p : in std_logic_vector(3 downto 0) := "0000"; digit6_p : in std_logic_vector(3 downto 0) := "0000"; digit7_p : in std_logic_vector(3 downto 0) := "0000"; digit8_p : in std_logic_vector(3 downto 0) := "0000" ); end ssegDriver; ------------------------------------------------ architecture behavioural of ssegDriver is signal digit_reg : std_logic_vector(31 downto 0); signal anode_reg : std_logic_vector(7 downto 0); signal digitout_reg : std_logic_vector(3 downto 0); signal digit_sel : std_logic_vector(2 downto 0); signal next_sel : std_logic_vector(2 downto 0); begin --Clock and set state machine process (clk, rst) begin if (rst = '1') then digit_reg <= "00000000000000000000000000000000"; digit_sel <= "000"; next_sel <= "000"; digitout_reg <= "0000"; anode_reg <= "11111111"; elsif (clk'event and clk = '1') then --latch digits into register on clock edge digit_reg(3 downto 0) <= digit1_p; digit_reg(7 downto 4) <= digit2_p; digit_reg(11 downto 8) <= digit3_p; digit_reg(15 downto 12) <= digit4_p; digit_reg(19 downto 16) <= digit5_p; digit_reg(23 downto 20) <= digit6_p; digit_reg(27 downto 24) <= digit7_p; digit_reg(31 downto 28) <= digit8_p; digit_sel <= next_sel; case digit_sel is when "000" => anode_reg <= "11111110"; digitout_reg <= digit_reg(3 downto 0); next_sel <= "001"; when "001" => anode_reg <= "11111101"; digitout_reg <= digit_reg(7 downto 4); digit_sel <= "010"; when "010" => anode_reg <= "11111011"; digitout_reg <= digit_reg(11 downto 8); next_sel <= "011"; when "011" => anode_reg <= "11110111"; digitout_reg <= digit_reg(15 downto 12); next_sel <= "100"; when "100" => anode_reg <= "11101111"; digitout_reg <= digit_reg(19 downto 16); next_sel <= "101"; when "101" => anode_reg <= "11011111"; digitout_reg <= digit_reg(23 downto 20); next_sel <= "110"; when "110" => anode_reg <= "10111111"; digitout_reg <= digit_reg(27 downto 24); next_sel <= "111"; when "111" => anode_reg <= "01111111"; digitout_reg <= digit_reg(31 downto 28); next_sel <= "000"; when others => anode_reg <= "11111111"; digitout_reg <= "0000"; next_sel <= "000"; end case; end if; end process; --Connect the Cathode values with digitout_reg select cathode_p <= "11000000"when "0000", -- 0 "11111001" when "0001", -- 1 "10100100" when "0010", -- 2 "10110000" when "0011", -- 3 "10011001" when "0100", -- 4 "10010010" when "0101", -- 5 "10000010" when "0110", -- 6 "11111000" when "0111", -- 7 "10000000" when "1000", -- 8 "10011000" when "1001", -- 9 "10001000" when "1010", -- A "10000011" when "1011", -- B "11000110" when "1100", -- C "10100001" when "1101", -- D "10000110" when "1110", -- E "10001110" when "1111"; -- F --Connect the Anode values anode_p <= anode_reg; end behavioural;
--generated by V2 synthesiser library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ssegDriver is port ( clk : in std_logic; rst : in std_logic; cathode_p : out std_logic_vector(7 downto 0); anode_p : out std_logic_vector(7 downto 0); digit1_p : in std_logic_vector(3 downto 0) := "0000"; digit2_p : in std_logic_vector(3 downto 0) := "0000"; digit3_p : in std_logic_vector(3 downto 0) := "0000"; digit4_p : in std_logic_vector(3 downto 0) := "0000"; digit5_p : in std_logic_vector(3 downto 0) := "0000"; digit6_p : in std_logic_vector(3 downto 0) := "0000"; digit7_p : in std_logic_vector(3 downto 0) := "0000"; digit8_p : in std_logic_vector(3 downto 0) := "0000" ); end ssegDriver; ------------------------------------------------ architecture behavioural of ssegDriver is signal digit_reg : std_logic_vector(31 downto 0); signal anode_reg : std_logic_vector(7 downto 0); signal digitout_reg : std_logic_vector(3 downto 0); signal digit_sel : std_logic_vector(2 downto 0); signal next_sel : std_logic_vector(2 downto 0); begin --Clock and set state machine process (clk, rst) begin if (rst = '1') then digit_reg <= "00000000000000000000000000000000"; digit_sel <= "000"; next_sel <= "000"; digitout_reg <= "0000"; anode_reg <= "11111111"; elsif (clk'event and clk = '1') then --latch digits into register on clock edge digit_reg(3 downto 0) <= digit1_p; digit_reg(7 downto 4) <= digit2_p; digit_reg(11 downto 8) <= digit3_p; digit_reg(15 downto 12) <= digit4_p; digit_reg(19 downto 16) <= digit5_p; digit_reg(23 downto 20) <= digit6_p; digit_reg(27 downto 24) <= digit7_p; digit_reg(31 downto 28) <= digit8_p; digit_sel <= next_sel; case digit_sel is when "000" => anode_reg <= "11111110"; digitout_reg <= digit_reg(3 downto 0); next_sel <= "001"; when "001" => anode_reg <= "11111101"; digitout_reg <= digit_reg(7 downto 4); digit_sel <= "010"; when "010" => anode_reg <= "11111011"; digitout_reg <= digit_reg(11 downto 8); next_sel <= "011"; when "011" => anode_reg <= "11110111"; digitout_reg <= digit_reg(15 downto 12); next_sel <= "100"; when "100" => anode_reg <= "11101111"; digitout_reg <= digit_reg(19 downto 16); next_sel <= "101"; when "101" => anode_reg <= "11011111"; digitout_reg <= digit_reg(23 downto 20); next_sel <= "110"; when "110" => anode_reg <= "10111111"; digitout_reg <= digit_reg(27 downto 24); next_sel <= "111"; when "111" => anode_reg <= "01111111"; digitout_reg <= digit_reg(31 downto 28); next_sel <= "000"; when others => anode_reg <= "11111111"; digitout_reg <= "0000"; next_sel <= "000"; end case; end if; end process; --Connect the Cathode values with digitout_reg select cathode_p <= "11000000"when "0000", -- 0 "11111001" when "0001", -- 1 "10100100" when "0010", -- 2 "10110000" when "0011", -- 3 "10011001" when "0100", -- 4 "10010010" when "0101", -- 5 "10000010" when "0110", -- 6 "11111000" when "0111", -- 7 "10000000" when "1000", -- 8 "10011000" when "1001", -- 9 "10001000" when "1010", -- A "10000011" when "1011", -- B "11000110" when "1100", -- C "10100001" when "1101", -- D "10000110" when "1110", -- E "10001110" when "1111"; -- F --Connect the Anode values anode_p <= anode_reg; end behavioural;
------------------------------------------------------------------------------ -- Copyright (C) 2007 Jonathon W. Donaldson -- jwdonal a t opencores DOT org -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -- ------------------------------------------------------------------------------ -- -- $Id: vsyncx_control.vhd,v 1.1 2008-11-07 00:48:12 jwdonal Exp $ -- -- Description: -- This file controls VSYNCx. VSYNCx is dependent upon the number of HSYNCx -- activations (i.e. the numbers of lines) that have passed. The really cool -- thing about the VSYNCx control state machine is that it is _EXACTLY_ the -- same as the HSYNCx control state machine expect that instead of have the -- counter process counting CLK_LCD cycles we have counting HSYNCx cycles! -- It's really that simple! -- -- VSYNCx signifies the start of a frame. HSYNCx must pulse exactly 7 times -- (i.e. 7 lines) after (minimum of 0 ns after - TVh) VSYNCx pulse occurs -- before sending data to the LCD. You can consider these 7 lines as blank -- lines that "live" above the physical top of the screen. After 7 HSYNCx -- pulses have passed we can then start with line 1 and go to line 240 for a -- total of 7 + 240 lines = 247 lines (or HSYNCx pulses) for every complete -- image or "frame" drawn to the screen! -- -- Note: Even though VSYNCx controls the start of a frame you cannot simply -- disable HSYNCx cycling once the data has been shifted into the LCD. This -- is b/c there is a MAX cycle time spec in the datasheet of 450 clocks! -- It is simplest to just leave HSYNCx running at all times no matter what. -- -- Structure: -- - xupv2p.ucf -- - components.vhd -- - lq057q3dc02_tb.vhd -- - lq057q3dc02.vhd -- - dcm_sys_to_lcd.xaw -- - video_controller.vhd -- - enab_control.vhd -- - hsyncx_control.vhd -- - vsyncx_control.vhd -- - clk_lcd_cyc_cntr.vhd -- - image_gen_bram.vhd -- - image_gen_bram_red.xco -- - image_gen_bram_green.xco -- - image_gen_bram_blue.xco -- ------------------------------------------------------------------------------ -- -- Naming Conventions: -- active low signals "x" -- clock signal "CLK_" -- reset signal "RST" -- generic/constant "C_" -- user defined type "TYPE_" -- state machine next state "_ns" -- state machine current state "_cs"" -- pipelined signals "_d#" -- register delay signals "_p#" -- signal "_sig" -- variable "_var" -- storage register "_reg" -- clock enable signals "_ce" -- internal version of output port used as connecting wire "_wire" -- input/output port "ALL_CAPS" -- process "_PROC" -- ------------------------------------------------------------------------------ --////////////////////-- -- LIBRARY INCLUSIONS -- --////////////////////-- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; --////////////////////-- -- ENTITY DECLARATION -- --////////////////////-- ENTITY vsyncx_control IS ----------------------------------------------------------------- -- Generic Descriptions: -- -- C_LINE_NUM_WIDTH -- Must be at least 9 bits to hold maximum -- -- timespec of 280 lines. ----------------------------------------------------------------- generic ( C_VSYNC_TV, C_VSYNC_TVP, C_LINE_NUM_WIDTH : POSITIVE ); port ( RSTx, CLK_LCD, HSYNCx : IN STD_LOGIC; LINE_NUM : OUT STD_LOGIC_VECTOR(C_LINE_NUM_WIDTH-1 downto 0); VSYNCx : OUT STD_LOGIC ); END ENTITY vsyncx_control; --////////////////////////-- -- ARCHITECTURE OF ENTITY -- --////////////////////////-- ARCHITECTURE vsyncx_control_arch OF vsyncx_control IS --Enables/Disables the line counter process signal line_cnt_en_sig : std_logic; --Stores current line number. --This register is attached to the LINE_NUM output. signal line_num_reg : std_logic_vector(C_LINE_NUM_WIDTH-1 downto 0) := (others => '0'); --------------------------------------------------------------- -- States for VSYNCx_Line_Cntr_*_PROC --------------------------------------------------------------- --FRAME_START => Start of a new frame --ADD => Add one (1) to the line count --ADD_WAIT => Wait for HSYNCx pulse to pass --READY => Get ready to add one (1) for the next line type TYPE_Line_Cntr_Sts is ( FRAME_START, ADD, ADD_WAIT, READY ); signal Line_Cntr_cs : TYPE_Line_Cntr_Sts; signal Line_Cntr_ns : TYPE_Line_Cntr_Sts; begin --///////////////////////-- -- CONCURRENT STATEMENTS -- --///////////////////////-- LINE_NUM <= line_num_reg; --///////////-- -- PROCESSES -- --///////////-- ------------------------------------------------------------------ -- Process Description: -- This is finite state machine process 1 of 3 for the VSYNCx -- signal controller. This process only controls the reset of -- the state and the "current state to next state" assignment. -- -- Inputs: -- RSTx -- CLK_LCD -- -- Outputs: -- Line_Cntr_cs -- -- Notes: -- N/A ------------------------------------------------------------------ VSYNCx_Line_Cntr_1_PROC : process( RSTx, CLK_LCD ) begin if( RSTx = '0' ) then Line_Cntr_cs <= READY; elsif( CLK_LCD'event and CLK_LCD = '1' ) then Line_Cntr_cs <= Line_Cntr_ns; end if; end process VSYNCx_Line_Cntr_1_PROC; ------------------------------------------------------------------ -- Process Description: -- This is finite state machine process 2 of 3 for the VSYNCx -- signal controller. This process controls all of the state -- changes. -- -- Inputs: -- Line_Cntr_cs -- HSYNCx -- line_num_reg -- -- Outputs: -- Line_Cntr_ns -- -- Notes: -- We only want to start counting lines at the first HSYNCx pulse -- we see _after_ VSYNCx has been activated. This is because -- VSYNCx must occur before HSYNCx can be counted (NOTE: there is -- no sense in couting lines unless we know that a new frame has -- started - this is _most_ important for the ENAB_Cntrl process!) ------------------------------------------------------------------ VSYNCx_Line_Cntr_2_PROC : process( Line_Cntr_cs, HSYNCx, line_num_reg ) begin case Line_Cntr_cs is when FRAME_START => --reset the counter because we have started a new frame! if( HSYNCx = '0' ) then -- a new frame is starting (controlled by VSYNCx_control state machine) and here is our first line! Line_Cntr_ns <= ADD_WAIT; -- do not add +1 lines until HSYNCx goes high! The rising edge is what counts as a line, not the falling edge! else Line_Cntr_ns <= FRAME_START; -- keep waiting for first line to occur after start of new frame end if; when ADD_WAIT => if( HSYNCx = '1' ) then Line_Cntr_ns <= ADD; -- line_num_reg + 1 ! else Line_Cntr_ns <= ADD_WAIT; -- stay here until HSYNCx has been released b/c we only want to count the rising edge of HSYNCx as a line! end if; when ADD => Line_Cntr_ns <= READY; -- get ready to count another line if necessary when READY => if( line_num_reg = C_VSYNC_TV - 1 ) then -- 0 to 254 = 255 lines (first make sure we haven't reach the end of the VSYNC cycle - which is just a little bit longer than the actual number of lines on the screen - TV) Line_Cntr_ns <= FRAME_START; -- if we've reached the max VSYNC cycle time (i.e. TV) then start over! elsif( HSYNCx = '0' ) then Line_Cntr_ns <= ADD_WAIT; -- a new line has started! line_num_reg + 1!! else Line_Cntr_ns <= READY; -- stay here until HSYNCx pulse occurs end if; when others => --UH OH! How did we get here??? Line_Cntr_ns <= FRAME_START; end case; end process VSYNCx_Line_Cntr_2_PROC; ------------------------------------------------------------------ -- Process Description: -- This is finite state machine process 3 of 3 for the VSYNCx -- signal controller. This process only controls the change of -- of output values based on the current state. -- -- Inputs: -- Line_Cntr_cs -- -- Outputs: -- line_cnt_en_sig -- -- Notes: -- N/A ------------------------------------------------------------------ VSYNCx_Line_Cntr_3_PROC : process( Line_Cntr_cs ) begin case Line_Cntr_cs is when FRAME_START => --reset line_num_reg at start of new frame line_cnt_en_sig <= '0'; when READY => line_cnt_en_sig <= '0'; when ADD_WAIT => line_cnt_en_sig <= '0'; when ADD => --we will only ever be in this state for one CLK_LCD cycle. This is IMPORTANT! b/c we only want to count one CLK_LCD cycle worth of the HSYNCx active pulse no matter how long the HSYNCx pulse is! line_cnt_en_sig <= '1'; when others => --UH OH! How did we get here??? line_cnt_en_sig <= '0'; end case; end process VSYNCx_Line_Cntr_3_PROC; ------------------------------------------------------------------ -- Process Description: -- This process starts, stops, and resets the line counter -- based on the line count enable signal and the current state -- of the line counter state machine. -- -- Inputs: -- RSTx -- CLK_LCD -- -- Outputs: -- line_num_reg -- -- Notes: -- N/A ------------------------------------------------------------------ Line_cntr_PROC : process( RSTx, CLK_LCD ) begin if( RSTx = '0' ) then line_num_reg <= (others => '0'); elsif( CLK_LCD'event and CLK_LCD = '1' ) then if( line_cnt_en_sig = '1' ) then line_num_reg <= line_num_reg + 1; elsif( Line_Cntr_cs = FRAME_START ) then line_num_reg <= (others => '0'); else line_num_reg <= line_num_reg; end if; end if; end process Line_cntr_PROC; ------------------------------------------------------------------ -- Process Description: -- This process activates/deactivates the VSYNCx signal depending -- on the current line number relative to the VSYNC pulse width -- paramter. -- -- Inputs: -- RSTx -- CLK_LCD -- -- Outputs: -- VSYNCx -- -- Notes: -- N/A ------------------------------------------------------------------ VSYNCx_cntrl_PROC : process( RSTx, CLK_LCD ) begin if( RSTx = '0' ) then VSYNCx <= '1'; --INACTIVE elsif( CLK_LCD'event and CLK_LCD = '1' ) then if( line_num_reg < C_VSYNC_TVP ) then VSYNCx <= '0'; --ACTIVE else VSYNCx <= '1'; --INACTIVE end if; end if; end process VSYNCx_cntrl_PROC; END ARCHITECTURE vsyncx_control_arch;
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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block X/jPdmZ1+nSUlEnmoPAY14UVim7A9aEJcqh06tFqGlcGbH9yWK3XAStPh13NwNzkKlEwIcwn/m0V d7UX4m89ZA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block mYMJpKKFx03+nmQ4ea0UgJjtB1wlqqmjFbJyvYmn3G/s4tXfRMROaotUMoTwxA332GU+d5y20iMu mfPXeioSeyGE35gff/2NXRAmXBtbWTem0dE/PvfPIVXpzERNqB6Y0poSXwoSB2Iiz8RtkEWbqTm0 XuEUcxxaUjblueJFiyo= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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---------------------------------------- -- Register Module : IITB-RISC -- Author : Titto Thomas -- Date : 8/3/2014 ---------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity reg is generic ( nbits : integer); port ( reg_in : in std_logic_vector(nbits-1 downto 0); -- register input reg_out : out std_logic_vector(nbits-1 downto 0); -- register output clock : in std_logic; -- clock signal write : in std_logic; -- write enable signal reset : in std_logic -- reset signal ); end reg; architecture behave of reg is begin -- behave process(clock,reset) begin if(rising_edge(clock)) then if(reset = '1') then reg_out <= (others => '0'); -- reset the register elsif write = '1' then reg_out <= reg_in; -- store the input end if; end if; end process; end behave;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: grtestmod -- File: grtestmod.vhd -- Author: Jiri Gaisler, Gaisler Research -- Modified: Jan Andersson, Aeroflex Gaisler -- Contact: support@gaisler.com -- Description: Test report module -- -- See also the gaiser.sim.ahbrep module for a module connected via AHB for -- for use internally on SoC. -- -- This module supports a 16- or 32-bit interface as selected via the 'width' -- generic. -- -- In 32-bit mode the module has the following memory map: -- -- 0x00 : sets and prints vendor id from data[31:24] and -- device id from data[23:12] -- 0x04 : asserts error number data[15:0] -- 0x08 : calls subtest data[7:0] -- 0x10 : prints * GRLIB system test starting * -- 0x14 : prints Test passed / errors detected -- 0x18 : prints Checkpoint data[15:0] with time stamp -- -- In 16-bit mode the module has the following memory map: -- -- 0x00 : sets vendor id from data[15:8] and MSbs of device id from data[7:0] -- 0x04 : asserts error number data[15:0] -- 0x08 : calls subtest data[7:0] -- 0x0C : sets LSbs of device id from data[15:12], prints vendor and device id -- 0x10 : prints * GRLIB system test starting * -- 0x14 : prints Test passed / errors detected -- 0x18 : prints Checkpoint data[15:0] with time stamp -- -- The width is defined for the systest software via GRLIB_REPORTDEV_WIDTH ------------------------------------------------------------------------------ -- pragma translate_off library ieee; use ieee.std_logic_1164.all; library gaisler; use gaisler.sim.all; library grlib; use grlib.stdlib.all; use grlib.stdio.all; use grlib.devices.all; use std.textio.all; entity grtestmod is generic ( halt : integer := 0; width : integer := 32); port ( resetn : in std_ulogic; clk : in std_ulogic; errorn : in std_ulogic; address : in std_logic_vector(21 downto 2); data : inout std_logic_vector(width-1 downto 0); iosn : in std_ulogic; oen : in std_ulogic; writen : in std_ulogic; brdyn : out std_ulogic := '1'; bexcn : out std_ulogic := '1'; state : out std_logic_vector(1 downto 0); testdev : out std_logic_vector(19 downto 0); subtest : out std_logic_vector(7 downto 0) ); end; architecture sim of grtestmod is subtype msgtype is string(1 to 40); constant ntests : integer := 2; type msgarr is array (0 to ntests) of msgtype; constant msg : msgarr := ( "* Starting GRLIB system test * ", -- 0 "Test completed OK, halting simulation ", -- 1 "Test FAILED " -- 2 ); signal ior, iow : std_ulogic; signal addr : std_logic_vector(21 downto 2); signal ldata : std_logic_vector(width-1 downto 0); begin ior <= iosn or oen; iow <= iosn or writen; data <= (others => 'Z'); addr <= to_X01(address) after 1 ns; ldata <= to_X01(data) after 1 ns; log : process(ior, iow) --, clk) variable errno, errcnt, lsubtest, vendorid, deviceid : integer; variable lstate: std_logic_vector(1 downto 0) := "00"; --variable addr : std_logic_vector(21 downto 2); --variable ldata : std_logic_vector(width-1 downto 0); begin --if rising_edge(clk) then -- addr := to_X01(address); -- ldata := to_X01(data); --end if; if falling_edge (ior) then brdyn <= '1', '0' after 100 ns; if addr(15) = '1' then bexcn <= '1', '0' after 100 ns; end if; elsif rising_edge (ior) then brdyn <= '1'; bexcn <= '1'; elsif falling_edge(iow) then brdyn <= '1', '0' after 100 ns; if addr(15) = '1' then bexcn <= '1', '0' after 100 ns; end if; elsif rising_edge(iow) then brdyn <= '1'; bexcn <= '1'; -- addr := to_X01(address); case addr(7 downto 2) is when "000000" => if width = 32 then vendorid := conv_integer(ldata(31(width/32) downto 24(width/32))); deviceid := conv_integer(ldata(23(width/32) downto 12(width/32))); print(iptable(vendorid).device_table(deviceid)); testdev <= conv_std_logic_vector(vendorid256+deviceid,20); else vendorid := conv_integer(ldata(15 downto 8)); deviceid := 24conv_integer(ldata(7 downto 0)); end if; when "000001" => errno := conv_integer(ldata(15 downto 0)); if (halt = 0) then assert false report "test failed, error (" & tost(errno) & ")" severity failure; else assert false report "test failed, error (" & tost(errno) & ")" severity warning; end if; lstate := "11"; when "000010" => lsubtest := conv_integer(ldata(7 downto 0)); call_subtest(vendorid, deviceid, lsubtest); subtest <= conv_std_logic_vector(lsubtest,8); when "000011" => if width = 16 then deviceid := deviceid + conv_integer(ldata(15 downto 12)); print(iptable(vendorid).device_table(deviceid)); testdev <= conv_std_logic_vector(vendorid256+deviceid,20); end if; when "000100" => print (""); print ("* GRLIB system test starting **"); errcnt := 0; if lstate="00" then lstate := "01"; end if; when "000101" => if errcnt = 0 then print ("Test passed, halting with IU error mode"); if lstate="01" then lstate := "10"; end if; elsif errcnt = 1 then print ("1 error detected, halting with IU error mode"); else print (tost(errcnt) & " errors detected, halting with IU error mode"); end if; print (""); when "000110" => grlib.testlib.print("Checkpoint " & tost(conv_integer(ldata(15 downto 0)))); when others => end case; end if; state <= lstate; end process; end; -- pragma translate_on
--------------------------------------------------------------------- -- TITLE: Arithmetic Logic Unit -- AUTHOR: Steve Rhoads (rhoadss@yahoo.com) -- DATE CREATED: 2/8/01 -- FILENAME: alu.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Implements the ALU. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mlite_pack.all; entity function_11 is port( INPUT_1 : in std_logic_vector(31 downto 0); INPUT_2 : in std_logic_vector(31 downto 0); OUTPUT_1 : out std_logic_vector(31 downto 0) ); end; --comb_alu_1 architecture logic of function_11 is begin ------------------------------------------------------------------------- computation : process (INPUT_1, INPUT_2) variable rTemp1 : UNSIGNED(31 downto 0); variable rTemp2 : UNSIGNED(31 downto 0); variable rTemp3 : UNSIGNED(31 downto 0); begin rTemp1 := UNSIGNED( INPUT_1 ); rTemp2 := UNSIGNED( INPUT_2 ); rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED(11, 32); OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 ); end process; ------------------------------------------------------------------------- end; --architecture logic
--------------------------------------------------------------------- -- TITLE: Arithmetic Logic Unit -- AUTHOR: Steve Rhoads (rhoadss@yahoo.com) -- DATE CREATED: 2/8/01 -- FILENAME: alu.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Implements the ALU. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mlite_pack.all; entity function_11 is port( INPUT_1 : in std_logic_vector(31 downto 0); INPUT_2 : in std_logic_vector(31 downto 0); OUTPUT_1 : out std_logic_vector(31 downto 0) ); end; --comb_alu_1 architecture logic of function_11 is begin ------------------------------------------------------------------------- computation : process (INPUT_1, INPUT_2) variable rTemp1 : UNSIGNED(31 downto 0); variable rTemp2 : UNSIGNED(31 downto 0); variable rTemp3 : UNSIGNED(31 downto 0); begin rTemp1 := UNSIGNED( INPUT_1 ); rTemp2 := UNSIGNED( INPUT_2 ); rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED(11, 32); OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 ); end process; ------------------------------------------------------------------------- end; --architecture logic
--------------------------------------------------------------------- -- TITLE: Arithmetic Logic Unit -- AUTHOR: Steve Rhoads (rhoadss@yahoo.com) -- DATE CREATED: 2/8/01 -- FILENAME: alu.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Implements the ALU. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mlite_pack.all; entity function_11 is port( INPUT_1 : in std_logic_vector(31 downto 0); INPUT_2 : in std_logic_vector(31 downto 0); OUTPUT_1 : out std_logic_vector(31 downto 0) ); end; --comb_alu_1 architecture logic of function_11 is begin ------------------------------------------------------------------------- computation : process (INPUT_1, INPUT_2) variable rTemp1 : UNSIGNED(31 downto 0); variable rTemp2 : UNSIGNED(31 downto 0); variable rTemp3 : UNSIGNED(31 downto 0); begin rTemp1 := UNSIGNED( INPUT_1 ); rTemp2 := UNSIGNED( INPUT_2 ); rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED(11, 32); OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 ); end process; ------------------------------------------------------------------------- end; --architecture logic
--------------------------------------------------------------------- -- TITLE: Arithmetic Logic Unit -- AUTHOR: Steve Rhoads (rhoadss@yahoo.com) -- DATE CREATED: 2/8/01 -- FILENAME: alu.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Implements the ALU. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mlite_pack.all; entity function_11 is port( INPUT_1 : in std_logic_vector(31 downto 0); INPUT_2 : in std_logic_vector(31 downto 0); OUTPUT_1 : out std_logic_vector(31 downto 0) ); end; --comb_alu_1 architecture logic of function_11 is begin ------------------------------------------------------------------------- computation : process (INPUT_1, INPUT_2) variable rTemp1 : UNSIGNED(31 downto 0); variable rTemp2 : UNSIGNED(31 downto 0); variable rTemp3 : UNSIGNED(31 downto 0); begin rTemp1 := UNSIGNED( INPUT_1 ); rTemp2 := UNSIGNED( INPUT_2 ); rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED(11, 32); OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 ); end process; ------------------------------------------------------------------------- end; --architecture logic
--------------------------------------------------------------------- -- TITLE: Arithmetic Logic Unit -- AUTHOR: Steve Rhoads (rhoadss@yahoo.com) -- DATE CREATED: 2/8/01 -- FILENAME: alu.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Implements the ALU. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mlite_pack.all; entity function_11 is port( INPUT_1 : in std_logic_vector(31 downto 0); INPUT_2 : in std_logic_vector(31 downto 0); OUTPUT_1 : out std_logic_vector(31 downto 0) ); end; --comb_alu_1 architecture logic of function_11 is begin ------------------------------------------------------------------------- computation : process (INPUT_1, INPUT_2) variable rTemp1 : UNSIGNED(31 downto 0); variable rTemp2 : UNSIGNED(31 downto 0); variable rTemp3 : UNSIGNED(31 downto 0); begin rTemp1 := UNSIGNED( INPUT_1 ); rTemp2 := UNSIGNED( INPUT_2 ); rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED(11, 32); OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 ); end process; ------------------------------------------------------------------------- end; --architecture logic
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block DV/AB/xacdFgmpcZTKQjOdctD2VHTaUGUrPAUfaEEFxA9l+kv/UxRdlGKc0yRG3n2dtWbZxIZeZZ Y2NA9UK6BQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block M14XHNobA3hRVRjlzrOOll38qlKnPTArHnpTKjx1Oea/5cSIF+3FGdNAJYGpgqxsD80omRIbu4Jf l2bmOJ+zAqplHoNgYC3o5oTMJ6rC9MQByFkQd8O7Hkt0S/IheEMp7bbMkn8VuiU3WzCqT65oUc61 Fo7r9VKUJBOKDEVIOyc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block DV/AB/xacdFgmpcZTKQjOdctD2VHTaUGUrPAUfaEEFxA9l+kv/UxRdlGKc0yRG3n2dtWbZxIZeZZ Y2NA9UK6BQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block M14XHNobA3hRVRjlzrOOll38qlKnPTArHnpTKjx1Oea/5cSIF+3FGdNAJYGpgqxsD80omRIbu4Jf l2bmOJ+zAqplHoNgYC3o5oTMJ6rC9MQByFkQd8O7Hkt0S/IheEMp7bbMkn8VuiU3WzCqT65oUc61 Fo7r9VKUJBOKDEVIOyc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block iAoVuAxscbP7gWiXggays0uhg8jJ9BgdvjqJThzRmFeLnHjvA4+6mtsaxMSN5PObQldy4x9SS768 j6W7erSb54LqZcLTQnpbW7JvGkeX3dQRfN2alj0Oqe4iiE5XWl63BYvodOlCabqeFTkDMxuwuMv+ u+7681IBeDjxLoGahi3tI9XIOT7hML119OckvMTZleBObeHBYygNCjgz1PONsnRXn9aIecCCZJRB OVTV/8hMMK69jEyapX+p2ihSCkvqylwcaIKm3xacgjNdotQgmj6CisUijmUnKIRPorpVlYWc3mvL 8ycqmBPnDhrv8SJ4ob7oGgwtELhpPWgfeAQP/g== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block ABLhiYY4GcQoEQIrgjrLb1sae3X/mUkia7GTpn776NzQVfBqkPccAvrFrobkV+Dezw4r3hCyUkDJ DAfG0apprGQuwpeDkM3OHA6SfKqzcWKqVHgxInadOBEjYRWqqblh30GgULdetR2P21EX8lu5RP05 K79DS6/WaO+fSgz/Yzw= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block YkVwqvEcPFEitDt0CHFYj/5CLkrlaEfxeTYo0QFCvEWyu0K+30Lwa/yYZOrbOD8T0FoALREm90CB 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LIBRARY IEEE; USE STD.TEXTIO.ALL; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_TEXTIO.ALL; --ENTITY DECLARATION ENTITY TB_CHK_3BIT IS END ENTITY TB_CHK_3BIT; --ARCHITECTURE BODY ARCHITECTURE TEXTIO_WAY OF TB_CHK_3BIT IS FILE INTEST : TEXT IS IN "TEST_DATA.TXT"; SIGNAL CLK : STD_LOGIC; SIGNAL RESET : STD_LOGIC; SIGNAL BIT3 : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL DIN : STD_LOGIC; SIGNAL DOUT : STD_LOGIC; CONSTANT CLK_CYCLE: TIME :=10 NS; COMPONENT CHK_3BIT PORT ( CLK : IN STD_LOGIC; RESET : IN STD_LOGIC; BIT3 :IN STD_LOGIC_VECTOR(2 DOWNTO 0); DIN : IN STD_LOGIC; DOUT : OUT STD_LOGIC ); END COMPONENT; BEGIN DUT : CHK_3BIT PORT MAP ( CLK => CLK, RESET => RESET, BIT3 => BIT3, DIN => DIN, DOUT => DOUT ); ALWAYS:PROCESS VARIABLE LI: LINE; VARIABLE CLK_V, RESET_V, DIN_V: STD_LOGIC; VARIABLE BIT3_V:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN READLINE(INTEST, LI); READ(LI, CLK_V); READ(LI, RESET_V); READ(LI, BIT3_V); READ(LI, DIN_V); CLK<=CLK_V; RESET<=RESET_V; BIT3<=BIT3_V; DIN<=DIN_V; WAIT FOR CLK_CYCLE/4; IF (ENDFILE(INTEST)) THEN WAIT; END IF; END PROCESS; END ARCHITECTURE TEXTIO_WAY;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.arch_defs.all; use work.memory_map.all; use work.txt_utils.all; use work.utils.all; entity mem is generic (ROM : string := ""; RAMSIZE : positive := 32); port( addr : in addr_t; din : in word_t; dout : out word_t; size : in ctrl_memwidth_t; wr : in std_logic; clk : in std_logic; -- VGA I/O vgaclk, rst : in std_logic; r, g, b : out std_logic_vector (3 downto 0); hsync, vsync : out std_logic; -- LEDs leds : out std_logic_vector(7 downto 0); -- Push buttons buttons : in std_logic_vector(3 downto 0); -- DIP Switch IO switch : in std_logic_vector(7 downto 0) ); end mem; architecture struct of mem is component addrdec is port( A : in addr_t; cs : out memchipsel_t); end component; component rom_default is port (a: in addr_t; z: out word_t; en: in ctrl_t); end component; component rom_vga is port (a: in addr_t; z: out word_t; en: in ctrl_t); end component; signal cs : memchipsel_t; signal instr : instruction_t; component async_ram is generic ( MEMSIZE :integer := RAMSIZE ); port ( address : in addr_t; din : in word_t; dout : out word_t; size : in ctrl_memwidth_t; wr : in std_logic; en : in std_logic ); end component; component mmio_vga is port( -- static addr : in addr_t; din: in word_t; dout: out word_t; size : in std_logic_vector(1 downto 0); -- is also enable when = "00" wr : in std_logic; en : in std_logic; memclk : in std_logic; trap : out traps_t := TRAP_NONE; -- VGA I/O vgaclk, rst : in std_logic; r, g, b : out std_logic_vector (3 downto 0); hsync, vsync : out std_logic ); end component; component mmio_leds is port ( -- static addr : in addr_t; din: in word_t; dout: out word_t; size : in std_logic_vector(1 downto 0); -- is also enable when = "00" wr : in std_logic; en : in std_logic; clk : in std_logic; trap : out traps_t := TRAP_NONE; -- leds leds : out std_logic_vector(7 downto 0) ); end component; component mmio_buttons is port ( -- static addr : in addr_t; din: in word_t; dout: out word_t; size : in std_logic_vector(1 downto 0); -- is also enable when = "00" wr : in std_logic; en : in std_logic; clk : in std_logic; trap : out traps_t := TRAP_NONE; -- push buttons buttons : in std_logic_vector(3 downto 0) ); end component; component mmio_tsc is port ( -- static addr : in addr_t; din: in word_t; dout: out word_t; size : in std_logic_vector(1 downto 0); -- is also enable when = "00" wr : in std_logic; en : in std_logic; clk : in std_logic; trap : out traps_t := TRAP_NONE ); end component; component mmio_dipswitch is port ( -- static addr : in addr_t; din: in word_t; dout: out word_t; size : in std_logic_vector(1 downto 0); -- is also enable when = "00" wr : in std_logic; en : in std_logic; clk : in std_logic; trap : out traps_t := TRAP_NONE; -- dip switch switch : in std_logic_vector(7 downto 0) ); end component; signal vga_en : ctrl_t := '0'; begin addrdec_instance : addrdec port map(addr, cs); vga_rom_selector: if ROM = "VGA" or ROM = "vga" generate begin instruction_mem : rom_vga port map(addr, dout, cs(mmap_rom)); end generate; default_rom_selector: if ROM = "" generate begin instruction_mem : rom_default port map(addr, dout, cs(mmap_rom)); end generate; -- It's possible that this isn't interferrable. If so, maybe use synchronous RAM instead? working_ram : async_ram port map(address => addr, din => din, dout => dout, size => size, wr => wr, en => cs(mmap_ram) ); vga_en <= cs(mmap_vram) or cs(mmap_videocfg); vga : mmio_vga port map(addr => addr, din => din, dout => dout, size => size, wr => wr, en => vga_en, memclk => clk, trap => open, vgaclk => vgaclk, rst => rst, r => r, g => g, b => b, hsync => hsync, vsync => vsync ); ledbank: mmio_leds port map(addr => addr, din => din, dout => dout, size => size, wr => wr, en => cs(mmap_led), clk => clk, trap => open, leds => leds ); pushbuttons : mmio_buttons port map(addr => addr, din => din, dout => dout, size => size, wr => wr, en => cs(mmap_push), clk => clk, trap => open, buttons => buttons ); timestamp_counter : mmio_tsc port map(addr => addr, din => din, dout => dout, size => size, wr => wr, en => cs(mmap_tsc), clk => clk, trap => open ); dipswitch: mmio_dipswitch port map(addr => addr, din => din, dout => dout, size => size, wr => wr, en => cs(mmap_dipswitch), clk => clk, trap => open, switch => switch ); end struct;
library ieee; use ieee.std_logic_1164.all; entity rotator_cc is port ( clk: in std_logic; reset: in std_logic; i_data_tdata: in std_logic_vector(31 downto 0); i_data_tvalid: in std_logic; i_data_tlast: in std_logic; i_data_tready: out std_logic; i_config_tdata: in std_logic_vector(31 downto 0); i_config_tvalid: in std_logic; i_config_tready: out std_logic; o_tdata: out std_logic_vector(31 downto 0); o_tvalid: out std_logic; o_tlast: out std_logic; o_tready: in std_logic ); end rotator_cc; architecture arch of rotator_cc is signal int_data: std_logic_vector(31 downto 0); signal int_valid: std_logic; signal int_ready: std_logic; signal resetn: std_logic; signal long_tdata: std_logic_vector(79 downto 0); signal long_tvalid: std_logic; signal long_tready: std_logic; signal long_tlast: std_logic; begin resetn <= not reset; the_nco: entity work.nco port map ( aclk => clk, aresetn => resetn, s_axis_config_tdata => i_config_tdata, s_axis_config_tvalid => i_config_tvalid, s_axis_config_tready => i_config_tready, m_axis_data_tdata => int_data, m_axis_data_tvalid => int_valid, m_axis_data_tready => int_ready ); the_mult: entity work.complex_multiply port map ( aclk => clk, s_axis_a_tdata => i_data_tdata, s_axis_a_tvalid => i_data_tvalid, s_axis_a_tlast => i_data_tlast, s_axis_a_tready => i_data_tready, s_axis_b_tdata => int_data, s_axis_b_tvalid => int_valid, s_axis_b_tready => int_ready, m_axis_dout_tdata => long_tdata, m_axis_dout_tvalid => long_tvalid, m_axis_dout_tlast => long_tlast, m_axis_dout_tready => long_tready ); chopper: entity work.axi_round_and_clip_complex generic map ( WIDTH_IN => 40, WIDTH_OUT => 16, CLIP_BITS => 9 ) port map ( clk => clk, reset => reset, i_tdata => long_tdata, i_tvalid => long_tvalid, i_tlast => long_tlast, i_tready => long_tready, o_tdata => o_tdata, o_tvalid => o_tvalid, o_tlast => o_tlast, o_tready => o_tready ); end arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2336.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b07x00p02n02i02336ent IS END c07s02b07x00p02n02i02336ent; ARCHITECTURE c07s02b07x00p02n02i02336arch OF c07s02b07x00p02n02i02336ent IS BEGIN TESTING: PROCESS variable BITV : BIT := '0'; variable INTV : INTEGER; BEGIN INTV := BITV 2; assert FALSE report "*FAILED TEST: c07s02b07x00p02n02i02336 - Exponent can only be of type Integer." severity ERROR; wait; END PROCESS TESTING; END c07s02b07x00p02n02i02336arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2336.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b07x00p02n02i02336ent IS END c07s02b07x00p02n02i02336ent; ARCHITECTURE c07s02b07x00p02n02i02336arch OF c07s02b07x00p02n02i02336ent IS BEGIN TESTING: PROCESS variable BITV : BIT := '0'; variable INTV : INTEGER; BEGIN INTV := BITV 2; assert FALSE report "*FAILED TEST: c07s02b07x00p02n02i02336 - Exponent can only be of type Integer." severity ERROR; wait; END PROCESS TESTING; END c07s02b07x00p02n02i02336arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2336.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b07x00p02n02i02336ent IS END c07s02b07x00p02n02i02336ent; ARCHITECTURE c07s02b07x00p02n02i02336arch OF c07s02b07x00p02n02i02336ent IS BEGIN TESTING: PROCESS variable BITV : BIT := '0'; variable INTV : INTEGER; BEGIN INTV := BITV 2; assert FALSE report "*FAILED TEST: c07s02b07x00p02n02i02336 - Exponent can only be of type Integer." severity ERROR; wait; END PROCESS TESTING; END c07s02b07x00p02n02i02336arch;
-- NetUP Universal Dual DVB-CI FPGA firmware -- http://www.netup.tv -- -- Copyright (c) 2014 NetUP Inc, AVB Labs -- License: GPLv3 -- dma_arbiter_0.vhd -- This file was auto-generated as part of a generation operation. -- If you edit it your changes will probably be lost. library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity dma_arbiter_0 is port ( clk : in std_logic := '0'; -- clock.clk rst : in std_logic := '0'; -- reset_sink.reset dma0_addr : in std_logic_vector(60 downto 0) := (others => '0'); -- conduit_end.export dma0_wrdata : in std_logic_vector(63 downto 0) := (others => '0'); -- .export dma0_size : in std_logic_vector(6 downto 0) := (others => '0'); -- .export dma0_write : in std_logic := '0'; -- .export dma0_wait : out std_logic; -- .export dma1_addr : in std_logic_vector(60 downto 0) := (others => '0'); -- .export dma1_size : in std_logic_vector(6 downto 0) := (others => '0'); -- .export dma1_wrdata : in std_logic_vector(63 downto 0) := (others => '0'); -- .export dma1_write : in std_logic := '0'; -- .export dma1_wait : out std_logic; -- .export dma0_byteen : in std_logic_vector(7 downto 0) := (others => '0'); -- .export dma1_byteen : in std_logic_vector(7 downto 0) := (others => '0'); -- .export mem_addr : out std_logic_vector(30 downto 0); -- avalon_master.address mem_size : out std_logic_vector(6 downto 0); -- .burstcount mem_wrdata : out std_logic_vector(63 downto 0); -- .writedata mem_write : out std_logic; -- .write mem_waitreq : in std_logic := '0'; -- .waitrequest mem_byteen : out std_logic_vector(7 downto 0) -- .byteenable ); end entity dma_arbiter_0; architecture rtl of dma_arbiter_0 is component dma_arbiter is generic ( MEM_ADDR_WIDTH : natural := 31 ); port ( clk : in std_logic := 'X'; -- clk rst : in std_logic := 'X'; -- reset dma0_addr : in std_logic_vector(60 downto 0) := (others => 'X'); -- export dma0_wrdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- export dma0_size : in std_logic_vector(6 downto 0) := (others => 'X'); -- export dma0_write : in std_logic := 'X'; -- export dma0_wait : out std_logic; -- export dma1_addr : in std_logic_vector(60 downto 0) := (others => 'X'); -- export dma1_size : in std_logic_vector(6 downto 0) := (others => 'X'); -- export dma1_wrdata : in std_logic_vector(63 downto 0) := (others => 'X'); -- export dma1_write : in std_logic := 'X'; -- export dma1_wait : out std_logic; -- export dma0_byteen : in std_logic_vector(7 downto 0) := (others => 'X'); -- export dma1_byteen : in std_logic_vector(7 downto 0) := (others => 'X'); -- export mem_addr : out std_logic_vector(30 downto 0); -- address mem_size : out std_logic_vector(6 downto 0); -- burstcount mem_wrdata : out std_logic_vector(63 downto 0); -- writedata mem_write : out std_logic; -- write mem_waitreq : in std_logic := 'X'; -- waitrequest mem_byteen : out std_logic_vector(7 downto 0) -- byteenable ); end component dma_arbiter; begin dma_arbiter_0 : component dma_arbiter generic map ( MEM_ADDR_WIDTH => 31 ) port map ( clk => clk, -- clock.clk rst => rst, -- reset_sink.reset dma0_addr => dma0_addr, -- conduit_end.export dma0_wrdata => dma0_wrdata, -- .export dma0_size => dma0_size, -- .export dma0_write => dma0_write, -- .export dma0_wait => dma0_wait, -- .export dma1_addr => dma1_addr, -- .export dma1_size => dma1_size, -- .export dma1_wrdata => dma1_wrdata, -- .export dma1_write => dma1_write, -- .export dma1_wait => dma1_wait, -- .export dma0_byteen => dma0_byteen, -- .export dma1_byteen => dma1_byteen, -- .export mem_addr => mem_addr, -- avalon_master.address mem_size => mem_size, -- .burstcount mem_wrdata => mem_wrdata, -- .writedata mem_write => mem_write, -- .write mem_waitreq => mem_waitreq, -- .waitrequest mem_byteen => mem_byteen -- .byteenable ); end architecture rtl; -- of dma_arbiter_0
-- This source file was created for J-PET project in WFAIS (Jagiellonian University in Cracow) -- License for distribution outside WFAIS UJ and J-PET project is GPL v 3 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity parser is Port ( clk_read : in STD_LOGIC; reset : in STD_LOGIC; start_packet : in STD_LOGIC; end_packet : in STD_LOGIC; data_valid : in STD_LOGIC; data_in : in STD_LOGIC_VECTOR(7 downto 0); eventID: out std_logic_vector(31 downto 0); triggerID: out std_logic_vector(31 downto 0); deviceID: out std_logic_vector(15 downto 0); dataWORD: out std_logic_vector(31 downto 0); out_data: out std_logic ); end parser; architecture Behavioral of parser is type data_state is(IDLE,PACKET); signal current_data_state:data_state:=IDLE; type queue_state is(IDLE,QUEUE_HEADER,QUEUE_BODY,QUEUE_TAIL); signal current_queue_state,next_queue_state:queue_state:=IDLE; type subqueue_state is(IDLE,SUBHEADER,SUBQUEUE); signal current_subqueue_state,next_subqueue_state:subqueue_state:=IDLE; type dataitem_state is (IDLE,ITEMHEADER,ITEMBODY); signal current_item_state,next_item_state:dataitem_state:=IDLE; begin packet_state_proc:process(clk_read) begin if rising_edge(clk_read)then if start_packet='1' then current_data_state<=PACKET; elsif end_packet='1' then current_data_state<=IDLE; elsif reset='1' then current_data_state<=IDLE; end if; end if; end process packet_state_proc; parcer_state_proc:process(clk_read,reset) begin if falling_edge(clk_read) then current_queue_state<=next_queue_state; current_subqueue_state<=next_subqueue_state; current_item_state<=next_item_state; if reset='1' then current_queue_state<=IDLE; current_subqueue_state<=IDLE; current_item_state<=IDLE; end if; end if; end process parcer_state_proc; parcer_queue:process(clk_read) variable queue_cnt,queue_size:integer:=0; begin if rising_edge(clk_read)then if reset='1' then next_queue_state<=IDLE; elsif (data_valid='1')and(current_data_state=PACKET)then queue_cnt:=queue_cnt+1; case current_queue_state is when IDLE => next_queue_state<=QUEUE_HEADER; queue_cnt:=0; queue_size:=0; for i in 7 downto 0 loop queue_size:=queue_size2; if data_in(i)='1' then queue_size:=queue_size+1; end if; end loop; when QUEUE_HEADER => if queue_cnt<4 then for i in 7 downto 0 loop queue_size:=queue_size2; if data_in(i)='1' then queue_size:=queue_size+1; end if; end loop; end if; if queue_cnt=7 then next_queue_state<=QUEUE_BODY; end if; when QUEUE_BODY => if queue_cnt>=(queue_size-1)then next_queue_state<=QUEUE_TAIL; queue_cnt:=0; end if; when QUEUE_TAIL => if queue_cnt=32 then next_queue_state<=IDLE; end if; end case; end if; end if; end process parcer_queue; parcer_subqueue:process(clk_read) variable subqueue_cnt,subqueue_size:integer:=0; variable event_id,trigger_id:std_logic_vector(31 downto 0); begin if rising_edge(clk_read)then if reset='1' then next_subqueue_state<=IDLE; elsif (data_valid='1')and(current_data_state=PACKET)then if not(current_queue_state=QUEUE_BODY) then next_subqueue_state<=IDLE; else subqueue_cnt:=subqueue_cnt+1; case current_subqueue_state is when IDLE => next_subqueue_state<=SUBHEADER; subqueue_cnt:=0; subqueue_size:=0; for i in 7 downto 0 loop subqueue_size:=subqueue_size2; if data_in(i)='1' then subqueue_size:=subqueue_size+1; end if; end loop; when SUBHEADER => if subqueue_cnt<4 then for i in 7 downto 0 loop subqueue_size:=subqueue_size2; if data_in(i)='1' then subqueue_size:=subqueue_size+1; end if; end loop; end if; if subqueue_cnt=4 then subqueue_size:=subqueue_size+4; end if; if(subqueue_cnt>=8)and(subqueue_cnt<12)then for i in 7 downto 0 loop event_id((11-subqueue_cnt)8+i):=data_in(i); end loop; end if; if(subqueue_cnt>=12)and(subqueue_cnt<16)then for i in 7 downto 0 loop trigger_id((15-subqueue_cnt)8+i):=data_in(i); end loop; end if; if subqueue_cnt=15 then next_subqueue_state<=SUBQUEUE; eventID<=event_id; triggerID<=trigger_id; end if; when SUBQUEUE => if subqueue_cnt>=(subqueue_size-1)then next_subqueue_state<=IDLE; subqueue_cnt:=0; end if; end case; end if; end if; end if; end process parcer_subqueue; parce_dataitems: process(clk_read) variable dataitem_cnt,data_words_number:integer:=0; variable device_id:std_logic_vector(15 downto 0); variable current_word:std_logic_vector(31 downto 0); begin if rising_edge(clk_read)then if reset='1' then next_item_state<=IDLE; elsif(data_valid='1')and(current_data_state=PACKET)then if current_subqueue_state=SUBQUEUE then if not(current_item_state=IDLE)then dataitem_cnt:=dataitem_cnt+1; end if; case current_item_state is when IDLE => dataitem_cnt:=0; data_words_number:=0; for i in 7 downto 0 loop data_words_number:=data_words_number2; if data_in(i)='1' then data_words_number:=data_words_number+1; end if; end loop; next_item_state<=ITEMHEADER; when ITEMHEADER => if dataitem_cnt<2 then for i in 7 downto 0 loop data_words_number:=data_words_number2; if data_in(i)='1' then data_words_number:=data_words_number+1; end if; end loop; else for i in 7 downto 0 loop device_id((3-dataitem_cnt)8+i):=data_in(i); end loop; if dataitem_cnt=3 then deviceID<=device_id; next_item_state<=ITEMBODY; end if; end if; when ITEMBODY => for i in 7 downto 0 loop current_word((3-(dataitem_cnt mod 4))8+i):=data_in(i); end loop; if (dataitem_cnt mod 4)=3 then dataWORD<=current_word; out_data<='1'; end if; if dataitem_cnt>=((data_words_number+1)*4)-1 then next_item_state<=IDLE; end if; end case; end if; else out_data<='0'; end if; if not(current_subqueue_state=SUBQUEUE) then next_item_state<=IDLE; end if; end if; end process parce_dataitems; end Behavioral;
entity crash_entity is end entity; architecture default of crash_entity is type foo_t is record a, b : bit; end record; function func return bit is variable v : foo_t(0 to 1); begin return '1'; end function; begin end architecture;
---------------------------------------------------------------------------------- -- Company: NTU Athens - BNL -- Engineer: Christos Bakalis (christos.bakalis@cern.ch) -- -- Copyright Notice/Copying Permission: -- Copyright 2017 Christos Bakalis -- -- This file is part of NTUA-BNL_VMM_firmware. -- -- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>. -- -- Create Date: 05.08.2017 -- Design Name: FPGA Configuration Router -- Module Name: fpga_config_router - RTL -- Project Name: MMFE8 - NTUA -- Target Devices: Artix7 xc7a200t-2fbg484 and xc7a200t-3fbg484 -- Tool Versions: Vivado 2017.2 -- Description: Module that drives the register value bus shift register to the -- appropriate FPGA register depending on the address. -- Dependencies: MMFE8 NTUA Project -- -- Changelog: -- -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity fpga_config_router is port( ------------------------------------ ------ General Interface ----------- clk_125 : in std_logic; reg_addr : in std_logic_vector(7 downto 0); reg_rst : in std_logic; reg_value_bit : in std_logic; sreg_ena : in std_logic; ------------------------------------ ---------- XADC Interface ---------- vmm_id_xadc : out std_logic_vector(15 downto 0); xadc_sample_size : out std_logic_vector(10 downto 0); xadc_delay : out std_logic_vector(17 downto 0); ------------------------------------ ---------- AXI4SPI Interface ------- myIP_set : out std_logic_vector(31 downto 0); myMAC_set : out std_logic_vector(47 downto 0); destIP_set : out std_logic_vector(31 downto 0); ------------------------------------ -------- CKTP/CKBC Interface ------- ckbc_freq : out std_logic_vector(7 downto 0); cktk_max_num : out std_logic_vector(7 downto 0); cktp_max_num : out std_logic_vector(15 downto 0); cktp_skew : out std_logic_vector(7 downto 0); cktp_period : out std_logic_vector(15 downto 0); cktp_width : out std_logic_vector(7 downto 0); ------------------------------------ -------- FPGA Config Interface ----- latency : out std_logic_vector(15 downto 0); tr_delay_limit : out std_logic_vector(15 downto 0); ckbc_max_num : out std_logic_vector(7 downto 0); daq_state : out std_logic_vector(7 downto 0); trig_state : out std_logic_vector(7 downto 0); ro_state : out std_logic_vector(7 downto 0); fpga_rst_state : out std_logic_vector(7 downto 0) ); end fpga_config_router; architecture RTL of fpga_config_router is ---- shift register enable buses. unused, but added here for index reference ---- 0 (index) --signal vmm_id_xadc_ena : std_logic := '0'; ---- 1 --signal xadc_sample_size_ena : std_logic := '0'; ---- 2 --signal xadc_delay_ena : std_logic := '0'; ---- 3 --signal destIP_set_ena : std_logic := '0'; ---- 4 --signal myIP_set_ena : std_logic := '0'; ---- 5 --signal myMAC_set_ena(47 downto 32) : std_logic := '0'; ---- 19 --signal myMAC_set_ena(31 downto 0) : std_logic := '0'; ---- 6 --signal ckbc_freq_ena : std_logic := '0'; ---- 7 --signal cktk_max_num_ena : std_logic := '0'; ---- 8 --signal cktp_max_num_ena : std_logic := '0'; ---- 9 --signal cktp_skew_ena : std_logic := '0'; ---- 10 --signal cktp_period_ena : std_logic := '0'; ---- 11 --signal cktp_width_ena : std_logic := '0'; ---- 12 --signal latency_ena : std_logic := '0'; ---- 13 --signal tr_delay_limit_ena : std_logic := '0'; ---- 14 --signal ckbc_max_num_ena : std_logic := '0'; ---- 15 --signal daq_state_ena : std_logic := '0'; ---- 16 --signal trig_state_ena : std_logic := '0'; ---- 17 --signal ro_state_ena : std_logic := '0'; ---- 18 --signal fpga_rst_ena : std_logic := '0'; signal ena_bus : std_logic_vector(31 downto 0) := (others => '0'); -- internal registers signal daq_state_reg : std_logic_vector(7 downto 0) := (others => '0'); signal trig_state_reg : std_logic_vector(7 downto 0) := (others => '0'); signal ro_state_reg : std_logic_vector(7 downto 0) := (others => '0'); signal fpga_rst_reg : std_logic_vector(7 downto 0) := (others => '0'); signal myMAC_0 : std_logic_vector(15 downto 0) := (others => '0'); signal myMAC_1 : std_logic_vector(31 downto 0) := (others => '0'); signal latency_i : std_logic_vector(15 downto 0) := (others => '0'); signal cktk_max_num_i : std_logic_vector(7 downto 0) := (others => '0'); signal ckbc_freq_i : std_logic_vector(7 downto 0) := (others => '0'); signal cktp_max_num_i : std_logic_vector(15 downto 0) := (others => '0'); signal cktp_skew_i : std_logic_vector(7 downto 0) := (others => '0'); signal cktp_period_i : std_logic_vector(15 downto 0) := (others => '0'); signal cktp_width_i : std_logic_vector(7 downto 0) := (others => '0'); signal ckbc_max_num_i : std_logic_vector(7 downto 0) := (others => '0'); signal tr_delay_limit_i : std_logic_vector(15 downto 0) := (others => '0'); signal vmm_id_xadc_i : std_logic_vector(15 downto 0) := (others => '0'); signal xadc_sample_size_i : std_logic_vector(10 downto 0) := (others => '0'); signal xadc_delay_i : std_logic_vector(17 downto 0) := (others => '0'); signal destIP_set_i : std_logic_vector(31 downto 0) := (others => '0'); signal myIP_set_i : std_logic_vector(31 downto 0) := (others => '0'); function bit_reverse(s1:std_logic_vector) return std_logic_vector is variable rr : std_logic_vector(s1'high downto s1'low); begin for ii in s1'high downto s1'low loop rr(ii) := s1(s1'high-ii); end loop; return rr; end bit_reverse; begin router_demux: process(reg_addr, sreg_ena) begin case reg_addr is ----- fpga conf ------ when x"ab" => ena_bus(16) <= sreg_ena; ena_bus(15 downto 0) <= (others => '0'); ena_bus(31 downto 17) <= (others => '0'); -- trigger mode when x"0f" => ena_bus(15) <= sreg_ena; ena_bus(14 downto 0) <= (others => '0'); ena_bus(31 downto 16) <= (others => '0'); -- DAQ state when x"cd" => ena_bus(17) <= sreg_ena; ena_bus(16 downto 0) <= (others => '0'); ena_bus(31 downto 18) <= (others => '0'); -- readout state when x"af" => ena_bus(18) <= sreg_ena; ena_bus(17 downto 0) <= (others => '0'); ena_bus(31 downto 19) <= (others => '0'); -- FPGA reset when x"05" => ena_bus(12) <= sreg_ena; ena_bus(11 downto 0) <= (others => '0'); ena_bus(31 downto 13) <= (others => '0'); -- latency when x"c1" => ena_bus(7) <= sreg_ena; ena_bus(6 downto 0) <= (others => '0'); ena_bus(31 downto 8) <= (others => '0'); -- CKTK max when x"c2" => ena_bus(6) <= sreg_ena; ena_bus(5 downto 0) <= (others => '0'); ena_bus(31 downto 7) <= (others => '0'); -- CKBC freq when x"c3" => ena_bus(8) <= sreg_ena; ena_bus(7 downto 0) <= (others => '0'); ena_bus(31 downto 9) <= (others => '0'); -- CKTP max when x"c4" => ena_bus(9) <= sreg_ena; ena_bus(8 downto 0) <= (others => '0'); ena_bus(31 downto 10) <= (others => '0'); -- CKTP skew when x"c5" => ena_bus(10) <= sreg_ena; ena_bus(9 downto 0) <= (others => '0'); ena_bus(31 downto 11) <= (others => '0'); -- CKTP period when x"c6" => ena_bus(11) <= sreg_ena; ena_bus(10 downto 0) <= (others => '0'); ena_bus(31 downto 12) <= (others => '0'); -- CKTP width when x"c7" => ena_bus(14) <= sreg_ena; ena_bus(13 downto 0) <= (others => '0'); ena_bus(31 downto 15) <= (others => '0'); -- CKBC max when x"c8" => ena_bus(13) <= sreg_ena; ena_bus(12 downto 0) <= (others => '0'); ena_bus(31 downto 14) <= (others => '0'); -- trigger delay ----- xADC conf ------ when x"a1" => ena_bus(0) <= sreg_ena; ena_bus(31 downto 1) <= (others => '0'); ena_bus(31 downto 1) <= (others => '0'); -- VMM ID xADC when x"a2" => ena_bus(1) <= sreg_ena; ena_bus(0 downto 0) <= (others => '0'); ena_bus(31 downto 2) <= (others => '0'); -- xADC sample size when x"a3" => ena_bus(2) <= sreg_ena; ena_bus(1 downto 0) <= (others => '0'); ena_bus(31 downto 3) <= (others => '0'); -- xADC delay ----- flash IP conf -- when x"b1" => ena_bus(3) <= sreg_ena; ena_bus(2 downto 0) <= (others => '0'); ena_bus(31 downto 4) <= (others => '0'); -- destIP when x"b2" => ena_bus(4) <= sreg_ena; ena_bus(3 downto 0) <= (others => '0'); ena_bus(31 downto 5) <= (others => '0'); -- myIP when x"b3" => ena_bus(5) <= sreg_ena; ena_bus(4 downto 0) <= (others => '0'); ena_bus(31 downto 6) <= (others => '0'); -- myMAC(47 downto 32) when x"b4" => ena_bus(19) <= sreg_ena; ena_bus(18 downto 0) <= (others => '0'); ena_bus(31 downto 20) <= (others => '0'); -- myMAC(31 downto 0) when others => null; end case; end process; -- drives the enable signal to the correct shift register sreg_proc: process(clk_125) begin if(rising_edge(clk_125))then if(reg_rst = '1')then fpga_rst_reg <= (others => '0'); else ----- fpga conf ------ if(ena_bus(16) = '1')then trig_state_reg <= reg_value_bit & trig_state_reg(7 downto 1); else null; end if; if(ena_bus(15) = '1')then daq_state_reg <= reg_value_bit & daq_state_reg(7 downto 1); else null; end if; if(ena_bus(17) = '1')then ro_state_reg <= reg_value_bit & ro_state_reg(7 downto 1); else null; end if; if(ena_bus(18) = '1')then fpga_rst_reg <= reg_value_bit & fpga_rst_reg(7 downto 1); else null; end if; if(ena_bus(12) = '1')then latency_i <= reg_value_bit & latency_i(15 downto 1); else null; end if; if(ena_bus(7) = '1')then cktk_max_num_i <= reg_value_bit & cktk_max_num_i(7 downto 1); else null; end if; if(ena_bus(6) = '1')then ckbc_freq_i <= reg_value_bit & ckbc_freq_i(7 downto 1); else null; end if; if(ena_bus(8) = '1')then cktp_max_num_i <= reg_value_bit & cktp_max_num_i(15 downto 1); else null; end if; if(ena_bus(9) = '1')then cktp_skew_i <= reg_value_bit & cktp_skew_i(7 downto 1); else null; end if; if(ena_bus(10) = '1')then cktp_period_i <= reg_value_bit & cktp_period_i(15 downto 1); else null; end if; if(ena_bus(11) = '1')then cktp_width_i <= reg_value_bit & cktp_width_i(7 downto 1); else null; end if; if(ena_bus(14) = '1')then ckbc_max_num_i <= reg_value_bit & ckbc_max_num_i(7 downto 1); else null; end if; if(ena_bus(13) = '1')then tr_delay_limit_i <= reg_value_bit & tr_delay_limit_i(15 downto 1); else null; end if; ----- xADC conf ------ if(ena_bus(0) = '1')then vmm_id_xadc_i <= reg_value_bit & vmm_id_xadc_i(15 downto 1); else null; end if; if(ena_bus(1) = '1')then xadc_sample_size_i <= reg_value_bit & xadc_sample_size_i(10 downto 1); else null; end if; if(ena_bus(2) = '1')then xadc_delay_i <= reg_value_bit & xadc_delay_i(17 downto 1); else null; end if; ----- flash IP conf ---- if(ena_bus(3) = '1')then destIP_set_i <= reg_value_bit & destIP_set_i(31 downto 1); else null; end if; if(ena_bus(4) = '1')then myIP_set_i <= reg_value_bit & myIP_set_i(31 downto 1); else null; end if; if(ena_bus(5) = '1')then myMAC_0 <= reg_value_bit & myMAC_0(15 downto 1); else null; end if; if(ena_bus(19) = '1')then myMAC_1 <= reg_value_bit & myMAC_1(31 downto 1); else null; end if; end if; end if; end process; latency <= bit_reverse(latency_i); cktk_max_num <= bit_reverse(cktk_max_num_i); ckbc_freq <= bit_reverse(ckbc_freq_i); cktp_max_num <= bit_reverse(cktp_max_num_i); cktp_skew <= bit_reverse(cktp_skew_i); cktp_period <= bit_reverse(cktp_period_i); cktp_width <= bit_reverse(cktp_width_i); ckbc_max_num <= bit_reverse(ckbc_max_num_i); tr_delay_limit <= bit_reverse(tr_delay_limit_i); vmm_id_xadc <= bit_reverse(vmm_id_xadc_i); xadc_sample_size<= bit_reverse(xadc_sample_size_i); xadc_delay <= bit_reverse(xadc_delay_i); destIP_set <= bit_reverse(destIP_set_i); myIP_set <= bit_reverse(myIP_set_i); myMAC_set <= bit_reverse(myMAC_0) & bit_reverse(myMAC_1); daq_state <= bit_reverse(daq_state_reg); trig_state <= bit_reverse(trig_state_reg); ro_state <= bit_reverse(ro_state_reg); fpga_rst_state <= bit_reverse(fpga_rst_reg); end RTL;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_13_fg_13_23.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity nor_gate is generic ( width : positive; Tpd01, Tpd10 : delay_length ); port ( input : in std_logic_vector(0 to width - 1); output : out std_logic ); end entity nor_gate; architecture primitive of nor_gate is function max ( a, b : delay_length ) return delay_length is begin if a > b then return a; else return b; end if; end function max; begin reducer : process (input) is variable result : std_logic; begin result := '0'; for index in input'range loop result := result or input(index); end loop; if not result = '1' then output <= not result after Tpd01; elsif not result = '0' then output <= not result after Tpd10; else output <= not result after max(Tpd01, Tpd10); end if; end process reducer; end architecture primitive; library ieee; use ieee.std_logic_1164.all; library cell_lib; entity interlock_control is end entity interlock_control; -- code from book architecture detailed_timing of interlock_control is component nor_gate is generic ( input_width : positive ); port ( input : in std_logic_vector(0 to input_width - 1); output : out std_logic ); end component nor_gate; for ex_interlock_gate : nor_gate use entity cell_lib.nor_gate(primitive) generic map ( width => input_width, Tpd01 => 250 ps, Tpd10 => 200 ps ); -- estimates -- . . . -- not in book signal reg_access_hazard, load_hazard, stall_ex_n : std_logic; -- end not in book begin ex_interlock_gate : component nor_gate generic map ( input_width => 2 ) port map ( input(0) => reg_access_hazard, input(1) => load_hazard, output => stall_ex_n); -- . . . -- not in book reg_access_hazard <= '0' after 10 ns, '1' after 20 ns, 'X' after 30 ns; load_hazard <= '0' after 2 ns, '1' after 4 ns, 'X' after 6 ns, '0' after 12 ns, '1' after 14 ns, 'X' after 16 ns, '0' after 22 ns, '1' after 24 ns, 'X' after 26 ns, '0' after 32 ns, '1' after 34 ns, 'X' after 36 ns; -- end not in book end architecture detailed_timing; -- end code from book
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_13_fg_13_23.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity nor_gate is generic ( width : positive; Tpd01, Tpd10 : delay_length ); port ( input : in std_logic_vector(0 to width - 1); output : out std_logic ); end entity nor_gate; architecture primitive of nor_gate is function max ( a, b : delay_length ) return delay_length is begin if a > b then return a; else return b; end if; end function max; begin reducer : process (input) is variable result : std_logic; begin result := '0'; for index in input'range loop result := result or input(index); end loop; if not result = '1' then output <= not result after Tpd01; elsif not result = '0' then output <= not result after Tpd10; else output <= not result after max(Tpd01, Tpd10); end if; end process reducer; end architecture primitive; library ieee; use ieee.std_logic_1164.all; library cell_lib; entity interlock_control is end entity interlock_control; -- code from book architecture detailed_timing of interlock_control is component nor_gate is generic ( input_width : positive ); port ( input : in std_logic_vector(0 to input_width - 1); output : out std_logic ); end component nor_gate; for ex_interlock_gate : nor_gate use entity cell_lib.nor_gate(primitive) generic map ( width => input_width, Tpd01 => 250 ps, Tpd10 => 200 ps ); -- estimates -- . . . -- not in book signal reg_access_hazard, load_hazard, stall_ex_n : std_logic; -- end not in book begin ex_interlock_gate : component nor_gate generic map ( input_width => 2 ) port map ( input(0) => reg_access_hazard, input(1) => load_hazard, output => stall_ex_n); -- . . . -- not in book reg_access_hazard <= '0' after 10 ns, '1' after 20 ns, 'X' after 30 ns; load_hazard <= '0' after 2 ns, '1' after 4 ns, 'X' after 6 ns, '0' after 12 ns, '1' after 14 ns, 'X' after 16 ns, '0' after 22 ns, '1' after 24 ns, 'X' after 26 ns, '0' after 32 ns, '1' after 34 ns, 'X' after 36 ns; -- end not in book end architecture detailed_timing; -- end code from book
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_13_fg_13_23.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity nor_gate is generic ( width : positive; Tpd01, Tpd10 : delay_length ); port ( input : in std_logic_vector(0 to width - 1); output : out std_logic ); end entity nor_gate; architecture primitive of nor_gate is function max ( a, b : delay_length ) return delay_length is begin if a > b then return a; else return b; end if; end function max; begin reducer : process (input) is variable result : std_logic; begin result := '0'; for index in input'range loop result := result or input(index); end loop; if not result = '1' then output <= not result after Tpd01; elsif not result = '0' then output <= not result after Tpd10; else output <= not result after max(Tpd01, Tpd10); end if; end process reducer; end architecture primitive; library ieee; use ieee.std_logic_1164.all; library cell_lib; entity interlock_control is end entity interlock_control; -- code from book architecture detailed_timing of interlock_control is component nor_gate is generic ( input_width : positive ); port ( input : in std_logic_vector(0 to input_width - 1); output : out std_logic ); end component nor_gate; for ex_interlock_gate : nor_gate use entity cell_lib.nor_gate(primitive) generic map ( width => input_width, Tpd01 => 250 ps, Tpd10 => 200 ps ); -- estimates -- . . . -- not in book signal reg_access_hazard, load_hazard, stall_ex_n : std_logic; -- end not in book begin ex_interlock_gate : component nor_gate generic map ( input_width => 2 ) port map ( input(0) => reg_access_hazard, input(1) => load_hazard, output => stall_ex_n); -- . . . -- not in book reg_access_hazard <= '0' after 10 ns, '1' after 20 ns, 'X' after 30 ns; load_hazard <= '0' after 2 ns, '1' after 4 ns, 'X' after 6 ns, '0' after 12 ns, '1' after 14 ns, 'X' after 16 ns, '0' after 22 ns, '1' after 24 ns, 'X' after 26 ns, '0' after 32 ns, '1' after 34 ns, 'X' after 36 ns; -- end not in book end architecture detailed_timing; -- end code from book
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block mv/5S+vZc29GbeK8VAxiV166iFU3oO6o1d9hfxC6XpLHGqUsEhfXsrDxLe6x5k5kf/rylZEtsRYd AN85LLn38w== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block O93KTtv8B4S83QtYQN6GMqg10UqrWiDrvXwXNVktJNhFpYDGuehPevqLItz8Obzj6UOSIezCP2hY wqElVMSh/nP/OSiQBkFSt+2OhOEcLm1ZAA94KqmWilQ27o2c4938zZcxIi/5GMoDzQhK0ztcu6eF k6q4eCBSsfnDnMpv4jE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block mv/5S+vZc29GbeK8VAxiV166iFU3oO6o1d9hfxC6XpLHGqUsEhfXsrDxLe6x5k5kf/rylZEtsRYd AN85LLn38w== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block O93KTtv8B4S83QtYQN6GMqg10UqrWiDrvXwXNVktJNhFpYDGuehPevqLItz8Obzj6UOSIezCP2hY wqElVMSh/nP/OSiQBkFSt+2OhOEcLm1ZAA94KqmWilQ27o2c4938zZcxIi/5GMoDzQhK0ztcu6eF k6q4eCBSsfnDnMpv4jE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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--########################################################################### -- -- LOGIC CORE: Control Interface - Top level module -- MODULE NAME: control_interface() -- COMPANY: Altera Corporation -- www.altera.com -- -- REVISION HISTORY: -- -- Revision 1.1 06/06/2000 Description: Initial Release. -- -- FUNCTIONAL DESCRIPTION: -- -- This module is the command interface module for the SDR SDRAM controller. -- -- Copyright (C) 1991-2000 Altera Corporation -- --########################################################################## library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity sdr_control_interface is generic (ASIZE : integer := 32); port ( CLK : in std_logic; -- System Clock RESET_N : in std_logic; -- System Reset CMD : in std_logic_vector(2 downto 0); -- Command input ADDR : in std_logic_vector(ASIZE-1 downto 0); -- Address REF_ACK : in std_logic; -- Refresh request acknowledge CM_ACK : in std_logic; -- Command acknowledge NOP : out std_logic; -- Decoded NOP command READA : out std_logic; -- Decoded READA command WRITEA : out std_logic; -- Decoded WRITEA command REFRESH : out std_logic; -- Decoded REFRESH command PRECHARGE : out std_logic; -- Decoded PRECHARGE command LOAD_MODE : out std_logic; -- Decoded LOAD_MODE command SADDR : out std_logic_vector(ASIZE-1 downto 0); -- Registered version of ADDR SC_CL : out std_logic_vector(1 downto 0); -- Programmed CAS latency SC_RC : out std_logic_vector(1 downto 0); -- Programmed RC delay SC_RRD : out std_logic_vector(3 downto 0); -- Programmed RRD delay SC_PM : out std_logic; -- programmed Page Mode SC_BL : out std_logic_vector(3 downto 0); -- Programmed burst length REF_REQ : out std_logic; -- Hidden refresh request CMD_ACK : out std_logic -- Command acknowledge ); end sdr_control_interface; architecture RTL of sdr_control_interface is -- signal declarations signal LOAD_REG1 : std_logic; signal LOAD_REG2 : std_logic; signal REF_PER : std_logic_vector(15 downto 0); signal timer : signed(15 downto 0); signal timer_zero : std_logic; signal SADDR_int : std_logic_vector(ASIZE-1 downto 0); signal CMD_ACK_int : std_logic; signal SC_BL_int : std_logic_vector(3 downto 0); begin -- This module decodes the commands from the CMD input to individual -- command lines, NOP, READA, WRITEA, REFRESH, PRECHARGE, LOAD_MODE. -- ADDR is register in order to keep it aligned with decoded command. process(CLK, RESET_N) begin if (RESET_N = '0') then NOP <= '0'; READA <= '0'; WRITEA <= '0'; REFRESH <= '0'; PRECHARGE <= '0'; LOAD_MODE <= '0'; load_reg1 <= '0'; load_reg2 <= '0'; SADDR_int <= (others => '0'); elsif rising_edge(CLK) then SADDR_int <= ADDR; -- register the address to keep proper -- alignment with the command if (CMD = "000") then -- NOP command NOP <= '1'; else NOP <= '0'; end if; if (CMD = "001") then -- READA command READA <= '1'; else READA <= '0'; end if; if (CMD = "010") then -- WRITEA command WRITEA <= '1'; else WRITEA <= '0'; end if; if (CMD = "011") then -- REFRESH command REFRESH <= '1'; else REFRESH <= '0'; end if; if (CMD = "100") then -- PRECHARGE command PRECHARGE <= '1'; else PRECHARGE <= '0'; end if; if (CMD = "101") then -- LOAD_MODE command LOAD_MODE <= '1'; else LOAD_MODE <= '0'; end if; if ((CMD = "110") and (LOAD_REG1 = '0')) then --LOAD_REG1 command LOAD_REG1 <= '1'; else LOAD_REG1 <= '0'; end if; if ((CMD = "111") and (LOAD_REG2 = '0')) then --LOAD_REG2 command LOAD_REG2 <= '1'; else LOAD_REG2 <= '0'; end if; end if; end process; -- This always block processes the LOAD_REG1 and LOAD_REG2 commands. -- The register data comes in on SADDR and is distributed to the various -- registers. process(CLK, RESET_N) begin if (RESET_N = '0') then SC_CL <= (others => '0'); SC_RC <= (others => '0'); SC_RRD <= (others => '0'); SC_PM <= '0'; SC_BL_int <= (others => '0'); REF_PER <= (others => '0'); elsif rising_edge(CLK) then if (LOAD_REG1 = '1') then -- LOAD_REG1 command SC_CL <= SADDR_int(1 downto 0); -- CAS Latency SC_RC <= SADDR_int(3 downto 2); -- RC delay SC_RRD <= SADDR_int(7 downto 4); -- RRD delay SC_PM <= SADDR_int(8); -- Page Mode SC_BL_int <= SADDR_int(12 downto 9); -- Burst length end if; if (LOAD_REG2 = '1') then -- LOAD_REG2 command REF_PER <= SADDR_int(15 downto 0); -- REFRESH Period end if; end if; end process; SADDR <= SADDR_int; SC_BL <= SC_BL_int; -- This always block generates the command acknowledge, CMD_ACK, for the -- commands that are handled by this module, LOAD_RE1,2, and it lets -- the command ack from the lower module pass through when necessary. process(CLK, RESET_N) begin if (RESET_N = '0') then CMD_ACK_int <= '0'; elsif rising_edge(CLK) then if (((CM_ACK = '1') or (LOAD_REG1 = '1') or (LOAD_REG2 = '1')) and (CMD_ACK_int = '0')) then CMD_ACK_int <= '1'; else CMD_ACK_int <= '0'; end if; end if; end process; CMD_ACK <= CMD_ACK_int; -- This always block implements the refresh timer. The timer is a 16bit -- downcounter and a REF_REQ is generated whenever the counter reaches the -- count of zero. After reaching zero, the counter reloads with the value that -- was loaded into the refresh period register with the LOAD_REG2 command. -- Note that the refresh counter is disabled when the controller is in -- page mode operation. process(CLK, RESET_N) begin if (RESET_N = '0') then timer <= (others => '0'); timer_zero <= '0'; REF_REQ <= '0'; elsif rising_edge(CLK) then if (timer_zero = '1') then timer <= signed(REF_PER); elsif (not (SC_BL_int = "0000")) then -- only run timer if not in page mode timer <= timer - 1; end if; if (timer=0 and not (SC_BL_int = "0000")) then timer_zero <= '1'; -- count has reached zero, issue ref_req and reload REF_REQ <= '1'; -- the timer else if (REF_ACK = '1') then -- wait for the ack to come back from the lower timer_zero <= '0'; REF_REQ <= '0'; end if; end if; end if; end process; end RTL;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 18:52:27 11/19/2014 -- Design Name: -- Module Name: pwm - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity pwm is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; enable : in STD_LOGIC; top : in STD_LOGIC_VECTOR (31 downto 0); duty_cycle : in STD_LOGIC_VECTOR (31 downto 0); output : out STD_LOGIC); end pwm; architecture Behavioral of pwm is signal timer_count : unsigned(31 downto 0); signal out_signal : std_logic; begin pwm_proc: process(clk, rst) begin if(rst = '1') then timer_count <= (others => '0'); out_signal <= '1'; elsif(rising_edge(clk)) then if(enable = '1') then timer_count <= timer_count + 1; end if; if(timer_count > unsigned(top)) then timer_count <= (others => '0'); end if; if(timer_count < unsigned(duty_cycle)) then out_signal <= '0'; else out_signal <= '1'; end if; end if; end process; output <= out_signal; end Behavioral;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 18:52:27 11/19/2014 -- Design Name: -- Module Name: pwm - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity pwm is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; enable : in STD_LOGIC; top : in STD_LOGIC_VECTOR (31 downto 0); duty_cycle : in STD_LOGIC_VECTOR (31 downto 0); output : out STD_LOGIC); end pwm; architecture Behavioral of pwm is signal timer_count : unsigned(31 downto 0); signal out_signal : std_logic; begin pwm_proc: process(clk, rst) begin if(rst = '1') then timer_count <= (others => '0'); out_signal <= '1'; elsif(rising_edge(clk)) then if(enable = '1') then timer_count <= timer_count + 1; end if; if(timer_count > unsigned(top)) then timer_count <= (others => '0'); end if; if(timer_count < unsigned(duty_cycle)) then out_signal <= '0'; else out_signal <= '1'; end if; end if; end process; output <= out_signal; end Behavioral;
--------------------------------------------------------------------------- -- -- Title: Hardware Thread User Logic Exit Thread -- To be used as a place holder, and size estimate for HWTI -- --------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_misc.all; library Unisim; use Unisim.all; --------------------------------------------------------------------------- -- Port declarations --------------------------------------------------------------------------- -- Definition of Ports: -- -- Misc. Signals -- clock -- -- HWTI to HWTUL interconnect -- intrfc2thrd_address 32 bits memory -- intrfc2thrd_value 32 bits memory function -- intrfc2thrd_function 16 bits control -- intrfc2thrd_goWait 1 bits control -- -- HWTUL to HWTI interconnect -- thrd2intrfc_address 32 bits memory -- thrd2intrfc_value 32 bits memory function -- thrd2intrfc_function 16 bits function -- thrd2intrfc_opcode 6 bits memory function -- --------------------------------------------------------------------------- -- Thread Manager Entity section --------------------------------------------------------------------------- entity user_logic_hwtul is port ( clock : in std_logic; intrfc2thrd_address : in std_logic_vector(0 to 31); intrfc2thrd_value : in std_logic_vector(0 to 31); intrfc2thrd_function : in std_logic_vector(0 to 15); intrfc2thrd_goWait : in std_logic; thrd2intrfc_address : out std_logic_vector(0 to 31); thrd2intrfc_value : out std_logic_vector(0 to 31); thrd2intrfc_function : out std_logic_vector(0 to 15); thrd2intrfc_opcode : out std_logic_vector(0 to 5) ); end entity user_logic_hwtul; --------------------------------------------------------------------------- -- Architecture section --------------------------------------------------------------------------- architecture IMP of user_logic_hwtul is --------------------------------------------------------------------------- -- Signal declarations --------------------------------------------------------------------------- type state_machine is ( FUNCTION_RESET, FUNCTION_USER_SELECT, FUNCTION_START, FUNCTION_EXIT, STATE_1, STATE_2, STATE_3, STATE_4, STATE_5, STATE_6, STATE_7, STATE_8, STATE_9, STATE_10, STATE_11, STATE_12, STATE_13, STATE_14, STATE_15, STATE_16, STATE_17, STATE_18, STATE_19, STATE_20, WAIT_STATE, ERROR_STATE); -- Function definitions constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000"; constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001"; constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002"; constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003"; constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101"; constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102"; constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103"; constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104"; constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105"; constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106"; constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107"; constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108"; constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109"; constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110"; constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111"; constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112"; constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113"; constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114"; constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115"; constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116"; constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117"; constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118"; constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119"; constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120"; -- Range 0003 to 7999 reserved for user logic's state machine -- Range 8000 to 9999 reserved for system calls constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000"; constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001"; constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010"; constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011"; constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012"; constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013"; constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014"; constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015"; constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016"; constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020"; constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021"; constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022"; constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023"; constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030"; constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031"; constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032"; constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033"; constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034"; constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040"; constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041"; constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042"; constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043"; constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050"; constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051"; constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052"; constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053"; constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054"; -- Ranged A000 to FFFF reserved for supported library calls constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000"; constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001"; constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002"; -- user_opcode Constants constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000"; -- Memory sub-interface specific opcodes constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001"; constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010"; constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011"; constant OPCODE_READ : std_logic_vector(0 to 5) := "000100"; constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101"; constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110"; -- Function sub-interface specific opcodes constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000"; constant OPCODE_POP : std_logic_vector(0 to 5) := "010001"; constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010"; constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011"; constant Z32 : std_logic_vector(0 to 31) := (others => '0'); signal current_state, next_state : state_machine := FUNCTION_RESET; signal return_state, return_state_next: state_machine := FUNCTION_RESET; signal toUser_address : std_logic_vector(0 to 31); signal toUser_value : std_logic_vector(0 to 31); signal toUser_function : std_logic_vector(0 to 15); signal toUser_goWait : std_logic; signal retVal, retVal_next : std_logic_vector(0 to 31); signal arg, arg_next : std_logic_vector(0 to 31); signal reg1, reg1_next : std_logic_vector(0 to 31); signal reg2, reg2_next : std_logic_vector(0 to 31); signal reg3, reg3_next : std_logic_vector(0 to 31); signal reg4, reg4_next : std_logic_vector(0 to 31); signal reg5, reg5_next : std_logic_vector(0 to 31); signal reg6, reg6_next : std_logic_vector(0 to 31); signal reg7, reg7_next : std_logic_vector(0 to 31); signal reg8, reg8_next : std_logic_vector(0 to 31); --------------------------------------------------------------------------- -- Begin architecture --------------------------------------------------------------------------- begin -- architecture IMP HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is begin if (clock'event and (clock = '1')) then toUser_address <= intrfc2thrd_address; toUser_value <= intrfc2thrd_value; toUser_function <= intrfc2thrd_function; toUser_goWait <= intrfc2thrd_goWait; return_state <= return_state_next; retVal <= retVal_next; arg <= arg_next; reg1 <= reg1_next; reg2 <= reg2_next; reg3 <= reg3_next; reg4 <= reg4_next; reg5 <= reg5_next; reg6 <= reg6_next; reg7 <= reg7_next; reg8 <= reg8_next; -- Find out if the HWTI is tell us what to do if (intrfc2thrd_goWait = '1') then case intrfc2thrd_function is -- Typically the HWTI will tell us to control our own destiny when U_FUNCTION_USER_SELECT => current_state <= next_state; -- List all the functions the HWTI could tell us to run when U_FUNCTION_RESET => current_state <= FUNCTION_RESET; when U_FUNCTION_START => current_state <= FUNCTION_START; when U_STATE_1 => current_state <= STATE_1; when U_STATE_2 => current_state <= STATE_2; when U_STATE_3 => current_state <= STATE_3; when U_STATE_4 => current_state <= STATE_4; when U_STATE_5 => current_state <= STATE_5; when U_STATE_6 => current_state <= STATE_6; when U_STATE_7 => current_state <= STATE_7; when U_STATE_8 => current_state <= STATE_8; when U_STATE_9 => current_state <= STATE_9; when U_STATE_10 => current_state <= STATE_10; when U_STATE_11 => current_state <= STATE_11; when U_STATE_12 => current_state <= STATE_12; when U_STATE_13 => current_state <= STATE_13; when U_STATE_14 => current_state <= STATE_14; when U_STATE_15 => current_state <= STATE_15; when U_STATE_16 => current_state <= STATE_16; when U_STATE_17 => current_state <= STATE_17; when U_STATE_18 => current_state <= STATE_18; when U_STATE_19 => current_state <= STATE_19; when U_STATE_20 => current_state <= STATE_20; -- If the HWTI tells us to do something we don't know, error when OTHERS => current_state <= ERROR_STATE; end case; else current_state <= WAIT_STATE; end if; end if; end process HWTUL_STATE_PROCESS; HWTUL_STATE_MACHINE : process (clock) is begin -- Default register assignments thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse thrd2intrfc_address <= Z32; thrd2intrfc_value <= Z32; thrd2intrfc_function <= U_FUNCTION_USER_SELECT; return_state_next <= return_state; next_state <= current_state; retVal_next <= retVal; arg_next <= arg; reg1_next <= reg1; reg2_next <= reg2; reg3_next <= reg3; reg4_next <= reg4; reg5_next <= reg5; reg6_next <= reg6; reg7_next <= reg7; reg8_next <= reg8; ----------------------------------------------------------------------- -- mutex_unlock_1.c ----------------------------------------------------------------------- -- The state machine case current_state is when FUNCTION_RESET => --Set default values thrd2intrfc_opcode <= OPCODE_NOOP; thrd2intrfc_address <= Z32; thrd2intrfc_value <= Z32; thrd2intrfc_function <= U_FUNCTION_START; -- hthread_mutex_t * mutex = (hthread_mutex_t ) arg when FUNCTION_START => -- Pop the argument thrd2intrfc_value <= Z32; thrd2intrfc_opcode <= OPCODE_POP; next_state <= WAIT_STATE; return_state_next <= STATE_1; when STATE_1 => arg_next <= intrfc2thrd_value; next_state <= STATE_2; -- hthread_mutex_lock( mutex ); when STATE_2 => -- Push mutex thrd2intrfc_opcode <= OPCODE_PUSH; thrd2intrfc_value <= arg; next_state <= WAIT_STATE; return_state_next <= STATE_3; when STATE_3 => -- Call hthread_mutex_lock thrd2intrfc_opcode <= OPCODE_CALL; thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK; thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4; next_state <= WAIT_STATE; -- hthread_mutex_unlock( mutex ); when STATE_4 => -- Push mutex thrd2intrfc_opcode <= OPCODE_PUSH; thrd2intrfc_value <= arg; next_state <= WAIT_STATE; return_state_next <= STATE_5; when STATE_5 => -- Call hthread_mutex_unlock thrd2intrfc_opcode <= OPCODE_CALL; thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK; thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6; next_state <= WAIT_STATE; -- if( _mutex_owner( mutex->num ) != hthread_self() ) when STATE_6 => -- Load the value of mutex->num thrd2intrfc_opcode <= OPCODE_LOAD; thrd2intrfc_address <= arg; next_state <= WAIT_STATE; return_state_next <= STATE_7; when STATE_7 => reg1_next <= intrfc2thrd_value; -- Call the Synch Manager to find out the owner thrd2intrfc_opcode <= OPCODE_LOAD; thrd2intrfc_address <= x"75030000"; -- and yes I"m cheating with the calculated address next_state <= WAIT_STATE; return_state_next <= STATE_8; when STATE_8 => reg1_next <= intrfc2thrd_value; -- Call hthread_self(); thrd2intrfc_opcode <= OPCODE_CALL; thrd2intrfc_function <= FUNCTION_HTHREAD_SELF; thrd2intrfc_value <= Z32(0 to 15) & U_STATE_9; next_state <= WAIT_STATE; when STATE_9 => if ( intrfc2thrd_value = reg1 ) then retVal_next <= x"00000001"; else retVal_next <= Z32; end if; next_state <= STATE_10; when STATE_10 => next_state <= FUNCTION_EXIT; when FUNCTION_EXIT => --Same as hthread_exit( (void ) retVal ); thrd2intrfc_value <= retVal; thrd2intrfc_opcode <= OPCODE_RETURN; next_state <= WAIT_STATE; when WAIT_STATE => next_state <= return_state; when ERROR_STATE => next_state <= ERROR_STATE; when others => next_state <= ERROR_STATE; end case; end process HWTUL_STATE_MACHINE; end architecture IMP;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_21_ch_21_02.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity ch_21_02 is end entity ch_21_02; ---------------------------------------------------------------- architecture test of ch_21_02 is signal s : bit; begin -- code from book: p : postponed process is -- . . . begin -- . . . wait until s = '1'; -- . . . -- s may not be '1'!! -- not in book report bit'image(s); wait; -- end not in book end postponed process p; -- end of code from book stimulus : process is begin wait for 10 ns; s <= '1'; wait for 0 ns; s <= '0'; wait; end process stimulus; end architecture test;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_21_ch_21_02.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity ch_21_02 is end entity ch_21_02; ---------------------------------------------------------------- architecture test of ch_21_02 is signal s : bit; begin -- code from book: p : postponed process is -- . . . begin -- . . . wait until s = '1'; -- . . . -- s may not be '1'!! -- not in book report bit'image(s); wait; -- end not in book end postponed process p; -- end of code from book stimulus : process is begin wait for 10 ns; s <= '1'; wait for 0 ns; s <= '0'; wait; end process stimulus; end architecture test;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_21_ch_21_02.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity ch_21_02 is end entity ch_21_02; ---------------------------------------------------------------- architecture test of ch_21_02 is signal s : bit; begin -- code from book: p : postponed process is -- . . . begin -- . . . wait until s = '1'; -- . . . -- s may not be '1'!! -- not in book report bit'image(s); wait; -- end not in book end postponed process p; -- end of code from book stimulus : process is begin wait for 10 ns; s <= '1'; wait for 0 ns; s <= '0'; wait; end process stimulus; end architecture test;
entity test is type test1 is (foo); subtype test2 is test1; begin end;
library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity add_487 is port ( result : out std_logic_vector(31 downto 0); in_a : in std_logic_vector(31 downto 0); in_b : in std_logic_vector(31 downto 0) ); end add_487; architecture augh of add_487 is signal carry_inA : std_logic_vector(33 downto 0); signal carry_inB : std_logic_vector(33 downto 0); signal carry_res : std_logic_vector(33 downto 0); begin -- To handle the CI input, the operation is '1' + CI -- If CI is not present, the operation is '1' + '0' carry_inA <= '0' & in_a & '1'; carry_inB <= '0' & in_b & '0'; -- Compute the result carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB)); -- Set the outputs result <= carry_res(32 downto 1); end architecture;
library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity add_487 is port ( result : out std_logic_vector(31 downto 0); in_a : in std_logic_vector(31 downto 0); in_b : in std_logic_vector(31 downto 0) ); end add_487; architecture augh of add_487 is signal carry_inA : std_logic_vector(33 downto 0); signal carry_inB : std_logic_vector(33 downto 0); signal carry_res : std_logic_vector(33 downto 0); begin -- To handle the CI input, the operation is '1' + CI -- If CI is not present, the operation is '1' + '0' carry_inA <= '0' & in_a & '1'; carry_inB <= '0' & in_b & '0'; -- Compute the result carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB)); -- Set the outputs result <= carry_res(32 downto 1); end architecture;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --library ims; --use ims.coprocessor.all; entity MMX_EQU_8b is port ( INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0); INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0); OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0) ); end; architecture rtl of MMX_EQU_8b is begin ------------------------------------------------------------------------- -- synthesis translate_off process begin wait for 1 ns; REPORT "(IMS) MMX 8bis EQU RESSOURCE : ALLOCATION OK !"; wait; end process; -- synthesis translate_on ------------------------------------------------------------------------- ------------------------------------------------------------------------- computation : process (INPUT_1, INPUT_2) variable rTemp1 : STD_LOGIC_VECTOR(7 downto 0); variable rTemp2 : STD_LOGIC_VECTOR(7 downto 0); variable rTemp3 : STD_LOGIC_VECTOR(7 downto 0); variable rTemp4 : STD_LOGIC_VECTOR(7 downto 0); begin if( UNSIGNED(INPUT_1( 7 downto 0)) = UNSIGNED(INPUT_2( 7 downto 0)) ) then rTemp1 := "11111111"; else rTemp1 := "00000000"; end if; if( UNSIGNED(INPUT_1(15 downto 8)) = UNSIGNED(INPUT_2(15 downto 8)) ) then rTemp2 := "11111111"; else rTemp2 := "00000000"; end if; if( UNSIGNED(INPUT_1(23 downto 16)) = UNSIGNED(INPUT_2(23 downto 16)) ) then rTemp3 := "11111111"; else rTemp3 := "00000000"; end if; if( UNSIGNED(INPUT_1(31 downto 24)) = UNSIGNED(INPUT_2(31 downto 24)) ) then rTemp4 := "11111111"; else rTemp4 := "00000000"; end if; OUTPUT_1 <= (rTemp4 & rTemp3 & rTemp2 & rTemp1); end process; ------------------------------------------------------------------------- end;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:user:vga_sync:1.0 -- IP Revision: 13 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY system_vga_sync_0_0 IS PORT ( clk : IN STD_LOGIC; rst : IN STD_LOGIC; active : OUT STD_LOGIC; hsync : OUT STD_LOGIC; vsync : OUT STD_LOGIC; xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END system_vga_sync_0_0; ARCHITECTURE system_vga_sync_0_0_arch OF system_vga_sync_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT vga_sync IS GENERIC ( H_SIZE : INTEGER; H_FRONT_DELAY : INTEGER; H_BACK_DELAY : INTEGER; H_RETRACE_DELAY : INTEGER; V_SIZE : INTEGER; V_FRONT_DELAY : INTEGER; V_BACK_DELAY : INTEGER; V_RETRACE_DELAY : INTEGER ); PORT ( clk : IN STD_LOGIC; rst : IN STD_LOGIC; active : OUT STD_LOGIC; hsync : OUT STD_LOGIC; vsync : OUT STD_LOGIC; xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT vga_sync; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF system_vga_sync_0_0_arch: ARCHITECTURE IS "vga_sync,Vivado 2016.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_sync_0_0_arch : ARCHITECTURE IS "system_vga_sync_0_0,vga_sync,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF system_vga_sync_0_0_arch: ARCHITECTURE IS "system_vga_sync_0_0,vga_sync,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_sync,x_ipVersion=1.0,x_ipCoreRevision=13,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,H_FRONT_DELAY=16,H_BACK_DELAY=48,H_RETRACE_DELAY=96,V_SIZE=480,V_FRONT_DELAY=10,V_BACK_DELAY=33,V_RETRACE_DELAY=2}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK"; ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST"; BEGIN U0 : vga_sync GENERIC MAP ( H_SIZE => 640, H_FRONT_DELAY => 16, H_BACK_DELAY => 48, H_RETRACE_DELAY => 96, V_SIZE => 480, V_FRONT_DELAY => 10, V_BACK_DELAY => 33, V_RETRACE_DELAY => 2 ) PORT MAP ( clk => clk, rst => rst, active => active, hsync => hsync, vsync => vsync, xaddr => xaddr, yaddr => yaddr ); END system_vga_sync_0_0_arch;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 18:05:34 11/17/2013 -- Design Name: -- Module Name: My_Or_948282 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity My_Or_948282 is Port ( A : in STD_LOGIC; B : in STD_LOGIC; R : out STD_LOGIC); end My_Or_948282; architecture Behavioral of My_Or_948282 is component myNanddown_948282 is Port ( i0 : in STD_LOGIC; i1 : in STD_LOGIC; o1 : out STD_LOGIC); end component; component myNOT_948282 is Port ( i1 : in STD_LOGIC; o1 : out STD_LOGIC); end component; signal sig1: std_logic; signal sig2: std_logic; begin u0: myNanddown_948282 port map (i0=>A, i1=>A, o1=>sig1); u1: myNanddown_948282 port map (i0=>B, i1=>B, o1=>sig2); u2: myNanddown_948282 port map (i0=>sig1, i1=>sig2, o1=>R); end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; use work.cpu_pack.ALL; entity data_core is PORT( CLK_I : in std_logic; T2 : in std_logic; CLR : in std_logic; CE : in std_logic; -- select signals SX : in std_logic_vector( 1 downto 0); SY : in std_logic_vector( 3 downto 0); OP : in std_logic_vector( 4 downto 0); -- alu op PC : in std_logic_vector(15 downto 0); -- PC QU : in std_logic_vector( 3 downto 0); -- quick operand SA : in std_logic_vector(4 downto 0); -- select address SMQ : in std_logic; -- select MQ (H/L) -- write enable/select signal WE_RR : in std_logic; WE_LL : in std_logic; WE_SP : in SP_OP; -- data in signals IMM : in std_logic_vector(15 downto 0); -- immediate data M_RDAT : in std_logic_vector( 7 downto 0); -- memory data -- memory control signals ADR : out std_logic_vector(15 downto 0); MQ : out std_logic_vector( 7 downto 0); -- input/output IO_RDAT: in std_logic_vector( 7 downto 0); Q_RR : out std_logic_vector(15 downto 0); Q_LL : out std_logic_vector(15 downto 0); Q_SP : out std_logic_vector(15 downto 0) ); end data_core; architecture Behavioral of data_core is function b8(A : std_logic) return std_logic_vector is begin return A & A & A & A & A & A & A & A; end; COMPONENT alu8 PORT( CLK_I : in std_logic; T2 : in std_logic; CE : in std_logic; CLR : in std_logic; ALU_OP : IN std_logic_vector( 4 downto 0); XX : IN std_logic_vector(15 downto 0); YY : IN std_logic_vector(15 downto 0); ZZ : OUT std_logic_vector(15 downto 0) ); END COMPONENT; COMPONENT select_yy PORT( SY : IN std_logic_vector( 3 downto 0); IMM : IN std_logic_vector(15 downto 0); QUICK : IN std_logic_vector( 3 downto 0); M_RDAT : IN std_logic_vector( 7 downto 0); IO_RDAT : IN std_logic_vector( 7 downto 0); RR : IN std_logic_vector(15 downto 0); YY : OUT std_logic_vector(15 downto 0) ); END COMPONENT; -- cpu registers -- signal RR : std_logic_vector(15 downto 0); signal LL : std_logic_vector(15 downto 0); signal SP : std_logic_vector(15 downto 0); -- internal buses -- signal XX : std_logic_vector(15 downto 0); signal YY : std_logic_vector(15 downto 0); signal ZZ : std_logic_vector(15 downto 0); signal ADR_X : std_logic_vector(15 downto 0); signal ADR_Z : std_logic_vector(15 downto 0); signal ADR_YZ : std_logic_vector(15 downto 0); signal ADR_XYZ : std_logic_vector(15 downto 0); begin alu_8: alu8 PORT MAP( CLK_I => CLK_I, T2 => T2, CE => CE, CLR => CLR, ALU_OP => OP, XX => XX, YY => YY, ZZ => ZZ ); selyy: select_yy PORT MAP( SY => SY, IMM => IMM, QUICK => QU, M_RDAT => M_RDAT, IO_RDAT => IO_RDAT, RR => RR, YY => YY ); ADR <= ADR_XYZ; MQ <= ZZ(15 downto 8) when SMQ = '1' else ZZ(7 downto 0); Q_RR <= RR; Q_LL <= LL; Q_SP <= SP; -- memory address -- sel_ax: process(SA(4 downto 3), IMM) variable SAX : std_logic_vector(4 downto 3); begin SAX := SA(4 downto 3); case SAX is when SA_43_I16 => ADR_X <= IMM; when SA_43_I8S => ADR_X <= b8(IMM(7)) & IMM(7 downto 0); when others => ADR_X <= b8(SA(3)) & b8(SA(3)); end case; end process; sel_az: process(SA(2 downto 1), LL, RR, SP) variable SAZ : std_logic_vector(2 downto 1); begin SAZ := SA(2 downto 1); case SAZ is when SA_21_0 => ADR_Z <= X"0000"; when SA_21_LL => ADR_Z <= LL; when SA_21_RR => ADR_Z <= RR; when others => ADR_Z <= SP; end case; end process; sel_ayz: process(SA(0), ADR_Z) begin ADR_YZ <= ADR_Z + (X"000" & "000" & SA(0)); end process; sel_axyz: process(ADR_X, ADR_YZ) begin ADR_XYZ <= ADR_X + ADR_YZ; end process; sel_xx: process(SX, LL, RR, SP, PC) begin case SX is when SX_LL => XX <= LL; when SX_RR => XX <= RR; when SX_SP => XX <= SP; when others => XX <= PC; end case; end process; regs: process(CLK_I) begin if (rising_edge(CLK_I)) then if (T2 = '1') then if (CLR = '1') then RR <= X"0000"; LL <= X"0000"; SP <= X"0000"; elsif (CE = '1') then if (WE_RR = '1') then RR <= ZZ; end if; if (WE_LL = '1') then LL <= ZZ; end if; case WE_SP is when SP_INC => SP <= ADR_YZ; when SP_LOAD => SP <= ADR_XYZ; when SP_NOP => null; end case; end if; end if; end if; end process; end Behavioral;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:floating_point:7.1 -- IP Revision: 4 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY floating_point_v7_1_4; USE floating_point_v7_1_4.floating_point_v7_1_4; ENTITY convolve_kernel_ap_fadd_12_no_dsp_32 IS PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END convolve_kernel_ap_fadd_12_no_dsp_32; ARCHITECTURE convolve_kernel_ap_fadd_12_no_dsp_32_arch OF convolve_kernel_ap_fadd_12_no_dsp_32 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF convolve_kernel_ap_fadd_12_no_dsp_32_arch: ARCHITECTURE IS "yes"; COMPONENT floating_point_v7_1_4 IS GENERIC ( C_XDEVICEFAMILY : STRING; C_HAS_ADD : INTEGER; C_HAS_SUBTRACT : INTEGER; C_HAS_MULTIPLY : INTEGER; C_HAS_DIVIDE : INTEGER; C_HAS_SQRT : INTEGER; C_HAS_COMPARE : INTEGER; C_HAS_FIX_TO_FLT : INTEGER; C_HAS_FLT_TO_FIX : INTEGER; C_HAS_FLT_TO_FLT : INTEGER; C_HAS_RECIP : INTEGER; C_HAS_RECIP_SQRT : INTEGER; C_HAS_ABSOLUTE : INTEGER; C_HAS_LOGARITHM : INTEGER; C_HAS_EXPONENTIAL : INTEGER; C_HAS_FMA : INTEGER; C_HAS_FMS : INTEGER; C_HAS_ACCUMULATOR_A : INTEGER; C_HAS_ACCUMULATOR_S : INTEGER; C_A_WIDTH : INTEGER; C_A_FRACTION_WIDTH : INTEGER; C_B_WIDTH : INTEGER; C_B_FRACTION_WIDTH : INTEGER; C_C_WIDTH : INTEGER; C_C_FRACTION_WIDTH : INTEGER; C_RESULT_WIDTH : INTEGER; C_RESULT_FRACTION_WIDTH : INTEGER; C_COMPARE_OPERATION : INTEGER; C_LATENCY : INTEGER; C_OPTIMIZATION : INTEGER; C_MULT_USAGE : INTEGER; C_BRAM_USAGE : INTEGER; C_RATE : INTEGER; C_ACCUM_INPUT_MSB : INTEGER; C_ACCUM_MSB : INTEGER; C_ACCUM_LSB : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_INVALID_OP : INTEGER; C_HAS_DIVIDE_BY_ZERO : INTEGER; C_HAS_ACCUM_OVERFLOW : INTEGER; C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER; C_HAS_ACLKEN : INTEGER; C_HAS_ARESETN : INTEGER; C_THROTTLE_SCHEME : INTEGER; C_HAS_A_TUSER : INTEGER; C_HAS_A_TLAST : INTEGER; C_HAS_B : INTEGER; C_HAS_B_TUSER : INTEGER; C_HAS_B_TLAST : INTEGER; C_HAS_C : INTEGER; C_HAS_C_TUSER : INTEGER; C_HAS_C_TLAST : INTEGER; C_HAS_OPERATION : INTEGER; C_HAS_OPERATION_TUSER : INTEGER; C_HAS_OPERATION_TLAST : INTEGER; C_HAS_RESULT_TUSER : INTEGER; C_HAS_RESULT_TLAST : INTEGER; C_TLAST_RESOLUTION : INTEGER; C_A_TDATA_WIDTH : INTEGER; C_A_TUSER_WIDTH : INTEGER; C_B_TDATA_WIDTH : INTEGER; C_B_TUSER_WIDTH : INTEGER; C_C_TDATA_WIDTH : INTEGER; C_C_TUSER_WIDTH : INTEGER; C_OPERATION_TDATA_WIDTH : INTEGER; C_OPERATION_TUSER_WIDTH : INTEGER; C_RESULT_TDATA_WIDTH : INTEGER; C_RESULT_TUSER_WIDTH : INTEGER; C_FIXED_DATA_UNSIGNED : INTEGER ); PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; aresetn : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tready : OUT STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_a_tlast : IN STD_LOGIC; s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tready : OUT STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_b_tlast : IN STD_LOGIC; s_axis_c_tvalid : IN STD_LOGIC; s_axis_c_tready : OUT STD_LOGIC; s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_c_tlast : IN STD_LOGIC; s_axis_operation_tvalid : IN STD_LOGIC; s_axis_operation_tready : OUT STD_LOGIC; s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_operation_tlast : IN STD_LOGIC; m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tready : IN STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_result_tlast : OUT STD_LOGIC ); END COMPONENT floating_point_v7_1_4; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF convolve_kernel_ap_fadd_12_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_4,Vivado 2017.2"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF convolve_kernel_ap_fadd_12_no_dsp_32_arch : ARCHITECTURE IS "convolve_kernel_ap_fadd_12_no_dsp_32,floating_point_v7_1_4,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF convolve_kernel_ap_fadd_12_no_dsp_32_arch: ARCHITECTURE IS "convolve_kernel_ap_fadd_12_no_dsp_32,floating_point_v7_1_4,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_F" & "MS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=12,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=" & "0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0" & "}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA"; BEGIN U0 : floating_point_v7_1_4 GENERIC MAP ( C_XDEVICEFAMILY => "zynq", C_HAS_ADD => 1, C_HAS_SUBTRACT => 0, C_HAS_MULTIPLY => 0, C_HAS_DIVIDE => 0, C_HAS_SQRT => 0, C_HAS_COMPARE => 0, C_HAS_FIX_TO_FLT => 0, C_HAS_FLT_TO_FIX => 0, C_HAS_FLT_TO_FLT => 0, C_HAS_RECIP => 0, C_HAS_RECIP_SQRT => 0, C_HAS_ABSOLUTE => 0, C_HAS_LOGARITHM => 0, C_HAS_EXPONENTIAL => 0, C_HAS_FMA => 0, C_HAS_FMS => 0, C_HAS_ACCUMULATOR_A => 0, C_HAS_ACCUMULATOR_S => 0, C_A_WIDTH => 32, C_A_FRACTION_WIDTH => 24, C_B_WIDTH => 32, C_B_FRACTION_WIDTH => 24, C_C_WIDTH => 32, C_C_FRACTION_WIDTH => 24, C_RESULT_WIDTH => 32, C_RESULT_FRACTION_WIDTH => 24, C_COMPARE_OPERATION => 8, C_LATENCY => 12, C_OPTIMIZATION => 1, C_MULT_USAGE => 0, C_BRAM_USAGE => 0, C_RATE => 1, C_ACCUM_INPUT_MSB => 32, C_ACCUM_MSB => 32, C_ACCUM_LSB => -31, C_HAS_UNDERFLOW => 0, C_HAS_OVERFLOW => 0, C_HAS_INVALID_OP => 0, C_HAS_DIVIDE_BY_ZERO => 0, C_HAS_ACCUM_OVERFLOW => 0, C_HAS_ACCUM_INPUT_OVERFLOW => 0, C_HAS_ACLKEN => 1, C_HAS_ARESETN => 0, C_THROTTLE_SCHEME => 3, C_HAS_A_TUSER => 0, C_HAS_A_TLAST => 0, C_HAS_B => 1, C_HAS_B_TUSER => 0, C_HAS_B_TLAST => 0, C_HAS_C => 0, C_HAS_C_TUSER => 0, C_HAS_C_TLAST => 0, C_HAS_OPERATION => 0, C_HAS_OPERATION_TUSER => 0, C_HAS_OPERATION_TLAST => 0, C_HAS_RESULT_TUSER => 0, C_HAS_RESULT_TLAST => 0, C_TLAST_RESOLUTION => 0, C_A_TDATA_WIDTH => 32, C_A_TUSER_WIDTH => 1, C_B_TDATA_WIDTH => 32, C_B_TUSER_WIDTH => 1, C_C_TDATA_WIDTH => 32, C_C_TUSER_WIDTH => 1, C_OPERATION_TDATA_WIDTH => 8, C_OPERATION_TUSER_WIDTH => 1, C_RESULT_TDATA_WIDTH => 32, C_RESULT_TUSER_WIDTH => 1, C_FIXED_DATA_UNSIGNED => 0 ) PORT MAP ( aclk => aclk, aclken => aclken, aresetn => '1', s_axis_a_tvalid => s_axis_a_tvalid, s_axis_a_tdata => s_axis_a_tdata, s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_a_tlast => '0', s_axis_b_tvalid => s_axis_b_tvalid, s_axis_b_tdata => s_axis_b_tdata, s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_b_tlast => '0', s_axis_c_tvalid => '0', s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_c_tlast => '0', s_axis_operation_tvalid => '0', s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_operation_tlast => '0', m_axis_result_tvalid => m_axis_result_tvalid, m_axis_result_tready => '0', m_axis_result_tdata => m_axis_result_tdata ); END convolve_kernel_ap_fadd_12_no_dsp_32_arch;
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:lmb_v10:3.0 -- IP Revision: 6 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY lmb_v10_v3_0; USE lmb_v10_v3_0.lmb_v10; ENTITY design_1_dlmb_v10_0 IS PORT ( LMB_Clk : IN STD_LOGIC; SYS_Rst : IN STD_LOGIC; LMB_Rst : OUT STD_LOGIC; M_ABus : IN STD_LOGIC_VECTOR(0 TO 31); M_ReadStrobe : IN STD_LOGIC; M_WriteStrobe : IN STD_LOGIC; M_AddrStrobe : IN STD_LOGIC; M_DBus : IN STD_LOGIC_VECTOR(0 TO 31); M_BE : IN STD_LOGIC_VECTOR(0 TO 3); Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31); Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0); Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0); Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0); Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0); LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31); LMB_ReadStrobe : OUT STD_LOGIC; LMB_WriteStrobe : OUT STD_LOGIC; LMB_AddrStrobe : OUT STD_LOGIC; LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31); LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31); LMB_Ready : OUT STD_LOGIC; LMB_Wait : OUT STD_LOGIC; LMB_UE : OUT STD_LOGIC; LMB_CE : OUT STD_LOGIC; LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3) ); END design_1_dlmb_v10_0; ARCHITECTURE design_1_dlmb_v10_0_arch OF design_1_dlmb_v10_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_dlmb_v10_0_arch: ARCHITECTURE IS "yes"; COMPONENT lmb_v10 IS GENERIC ( C_LMB_NUM_SLAVES : INTEGER; C_LMB_DWIDTH : INTEGER; C_LMB_AWIDTH : INTEGER; C_EXT_RESET_HIGH : INTEGER ); PORT ( LMB_Clk : IN STD_LOGIC; SYS_Rst : IN STD_LOGIC; LMB_Rst : OUT STD_LOGIC; M_ABus : IN STD_LOGIC_VECTOR(0 TO 31); M_ReadStrobe : IN STD_LOGIC; M_WriteStrobe : IN STD_LOGIC; M_AddrStrobe : IN STD_LOGIC; M_DBus : IN STD_LOGIC_VECTOR(0 TO 31); M_BE : IN STD_LOGIC_VECTOR(0 TO 3); Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31); Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0); Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0); Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0); Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0); LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31); LMB_ReadStrobe : OUT STD_LOGIC; LMB_WriteStrobe : OUT STD_LOGIC; LMB_AddrStrobe : OUT STD_LOGIC; LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31); LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31); LMB_Ready : OUT STD_LOGIC; LMB_Wait : OUT STD_LOGIC; LMB_UE : OUT STD_LOGIC; LMB_CE : OUT STD_LOGIC; LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3) ); END COMPONENT lmb_v10; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF design_1_dlmb_v10_0_arch: ARCHITECTURE IS "lmb_v10,Vivado 2015.2"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_dlmb_v10_0_arch : ARCHITECTURE IS "design_1_dlmb_v10_0,lmb_v10,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF design_1_dlmb_v10_0_arch: ARCHITECTURE IS "design_1_dlmb_v10_0,lmb_v10,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_v10,x_ipVersion=3.0,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_LMB_NUM_SLAVES=1,C_LMB_DWIDTH=32,C_LMB_AWIDTH=32,C_EXT_RESET_HIGH=1}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK"; ATTRIBUTE X_INTERFACE_INFO OF SYS_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.SYS_Rst RST"; ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 RST, xilinx.com:interface:lmb:1.0 LMB_M RST"; ATTRIBUTE X_INTERFACE_INFO OF M_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ABUS"; ATTRIBUTE X_INTERFACE_INFO OF M_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READSTROBE"; ATTRIBUTE X_INTERFACE_INFO OF M_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITESTROBE"; ATTRIBUTE X_INTERFACE_INFO OF M_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ADDRSTROBE"; ATTRIBUTE X_INTERFACE_INFO OF M_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITEDBUS"; ATTRIBUTE X_INTERFACE_INFO OF M_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M BE"; ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READDBUS"; ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READY"; ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WAIT"; ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 UE"; ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 CE"; ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ABUS"; ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READSTROBE"; ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITESTROBE"; ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ADDRSTROBE"; ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READDBUS"; ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITEDBUS"; ATTRIBUTE X_INTERFACE_INFO OF LMB_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READY"; ATTRIBUTE X_INTERFACE_INFO OF LMB_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WAIT"; ATTRIBUTE X_INTERFACE_INFO OF LMB_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M UE"; ATTRIBUTE X_INTERFACE_INFO OF LMB_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M CE"; ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 BE"; BEGIN U0 : lmb_v10 GENERIC MAP ( C_LMB_NUM_SLAVES => 1, C_LMB_DWIDTH => 32, C_LMB_AWIDTH => 32, C_EXT_RESET_HIGH => 1 ) PORT MAP ( LMB_Clk => LMB_Clk, SYS_Rst => SYS_Rst, LMB_Rst => LMB_Rst, M_ABus => M_ABus, M_ReadStrobe => M_ReadStrobe, M_WriteStrobe => M_WriteStrobe, M_AddrStrobe => M_AddrStrobe, M_DBus => M_DBus, M_BE => M_BE, Sl_DBus => Sl_DBus, Sl_Ready => Sl_Ready, Sl_Wait => Sl_Wait, Sl_UE => Sl_UE, Sl_CE => Sl_CE, LMB_ABus => LMB_ABus, LMB_ReadStrobe => LMB_ReadStrobe, LMB_WriteStrobe => LMB_WriteStrobe, LMB_AddrStrobe => LMB_AddrStrobe, LMB_ReadDBus => LMB_ReadDBus, LMB_WriteDBus => LMB_WriteDBus, LMB_Ready => LMB_Ready, LMB_Wait => LMB_Wait, LMB_UE => LMB_UE, LMB_CE => LMB_CE, LMB_BE => LMB_BE ); END design_1_dlmb_v10_0_arch;
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:lmb_v10:3.0 -- IP Revision: 6 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY lmb_v10_v3_0; USE lmb_v10_v3_0.lmb_v10; ENTITY design_1_dlmb_v10_0 IS PORT ( LMB_Clk : IN STD_LOGIC; SYS_Rst : IN STD_LOGIC; LMB_Rst : OUT STD_LOGIC; M_ABus : IN STD_LOGIC_VECTOR(0 TO 31); M_ReadStrobe : IN STD_LOGIC; M_WriteStrobe : IN STD_LOGIC; M_AddrStrobe : IN STD_LOGIC; M_DBus : IN STD_LOGIC_VECTOR(0 TO 31); M_BE : IN STD_LOGIC_VECTOR(0 TO 3); Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31); Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0); Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0); Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0); Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0); LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31); LMB_ReadStrobe : OUT STD_LOGIC; LMB_WriteStrobe : OUT STD_LOGIC; LMB_AddrStrobe : OUT STD_LOGIC; LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31); LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31); LMB_Ready : OUT STD_LOGIC; LMB_Wait : OUT STD_LOGIC; LMB_UE : OUT STD_LOGIC; LMB_CE : OUT STD_LOGIC; LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3) ); END design_1_dlmb_v10_0; ARCHITECTURE design_1_dlmb_v10_0_arch OF design_1_dlmb_v10_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_dlmb_v10_0_arch: ARCHITECTURE IS "yes"; COMPONENT lmb_v10 IS GENERIC ( C_LMB_NUM_SLAVES : INTEGER; C_LMB_DWIDTH : INTEGER; C_LMB_AWIDTH : INTEGER; C_EXT_RESET_HIGH : INTEGER ); PORT ( LMB_Clk : IN STD_LOGIC; SYS_Rst : IN STD_LOGIC; LMB_Rst : OUT STD_LOGIC; M_ABus : IN STD_LOGIC_VECTOR(0 TO 31); M_ReadStrobe : IN STD_LOGIC; M_WriteStrobe : IN STD_LOGIC; M_AddrStrobe : IN STD_LOGIC; M_DBus : IN STD_LOGIC_VECTOR(0 TO 31); M_BE : IN STD_LOGIC_VECTOR(0 TO 3); Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31); Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0); Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0); Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0); Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0); LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31); LMB_ReadStrobe : OUT STD_LOGIC; LMB_WriteStrobe : OUT STD_LOGIC; LMB_AddrStrobe : OUT STD_LOGIC; LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31); LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31); LMB_Ready : OUT STD_LOGIC; LMB_Wait : OUT STD_LOGIC; LMB_UE : OUT STD_LOGIC; LMB_CE : OUT STD_LOGIC; LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3) ); END COMPONENT lmb_v10; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF design_1_dlmb_v10_0_arch: ARCHITECTURE IS "lmb_v10,Vivado 2015.2"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_dlmb_v10_0_arch : ARCHITECTURE IS "design_1_dlmb_v10_0,lmb_v10,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF design_1_dlmb_v10_0_arch: ARCHITECTURE IS "design_1_dlmb_v10_0,lmb_v10,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_v10,x_ipVersion=3.0,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_LMB_NUM_SLAVES=1,C_LMB_DWIDTH=32,C_LMB_AWIDTH=32,C_EXT_RESET_HIGH=1}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK"; ATTRIBUTE X_INTERFACE_INFO OF SYS_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.SYS_Rst RST"; ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 RST, xilinx.com:interface:lmb:1.0 LMB_M RST"; ATTRIBUTE X_INTERFACE_INFO OF M_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ABUS"; ATTRIBUTE X_INTERFACE_INFO OF M_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READSTROBE"; ATTRIBUTE X_INTERFACE_INFO OF M_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITESTROBE"; ATTRIBUTE X_INTERFACE_INFO OF M_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ADDRSTROBE"; ATTRIBUTE X_INTERFACE_INFO OF M_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITEDBUS"; ATTRIBUTE X_INTERFACE_INFO OF M_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M BE"; ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READDBUS"; ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READY"; ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WAIT"; ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 UE"; ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 CE"; ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ABUS"; ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READSTROBE"; ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITESTROBE"; ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ADDRSTROBE"; ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READDBUS"; ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITEDBUS"; ATTRIBUTE X_INTERFACE_INFO OF LMB_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READY"; ATTRIBUTE X_INTERFACE_INFO OF LMB_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WAIT"; ATTRIBUTE X_INTERFACE_INFO OF LMB_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M UE"; ATTRIBUTE X_INTERFACE_INFO OF LMB_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M CE"; ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 BE"; BEGIN U0 : lmb_v10 GENERIC MAP ( C_LMB_NUM_SLAVES => 1, C_LMB_DWIDTH => 32, C_LMB_AWIDTH => 32, C_EXT_RESET_HIGH => 1 ) PORT MAP ( LMB_Clk => LMB_Clk, SYS_Rst => SYS_Rst, LMB_Rst => LMB_Rst, M_ABus => M_ABus, M_ReadStrobe => M_ReadStrobe, M_WriteStrobe => M_WriteStrobe, M_AddrStrobe => M_AddrStrobe, M_DBus => M_DBus, M_BE => M_BE, Sl_DBus => Sl_DBus, Sl_Ready => Sl_Ready, Sl_Wait => Sl_Wait, Sl_UE => Sl_UE, Sl_CE => Sl_CE, LMB_ABus => LMB_ABus, LMB_ReadStrobe => LMB_ReadStrobe, LMB_WriteStrobe => LMB_WriteStrobe, LMB_AddrStrobe => LMB_AddrStrobe, LMB_ReadDBus => LMB_ReadDBus, LMB_WriteDBus => LMB_WriteDBus, LMB_Ready => LMB_Ready, LMB_Wait => LMB_Wait, LMB_UE => LMB_UE, LMB_CE => LMB_CE, LMB_BE => LMB_BE ); END design_1_dlmb_v10_0_arch;
---------------------------------------------------------------------------------- -- Company: ITESM CQ -- Engineer: Miguel Gonzalez A01203712 -- -- Create Date: 12:36:48 10/08/2015 -- Design Name: -- Module Name: Descending_Decimal_BCD_Counter - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: 4 bits Descending_Decimal_BCD_Counter -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use IEEE.std_logic_unsigned.all; entity Descending_Decimal_BCD_Counter is Port ( Clk : in STD_LOGIC; Rst : in STD_LOGIC; Seg : out STD_LOGIC_VECTOR (7 downto 0); Disp : out STD_LOGIC_VECTOR (3 downto 0)); end Descending_Decimal_BCD_Counter; architecture Behavioral of Descending_Decimal_BCD_Counter is signal count : STD_LOGIC_VECTOR(3 downto 0); signal frequency_counter : integer range 0 to 100000000; signal one_hz : STD_LOGIC; signal result : STD_LOGIC_VECTOR(3 downto 0); constant limit : STD_LOGIC_VECTOR(3 downto 0) := "1001"; begin Frequency_divider: process(Rst, Clk) begin if(rising_edge(Clk)) then --check counter final value if(frequency_counter = 100000000) then frequency_counter <= 1; one_hz <= '1'; else frequency_counter <= frequency_counter + 1; one_hz <= '0'; end if; end if; end process Frequency_divider; Binary_counter: process(Rst, Clk, one_hz) begin --Async reset if (Rst = '1') then --fill zeros count <= (others => '0'); elsif (rising_edge(Clk) and one_hz = '1') then if (count = limit) then count <= (others => '0'); else count <= count + 1; end if; end if; end process Binary_counter; result <= limit - count; --Decoder decoder_case: process(result) VARIABLE bufer: STD_LOGIC_VECTOR (7 downto 0); begin case(result) is when "0000" => bufer:= "11000000"; when "0001" => bufer:= "11111001"; when "0010" => bufer:= "10100100"; when "0011" => bufer:= "10110000"; when "0100" => bufer:= "10011001"; when "0101" => bufer:= "10010010"; when "0110" => bufer:= "10000010"; when "0111" => bufer:= "11111000"; when "1000" => bufer:= "10000000"; when "1001" => bufer:= "10011000"; when "1010" => bufer:= "10001000"; when "1011" => bufer:= "10000011"; when "1100" => bufer:= "11000110"; when "1101" => bufer:= "10100001"; when "1110" => bufer:= "10000110"; when others => bufer:= "10001110"; end case; Seg <= bufer; end process decoder_case; disp <= "1110"; end Behavioral;
------------------------------------------------------------------------------- -- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- or_muxcy_f ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: or_muxcy_f.vhd -- -- Description: -- (Note: It is recommended to use this module sparingly. -- XST synthesis inferral of reduction-OR functionality -- has progressed to where a carry-chain implementation -- will be selected if it has advantages. At the same -- time, if a rigid carry chain structure is not imposed, -- XST has more degrees of freedom for optimization. -- -- This module can be used to get an inferred implementation -- by specifying C_FAMILY = "nofamily", which is the default -- value of this Generic. It is equally possible to use -- a reduction-or function (see or_reduce, below, for an -- example) instead of this module. -- -- If however the designer wants without compromise -- a structural carry-chain implementation, then this -- module can be used with C_FAMILY set to the target -- Xilinx FPGA family. -- -- End of Note. -- ) -- -- -- Or_out <= or_reduce(In_bus) -- -- i.e., OR together the bits in In_bus and assign to Or_out. -- -- The implementation uses a single LUT if possible. -- Otherwise, if C_FAMILY supports the carry chain concept, -- it uses a minimal number of LUTs on a carry chain. -- The native LUT size of C_FAMILY is taken into account. -- ------------------------------------------------------------------------------- -- Structure: Common use module ------------------------------------------------------------------------------- -- Author: FLO -- History: -- FLO 07/06/06 -- First version - derived from or_with_enable_f -- ~~~~~~ -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- entity or_muxcy_f is generic ( C_NUM_BITS : integer; C_FAMILY : string := "nofamily" ); port ( In_bus : in std_logic_vector(0 to C_NUM_BITS-1); Or_out : out std_logic ); end or_muxcy_f; library proc_common_v4_0; use proc_common_v4_0.family_support.all; -- Makes visible the function 'supported' and related types, -- including enumeration literals for the unisim primitives (e.g. -- the "u_" prefixed identifiers such as u_MUXCY, u_LUT4, etc.). library unisim; use unisim.all; -- Make unisim entities available for default binding. -- architecture implementation of or_muxcy_f is ---------------------------------------------------------------------------- -- Here is determined the largest LUT width supported by the target family. -- If no LUT is supported, the width is set to a very large number, which, -- as things are structured, will cause an inferred implementation -- to be used. ---------------------------------------------------------------------------- constant lut_size : integer := native_lut_size(fam_as_string => C_FAMILY, no_lut_return_val => integer'high); ---------------------------------------------------------------------------- -- Here is determined which structural or inferred implementation to use. ---------------------------------------------------------------------------- constant USE_STRUCTURAL_A : boolean := supported(C_FAMILY, u_MUXCY) and In_bus'length > lut_size; -- Structural implementation not needed if the number -- bits to be ORed will fit into a single LUT. constant USE_INFERRED : boolean := not USE_STRUCTURAL_A; ---------------------------------------------------------------------------- -- Reduction OR function. ---------------------------------------------------------------------------- function or_reduce (v : std_logic_vector) return std_logic is variable r : std_logic := '0'; begin for i in v'range loop r := r or v(i); end loop; return r; end; ---------------------------------------------------------------------------- -- Min function. ---------------------------------------------------------------------------- function min (a, b: natural) return natural is begin if (a>b) then return b; else return a; end if; end; ---------------------------------------------------------------------------- -- Signal to recast In_bus into a local array whose index bounds and -- direction are known. ---------------------------------------------------------------------------- signal OB : std_logic_vector(0 to In_bus'length-1); ---------------------------------------------------------------------------- -- Unisim components declared locally for maximum avoidance of default -- binding and vcomponents version issues. ---------------------------------------------------------------------------- component MUXCY port ( O : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end component; begin OB <= In_bus; ---------------------------------------------------------------------------- -- Inferred implementation. ---------------------------------------------------------------------------- INFERRED_GEN : if USE_INFERRED generate begin Or_out <= or_reduce(OB); end generate INFERRED_GEN; ---------------------------------------------------------------------------- -- Structural implementation. ---------------------------------------------------------------------------- STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate constant NUM_LUTS : positive := ((OB'length + lut_size - 1) / lut_size); signal cy : std_logic_vector(0 to NUM_LUTS); begin -- cy(0) <= '0'; -- GEN : for i in 0 to NUM_LUTS-1 generate signal lut : std_logic; begin lut <= not or_reduce(OB(ilut_size to min((i+1)*lut_size-1, OB'right))); -- The min -- function catches the case where one LUT -- is partial (i.e., not all inputs are used). -- I_MUXCY : component MUXCY port map (O =>cy(NUM_LUTS - i), CI=>cy(NUM_LUTS - 1 - i), DI=>'1', S =>lut); -- Note on cy handling: As done here, the partial LUT, if any, -- is placed at the start of the cy chain. end generate; -- Or_out <= cy(NUM_LUTS); -- end generate STRUCTURAL_A_GEN; end implementation;
------------------------------------------------------------------------------- -- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- or_muxcy_f ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: or_muxcy_f.vhd -- -- Description: -- (Note: It is recommended to use this module sparingly. -- XST synthesis inferral of reduction-OR functionality -- has progressed to where a carry-chain implementation -- will be selected if it has advantages. At the same -- time, if a rigid carry chain structure is not imposed, -- XST has more degrees of freedom for optimization. -- -- This module can be used to get an inferred implementation -- by specifying C_FAMILY = "nofamily", which is the default -- value of this Generic. It is equally possible to use -- a reduction-or function (see or_reduce, below, for an -- example) instead of this module. -- -- If however the designer wants without compromise -- a structural carry-chain implementation, then this -- module can be used with C_FAMILY set to the target -- Xilinx FPGA family. -- -- End of Note. -- ) -- -- -- Or_out <= or_reduce(In_bus) -- -- i.e., OR together the bits in In_bus and assign to Or_out. -- -- The implementation uses a single LUT if possible. -- Otherwise, if C_FAMILY supports the carry chain concept, -- it uses a minimal number of LUTs on a carry chain. -- The native LUT size of C_FAMILY is taken into account. -- ------------------------------------------------------------------------------- -- Structure: Common use module ------------------------------------------------------------------------------- -- Author: FLO -- History: -- FLO 07/06/06 -- First version - derived from or_with_enable_f -- ~~~~~~ -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- entity or_muxcy_f is generic ( C_NUM_BITS : integer; C_FAMILY : string := "nofamily" ); port ( In_bus : in std_logic_vector(0 to C_NUM_BITS-1); Or_out : out std_logic ); end or_muxcy_f; library proc_common_v4_0; use proc_common_v4_0.family_support.all; -- Makes visible the function 'supported' and related types, -- including enumeration literals for the unisim primitives (e.g. -- the "u_" prefixed identifiers such as u_MUXCY, u_LUT4, etc.). library unisim; use unisim.all; -- Make unisim entities available for default binding. -- architecture implementation of or_muxcy_f is ---------------------------------------------------------------------------- -- Here is determined the largest LUT width supported by the target family. -- If no LUT is supported, the width is set to a very large number, which, -- as things are structured, will cause an inferred implementation -- to be used. ---------------------------------------------------------------------------- constant lut_size : integer := native_lut_size(fam_as_string => C_FAMILY, no_lut_return_val => integer'high); ---------------------------------------------------------------------------- -- Here is determined which structural or inferred implementation to use. ---------------------------------------------------------------------------- constant USE_STRUCTURAL_A : boolean := supported(C_FAMILY, u_MUXCY) and In_bus'length > lut_size; -- Structural implementation not needed if the number -- bits to be ORed will fit into a single LUT. constant USE_INFERRED : boolean := not USE_STRUCTURAL_A; ---------------------------------------------------------------------------- -- Reduction OR function. ---------------------------------------------------------------------------- function or_reduce (v : std_logic_vector) return std_logic is variable r : std_logic := '0'; begin for i in v'range loop r := r or v(i); end loop; return r; end; ---------------------------------------------------------------------------- -- Min function. ---------------------------------------------------------------------------- function min (a, b: natural) return natural is begin if (a>b) then return b; else return a; end if; end; ---------------------------------------------------------------------------- -- Signal to recast In_bus into a local array whose index bounds and -- direction are known. ---------------------------------------------------------------------------- signal OB : std_logic_vector(0 to In_bus'length-1); ---------------------------------------------------------------------------- -- Unisim components declared locally for maximum avoidance of default -- binding and vcomponents version issues. ---------------------------------------------------------------------------- component MUXCY port ( O : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end component; begin OB <= In_bus; ---------------------------------------------------------------------------- -- Inferred implementation. ---------------------------------------------------------------------------- INFERRED_GEN : if USE_INFERRED generate begin Or_out <= or_reduce(OB); end generate INFERRED_GEN; ---------------------------------------------------------------------------- -- Structural implementation. ---------------------------------------------------------------------------- STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate constant NUM_LUTS : positive := ((OB'length + lut_size - 1) / lut_size); signal cy : std_logic_vector(0 to NUM_LUTS); begin -- cy(0) <= '0'; -- GEN : for i in 0 to NUM_LUTS-1 generate signal lut : std_logic; begin lut <= not or_reduce(OB(ilut_size to min((i+1)*lut_size-1, OB'right))); -- The min -- function catches the case where one LUT -- is partial (i.e., not all inputs are used). -- I_MUXCY : component MUXCY port map (O =>cy(NUM_LUTS - i), CI=>cy(NUM_LUTS - 1 - i), DI=>'1', S =>lut); -- Note on cy handling: As done here, the partial LUT, if any, -- is placed at the start of the cy chain. end generate; -- Or_out <= cy(NUM_LUTS); -- end generate STRUCTURAL_A_GEN; end implementation;
------------------------------------------------------------------------------- -- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- or_muxcy_f ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: or_muxcy_f.vhd -- -- Description: -- (Note: It is recommended to use this module sparingly. -- XST synthesis inferral of reduction-OR functionality -- has progressed to where a carry-chain implementation -- will be selected if it has advantages. At the same -- time, if a rigid carry chain structure is not imposed, -- XST has more degrees of freedom for optimization. -- -- This module can be used to get an inferred implementation -- by specifying C_FAMILY = "nofamily", which is the default -- value of this Generic. It is equally possible to use -- a reduction-or function (see or_reduce, below, for an -- example) instead of this module. -- -- If however the designer wants without compromise -- a structural carry-chain implementation, then this -- module can be used with C_FAMILY set to the target -- Xilinx FPGA family. -- -- End of Note. -- ) -- -- -- Or_out <= or_reduce(In_bus) -- -- i.e., OR together the bits in In_bus and assign to Or_out. -- -- The implementation uses a single LUT if possible. -- Otherwise, if C_FAMILY supports the carry chain concept, -- it uses a minimal number of LUTs on a carry chain. -- The native LUT size of C_FAMILY is taken into account. -- ------------------------------------------------------------------------------- -- Structure: Common use module ------------------------------------------------------------------------------- -- Author: FLO -- History: -- FLO 07/06/06 -- First version - derived from or_with_enable_f -- ~~~~~~ -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- entity or_muxcy_f is generic ( C_NUM_BITS : integer; C_FAMILY : string := "nofamily" ); port ( In_bus : in std_logic_vector(0 to C_NUM_BITS-1); Or_out : out std_logic ); end or_muxcy_f; library proc_common_v4_0; use proc_common_v4_0.family_support.all; -- Makes visible the function 'supported' and related types, -- including enumeration literals for the unisim primitives (e.g. -- the "u_" prefixed identifiers such as u_MUXCY, u_LUT4, etc.). library unisim; use unisim.all; -- Make unisim entities available for default binding. -- architecture implementation of or_muxcy_f is ---------------------------------------------------------------------------- -- Here is determined the largest LUT width supported by the target family. -- If no LUT is supported, the width is set to a very large number, which, -- as things are structured, will cause an inferred implementation -- to be used. ---------------------------------------------------------------------------- constant lut_size : integer := native_lut_size(fam_as_string => C_FAMILY, no_lut_return_val => integer'high); ---------------------------------------------------------------------------- -- Here is determined which structural or inferred implementation to use. ---------------------------------------------------------------------------- constant USE_STRUCTURAL_A : boolean := supported(C_FAMILY, u_MUXCY) and In_bus'length > lut_size; -- Structural implementation not needed if the number -- bits to be ORed will fit into a single LUT. constant USE_INFERRED : boolean := not USE_STRUCTURAL_A; ---------------------------------------------------------------------------- -- Reduction OR function. ---------------------------------------------------------------------------- function or_reduce (v : std_logic_vector) return std_logic is variable r : std_logic := '0'; begin for i in v'range loop r := r or v(i); end loop; return r; end; ---------------------------------------------------------------------------- -- Min function. ---------------------------------------------------------------------------- function min (a, b: natural) return natural is begin if (a>b) then return b; else return a; end if; end; ---------------------------------------------------------------------------- -- Signal to recast In_bus into a local array whose index bounds and -- direction are known. ---------------------------------------------------------------------------- signal OB : std_logic_vector(0 to In_bus'length-1); ---------------------------------------------------------------------------- -- Unisim components declared locally for maximum avoidance of default -- binding and vcomponents version issues. ---------------------------------------------------------------------------- component MUXCY port ( O : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end component; begin OB <= In_bus; ---------------------------------------------------------------------------- -- Inferred implementation. ---------------------------------------------------------------------------- INFERRED_GEN : if USE_INFERRED generate begin Or_out <= or_reduce(OB); end generate INFERRED_GEN; ---------------------------------------------------------------------------- -- Structural implementation. ---------------------------------------------------------------------------- STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate constant NUM_LUTS : positive := ((OB'length + lut_size - 1) / lut_size); signal cy : std_logic_vector(0 to NUM_LUTS); begin -- cy(0) <= '0'; -- GEN : for i in 0 to NUM_LUTS-1 generate signal lut : std_logic; begin lut <= not or_reduce(OB(ilut_size to min((i+1)*lut_size-1, OB'right))); -- The min -- function catches the case where one LUT -- is partial (i.e., not all inputs are used). -- I_MUXCY : component MUXCY port map (O =>cy(NUM_LUTS - i), CI=>cy(NUM_LUTS - 1 - i), DI=>'1', S =>lut); -- Note on cy handling: As done here, the partial LUT, if any, -- is placed at the start of the cy chain. end generate; -- Or_out <= cy(NUM_LUTS); -- end generate STRUCTURAL_A_GEN; end implementation;
------------------------------------------------------------------------------- -- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- or_muxcy_f ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: or_muxcy_f.vhd -- -- Description: -- (Note: It is recommended to use this module sparingly. -- XST synthesis inferral of reduction-OR functionality -- has progressed to where a carry-chain implementation -- will be selected if it has advantages. At the same -- time, if a rigid carry chain structure is not imposed, -- XST has more degrees of freedom for optimization. -- -- This module can be used to get an inferred implementation -- by specifying C_FAMILY = "nofamily", which is the default -- value of this Generic. It is equally possible to use -- a reduction-or function (see or_reduce, below, for an -- example) instead of this module. -- -- If however the designer wants without compromise -- a structural carry-chain implementation, then this -- module can be used with C_FAMILY set to the target -- Xilinx FPGA family. -- -- End of Note. -- ) -- -- -- Or_out <= or_reduce(In_bus) -- -- i.e., OR together the bits in In_bus and assign to Or_out. -- -- The implementation uses a single LUT if possible. -- Otherwise, if C_FAMILY supports the carry chain concept, -- it uses a minimal number of LUTs on a carry chain. -- The native LUT size of C_FAMILY is taken into account. -- ------------------------------------------------------------------------------- -- Structure: Common use module ------------------------------------------------------------------------------- -- Author: FLO -- History: -- FLO 07/06/06 -- First version - derived from or_with_enable_f -- ~~~~~~ -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- entity or_muxcy_f is generic ( C_NUM_BITS : integer; C_FAMILY : string := "nofamily" ); port ( In_bus : in std_logic_vector(0 to C_NUM_BITS-1); Or_out : out std_logic ); end or_muxcy_f; library proc_common_v4_0; use proc_common_v4_0.family_support.all; -- Makes visible the function 'supported' and related types, -- including enumeration literals for the unisim primitives (e.g. -- the "u_" prefixed identifiers such as u_MUXCY, u_LUT4, etc.). library unisim; use unisim.all; -- Make unisim entities available for default binding. -- architecture implementation of or_muxcy_f is ---------------------------------------------------------------------------- -- Here is determined the largest LUT width supported by the target family. -- If no LUT is supported, the width is set to a very large number, which, -- as things are structured, will cause an inferred implementation -- to be used. ---------------------------------------------------------------------------- constant lut_size : integer := native_lut_size(fam_as_string => C_FAMILY, no_lut_return_val => integer'high); ---------------------------------------------------------------------------- -- Here is determined which structural or inferred implementation to use. ---------------------------------------------------------------------------- constant USE_STRUCTURAL_A : boolean := supported(C_FAMILY, u_MUXCY) and In_bus'length > lut_size; -- Structural implementation not needed if the number -- bits to be ORed will fit into a single LUT. constant USE_INFERRED : boolean := not USE_STRUCTURAL_A; ---------------------------------------------------------------------------- -- Reduction OR function. ---------------------------------------------------------------------------- function or_reduce (v : std_logic_vector) return std_logic is variable r : std_logic := '0'; begin for i in v'range loop r := r or v(i); end loop; return r; end; ---------------------------------------------------------------------------- -- Min function. ---------------------------------------------------------------------------- function min (a, b: natural) return natural is begin if (a>b) then return b; else return a; end if; end; ---------------------------------------------------------------------------- -- Signal to recast In_bus into a local array whose index bounds and -- direction are known. ---------------------------------------------------------------------------- signal OB : std_logic_vector(0 to In_bus'length-1); ---------------------------------------------------------------------------- -- Unisim components declared locally for maximum avoidance of default -- binding and vcomponents version issues. ---------------------------------------------------------------------------- component MUXCY port ( O : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end component; begin OB <= In_bus; ---------------------------------------------------------------------------- -- Inferred implementation. ---------------------------------------------------------------------------- INFERRED_GEN : if USE_INFERRED generate begin Or_out <= or_reduce(OB); end generate INFERRED_GEN; ---------------------------------------------------------------------------- -- Structural implementation. ---------------------------------------------------------------------------- STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate constant NUM_LUTS : positive := ((OB'length + lut_size - 1) / lut_size); signal cy : std_logic_vector(0 to NUM_LUTS); begin -- cy(0) <= '0'; -- GEN : for i in 0 to NUM_LUTS-1 generate signal lut : std_logic; begin lut <= not or_reduce(OB(ilut_size to min((i+1)*lut_size-1, OB'right))); -- The min -- function catches the case where one LUT -- is partial (i.e., not all inputs are used). -- I_MUXCY : component MUXCY port map (O =>cy(NUM_LUTS - i), CI=>cy(NUM_LUTS - 1 - i), DI=>'1', S =>lut); -- Note on cy handling: As done here, the partial LUT, if any, -- is placed at the start of the cy chain. end generate; -- Or_out <= cy(NUM_LUTS); -- end generate STRUCTURAL_A_GEN; end implementation;
------------------------------------------------------------------------------- -- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- or_muxcy_f ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: or_muxcy_f.vhd -- -- Description: -- (Note: It is recommended to use this module sparingly. -- XST synthesis inferral of reduction-OR functionality -- has progressed to where a carry-chain implementation -- will be selected if it has advantages. At the same -- time, if a rigid carry chain structure is not imposed, -- XST has more degrees of freedom for optimization. -- -- This module can be used to get an inferred implementation -- by specifying C_FAMILY = "nofamily", which is the default -- value of this Generic. It is equally possible to use -- a reduction-or function (see or_reduce, below, for an -- example) instead of this module. -- -- If however the designer wants without compromise -- a structural carry-chain implementation, then this -- module can be used with C_FAMILY set to the target -- Xilinx FPGA family. -- -- End of Note. -- ) -- -- -- Or_out <= or_reduce(In_bus) -- -- i.e., OR together the bits in In_bus and assign to Or_out. -- -- The implementation uses a single LUT if possible. -- Otherwise, if C_FAMILY supports the carry chain concept, -- it uses a minimal number of LUTs on a carry chain. -- The native LUT size of C_FAMILY is taken into account. -- ------------------------------------------------------------------------------- -- Structure: Common use module ------------------------------------------------------------------------------- -- Author: FLO -- History: -- FLO 07/06/06 -- First version - derived from or_with_enable_f -- ~~~~~~ -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- entity or_muxcy_f is generic ( C_NUM_BITS : integer; C_FAMILY : string := "nofamily" ); port ( In_bus : in std_logic_vector(0 to C_NUM_BITS-1); Or_out : out std_logic ); end or_muxcy_f; library proc_common_v4_0; use proc_common_v4_0.family_support.all; -- Makes visible the function 'supported' and related types, -- including enumeration literals for the unisim primitives (e.g. -- the "u_" prefixed identifiers such as u_MUXCY, u_LUT4, etc.). library unisim; use unisim.all; -- Make unisim entities available for default binding. -- architecture implementation of or_muxcy_f is ---------------------------------------------------------------------------- -- Here is determined the largest LUT width supported by the target family. -- If no LUT is supported, the width is set to a very large number, which, -- as things are structured, will cause an inferred implementation -- to be used. ---------------------------------------------------------------------------- constant lut_size : integer := native_lut_size(fam_as_string => C_FAMILY, no_lut_return_val => integer'high); ---------------------------------------------------------------------------- -- Here is determined which structural or inferred implementation to use. ---------------------------------------------------------------------------- constant USE_STRUCTURAL_A : boolean := supported(C_FAMILY, u_MUXCY) and In_bus'length > lut_size; -- Structural implementation not needed if the number -- bits to be ORed will fit into a single LUT. constant USE_INFERRED : boolean := not USE_STRUCTURAL_A; ---------------------------------------------------------------------------- -- Reduction OR function. ---------------------------------------------------------------------------- function or_reduce (v : std_logic_vector) return std_logic is variable r : std_logic := '0'; begin for i in v'range loop r := r or v(i); end loop; return r; end; ---------------------------------------------------------------------------- -- Min function. ---------------------------------------------------------------------------- function min (a, b: natural) return natural is begin if (a>b) then return b; else return a; end if; end; ---------------------------------------------------------------------------- -- Signal to recast In_bus into a local array whose index bounds and -- direction are known. ---------------------------------------------------------------------------- signal OB : std_logic_vector(0 to In_bus'length-1); ---------------------------------------------------------------------------- -- Unisim components declared locally for maximum avoidance of default -- binding and vcomponents version issues. ---------------------------------------------------------------------------- component MUXCY port ( O : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end component; begin OB <= In_bus; ---------------------------------------------------------------------------- -- Inferred implementation. ---------------------------------------------------------------------------- INFERRED_GEN : if USE_INFERRED generate begin Or_out <= or_reduce(OB); end generate INFERRED_GEN; ---------------------------------------------------------------------------- -- Structural implementation. ---------------------------------------------------------------------------- STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate constant NUM_LUTS : positive := ((OB'length + lut_size - 1) / lut_size); signal cy : std_logic_vector(0 to NUM_LUTS); begin -- cy(0) <= '0'; -- GEN : for i in 0 to NUM_LUTS-1 generate signal lut : std_logic; begin lut <= not or_reduce(OB(ilut_size to min((i+1)*lut_size-1, OB'right))); -- The min -- function catches the case where one LUT -- is partial (i.e., not all inputs are used). -- I_MUXCY : component MUXCY port map (O =>cy(NUM_LUTS - i), CI=>cy(NUM_LUTS - 1 - i), DI=>'1', S =>lut); -- Note on cy handling: As done here, the partial LUT, if any, -- is placed at the start of the cy chain. end generate; -- Or_out <= cy(NUM_LUTS); -- end generate STRUCTURAL_A_GEN; end implementation;
------------------------------------------------------------------------------- -- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- or_muxcy_f ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: or_muxcy_f.vhd -- -- Description: -- (Note: It is recommended to use this module sparingly. -- XST synthesis inferral of reduction-OR functionality -- has progressed to where a carry-chain implementation -- will be selected if it has advantages. At the same -- time, if a rigid carry chain structure is not imposed, -- XST has more degrees of freedom for optimization. -- -- This module can be used to get an inferred implementation -- by specifying C_FAMILY = "nofamily", which is the default -- value of this Generic. It is equally possible to use -- a reduction-or function (see or_reduce, below, for an -- example) instead of this module. -- -- If however the designer wants without compromise -- a structural carry-chain implementation, then this -- module can be used with C_FAMILY set to the target -- Xilinx FPGA family. -- -- End of Note. -- ) -- -- -- Or_out <= or_reduce(In_bus) -- -- i.e., OR together the bits in In_bus and assign to Or_out. -- -- The implementation uses a single LUT if possible. -- Otherwise, if C_FAMILY supports the carry chain concept, -- it uses a minimal number of LUTs on a carry chain. -- The native LUT size of C_FAMILY is taken into account. -- ------------------------------------------------------------------------------- -- Structure: Common use module ------------------------------------------------------------------------------- -- Author: FLO -- History: -- FLO 07/06/06 -- First version - derived from or_with_enable_f -- ~~~~~~ -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- entity or_muxcy_f is generic ( C_NUM_BITS : integer; C_FAMILY : string := "nofamily" ); port ( In_bus : in std_logic_vector(0 to C_NUM_BITS-1); Or_out : out std_logic ); end or_muxcy_f; library proc_common_v4_0; use proc_common_v4_0.family_support.all; -- Makes visible the function 'supported' and related types, -- including enumeration literals for the unisim primitives (e.g. -- the "u_" prefixed identifiers such as u_MUXCY, u_LUT4, etc.). library unisim; use unisim.all; -- Make unisim entities available for default binding. -- architecture implementation of or_muxcy_f is ---------------------------------------------------------------------------- -- Here is determined the largest LUT width supported by the target family. -- If no LUT is supported, the width is set to a very large number, which, -- as things are structured, will cause an inferred implementation -- to be used. ---------------------------------------------------------------------------- constant lut_size : integer := native_lut_size(fam_as_string => C_FAMILY, no_lut_return_val => integer'high); ---------------------------------------------------------------------------- -- Here is determined which structural or inferred implementation to use. ---------------------------------------------------------------------------- constant USE_STRUCTURAL_A : boolean := supported(C_FAMILY, u_MUXCY) and In_bus'length > lut_size; -- Structural implementation not needed if the number -- bits to be ORed will fit into a single LUT. constant USE_INFERRED : boolean := not USE_STRUCTURAL_A; ---------------------------------------------------------------------------- -- Reduction OR function. ---------------------------------------------------------------------------- function or_reduce (v : std_logic_vector) return std_logic is variable r : std_logic := '0'; begin for i in v'range loop r := r or v(i); end loop; return r; end; ---------------------------------------------------------------------------- -- Min function. ---------------------------------------------------------------------------- function min (a, b: natural) return natural is begin if (a>b) then return b; else return a; end if; end; ---------------------------------------------------------------------------- -- Signal to recast In_bus into a local array whose index bounds and -- direction are known. ---------------------------------------------------------------------------- signal OB : std_logic_vector(0 to In_bus'length-1); ---------------------------------------------------------------------------- -- Unisim components declared locally for maximum avoidance of default -- binding and vcomponents version issues. ---------------------------------------------------------------------------- component MUXCY port ( O : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end component; begin OB <= In_bus; ---------------------------------------------------------------------------- -- Inferred implementation. ---------------------------------------------------------------------------- INFERRED_GEN : if USE_INFERRED generate begin Or_out <= or_reduce(OB); end generate INFERRED_GEN; ---------------------------------------------------------------------------- -- Structural implementation. ---------------------------------------------------------------------------- STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate constant NUM_LUTS : positive := ((OB'length + lut_size - 1) / lut_size); signal cy : std_logic_vector(0 to NUM_LUTS); begin -- cy(0) <= '0'; -- GEN : for i in 0 to NUM_LUTS-1 generate signal lut : std_logic; begin lut <= not or_reduce(OB(ilut_size to min((i+1)*lut_size-1, OB'right))); -- The min -- function catches the case where one LUT -- is partial (i.e., not all inputs are used). -- I_MUXCY : component MUXCY port map (O =>cy(NUM_LUTS - i), CI=>cy(NUM_LUTS - 1 - i), DI=>'1', S =>lut); -- Note on cy handling: As done here, the partial LUT, if any, -- is placed at the start of the cy chain. end generate; -- Or_out <= cy(NUM_LUTS); -- end generate STRUCTURAL_A_GEN; end implementation;
------------------------------------------------------------------------------- -- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- or_muxcy_f ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: or_muxcy_f.vhd -- -- Description: -- (Note: It is recommended to use this module sparingly. -- XST synthesis inferral of reduction-OR functionality -- has progressed to where a carry-chain implementation -- will be selected if it has advantages. At the same -- time, if a rigid carry chain structure is not imposed, -- XST has more degrees of freedom for optimization. -- -- This module can be used to get an inferred implementation -- by specifying C_FAMILY = "nofamily", which is the default -- value of this Generic. It is equally possible to use -- a reduction-or function (see or_reduce, below, for an -- example) instead of this module. -- -- If however the designer wants without compromise -- a structural carry-chain implementation, then this -- module can be used with C_FAMILY set to the target -- Xilinx FPGA family. -- -- End of Note. -- ) -- -- -- Or_out <= or_reduce(In_bus) -- -- i.e., OR together the bits in In_bus and assign to Or_out. -- -- The implementation uses a single LUT if possible. -- Otherwise, if C_FAMILY supports the carry chain concept, -- it uses a minimal number of LUTs on a carry chain. -- The native LUT size of C_FAMILY is taken into account. -- ------------------------------------------------------------------------------- -- Structure: Common use module ------------------------------------------------------------------------------- -- Author: FLO -- History: -- FLO 07/06/06 -- First version - derived from or_with_enable_f -- ~~~~~~ -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- entity or_muxcy_f is generic ( C_NUM_BITS : integer; C_FAMILY : string := "nofamily" ); port ( In_bus : in std_logic_vector(0 to C_NUM_BITS-1); Or_out : out std_logic ); end or_muxcy_f; library proc_common_v4_0; use proc_common_v4_0.family_support.all; -- Makes visible the function 'supported' and related types, -- including enumeration literals for the unisim primitives (e.g. -- the "u_" prefixed identifiers such as u_MUXCY, u_LUT4, etc.). library unisim; use unisim.all; -- Make unisim entities available for default binding. -- architecture implementation of or_muxcy_f is ---------------------------------------------------------------------------- -- Here is determined the largest LUT width supported by the target family. -- If no LUT is supported, the width is set to a very large number, which, -- as things are structured, will cause an inferred implementation -- to be used. ---------------------------------------------------------------------------- constant lut_size : integer := native_lut_size(fam_as_string => C_FAMILY, no_lut_return_val => integer'high); ---------------------------------------------------------------------------- -- Here is determined which structural or inferred implementation to use. ---------------------------------------------------------------------------- constant USE_STRUCTURAL_A : boolean := supported(C_FAMILY, u_MUXCY) and In_bus'length > lut_size; -- Structural implementation not needed if the number -- bits to be ORed will fit into a single LUT. constant USE_INFERRED : boolean := not USE_STRUCTURAL_A; ---------------------------------------------------------------------------- -- Reduction OR function. ---------------------------------------------------------------------------- function or_reduce (v : std_logic_vector) return std_logic is variable r : std_logic := '0'; begin for i in v'range loop r := r or v(i); end loop; return r; end; ---------------------------------------------------------------------------- -- Min function. ---------------------------------------------------------------------------- function min (a, b: natural) return natural is begin if (a>b) then return b; else return a; end if; end; ---------------------------------------------------------------------------- -- Signal to recast In_bus into a local array whose index bounds and -- direction are known. ---------------------------------------------------------------------------- signal OB : std_logic_vector(0 to In_bus'length-1); ---------------------------------------------------------------------------- -- Unisim components declared locally for maximum avoidance of default -- binding and vcomponents version issues. ---------------------------------------------------------------------------- component MUXCY port ( O : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end component; begin OB <= In_bus; ---------------------------------------------------------------------------- -- Inferred implementation. ---------------------------------------------------------------------------- INFERRED_GEN : if USE_INFERRED generate begin Or_out <= or_reduce(OB); end generate INFERRED_GEN; ---------------------------------------------------------------------------- -- Structural implementation. ---------------------------------------------------------------------------- STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate constant NUM_LUTS : positive := ((OB'length + lut_size - 1) / lut_size); signal cy : std_logic_vector(0 to NUM_LUTS); begin -- cy(0) <= '0'; -- GEN : for i in 0 to NUM_LUTS-1 generate signal lut : std_logic; begin lut <= not or_reduce(OB(ilut_size to min((i+1)*lut_size-1, OB'right))); -- The min -- function catches the case where one LUT -- is partial (i.e., not all inputs are used). -- I_MUXCY : component MUXCY port map (O =>cy(NUM_LUTS - i), CI=>cy(NUM_LUTS - 1 - i), DI=>'1', S =>lut); -- Note on cy handling: As done here, the partial LUT, if any, -- is placed at the start of the cy chain. end generate; -- Or_out <= cy(NUM_LUTS); -- end generate STRUCTURAL_A_GEN; end implementation;
------------------------------------------------------------------------------- -- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- or_muxcy_f ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: or_muxcy_f.vhd -- -- Description: -- (Note: It is recommended to use this module sparingly. -- XST synthesis inferral of reduction-OR functionality -- has progressed to where a carry-chain implementation -- will be selected if it has advantages. At the same -- time, if a rigid carry chain structure is not imposed, -- XST has more degrees of freedom for optimization. -- -- This module can be used to get an inferred implementation -- by specifying C_FAMILY = "nofamily", which is the default -- value of this Generic. It is equally possible to use -- a reduction-or function (see or_reduce, below, for an -- example) instead of this module. -- -- If however the designer wants without compromise -- a structural carry-chain implementation, then this -- module can be used with C_FAMILY set to the target -- Xilinx FPGA family. -- -- End of Note. -- ) -- -- -- Or_out <= or_reduce(In_bus) -- -- i.e., OR together the bits in In_bus and assign to Or_out. -- -- The implementation uses a single LUT if possible. -- Otherwise, if C_FAMILY supports the carry chain concept, -- it uses a minimal number of LUTs on a carry chain. -- The native LUT size of C_FAMILY is taken into account. -- ------------------------------------------------------------------------------- -- Structure: Common use module ------------------------------------------------------------------------------- -- Author: FLO -- History: -- FLO 07/06/06 -- First version - derived from or_with_enable_f -- ~~~~~~ -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- entity or_muxcy_f is generic ( C_NUM_BITS : integer; C_FAMILY : string := "nofamily" ); port ( In_bus : in std_logic_vector(0 to C_NUM_BITS-1); Or_out : out std_logic ); end or_muxcy_f; library proc_common_v4_0; use proc_common_v4_0.family_support.all; -- Makes visible the function 'supported' and related types, -- including enumeration literals for the unisim primitives (e.g. -- the "u_" prefixed identifiers such as u_MUXCY, u_LUT4, etc.). library unisim; use unisim.all; -- Make unisim entities available for default binding. -- architecture implementation of or_muxcy_f is ---------------------------------------------------------------------------- -- Here is determined the largest LUT width supported by the target family. -- If no LUT is supported, the width is set to a very large number, which, -- as things are structured, will cause an inferred implementation -- to be used. ---------------------------------------------------------------------------- constant lut_size : integer := native_lut_size(fam_as_string => C_FAMILY, no_lut_return_val => integer'high); ---------------------------------------------------------------------------- -- Here is determined which structural or inferred implementation to use. ---------------------------------------------------------------------------- constant USE_STRUCTURAL_A : boolean := supported(C_FAMILY, u_MUXCY) and In_bus'length > lut_size; -- Structural implementation not needed if the number -- bits to be ORed will fit into a single LUT. constant USE_INFERRED : boolean := not USE_STRUCTURAL_A; ---------------------------------------------------------------------------- -- Reduction OR function. ---------------------------------------------------------------------------- function or_reduce (v : std_logic_vector) return std_logic is variable r : std_logic := '0'; begin for i in v'range loop r := r or v(i); end loop; return r; end; ---------------------------------------------------------------------------- -- Min function. ---------------------------------------------------------------------------- function min (a, b: natural) return natural is begin if (a>b) then return b; else return a; end if; end; ---------------------------------------------------------------------------- -- Signal to recast In_bus into a local array whose index bounds and -- direction are known. ---------------------------------------------------------------------------- signal OB : std_logic_vector(0 to In_bus'length-1); ---------------------------------------------------------------------------- -- Unisim components declared locally for maximum avoidance of default -- binding and vcomponents version issues. ---------------------------------------------------------------------------- component MUXCY port ( O : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end component; begin OB <= In_bus; ---------------------------------------------------------------------------- -- Inferred implementation. ---------------------------------------------------------------------------- INFERRED_GEN : if USE_INFERRED generate begin Or_out <= or_reduce(OB); end generate INFERRED_GEN; ---------------------------------------------------------------------------- -- Structural implementation. ---------------------------------------------------------------------------- STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate constant NUM_LUTS : positive := ((OB'length + lut_size - 1) / lut_size); signal cy : std_logic_vector(0 to NUM_LUTS); begin -- cy(0) <= '0'; -- GEN : for i in 0 to NUM_LUTS-1 generate signal lut : std_logic; begin lut <= not or_reduce(OB(ilut_size to min((i+1)*lut_size-1, OB'right))); -- The min -- function catches the case where one LUT -- is partial (i.e., not all inputs are used). -- I_MUXCY : component MUXCY port map (O =>cy(NUM_LUTS - i), CI=>cy(NUM_LUTS - 1 - i), DI=>'1', S =>lut); -- Note on cy handling: As done here, the partial LUT, if any, -- is placed at the start of the cy chain. end generate; -- Or_out <= cy(NUM_LUTS); -- end generate STRUCTURAL_A_GEN; end implementation;
------------------------------------------------------------------------------- -- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- or_muxcy_f ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: or_muxcy_f.vhd -- -- Description: -- (Note: It is recommended to use this module sparingly. -- XST synthesis inferral of reduction-OR functionality -- has progressed to where a carry-chain implementation -- will be selected if it has advantages. At the same -- time, if a rigid carry chain structure is not imposed, -- XST has more degrees of freedom for optimization. -- -- This module can be used to get an inferred implementation -- by specifying C_FAMILY = "nofamily", which is the default -- value of this Generic. It is equally possible to use -- a reduction-or function (see or_reduce, below, for an -- example) instead of this module. -- -- If however the designer wants without compromise -- a structural carry-chain implementation, then this -- module can be used with C_FAMILY set to the target -- Xilinx FPGA family. -- -- End of Note. -- ) -- -- -- Or_out <= or_reduce(In_bus) -- -- i.e., OR together the bits in In_bus and assign to Or_out. -- -- The implementation uses a single LUT if possible. -- Otherwise, if C_FAMILY supports the carry chain concept, -- it uses a minimal number of LUTs on a carry chain. -- The native LUT size of C_FAMILY is taken into account. -- ------------------------------------------------------------------------------- -- Structure: Common use module ------------------------------------------------------------------------------- -- Author: FLO -- History: -- FLO 07/06/06 -- First version - derived from or_with_enable_f -- ~~~~~~ -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- entity or_muxcy_f is generic ( C_NUM_BITS : integer; C_FAMILY : string := "nofamily" ); port ( In_bus : in std_logic_vector(0 to C_NUM_BITS-1); Or_out : out std_logic ); end or_muxcy_f; library proc_common_v4_0; use proc_common_v4_0.family_support.all; -- Makes visible the function 'supported' and related types, -- including enumeration literals for the unisim primitives (e.g. -- the "u_" prefixed identifiers such as u_MUXCY, u_LUT4, etc.). library unisim; use unisim.all; -- Make unisim entities available for default binding. -- architecture implementation of or_muxcy_f is ---------------------------------------------------------------------------- -- Here is determined the largest LUT width supported by the target family. -- If no LUT is supported, the width is set to a very large number, which, -- as things are structured, will cause an inferred implementation -- to be used. ---------------------------------------------------------------------------- constant lut_size : integer := native_lut_size(fam_as_string => C_FAMILY, no_lut_return_val => integer'high); ---------------------------------------------------------------------------- -- Here is determined which structural or inferred implementation to use. ---------------------------------------------------------------------------- constant USE_STRUCTURAL_A : boolean := supported(C_FAMILY, u_MUXCY) and In_bus'length > lut_size; -- Structural implementation not needed if the number -- bits to be ORed will fit into a single LUT. constant USE_INFERRED : boolean := not USE_STRUCTURAL_A; ---------------------------------------------------------------------------- -- Reduction OR function. ---------------------------------------------------------------------------- function or_reduce (v : std_logic_vector) return std_logic is variable r : std_logic := '0'; begin for i in v'range loop r := r or v(i); end loop; return r; end; ---------------------------------------------------------------------------- -- Min function. ---------------------------------------------------------------------------- function min (a, b: natural) return natural is begin if (a>b) then return b; else return a; end if; end; ---------------------------------------------------------------------------- -- Signal to recast In_bus into a local array whose index bounds and -- direction are known. ---------------------------------------------------------------------------- signal OB : std_logic_vector(0 to In_bus'length-1); ---------------------------------------------------------------------------- -- Unisim components declared locally for maximum avoidance of default -- binding and vcomponents version issues. ---------------------------------------------------------------------------- component MUXCY port ( O : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end component; begin OB <= In_bus; ---------------------------------------------------------------------------- -- Inferred implementation. ---------------------------------------------------------------------------- INFERRED_GEN : if USE_INFERRED generate begin Or_out <= or_reduce(OB); end generate INFERRED_GEN; ---------------------------------------------------------------------------- -- Structural implementation. ---------------------------------------------------------------------------- STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate constant NUM_LUTS : positive := ((OB'length + lut_size - 1) / lut_size); signal cy : std_logic_vector(0 to NUM_LUTS); begin -- cy(0) <= '0'; -- GEN : for i in 0 to NUM_LUTS-1 generate signal lut : std_logic; begin lut <= not or_reduce(OB(ilut_size to min((i+1)*lut_size-1, OB'right))); -- The min -- function catches the case where one LUT -- is partial (i.e., not all inputs are used). -- I_MUXCY : component MUXCY port map (O =>cy(NUM_LUTS - i), CI=>cy(NUM_LUTS - 1 - i), DI=>'1', S =>lut); -- Note on cy handling: As done here, the partial LUT, if any, -- is placed at the start of the cy chain. end generate; -- Or_out <= cy(NUM_LUTS); -- end generate STRUCTURAL_A_GEN; end implementation;
------------------------------------------------------------------------------- -- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- or_muxcy_f ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: or_muxcy_f.vhd -- -- Description: -- (Note: It is recommended to use this module sparingly. -- XST synthesis inferral of reduction-OR functionality -- has progressed to where a carry-chain implementation -- will be selected if it has advantages. At the same -- time, if a rigid carry chain structure is not imposed, -- XST has more degrees of freedom for optimization. -- -- This module can be used to get an inferred implementation -- by specifying C_FAMILY = "nofamily", which is the default -- value of this Generic. It is equally possible to use -- a reduction-or function (see or_reduce, below, for an -- example) instead of this module. -- -- If however the designer wants without compromise -- a structural carry-chain implementation, then this -- module can be used with C_FAMILY set to the target -- Xilinx FPGA family. -- -- End of Note. -- ) -- -- -- Or_out <= or_reduce(In_bus) -- -- i.e., OR together the bits in In_bus and assign to Or_out. -- -- The implementation uses a single LUT if possible. -- Otherwise, if C_FAMILY supports the carry chain concept, -- it uses a minimal number of LUTs on a carry chain. -- The native LUT size of C_FAMILY is taken into account. -- ------------------------------------------------------------------------------- -- Structure: Common use module ------------------------------------------------------------------------------- -- Author: FLO -- History: -- FLO 07/06/06 -- First version - derived from or_with_enable_f -- ~~~~~~ -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- entity or_muxcy_f is generic ( C_NUM_BITS : integer; C_FAMILY : string := "nofamily" ); port ( In_bus : in std_logic_vector(0 to C_NUM_BITS-1); Or_out : out std_logic ); end or_muxcy_f; library proc_common_v4_0; use proc_common_v4_0.family_support.all; -- Makes visible the function 'supported' and related types, -- including enumeration literals for the unisim primitives (e.g. -- the "u_" prefixed identifiers such as u_MUXCY, u_LUT4, etc.). library unisim; use unisim.all; -- Make unisim entities available for default binding. -- architecture implementation of or_muxcy_f is ---------------------------------------------------------------------------- -- Here is determined the largest LUT width supported by the target family. -- If no LUT is supported, the width is set to a very large number, which, -- as things are structured, will cause an inferred implementation -- to be used. ---------------------------------------------------------------------------- constant lut_size : integer := native_lut_size(fam_as_string => C_FAMILY, no_lut_return_val => integer'high); ---------------------------------------------------------------------------- -- Here is determined which structural or inferred implementation to use. ---------------------------------------------------------------------------- constant USE_STRUCTURAL_A : boolean := supported(C_FAMILY, u_MUXCY) and In_bus'length > lut_size; -- Structural implementation not needed if the number -- bits to be ORed will fit into a single LUT. constant USE_INFERRED : boolean := not USE_STRUCTURAL_A; ---------------------------------------------------------------------------- -- Reduction OR function. ---------------------------------------------------------------------------- function or_reduce (v : std_logic_vector) return std_logic is variable r : std_logic := '0'; begin for i in v'range loop r := r or v(i); end loop; return r; end; ---------------------------------------------------------------------------- -- Min function. ---------------------------------------------------------------------------- function min (a, b: natural) return natural is begin if (a>b) then return b; else return a; end if; end; ---------------------------------------------------------------------------- -- Signal to recast In_bus into a local array whose index bounds and -- direction are known. ---------------------------------------------------------------------------- signal OB : std_logic_vector(0 to In_bus'length-1); ---------------------------------------------------------------------------- -- Unisim components declared locally for maximum avoidance of default -- binding and vcomponents version issues. ---------------------------------------------------------------------------- component MUXCY port ( O : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end component; begin OB <= In_bus; ---------------------------------------------------------------------------- -- Inferred implementation. ---------------------------------------------------------------------------- INFERRED_GEN : if USE_INFERRED generate begin Or_out <= or_reduce(OB); end generate INFERRED_GEN; ---------------------------------------------------------------------------- -- Structural implementation. ---------------------------------------------------------------------------- STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate constant NUM_LUTS : positive := ((OB'length + lut_size - 1) / lut_size); signal cy : std_logic_vector(0 to NUM_LUTS); begin -- cy(0) <= '0'; -- GEN : for i in 0 to NUM_LUTS-1 generate signal lut : std_logic; begin lut <= not or_reduce(OB(ilut_size to min((i+1)*lut_size-1, OB'right))); -- The min -- function catches the case where one LUT -- is partial (i.e., not all inputs are used). -- I_MUXCY : component MUXCY port map (O =>cy(NUM_LUTS - i), CI=>cy(NUM_LUTS - 1 - i), DI=>'1', S =>lut); -- Note on cy handling: As done here, the partial LUT, if any, -- is placed at the start of the cy chain. end generate; -- Or_out <= cy(NUM_LUTS); -- end generate STRUCTURAL_A_GEN; end implementation;
------------------------------------------------------------------------------- -- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- or_muxcy_f ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: or_muxcy_f.vhd -- -- Description: -- (Note: It is recommended to use this module sparingly. -- XST synthesis inferral of reduction-OR functionality -- has progressed to where a carry-chain implementation -- will be selected if it has advantages. At the same -- time, if a rigid carry chain structure is not imposed, -- XST has more degrees of freedom for optimization. -- -- This module can be used to get an inferred implementation -- by specifying C_FAMILY = "nofamily", which is the default -- value of this Generic. It is equally possible to use -- a reduction-or function (see or_reduce, below, for an -- example) instead of this module. -- -- If however the designer wants without compromise -- a structural carry-chain implementation, then this -- module can be used with C_FAMILY set to the target -- Xilinx FPGA family. -- -- End of Note. -- ) -- -- -- Or_out <= or_reduce(In_bus) -- -- i.e., OR together the bits in In_bus and assign to Or_out. -- -- The implementation uses a single LUT if possible. -- Otherwise, if C_FAMILY supports the carry chain concept, -- it uses a minimal number of LUTs on a carry chain. -- The native LUT size of C_FAMILY is taken into account. -- ------------------------------------------------------------------------------- -- Structure: Common use module ------------------------------------------------------------------------------- -- Author: FLO -- History: -- FLO 07/06/06 -- First version - derived from or_with_enable_f -- ~~~~~~ -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- entity or_muxcy_f is generic ( C_NUM_BITS : integer; C_FAMILY : string := "nofamily" ); port ( In_bus : in std_logic_vector(0 to C_NUM_BITS-1); Or_out : out std_logic ); end or_muxcy_f; library proc_common_v4_0; use proc_common_v4_0.family_support.all; -- Makes visible the function 'supported' and related types, -- including enumeration literals for the unisim primitives (e.g. -- the "u_" prefixed identifiers such as u_MUXCY, u_LUT4, etc.). library unisim; use unisim.all; -- Make unisim entities available for default binding. -- architecture implementation of or_muxcy_f is ---------------------------------------------------------------------------- -- Here is determined the largest LUT width supported by the target family. -- If no LUT is supported, the width is set to a very large number, which, -- as things are structured, will cause an inferred implementation -- to be used. ---------------------------------------------------------------------------- constant lut_size : integer := native_lut_size(fam_as_string => C_FAMILY, no_lut_return_val => integer'high); ---------------------------------------------------------------------------- -- Here is determined which structural or inferred implementation to use. ---------------------------------------------------------------------------- constant USE_STRUCTURAL_A : boolean := supported(C_FAMILY, u_MUXCY) and In_bus'length > lut_size; -- Structural implementation not needed if the number -- bits to be ORed will fit into a single LUT. constant USE_INFERRED : boolean := not USE_STRUCTURAL_A; ---------------------------------------------------------------------------- -- Reduction OR function. ---------------------------------------------------------------------------- function or_reduce (v : std_logic_vector) return std_logic is variable r : std_logic := '0'; begin for i in v'range loop r := r or v(i); end loop; return r; end; ---------------------------------------------------------------------------- -- Min function. ---------------------------------------------------------------------------- function min (a, b: natural) return natural is begin if (a>b) then return b; else return a; end if; end; ---------------------------------------------------------------------------- -- Signal to recast In_bus into a local array whose index bounds and -- direction are known. ---------------------------------------------------------------------------- signal OB : std_logic_vector(0 to In_bus'length-1); ---------------------------------------------------------------------------- -- Unisim components declared locally for maximum avoidance of default -- binding and vcomponents version issues. ---------------------------------------------------------------------------- component MUXCY port ( O : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end component; begin OB <= In_bus; ---------------------------------------------------------------------------- -- Inferred implementation. ---------------------------------------------------------------------------- INFERRED_GEN : if USE_INFERRED generate begin Or_out <= or_reduce(OB); end generate INFERRED_GEN; ---------------------------------------------------------------------------- -- Structural implementation. ---------------------------------------------------------------------------- STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate constant NUM_LUTS : positive := ((OB'length + lut_size - 1) / lut_size); signal cy : std_logic_vector(0 to NUM_LUTS); begin -- cy(0) <= '0'; -- GEN : for i in 0 to NUM_LUTS-1 generate signal lut : std_logic; begin lut <= not or_reduce(OB(ilut_size to min((i+1)*lut_size-1, OB'right))); -- The min -- function catches the case where one LUT -- is partial (i.e., not all inputs are used). -- I_MUXCY : component MUXCY port map (O =>cy(NUM_LUTS - i), CI=>cy(NUM_LUTS - 1 - i), DI=>'1', S =>lut); -- Note on cy handling: As done here, the partial LUT, if any, -- is placed at the start of the cy chain. end generate; -- Or_out <= cy(NUM_LUTS); -- end generate STRUCTURAL_A_GEN; end implementation;
------------------------------------------------------------------------------- -- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- or_muxcy_f ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: or_muxcy_f.vhd -- -- Description: -- (Note: It is recommended to use this module sparingly. -- XST synthesis inferral of reduction-OR functionality -- has progressed to where a carry-chain implementation -- will be selected if it has advantages. At the same -- time, if a rigid carry chain structure is not imposed, -- XST has more degrees of freedom for optimization. -- -- This module can be used to get an inferred implementation -- by specifying C_FAMILY = "nofamily", which is the default -- value of this Generic. It is equally possible to use -- a reduction-or function (see or_reduce, below, for an -- example) instead of this module. -- -- If however the designer wants without compromise -- a structural carry-chain implementation, then this -- module can be used with C_FAMILY set to the target -- Xilinx FPGA family. -- -- End of Note. -- ) -- -- -- Or_out <= or_reduce(In_bus) -- -- i.e., OR together the bits in In_bus and assign to Or_out. -- -- The implementation uses a single LUT if possible. -- Otherwise, if C_FAMILY supports the carry chain concept, -- it uses a minimal number of LUTs on a carry chain. -- The native LUT size of C_FAMILY is taken into account. -- ------------------------------------------------------------------------------- -- Structure: Common use module ------------------------------------------------------------------------------- -- Author: FLO -- History: -- FLO 07/06/06 -- First version - derived from or_with_enable_f -- ~~~~~~ -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- entity or_muxcy_f is generic ( C_NUM_BITS : integer; C_FAMILY : string := "nofamily" ); port ( In_bus : in std_logic_vector(0 to C_NUM_BITS-1); Or_out : out std_logic ); end or_muxcy_f; library proc_common_v4_0; use proc_common_v4_0.family_support.all; -- Makes visible the function 'supported' and related types, -- including enumeration literals for the unisim primitives (e.g. -- the "u_" prefixed identifiers such as u_MUXCY, u_LUT4, etc.). library unisim; use unisim.all; -- Make unisim entities available for default binding. -- architecture implementation of or_muxcy_f is ---------------------------------------------------------------------------- -- Here is determined the largest LUT width supported by the target family. -- If no LUT is supported, the width is set to a very large number, which, -- as things are structured, will cause an inferred implementation -- to be used. ---------------------------------------------------------------------------- constant lut_size : integer := native_lut_size(fam_as_string => C_FAMILY, no_lut_return_val => integer'high); ---------------------------------------------------------------------------- -- Here is determined which structural or inferred implementation to use. ---------------------------------------------------------------------------- constant USE_STRUCTURAL_A : boolean := supported(C_FAMILY, u_MUXCY) and In_bus'length > lut_size; -- Structural implementation not needed if the number -- bits to be ORed will fit into a single LUT. constant USE_INFERRED : boolean := not USE_STRUCTURAL_A; ---------------------------------------------------------------------------- -- Reduction OR function. ---------------------------------------------------------------------------- function or_reduce (v : std_logic_vector) return std_logic is variable r : std_logic := '0'; begin for i in v'range loop r := r or v(i); end loop; return r; end; ---------------------------------------------------------------------------- -- Min function. ---------------------------------------------------------------------------- function min (a, b: natural) return natural is begin if (a>b) then return b; else return a; end if; end; ---------------------------------------------------------------------------- -- Signal to recast In_bus into a local array whose index bounds and -- direction are known. ---------------------------------------------------------------------------- signal OB : std_logic_vector(0 to In_bus'length-1); ---------------------------------------------------------------------------- -- Unisim components declared locally for maximum avoidance of default -- binding and vcomponents version issues. ---------------------------------------------------------------------------- component MUXCY port ( O : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end component; begin OB <= In_bus; ---------------------------------------------------------------------------- -- Inferred implementation. ---------------------------------------------------------------------------- INFERRED_GEN : if USE_INFERRED generate begin Or_out <= or_reduce(OB); end generate INFERRED_GEN; ---------------------------------------------------------------------------- -- Structural implementation. ---------------------------------------------------------------------------- STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate constant NUM_LUTS : positive := ((OB'length + lut_size - 1) / lut_size); signal cy : std_logic_vector(0 to NUM_LUTS); begin -- cy(0) <= '0'; -- GEN : for i in 0 to NUM_LUTS-1 generate signal lut : std_logic; begin lut <= not or_reduce(OB(ilut_size to min((i+1)*lut_size-1, OB'right))); -- The min -- function catches the case where one LUT -- is partial (i.e., not all inputs are used). -- I_MUXCY : component MUXCY port map (O =>cy(NUM_LUTS - i), CI=>cy(NUM_LUTS - 1 - i), DI=>'1', S =>lut); -- Note on cy handling: As done here, the partial LUT, if any, -- is placed at the start of the cy chain. end generate; -- Or_out <= cy(NUM_LUTS); -- end generate STRUCTURAL_A_GEN; end implementation;
------------------------------------------------------------------------------- -- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- or_muxcy_f ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: or_muxcy_f.vhd -- -- Description: -- (Note: It is recommended to use this module sparingly. -- XST synthesis inferral of reduction-OR functionality -- has progressed to where a carry-chain implementation -- will be selected if it has advantages. At the same -- time, if a rigid carry chain structure is not imposed, -- XST has more degrees of freedom for optimization. -- -- This module can be used to get an inferred implementation -- by specifying C_FAMILY = "nofamily", which is the default -- value of this Generic. It is equally possible to use -- a reduction-or function (see or_reduce, below, for an -- example) instead of this module. -- -- If however the designer wants without compromise -- a structural carry-chain implementation, then this -- module can be used with C_FAMILY set to the target -- Xilinx FPGA family. -- -- End of Note. -- ) -- -- -- Or_out <= or_reduce(In_bus) -- -- i.e., OR together the bits in In_bus and assign to Or_out. -- -- The implementation uses a single LUT if possible. -- Otherwise, if C_FAMILY supports the carry chain concept, -- it uses a minimal number of LUTs on a carry chain. -- The native LUT size of C_FAMILY is taken into account. -- ------------------------------------------------------------------------------- -- Structure: Common use module ------------------------------------------------------------------------------- -- Author: FLO -- History: -- FLO 07/06/06 -- First version - derived from or_with_enable_f -- ~~~~~~ -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- entity or_muxcy_f is generic ( C_NUM_BITS : integer; C_FAMILY : string := "nofamily" ); port ( In_bus : in std_logic_vector(0 to C_NUM_BITS-1); Or_out : out std_logic ); end or_muxcy_f; library proc_common_v4_0; use proc_common_v4_0.family_support.all; -- Makes visible the function 'supported' and related types, -- including enumeration literals for the unisim primitives (e.g. -- the "u_" prefixed identifiers such as u_MUXCY, u_LUT4, etc.). library unisim; use unisim.all; -- Make unisim entities available for default binding. -- architecture implementation of or_muxcy_f is ---------------------------------------------------------------------------- -- Here is determined the largest LUT width supported by the target family. -- If no LUT is supported, the width is set to a very large number, which, -- as things are structured, will cause an inferred implementation -- to be used. ---------------------------------------------------------------------------- constant lut_size : integer := native_lut_size(fam_as_string => C_FAMILY, no_lut_return_val => integer'high); ---------------------------------------------------------------------------- -- Here is determined which structural or inferred implementation to use. ---------------------------------------------------------------------------- constant USE_STRUCTURAL_A : boolean := supported(C_FAMILY, u_MUXCY) and In_bus'length > lut_size; -- Structural implementation not needed if the number -- bits to be ORed will fit into a single LUT. constant USE_INFERRED : boolean := not USE_STRUCTURAL_A; ---------------------------------------------------------------------------- -- Reduction OR function. ---------------------------------------------------------------------------- function or_reduce (v : std_logic_vector) return std_logic is variable r : std_logic := '0'; begin for i in v'range loop r := r or v(i); end loop; return r; end; ---------------------------------------------------------------------------- -- Min function. ---------------------------------------------------------------------------- function min (a, b: natural) return natural is begin if (a>b) then return b; else return a; end if; end; ---------------------------------------------------------------------------- -- Signal to recast In_bus into a local array whose index bounds and -- direction are known. ---------------------------------------------------------------------------- signal OB : std_logic_vector(0 to In_bus'length-1); ---------------------------------------------------------------------------- -- Unisim components declared locally for maximum avoidance of default -- binding and vcomponents version issues. ---------------------------------------------------------------------------- component MUXCY port ( O : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end component; begin OB <= In_bus; ---------------------------------------------------------------------------- -- Inferred implementation. ---------------------------------------------------------------------------- INFERRED_GEN : if USE_INFERRED generate begin Or_out <= or_reduce(OB); end generate INFERRED_GEN; ---------------------------------------------------------------------------- -- Structural implementation. ---------------------------------------------------------------------------- STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate constant NUM_LUTS : positive := ((OB'length + lut_size - 1) / lut_size); signal cy : std_logic_vector(0 to NUM_LUTS); begin -- cy(0) <= '0'; -- GEN : for i in 0 to NUM_LUTS-1 generate signal lut : std_logic; begin lut <= not or_reduce(OB(ilut_size to min((i+1)*lut_size-1, OB'right))); -- The min -- function catches the case where one LUT -- is partial (i.e., not all inputs are used). -- I_MUXCY : component MUXCY port map (O =>cy(NUM_LUTS - i), CI=>cy(NUM_LUTS - 1 - i), DI=>'1', S =>lut); -- Note on cy handling: As done here, the partial LUT, if any, -- is placed at the start of the cy chain. end generate; -- Or_out <= cy(NUM_LUTS); -- end generate STRUCTURAL_A_GEN; end implementation;
------------------------------------------------------------------------------- -- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- or_muxcy_f ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: or_muxcy_f.vhd -- -- Description: -- (Note: It is recommended to use this module sparingly. -- XST synthesis inferral of reduction-OR functionality -- has progressed to where a carry-chain implementation -- will be selected if it has advantages. At the same -- time, if a rigid carry chain structure is not imposed, -- XST has more degrees of freedom for optimization. -- -- This module can be used to get an inferred implementation -- by specifying C_FAMILY = "nofamily", which is the default -- value of this Generic. It is equally possible to use -- a reduction-or function (see or_reduce, below, for an -- example) instead of this module. -- -- If however the designer wants without compromise -- a structural carry-chain implementation, then this -- module can be used with C_FAMILY set to the target -- Xilinx FPGA family. -- -- End of Note. -- ) -- -- -- Or_out <= or_reduce(In_bus) -- -- i.e., OR together the bits in In_bus and assign to Or_out. -- -- The implementation uses a single LUT if possible. -- Otherwise, if C_FAMILY supports the carry chain concept, -- it uses a minimal number of LUTs on a carry chain. -- The native LUT size of C_FAMILY is taken into account. -- ------------------------------------------------------------------------------- -- Structure: Common use module ------------------------------------------------------------------------------- -- Author: FLO -- History: -- FLO 07/06/06 -- First version - derived from or_with_enable_f -- ~~~~~~ -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- entity or_muxcy_f is generic ( C_NUM_BITS : integer; C_FAMILY : string := "nofamily" ); port ( In_bus : in std_logic_vector(0 to C_NUM_BITS-1); Or_out : out std_logic ); end or_muxcy_f; library proc_common_v4_0; use proc_common_v4_0.family_support.all; -- Makes visible the function 'supported' and related types, -- including enumeration literals for the unisim primitives (e.g. -- the "u_" prefixed identifiers such as u_MUXCY, u_LUT4, etc.). library unisim; use unisim.all; -- Make unisim entities available for default binding. -- architecture implementation of or_muxcy_f is ---------------------------------------------------------------------------- -- Here is determined the largest LUT width supported by the target family. -- If no LUT is supported, the width is set to a very large number, which, -- as things are structured, will cause an inferred implementation -- to be used. ---------------------------------------------------------------------------- constant lut_size : integer := native_lut_size(fam_as_string => C_FAMILY, no_lut_return_val => integer'high); ---------------------------------------------------------------------------- -- Here is determined which structural or inferred implementation to use. ---------------------------------------------------------------------------- constant USE_STRUCTURAL_A : boolean := supported(C_FAMILY, u_MUXCY) and In_bus'length > lut_size; -- Structural implementation not needed if the number -- bits to be ORed will fit into a single LUT. constant USE_INFERRED : boolean := not USE_STRUCTURAL_A; ---------------------------------------------------------------------------- -- Reduction OR function. ---------------------------------------------------------------------------- function or_reduce (v : std_logic_vector) return std_logic is variable r : std_logic := '0'; begin for i in v'range loop r := r or v(i); end loop; return r; end; ---------------------------------------------------------------------------- -- Min function. ---------------------------------------------------------------------------- function min (a, b: natural) return natural is begin if (a>b) then return b; else return a; end if; end; ---------------------------------------------------------------------------- -- Signal to recast In_bus into a local array whose index bounds and -- direction are known. ---------------------------------------------------------------------------- signal OB : std_logic_vector(0 to In_bus'length-1); ---------------------------------------------------------------------------- -- Unisim components declared locally for maximum avoidance of default -- binding and vcomponents version issues. ---------------------------------------------------------------------------- component MUXCY port ( O : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end component; begin OB <= In_bus; ---------------------------------------------------------------------------- -- Inferred implementation. ---------------------------------------------------------------------------- INFERRED_GEN : if USE_INFERRED generate begin Or_out <= or_reduce(OB); end generate INFERRED_GEN; ---------------------------------------------------------------------------- -- Structural implementation. ---------------------------------------------------------------------------- STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate constant NUM_LUTS : positive := ((OB'length + lut_size - 1) / lut_size); signal cy : std_logic_vector(0 to NUM_LUTS); begin -- cy(0) <= '0'; -- GEN : for i in 0 to NUM_LUTS-1 generate signal lut : std_logic; begin lut <= not or_reduce(OB(ilut_size to min((i+1)*lut_size-1, OB'right))); -- The min -- function catches the case where one LUT -- is partial (i.e., not all inputs are used). -- I_MUXCY : component MUXCY port map (O =>cy(NUM_LUTS - i), CI=>cy(NUM_LUTS - 1 - i), DI=>'1', S =>lut); -- Note on cy handling: As done here, the partial LUT, if any, -- is placed at the start of the cy chain. end generate; -- Or_out <= cy(NUM_LUTS); -- end generate STRUCTURAL_A_GEN; end implementation;
------------------------------------------------------------------------------- -- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- or_muxcy_f ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: or_muxcy_f.vhd -- -- Description: -- (Note: It is recommended to use this module sparingly. -- XST synthesis inferral of reduction-OR functionality -- has progressed to where a carry-chain implementation -- will be selected if it has advantages. At the same -- time, if a rigid carry chain structure is not imposed, -- XST has more degrees of freedom for optimization. -- -- This module can be used to get an inferred implementation -- by specifying C_FAMILY = "nofamily", which is the default -- value of this Generic. It is equally possible to use -- a reduction-or function (see or_reduce, below, for an -- example) instead of this module. -- -- If however the designer wants without compromise -- a structural carry-chain implementation, then this -- module can be used with C_FAMILY set to the target -- Xilinx FPGA family. -- -- End of Note. -- ) -- -- -- Or_out <= or_reduce(In_bus) -- -- i.e., OR together the bits in In_bus and assign to Or_out. -- -- The implementation uses a single LUT if possible. -- Otherwise, if C_FAMILY supports the carry chain concept, -- it uses a minimal number of LUTs on a carry chain. -- The native LUT size of C_FAMILY is taken into account. -- ------------------------------------------------------------------------------- -- Structure: Common use module ------------------------------------------------------------------------------- -- Author: FLO -- History: -- FLO 07/06/06 -- First version - derived from or_with_enable_f -- ~~~~~~ -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- entity or_muxcy_f is generic ( C_NUM_BITS : integer; C_FAMILY : string := "nofamily" ); port ( In_bus : in std_logic_vector(0 to C_NUM_BITS-1); Or_out : out std_logic ); end or_muxcy_f; library proc_common_v4_0; use proc_common_v4_0.family_support.all; -- Makes visible the function 'supported' and related types, -- including enumeration literals for the unisim primitives (e.g. -- the "u_" prefixed identifiers such as u_MUXCY, u_LUT4, etc.). library unisim; use unisim.all; -- Make unisim entities available for default binding. -- architecture implementation of or_muxcy_f is ---------------------------------------------------------------------------- -- Here is determined the largest LUT width supported by the target family. -- If no LUT is supported, the width is set to a very large number, which, -- as things are structured, will cause an inferred implementation -- to be used. ---------------------------------------------------------------------------- constant lut_size : integer := native_lut_size(fam_as_string => C_FAMILY, no_lut_return_val => integer'high); ---------------------------------------------------------------------------- -- Here is determined which structural or inferred implementation to use. ---------------------------------------------------------------------------- constant USE_STRUCTURAL_A : boolean := supported(C_FAMILY, u_MUXCY) and In_bus'length > lut_size; -- Structural implementation not needed if the number -- bits to be ORed will fit into a single LUT. constant USE_INFERRED : boolean := not USE_STRUCTURAL_A; ---------------------------------------------------------------------------- -- Reduction OR function. ---------------------------------------------------------------------------- function or_reduce (v : std_logic_vector) return std_logic is variable r : std_logic := '0'; begin for i in v'range loop r := r or v(i); end loop; return r; end; ---------------------------------------------------------------------------- -- Min function. ---------------------------------------------------------------------------- function min (a, b: natural) return natural is begin if (a>b) then return b; else return a; end if; end; ---------------------------------------------------------------------------- -- Signal to recast In_bus into a local array whose index bounds and -- direction are known. ---------------------------------------------------------------------------- signal OB : std_logic_vector(0 to In_bus'length-1); ---------------------------------------------------------------------------- -- Unisim components declared locally for maximum avoidance of default -- binding and vcomponents version issues. ---------------------------------------------------------------------------- component MUXCY port ( O : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end component; begin OB <= In_bus; ---------------------------------------------------------------------------- -- Inferred implementation. ---------------------------------------------------------------------------- INFERRED_GEN : if USE_INFERRED generate begin Or_out <= or_reduce(OB); end generate INFERRED_GEN; ---------------------------------------------------------------------------- -- Structural implementation. ---------------------------------------------------------------------------- STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate constant NUM_LUTS : positive := ((OB'length + lut_size - 1) / lut_size); signal cy : std_logic_vector(0 to NUM_LUTS); begin -- cy(0) <= '0'; -- GEN : for i in 0 to NUM_LUTS-1 generate signal lut : std_logic; begin lut <= not or_reduce(OB(ilut_size to min((i+1)*lut_size-1, OB'right))); -- The min -- function catches the case where one LUT -- is partial (i.e., not all inputs are used). -- I_MUXCY : component MUXCY port map (O =>cy(NUM_LUTS - i), CI=>cy(NUM_LUTS - 1 - i), DI=>'1', S =>lut); -- Note on cy handling: As done here, the partial LUT, if any, -- is placed at the start of the cy chain. end generate; -- Or_out <= cy(NUM_LUTS); -- end generate STRUCTURAL_A_GEN; end implementation;
--------------------------------------------------------------------------- -- (c) 2013 mark watson -- I am happy for anyone to use this for non-commercial use. -- If my vhdl files are used commercially or otherwise sold, -- please contact me for explicit permission at scrameta (gmail). -- This applies for source and binary form and derived works. --------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.numeric_std.all; ENTITY scandoubler IS GENERIC ( video_bits : integer := 4 ); PORT ( CLK : IN STD_LOGIC; RESET_N : IN STD_LOGIC; VGA : IN STD_LOGIC; COMPOSITE_ON_HSYNC : in std_logic; colour_enable : in std_logic; doubled_enable : in std_logic; scanlines_on : in std_logic := '0'; -- GTIA interface colour_in : in std_logic_vector(7 downto 0); vsync_in : in std_logic; hsync_in : in std_logic; -- TO TV... R : OUT STD_LOGIC_vector(video_bits-1 downto 0); G : OUT STD_LOGIC_vector(video_bits-1 downto 0); B : OUT STD_LOGIC_vector(video_bits-1 downto 0); VSYNC : out std_logic; HSYNC : out std_logic ); END scandoubler; ARCHITECTURE vhdl OF scandoubler IS COMPONENT gtia_palette IS PORT ( ATARI_COLOUR : IN STD_LOGIC_VECTOR(7 downto 0); R_next : OUT STD_LOGIC_VECTOR(7 downto 0); G_next : OUT STD_LOGIC_VECTOR(7 downto 0); B_next : OUT STD_LOGIC_VECTOR(7 downto 0) ); END component; -- component reg_file IS -- generic -- ( -- BYTES : natural := 1; -- WIDTH : natural := 1 -- ); -- PORT -- ( -- CLK : IN STD_LOGIC; -- ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0); -- DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- WR_EN : IN STD_LOGIC; -- -- DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) -- ); -- END component; component scandouble_ram_infer IS PORT ( clock: IN std_logic; data: IN std_logic_vector (7 DOWNTO 0); address: IN integer RANGE 0 to 1824; we: IN std_logic; q: OUT std_logic_vector (7 DOWNTO 0) ); END component; component delay_line IS generic(COUNT : natural := 1); PORT ( CLK : IN STD_LOGIC; SYNC_RESET : IN STD_LOGIC; DATA_IN : IN STD_LOGIC; ENABLE : IN STD_LOGIC; -- i.e. shift on this clock RESET_N : IN STD_LOGIC; DATA_OUT : OUT STD_LOGIC ); END component; signal colour_next : std_logic_vector(7 downto 0); signal colour_reg : std_logic_vector(7 downto 0); signal vsync_next : std_logic; signal vsync_reg : std_logic; signal hsync_next : std_logic; signal hsync_reg : std_logic; signal r_next : std_logic_vector(7 downto 0); signal g_next : std_logic_vector(7 downto 0); signal b_next : std_logic_vector(7 downto 0); signal r_reg : std_logic_vector(7 downto 0); signal g_reg : std_logic_vector(7 downto 0); signal b_reg : std_logic_vector(7 downto 0); signal linea_address : std_logic_vector(10 downto 0); signal linea_write_enable : std_logic; signal linea_out : std_logic_vector(7 downto 0); signal lineb_address : std_logic_vector(10 downto 0); signal lineb_write_enable : std_logic; signal lineb_out : std_logic_vector(7 downto 0); signal input_address_next : std_logic_vector(10 downto 0); signal input_address_reg : std_logic_vector(10 downto 0); signal output_address_next : std_logic_vector(10 downto 0); signal output_address_reg : std_logic_vector(10 downto 0); signal buffer_select_next : std_logic; signal buffer_select_reg : std_logic; signal hsync_in_reg : std_logic; signal vga_hsync_next : std_logic; signal vga_hsync_reg : std_logic; signal vga_hsync_start : std_logic; signal vga_hsync_end : std_logic; signal vga_odd_reg : std_logic; signal vga_odd_next : std_logic; begin -- register process(clk,reset_n) begin if (reset_n = '0') then r_reg <= (others=>'0'); g_reg <= (others=>'0'); b_reg <= (others=>'0'); colour_reg <= (others=>'0'); hsync_reg <= '0'; vsync_reg <= '0'; input_address_reg <= (others=>'0'); output_address_reg <= (others=>'0'); buffer_select_reg <= '0'; vga_hsync_reg <= '0'; vga_odd_reg <= '0'; elsif (clk'event and clk='1') then r_reg <= r_next; g_reg <= g_next; b_reg <= b_next; colour_reg <= colour_next; hsync_reg <= hsync_next; vsync_reg <= vsync_next; input_address_reg <= input_address_next; output_address_reg <= output_address_next; buffer_select_reg <= buffer_select_next; hsync_in_reg <= hsync_in; vga_hsync_reg <= vga_hsync_next; vga_odd_reg <= vga_odd_next; end if; end process; -- TODO - these should use FPGA RAM - at present about 50% of FPGA is taken by these!!! -- linea : reg_file --generic map (BYTES=>456,WIDTH=>9) --port map (clk=>clk,addr=>linea_address,wr_en=>linea_write_enable,data_in=>colour_in,data_out=>linea_out); --lineb : reg_file -- generic map (BYTES=>456,WIDTH=>9) -- port map (clk=>clk,addr=>lineb_address,wr_en=>lineb_write_enable,data_in=>colour_in,data_out=>lineb_out); linea : scandouble_ram_infer port map (clock=>clk,address=>to_integer(unsigned(linea_address)),we=>linea_write_enable,data=>colour_in,q=>linea_out); lineb : scandouble_ram_infer port map (clock=>clk,address=>to_integer(unsigned(lineb_address)),we=>lineb_write_enable,data=>colour_in,q=>lineb_out); -- capture process(input_address_reg,colour_enable,hsync_in,hsync_in_reg,buffer_select_reg) begin input_address_next <= input_address_reg; buffer_select_next <= buffer_select_reg; linea_write_enable <= '0'; lineb_write_enable <= '0'; if (colour_enable = '1') then input_address_next <= std_logic_vector(unsigned(input_address_reg)+1); linea_write_enable <= buffer_select_reg; lineb_write_enable <= not(buffer_select_reg); end if; if (hsync_in = '1' and hsync_in_reg = '0') then input_address_next <= (others=>'0'); buffer_select_next <= not(buffer_select_reg); end if; end process; -- output process(vga_hsync_reg,vga_hsync_end,output_address_reg,doubled_enable,vga_odd_reg) begin output_address_next <= output_address_reg; vga_hsync_start<='0'; vga_hsync_next <= vga_hsync_reg; vga_odd_next <= vga_odd_reg; if (doubled_enable = '1') then output_address_next <= std_logic_vector(unsigned(output_address_reg)+1); if (output_address_reg = "111"&X"1F") then output_address_next <= (others=>'0'); vga_hsync_start <= '1'; vga_hsync_next <= '1'; end if; end if; if (vga_hsync_end = '1') then vga_hsync_next <= '0'; vga_odd_next <= not(vga_odd_reg); end if; end process; linea_address <= input_address_reg when buffer_select_reg='1' else output_address_reg; lineb_address <= input_address_reg when buffer_select_reg='0' else output_address_reg; hsync_delay : delay_line generic map (COUNT=>128) port map(clk=>clk,sync_reset=>'0',data_in=>vga_hsync_start,enable=>doubled_enable,reset_n=>reset_n,data_out=>vga_hsync_end); -- display process(colour_reg,vsync_reg,vga_hsync_reg,hsync_reg,colour_in,vsync_in,hsync_in,colour_enable,doubled_enable,vga,composite_on_hsync,buffer_select_reg,linea_out,lineb_out, scanlines_on, vga_odd_reg) begin colour_next <= colour_reg; vsync_next <= vsync_reg; hsync_next <= hsync_reg; if (vga = '0') then -- non-vga mode - pass through colour_next <= colour_in; vsync_next <= not(vsync_in); --hsync_next <= not(hsync_in or vsync_in); if (composite_on_hsync = '1') then hsync_next <= not(hsync_in xor vsync_in); else hsync_next <= not(hsync_in); end if; else -- vga mode, store all inputs - then play back! if (buffer_select_reg = '0') then if (scanlines_on ='1' and vga_odd_reg='1') then colour_next(7 downto 4) <= linea_out(7 downto 4); colour_next(3) <= '0'; colour_next(2 downto 0) <= linea_out(3 downto 1); else colour_next <= linea_out; end if; else if (scanlines_on ='1' and vga_odd_reg='1') then colour_next(7 downto 4) <= lineb_out(7 downto 4); colour_next(3) <= '0'; colour_next(2 downto 0) <= lineb_out(3 downto 1); else colour_next <= lineb_out; end if; end if; vsync_next <= not(vsync_in); --hsync_next <= not(vga_hsync_reg); if (composite_on_hsync = '1') then hsync_next <= not(vga_hsync_reg xor vsync_in); else hsync_next <= not(vga_hsync_reg); end if; end if; end process; -- colour palette -- Color Value Color Value --Black 0, 0 Medium blue 8, 128 --Rust 1, 16 Dark blue 9, 144 --Red-orange 2, 32 Blue-grey 10, 160 --Dark orange 3, 48 Olive green 11, 176 --Red 4, 64 Medium green 12, 192 --Dk lavender 5, 80 Dark green 13, 208 --Cobalt blue 6, 96 Orange-green 14, 224 --Ultramarine 7, 112 Orange 15, 240 -- from altirra palette1 : entity work.gtia_palette(altirra) port map (ATARI_COLOUR=>colour_reg, R_next=>R_next, G_next=>G_next, B_next=>B_next); -- from lao -- palette2 : entity work.gtia_palette(laoo) -- port map (ATARI_COLOUR=>COLOUR, R_next=>R_next, G_next=>G_next, B_next=>B_next); -- output -- TODO - for DE2, output full 8 bits R <= R_reg(7 downto 8-video_bits); G <= G_reg(7 downto 8-video_bits); B <= B_reg(7 downto 8-video_bits); vsync<=vsync_reg; hsync<=hsync_reg; end vhdl;

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