content stringlengths 1 1.04M ⌀ |
|---|
library verilog;
use verilog.vl_types.all;
entity hazard_detect is
port(
rst_b : in vl_logic;
mask_of_real_read_reg: in vl_logic_vector(2 downto 0);
read_reg_num : in vl_logic;
IDEX_rd_we : in vl_logic;
EXMEM_rd_we : in vl_logic;
... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_1_e
--
-- Generated
-- by: wig
-- on: Wed Nov 30 06:48:17 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MAGIC_global is
PORT (
ADDRESS_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
AD... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MAGIC_global is
PORT (
ADDRESS_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
AD... |
entity arrayop1 is
end entity;
architecture test of arrayop1 is
begin
p1: process is
variable x : bit_vector(1 to 3);
begin
assert x < "000";
wait;
end process;
end architecture;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
entity array1 is
end entity;
architecture test of array1 is
function func return bit_vector;
begin
process is
begin
assert func = "10";
wait;
end process;
end architecture;
|
entity array1 is
end entity;
architecture test of array1 is
function func return bit_vector;
begin
process is
begin
assert func = "10";
wait;
end process;
end architecture;
|
entity array1 is
end entity;
architecture test of array1 is
function func return bit_vector;
begin
process is
begin
assert func = "10";
wait;
end process;
end architecture;
|
entity array1 is
end entity;
architecture test of array1 is
function func return bit_vector;
begin
process is
begin
assert func = "10";
wait;
end process;
end architecture;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
--Módulo para definir instrução armazenada em determinado endereço de MI. A instrução irá seguir para display 7 segmentos
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dec_mi is
generic(N: integer := 7; M: integer := 32);
port(
clk : in std_logic;
SW : in STD_LOGIC_... |
--Módulo para definir instrução armazenada em determinado endereço de MI. A instrução irá seguir para display 7 segmentos
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dec_mi is
generic(N: integer := 7; M: integer := 32);
port(
clk : in std_logic;
SW : in STD_LOGIC_... |
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
--Date : Thu Mar 10 15:45:23 2016
--Host : minmi running 64-bit elementary OS Freya
... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ec_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
--... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity mark1_nov is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(15 downto 0)
);
end mark1_nov;
architecture behaviour of mark1_nov is
constant state1: std_logic_vector(3 downto ... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity mark1_nov is
port(
clock: in std_logic;
input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(15 downto 0)
);
end mark1_nov;
architecture behaviour of mark1_nov is
constant state1: std_logic_vector(3 downto ... |
-- file: timer_tb.vhd
--
-- (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a... |
-- Library statements --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity declaration --
entity half_adder is
port (a, b : in std_logic;
sum, carry_out : out std_logic
);
end dataflow_half_adder;
-- Architecture --
architecture dataflow of half_adder is
begin
sum <= a xor b;
carry_out <= a and b;
end ... |
--generated by V2 synthesiser
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ssegDriver is port (
clk : in std_logic;
rst : in std_logic;
cathode_p : out std_logic_vector(7 downto 0);
anode_p : out std_logic_vector(7 downto 0);
digit1_p : in std_l... |
--generated by V2 synthesiser
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ssegDriver is port (
clk : in std_logic;
rst : in std_logic;
cathode_p : out std_logic_vector(7 downto 0);
anode_p : out std_logic_vector(7 downto 0);
digit1_p : in std_l... |
--generated by V2 synthesiser
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ssegDriver is port (
clk : in std_logic;
rst : in std_logic;
cathode_p : out std_logic_vector(7 downto 0);
anode_p : out std_logic_vector(7 downto 0);
digit1_p : in std_l... |
--generated by V2 synthesiser
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ssegDriver is port (
clk : in std_logic;
rst : in std_logic;
cathode_p : out std_logic_vector(7 downto 0);
anode_p : out std_logic_vector(7 downto 0);
digit1_p : in std_l... |
------------------------------------------------------------------------------
-- Copyright (C) 2007 Jonathon W. Donaldson
-- jwdonal a t opencores DOT org
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
----------------------------------------
-- Register Module : IITB-RISC
-- Author : Titto Thomas
-- Date : 8/3/2014
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reg is
generic (
nbits : integer);
port (
reg_in : in std_logic_vector(nb... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without wa... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
LIBRARY IEEE;
USE STD.TEXTIO.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
--ENTITY DECLARATION
ENTITY TB_CHK_3BIT IS
END ENTITY TB_CHK_3BIT;
--ARCHITECTURE BODY
ARCHITECTURE TEXTIO_WAY OF TB_CHK_3BIT IS
FILE INTEST : TEXT IS IN "TEST_DATA.TXT";
SIGNAL CLK : STD_LOGIC;
SIGNAL RESET : STD_LOGIC;
S... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.memory_map.all;
use work.txt_utils.all;
use work.utils.all;
entity mem is
generic (ROM : string := ""; RAMSIZE : positive := 32);
port(
addr : in addr_t;
din : in word_t;
do... |
library ieee;
use ieee.std_logic_1164.all;
entity rotator_cc is
port (
clk: in std_logic;
reset: in std_logic;
i_data_tdata: in std_logic_vector(31 downto 0);
i_data_tvalid: in std_logic;
i_data_tlast: in std_logic;
i_data_tready: out std_logic;
i_config_tdata: in std_logic_vec... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- dma_arbiter_0.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
... |
-- This source file was created for J-PET project in WFAIS (Jagiellonian University in Cracow)
-- License for distribution outside WFAIS UJ and J-PET project is GPL v 3
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity parser is
Port (
clk_read : in STD_LOGIC;
reset : in STD_LOGIC;
... |
entity crash_entity is end entity;
architecture default of crash_entity is
type foo_t is record
a, b : bit;
end record;
function func return bit is
variable v : foo_t(0 to 1);
begin
return '1';
end function;
begin
end architecture;
|
----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis (christos.bakalis@cern.ch)
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-B... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--###########################################################################
--
-- LOGIC CORE: Control Interface - Top level module
-- MODULE NAME: control_interface()
-- COMPANY: Altera Corporation
-- www.altera.com
--
-- REVISION HISTORY:
--
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:52:27 11/19/2014
-- Design Name:
-- Module Name: pwm - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:52:27 11/19/2014
-- Design Name:
-- Module Name: pwm - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
... |
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEE... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
entity test is
type test1 is (foo);
subtype test2 is test1;
begin end;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_487 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_487;
architecture augh of add_487 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_487 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_487;
architecture augh of add_487 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library ims;
--use ims.coprocessor.all;
entity MMX_EQU_8b is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of MMX_E... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:05:34 11/17/2013
-- Design Name:
-- Module Name: My_Or_948282 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Re... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity data_c... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
----------------------------------------------------------------------------------
-- Company: ITESM CQ
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 12:36:48 10/08/2015
-- Design Name:
-- Module Name: Descending_Decimal_BCD_Counter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool v... |
-------------------------------------------------------------------------------
-- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_muxcy_f
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-... |
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-- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
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-- or_muxcy_f
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-- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
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-- or_muxcy_f
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-- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_muxcy_f
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-- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
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-- or_muxcy_f
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-- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
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-- or_muxcy_f
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-- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
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-- or_muxcy_f
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-- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
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-- or_muxcy_f
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-- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
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-- or_muxcy_f
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-- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
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-- or_muxcy_f
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-- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
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-- or_muxcy_f
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-- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
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-- or_muxcy_f
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-- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
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-- or_muxcy_f
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-------------------------------------------------------------------------------
-- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
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-- or_muxcy_f
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-------------------------------------------------------------------------------
-- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_muxcy_f
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-... |
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and b... |
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