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|---|
-- Does not saturate currently, only provides built in VHDL addition.
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity AdderSat is
generic (
wordLength : natural := 12
);
port (
a : in std_logic_vector(wordLength-1 downto 0);
b : in std_logic_vector(wordLength-1 downto 0);
s : out std_logic_vector(wordLength-1 downto 0)
);
end entity ; -- AdderSat
architecture arch of AdderSat is
begin
s <= std_logic_vector(signed(a) + signed(b));
end architecture ; -- arch |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
signal start2 : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rd_done1,wr_done1 : std_logic;
--signal rd_done2,wr_done2 : std_logic;
signal wrack_1,rdack_1 : std_logic;
--signal wrack_2,rdack_2 : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
signal is_read, is_write : std_logic;
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
--bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
-- else
-- '0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
--bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
-- when (S_AXI_ARVALID='1')
-- else
-- ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
--start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
-- when (state = SM_IDLE)
-- else
-- '0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or (timeout and is_read);
wr_done <= IP2Bus_WrAck or (timeout and is_write);
--wr_done1 <= (not (wrack_1) and IP2Bus_WrAck) or timeout;
--rd_done1 <= (not (rdack_1) and IP2Bus_RdAck) or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v3_0.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start2,
Bus_RNW => bus2ip_rnw_i, --S_AXI_ARVALID,
Bus_RNW_Erly => bus2ip_rnw_i, --S_AXI_ARVALID,
CS_CE_ld_enable => start2,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start2,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
REGISTERING_RESET_P2 : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
-- wrack_1 <= '0';
-- rdack_1 <= '0';
-- wrack_2 <= '0';
-- rdack_2 <= '0';
-- wr_done2 <= '0';
-- rd_done2 <= '0';
bus2ip_rnw_i <= '0';
bus2ip_addr_i <= (others => '0');
start2 <= '0';
else
-- wrack_1 <= IP2Bus_WrAck;
-- rdack_1 <= IP2Bus_RdAck;
-- wrack_2 <= wrack_1;
-- rdack_2 <= rdack_1;
-- wr_done2 <= wr_done1;
-- rd_done2 <= rd_done1;
if (state = SM_IDLE and S_AXI_ARVALID='1') then
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '1';
start2 <= '1';
elsif (state = SM_IDLE and (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1')) then
bus2ip_addr_i <= ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '0';
start2 <= '1';
else
bus2ip_rnw_i <= bus2ip_rnw_i;
bus2ip_addr_i <= bus2ip_addr_i;
start2 <= '0';
end if;
end if;
end if;
end process REGISTERING_RESET_P2;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
is_read <= '0';
is_write <= '0';
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
is_read <='1';
is_write <= '0';
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
is_read <='0';
is_write <= '1';
else
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= '1' when (dpto_cnt = C_DPHASE_TIMEOUT) else '0';
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
signal start2 : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rd_done1,wr_done1 : std_logic;
--signal rd_done2,wr_done2 : std_logic;
signal wrack_1,rdack_1 : std_logic;
--signal wrack_2,rdack_2 : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
signal is_read, is_write : std_logic;
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
--bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
-- else
-- '0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
--bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
-- when (S_AXI_ARVALID='1')
-- else
-- ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
--start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
-- when (state = SM_IDLE)
-- else
-- '0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or (timeout and is_read);
wr_done <= IP2Bus_WrAck or (timeout and is_write);
--wr_done1 <= (not (wrack_1) and IP2Bus_WrAck) or timeout;
--rd_done1 <= (not (rdack_1) and IP2Bus_RdAck) or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v3_0.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start2,
Bus_RNW => bus2ip_rnw_i, --S_AXI_ARVALID,
Bus_RNW_Erly => bus2ip_rnw_i, --S_AXI_ARVALID,
CS_CE_ld_enable => start2,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start2,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
REGISTERING_RESET_P2 : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
-- wrack_1 <= '0';
-- rdack_1 <= '0';
-- wrack_2 <= '0';
-- rdack_2 <= '0';
-- wr_done2 <= '0';
-- rd_done2 <= '0';
bus2ip_rnw_i <= '0';
bus2ip_addr_i <= (others => '0');
start2 <= '0';
else
-- wrack_1 <= IP2Bus_WrAck;
-- rdack_1 <= IP2Bus_RdAck;
-- wrack_2 <= wrack_1;
-- rdack_2 <= rdack_1;
-- wr_done2 <= wr_done1;
-- rd_done2 <= rd_done1;
if (state = SM_IDLE and S_AXI_ARVALID='1') then
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '1';
start2 <= '1';
elsif (state = SM_IDLE and (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1')) then
bus2ip_addr_i <= ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '0';
start2 <= '1';
else
bus2ip_rnw_i <= bus2ip_rnw_i;
bus2ip_addr_i <= bus2ip_addr_i;
start2 <= '0';
end if;
end if;
end if;
end process REGISTERING_RESET_P2;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
is_read <= '0';
is_write <= '0';
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
is_read <='1';
is_write <= '0';
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
is_read <='0';
is_write <= '1';
else
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= '1' when (dpto_cnt = C_DPHASE_TIMEOUT) else '0';
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
signal start2 : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rd_done1,wr_done1 : std_logic;
--signal rd_done2,wr_done2 : std_logic;
signal wrack_1,rdack_1 : std_logic;
--signal wrack_2,rdack_2 : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
signal is_read, is_write : std_logic;
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
--bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
-- else
-- '0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
--bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
-- when (S_AXI_ARVALID='1')
-- else
-- ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
--start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
-- when (state = SM_IDLE)
-- else
-- '0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or (timeout and is_read);
wr_done <= IP2Bus_WrAck or (timeout and is_write);
--wr_done1 <= (not (wrack_1) and IP2Bus_WrAck) or timeout;
--rd_done1 <= (not (rdack_1) and IP2Bus_RdAck) or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v3_0.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start2,
Bus_RNW => bus2ip_rnw_i, --S_AXI_ARVALID,
Bus_RNW_Erly => bus2ip_rnw_i, --S_AXI_ARVALID,
CS_CE_ld_enable => start2,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start2,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
REGISTERING_RESET_P2 : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
-- wrack_1 <= '0';
-- rdack_1 <= '0';
-- wrack_2 <= '0';
-- rdack_2 <= '0';
-- wr_done2 <= '0';
-- rd_done2 <= '0';
bus2ip_rnw_i <= '0';
bus2ip_addr_i <= (others => '0');
start2 <= '0';
else
-- wrack_1 <= IP2Bus_WrAck;
-- rdack_1 <= IP2Bus_RdAck;
-- wrack_2 <= wrack_1;
-- rdack_2 <= rdack_1;
-- wr_done2 <= wr_done1;
-- rd_done2 <= rd_done1;
if (state = SM_IDLE and S_AXI_ARVALID='1') then
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '1';
start2 <= '1';
elsif (state = SM_IDLE and (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1')) then
bus2ip_addr_i <= ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '0';
start2 <= '1';
else
bus2ip_rnw_i <= bus2ip_rnw_i;
bus2ip_addr_i <= bus2ip_addr_i;
start2 <= '0';
end if;
end if;
end if;
end process REGISTERING_RESET_P2;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
is_read <= '0';
is_write <= '0';
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
is_read <='1';
is_write <= '0';
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
is_read <='0';
is_write <= '1';
else
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= '1' when (dpto_cnt = C_DPHASE_TIMEOUT) else '0';
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
signal start2 : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rd_done1,wr_done1 : std_logic;
--signal rd_done2,wr_done2 : std_logic;
signal wrack_1,rdack_1 : std_logic;
--signal wrack_2,rdack_2 : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
signal is_read, is_write : std_logic;
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
--bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
-- else
-- '0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
--bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
-- when (S_AXI_ARVALID='1')
-- else
-- ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
--start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
-- when (state = SM_IDLE)
-- else
-- '0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or (timeout and is_read);
wr_done <= IP2Bus_WrAck or (timeout and is_write);
--wr_done1 <= (not (wrack_1) and IP2Bus_WrAck) or timeout;
--rd_done1 <= (not (rdack_1) and IP2Bus_RdAck) or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v3_0.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start2,
Bus_RNW => bus2ip_rnw_i, --S_AXI_ARVALID,
Bus_RNW_Erly => bus2ip_rnw_i, --S_AXI_ARVALID,
CS_CE_ld_enable => start2,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start2,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
REGISTERING_RESET_P2 : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
-- wrack_1 <= '0';
-- rdack_1 <= '0';
-- wrack_2 <= '0';
-- rdack_2 <= '0';
-- wr_done2 <= '0';
-- rd_done2 <= '0';
bus2ip_rnw_i <= '0';
bus2ip_addr_i <= (others => '0');
start2 <= '0';
else
-- wrack_1 <= IP2Bus_WrAck;
-- rdack_1 <= IP2Bus_RdAck;
-- wrack_2 <= wrack_1;
-- rdack_2 <= rdack_1;
-- wr_done2 <= wr_done1;
-- rd_done2 <= rd_done1;
if (state = SM_IDLE and S_AXI_ARVALID='1') then
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '1';
start2 <= '1';
elsif (state = SM_IDLE and (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1')) then
bus2ip_addr_i <= ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '0';
start2 <= '1';
else
bus2ip_rnw_i <= bus2ip_rnw_i;
bus2ip_addr_i <= bus2ip_addr_i;
start2 <= '0';
end if;
end if;
end if;
end process REGISTERING_RESET_P2;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
is_read <= '0';
is_write <= '0';
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
is_read <='1';
is_write <= '0';
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
is_read <='0';
is_write <= '1';
else
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= '1' when (dpto_cnt = C_DPHASE_TIMEOUT) else '0';
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
signal start2 : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rd_done1,wr_done1 : std_logic;
--signal rd_done2,wr_done2 : std_logic;
signal wrack_1,rdack_1 : std_logic;
--signal wrack_2,rdack_2 : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
signal is_read, is_write : std_logic;
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
--bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
-- else
-- '0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
--bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
-- when (S_AXI_ARVALID='1')
-- else
-- ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
--start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
-- when (state = SM_IDLE)
-- else
-- '0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or (timeout and is_read);
wr_done <= IP2Bus_WrAck or (timeout and is_write);
--wr_done1 <= (not (wrack_1) and IP2Bus_WrAck) or timeout;
--rd_done1 <= (not (rdack_1) and IP2Bus_RdAck) or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v3_0.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start2,
Bus_RNW => bus2ip_rnw_i, --S_AXI_ARVALID,
Bus_RNW_Erly => bus2ip_rnw_i, --S_AXI_ARVALID,
CS_CE_ld_enable => start2,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start2,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
REGISTERING_RESET_P2 : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
-- wrack_1 <= '0';
-- rdack_1 <= '0';
-- wrack_2 <= '0';
-- rdack_2 <= '0';
-- wr_done2 <= '0';
-- rd_done2 <= '0';
bus2ip_rnw_i <= '0';
bus2ip_addr_i <= (others => '0');
start2 <= '0';
else
-- wrack_1 <= IP2Bus_WrAck;
-- rdack_1 <= IP2Bus_RdAck;
-- wrack_2 <= wrack_1;
-- rdack_2 <= rdack_1;
-- wr_done2 <= wr_done1;
-- rd_done2 <= rd_done1;
if (state = SM_IDLE and S_AXI_ARVALID='1') then
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '1';
start2 <= '1';
elsif (state = SM_IDLE and (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1')) then
bus2ip_addr_i <= ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '0';
start2 <= '1';
else
bus2ip_rnw_i <= bus2ip_rnw_i;
bus2ip_addr_i <= bus2ip_addr_i;
start2 <= '0';
end if;
end if;
end if;
end process REGISTERING_RESET_P2;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
is_read <= '0';
is_write <= '0';
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
is_read <='1';
is_write <= '0';
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
is_read <='0';
is_write <= '1';
else
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= '1' when (dpto_cnt = C_DPHASE_TIMEOUT) else '0';
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
signal start2 : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rd_done1,wr_done1 : std_logic;
--signal rd_done2,wr_done2 : std_logic;
signal wrack_1,rdack_1 : std_logic;
--signal wrack_2,rdack_2 : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
signal is_read, is_write : std_logic;
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
--bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
-- else
-- '0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
--bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
-- when (S_AXI_ARVALID='1')
-- else
-- ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
--start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
-- when (state = SM_IDLE)
-- else
-- '0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or (timeout and is_read);
wr_done <= IP2Bus_WrAck or (timeout and is_write);
--wr_done1 <= (not (wrack_1) and IP2Bus_WrAck) or timeout;
--rd_done1 <= (not (rdack_1) and IP2Bus_RdAck) or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v3_0.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start2,
Bus_RNW => bus2ip_rnw_i, --S_AXI_ARVALID,
Bus_RNW_Erly => bus2ip_rnw_i, --S_AXI_ARVALID,
CS_CE_ld_enable => start2,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start2,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
REGISTERING_RESET_P2 : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
-- wrack_1 <= '0';
-- rdack_1 <= '0';
-- wrack_2 <= '0';
-- rdack_2 <= '0';
-- wr_done2 <= '0';
-- rd_done2 <= '0';
bus2ip_rnw_i <= '0';
bus2ip_addr_i <= (others => '0');
start2 <= '0';
else
-- wrack_1 <= IP2Bus_WrAck;
-- rdack_1 <= IP2Bus_RdAck;
-- wrack_2 <= wrack_1;
-- rdack_2 <= rdack_1;
-- wr_done2 <= wr_done1;
-- rd_done2 <= rd_done1;
if (state = SM_IDLE and S_AXI_ARVALID='1') then
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '1';
start2 <= '1';
elsif (state = SM_IDLE and (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1')) then
bus2ip_addr_i <= ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '0';
start2 <= '1';
else
bus2ip_rnw_i <= bus2ip_rnw_i;
bus2ip_addr_i <= bus2ip_addr_i;
start2 <= '0';
end if;
end if;
end if;
end process REGISTERING_RESET_P2;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
is_read <= '0';
is_write <= '0';
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
is_read <='1';
is_write <= '0';
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
is_read <='0';
is_write <= '1';
else
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= '1' when (dpto_cnt = C_DPHASE_TIMEOUT) else '0';
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: filtering_alogrithm_single - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity filtering_alogrithm_single is
port (
clk : in std_logic;
sclr : in std_logic;
start : in std_logic;
-- initial parameters
k : in centre_index_type;
root_address : in node_address_type;
-- init node and centre memory
wr_init_cent : in std_logic;
wr_centre_list_address_init : in centre_list_address_type;
wr_centre_list_data_init : in centre_index_type;
wr_init_node : in std_logic;
wr_node_address_init : in node_address_type;
wr_node_data_init : in node_data_type;
wr_init_pos : in std_logic;
wr_centre_list_pos_address_init : in centre_index_type;
wr_centre_list_pos_data_init : in data_type;
-- access centre buffer
rdo_centre_buffer : in std_logic;
centre_buffer_addr : in centre_index_type;
valid : out std_logic;
wgtCent_out : out data_type_ext;
sum_sq_out : out coord_type_ext;
count_out : out coord_type;
-- processing done
rdy : out std_logic
);
end filtering_alogrithm_single;
architecture Behavioral of filtering_alogrithm_single is
constant STACK_LAT : integer := 3;
type state_type is (idle, init, processing_phase1, processing_phase2, done);
type schedule_state_type is (free, busy, wait_cycle);
type node_addr_delay_type is array(0 to STACK_LAT-1) of node_address_type;
type centre_list_addr_delay_type is array(0 to STACK_LAT-1) of centre_list_address_type;
type k_delay_type is array(0 to STACK_LAT-1) of centre_index_type;
component memory_mgmt
port (
clk : in std_logic;
sclr : in std_logic;
rd : in std_logic;
rd_node_addr : in node_address_type;
rd_centre_list_address : in centre_list_address_type;
rd_k : in centre_index_type;
wr_cent_nd : in std_logic;
wr_cent : in std_logic;
wr_centre_list_address : in centre_list_address_type;
wr_centre_list_data : in centre_index_type;
wr_init_cent : in std_logic;
wr_centre_list_address_init : in centre_list_address_type;
wr_centre_list_data_init : in centre_index_type;
wr_init_node : in std_logic;
wr_node_address_init : in node_address_type;
wr_node_data_init : in node_data_type;
wr_init_pos : in std_logic;
wr_centre_list_pos_address_init : in centre_index_type;
wr_centre_list_pos_data_init : in data_type;
valid : out std_logic;
rd_node_data : out node_data_type;
rd_centre_list_data : out centre_index_type;
rd_centre_list_pos_data : out data_type;
last_centre : out std_logic;
item_read_twice : out std_logic;
rd_centre_list_address_out : out centre_list_address_type
);
end component;
component process_tree_node
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
u_in : in node_data_type;
centre_positions_in : in data_type;
centre_indices_in : in centre_index_type;
update_centre_buffer : out std_logic;
final_index_out : out centre_index_type;
sum_sq_out : out coord_type_ext;
rdy : out std_logic;
dead_end : out std_logic;
u_out : out node_data_type;
k_out : out centre_index_type;
centre_index_rdy : out std_logic;
centre_index_wr : out std_logic;
centre_indices_out : out centre_index_type
);
end component;
component centre_buffer_mgmt
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
init : in std_logic;
addr_in_init : in centre_index_type;
request_rdo : in std_logic;
addr_in : in centre_index_type;
wgtCent_in : in data_type_ext;
sum_sq_in : in coord_type_ext;
count_in : in coord_type;
valid : out std_logic;
wgtCent_out : out data_type_ext;
sum_sq_out : out coord_type_ext;
count_out : out coord_type
);
end component;
component stack_top
port (
clk : in STD_LOGIC;
sclr : in STD_LOGIC;
push : in std_logic;
pop : in std_logic;
node_addr_in_1 : in node_address_type;
node_addr_in_2 : in node_address_type;
cntr_addr_in_1 : in centre_list_address_type;
cntr_addr_in_2 : in centre_list_address_type;
k_in_1 : in centre_index_type;
k_in_2 : in centre_index_type;
node_addr_out : out node_address_type;
cntr_addr_out : out centre_list_address_type;
k_out : out centre_index_type;
empty : out std_logic;
valid : out std_logic
);
end component;
component allocator
generic (
MEMORY_SIZE : integer := 1024
);
port (
clk : in std_logic;
sclr : in std_logic;
alloc : in std_logic;
free : in std_logic;
address_in : in std_logic_vector(integer(ceil(log2(real(MEMORY_SIZE))))-1 downto 0);
rdy : out std_logic;
address_out : out std_logic_vector(integer(ceil(log2(real(MEMORY_SIZE))))-1 downto 0);
heap_full : out std_logic
);
end component;
-- fsm
signal state : state_type;
signal start_processing : std_logic;
signal processing_done : std_logic;
signal processing_counter_enable : std_logic;
signal processing_done_value : unsigned(INDEX_BITWIDTH+1-1 downto 0);
signal processing_done_counter : unsigned(INDEX_BITWIDTH+1-1 downto 0);
-- memory mgmt
signal memory_mgmt_rd : std_logic;
signal memory_data_valid : std_logic;
signal memory_mgmt_last_centre : std_logic;
signal memory_mgmt_item_read_twice : std_logic;
--signal memory_data_valid_reg : std_logic;
signal rd_node_addr : node_address_type;
signal rd_centre_list_address : centre_list_address_type;
signal rd_k : centre_index_type;
signal rd_node_data : node_data_type;
signal rd_centre_indices : centre_index_type;
signal rd_centre_positions : data_type;
signal rd_centre_list_address_out : centre_list_address_type;
signal rd_centre_list_address_out_reg : centre_list_address_type;
-- process_tree_node
signal ptn_update_centre_buffer : std_logic;
signal ptn_final_index_out : centre_index_type;
signal ptn_sum_sq_out : coord_type_ext;
signal ptn_rdy : std_logic;
signal ptn_dead_end : std_logic;
signal ptn_u_out : node_data_type;
signal ptn_k_out : centre_index_type;
signal ptn_centre_index_rdy : std_logic;
signal ptn_centre_index_rdy_reg : std_logic;
signal ptn_centre_index_wr : std_logic;
signal ptn_centre_indices_out : centre_index_type;
-- centre buffer mgmt
signal tmp_addr : centre_index_type;
-- stack
signal stack_push : std_logic;
signal stack_push_reg : std_logic;
signal stack_pop : std_logic;
signal node_stack_addr_in_1 : node_address_type;
signal node_stack_addr_in_2 : node_address_type;
signal cntr_stack_addr_in : centre_list_address_type;
signal cntr_stack_addr_in_reg : centre_list_address_type;
signal cntr_stack_k_in : centre_index_type;
signal stack_valid : std_logic;
signal stack_empty : std_logic;
signal node_stack_addr_out : node_address_type;
signal cntr_stack_addr_out : centre_list_address_type;
signal cntr_stack_k_out : centre_index_type;
-- scheduler
signal schedule_state : schedule_state_type;
signal schedule_counter : centre_index_type;
signal schedule_counter_done : std_logic;
signal schedule_k_reg : centre_index_type;
signal schedule_next : std_logic;
-- allocator
signal allocator_free : std_logic;
signal allocator_free_1 : std_logic;
signal allocator_free_2 : std_logic;
signal allocator_free_reg : std_logic;
signal allocator_free_address : centre_list_address_type;
signal allocator_alloc : std_logic;
signal allocator_rdy : std_logic;
signal allocator_address_out : centre_list_address_type;
signal allocator_address_out_reg : centre_list_address_type;
signal allocator_heap_full : std_logic;
-- debug and stats (not synthesised)
signal debug_u_left : node_address_type;
signal debug_u_right : node_address_type;
signal first_start : std_logic := '0';
signal visited_nodes : unsigned(31 downto 0);
signal cycle_count : unsigned(31 downto 0);
signal debug_stack_counter : unsigned(31 downto 0);
signal debug_max_stack_counter : unsigned(31 downto 0);
begin
G_NOSYNTH_0 : if SYNTHESIS = false generate
-- some statistics
vn_counter_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
visited_nodes <= (others=> '0');
elsif ptn_rdy = '1' then
visited_nodes <= visited_nodes+1;
end if;
if start = '1' then
first_start <= '1'; -- latch the first start assertion
end if;
if first_start = '0' then
cycle_count <= (others=> '0');
else -- count cycles for all iterations
cycle_count <= cycle_count+1;
end if;
if sclr = '1' then
debug_stack_counter <= (others=>'0');
debug_max_stack_counter <= (others=>'0');
else
if debug_max_stack_counter < debug_stack_counter then
debug_max_stack_counter <= debug_stack_counter;
end if;
if stack_push = '1' AND stack_pop = '0' then
debug_stack_counter <= debug_stack_counter+2;
elsif stack_push = '0' AND stack_pop = '1' then
debug_stack_counter <= debug_stack_counter-1;
end if;
end if;
end if;
end process vn_counter_proc;
end generate G_NOSYNTH_0;
fsm_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
-- state <= idle;
--elsif state = idle AND wr_init_pos = '1' then
state <= init;
elsif state = init AND start = '1' then
state <= processing_phase1;
elsif state = processing_phase1 AND ptn_rdy = '1' then
state <= processing_phase2;
elsif state = processing_phase2 AND processing_done = '1' then
state <= done;
elsif state = done then
state <= init;
end if;
end if;
end process fsm_proc;
start_processing <= '1' WHEN state = init AND start = '1' ELSE '0';
-- scheduler (decides when the next item is popped from stack)
scheduler_proc : process(clk)
--variable var_schedule_next : std_logic;
--variable var_counter_done : std_logic;
begin
if rising_edge(clk) then
--var_schedule_next := '0';
if schedule_state = busy AND stack_valid = '1' then
schedule_k_reg <= cntr_stack_k_out;
elsif schedule_state = free then
schedule_k_reg <= (others => '1');
end if;
if sclr = '1' then
schedule_state <= free;
elsif schedule_state = free AND schedule_next = '1' then
schedule_state <= busy;
elsif schedule_state = busy AND schedule_counter_done = '1' then
schedule_state <= free;
end if;
if sclr = '1' OR schedule_state = free then
schedule_counter <= to_unsigned(0,INDEX_BITWIDTH);
elsif schedule_state = busy AND schedule_counter_done = '0' then
schedule_counter <= schedule_counter+1;
end if;
end if;
end process scheduler_proc;
schedule_next <= '1' WHEN schedule_state = free AND stack_empty = '0' AND stack_push = '0' AND stack_push_reg = '0' ELSE '0';
schedule_counter_done <= '1' WHEN (stack_valid = '1' AND schedule_counter >= cntr_stack_k_out) OR (stack_valid = '0' AND schedule_counter >= schedule_k_reg) ELSE '0';
memory_mgmt_rd <= stack_valid WHEN state = processing_phase2 ELSE start_processing;
rd_node_addr <= root_address WHEN start_processing = '1' ELSE
node_stack_addr_out;
rd_centre_list_address <= std_logic_vector(to_unsigned(0,CNTR_POINTER_BITWIDTH)) WHEN start_processing = '1' ELSE
cntr_stack_addr_out;
rd_k <= k WHEN start_processing = '1' ELSE
cntr_stack_k_out;
memory_mgmt_inst : memory_mgmt
port map (
clk => clk,
sclr => sclr,
rd => memory_mgmt_rd,
rd_node_addr => rd_node_addr,
rd_centre_list_address => rd_centre_list_address,
rd_k => rd_k,
wr_cent_nd => ptn_centre_index_rdy,
wr_cent => ptn_centre_index_wr,
wr_centre_list_address => allocator_address_out,
wr_centre_list_data => ptn_centre_indices_out,
wr_init_cent => wr_init_cent,
wr_centre_list_address_init => wr_centre_list_address_init,
wr_centre_list_data_init => wr_centre_list_data_init,
wr_init_node => wr_init_node,
wr_node_address_init => wr_node_address_init,
wr_node_data_init => wr_node_data_init,
wr_init_pos => wr_init_pos,
wr_centre_list_pos_address_init => wr_centre_list_pos_address_init,
wr_centre_list_pos_data_init => wr_centre_list_pos_data_init,
valid => memory_data_valid,
rd_node_data => rd_node_data,
rd_centre_list_data => rd_centre_indices,
rd_centre_list_pos_data => rd_centre_positions,
last_centre => memory_mgmt_last_centre,
item_read_twice => memory_mgmt_item_read_twice,
rd_centre_list_address_out => rd_centre_list_address_out
);
process_tree_node_inst : process_tree_node
port map (
clk => clk,
sclr => sclr,
nd => memory_data_valid,
u_in => rd_node_data,
centre_positions_in => rd_centre_positions,
centre_indices_in => rd_centre_indices,
update_centre_buffer => ptn_update_centre_buffer,
final_index_out => ptn_final_index_out,
sum_sq_out => ptn_sum_sq_out,
rdy => ptn_rdy,
dead_end => ptn_dead_end,
u_out => ptn_u_out,
k_out => ptn_k_out,
centre_index_rdy => ptn_centre_index_rdy,
centre_index_wr => ptn_centre_index_wr,
centre_indices_out => ptn_centre_indices_out
);
debug_u_left <= ptn_u_out.left;
debug_u_right <= ptn_u_out.right;
tmp_addr <= ptn_final_index_out WHEN rdo_centre_buffer = '0' ELSE centre_buffer_addr;
centre_buffer_mgmt_inst : centre_buffer_mgmt
port map (
clk => clk,
sclr => sclr,
init => wr_init_pos,
addr_in_init => wr_centre_list_pos_address_init,
nd => ptn_update_centre_buffer,
request_rdo => rdo_centre_buffer,
addr_in => tmp_addr,
wgtCent_in => ptn_u_out.wgtCent,
sum_sq_in => ptn_sum_sq_out,
count_in => ptn_u_out.count,
valid => valid,
wgtCent_out => wgtCent_out,
sum_sq_out => sum_sq_out,
count_out => count_out
);
-- used to prevent pops right after a push
stack_push_reg_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
stack_push_reg <= '0';
else
stack_push_reg <= stack_push;
end if;
end if;
end process stack_push_reg_proc;
stack_pop <= schedule_next;
stack_push <= ptn_rdy AND NOT(ptn_dead_end);
node_stack_addr_in_1 <= ptn_u_out.right;
node_stack_addr_in_2 <= ptn_u_out.left;
stack_top_inst : stack_top
port map(
clk => clk,
sclr => sclr,
push => stack_push,
pop => stack_pop,
node_addr_in_1 => node_stack_addr_in_1,
node_addr_in_2 => node_stack_addr_in_2,
cntr_addr_in_1 => cntr_stack_addr_in,
cntr_addr_in_2 => cntr_stack_addr_in,
k_in_1 => cntr_stack_k_in,
k_in_2 => cntr_stack_k_in,
node_addr_out => node_stack_addr_out,
cntr_addr_out => cntr_stack_addr_out,
k_out => cntr_stack_k_out,
empty => stack_empty,
valid => stack_valid
);
G_NO_DYN_ALLOC : if DYN_ALLOC = false generate
-- generate a unique address for each centre list written to memory
inc_centre_list_addr_proc : process(clk)
variable new_cntr_stack_addr_in : unsigned(CNTR_POINTER_BITWIDTH-1 downto 0);
begin
if rising_edge(clk) then
if sclr = '1' then
cntr_stack_addr_in <= std_logic_vector(to_unsigned(1,CNTR_POINTER_BITWIDTH));
else
if ptn_rdy = '1' AND ptn_dead_end = '0' then
new_cntr_stack_addr_in := unsigned(cntr_stack_addr_in)+1;
cntr_stack_addr_in <= std_logic_vector(new_cntr_stack_addr_in);
end if;
end if;
end if;
end process inc_centre_list_addr_proc;
cntr_stack_k_in <= ptn_k_out;
allocator_address_out <= cntr_stack_addr_in;
end generate G_NO_DYN_ALLOC;
G_DYN_ALLOC : if DYN_ALLOC = true generate
allocator_ctrl_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
ptn_centre_index_rdy_reg <= '0';
allocator_free_reg <= '0';
else
ptn_centre_index_rdy_reg <= ptn_centre_index_rdy;
if allocator_free_1 = '1' AND allocator_free_2 = '1' then --two free requests at the same time?
allocator_free_reg <= '1';
else
allocator_free_reg <= '0';
end if;
end if;
if allocator_rdy = '1' then
allocator_address_out_reg <= allocator_address_out;
end if ;
rd_centre_list_address_out_reg <= rd_centre_list_address_out;
end if;
end process allocator_ctrl_proc;
allocator_free_1 <= ptn_rdy AND ptn_dead_end;
allocator_free_2 <= memory_mgmt_last_centre AND memory_mgmt_item_read_twice;
allocator_free_address <= allocator_address_out_reg WHEN (allocator_free_1 = '1' AND allocator_free_2 = '0') OR (allocator_free_1 = '1' AND allocator_free_2 = '1') ELSE
rd_centre_list_address_out WHEN allocator_free_1 = '0' AND allocator_free_2 = '1' ELSE
rd_centre_list_address_out_reg;
allocator_free <= allocator_free_1 OR allocator_free_2 OR allocator_free_reg;
allocator_alloc <= ptn_centre_index_rdy AND NOT(ptn_centre_index_rdy_reg); -- first cycle only --ptn_rdy AND NOT(ptn_dead_end);
allocator_inst : allocator
generic map (
MEMORY_SIZE => HEAP_SIZE
)
port map (
clk => clk,
sclr => wr_init_node,--sclr,
alloc => allocator_alloc,
free => allocator_free,
address_in => allocator_free_address,
rdy => allocator_rdy,
address_out => allocator_address_out,
heap_full => allocator_heap_full
);
cntr_stack_addr_in <= allocator_address_out_reg;
cntr_stack_k_in <= k WHEN allocator_address_out_reg = std_logic_vector(to_unsigned(0,CNTR_POINTER_BITWIDTH)) ELSE ptn_k_out;
end generate G_DYN_ALLOC;
processing_done_counter_proc : process(clk)
begin
if rising_edge(clk) then
if start_processing = '1' then
processing_done_value <= k+to_unsigned(38+100,INDEX_BITWIDTH+1);
end if;
if sclr = '1' OR state = processing_phase1 OR state = done then
processing_counter_enable <= '0';
else
if state = processing_phase2 AND ptn_rdy = '1' then
processing_counter_enable <= '1';
end if;
end if;
if sclr = '1' OR state = processing_phase1 then
processing_done_counter <= (others => '0');
elsif processing_counter_enable = '1' AND ptn_rdy = '0' then
processing_done_counter <= processing_done_counter+1;
elsif processing_counter_enable = '1' AND ptn_rdy = '1' then
processing_done_counter <= (others => '0');
end if;
end if;
end process processing_done_counter_proc;
-- output
processing_done <= '1' WHEN processing_done_counter = processing_done_value ELSE '0';
rdy <= processing_done;
end Behavioral;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity bbtas_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end bbtas_jed;
architecture behaviour of bbtas_jed is
constant st0: std_logic_vector(2 downto 0) := "000";
constant st1: std_logic_vector(2 downto 0) := "001";
constant st2: std_logic_vector(2 downto 0) := "100";
constant st3: std_logic_vector(2 downto 0) := "101";
constant st4: std_logic_vector(2 downto 0) := "111";
constant st5: std_logic_vector(2 downto 0) := "011";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "--";
case current_state is
when st0 =>
if std_match(input, "00") then next_state <= st0; output <= "00";
elsif std_match(input, "01") then next_state <= st1; output <= "00";
elsif std_match(input, "10") then next_state <= st1; output <= "00";
elsif std_match(input, "11") then next_state <= st1; output <= "00";
end if;
when st1 =>
if std_match(input, "00") then next_state <= st0; output <= "00";
elsif std_match(input, "01") then next_state <= st2; output <= "00";
elsif std_match(input, "10") then next_state <= st2; output <= "00";
elsif std_match(input, "11") then next_state <= st2; output <= "00";
end if;
when st2 =>
if std_match(input, "00") then next_state <= st1; output <= "00";
elsif std_match(input, "01") then next_state <= st3; output <= "00";
elsif std_match(input, "10") then next_state <= st3; output <= "00";
elsif std_match(input, "11") then next_state <= st3; output <= "00";
end if;
when st3 =>
if std_match(input, "00") then next_state <= st4; output <= "00";
elsif std_match(input, "01") then next_state <= st3; output <= "01";
elsif std_match(input, "10") then next_state <= st3; output <= "10";
elsif std_match(input, "11") then next_state <= st3; output <= "11";
end if;
when st4 =>
if std_match(input, "00") then next_state <= st5; output <= "00";
elsif std_match(input, "01") then next_state <= st4; output <= "00";
elsif std_match(input, "10") then next_state <= st4; output <= "00";
elsif std_match(input, "11") then next_state <= st4; output <= "00";
end if;
when st5 =>
if std_match(input, "00") then next_state <= st0; output <= "00";
elsif std_match(input, "01") then next_state <= st5; output <= "00";
elsif std_match(input, "10") then next_state <= st5; output <= "00";
elsif std_match(input, "11") then next_state <= st5; output <= "00";
end if;
when others => next_state <= "---"; output <= "--";
end case;
end process;
end behaviour;
|
-- NEED RESULT: ARCH00557: Variable declarations - scalar globally static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00557
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.1.3 (9)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00557)
-- ENT00557_Test_Bench(ARCH00557_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00557 of GENERIC_STANDARD_TYPES is
begin
process
variable correct : boolean := true ;
variable va_boolean_1 : boolean
:= c_boolean_1 ;
variable va_bit_1 : bit
:= c_bit_1 ;
variable va_severity_level_1 : severity_level
:= c_severity_level_1 ;
variable va_character_1 : character
:= c_character_1 ;
variable va_t_enum1_1 : t_enum1
:= c_t_enum1_1 ;
variable va_st_enum1_1 : st_enum1
:= c_st_enum1_1 ;
variable va_integer_1 : integer
:= c_integer_1 ;
variable va_t_int1_1 : t_int1
:= c_t_int1_1 ;
variable va_st_int1_1 : st_int1
:= c_st_int1_1 ;
variable va_time_1 : time
:= c_time_1 ;
variable va_t_phys1_1 : t_phys1
:= c_t_phys1_1 ;
variable va_st_phys1_1 : st_phys1
:= c_st_phys1_1 ;
variable va_real_1 : real
:= c_real_1 ;
variable va_t_real1_1 : t_real1
:= c_t_real1_1 ;
variable va_st_real1_1 : st_real1
:= c_st_real1_1 ;
begin
correct := correct and va_boolean_1 = c_boolean_1 ;
correct := correct and va_bit_1 = c_bit_1 ;
correct := correct and va_severity_level_1 = c_severity_level_1 ;
correct := correct and va_character_1 = c_character_1 ;
correct := correct and va_t_enum1_1 = c_t_enum1_1 ;
correct := correct and va_st_enum1_1 = c_st_enum1_1 ;
correct := correct and va_integer_1 = c_integer_1 ;
correct := correct and va_t_int1_1 = c_t_int1_1 ;
correct := correct and va_st_int1_1 = c_st_int1_1 ;
correct := correct and va_time_1 = c_time_1 ;
correct := correct and va_t_phys1_1 = c_t_phys1_1 ;
correct := correct and va_st_phys1_1 = c_st_phys1_1 ;
correct := correct and va_real_1 = c_real_1 ;
correct := correct and va_t_real1_1 = c_t_real1_1 ;
correct := correct and va_st_real1_1 = c_st_real1_1 ;
va_boolean_1 := c_boolean_2 ;
va_bit_1 := c_bit_2 ;
va_severity_level_1 := c_severity_level_2 ;
va_character_1 := c_character_2 ;
va_t_enum1_1 := c_t_enum1_2 ;
va_st_enum1_1 := c_st_enum1_2 ;
va_integer_1 := c_integer_2 ;
va_t_int1_1 := c_t_int1_2 ;
va_st_int1_1 := c_st_int1_2 ;
va_time_1 := c_time_2 ;
va_t_phys1_1 := c_t_phys1_2 ;
va_st_phys1_1 := c_st_phys1_2 ;
va_real_1 := c_real_2 ;
va_t_real1_1 := c_t_real1_2 ;
va_st_real1_1 := c_st_real1_2 ;
correct := correct and va_boolean_1 = c_boolean_2 ;
correct := correct and va_bit_1 = c_bit_2 ;
correct := correct and va_severity_level_1 = c_severity_level_2 ;
correct := correct and va_character_1 = c_character_2 ;
correct := correct and va_t_enum1_1 = c_t_enum1_2 ;
correct := correct and va_st_enum1_1 = c_st_enum1_2 ;
correct := correct and va_integer_1 = c_integer_2 ;
correct := correct and va_t_int1_1 = c_t_int1_2 ;
correct := correct and va_st_int1_1 = c_st_int1_2 ;
correct := correct and va_time_1 = c_time_2 ;
correct := correct and va_t_phys1_1 = c_t_phys1_2 ;
correct := correct and va_st_phys1_1 = c_st_phys1_2 ;
correct := correct and va_real_1 = c_real_2 ;
correct := correct and va_t_real1_1 = c_t_real1_2 ;
correct := correct and va_st_real1_1 = c_st_real1_2 ;
test_report ( "ARCH00557" ,
"Variable declarations - scalar globally static subtypes" ,
correct) ;
wait ;
end process ;
end ARCH00557 ;
--
entity ENT00557_Test_Bench is
end ENT00557_Test_Bench ;
--
architecture ARCH00557_Test_Bench of ENT00557_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00557 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00557_Test_Bench ;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1_jed is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(5 downto 0)
);
end s1_jed;
architecture behaviour of s1_jed is
constant st0: std_logic_vector(4 downto 0) := "11100";
constant st1: std_logic_vector(4 downto 0) := "11101";
constant st2: std_logic_vector(4 downto 0) := "11000";
constant st5: std_logic_vector(4 downto 0) := "01000";
constant st3: std_logic_vector(4 downto 0) := "11001";
constant st4: std_logic_vector(4 downto 0) := "11110";
constant st6: std_logic_vector(4 downto 0) := "10111";
constant st7: std_logic_vector(4 downto 0) := "00001";
constant st12: std_logic_vector(4 downto 0) := "01101";
constant st13: std_logic_vector(4 downto 0) := "01100";
constant st8: std_logic_vector(4 downto 0) := "10100";
constant st11: std_logic_vector(4 downto 0) := "00000";
constant st15: std_logic_vector(4 downto 0) := "10110";
constant st9: std_logic_vector(4 downto 0) := "10000";
constant st10: std_logic_vector(4 downto 0) := "10001";
constant st14: std_logic_vector(4 downto 0) := "10101";
constant st16: std_logic_vector(4 downto 0) := "10011";
constant st17: std_logic_vector(4 downto 0) := "00100";
constant st18: std_logic_vector(4 downto 0) := "10010";
constant st19: std_logic_vector(4 downto 0) := "00101";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "------";
case current_state is
when st0 =>
if std_match(input, "-1-00---") then next_state <= st0; output <= "000001";
elsif std_match(input, "00--0---") then next_state <= st0; output <= "000001";
elsif std_match(input, "-0--1---") then next_state <= st1; output <= "000011";
elsif std_match(input, "-1-01---") then next_state <= st1; output <= "000011";
elsif std_match(input, "01-10---") then next_state <= st2; output <= "001001";
elsif std_match(input, "11-10---") then next_state <= st5; output <= "011001";
elsif std_match(input, "-1-11---") then next_state <= st3; output <= "001011";
elsif std_match(input, "10--0---") then next_state <= st4; output <= "010001";
end if;
when st1 =>
if std_match(input, "-0------") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-0----") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-1----") then next_state <= st7; output <= "001101";
end if;
when st2 =>
if std_match(input, "0---0---") then next_state <= st2; output <= "001001";
elsif std_match(input, "----1---") then next_state <= st3; output <= "001011";
elsif std_match(input, "1---0---") then next_state <= st5; output <= "011001";
end if;
when st3 =>
if std_match(input, "--------") then next_state <= st7; output <= "001101";
end if;
when st4 =>
if std_match(input, "--0-----") then next_state <= st12; output <= "100001";
elsif std_match(input, "--1-----") then next_state <= st13; output <= "101001";
end if;
when st5 =>
if std_match(input, "--------") then next_state <= st13; output <= "101001";
end if;
when st6 =>
if std_match(input, "-0--1---") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-01---") then next_state <= st6; output <= "000101";
elsif std_match(input, "-1-11---") then next_state <= st7; output <= "001101";
elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000";
elsif std_match(input, "11-10---") then next_state <= st11; output <= "011000";
elsif std_match(input, "10--0---") then next_state <= st15; output <= "010000";
elsif std_match(input, "01-10---") then next_state <= st9; output <= "001000";
end if;
when st7 =>
if std_match(input, "----1---") then next_state <= st7; output <= "001101";
elsif std_match(input, "0---0---") then next_state <= st9; output <= "001000";
elsif std_match(input, "1---0---") then next_state <= st11; output <= "011000";
end if;
when st8 =>
if std_match(input, "00--00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "00---1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-000--") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-0-1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "00--01-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "-1-001-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "-0--11-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "-1-011-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "10--01-1") then next_state <= st4; output <= "010001";
elsif std_match(input, "01-100--") then next_state <= st9; output <= "001000";
elsif std_match(input, "01-1-1--") then next_state <= st9; output <= "001000";
elsif std_match(input, "01-110--") then next_state <= st10; output <= "001010";
elsif std_match(input, "11-1----") then next_state <= st11; output <= "011000";
elsif std_match(input, "100-10--") then next_state <= st14; output <= "000010";
elsif std_match(input, "-1-010--") then next_state <= st14; output <= "000010";
elsif std_match(input, "101-101-") then next_state <= st14; output <= "000010";
elsif std_match(input, "00--10--") then next_state <= st14; output <= "000010";
elsif std_match(input, "10--00--") then next_state <= st15; output <= "010000";
elsif std_match(input, "10---1-0") then next_state <= st15; output <= "010000";
elsif std_match(input, "101-100-") then next_state <= st15; output <= "010000";
end if;
when st9 =>
if std_match(input, "0---00--") then next_state <= st9; output <= "001000";
elsif std_match(input, "0----1-0") then next_state <= st9; output <= "001000";
elsif std_match(input, "0---01-1") then next_state <= st2; output <= "001001";
elsif std_match(input, "0---10--") then next_state <= st10; output <= "001010";
elsif std_match(input, "0---11-1") then next_state <= st3; output <= "001011";
elsif std_match(input, "1----0--") then next_state <= st11; output <= "011000";
elsif std_match(input, "1----1-0") then next_state <= st11; output <= "011000";
elsif std_match(input, "1----1-1") then next_state <= st5; output <= "011001";
end if;
when st10 =>
if std_match(input, "------0-") then next_state <= st16; output <= "001100";
elsif std_match(input, "------1-") then next_state <= st7; output <= "001101";
end if;
when st11 =>
if std_match(input, "-----1-1") then next_state <= st13; output <= "101001";
elsif std_match(input, "-----0--") then next_state <= st17; output <= "101000";
elsif std_match(input, "-----1-0") then next_state <= st17; output <= "101000";
end if;
when st12 =>
if std_match(input, "1-0-----") then next_state <= st12; output <= "100001";
elsif std_match(input, "1-1-----") then next_state <= st13; output <= "101001";
elsif std_match(input, "0---1---") then next_state <= st1; output <= "000011";
elsif std_match(input, "0---0---") then next_state <= st0; output <= "000001";
end if;
when st13 =>
if std_match(input, "1-------") then next_state <= st13; output <= "101001";
elsif std_match(input, "0---0---") then next_state <= st0; output <= "000001";
elsif std_match(input, "0---1---") then next_state <= st1; output <= "000011";
end if;
when st14 =>
if std_match(input, "---0--1-") then next_state <= st6; output <= "000101";
elsif std_match(input, "---0--0-") then next_state <= st18; output <= "000100";
elsif std_match(input, "-0-1----") then next_state <= st18; output <= "000100";
elsif std_match(input, "-1-1----") then next_state <= st16; output <= "001100";
end if;
when st15 =>
if std_match(input, "--0--0--") then next_state <= st19; output <= "100000";
elsif std_match(input, "--0--1-0") then next_state <= st19; output <= "100000";
elsif std_match(input, "--0--1-1") then next_state <= st12; output <= "100001";
elsif std_match(input, "--1-----") then next_state <= st17; output <= "101000";
end if;
when st16 =>
if std_match(input, "----1-0-") then next_state <= st16; output <= "001100";
elsif std_match(input, "----1-1-") then next_state <= st7; output <= "001101";
elsif std_match(input, "1---0---") then next_state <= st11; output <= "011000";
elsif std_match(input, "0---0---") then next_state <= st9; output <= "001000";
end if;
when st17 =>
if std_match(input, "1----0--") then next_state <= st17; output <= "101000";
elsif std_match(input, "1----1-0") then next_state <= st17; output <= "101000";
elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "1----1-1") then next_state <= st13; output <= "101001";
elsif std_match(input, "0---10--") then next_state <= st14; output <= "000010";
end if;
when st18 =>
if std_match(input, "----1-1-") then next_state <= st6; output <= "000101";
elsif std_match(input, "00--0---") then next_state <= st8; output <= "000000";
elsif std_match(input, "-1-00---") then next_state <= st8; output <= "000000";
elsif std_match(input, "01-10---") then next_state <= st9; output <= "001000";
elsif std_match(input, "11-10---") then next_state <= st11; output <= "011000";
elsif std_match(input, "10--0---") then next_state <= st15; output <= "010000";
elsif std_match(input, "-1-11-0-") then next_state <= st16; output <= "001100";
elsif std_match(input, "-0--1-0-") then next_state <= st18; output <= "000100";
elsif std_match(input, "-1-01-0-") then next_state <= st18; output <= "000100";
end if;
when st19 =>
if std_match(input, "1-0--0--") then next_state <= st19; output <= "100000";
elsif std_match(input, "1-0--1-0") then next_state <= st19; output <= "100000";
elsif std_match(input, "0---00--") then next_state <= st8; output <= "000000";
elsif std_match(input, "0----1-0") then next_state <= st8; output <= "000000";
elsif std_match(input, "0---01-1") then next_state <= st0; output <= "000001";
elsif std_match(input, "0---10--") then next_state <= st14; output <= "000010";
elsif std_match(input, "0---11-1") then next_state <= st1; output <= "000011";
elsif std_match(input, "1-0--1-1") then next_state <= st12; output <= "100001";
elsif std_match(input, "1-1-----") then next_state <= st17; output <= "101000";
end if;
when others => next_state <= "-----"; output <= "------";
end case;
end process;
end behaviour;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos (rodrigo4zevedo@gmail.com)
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity ReedSolomonEncoder is
Port ( Clock : in std_logic;
Count7 : in std_logic;
Qs0 : in std_logic_vector(2 downto 0);
Qp : out std_logic_vector(2 downto 0));
end ReedSolomonEncoder;
architecture Behavioral of ReedSolomonEncoder is
component flipflop is
Port ( D: in std_logic_vector(2 downto 0) ;
Clock : in std_logic;
Reset : in std_logic;
Q : out std_logic_vector(2 downto 0)) ;
end component;
component AdderXor is
Port ( a: in std_logic_vector(2 downto 0) ;
b: in std_logic_vector(2 downto 0);
c: out std_logic_vector(2 downto 0)) ;
end component;
component Mult is
port( uncoded_a, uncoded_b:
in std_logic_vector(2 downto 0);
uncoded_multab: out std_logic_vector(2 downto 0)
);
end component;
component mux6 IS
Port (y1: in std_logic_vector(2 downto 0 ) ;
y0: in std_logic_vector(2 downto 0 ) ;
s: in std_logic ;
f: out std_logic_vector(2 downto 0 ));
end component;
signal alpha3 : std_logic_vector(2 downto 0);
signal alpha4 : std_logic_vector(2 downto 0);
signal D1 : std_logic_vector(2 downto 0);
signal D2 : std_logic_vector(2 downto 0);
signal Q1 : std_logic_vector(2 downto 0);
signal Q2 : std_logic_vector(2 downto 0);
signal C0 : std_logic_vector(2 downto 0);
signal multa1 : std_logic_vector(2 downto 0);
signal multa2 : std_logic_vector(2 downto 0);
begin
alpha3(0) <= '0'; alpha3(1) <= '1'; alpha3(2) <= '1';
alpha4(0) <= '1'; alpha4(1) <= '1'; alpha4(2) <= '0';
ff1 : flipflop port map (D1,Clock,Count7,Q1);
ff2 : flipflop port map (D2,Clock,Count7,Q2);
add1 : AdderXor port map (Q2, Qs0, C0);
mult1 : Mult port map (C0, alpha4, multa1);
mult2 : Mult port map (C0, alpha3, multa2);
add2 : AdderXor port map(Q1, multa1, D2);
D1 <= multa2;
Qp <= Q2;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1000.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p09n01i01000pkg is
type TWO is range 1 to 2;
end c06s03b00x00p09n01i01000pkg;
use work.c06s03b00x00p09n01i01000pkg.all;
ENTITY c06s03b00x00p09n01i01000ent IS
END c06s03b00x00p09n01i01000ent;
ARCHITECTURE c06s03b00x00p09n01i01000arch OF c06s03b00x00p09n01i01000ent IS
BEGIN
TESTING: PROCESS
subtype ST4 is c06s03b00x00p09n01i01000ent.c06s03b00x00p09n01i01000pkg.TWO (1 to 1);
-- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
BEGIN
assert FALSE
report "***FAILED TEST: c06s03b00x00p09n01i01000 - Expanded name is illegal."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p09n01i01000arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1000.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p09n01i01000pkg is
type TWO is range 1 to 2;
end c06s03b00x00p09n01i01000pkg;
use work.c06s03b00x00p09n01i01000pkg.all;
ENTITY c06s03b00x00p09n01i01000ent IS
END c06s03b00x00p09n01i01000ent;
ARCHITECTURE c06s03b00x00p09n01i01000arch OF c06s03b00x00p09n01i01000ent IS
BEGIN
TESTING: PROCESS
subtype ST4 is c06s03b00x00p09n01i01000ent.c06s03b00x00p09n01i01000pkg.TWO (1 to 1);
-- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
BEGIN
assert FALSE
report "***FAILED TEST: c06s03b00x00p09n01i01000 - Expanded name is illegal."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p09n01i01000arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1000.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p09n01i01000pkg is
type TWO is range 1 to 2;
end c06s03b00x00p09n01i01000pkg;
use work.c06s03b00x00p09n01i01000pkg.all;
ENTITY c06s03b00x00p09n01i01000ent IS
END c06s03b00x00p09n01i01000ent;
ARCHITECTURE c06s03b00x00p09n01i01000arch OF c06s03b00x00p09n01i01000ent IS
BEGIN
TESTING: PROCESS
subtype ST4 is c06s03b00x00p09n01i01000ent.c06s03b00x00p09n01i01000pkg.TWO (1 to 1);
-- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
BEGIN
assert FALSE
report "***FAILED TEST: c06s03b00x00p09n01i01000 - Expanded name is illegal."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p09n01i01000arch;
|
-- c_0_0 opt232
cfg.gridConf(0)(0).procConf.AluOpxS := alu_pass0;
-- i.0
cfg.gridConf(0)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(0).routConf.i(0).LocalxE(LOCAL_SW) := '1';
-- c_0_1 op13
cfg.gridConf(0)(1).procConf.AluOpxS := alu_add;
-- i.0
cfg.gridConf(0)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(1).routConf.i(0).HBusNxE(0) := '1';
-- i.1
cfg.gridConf(0)(1).procConf.OpMuxS(1) := I_REG_CTX_THIS;
cfg.gridConf(0)(1).routConf.i(1).LocalxE(LOCAL_N) := '1';
-- o.0
cfg.gridConf(0)(1).procConf.OutMuxS := O_NOREG;
-- c_0_2 op14
cfg.gridConf(0)(2).procConf.AluOpxS := alu_mux;
-- i.0
cfg.gridConf(0)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(2).routConf.i(0).LocalxE(LOCAL_NE) := '1';
-- i.1
cfg.gridConf(0)(2).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(0)(2).routConf.i(1).LocalxE(LOCAL_W) := '1';
-- i.2
cfg.gridConf(0)(2).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(0)(2).routConf.i(2).LocalxE(LOCAL_N) := '1';
-- o.0
cfg.gridConf(0)(2).procConf.OutMuxS := O_NOREG;
cfg.gridConf(0)(2).routConf.o.VBusExE(1) := '1';
-- c_0_3 op6
cfg.gridConf(0)(3).procConf.AluOpxS := alu_and;
-- i.0
cfg.gridConf(0)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(3).routConf.i(0).HBusNxE(1) := '1';
-- i.1
cfg.gridConf(0)(3).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(0)(3).procConf.ConstOpxD := i2cfgconst(7);
-- o.0
cfg.gridConf(0)(3).procConf.OutMuxS := O_NOREG;
cfg.gridConf(0)(3).routConf.o.HBusNxE(0) := '1';
-- c_1_0 opt230
cfg.gridConf(1)(0).procConf.AluOpxS := alu_pass0;
-- i.0
cfg.gridConf(1)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(0).routConf.i(0).LocalxE(LOCAL_SE) := '1';
-- c_1_1 op8
cfg.gridConf(1)(1).procConf.AluOpxS := alu_tstbitat1;
-- i.0
cfg.gridConf(1)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(1).routConf.i(0).HBusNxE(0) := '1';
-- i.1
cfg.gridConf(1)(1).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(1)(1).procConf.ConstOpxD := i2cfgconst(2);
-- o.0
cfg.gridConf(1)(1).procConf.OutMuxS := O_NOREG;
cfg.gridConf(1)(1).routConf.o.HBusNxE(0) := '1';
-- c_1_2 op15
cfg.gridConf(1)(2).procConf.AluOpxS := alu_add;
-- i.0
cfg.gridConf(1)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(2).routConf.i(0).LocalxE(LOCAL_N) := '1';
-- i.1
cfg.gridConf(1)(2).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(1)(2).routConf.i(1).LocalxE(LOCAL_S) := '1';
-- o.0
cfg.gridConf(1)(2).procConf.OutMuxS := O_NOREG;
-- c_1_3 op9
cfg.gridConf(1)(3).procConf.AluOpxS := alu_tstbitat1;
-- i.0
cfg.gridConf(1)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(1)(3).routConf.i(0).LocalxE(LOCAL_N) := '1';
-- i.1
cfg.gridConf(1)(3).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(1)(3).procConf.ConstOpxD := i2cfgconst(1);
-- o.0
cfg.gridConf(1)(3).procConf.OutMuxS := O_NOREG;
-- c_2_0 opt231
cfg.gridConf(2)(0).procConf.AluOpxS := alu_pass0;
-- i.0
cfg.gridConf(2)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(0).routConf.i(0).LocalxE(LOCAL_W) := '1';
-- c_2_1 op17
cfg.gridConf(2)(1).procConf.AluOpxS := alu_add;
-- i.0
cfg.gridConf(2)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(1).routConf.i(0).HBusSxE(0) := '1';
-- i.1
cfg.gridConf(2)(1).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(2)(1).routConf.i(1).LocalxE(LOCAL_SW) := '1';
-- o.0
cfg.gridConf(2)(1).procConf.OutMuxS := O_NOREG;
-- c_2_2 op11
cfg.gridConf(2)(2).procConf.AluOpxS := alu_srl;
-- i.0
cfg.gridConf(2)(2).procConf.OpMuxS(0) := I_REG_CTX_THIS;
cfg.gridConf(2)(2).routConf.i(0).LocalxE(LOCAL_SW) := '1';
-- i.1
cfg.gridConf(2)(2).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(2)(2).procConf.ConstOpxD := i2cfgconst(1);
-- o.0
cfg.gridConf(2)(2).procConf.OutMuxS := O_NOREG;
-- c_2_3 op16
cfg.gridConf(2)(3).procConf.AluOpxS := alu_mux;
-- i.0
cfg.gridConf(2)(3).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(2)(3).routConf.i(0).VBusExE(1) := '1';
-- i.1
cfg.gridConf(2)(3).procConf.OpMuxS(1) := I_NOREG;
cfg.gridConf(2)(3).routConf.i(1).LocalxE(LOCAL_NW) := '1';
-- i.2
cfg.gridConf(2)(3).procConf.OpMuxS(2) := I_NOREG;
cfg.gridConf(2)(3).routConf.i(2).HBusNxE(0) := '1';
-- o.0
cfg.gridConf(2)(3).procConf.OutMuxS := O_NOREG;
cfg.gridConf(2)(3).routConf.o.HBusSxE(0) := '1';
-- c_3_0 op10
cfg.gridConf(3)(0).procConf.AluOpxS := alu_srl;
-- i.0
cfg.gridConf(3)(0).procConf.OpMuxS(0) := I_REG_CTX_THIS;
cfg.gridConf(3)(0).routConf.i(0).LocalxE(LOCAL_E) := '1';
-- i.1
cfg.gridConf(3)(0).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(3)(0).procConf.ConstOpxD := i2cfgconst(2);
-- o.0
cfg.gridConf(3)(0).procConf.OutMuxS := O_NOREG;
-- c_3_1 opt120
cfg.gridConf(3)(1).procConf.AluOpxS := alu_pass0;
-- o.0
cfg.gridConf(3)(1).procConf.OutMuxS := O_REG_CTX_OTHER;
cfg.gridConf(3)(1).procConf.OutCtxRegSelxS := i2ctx(0);
cfg.gridConf(3)(1).routConf.o.HBusSxE(1) := '1';
-- c_3_2 op7
cfg.gridConf(3)(2).procConf.AluOpxS := alu_tstbitat1;
-- i.0
cfg.gridConf(3)(2).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(3)(2).routConf.i(0).LocalxE(LOCAL_SE) := '1';
-- i.1
cfg.gridConf(3)(2).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(3)(2).procConf.ConstOpxD := i2cfgconst(4);
-- o.0
cfg.gridConf(3)(2).procConf.OutMuxS := O_NOREG;
-- c_3_3 op12
cfg.gridConf(3)(3).procConf.AluOpxS := alu_srl;
-- i.0
cfg.gridConf(3)(3).procConf.OpMuxS(0) := I_REG_CTX_THIS;
cfg.gridConf(3)(3).routConf.i(0).HBusSxE(1) := '1';
-- i.1
cfg.gridConf(3)(3).procConf.OpMuxS(1) := I_CONST;
cfg.gridConf(3)(3).procConf.ConstOpxD := i2cfgconst(3);
-- o.0
cfg.gridConf(3)(3).procConf.OutMuxS := O_NOREG;
cfg.gridConf(3)(3).routConf.o.HBusNxE(0) := '1';
-- input drivers
cfg.inputDriverConf(0)(0)(1) := '1';
-- output drivers
|
architecture RTL of FIFO is
begin
-- These are passing
a <= b; -- Comment 1
a <= when c = '0' else '1'; -- Comment 2
a <= b; -- Comment 3
a <= when c = '0' else '1'; -- Comment 4
-- Failing variations
a <= b;-- Comment 1
a <= when c = '0' else '1'; -- Comment 2
a <= b; -- Comment 3
a <= when c = '0' else '1';-- Comment 4
process -- comment process
begin -- comment begin
a <= b; -- Comment
b <= c; -- Comment
c <= d; -- Comment
end process; -- comment end process
x <= z when b = c else -- comment a
y when c = d else -- comment b
x when d = e; -- comment c
z <= w when e = f else -- comment d
x when f = g else -- comment e
z; -- comment f
INST : INST_1 -- instantiation comment
port map ( -- port map comment
a => '0' -- port comment
); -- end port map comment
assert True -- assert comment
report "Hello" -- report comment
severity Warning; -- severity comment
procedure_call( -- procedure call comment
a => b, -- procedure call parameter 1
c => d -- procedure call parameter 2
); -- procedure call end parenthesis
-- Block
block_label : block -- Block comment
begin -- block begin comment
a <= b; -- comment z
c <= d; -- comment y
e <= f; -- comment x
end block; -- end block comment
-- Generate statements
for_generate_label : for i in 0 to 200 generate -- for generate comment
ab <= bc; -- comment zz
ac <= ad; -- coment za
ae <= af; -- comment ab
end generate; -- end for generate label
a <= b; -- comment
c <= d; -- comment
-- comment line
s <= a;
-- A
s <= b; -- B
s <= cc; -- C
end architecture RTL;
|
-------------------------------------------------------------------------------
-- rd_chnl.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: rd_chnl.vhd
--
-- Description: This file is the top level module for the AXI BRAM
-- controller read channel interfaces. Controls all
-- handshaking and data flow on the AXI read address (AR)
-- and read data (R) channels.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Minor code cleanup.
-- Remove library version # dependency. Replace with work library.
-- ^^^^^^
-- JLJ 2/3/2011 v1.03a
-- ~~~~~~
-- Edits for scalability and support of 512 and 1024-bit data widths.
-- ^^^^^^
-- JLJ 2/14/2011 v1.03a
-- ~~~~~~
-- Initial integration of Hsiao ECC algorithm.
-- Add C_ECC_TYPE top level parameter.
-- Similar edits as wr_chnl on Hsiao ECC code.
-- ^^^^^^
-- JLJ 2/18/2011 v1.03a
-- ~~~~~~
-- Update for usage of ecc_gen.vhd module directly from MIG.
-- Clean-up XST warnings.
-- ^^^^^^
-- JLJ 2/22/2011 v1.03a
-- ~~~~~~
-- Found issue with ECC decoding on read path. Remove MSB '0' usage
-- in syndrome calculation, since h_matrix is based on 32 + 7 = 39 bits.
-- Modify read data signal used in single bit error correction.
-- ^^^^^^
-- JLJ 2/23/2011 v1.03a
-- ~~~~~~
-- Move all MIG functions to package body.
-- ^^^^^^
-- JLJ 3/2/2011 v1.03a
-- ~~~~~~
-- Fix XST handling for DIV functions. Create seperate process when
-- divisor is not constant and a power of two.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Clean-up unused signal, narrow_addr_inc.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs. And general code clean-up.
-- ^^^^^^
-- JLJ 4/21/2011 v1.03a
-- ~~~~~~
-- Code clean up.
-- Add defaults to araddr_pipe_sel & axi_arready_int when in single port mode.
-- Remove use of IF_IS_AXI4 constant.
-- ^^^^^^
-- JLJ 4/22/2011 v1.03a
-- ~~~~~~
-- Code clean up.
-- ^^^^^^
-- JLJ 5/6/2011 v1.03a
-- ~~~~~~
-- Remove usage of C_FAMILY.
-- Hard code C_USE_LUT6 constant.
-- ^^^^^^
-- JLJ 5/26/2011 v1.03a
-- ~~~~~~
-- With CR # 609695, update else clause for narrow_burst_cnt_ld to
-- remove simulation warnings when axi_byte_div_curr_arsize = zero.
-- ^^^^^^
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.wrap_brst;
use work.ua_narrow;
use work.checkbit_handler;
use work.checkbit_handler_64;
use work.correct_one_bit;
use work.correct_one_bit_64;
use work.ecc_gen;
use work.parity;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity rd_chnl is
generic (
-- C_FAMILY : string := "virtex6";
-- Specify the target architecture type
C_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_BRAM_ADDR_ADJUST_FACTOR : integer := 2;
-- Adjust factor to BRAM address width based on data width (in bits)
C_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_AXI_ID_WIDTH : integer := 4;
-- AXI ID vector width
C_S_AXI_SUPPORTS_NARROW : integer := 1;
-- Support for narrow burst operations
C_S_AXI_PROTOCOL : string := "AXI4";
-- Set to "AXI4LITE" to optimize out burst transaction support
C_SINGLE_PORT_BRAM : integer := 0;
-- Enable single port usage of BRAM
C_ECC : integer := 0;
-- Enables or disables ECC functionality
C_ECC_WIDTH : integer := 8;
-- Width of ECC data vector
C_ECC_TYPE : integer := 0 -- v1.03a
-- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code
);
port (
-- AXI Global Signals
S_AXI_AClk : in std_logic;
S_AXI_AResetn : in std_logic;
-- AXI Read Address Channel Signals (AR)
AXI_ARID : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
AXI_ARADDR : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0);
AXI_ARLEN : in std_logic_vector(7 downto 0);
-- Specifies the number of data transfers in the burst
-- "0000 0000" 1 data transfer
-- "0000 0001" 2 data transfers
-- ...
-- "1111 1111" 256 data transfers
AXI_ARSIZE : in std_logic_vector(2 downto 0);
-- Specifies the max number of data bytes to transfer in each data beat
-- "000" 1 byte to transfer
-- "001" 2 bytes to transfer
-- "010" 3 bytes to transfer
-- ...
AXI_ARBURST : in std_logic_vector(1 downto 0);
-- Specifies burst type
-- "00" FIXED = Fixed burst address (handled as INCR)
-- "01" INCR = Increment burst address
-- "10" WRAP = Incrementing address burst that wraps to lower order address at boundary
-- "11" Reserved (not checked)
AXI_ARLOCK : in std_logic;
AXI_ARCACHE : in std_logic_vector(3 downto 0);
AXI_ARPROT : in std_logic_vector(2 downto 0);
AXI_ARVALID : in std_logic;
AXI_ARREADY : out std_logic;
-- AXI Read Data Channel Signals (R)
AXI_RID : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
AXI_RDATA : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0);
AXI_RRESP : out std_logic_vector(1 downto 0);
AXI_RLAST : out std_logic;
AXI_RVALID : out std_logic;
AXI_RREADY : in std_logic;
-- ECC Register Interface Signals
Enable_ECC : in std_logic;
BRAM_Addr_En : out std_logic;
CE_Failing_We : out std_logic := '0';
Sl_CE : out std_logic := '0';
Sl_UE : out std_logic := '0';
-- Single Port Arbitration Signals
Arb2AR_Active : in std_logic;
AR2Arb_Active_Clr : out std_logic := '0';
Sng_BRAM_Addr_Ld_En : out std_logic := '0';
Sng_BRAM_Addr_Ld : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
Sng_BRAM_Addr_Inc : out std_logic := '0';
Sng_BRAM_Addr : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR);
-- BRAM Read Port Interface Signals
BRAM_En : out std_logic;
BRAM_Addr : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0);
BRAM_RdData : in std_logic_vector (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0)
);
end entity rd_chnl;
-------------------------------------------------------------------------------
architecture implementation of rd_chnl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- All functions defined in axi_bram_ctrl_funcs package.
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
constant RESP_OKAY : std_logic_vector (1 downto 0) := "00"; -- Normal access OK response
constant RESP_SLVERR : std_logic_vector (1 downto 0) := "10"; -- Slave error
-- For future support. constant RESP_EXOKAY : std_logic_vector (1 downto 0) := "01"; -- Exclusive access OK response
-- For future support. constant RESP_DECERR : std_logic_vector (1 downto 0) := "11"; -- Decode error
-- Set constants for ARLEN equal to a count of one or two beats.
constant AXI_ARLEN_ONE : std_logic_vector(7 downto 0) := (others => '0');
constant AXI_ARLEN_TWO : std_logic_vector(7 downto 0) := "00000001";
-- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width
-- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00"
-- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000"
-- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000"
-- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000"
-- Move to full_axi module
-- constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_AXI_DATA_WIDTH/8);
-- Not used
-- constant C_BRAM_ADDR_ADJUST : integer := C_AXI_ADDR_WIDTH - C_BRAM_ADDR_ADJUST_FACTOR;
-- Determine maximum size for narrow burst length counter
-- When C_AXI_DATA_WIDTH = 32, minimum narrow width burst is 8 bits
-- resulting in a count 3 downto 0 => so minimum counter width = 2 bits.
-- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst is 8 bits
-- resulting in a count 31 downto 0 => so minimum counter width = 5 bits.
constant C_NARROW_BURST_CNT_LEN : integer := log2 (C_AXI_DATA_WIDTH/8);
constant NARROW_CNT_MAX : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
-- Max length burst count AXI4 specification
constant C_MAX_BRST_CNT : integer := 256;
constant C_BRST_CNT_SIZE : integer := log2 (C_MAX_BRST_CNT);
-- When the burst count = 0
constant C_BRST_CNT_ZERO : std_logic_vector(C_BRST_CNT_SIZE-1 downto 0) := (others => '0');
-- Burst count = 1
constant C_BRST_CNT_ONE : std_logic_vector(7 downto 0) := "00000001";
-- Burst count = 2
constant C_BRST_CNT_TWO : std_logic_vector(7 downto 0) := "00000010";
-- Read data mux select constants (for signal rddata_mux_sel)
-- '0' selects BRAM
-- '1' selects read skid buffer
constant C_RDDATA_MUX_BRAM : std_logic := '0';
constant C_RDDATA_MUX_SKID_BUF : std_logic := '1';
-- Determine the number of bytes based on the AXI data width.
constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8;
-- AXI Burst Types
-- AXI Spec 4.4
constant C_AXI_BURST_WRAP : std_logic_vector (1 downto 0) := "10";
constant C_AXI_BURST_INCR : std_logic_vector (1 downto 0) := "01";
constant C_AXI_BURST_FIXED : std_logic_vector (1 downto 0) := "00";
-- AXI Size Constants
-- constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte
-- constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes
-- constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM
-- constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM
-- constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM
-- constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM
-- constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM
-- constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM
-- Determine max value of ARSIZE based on the AXI data width.
-- Use function in axi_bram_ctrl_funcs package.
constant C_AXI_SIZE_MAX : std_logic_vector (2 downto 0) := Create_Size_Max (C_AXI_DATA_WIDTH);
-- Internal ECC data width size.
constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_AXI_DATA_WIDTH);
-- For use with ECC functions (to use LUT6 components or let synthesis infer the optimal implementation).
-- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6;
-- Remove usage of C_FAMILY.
-- All architectures supporting AXI will support a LUT6.
-- Hard code this internal constant used in ECC algorithm.
constant C_USE_LUT6 : boolean := TRUE;
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Read Address Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type RD_ADDR_SM_TYPE is ( IDLE,
LD_ARADDR
);
signal rd_addr_sm_cs, rd_addr_sm_ns : RD_ADDR_SM_TYPE;
signal ar_active_set : std_logic := '0';
signal ar_active_set_i : std_logic := '0';
signal ar_active_clr : std_logic := '0';
signal ar_active : std_logic := '0';
signal ar_active_d1 : std_logic := '0';
signal ar_active_re : std_logic := '0';
signal axi_araddr_pipe : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal curr_araddr_lsb : std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0');
signal araddr_pipe_ld : std_logic := '0';
signal araddr_pipe_ld_i : std_logic := '0';
signal araddr_pipe_sel : std_logic := '0';
-- '0' indicates mux select from AXI
-- '1' indicates mux select from AR Addr Register
signal axi_araddr_full : std_logic := '0';
signal axi_arready_int : std_logic := '0';
signal axi_early_arready_int : std_logic := '0';
signal axi_aresetn_d1 : std_logic := '0';
signal axi_aresetn_d2 : std_logic := '0';
signal axi_aresetn_re : std_logic := '0';
signal axi_aresetn_re_reg : std_logic := '0';
signal no_ar_ack_cmb : std_logic := '0';
signal no_ar_ack : std_logic := '0';
signal pend_rd_op_cmb : std_logic := '0';
signal pend_rd_op : std_logic := '0';
signal axi_arid_pipe : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_arsize_pipe : std_logic_vector (2 downto 0) := (others => '0');
signal axi_arsize_pipe_4byte : std_logic := '0';
signal axi_arsize_pipe_8byte : std_logic := '0';
signal axi_arsize_pipe_16byte : std_logic := '0';
signal axi_arsize_pipe_32byte : std_logic := '0';
-- v1.03a
signal axi_arsize_pipe_max : std_logic := '0';
signal curr_arsize : std_logic_vector (2 downto 0) := (others => '0');
signal curr_arsize_reg : std_logic_vector (2 downto 0) := (others => '0');
signal axi_arlen_pipe : std_logic_vector(7 downto 0) := (others => '0');
signal axi_arlen_pipe_1_or_2 : std_logic := '0';
signal curr_arlen : std_logic_vector(7 downto 0) := (others => '0');
signal curr_arlen_reg : std_logic_vector(7 downto 0) := (others => '0');
signal axi_arburst_pipe : std_logic_vector(1 downto 0) := (others => '0');
signal axi_arburst_pipe_fixed : std_logic := '0';
signal curr_arburst : std_logic_vector(1 downto 0) := (others => '0');
signal curr_wrap_burst : std_logic := '0';
signal curr_wrap_burst_reg : std_logic := '0';
signal max_wrap_burst : std_logic := '0';
signal curr_incr_burst : std_logic := '0';
signal curr_fixed_burst : std_logic := '0';
signal curr_fixed_burst_reg : std_logic := '0';
-- BRAM Address Counter
signal bram_addr_ld_en : std_logic := '0';
signal bram_addr_ld_en_i : std_logic := '0';
signal bram_addr_ld_en_mod : std_logic := '0';
signal bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_ld_wrap : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_inc : std_logic := '0';
signal bram_addr_inc_mod : std_logic := '0';
signal bram_addr_inc_wrap_mod : std_logic := '0';
-------------------------------------------------------------------------------
-- AXI Read Data Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type RD_DATA_SM_TYPE is ( IDLE,
SNG_ADDR,
SEC_ADDR,
FULL_PIPE,
FULL_THROTTLE,
LAST_ADDR,
LAST_THROTTLE,
LAST_DATA,
LAST_DATA_AR_PEND
);
signal rd_data_sm_cs, rd_data_sm_ns : RD_DATA_SM_TYPE;
signal rd_adv_buf : std_logic := '0';
signal axi_rd_burst : std_logic := '0';
signal axi_rd_burst_two : std_logic := '0';
signal act_rd_burst : std_logic := '0';
signal act_rd_burst_set : std_logic := '0';
signal act_rd_burst_clr : std_logic := '0';
signal act_rd_burst_two : std_logic := '0';
-- Rd Data Buffer/Register
signal rd_skid_buf_ld_cmb : std_logic := '0';
signal rd_skid_buf_ld_reg : std_logic := '0';
signal rd_skid_buf_ld : std_logic := '0';
signal rd_skid_buf_ld_imm : std_logic := '0';
signal rd_skid_buf : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal rddata_mux_sel_cmb : std_logic := '0';
signal rddata_mux_sel : std_logic := '0';
signal axi_rdata_en : std_logic := '0';
signal axi_rdata_mux : std_logic_vector (C_AXI_DATA_WIDTH+8*C_ECC-1 downto 0) := (others => '0');
-- Read Burst Counter
signal brst_cnt_max : std_logic := '0';
signal brst_cnt_max_d1 : std_logic := '0';
signal brst_cnt_max_re : std_logic := '0';
signal end_brst_rd_clr_cmb : std_logic := '0';
signal end_brst_rd_clr : std_logic := '0';
signal end_brst_rd : std_logic := '0';
signal brst_zero : std_logic := '0';
signal brst_one : std_logic := '0';
signal brst_cnt_ld : std_logic_vector (C_BRST_CNT_SIZE-1 downto 0) := (others => '0');
signal brst_cnt_rst : std_logic := '0';
signal brst_cnt_ld_en : std_logic := '0';
signal brst_cnt_ld_en_i : std_logic := '0';
signal brst_cnt_dec : std_logic := '0';
signal brst_cnt : std_logic_vector (C_BRST_CNT_SIZE-1 downto 0) := (others => '0');
-- AXI Read Response Signals
signal axi_rid_temp : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_rid_temp_full : std_logic := '0';
signal axi_rid_temp_full_d1 : std_logic := '0';
signal axi_rid_temp_full_fe : std_logic := '0';
signal axi_rid_temp2 : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_rid_temp2_full : std_logic := '0';
signal axi_b2b_rid_adv : std_logic := '0';
signal axi_rid_int : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_rresp_int : std_logic_vector (1 downto 0) := (others => '0');
signal axi_rvalid_clr_ok : std_logic := '0';
signal axi_rvalid_set_cmb : std_logic := '0';
signal axi_rvalid_set : std_logic := '0';
signal axi_rvalid_int : std_logic := '0';
signal axi_rlast_int : std_logic := '0';
signal axi_rlast_set : std_logic := '0';
-- Internal BRAM Signals
signal bram_en_cmb : std_logic := '0';
signal bram_en_int : std_logic := '0';
signal bram_addr_int : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
-- Narrow Burst Signals
signal curr_narrow_burst_cmb : std_logic := '0';
signal curr_narrow_burst : std_logic := '0';
signal narrow_burst_cnt_ld : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal narrow_burst_cnt_ld_reg : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal narrow_burst_cnt_ld_mod : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal narrow_addr_rst : std_logic := '0';
signal narrow_addr_ld_en : std_logic := '0';
signal narrow_addr_dec : std_logic := '0';
signal narrow_bram_addr_inc : std_logic := '0';
signal narrow_bram_addr_inc_d1 : std_logic := '0';
signal narrow_bram_addr_inc_re : std_logic := '0';
signal narrow_addr_int : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal curr_ua_narrow_wrap : std_logic := '0';
signal curr_ua_narrow_incr : std_logic := '0';
signal ua_narrow_load : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
-- State machine type declarations
type RLAST_SM_TYPE is ( IDLE,
W8_THROTTLE,
W8_2ND_LAST_DATA,
W8_LAST_DATA,
-- W8_LAST_DATA_B2,
W8_THROTTLE_B2
);
signal rlast_sm_cs, rlast_sm_ns : RLAST_SM_TYPE;
signal last_bram_addr : std_logic := '0';
signal set_last_bram_addr : std_logic := '0';
signal alast_bram_addr : std_logic := '0';
signal rd_b2b_elgible : std_logic := '0';
signal rd_b2b_elgible_no_thr_check : std_logic := '0';
signal throttle_last_data : std_logic := '0';
signal disable_b2b_brst_cmb : std_logic := '0';
signal disable_b2b_brst : std_logic := '0';
signal axi_b2b_brst_cmb : std_logic := '0';
signal axi_b2b_brst : std_logic := '0';
signal do_cmplt_burst_cmb : std_logic := '0';
signal do_cmplt_burst : std_logic := '0';
signal do_cmplt_burst_clr : std_logic := '0';
-------------------------------------------------------------------------------
-- ECC Signals
-------------------------------------------------------------------------------
signal UnCorrectedRdData : std_logic_vector (0 to C_AXI_DATA_WIDTH-1) := (others => '0');
-- Move vector from core ECC module to use in AXI RDATA register output
signal Syndrome : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
signal Syndrome_4 : std_logic_vector (0 to 1) := (others => '0'); -- Only used in 32-bit ECC
signal Syndrome_6 : std_logic_vector (0 to 5) := (others => '0'); -- Specific to ECC @ 32-bit data width
signal Syndrome_7 : std_logic_vector (0 to 11) := (others => '0'); -- Specific to ECC @ 64-bit data width
signal syndrome_reg : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
signal syndrome_reg_i : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
signal Sl_UE_i : std_logic := '0';
signal UE_Q : std_logic := '0';
-- v1.03a
-- Hsiao ECC
signal syndrome_r : std_logic_vector (C_INT_ECC_WIDTH - 1 downto 0) := (others => '0');
constant CODE_WIDTH : integer := C_AXI_DATA_WIDTH + C_INT_ECC_WIDTH;
constant ECC_WIDTH : integer := C_INT_ECC_WIDTH;
signal h_rows : std_logic_vector (CODE_WIDTH * ECC_WIDTH - 1 downto 0);
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- AXI Read Address Channel Output Signals
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_ARREADY_DUAL
-- Purpose: Generate AXI_ARREADY when in dual port mode.
---------------------------------------------------------------------------
GEN_ARREADY_DUAL: if C_SINGLE_PORT_BRAM = 0 generate
begin
-- Ensure ARREADY only gets asserted early when acknowledge recognized
-- on AXI read data channel.
AXI_ARREADY <= axi_arready_int or (axi_early_arready_int and rd_adv_buf);
end generate GEN_ARREADY_DUAL;
---------------------------------------------------------------------------
-- Generate: GEN_ARREADY_SNG
-- Purpose: Generate AXI_ARREADY when in single port mode.
---------------------------------------------------------------------------
GEN_ARREADY_SNG: if C_SINGLE_PORT_BRAM = 1 generate
begin
-- ARREADY generated by sng_port_arb module
AXI_ARREADY <= '0';
axi_arready_int <= '0';
end generate GEN_ARREADY_SNG;
---------------------------------------------------------------------------
-- AXI Read Data Channel Output Signals
---------------------------------------------------------------------------
-- UE flag is detected is same clock cycle that read data is presented on
-- the AXI bus. Must drive SLVERR combinatorially to align with corrupted
-- detected data word.
AXI_RRESP <= RESP_SLVERR when (C_ECC = 1 and Sl_UE_i = '1') else axi_rresp_int;
AXI_RVALID <= axi_rvalid_int;
AXI_RID <= axi_rid_int;
AXI_RLAST <= axi_rlast_int;
---------------------------------------------------------------------------
--
-- *** AXI Read Address Channel Interface ***
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_AR_PIPE_SNG
-- Purpose: Only generate pipeline registers when in dual port BRAM mode.
---------------------------------------------------------------------------
GEN_AR_PIPE_SNG: if C_SINGLE_PORT_BRAM = 1 generate
begin
-- Unused AW pipeline (set default values)
araddr_pipe_ld <= '0';
axi_araddr_pipe <= AXI_ARADDR;
axi_arid_pipe <= AXI_ARID;
axi_arsize_pipe <= AXI_ARSIZE;
axi_arlen_pipe <= AXI_ARLEN;
axi_arburst_pipe <= AXI_ARBURST;
axi_arlen_pipe_1_or_2 <= '0';
axi_arburst_pipe_fixed <= '0';
axi_araddr_full <= '0';
end generate GEN_AR_PIPE_SNG;
---------------------------------------------------------------------------
-- Generate: GEN_AR_PIPE_DUAL
-- Purpose: Only generate pipeline registers when in dual port BRAM mode.
---------------------------------------------------------------------------
GEN_AR_PIPE_DUAL: if C_SINGLE_PORT_BRAM = 0 generate
begin
-----------------------------------------------------------------------
-- AXI Read Address Buffer/Register
-- (mimic behavior of address pipeline for AXI_ARID)
-----------------------------------------------------------------------
GEN_ARADDR: for i in C_AXI_ADDR_WIDTH-1 downto 0 generate
begin
REG_ARADDR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- No reset condition to save resources/timing
if (araddr_pipe_ld = '1') then
axi_araddr_pipe (i) <= AXI_ARADDR (i);
else
axi_araddr_pipe (i) <= axi_araddr_pipe (i);
end if;
end if;
end process REG_ARADDR;
end generate GEN_ARADDR;
-------------------------------------------------------------------
-- Register ARID
-- No reset condition to save resources/timing
-------------------------------------------------------------------
REG_ARID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (araddr_pipe_ld = '1') then
axi_arid_pipe <= AXI_ARID;
else
axi_arid_pipe <= axi_arid_pipe;
end if;
end if;
end process REG_ARID;
---------------------------------------------------------------------------
-- In parallel to ARADDR pipeline and ARID
-- Use same control signals to capture AXI_ARSIZE, AXI_ARLEN & AXI_ARBURST.
-- Register AXI_ARSIZE, AXI_ARLEN & AXI_ARBURST
-- No reset condition to save resources/timing
REG_ARCTRL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (araddr_pipe_ld = '1') then
axi_arsize_pipe <= AXI_ARSIZE;
axi_arlen_pipe <= AXI_ARLEN;
axi_arburst_pipe <= AXI_ARBURST;
else
axi_arsize_pipe <= axi_arsize_pipe;
axi_arlen_pipe <= axi_arlen_pipe;
axi_arburst_pipe <= axi_arburst_pipe;
end if;
end if;
end process REG_ARCTRL;
---------------------------------------------------------------------------
-- Create signals that indicate value of AXI_ARLEN in pipeline stage
-- Used to decode length of burst when BRAM address can be loaded early
-- when pipeline is full.
--
-- Add early decode of ARBURST in pipeline.
-- Copy logic from WR_CHNL module (similar logic).
-- Add early decode of ARSIZE = 4 bytes in pipeline.
REG_ARLEN_PIPE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- No reset condition to save resources/timing
if (araddr_pipe_ld = '1') then
-- Create merge to decode ARLEN of ONE or TWO
if (AXI_ARLEN = AXI_ARLEN_ONE) or (AXI_ARLEN = AXI_ARLEN_TWO) then
axi_arlen_pipe_1_or_2 <= '1';
else
axi_arlen_pipe_1_or_2 <= '0';
end if;
-- Early decode on value in pipeline of ARBURST
if (AXI_ARBURST = C_AXI_BURST_FIXED) then
axi_arburst_pipe_fixed <= '1';
else
axi_arburst_pipe_fixed <= '0';
end if;
else
axi_arlen_pipe_1_or_2 <= axi_arlen_pipe_1_or_2;
axi_arburst_pipe_fixed <= axi_arburst_pipe_fixed;
end if;
end if;
end process REG_ARLEN_PIPE;
---------------------------------------------------------------------------
-- Create full flag for ARADDR pipeline
-- Set when read address register is loaded.
-- Cleared when read address stored in register is loaded into BRAM
-- address counter.
REG_RDADDR_FULL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- (bram_addr_ld_en = '1' and araddr_pipe_sel = '1') then
(bram_addr_ld_en = '1' and araddr_pipe_sel = '1' and araddr_pipe_ld = '0') then
axi_araddr_full <= '0';
elsif (araddr_pipe_ld = '1') then
axi_araddr_full <= '1';
else
axi_araddr_full <= axi_araddr_full;
end if;
end if;
end process REG_RDADDR_FULL;
---------------------------------------------------------------------------
end generate GEN_AR_PIPE_DUAL;
---------------------------------------------------------------------------
-- v1.03a
-- Add early decode of ARSIZE = max size in pipeline based on AXI data
-- bus width (use constant, C_AXI_SIZE_MAX)
REG_ARSIZE_PIPE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_arsize_pipe_max <= '0';
elsif (araddr_pipe_ld = '1') then
-- Early decode of ARSIZE in pipeline equal to max # of bytes
-- based on AXI data bus width
if (AXI_ARSIZE = C_AXI_SIZE_MAX) then
axi_arsize_pipe_max <= '1';
else
axi_arsize_pipe_max <= '0';
end if;
else
axi_arsize_pipe_max <= axi_arsize_pipe_max;
end if;
end if;
end process REG_ARSIZE_PIPE;
---------------------------------------------------------------------------
-- Generate: GE_ARREADY
-- Purpose: ARREADY is only created here when in dual port BRAM mode.
---------------------------------------------------------------------------
GEN_ARREADY: if (C_SINGLE_PORT_BRAM = 0) generate
begin
----------------------------------------------------------------------------
-- AXI_ARREADY Output Register
-- Description: Keep AXI_ARREADY output asserted until ARADDR pipeline
-- is full. When a full condition is reached, negate
-- ARREADY as another AR address can not be accepted.
-- Add condition to keep ARReady asserted if loading current
--- ARADDR pipeline value into the BRAM address counter.
-- Indicated by assertion of bram_addr_ld_en & araddr_pipe_sel.
--
----------------------------------------------------------------------------
REG_ARREADY: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_arready_int <= '0';
-- Detect end of S_AXI_AResetn to assert AWREADY and accept
-- new AWADDR values
elsif (axi_aresetn_re_reg = '1') or
-- Add condition for early ARREADY to keep pipeline full
(bram_addr_ld_en = '1' and araddr_pipe_sel = '1' and axi_early_arready_int = '0') then
axi_arready_int <= '1';
-- Add conditional check if ARREADY is asserted (with ARVALID) (one clock cycle later)
-- when the address pipeline is full.
elsif (araddr_pipe_ld = '1') or
(AXI_ARVALID = '1' and axi_arready_int = '1' and axi_araddr_full = '1') then
axi_arready_int <= '0';
else
axi_arready_int <= axi_arready_int;
end if;
end if;
end process REG_ARREADY;
----------------------------------------------------------------------------
REG_EARLY_ARREADY: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_early_arready_int <= '0';
-- Pending ARADDR and ARREADY is not yet asserted to accept
-- operation (due to ARADDR being full)
elsif (AXI_ARVALID = '1' and axi_arready_int = '0' and
axi_araddr_full = '1') and
(alast_bram_addr = '1') and
-- Add check for elgible back-to-back BRAM load
(rd_b2b_elgible = '1') then
axi_early_arready_int <= '1';
else
axi_early_arready_int <= '0';
end if;
end if;
end process REG_EARLY_ARREADY;
---------------------------------------------------------------------------
-- Need to detect end of reset cycle to assert ARREADY on AXI bus
REG_ARESETN: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
axi_aresetn_d1 <= S_AXI_AResetn;
axi_aresetn_d2 <= axi_aresetn_d1;
axi_aresetn_re_reg <= axi_aresetn_re;
end if;
end process REG_ARESETN;
-- Create combinatorial RE detect of S_AXI_AResetn
axi_aresetn_re <= '1' when (S_AXI_AResetn = '1' and axi_aresetn_d1 = '0') else '0';
----------------------------------------------------------------------------
end generate GEN_ARREADY;
---------------------------------------------------------------------------
-- Generate: GEN_DUAL_ADDR_CNT
-- Purpose: Instantiate BRAM address counter unique for wr_chnl logic
-- only when controller configured in dual port mode.
---------------------------------------------------------------------------
GEN_DUAL_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
---------------------------------------------------------------------------
-- Replace I_ADDR_CNT module usage of pf_counter in proc_common library.
-- Only need to use lower 12-bits of address due to max AXI burst size
-- Since AXI guarantees bursts do not cross 4KB boundary, the counting part
-- of I_ADDR_CNT can be reduced to max 4KB.
--
-- No reset on bram_addr_int.
-- Increment ONLY.
REG_ADDR_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (bram_addr_ld_en_mod = '1') then
bram_addr_int <= bram_addr_ld;
elsif (bram_addr_inc_mod = '1') then
bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12) <=
bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12);
bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR) <=
std_logic_vector (unsigned (bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR)) + 1);
end if;
end if;
end process REG_ADDR_CNT;
---------------------------------------------------------------------------
-- Set defaults to shared address counter
-- Only used in single port configurations
Sng_BRAM_Addr_Ld_En <= '0';
Sng_BRAM_Addr_Ld <= (others => '0');
Sng_BRAM_Addr_Inc <= '0';
end generate GEN_DUAL_ADDR_CNT;
---------------------------------------------------------------------------
-- Generate: GEN_SNG_ADDR_CNT
-- Purpose: When configured in single port BRAM mode, address counter
-- is shared with rd_chnl module. Assign output signals here
-- to counter instantiation at full_axi module level.
---------------------------------------------------------------------------
GEN_SNG_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
Sng_BRAM_Addr_Ld_En <= bram_addr_ld_en_mod;
Sng_BRAM_Addr_Ld <= bram_addr_ld;
Sng_BRAM_Addr_Inc <= bram_addr_inc_mod;
bram_addr_int <= Sng_BRAM_Addr;
end generate GEN_SNG_ADDR_CNT;
---------------------------------------------------------------------------
-- BRAM address load mux.
-- Either load BRAM counter directly from AXI bus or from stored registered value
-- Use registered signal to indicate current operation is a WRAP burst
--
-- Match bram_addr_ld to what asserts bram_addr_ld_en_mod
-- Include bram_addr_inc_mod when asserted to use bram_addr_ld_wrap value
-- (otherwise use pipelined or AXI bus value to load BRAM address counter)
bram_addr_ld <= bram_addr_ld_wrap when (max_wrap_burst = '1' and
curr_wrap_burst_reg = '1' and
bram_addr_inc_wrap_mod = '1') else
axi_araddr_pipe (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
when (araddr_pipe_sel = '1') else
AXI_ARADDR (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR);
---------------------------------------------------------------------------
-- On wrap burst max loads (simultaneous BRAM address increment is asserted).
-- Ensure that load has higher priority over increment.
-- Use registered signal to indicate current operation is a WRAP burst
bram_addr_ld_en_mod <= '1' when (bram_addr_ld_en = '1' or
(max_wrap_burst = '1' and
curr_wrap_burst_reg = '1' and
bram_addr_inc_wrap_mod = '1'))
else '0';
-- Create a special bram_addr_inc_mod for use in the bram_addr_ld_en_mod signal
-- logic. No need for the check if the current operation is NOT a fixed AND a wrap
-- burst. The transfer will be one or the other.
-- Found issue when narrow FIXED length burst is incorrectly
-- incrementing BRAM address counter
bram_addr_inc_wrap_mod <= bram_addr_inc when (curr_narrow_burst = '0')
else narrow_bram_addr_inc_re;
----------------------------------------------------------------------------
-- Narrow bursting
--
-- Handle read burst addressing on narrow burst operations
-- Intercept BRAM address increment flag, bram_addr_inc and only
-- increment address when the number of BRAM reads match the width of the
-- AXI data bus.
-- For a 32-bit BRAM, byte burst will increment the BRAM address
-- after four reads from BRAM.
-- For a 256-bit BRAM, a byte burst will increment the BRAM address
-- after 32 reads from BRAM.
-- Based on current operation being a narrow burst, hold off BRAM
-- address increment until narrow burst fits BRAM data width.
-- For non narrow burst operations, use bram_addr_inc from data SM.
--
-- Add in check that burst type is not FIXED, curr_fixed_burst_reg
-- bram_addr_inc_mod <= (bram_addr_inc and not (curr_fixed_burst_reg)) when (curr_narrow_burst = '0') else
-- narrow_bram_addr_inc_re;
--
--
-- Replace w/ below generate statements based on supporting narrow transfers or not.
-- Create generate statement around the signal assignment for bram_addr_inc_mod.
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_INC_MOD_W_NARROW
-- Purpose: Assign signal, bram_addr_inc_mod when narrow transfers
-- are supported in design instantiation.
---------------------------------------------------------------------------
GEN_BRAM_INC_MOD_W_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
-- Found issue when narrow FIXED length burst is incorrectly incrementing BRAM address counter
bram_addr_inc_mod <= (bram_addr_inc and not (curr_fixed_burst_reg)) when (curr_narrow_burst = '0') else
(narrow_bram_addr_inc_re and not (curr_fixed_burst_reg));
end generate GEN_BRAM_INC_MOD_W_NARROW;
---------------------------------------------------------------------------
-- Generate: GEN_WO_NARROW
-- Purpose: Assign signal, bram_addr_inc_mod when narrow transfers
-- are not supported in the design instantiation.
-- Drive default values for narrow counter and logic when
-- narrow operation support is disabled.
---------------------------------------------------------------------------
GEN_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 0) generate
begin
-- Found issue when narrow FIXED length burst is incorrectly incrementing BRAM address counter
bram_addr_inc_mod <= bram_addr_inc and not (curr_fixed_burst_reg);
narrow_addr_rst <= '0';
narrow_burst_cnt_ld_mod <= (others => '0');
narrow_addr_dec <= '0';
narrow_addr_ld_en <= '0';
narrow_bram_addr_inc <= '0';
narrow_bram_addr_inc_d1 <= '0';
narrow_bram_addr_inc_re <= '0';
narrow_addr_int <= (others => '0');
curr_narrow_burst <= '0';
end generate GEN_WO_NARROW;
---------------------------------------------------------------------------
--
-- Only instantiate NARROW_CNT and supporting logic when narrow transfers
-- are supported and utilized by masters in the AXI system.
-- The design parameter, C_S_AXI_SUPPORTS_NARROW will indicate this.
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_NARROW_CNT
-- Purpose: Instantiate narrow counter and logic when narrow
-- operation support is enabled.
---------------------------------------------------------------------------
GEN_NARROW_CNT: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
---------------------------------------------------------------------------
--
-- Generate seperate smaller counter for narrow burst operations
-- Replace I_NARROW_CNT module usage of pf_counter_top from proc_common library.
--
-- Counter size is adjusted based on size of data burst.
--
-- For example, 32-bit data width BRAM, minimum narrow width
-- burst is 8 bits resulting in a count 3 downto 0. So the
-- minimum counter width = 2 bits.
--
-- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst
-- is 8 bits resulting in a count 31 downto 0. So the
-- minimum counter width = 5 bits.
--
-- Size of counter = C_NARROW_BURST_CNT_LEN
--
---------------------------------------------------------------------------
REG_NARROW_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (narrow_addr_rst = '1') then
narrow_addr_int <= (others => '0');
-- Load enable
elsif (narrow_addr_ld_en = '1') then
narrow_addr_int <= narrow_burst_cnt_ld_mod;
-- Decrement ONLY (no increment functionality)
elsif (narrow_addr_dec = '1') then
narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0) <=
std_logic_vector (unsigned (narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0)) - 1);
end if;
end if;
end process REG_NARROW_CNT;
---------------------------------------------------------------------------
narrow_addr_rst <= not (S_AXI_AResetn);
-- Modify narrow burst count load value based on
-- unalignment of AXI address value
narrow_burst_cnt_ld_mod <= ua_narrow_load when (curr_ua_narrow_wrap = '1' or curr_ua_narrow_incr = '1') else
narrow_burst_cnt_ld when (bram_addr_ld_en = '1') else
narrow_burst_cnt_ld_reg;
narrow_addr_dec <= bram_addr_inc when (curr_narrow_burst = '1') else '0';
narrow_addr_ld_en <= (curr_narrow_burst_cmb and bram_addr_ld_en) or narrow_bram_addr_inc_re;
narrow_bram_addr_inc <= '1' when (narrow_addr_int = NARROW_CNT_MAX) and
(curr_narrow_burst = '1')
-- Ensure that narrow address counter doesn't
-- flag max or get loaded to
-- reset narrow counter until AXI read data
-- bus has acknowledged current
-- data on the AXI bus. Use rd_adv_buf signal
-- to indicate the non throttle
-- condition on the AXI bus.
and (bram_addr_inc = '1')
else '0';
----------------------------------------------------------------------------
-- Detect rising edge of narrow_bram_addr_inc
REG_NARROW_BRAM_ADDR_INC: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
narrow_bram_addr_inc_d1 <= '0';
else
narrow_bram_addr_inc_d1 <= narrow_bram_addr_inc;
end if;
end if;
end process REG_NARROW_BRAM_ADDR_INC;
narrow_bram_addr_inc_re <= '1' when (narrow_bram_addr_inc = '1') and
(narrow_bram_addr_inc_d1 = '0')
else '0';
---------------------------------------------------------------------------
end generate GEN_NARROW_CNT;
----------------------------------------------------------------------------
-- Specify current ARSIZE signal
-- Address pipeline MUX
curr_arsize <= axi_arsize_pipe when (araddr_pipe_sel = '1') else AXI_ARSIZE;
REG_ARSIZE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
curr_arsize_reg <= (others => '0');
-- Register curr_arsize when bram_addr_ld_en = '1'
elsif (bram_addr_ld_en = '1') then
curr_arsize_reg <= curr_arsize;
else
curr_arsize_reg <= curr_arsize_reg;
end if;
end if;
end process REG_ARSIZE;
---------------------------------------------------------------------------
-- Generate: GEN_NARROW_EN
-- Purpose: Only instantiate logic to determine if current burst
-- is a narrow burst when narrow bursting logic is supported.
---------------------------------------------------------------------------
GEN_NARROW_EN: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
-----------------------------------------------------------------------
-- Determine "narrow" burst transfers
-- Compare the ARSIZE to the BRAM data width
-----------------------------------------------------------------------
-- v1.03a
-- Detect if current burst operation is of size /= to the full
-- AXI data bus width. If not, then the current operation is a
-- "narrow" burst.
curr_narrow_burst_cmb <= '1' when (curr_arsize /= C_AXI_SIZE_MAX) else '0';
---------------------------------------------------------------------------
-- Register flag indicating the current operation
-- is a narrow read burst
NARROW_BURST_REG: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- Need to reset this flag at end of narrow burst operation
-- Ensure if curr_narrow_burst got set during previous transaction, axi_rlast_set
-- doesn't clear the flag (add check for pend_rd_op negated).
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_set = '1' and pend_rd_op = '0' and bram_addr_ld_en = '0') then
curr_narrow_burst <= '0';
-- Add check for burst operation using ARLEN value
-- Ensure that narrow burst flag does not get set during FIXED burst types
elsif (bram_addr_ld_en = '1') and (curr_arlen /= AXI_ARLEN_ONE) and
(curr_fixed_burst = '0') then
curr_narrow_burst <= curr_narrow_burst_cmb;
end if;
end if;
end process NARROW_BURST_REG;
end generate GEN_NARROW_EN;
---------------------------------------------------------------------------
-- Generate: GEN_NARROW_CNT_LD
-- Purpose: Only instantiate logic to determine narrow burst counter
-- load value when narrow bursts are enabled.
---------------------------------------------------------------------------
GEN_NARROW_CNT_LD: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
signal curr_arsize_unsigned : unsigned (2 downto 0) := (others => '0');
signal axi_byte_div_curr_arsize : integer := 1;
begin
-- v1.03a
-- Create narrow burst counter load value based on current operation
-- "narrow" data width (indicated by value of AWSIZE).
curr_arsize_unsigned <= unsigned (curr_arsize);
-- XST does not support divisors that are not constants and powers of 2.
-- Create process to create a fixed value for divisor.
-- Replace this statement:
-- narrow_burst_cnt_ld <= std_logic_vector (
-- to_unsigned (
-- (C_AXI_DATA_WIDTH_BYTES / (2**(to_integer (curr_arsize_unsigned))) ) - 1,
-- C_NARROW_BURST_CNT_LEN));
-- -- With this new process and subsequent signal assignment:
-- DIV_AWSIZE: process (curr_arsize_unsigned)
-- begin
--
-- case (to_integer (curr_arsize_unsigned)) is
-- when 0 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 1;
-- when 1 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 2;
-- when 2 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 4;
-- when 3 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 8;
-- when 4 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 16;
-- when 5 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 32;
-- when 6 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 64;
-- when 7 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 128;
-- --coverage off
-- when others => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES;
-- --coverage on
-- end case;
--
-- end process DIV_AWSIZE;
-- w/ CR # 609695
-- With this new process and subsequent signal assignment:
DIV_AWSIZE: process (curr_arsize_unsigned)
begin
case (curr_arsize_unsigned) is
when "000" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 1;
when "001" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 2;
when "010" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 4;
when "011" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 8;
when "100" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 16;
when "101" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 32;
when "110" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 64;
when "111" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 128;
--coverage off
when others => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES;
--coverage on
end case;
end process DIV_AWSIZE;
-- v1.03a
-- Replace with new signal assignment.
-- For synthesis to support only divisors that are constant and powers of two.
-- Updated else clause for simulation warnings w/ CR # 609695
narrow_burst_cnt_ld <= std_logic_vector (
to_unsigned (
(axi_byte_div_curr_arsize) - 1, C_NARROW_BURST_CNT_LEN))
when (axi_byte_div_curr_arsize > 0)
else std_logic_vector (to_unsigned (0, C_NARROW_BURST_CNT_LEN));
---------------------------------------------------------------------------
-- Register narrow burst count load indicator
REG_NAR_BRST_CNT_LD: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
narrow_burst_cnt_ld_reg <= (others => '0');
elsif (bram_addr_ld_en = '1') then
narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld;
else
narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld_reg;
end if;
end if;
end process REG_NAR_BRST_CNT_LD;
---------------------------------------------------------------------------
end generate GEN_NARROW_CNT_LD;
----------------------------------------------------------------------------
-- Handling for WRAP burst types
--
-- For WRAP burst types, the counter value will roll over when the burst
-- boundary is reached.
-- Boundary is reached based on ARSIZE and ARLEN.
--
-- Goal is to minimize muxing on initial load of counter value.
-- On WRAP burst types, detect when the max address is reached.
-- When the max address is reached, re-load counter with lower
-- address value set to '0'.
----------------------------------------------------------------------------
-- Detect valid WRAP burst types
curr_wrap_burst <= '1' when (curr_arburst = C_AXI_BURST_WRAP) else '0';
curr_incr_burst <= '1' when (curr_arburst = C_AXI_BURST_INCR) else '0';
curr_fixed_burst <= '1' when (curr_arburst = C_AXI_BURST_FIXED) else '0';
----------------------------------------------------------------------------
-- Register curr_wrap_burst & curr_fixed_burst signals when BRAM
-- address counter is initially loaded
REG_CURR_BRST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
curr_wrap_burst_reg <= '0';
curr_fixed_burst_reg <= '0';
elsif (bram_addr_ld_en = '1') then
curr_wrap_burst_reg <= curr_wrap_burst;
curr_fixed_burst_reg <= curr_fixed_burst;
else
curr_wrap_burst_reg <= curr_wrap_burst_reg;
curr_fixed_burst_reg <= curr_fixed_burst_reg;
end if;
end if;
end process REG_CURR_BRST;
---------------------------------------------------------------------------
-- Instance: I_WRAP_BRST
--
-- Description:
--
-- Instantiate WRAP_BRST module
-- Logic to generate the wrap around value to load into the BRAM address
-- counter on WRAP burst transactions.
-- WRAP value is based on current ARLEN, ARSIZE (for narrows) and
-- data width of BRAM module.
--
---------------------------------------------------------------------------
I_WRAP_BRST : entity work.wrap_brst
generic map (
C_AXI_ADDR_WIDTH => C_AXI_ADDR_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH
)
port map (
S_AXI_AClk => S_AXI_ACLK ,
S_AXI_AResetn => S_AXI_ARESETN ,
curr_axlen => curr_arlen ,
curr_axsize => curr_arsize ,
curr_narrow_burst => curr_narrow_burst ,
narrow_bram_addr_inc_re => narrow_bram_addr_inc_re ,
bram_addr_ld_en => bram_addr_ld_en ,
bram_addr_ld => bram_addr_ld ,
bram_addr_int => bram_addr_int ,
bram_addr_ld_wrap => bram_addr_ld_wrap ,
max_wrap_burst_mod => max_wrap_burst
);
----------------------------------------------------------------------------
-- Specify current ARBURST signal
-- Input address pipeline MUX
curr_arburst <= axi_arburst_pipe when (araddr_pipe_sel = '1') else AXI_ARBURST;
----------------------------------------------------------------------------
-- Specify current AWBURST signal
-- Input address pipeline MUX
curr_arlen <= axi_arlen_pipe when (araddr_pipe_sel = '1') else AXI_ARLEN;
----------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_UA_NARROW
-- Purpose: Only instantiate logic for burst narrow WRAP operations when
-- AXI bus protocol is not set for AXI-LITE and narrow
-- burst operations are supported.
--
---------------------------------------------------------------------------
GEN_UA_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
---------------------------------------------------------------------------
--
-- New logic to detect unaligned address on a narrow WRAP burst transaction.
-- If this condition is met, then the narrow burst counter will be
-- initially loaded with an offset value corresponding to the unalignment
-- in the ARADDR value.
--
--
-- Create a sub module for all logic to determine the narrow burst counter
-- offset value on unaligned WRAP burst operations.
--
-- Module generates the following signals:
--
-- => curr_ua_narrow_wrap, to indicate the current
-- operation is an unaligned narrow WRAP burst.
--
-- => curr_ua_narrow_incr, to load narrow burst counter
-- for unaligned INCR burst operations.
--
-- => ua_narrow_load, narrow counter load value.
-- Sized, (C_NARROW_BURST_CNT_LEN-1 downto 0)
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Instance: I_UA_NARROW
--
-- Description:
--
-- Creates a narrow burst count load value when an operation
-- is an unaligned narrow WRAP or INCR burst type. Used by
-- I_NARROW_CNT module.
--
-- Logic is customized for each C_AXI_DATA_WIDTH.
--
---------------------------------------------------------------------------
I_UA_NARROW : entity work.ua_narrow
generic map (
C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_NARROW_BURST_CNT_LEN => C_NARROW_BURST_CNT_LEN
)
port map (
curr_wrap_burst => curr_wrap_burst , -- in
curr_incr_burst => curr_incr_burst , -- in
bram_addr_ld_en => bram_addr_ld_en , -- in
curr_axlen => curr_arlen , -- in
curr_axsize => curr_arsize , -- in
curr_axaddr_lsb => curr_araddr_lsb , -- in
curr_ua_narrow_wrap => curr_ua_narrow_wrap , -- out
curr_ua_narrow_incr => curr_ua_narrow_incr , -- out
ua_narrow_load => ua_narrow_load -- out
);
-- Use in all C_AXI_DATA_WIDTH generate statements
-- Only probe least significant BRAM address bits
-- C_BRAM_ADDR_ADJUST_FACTOR offset down to 0.
curr_araddr_lsb <= axi_araddr_pipe (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0)
when (araddr_pipe_sel = '1') else
AXI_ARADDR (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0);
end generate GEN_UA_NARROW;
----------------------------------------------------------------------------
--
-- New logic to detect if pending operation in ARADDR pipeline is
-- elgible for back-to-back no "bubble" performance. And BRAM address
-- counter can be loaded upon last BRAM address presented for the current
-- operation.
-- This condition exists when the ARADDR pipeline is full and the pending
-- operation is a burst >= length of two data beats.
-- And not a FIXED burst type (must be INCR or WRAP type).
-- The DATA SM handles detecting a throttle condition and will void
-- the capability to be a back-to-back in performance transaction.
--
-- Add check if new operation is a narrow burst (to be loaded into BRAM
-- counter)
-- Add check for throttling condition on after last BRAM address is
-- presented
--
----------------------------------------------------------------------------
-- v1.03a
rd_b2b_elgible_no_thr_check <= '1' when (axi_araddr_full = '1') and
(axi_arlen_pipe_1_or_2 /= '1') and
(axi_arburst_pipe_fixed /= '1') and
(disable_b2b_brst = '0') and
(axi_arsize_pipe_max = '1')
else '0';
rd_b2b_elgible <= '1' when (rd_b2b_elgible_no_thr_check = '1') and
(throttle_last_data = '0')
else '0';
-- Check if SM is in LAST_THROTTLE state which also indicates we are throttling at
-- the last data beat in the read burst. Ensures that the bursts are not implemented
-- as back-to-back bursts and RVALID will negate upon recognition of RLAST and RID
-- pipeline will be advanced properly.
-- Fix timing path on araddr_pipe_sel generated in RDADDR SM
-- SM uses rd_b2b_elgible signal which checks throttle condition on
-- last data beat to hold off loading new BRAM address counter for next
-- back-to-back operation.
-- Attempt to modify logic in generation of throttle_last_data signal.
throttle_last_data <= '1' when ((brst_zero = '1') and (rd_adv_buf = '0')) or
(rd_data_sm_cs = LAST_THROTTLE)
else '0';
----------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_AR_SNG
-- Purpose: If single port BRAM configuration, set all AR flags from
-- logic generated in sng_port_arb module.
--
---------------------------------------------------------------------------
GEN_AR_SNG: if (C_SINGLE_PORT_BRAM = 1) generate
begin
araddr_pipe_sel <= '0'; -- Unused in single port configuration
ar_active <= Arb2AR_Active;
bram_addr_ld_en <= ar_active_re;
brst_cnt_ld_en <= ar_active_re;
AR2Arb_Active_Clr <= axi_rlast_int and AXI_RREADY;
-- Rising edge detect of Arb2AR_Active
RE_AR_ACT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- Clear ar_active_d1 early w/ ar_active
-- So back to back ar_active assertions see the new transaction
-- and initiate the read transfer.
if (S_AXI_AResetn = C_RESET_ACTIVE) or ((axi_rlast_int and AXI_RREADY) = '1') then
ar_active_d1 <= '0';
else
ar_active_d1 <= ar_active;
end if;
end if;
end process RE_AR_ACT;
ar_active_re <= '1' when (ar_active = '1' and ar_active_d1 = '0') else '0';
end generate GEN_AR_SNG;
---------------------------------------------------------------------------
--
-- Generate: GEN_AW_DUAL
-- Purpose: Generate AW control state machine logic only when AXI4
-- controller is configured for dual port mode. In dual port
-- mode, wr_chnl has full access over AW & port A of BRAM.
--
---------------------------------------------------------------------------
GEN_AR_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate
begin
AR2Arb_Active_Clr <= '0'; -- Only used in single port case
---------------------------------------------------------------------------
-- RD ADDR State Machine
--
-- Description: Central processing unit for AXI write address
-- channel interface handling and handshaking.
--
-- Outputs: araddr_pipe_ld Not Registered
-- araddr_pipe_sel Not Registered
-- bram_addr_ld_en Not Registered
-- brst_cnt_ld_en Not Registered
-- ar_active_set Not Registered
--
-- WR_ADDR_SM_CMB_PROCESS: Combinational process to determine next state.
-- WR_ADDR_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
RD_ADDR_SM_CMB_PROCESS: process ( AXI_ARVALID,
axi_araddr_full,
ar_active,
no_ar_ack,
pend_rd_op,
last_bram_addr,
rd_b2b_elgible,
rd_addr_sm_cs )
begin
-- assign default values for state machine outputs
rd_addr_sm_ns <= rd_addr_sm_cs;
araddr_pipe_ld_i <= '0';
bram_addr_ld_en_i <= '0';
brst_cnt_ld_en_i <= '0';
ar_active_set_i <= '0';
case rd_addr_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Reload BRAM address counter on last BRAM address of current burst
-- if a new address is pending in the AR pipeline and is elgible to
-- be loaded for subsequent back-to-back performance.
if (last_bram_addr = '1' and rd_b2b_elgible = '1') then
-- Load BRAM address counter from pipelined value
bram_addr_ld_en_i <= '1';
brst_cnt_ld_en_i <= '1';
ar_active_set_i <= '1';
-- If loading BRAM counter for subsequent operation
-- AND ARVALID is pending on the bus, go ahead and respond
-- and fill ARADDR pipeline with next operation.
--
-- Asserting the signal to load the ARADDR pipeline here
-- allows the full bandwidth utilization to BRAM on
-- back to back bursts of two data beats.
if (AXI_ARVALID = '1') then
araddr_pipe_ld_i <= '1';
rd_addr_sm_ns <= LD_ARADDR;
else
rd_addr_sm_ns <= IDLE;
end if;
elsif (AXI_ARVALID = '1') then
-- If address pipeline is full
-- ARReady output is negated
-- Remain in this state
--
-- Add check for already pending read operation
-- in data SM, but waiting on throttle (even though ar_active is
-- already set to '0').
if (ar_active = '0') and (no_ar_ack = '0') and (pend_rd_op = '0') then
rd_addr_sm_ns <= IDLE;
bram_addr_ld_en_i <= '1';
brst_cnt_ld_en_i <= '1';
ar_active_set_i <= '1';
-- Address counter is currently busy
else
-- Check if ARADDR pipeline is not full and can be loaded
if (axi_araddr_full = '0') then
rd_addr_sm_ns <= LD_ARADDR;
araddr_pipe_ld_i <= '1';
end if;
end if; -- ar_active
-- Pending operation in pipeline that is waiting
-- until current operation is complete (ar_active = '0')
elsif (axi_araddr_full = '1') and
(ar_active = '0') and
(no_ar_ack = '0') and
(pend_rd_op = '0') then
rd_addr_sm_ns <= IDLE;
-- Load BRAM address counter from pipelined value
bram_addr_ld_en_i <= '1';
brst_cnt_ld_en_i <= '1';
ar_active_set_i <= '1';
end if; -- ARVALID
---------------------------- LD_ARADDR State ---------------------------
when LD_ARADDR =>
-- Check here for subsequent BRAM address load when ARADDR pipe is loaded
-- in previous clock cycle.
--
-- Reload BRAM address counter on last BRAM address of current burst
-- if a new address is pending in the AR pipeline and is elgible to
-- be loaded for subsequent back-to-back performance.
if (last_bram_addr = '1' and rd_b2b_elgible = '1') then
-- Load BRAM address counter from pipelined value
bram_addr_ld_en_i <= '1';
brst_cnt_ld_en_i <= '1';
ar_active_set_i <= '1';
-- If loading BRAM counter for subsequent operation
-- AND ARVALID is pending on the bus, go ahead and respond
-- and fill ARADDR pipeline with next operation.
--
-- Asserting the signal to load the ARADDR pipeline here
-- allows the full bandwidth utilization to BRAM on
-- back to back bursts of two data beats.
if (AXI_ARVALID = '1') then
araddr_pipe_ld_i <= '1';
rd_addr_sm_ns <= LD_ARADDR;
-- Stay in this state another clock cycle
else
rd_addr_sm_ns <= IDLE;
end if;
else
rd_addr_sm_ns <= IDLE;
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
rd_addr_sm_ns <= IDLE;
--coverage on
end case;
end process RD_ADDR_SM_CMB_PROCESS;
---------------------------------------------------------------------------
-- CR # 582705
-- Ensure combinatorial SM output signals do not get set before
-- the end of the reset (and ARREAADY can be set).
bram_addr_ld_en <= bram_addr_ld_en_i and axi_aresetn_d2;
brst_cnt_ld_en <= brst_cnt_ld_en_i and axi_aresetn_d2;
ar_active_set <= ar_active_set_i and axi_aresetn_d2;
araddr_pipe_ld <= araddr_pipe_ld_i and axi_aresetn_d2;
RD_ADDR_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- if (S_AXI_AResetn = C_RESET_ACTIVE) then
-- CR # 582705
-- Ensure that ar_active does not get asserted (from SM) before
-- the end of reset and the ARREADY flag is set.
if (axi_aresetn_d2 = C_RESET_ACTIVE) then
rd_addr_sm_cs <= IDLE;
else
rd_addr_sm_cs <= rd_addr_sm_ns;
end if;
end if;
end process RD_ADDR_SM_REG_PROCESS;
---------------------------------------------------------------------------
-- Assert araddr_pipe_sel outside of SM logic
-- The BRAM address counter will get loaded with value in ARADDR pipeline
-- when data is stored in the ARADDR pipeline.
araddr_pipe_sel <= '1' when (axi_araddr_full = '1') else '0';
---------------------------------------------------------------------------
-- Register for ar_active
REG_AR_ACT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- if (S_AXI_AResetn = C_RESET_ACTIVE) then
-- CR # 582705
if (axi_aresetn_d2 = C_RESET_ACTIVE) then
ar_active <= '0';
elsif (ar_active_set = '1') then
ar_active <= '1';
-- For code coverage closure, ensure priority encoding in if/else clause
-- to prevent checking ar_active_set in reset clause.
elsif (ar_active_clr = '1') then
ar_active <= '0';
else
ar_active <= ar_active;
end if;
end if;
end process REG_AR_ACT;
end generate GEN_AR_DUAL;
---------------------------------------------------------------------------
--
-- REG_BRST_CNT.
-- Read Burst Counter.
-- No need to decrement burst counter.
-- Able to load with fixed burst length value.
-- Replace usage of proc_common_v4_0_2 library with direct HDL.
--
-- Size of counter = C_BRST_CNT_SIZE
-- Max size of burst transfer = 256 data beats
--
---------------------------------------------------------------------------
REG_BRST_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (brst_cnt_rst = '1') then
brst_cnt <= (others => '0');
-- Load burst counter
elsif (brst_cnt_ld_en = '1') then
brst_cnt <= brst_cnt_ld;
-- Decrement ONLY (no increment functionality)
elsif (brst_cnt_dec = '1') then
brst_cnt (C_BRST_CNT_SIZE-1 downto 0) <=
std_logic_vector (unsigned (brst_cnt (C_BRST_CNT_SIZE-1 downto 0)) - 1);
end if;
end if;
end process REG_BRST_CNT;
---------------------------------------------------------------------------
brst_cnt_rst <= not (S_AXI_AResetn);
-- Determine burst count load value
-- Either load BRAM counter directly from AXI bus or from stored registered value.
-- Use mux signal for ARLEN
BRST_CNT_LD_PROCESS : process (curr_arlen)
variable brst_cnt_ld_int : integer := 0;
begin
brst_cnt_ld_int := to_integer (unsigned (curr_arlen (7 downto 0)));
brst_cnt_ld <= std_logic_vector (to_unsigned (brst_cnt_ld_int, 8));
end process BRST_CNT_LD_PROCESS;
----------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_BRST_MAX_W_NARROW
-- Purpose: Generate registered logic for brst_cnt_max when the
-- design instantiation supports narrow operations.
--
---------------------------------------------------------------------------
GEN_BRST_MAX_W_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
REG_BRST_MAX: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_cnt_ld_en = '1')
-- Added with single port (13.1 release)
or (end_brst_rd_clr = '1') then
brst_cnt_max <= '0';
-- Replace usage of brst_cnt in this logic.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
elsif (brst_zero = '1') and (ar_active = '1') and (pend_rd_op = '0') then
-- Hold off assertion of brst_cnt_max on narrow burst transfers
-- Must wait until narrow burst count = 0.
if (curr_narrow_burst = '1') then
if (narrow_bram_addr_inc = '1') then
brst_cnt_max <= '1';
end if;
else
brst_cnt_max <= '1';
end if;
else
brst_cnt_max <= brst_cnt_max;
end if;
end if;
end process REG_BRST_MAX;
end generate GEN_BRST_MAX_W_NARROW;
---------------------------------------------------------------------------
--
-- Generate: GEN_BRST_MAX_WO_NARROW
-- Purpose: Generate registered logic for brst_cnt_max when the
-- design instantiation does not support narrow operations.
--
---------------------------------------------------------------------------
GEN_BRST_MAX_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 0) generate
begin
REG_BRST_MAX: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_cnt_ld_en = '1') then
brst_cnt_max <= '0';
-- Replace usage of brst_cnt in this logic.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
elsif (brst_zero = '1') and (ar_active = '1') and (pend_rd_op = '0') then
-- When narrow operations are not supported in the core
-- configuration, no check for curr_narrow_burst on assertion.
brst_cnt_max <= '1';
else
brst_cnt_max <= brst_cnt_max;
end if;
end if;
end process REG_BRST_MAX;
end generate GEN_BRST_MAX_WO_NARROW;
---------------------------------------------------------------------------
REG_BRST_MAX_D1: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
brst_cnt_max_d1 <= '0';
else
brst_cnt_max_d1 <= brst_cnt_max;
end if;
end if;
end process REG_BRST_MAX_D1;
brst_cnt_max_re <= '1' when (brst_cnt_max = '1') and (brst_cnt_max_d1 = '0') else '0';
-- Set flag that end of burst is reached
-- Need to capture this condition as the burst
-- counter may get reloaded for a subsequent read burst
REG_END_BURST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- SM may assert clear flag early (in case of narrow bursts)
-- Wait until the end_brst_rd flag is asserted to clear the flag.
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(end_brst_rd_clr = '1' and end_brst_rd = '1') then
end_brst_rd <= '0';
elsif (brst_cnt_max_re = '1') then
end_brst_rd <= '1';
end if;
end if;
end process REG_END_BURST;
---------------------------------------------------------------------------
-- Create flag that indicates burst counter is reaching ZEROs (max of burst
-- length)
REG_BURST_ZERO: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
((brst_cnt_ld_en = '1') and (brst_cnt_ld /= C_BRST_CNT_ZERO)) then
brst_zero <= '0';
elsif (brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_ONE) then
brst_zero <= '1';
else
brst_zero <= brst_zero;
end if;
end if;
end process REG_BURST_ZERO;
---------------------------------------------------------------------------
-- Create additional flag that indicates burst counter is reaching ONEs
-- (near end of burst length). Used to disable back-to-back condition in SM.
REG_BURST_ONE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
((brst_cnt_ld_en = '1') and (brst_cnt_ld /= C_BRST_CNT_ONE)) or
((brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_ONE)) then
brst_one <= '0';
elsif ((brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_TWO)) or
((brst_cnt_ld_en = '1') and (brst_cnt_ld = C_BRST_CNT_ONE)) then
brst_one <= '1';
else
brst_one <= brst_one;
end if;
end if;
end process REG_BURST_ONE;
---------------------------------------------------------------------------
-- Register flags for read burst operation
REG_RD_BURST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- Clear axi_rd_burst flags when burst count gets to zeros (unless the burst
-- counter is getting subsequently loaded for the new burst operation)
--
-- Replace usage of brst_cnt in this logic.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_zero = '1' and brst_cnt_ld_en = '0') then
axi_rd_burst <= '0';
axi_rd_burst_two <= '0';
elsif (brst_cnt_ld_en = '1') then
if (curr_arlen /= AXI_ARLEN_ONE and curr_arlen /= AXI_ARLEN_TWO) then
axi_rd_burst <= '1';
else
axi_rd_burst <= '0';
end if;
if (curr_arlen = AXI_ARLEN_TWO) then
axi_rd_burst_two <= '1';
else
axi_rd_burst_two <= '0';
end if;
else
axi_rd_burst <= axi_rd_burst;
axi_rd_burst_two <= axi_rd_burst_two;
end if;
end if;
end process REG_RD_BURST;
---------------------------------------------------------------------------
-- Seeing issue with axi_rd_burst getting cleared too soon
-- on subsquent brst_cnt_ld_en early assertion and pend_rd_op is asserted.
-- Create flag for currently active read burst operation
-- Gets asserted when burst counter is loaded, but does not
-- get cleared until the RD_DATA_SM has completed the read
-- burst operation
REG_ACT_RD_BURST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or (act_rd_burst_clr = '1') then
act_rd_burst <= '0';
act_rd_burst_two <= '0';
elsif (act_rd_burst_set = '1') then
-- If not loading the burst counter for a B2B operation
-- Then act_rd_burst follows axi_rd_burst and
-- act_rd_burst_two follows axi_rd_burst_two.
-- Get registered value of axi_* signal.
if (brst_cnt_ld_en = '0') then
act_rd_burst <= axi_rd_burst;
act_rd_burst_two <= axi_rd_burst_two;
else
-- Otherwise, duplicate logic for axi_* signals if burst counter
-- is getting loaded.
-- For improved code coverage here
-- The act_rd_burst_set signal will never get asserted if the burst
-- size is less than two data beats. So, the conditional check
-- for (curr_arlen /= AXI_ARLEN_ONE) is never evaluated. Removed
-- from this if clause.
if (curr_arlen /= AXI_ARLEN_TWO) then
act_rd_burst <= '1';
else
act_rd_burst <= '0';
end if;
if (curr_arlen = AXI_ARLEN_TWO) then
act_rd_burst_two <= '1';
else
act_rd_burst_two <= '0';
end if;
-- Note: re-code this if/else clause.
end if;
else
act_rd_burst <= act_rd_burst;
act_rd_burst_two <= act_rd_burst_two;
end if;
end if;
end process REG_ACT_RD_BURST;
---------------------------------------------------------------------------
rd_adv_buf <= axi_rvalid_int and AXI_RREADY;
---------------------------------------------------------------------------
-- RD DATA State Machine
--
-- Description: Central processing unit for AXI write data
-- channel interface handling and AXI write data response
-- handshaking.
--
-- Outputs: Name Type
--
-- bram_en_int Registered
-- bram_addr_inc Not Registered
-- brst_cnt_dec Not Registered
-- rddata_mux_sel Registered
-- axi_rdata_en Not Registered
-- axi_rvalid_set Registered
--
--
-- RD_DATA_SM_CMB_PROCESS: Combinational process to determine next state.
-- RD_DATA_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
RD_DATA_SM_CMB_PROCESS: process ( bram_addr_ld_en,
rd_adv_buf,
ar_active,
axi_araddr_full,
rd_b2b_elgible_no_thr_check,
disable_b2b_brst,
curr_arlen,
axi_rd_burst,
axi_rd_burst_two,
act_rd_burst,
act_rd_burst_two,
end_brst_rd,
brst_zero,
brst_one,
axi_b2b_brst,
bram_en_int,
rddata_mux_sel,
end_brst_rd_clr,
no_ar_ack,
pend_rd_op,
axi_rlast_int,
rd_data_sm_cs )
begin
-- assign default values for state machine outputs
rd_data_sm_ns <= rd_data_sm_cs;
bram_en_cmb <= bram_en_int;
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
rd_skid_buf_ld_cmb <= '0';
rd_skid_buf_ld_imm <= '0';
rddata_mux_sel_cmb <= rddata_mux_sel;
-- Change axi_rdata_en generated from SM to be a combinatorial signal
-- Can't afford the latency when throttling on the AXI bus.
axi_rdata_en <= '0';
axi_rvalid_set_cmb <= '0';
end_brst_rd_clr_cmb <= end_brst_rd_clr;
no_ar_ack_cmb <= no_ar_ack;
pend_rd_op_cmb <= pend_rd_op;
act_rd_burst_set <= '0';
act_rd_burst_clr <= '0';
set_last_bram_addr <= '0';
alast_bram_addr <= '0';
axi_b2b_brst_cmb <= axi_b2b_brst;
disable_b2b_brst_cmb <= disable_b2b_brst;
ar_active_clr <= '0';
case rd_data_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Initiate BRAM read when address is available in controller
-- Indicated by load of BRAM address counter
-- Remove use of pend_rd_op signal.
-- Never asserted as we transition back to IDLE
-- Detected in code coverage
if (bram_addr_ld_en = '1') then
-- At start of new read, clear end burst signal
end_brst_rd_clr_cmb <= '0';
-- Initiate BRAM read transfer
bram_en_cmb <= '1';
-- Only count addresses & burst length for read
-- burst operations
-- If currently loading BRAM address counter
-- Must check curr_arlen (mux output from pipe or AXI bus)
-- to determine length of next operation.
-- If ARLEN = 1 data beat, then set last_bram_addr signal
-- Otherwise, increment BRAM address counter.
if (curr_arlen /= AXI_ARLEN_ONE) then
-- Start of new operation, update act_rd_burst and
-- act_rd_burst_two signals
act_rd_burst_set <= '1';
else
-- Set flag for last_bram_addr on transition
-- to SNG_ADDR on single operations.
set_last_bram_addr <= '1';
end if;
-- Go to single active read address state
rd_data_sm_ns <= SNG_ADDR;
end if;
------------------------- SNG_ADDR State --------------------------
when SNG_ADDR =>
-- Clear flag once pending read is recognized
-- Duplicate logic here in case combinatorial flag was getting
-- set as the SM transitioned into this state.
if (pend_rd_op = '1') then
pend_rd_op_cmb <= '0';
end if;
-- At start of new read, clear end burst signal
end_brst_rd_clr_cmb <= '0';
-- Reach this state on first BRAM address & enable assertion
-- For burst operation, create next BRAM address and keep enable
-- asserted
-- Note:
-- No ability to throttle yet as RVALID has not yet been
-- asserted on the AXI bus
-- Reset data mux select between skid buffer and BRAM
-- Ensure read data mux is set for BRAM data
rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM;
-- Assert RVALID on AXI when 1st data beat available
-- from BRAM
axi_rvalid_set_cmb <= '1';
-- Reach this state when BRAM address counter is loaded
-- Use axi_rd_burst and axi_rd_burst_two to indicate if
-- operation is a single data beat burst.
if (axi_rd_burst = '0') and (axi_rd_burst_two = '0') then
-- Proceed directly to get BRAM read data
rd_data_sm_ns <= LAST_ADDR;
-- End of active current read address
ar_active_clr <= '1';
-- Negate BRAM enable
bram_en_cmb <= '0';
-- Load read data skid buffer for BRAM capture
-- in next clock cycle
rd_skid_buf_ld_cmb <= '1';
-- Assert new flag to disable back-to-back bursts
-- due to throttling
disable_b2b_brst_cmb <= '1';
-- Set flag for pending operation if bram_addr_ld_en is asserted (BRAM
-- address is loaded) and we are waiting for the current read burst to complete.
if (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
end if;
-- Read burst
else
-- Increment BRAM address counter (2nd data beat)
bram_addr_inc <= '1';
-- Decrement BRAM burst counter (2nd data beat)
brst_cnt_dec <= '1';
-- Keep BRAM enable asserted
bram_en_cmb <= '1';
rd_data_sm_ns <= SEC_ADDR;
-- Load read data skid buffer for BRAM capture
-- in next clock cycle
rd_skid_buf_ld_cmb <= '1';
-- Start of new operation, update act_rd_burst and
-- act_rd_burst_two signals
act_rd_burst_set <= '1';
-- If new burst is 2 data beats
-- Then disable capability on back-to-back bursts
if (axi_rd_burst_two = '1') then
-- Assert new flag to disable back-to-back bursts
-- due to throttling
disable_b2b_brst_cmb <= '1';
else
-- Support back-to-back for all other burst lengths
disable_b2b_brst_cmb <= '0';
end if;
end if;
------------------------- SEC_ADDR State --------------------------
when SEC_ADDR =>
-- Reach this state when the 2nd incremented address of the burst
-- is presented to the BRAM.
-- Only reach this state when axi_rd_burst = '1',
-- an active read burst.
-- Note:
-- No ability to throttle yet as RVALID has not yet been
-- asserted on the AXI bus
-- Enable AXI read data register
axi_rdata_en <= '1';
-- Only in dual port mode can the address counter get loaded early
if C_SINGLE_PORT_BRAM = 0 then
-- If we see the next address get loaded into the BRAM counter
-- then set flag for pending operation
if (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
end if;
end if;
-- Check here for burst length of two data transfers
-- If so, then the SM will NOT hit the condition of a full
-- pipeline:
-- Operation A) 1st BRAM address data on AXI bus
-- Operation B) 2nd BRAm address data read from BRAM
-- Operation C) 3rd BRAM address presented to BRAM
--
-- Full pipeline condition is hit for any read burst
-- length greater than 2 data beats.
if (axi_rd_burst_two = '1') then
-- No increment of BRAM address
-- or decrement of burst counter
-- Burst counter should be = zero
rd_data_sm_ns <= LAST_ADDR;
-- End of active current read address
ar_active_clr <= '1';
-- Ensure read data mux is set for BRAM data
rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM;
-- Negate BRAM enable
bram_en_cmb <= '0';
-- Load read data skid buffer for BRAM capture
-- in next clock cycle.
-- This signal will negate in the next state
-- if the data is not accepted on the AXI bus.
-- So that no new data from BRAM is registered into the
-- read channel controller.
rd_skid_buf_ld_cmb <= '1';
else
-- Burst length will hit full pipeline condition
-- Increment BRAM address counter (3rd data beat)
bram_addr_inc <= '1';
-- Decrement BRAM burst counter (3rd data beat)
brst_cnt_dec <= '1';
-- Keep BRAM enable asserted
bram_en_cmb <= '1';
rd_data_sm_ns <= FULL_PIPE;
-- Assert almost last BRAM address flag
-- so that ARVALID logic output can remain registered
--
-- Replace usage of brst_cnt with signal, brst_one.
if (brst_one = '1') then
alast_bram_addr <= '1';
end if;
-- Load read data skid buffer for BRAM capture
-- in next clock cycle
rd_skid_buf_ld_cmb <= '1';
end if; -- ARLEN = "0000 0001"
------------------------- FULL_PIPE State -------------------------
when FULL_PIPE =>
-- Reach this state when all three data beats in the burst
-- are active
--
-- Operation A) 1st BRAM address data on AXI bus
-- Operation B) 2nd BRAM address data read from BRAM
-- Operation C) 3rd BRAM address presented to BRAM
-- Ensure read data mux is set for BRAM data
rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM;
-- With new pipelining capability BRAM address counter may be
-- loaded in this state. This only occurs on back-to-back
-- bursts (when enabled).
-- No flag set for pending operation.
-- Modify the if clause here to check for back-to-back burst operations
-- If we load the BRAM address in this state for a subsequent burst, then
-- this condition indicates a back-to-back burst and no need to assert
-- the pending read operation flag.
-- Seeing corner case when pend_rd_op needs to be asserted and cleared
-- in this state. If the BRAM address counter is loaded early, but
-- axi_rlast_set is delayed in getting asserted (all while in this state).
-- The signal, curr_narrow_burst can not get cleared.
-- Only in dual port mode can the address counter get loaded early
if C_SINGLE_PORT_BRAM = 0 then
-- Set flag for pending operation if bram_addr_ld_en is asserted (BRAM
-- address is loaded) and we are waiting for the current read burst to complete.
if (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
-- Clear flag once pending read is recognized and
-- earlier read data phase is complete.
elsif (pend_rd_op = '1') and (axi_rlast_int = '1') then
pend_rd_op_cmb <= '0';
end if;
end if;
-- Check AXI throttling condition
-- If AXI bus advances and accepts read data, SM can
-- proceed with next data beat of burst.
-- If not, then go to FULL_THROTTLE state to wait for
-- AXI_RREADY = '1'.
if (rd_adv_buf = '1') then
-- Assert AXI read data enable for BRAM capture
axi_rdata_en <= '1';
-- Load read data skid buffer for BRAM capture in next clock cycle
rd_skid_buf_ld_cmb <= '1';
-- Assert almost last BRAM address flag
-- so that ARVALID logic output can remain registered
--
-- Replace usage of brst_cnt with signal, brst_one.
if (brst_one = '1') then
alast_bram_addr <= '1';
end if;
-- Check burst counter for max
-- If max burst count is reached, no new addresses
-- presented to BRAM, advance to last capture data states.
--
-- For timing, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (brst_zero = '1') or (end_brst_rd = '1' and axi_b2b_brst = '0') then
-- Check for elgible pending read operation to support back-to-back performance.
-- If so, load BRAM address counter.
--
-- Replace rd_b2b_elgible signal check to remove path from
-- arlen_pipe through rd_b2b_elgible
-- (with data throttle check)
if (rd_b2b_elgible_no_thr_check = '1') then
rd_data_sm_ns <= FULL_PIPE;
-- Set flag to indicate back-to-back read burst
-- RVALID will not clear in this case and remain asserted
axi_b2b_brst_cmb <= '1';
-- Set flag to update active read burst or
-- read burst of two flag
act_rd_burst_set <= '1';
-- Otherwise, complete current transaction
else
-- No increment of BRAM address
-- or decrement of burst counter
-- Burst counter should be = zero
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
rd_data_sm_ns <= LAST_ADDR;
-- Negate BRAM enable
bram_en_cmb <= '0';
-- End of active current read address
ar_active_clr <= '1';
end if;
else
-- Remain in this state until burst count reaches zero
-- Increment BRAM address counter (Nth data beat)
bram_addr_inc <= '1';
-- Decrement BRAM burst counter (Nth data beat)
brst_cnt_dec <= '1';
-- Keep BRAM enable asserted
bram_en_cmb <= '1';
-- Skid buffer load will remain asserted
-- AXI read data register is asserted
end if;
else
-- Throttling condition detected
rd_data_sm_ns <= FULL_THROTTLE;
-- Ensure that AXI read data output register is disabled
-- due to throttle condition.
axi_rdata_en <= '0';
-- Skid buffer gets loaded from BRAM read data in next clock
-- cycle ONLY.
-- Only on transition to THROTTLE state does skid buffer get loaded.
-- Negate load of read data skid buffer for BRAM capture
-- in next clock cycle due to detection of Throttle condition
rd_skid_buf_ld_cmb <= '0';
-- BRAM address is NOT getting incremented
-- (same for burst counter)
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
-- If transitioning to throttle state
-- Then next register enable assertion of the AXI read data
-- output register needs to come from the skid buffer
-- Set read data mux select here for SKID_BUFFER data
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
-- Detect if at end of burst read as we transition to FULL_THROTTLE
-- If so, negate the BRAM enable even if prior to throttle condition
-- on AXI bus. Read skid buffer will hold last beat of data in burst.
--
-- For timing purposes, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (brst_zero = '1') or (end_brst_rd = '1') then
-- No back to back "non bubble" support when AXI master
-- is throttling on current burst.
-- Seperate signal throttle_last_data will be asserted outside SM.
-- End of burst read, negate BRAM enable
bram_en_cmb <= '0';
-- Assert new flag to disable back-to-back bursts
-- due to throttling
disable_b2b_brst_cmb <= '1';
-- Disable B2B capability if throttling detected when
-- burst count is equal to one.
--
-- For timing purposes, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_one, indicating the
-- brst_cnt to be one when decrement.
elsif (brst_one = '1') then
-- Assert new flag to disable back-to-back bursts
-- due to throttling
disable_b2b_brst_cmb <= '1';
-- Throttle, but not end of burst
else
bram_en_cmb <= '1';
end if;
end if; -- rd_adv_buf (RREADY throttle)
------------------------- FULL_THROTTLE State ---------------------
when FULL_THROTTLE =>
-- Reach this state when the AXI bus throttles on the AXI data
-- beat read from BRAM (when the read pipeline is fully active)
-- Flag disable_b2b_brst_cmb should be asserted as we transition
-- to this state. Flag is asserted near the end of a read burst
-- to prevent the back-to-back performance pipelining in the BRAM
-- address counter.
-- Detect if at end of burst read
-- If so, negate the BRAM enable even if prior to throttle condition
-- on AXI bus. Read skid buffer will hold last beat of data in burst.
--
-- For timing, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (brst_zero = '1') or (end_brst_rd = '1') then
bram_en_cmb <= '0';
end if;
-- Set new flag for pending operation if bram_addr_ld_en is asserted (BRAM
-- address is loaded) and we are waiting for the current read burst to complete.
if (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
-- Clear flag once pending read is recognized and
-- earlier read data phase is complete.
elsif (pend_rd_op = '1') and (axi_rlast_int = '1') then
pend_rd_op_cmb <= '0';
end if;
-- Wait for RREADY to be asserted w/ RVALID on AXI bus
if (rd_adv_buf = '1') then
-- Ensure read data mux is set for skid buffer data
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
-- Ensure that AXI read data output register is enabled
axi_rdata_en <= '1';
-- Must reload skid buffer here from BRAM data
-- so if needed can be presented to AXI bus on the following clock cycle
rd_skid_buf_ld_imm <= '1';
-- When detecting end of throttle condition
-- Check first if burst count is complete
-- Check burst counter for max
-- If max burst count is reached, no new addresses
-- presented to BRAM, advance to last capture data states.
--
-- For timing, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (brst_zero = '1') or (end_brst_rd = '1') then
-- No back-to-back performance when AXI master throttles
-- If we reach the end of the burst, proceed to LAST_ADDR state.
-- No increment of BRAM address
-- or decrement of burst counter
-- Burst counter should be = zero
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
rd_data_sm_ns <= LAST_ADDR;
-- Negate BRAM enable
bram_en_cmb <= '0';
-- End of active current read address
ar_active_clr <= '1';
-- Not end of current burst w/ throttle condition
else
-- Go back to FULL_PIPE
rd_data_sm_ns <= FULL_PIPE;
-- Assert almost last BRAM address flag
-- so that ARVALID logic output can remain registered
--
-- For timing purposes, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_one, indicating the
-- brst_cnt to be one when decrement.
if (brst_one = '1') then
alast_bram_addr <= '1';
end if;
-- Increment BRAM address counter (Nth data beat)
bram_addr_inc <= '1';
-- Decrement BRAM burst counter (Nth data beat)
brst_cnt_dec <= '1';
-- Keep BRAM enable asserted
bram_en_cmb <= '1';
end if; -- Burst Max
else
-- Stay in this state
-- Ensure that AXI read data output register is disabled
-- due to throttle condition.
axi_rdata_en <= '0';
-- Ensure that skid buffer is not getting loaded with
-- current read data from BRAM
rd_skid_buf_ld_cmb <= '0';
-- BRAM address is NOT getting incremented
-- (same for burst counter)
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
end if; -- rd_adv_buf (RREADY throttle)
------------------------- LAST_ADDR State -------------------------
when LAST_ADDR =>
-- Reach this state in the clock cycle following the last address
-- presented to the BRAM. Capture the last BRAM data beat in the
-- next clock cycle.
--
-- Data is presented to AXI bus (if no throttling detected) and
-- loaded into the skid buffer.
-- If we reach this state after back to back burst transfers
-- then clear the flag to ensure that RVALID will clear when RLAST
-- is recognized
if (axi_b2b_brst = '1') then
axi_b2b_brst_cmb <= '0';
end if;
-- Clear flag that indicates end of read burst
-- Once we reach this state, we have recognized the burst complete.
--
-- It is getting asserted too early
-- and recognition of the end of the burst is missed when throttling
-- on the last two data beats in the read.
end_brst_rd_clr_cmb <= '1';
-- Set new flag for pending operation if ar_active is asserted (BRAM
-- address has already been loaded) and we are waiting for the current
-- read burst to complete. If those two conditions apply, set this flag.
-- For dual port, support checking for early writes into BRAM address counter
if (C_SINGLE_PORT_BRAM = 0) and ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then
-- Support back-to-backs for single AND dual port modes.
-- if ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then
-- if (ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
end if;
-- Load read data skid buffer for BRAM is asserted on transition
-- into this state. Only gets negated if done with operation
-- as detected in below if clause.
-- Check flag for no subsequent operations
-- Clear that now, with current operation completing
if (no_ar_ack = '1') then
no_ar_ack_cmb <= '0';
end if;
-- Check for single AXI read operations
-- If so, wait for RREADY to be asserted
-- Check for burst and bursts of two as seperate signals.
if (act_rd_burst = '0') and (act_rd_burst_two = '0') then
-- Create rvalid_set to only be asserted for a single clock
-- cycle.
-- Will get set as transitioning to LAST_ADDR on single read operations
-- Only assert RVALID here on single operations
-- Enable AXI read data register
axi_rdata_en <= '1';
-- Data will not yet be acknowledged on AXI
-- in this state.
-- Go to wait for last data beat
rd_data_sm_ns <= LAST_DATA;
-- Set read data mux select for SKID BUF
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
else
-- Only check throttling on AXI during read data burst operations
-- Check AXI throttling condition
-- If AXI bus advances and accepts read data, SM can
-- proceed with next data beat.
-- If not, then go to LAST_THROTTLE state to wait for
-- AXI_RREADY = '1'.
if (rd_adv_buf = '1') then
-- Assert AXI read data enable for BRAM capture
-- in next clock cycle
-- Enable AXI read data register
axi_rdata_en <= '1';
-- Ensure read data mux is set for BRAM data
rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM;
-- Burst counter already at zero. Reached this state due to NO
-- pending ARADDR in the read address pipeline. However, check
-- here for any new read addresses.
-- New ARADDR detected and loaded into BRAM address counter
-- Add check here for previously loaded BRAM address
-- ar_active will be asserted (and qualify that with the
-- condition that the read burst is complete, for narrow reads).
if (bram_addr_ld_en = '1') then
-- Initiate BRAM read transfer
bram_en_cmb <= '1';
-- Instead of transitioning to SNG_ADDR
-- go to wait for last data beat.
rd_data_sm_ns <= LAST_DATA_AR_PEND;
else
-- No pending read address to initiate next read burst
-- Go to capture last data beat from BRAM and present on AXI bus.
rd_data_sm_ns <= LAST_DATA;
end if; -- bram_addr_ld_en (New read burst)
else
-- Throttling condition detected
rd_data_sm_ns <= LAST_THROTTLE;
-- Ensure that AXI read data output register is disabled
-- due to throttle condition.
axi_rdata_en <= '0';
-- Skid buffer gets loaded from BRAM read data in next clock
-- cycle ONLY.
-- Only on transition to THROTTLE state does skid buffer get loaded.
-- Set read data mux select for SKID BUF
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
end if; -- rd_adv_buf (RREADY throttle)
end if; -- AXI read burst
------------------------- LAST_THROTTLE State ---------------------
when LAST_THROTTLE =>
-- Reach this state when the AXI bus throttles on the last data
-- beat read from BRAM
-- Data to be sourced from read skid buffer
-- Add check in LAST_THROTTLE as well as LAST_ADDR
-- as we may miss the setting of this flag for a subsequent operation.
-- For dual port, support checking for early writes into BRAM address counter
if (C_SINGLE_PORT_BRAM = 0) and ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then
-- Support back-to-back for single AND dual port modes.
-- if ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then
pend_rd_op_cmb <= '1';
end if;
-- Wait for RREADY to be asserted w/ RVALID on AXI bus
if (rd_adv_buf = '1') then
-- Assert AXI read data enable for BRAM capture
axi_rdata_en <= '1';
-- Set read data mux select for SKID BUF
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
-- No pending read address to initiate next read burst
-- Go to capture last data beat from BRAM and present on AXI bus.
rd_data_sm_ns <= LAST_DATA;
-- Load read data skid buffer for BRAM capture in next clock cycle
-- of last data read
-- Read Skid buffer already loaded with last data beat from BRAM
-- Does not need to be asserted again in this state
else
-- Stay in this state
-- Ensure that AXI read data output register is disabled
axi_rdata_en <= '0';
-- Ensure that skid buffer is not getting loaded with
-- current read data from BRAM
rd_skid_buf_ld_cmb <= '0';
-- BRAM address is NOT getting incremented
-- (same for burst counter)
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
-- Keep RVALID asserted on AXI
-- No need to assert RVALID again
end if; -- rd_adv_buf (RREADY throttle)
------------------------- LAST_DATA State -------------------------
when LAST_DATA =>
-- Reach this state when last BRAM data beat is
-- presented on AXI bus.
-- For a read burst, RLAST is not asserted until SM reaches
-- this state.
-- Ok to accept new operation if throttling detected
-- during current operation (and flag was previously set
-- to disable the back-to-back performance).
disable_b2b_brst_cmb <= '0';
-- Stay in this state until RREADY is asserted on AXI bus
-- Indicated by assertion of rd_adv_buf
if (rd_adv_buf = '1') then
-- Last data beat acknowledged on AXI bus
-- Check for new read burst or proceed back to IDLE
-- New ARADDR detected and loaded into BRAM address counter
-- Note: this condition may occur when C_SINGLE_PORT_BRAM = 0 or 1
if (bram_addr_ld_en = '1') or (pend_rd_op = '1') then
-- Clear flag once pending read is recognized
if (pend_rd_op = '1') then
pend_rd_op_cmb <= '0';
end if;
-- Initiate BRAM read transfer
bram_en_cmb <= '1';
-- Only count addresses & burst length for read
-- burst operations
-- Go to SNG_ADDR state
rd_data_sm_ns <= SNG_ADDR;
-- If current operation was a burst, clear the active
-- burst flag
if (act_rd_burst = '1') or (act_rd_burst_two = '1') then
act_rd_burst_clr <= '1';
end if;
-- If we are loading the BRAM, then we have to view the curr_arlen
-- signal to determine if the next operation is a single transfer.
-- Or if the BRAM address counter is already loaded (and we reach
-- this if clause due to pend_rd_op then the axi_* signals will indicate
-- if the next operation is a burst or not.
-- If the operation is a single transaction, then set the last_bram_addr
-- signal when we reach SNG_ADDR.
if (bram_addr_ld_en = '1') then
if (curr_arlen = AXI_ARLEN_ONE) then
-- Set flag for last_bram_addr on transition
-- to SNG_ADDR on single operations.
set_last_bram_addr <= '1';
end if;
elsif (pend_rd_op = '1') then
if (axi_rd_burst = '0' and axi_rd_burst_two = '0') then
set_last_bram_addr <= '1';
end if;
end if;
else
-- No pending read address to initiate next read burst.
-- Go to IDLE
rd_data_sm_ns <= IDLE;
-- If current operation was a burst, clear the active
-- burst flag
if (act_rd_burst = '1') or (act_rd_burst_two = '1') then
act_rd_burst_clr <= '1';
end if;
end if;
else
-- Throttling condition detected
-- Ensure that AXI read data output register is disabled
-- due to throttle condition.
axi_rdata_en <= '0';
-- If new ARADDR detected and loaded into BRAM address counter
if (bram_addr_ld_en = '1') then
-- Initiate BRAM read transfer
bram_en_cmb <= '1';
-- Only count addresses & burst length for read
-- burst operations
-- Instead of transitioning to SNG_ADDR
-- to wait for last data beat.
rd_data_sm_ns <= LAST_DATA_AR_PEND;
-- For singles, block any subsequent loads into BRAM address
-- counter from AR SM
no_ar_ack_cmb <= '1';
end if;
end if; -- rd_adv_buf (RREADY throttle)
------------------------ LAST_DATA_AR_PEND --------------------
when LAST_DATA_AR_PEND =>
-- Ok to accept new operation if throttling detected
-- during current operation (and flag was previously set
-- to disable the back-to-back performance).
disable_b2b_brst_cmb <= '0';
-- Reach this state when new BRAM address is loaded into
-- BRAM address counter
-- But waiting for last RREADY/RVALID/RLAST to be asserted
-- Once this occurs, continue with pending AR operation
if (rd_adv_buf = '1') then
-- Go to SNG_ADDR state
rd_data_sm_ns <= SNG_ADDR;
-- If current operation was a burst, clear the active
-- burst flag
if (act_rd_burst = '1') or (act_rd_burst_two = '1') then
act_rd_burst_clr <= '1';
end if;
-- In this state, the BRAM address counter is already loaded,
-- the axi_rd_burst and axi_rd_burst_two signals will indicate
-- if the next operation is a burst or not.
-- If the operation is a single transaction, then set the last_bram_addr
-- signal when we reach SNG_ADDR.
if (axi_rd_burst = '0' and axi_rd_burst_two = '0') then
set_last_bram_addr <= '1';
end if;
-- Code coverage tests are reporting that reaching this state
-- always when axi_rd_burst = '0' and axi_rd_burst_two = '0',
-- so no bursting operations.
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
rd_data_sm_ns <= IDLE;
--coverage on
end case;
end process RD_DATA_SM_CMB_PROCESS;
---------------------------------------------------------------------------
RD_DATA_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
rd_data_sm_cs <= IDLE;
bram_en_int <= '0';
rd_skid_buf_ld_reg <= '0';
rddata_mux_sel <= C_RDDATA_MUX_BRAM;
axi_rvalid_set <= '0';
end_brst_rd_clr <= '0';
no_ar_ack <= '0';
pend_rd_op <= '0';
axi_b2b_brst <= '0';
disable_b2b_brst <= '0';
else
rd_data_sm_cs <= rd_data_sm_ns;
bram_en_int <= bram_en_cmb;
rd_skid_buf_ld_reg <= rd_skid_buf_ld_cmb;
rddata_mux_sel <= rddata_mux_sel_cmb;
axi_rvalid_set <= axi_rvalid_set_cmb;
end_brst_rd_clr <= end_brst_rd_clr_cmb;
no_ar_ack <= no_ar_ack_cmb;
pend_rd_op <= pend_rd_op_cmb;
axi_b2b_brst <= axi_b2b_brst_cmb;
disable_b2b_brst <= disable_b2b_brst_cmb;
end if;
end if;
end process RD_DATA_SM_REG_PROCESS;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Create seperate registered process for last_bram_addr signal.
-- Only asserted for a single clock cycle
-- Gets set when the burst counter is loaded with 0's (for a single data beat operation)
-- (indicated by set_last_bram_addr from DATA SM)
-- or when the burst counter is decrement and the current value = 1
REG_LAST_BRAM_ADDR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
last_bram_addr <= '0';
-- The signal, set_last_bram_addr, is asserted when the DATA SM transitions to SNG_ADDR
-- on a single data beat burst. Can not use condition of loading burst counter
-- with the value of 0's (as the burst counter may be loaded during prior single operation
-- when waiting on last throttle/data beat, ie. rd_adv_buf not yet asserted).
elsif (set_last_bram_addr = '1') or
-- On burst operations at the last BRAM address presented to BRAM
(brst_cnt_dec = '1' and brst_cnt = C_BRST_CNT_ONE) then
last_bram_addr <= '1';
else
last_bram_addr <= '0';
end if;
end if;
end process REG_LAST_BRAM_ADDR;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- *** AXI Read Data Channel Interface ***
--
---------------------------------------------------------------------------
rd_skid_buf_ld <= rd_skid_buf_ld_reg or rd_skid_buf_ld_imm;
---------------------------------------------------------------------------
-- Generate: GEN_RDATA_NO_ECC
-- Purpose: Generation of AXI_RDATA output register without ECC
-- logic (C_ECC = 0 parameterization in design)
---------------------------------------------------------------------------
GEN_RDATA_NO_ECC: if C_ECC = 0 generate
signal axi_rdata_int : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
begin
---------------------------------------------------------------------------
-- AXI RdData Skid Buffer/Register
-- Sized according to size of AXI/BRAM data width
---------------------------------------------------------------------------
REG_RD_BUF: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
rd_skid_buf <= (others => '0');
-- Add immediate load of read skid buffer
-- Occurs in the case when at full throttle and RREADY/RVALID are asserted
elsif (rd_skid_buf_ld = '1') then
rd_skid_buf <= BRAM_RdData (C_AXI_DATA_WIDTH-1 downto 0);
else
rd_skid_buf <= rd_skid_buf;
end if;
end if;
end process REG_RD_BUF;
-- Rd Data Mux (selects between skid buffer and BRAM read data)
-- Select control signal from SM determines register load value
axi_rdata_mux <= BRAM_RdData (C_AXI_DATA_WIDTH-1 downto 0) when (rddata_mux_sel = C_RDDATA_MUX_BRAM) else
rd_skid_buf;
---------------------------------------------------------------------------
-- Generate: GEN_RDATA
-- Purpose: Generate each bit of AXI_RDATA.
---------------------------------------------------------------------------
GEN_RDATA: for i in C_AXI_DATA_WIDTH-1 downto 0 generate
begin
REG_RDATA: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- Clear output after last data beat accepted by requesting AXI master
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- Don't clear RDDATA when a back to back burst is occuring on RLAST & RVALID assertion
-- For improved code coverage, can remove the signal, axi_rvalid_int from this if clause.
-- It will always be asserted in this case.
(axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then
axi_rdata_int (i) <= '0';
elsif (axi_rdata_en = '1') then
axi_rdata_int (i) <= axi_rdata_mux (i);
else
axi_rdata_int (i) <= axi_rdata_int (i);
end if;
end if;
end process REG_RDATA;
end generate GEN_RDATA;
-- If C_ECC = 0, direct output assignment to AXI_RDATA
AXI_RDATA <= axi_rdata_int;
end generate GEN_RDATA_NO_ECC;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_RDATA_ECC
-- Purpose: Generation of AXI_RDATA output register when ECC
-- logic is enabled (C_ECC = 1 parameterization in design)
---------------------------------------------------------------------------
GEN_RDATA_ECC: if C_ECC = 1 generate
subtype syndrome_bits is std_logic_vector(0 to C_INT_ECC_WIDTH-1);
-- 0:6 for 32-bit ECC
-- 0:7 for 64-bit ECC
type correct_data_table_type is array (natural range 0 to C_AXI_DATA_WIDTH-1) of syndrome_bits;
signal rd_skid_buf_i : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi_rdata_int : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi_rdata_int_corr : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
begin
-- Remove GEN_RD_BUF that was doing bit reversal.
-- Replace with direct register assignments. Sized according to AXI data width.
REG_RD_BUF: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
rd_skid_buf_i <= (others => '0');
-- Add immediate load of read skid buffer
-- Occurs in the case when at full throttle and RREADY/RVALID are asserted
elsif (rd_skid_buf_ld = '1') then
rd_skid_buf_i (C_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1);
else
rd_skid_buf_i <= rd_skid_buf_i;
end if;
end if;
end process REG_RD_BUF;
-- Rd Data Mux (selects between skid buffer and BRAM read data)
-- Select control signal from SM determines register load value
-- axi_rdata_mux holds data + ECC bits.
-- Previous mux on input to checkbit_handler logic.
-- Removed now (mux inserted after checkbit_handler logic before register stage)
--
-- axi_rdata_mux <= BRAM_RdData (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) when (rddata_mux_sel = C_RDDATA_MUX_BRAM) else
-- rd_skid_buf_i;
-- Remove GEN_RDATA that was doing bit reversal.
REG_RDATA: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then
axi_rdata_int <= (others => '0');
elsif (axi_rdata_en = '1') then
-- Track uncorrected data vector with AXI RDATA output pipeline
-- Mimic mux logic here (from previous post checkbit XOR logic register)
if (rddata_mux_sel = C_RDDATA_MUX_BRAM) then
axi_rdata_int (C_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1);
else
axi_rdata_int <= rd_skid_buf_i;
end if;
else
axi_rdata_int <= axi_rdata_int;
end if;
end if;
end process REG_RDATA;
-- When C_ECC = 1, correct any single bit errors on output read data.
-- Post register stage to improve timing on ECC logic data path.
-- Use registers in AXI Interconnect IP core.
-- Perform bit swapping on output of correct_one_bit
-- module (axi_rdata_int_corr signal).
-- AXI_RDATA (i) <= axi_rdata_int (i) when (Enable_ECC = '0')
-- else axi_rdata_int_corr (C_AXI_DATA_WIDTH-1-i);
-- Found in HW debug
-- axi_rdata_int is reversed to be returned on AXI bus.
-- AXI_RDATA (i) <= axi_rdata_int (C_AXI_DATA_WIDTH-1-i) when (Enable_ECC = '0')
-- else axi_rdata_int_corr (C_AXI_DATA_WIDTH-1-i);
-- Remove bit reversal on AXI_RDATA output.
AXI_RDATA <= axi_rdata_int when (Enable_ECC = '0' or Sl_UE_i = '1') else axi_rdata_int_corr;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HAMMING_ECC_CORR
--
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
-- Generate statements to correct BRAM read data
-- dependent on ECC type.
------------------------------------------------------------------------
GEN_HAMMING_ECC_CORR: if C_ECC_TYPE = 0 generate
begin
------------------------------------------------------------------------
-- Generate: CHK_ECC_32
-- Purpose: Check ECC data unique for 32-bit BRAM.
------------------------------------------------------------------------
CHK_ECC_32: if C_AXI_DATA_WIDTH = 32 generate
constant correct_data_table_32 : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
signal syndrome_4_reg : std_logic_vector (0 to 1) := (others => '0'); -- Only used in 32-bit ECC
signal syndrome_6_reg : std_logic_vector (0 to 5) := (others => '0'); -- Specific for 32-bit ECC
begin
---------------------------------------------------------------------------
-- Register ECC syndrome value to correct any single bit errors
-- post-register on AXI read data.
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
syndrome_reg <= (others => '0');
syndrome_4_reg <= (others => '0');
syndrome_6_reg <= (others => '0');
-- Align register stage of syndrome with AXI read data pipeline
elsif (axi_rdata_en = '1') then
syndrome_reg <= Syndrome;
syndrome_4_reg <= Syndrome_4;
syndrome_6_reg <= Syndrome_6;
else
syndrome_reg <= syndrome_reg;
syndrome_4_reg <= syndrome_4_reg;
syndrome_6_reg <= syndrome_6_reg;
end if;
end if;
end process REG_SYNDROME;
---------------------------------------------------------------------------
-- Do last XOR on specific syndrome bits after pipeline stage before
-- correct_one_bit module.
syndrome_reg_i (0 to 3) <= syndrome_reg (0 to 3);
PARITY_CHK4: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2)
port map (
InA => syndrome_4_reg (0 to 1), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (4) ); -- [out std_logic]
syndrome_reg_i (5) <= syndrome_reg (5);
PARITY_CHK6: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_6_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (6) ); -- [out std_logic]
---------------------------------------------------------------------------
-- Generate: GEN_CORR_32
-- Purpose: Generate corrected read data based on syndrome value.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
GEN_CORR_32: for i in 0 to C_AXI_DATA_WIDTH-1 generate
begin
-----------------------------------------------------------------------
-- Instance: CORR_ONE_BIT_32
-- Description: Correct output read data based on syndrome vector.
-- A single error can be corrected by decoding the
-- syndrome value.
-- Input signal is declared (N:0).
-- Output signal is (N:0).
-- In order to reuse correct_one_bit module,
-- the single data bit correction is done LSB to MSB
-- in generate statement loop.
-----------------------------------------------------------------------
CORR_ONE_BIT_32: entity work.correct_one_bit
generic map (
C_USE_LUT6 => C_USE_LUT6,
Correct_Value => correct_data_table_32 (i))
port map (
DIn => axi_rdata_int (31-i), -- This is to match with LMB Controller Hamming Encoder logic (Bit Reversal)
Syndrome => syndrome_reg_i,
DCorr => axi_rdata_int_corr (31-i)); -- This is to match with LMB Controller Hamming Encoder logic (Bit Reversal)
end generate GEN_CORR_32;
end generate CHK_ECC_32;
------------------------------------------------------------------------
-- Generate: CHK_ECC_64
-- Purpose: Check ECC data unique for 64-bit BRAM.
------------------------------------------------------------------------
CHK_ECC_64: if C_AXI_DATA_WIDTH = 64 generate
constant correct_data_table_64 : correct_data_table_type := (
0 => "11000001", 1 => "10100001", 2 => "01100001", 3 => "11100001",
4 => "10010001", 5 => "01010001", 6 => "11010001", 7 => "00110001",
8 => "10110001", 9 => "01110001", 10 => "11110001", 11 => "10001001",
12 => "01001001", 13 => "11001001", 14 => "00101001", 15 => "10101001",
16 => "01101001", 17 => "11101001", 18 => "00011001", 19 => "10011001",
20 => "01011001", 21 => "11011001", 22 => "00111001", 23 => "10111001",
24 => "01111001", 25 => "11111001", 26 => "10000101", 27 => "01000101",
28 => "11000101", 29 => "00100101", 30 => "10100101", 31 => "01100101",
32 => "11100101", 33 => "00010101", 34 => "10010101", 35 => "01010101",
36 => "11010101", 37 => "00110101", 38 => "10110101", 39 => "01110101",
40 => "11110101", 41 => "00001101", 42 => "10001101", 43 => "01001101",
44 => "11001101", 45 => "00101101", 46 => "10101101", 47 => "01101101",
48 => "11101101", 49 => "00011101", 50 => "10011101", 51 => "01011101",
52 => "11011101", 53 => "00111101", 54 => "10111101", 55 => "01111101",
56 => "11111101", 57 => "10000011", 58 => "01000011", 59 => "11000011",
60 => "00100011", 61 => "10100011", 62 => "01100011", 63 => "11100011"
);
signal syndrome_7_reg : std_logic_vector (0 to 11) := (others => '0'); -- Specific for 64-bit ECC
signal syndrome_7_a : std_logic;
signal syndrome_7_b : std_logic;
begin
---------------------------------------------------------------------------
-- Register ECC syndrome value to correct any single bit errors
-- post-register on AXI read data.
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- Align register stage of syndrome with AXI read data pipeline
if (axi_rdata_en = '1') then
syndrome_reg <= Syndrome;
syndrome_7_reg <= Syndrome_7;
else
syndrome_reg <= syndrome_reg;
syndrome_7_reg <= syndrome_7_reg;
end if;
end if;
end process REG_SYNDROME;
---------------------------------------------------------------------------
-- Do last XOR on select syndrome bits after pipeline stage
-- before correct_one_bit_64 module.
PARITY_CHK7_A: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_7_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_7_a ); -- [out std_logic]
PARITY_CHK7_B: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_7_reg (6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_7_b ); -- [out std_logic]
-- Do last XOR on Syndrome MSB after pipeline stage before correct_one_bit module
-- PASSES: syndrome_reg_i (7) <= syndrome_reg (7) xor syndrome_7_b_reg;
syndrome_reg_i (7) <= syndrome_7_a xor syndrome_7_b;
syndrome_reg_i (0 to 6) <= syndrome_reg (0 to 6);
---------------------------------------------------------------------------
-- Generate: GEN_CORR_64
-- Purpose: Generate corrected read data based on syndrome value.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
GEN_CORR_64: for i in 0 to C_AXI_DATA_WIDTH-1 generate
begin
-----------------------------------------------------------------------
-- Instance: CORR_ONE_BIT_64
-- Description: Correct output read data based on syndrome vector.
-- A single error can be corrected by decoding the
-- syndrome value.
-----------------------------------------------------------------------
CORR_ONE_BIT_64: entity work.correct_one_bit_64
generic map (
C_USE_LUT6 => C_USE_LUT6,
Correct_Value => correct_data_table_64 (i))
port map (
DIn => axi_rdata_int (i),
Syndrome => syndrome_reg_i,
DCorr => axi_rdata_int_corr (i));
end generate GEN_CORR_64;
end generate CHK_ECC_64;
end generate GEN_HAMMING_ECC_CORR;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HSIAO_ECC_CORR
--
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
-- Derived from MIG v3.7 Hsiao HDL.
-- Generate statements to correct BRAM read data
-- dependent on ECC type.
------------------------------------------------------------------------
GEN_HSIAO_ECC_CORR: if C_ECC_TYPE = 1 generate
type type_int0 is array (C_AXI_DATA_WIDTH - 1 downto 0) of std_logic_vector (ECC_WIDTH - 1 downto 0);
signal h_matrix : type_int0;
signal flip_bits : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0);
signal ecc_rddata_r : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0);
begin
-- Reconstruct H-matrix
H_COL: for n in 0 to C_AXI_DATA_WIDTH - 1 generate
begin
H_BIT: for p in 0 to ECC_WIDTH - 1 generate
begin
h_matrix (n)(p) <= h_rows (p * CODE_WIDTH + n);
end generate H_BIT;
end generate H_COL;
-- Based on syndrome value, determine bits to flip in BRAM read data.
GEN_FLIP_BIT: for r in 0 to C_AXI_DATA_WIDTH - 1 generate
begin
flip_bits (r) <= BOOLEAN_TO_STD_LOGIC (h_matrix (r) = syndrome_r);
end generate GEN_FLIP_BIT;
ecc_rddata_r <= axi_rdata_int;
axi_rdata_int_corr (C_AXI_DATA_WIDTH-1 downto 0) <= -- UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1) xor
ecc_rddata_r (C_AXI_DATA_WIDTH-1 downto 0) xor
flip_bits (C_AXI_DATA_WIDTH-1 downto 0);
end generate GEN_HSIAO_ECC_CORR;
end generate GEN_RDATA_ECC;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_RID_SNG
-- Purpose: Generate RID output pipeline when the core is configured
-- in a single port mode.
---------------------------------------------------------------------------
GEN_RID_SNG: if (C_SINGLE_PORT_BRAM = 1) generate
begin
REG_RID_TEMP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rid_temp <= (others => '0');
elsif (bram_addr_ld_en = '1') then
axi_rid_temp <= AXI_ARID;
else
axi_rid_temp <= axi_rid_temp;
end if;
end if;
end process REG_RID_TEMP;
REG_RID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
axi_rid_int <= (others => '0');
elsif (bram_addr_ld_en = '1') then
axi_rid_int <= AXI_ARID;
elsif (axi_rvalid_set = '1') or (axi_b2b_rid_adv = '1') then
axi_rid_int <= axi_rid_temp;
else
axi_rid_int <= axi_rid_int;
end if;
end if;
end process REG_RID;
-- Advance RID pipeline values
axi_b2b_rid_adv <= '1' when (axi_rlast_int = '1' and
AXI_RREADY = '1' and
axi_b2b_brst = '1')
else '0';
end generate GEN_RID_SNG;
---------------------------------------------------------------------------
-- Generate: GEN_RID
-- Purpose: Generate RID in dual port mode (with read address pipeline).
---------------------------------------------------------------------------
GEN_RID: if (C_SINGLE_PORT_BRAM = 0) generate
begin
---------------------------------------------------------------------------
-- RID Output Register
--
-- Output RID value either comes from pipelined value or directly wrapped
-- ARID value. Determined by address pipeline usage.
---------------------------------------------------------------------------
-- Create intermediate temporary RID output register
REG_RID_TEMP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rid_temp <= (others => '0');
-- When BRAM address counter gets loaded
-- Set output RID value based on address source
elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '0') then
-- If BRAM address counter gets loaded directly from
-- AXI bus, then save ARID value for wrapping to RID
if (araddr_pipe_sel = '0') then
axi_rid_temp <= AXI_ARID;
else
-- Use pipelined AWID value
axi_rid_temp <= axi_arid_pipe;
end if;
-- Add condition to check for temp utilized (temp_full now = '0'), but a
-- pending RID is stored in temp2. Must advance the pipeline.
elsif ((axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and (axi_rid_temp2_full = '1')) or
(axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then
axi_rid_temp <= axi_rid_temp2;
else
axi_rid_temp <= axi_rid_temp;
end if;
end if;
end process REG_RID_TEMP;
-- Create flag that indicates if axi_rid_temp is full
REG_RID_TEMP_FULL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rid_temp_full = '1' and
(axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and
axi_rid_temp2_full = '0') then
axi_rid_temp_full <= '0';
elsif (bram_addr_ld_en = '1') or
((axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and (axi_rid_temp2_full = '1')) or
(axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then
axi_rid_temp_full <= '1';
else
axi_rid_temp_full <= axi_rid_temp_full;
end if;
end if;
end process REG_RID_TEMP_FULL;
-- Create flag to detect falling edge of axi_rid_temp_full flag
REG_RID_TEMP_FULL_D1: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rid_temp_full_d1 <= '0';
else
axi_rid_temp_full_d1 <= axi_rid_temp_full;
end if;
end if;
end process REG_RID_TEMP_FULL_D1;
axi_rid_temp_full_fe <= '1' when (axi_rid_temp_full = '0' and
axi_rid_temp_full_d1 = '1') else '0';
---------------------------------------------------------------------------
-- Create intermediate temporary RID output register
REG_RID_TEMP2: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rid_temp2 <= (others => '0');
-- When BRAM address counter gets loaded
-- Set output RID value based on address source
elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '1') then
-- If BRAM address counter gets loaded directly from
-- AXI bus, then save ARID value for wrapping to RID
if (araddr_pipe_sel = '0') then
axi_rid_temp2 <= AXI_ARID;
else
-- Use pipelined AWID value
axi_rid_temp2 <= axi_arid_pipe;
end if;
else
axi_rid_temp2 <= axi_rid_temp2;
end if;
end if;
end process REG_RID_TEMP2;
-- Create flag that indicates if axi_rid_temp2 is full
REG_RID_TEMP2_FULL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rid_temp2_full = '1' and (axi_rvalid_set = '1' or axi_b2b_rid_adv = '1')) or
(axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then
axi_rid_temp2_full <= '0';
elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '1') then
axi_rid_temp2_full <= '1';
else
axi_rid_temp2_full <= axi_rid_temp2_full;
end if;
end if;
end process REG_RID_TEMP2_FULL;
---------------------------------------------------------------------------
-- Output RID register is enabeld when RVALID is asserted on the AXI bus
-- Clear RID when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
REG_RID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- For improved code coverage, can remove the signal, axi_rvalid_int from statement.
(axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then
axi_rid_int <= (others => '0');
-- Add back to back case to advance RID
elsif (axi_rvalid_set = '1') or (axi_b2b_rid_adv = '1') then
axi_rid_int <= axi_rid_temp;
else
axi_rid_int <= axi_rid_int;
end if;
end if;
end process REG_RID;
-- Advance RID pipeline values
axi_b2b_rid_adv <= '1' when (axi_rlast_int = '1' and
AXI_RREADY = '1' and
axi_b2b_brst = '1')
else '0';
end generate GEN_RID;
---------------------------------------------------------------------------
-- Generate: GEN_RRESP
-- Purpose: Create register output unique when ECC is disabled.
-- Only possible output value = OKAY response.
---------------------------------------------------------------------------
GEN_RRESP: if C_ECC = 0 generate
begin
-----------------------------------------------------------------------
-- AXI_RRESP Output Register
--
-- Set when RVALID is asserted on AXI bus.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking
-- sequence and recognized by AXI requesting master.
-----------------------------------------------------------------------
REG_RRESP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- For improved code coverage, remove signal, axi_rvalid_int, it will always be asserted.
(axi_rlast_int = '1' and AXI_RREADY = '1') then
axi_rresp_int <= (others => '0');
elsif (axi_rvalid_set = '1') then
-- AXI BRAM only supports OK response for normal operations
-- Exclusive operations not yet supported
axi_rresp_int <= RESP_OKAY;
else
axi_rresp_int <= axi_rresp_int;
end if;
end if;
end process REG_RRESP;
end generate GEN_RRESP;
---------------------------------------------------------------------------
-- Generate: GEN_RRESP_ECC
-- Purpose: Create register output unique when ECC is disabled.
-- Only possible output value = OKAY response.
---------------------------------------------------------------------------
GEN_RRESP_ECC: if C_ECC = 1 generate
begin
-----------------------------------------------------------------------
-- AXI_RRESP Output Register
--
-- Set when RVALID is asserted on AXI bus.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking
-- sequence and recognized by AXI requesting master.
-----------------------------------------------------------------------
REG_RRESP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- For improved code coverage, remove signal, axi_rvalid_int, it will always be asserted.
(axi_rlast_int = '1' and AXI_RREADY = '1') then
axi_rresp_int <= (others => '0');
elsif (axi_rvalid_set = '1') then
-- AXI BRAM only supports OK response for normal operations
-- Exclusive operations not yet supported
-- For ECC implementation
-- Check that an uncorrectable error has not occured.
-- If so, then respond with RESP_SLVERR on AXI.
-- Ok to use combinatorial signal here. The Sl_UE_i
-- flag is generated based on the registered syndrome value.
-- if (Sl_UE_i = '1') then
-- axi_rresp_int <= RESP_SLVERR;
-- else
axi_rresp_int <= RESP_OKAY;
-- end if;
else
axi_rresp_int <= axi_rresp_int;
end if;
end if;
end process REG_RRESP;
end generate GEN_RRESP_ECC;
---------------------------------------------------------------------------
-- AXI_RVALID Output Register
--
-- Set AXI_RVALID when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RVALID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- Clear AXI_RVALID at the end of tranfer when able to clear
-- (axi_rlast_int = '1' and axi_rvalid_int = '1' and AXI_RREADY = '1' and
-- For improved code coverage, remove signal axi_rvalid_int.
(axi_rlast_int = '1' and AXI_RREADY = '1' and
-- Added axi_rvalid_clr_ok to check if during a back-to-back burst
-- and the back-to-back is elgible for streaming performance
axi_rvalid_clr_ok = '1') then
axi_rvalid_int <= '0';
elsif (axi_rvalid_set = '1') then
axi_rvalid_int <= '1';
else
axi_rvalid_int <= axi_rvalid_int;
end if;
end if;
end process REG_RVALID;
-- Create flag that gets set when we load BRAM address early in a B2B scenario
-- This will prevent the RVALID from getting cleared at the end of the current burst
-- Otherwise, the RVALID gets cleared after RLAST/RREADY dual assertion
REG_RVALID_CLR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rvalid_clr_ok <= '0';
-- When the new address loaded into the BRAM counter is for a back-to-back operation
-- Do not clear the RVALID
elsif (rd_b2b_elgible = '1' and bram_addr_ld_en = '1') then
axi_rvalid_clr_ok <= '0';
-- Else when we start a new transaction (that is not back-to-back)
-- Then enable the RVALID to get cleared upon RLAST/RREADY
elsif (bram_addr_ld_en = '1') or
(axi_rvalid_clr_ok = '0' and
(disable_b2b_brst = '1' or disable_b2b_brst_cmb = '1') and
last_bram_addr = '1') or
-- Add check for current SM state
-- If LAST_ADDR state reached, no longer performing back-to-back
-- transfers and keeping data streaming on AXI bus.
(rd_data_sm_cs = LAST_ADDR) then
axi_rvalid_clr_ok <= '1';
else
axi_rvalid_clr_ok <= axi_rvalid_clr_ok;
end if;
end if;
end process REG_RVALID_CLR;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- AXI_RLAST Output Register
--
-- Set AXI_RLAST when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RLAST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- To improve code coverage, remove
-- use of axi_rvalid_int (it will always be asserted with RLAST).
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1' and axi_rlast_set = '0') then
axi_rlast_int <= '0';
elsif (axi_rlast_set = '1') then
axi_rlast_int <= '1';
else
axi_rlast_int <= axi_rlast_int;
end if;
end if;
end process REG_RLAST;
---------------------------------------------------------------------------
-- Generate complete flag
do_cmplt_burst_cmb <= '1' when (last_bram_addr = '1' and
axi_rd_burst = '1' and
axi_rd_burst_two = '0') else '0';
-- Register complete flags
REG_CMPLT_BURST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or (do_cmplt_burst_clr = '1') then
do_cmplt_burst <= '0';
elsif (do_cmplt_burst_cmb = '1') then
do_cmplt_burst <= '1';
else
do_cmplt_burst <= do_cmplt_burst;
end if;
end if;
end process REG_CMPLT_BURST;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- RLAST State Machine
--
-- Description: SM to generate axi_rlast_set signal.
-- Created based on IR # 555346 to track when RLAST needs
-- to be asserted for back to back transfers
-- Uses the indication when last BRAM address is presented
-- and then counts the handshaking cycles on the AXI bus
-- (RVALID and RREADY both asserted).
-- Uses rd_adv_buf to perform this operation.
--
-- Output: Name Type
-- axi_rlast_set Not Registered
-- do_cmplt_burst_clr Not Registered
--
--
-- RLAST_SM_CMB_PROCESS: Combinational process to determine next state.
-- RLAST_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
RLAST_SM_CMB_PROCESS: process (
do_cmplt_burst,
last_bram_addr,
rd_adv_buf,
act_rd_burst,
axi_rd_burst,
act_rd_burst_two,
axi_rd_burst_two,
axi_rlast_int,
rlast_sm_cs )
begin
-- assign default values for state machine outputs
rlast_sm_ns <= rlast_sm_cs;
axi_rlast_set <= '0';
do_cmplt_burst_clr <= '0';
case rlast_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- If last read address is presented to BRAM
if (last_bram_addr = '1') then
-- If the operation is a single read operation
if (axi_rd_burst = '0') and (axi_rd_burst_two = '0') then
-- Go to wait for last data beat
rlast_sm_ns <= W8_LAST_DATA;
-- Else the transaction is a burst
else
-- Throttle condition on 3rd to last data beat
if (rd_adv_buf = '0') then
-- If AXI read burst = 2 (only two data beats to capture)
if (axi_rd_burst_two = '1' or act_rd_burst_two = '1') then
rlast_sm_ns <= W8_THROTTLE_B2;
else
rlast_sm_ns <= W8_THROTTLE;
end if;
-- No throttle on 3rd to last data beat
else
-- Only back-to-back support when burst size is greater
-- than two data beats. We will never toggle on a burst > 2
-- when last_bram_addr is asserted (as this is no toggle
-- condition)
-- Go to wait for 2nd to last data beat
rlast_sm_ns <= W8_2ND_LAST_DATA;
do_cmplt_burst_clr <= '1';
end if;
end if;
end if;
------------------------- W8_THROTTLE State -----------------------
when W8_THROTTLE =>
if (rd_adv_buf = '1') then
-- Go to wait for 2nd to last data beat
rlast_sm_ns <= W8_2ND_LAST_DATA;
-- If do_cmplt_burst flag is set, then clear it
if (do_cmplt_burst = '1') then
do_cmplt_burst_clr <= '1';
end if;
end if;
---------------------- W8_2ND_LAST_DATA State ---------------------
when W8_2ND_LAST_DATA =>
if (rd_adv_buf = '1') then
-- Assert RLAST on AXI
axi_rlast_set <= '1';
rlast_sm_ns <= W8_LAST_DATA;
end if;
------------------------- W8_LAST_DATA State ----------------------
when W8_LAST_DATA =>
-- If pending single to complete, keep RLAST asserted
-- Added to only assert axi_rlast_set for a single clock cycle
-- when we enter this state and are here waiting for the
-- throttle on the AXI bus.
if (axi_rlast_int = '1') then
axi_rlast_set <= '0';
else
axi_rlast_set <= '1';
end if;
-- Wait for last data beat to transition back to IDLE
if (rd_adv_buf = '1') then
rlast_sm_ns <= IDLE;
end if;
-------------------------- W8_THROTTLE_B2 ------------------------
when W8_THROTTLE_B2 =>
-- Wait for last data beat to transition back to IDLE
-- and set RLAST
if (rd_adv_buf = '1') then
rlast_sm_ns <= IDLE;
axi_rlast_set <= '1';
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
rlast_sm_ns <= IDLE;
--coverage on
end case;
end process RLAST_SM_CMB_PROCESS;
---------------------------------------------------------------------------
RLAST_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
rlast_sm_cs <= IDLE;
else
rlast_sm_cs <= rlast_sm_ns;
end if;
end if;
end process RLAST_SM_REG_PROCESS;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** ECC Logic ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_ECC
-- Purpose: Generate BRAM ECC write data and check ECC on read operations.
-- Create signals to update ECC registers (lite_ecc_reg module interface).
--
---------------------------------------------------------------------------
GEN_ECC: if C_ECC = 1 generate
signal bram_din_a_i : std_logic_vector(0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) := (others => '0'); -- Set for port data width
signal CE_Q : std_logic := '0';
signal Sl_CE_i : std_logic := '0';
signal bram_en_int_d1 : std_logic := '0';
signal bram_en_int_d2 : std_logic := '0';
begin
-- Generate signal to advance BRAM read address pipeline to
-- capture address for ECC error conditions (in lite_ecc_reg module).
-- BRAM_Addr_En <= bram_addr_inc or narrow_bram_addr_inc_re or
-- ((bram_en_int or bram_en_int_reg) and not (axi_rd_burst) and not (axi_rd_burst_two));
BRAM_Addr_En <= bram_addr_inc or narrow_bram_addr_inc_re or rd_adv_buf or
((bram_en_int or bram_en_int_d1 or bram_en_int_d2) and not (axi_rd_burst) and not (axi_rd_burst_two));
-- Enable 2nd & 3rd pipeline stage for BRAM address storage with single read transfers.
BRAM_EN_REG: process(S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
bram_en_int_d1 <= bram_en_int;
bram_en_int_d2 <= bram_en_int_d1;
end if;
end process BRAM_EN_REG;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HAMMING_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
------------------------------------------------------------------------
GEN_HAMMING_ECC: if C_ECC_TYPE = 0 generate
begin
------------------------------------------------------------------------
-- Generate: GEN_ECC_32
-- Purpose: Check ECC data unique for 32-bit BRAM.
-- Add extra '0' at MSB of ECC vector for data2mem alignment
-- w/ 32-bit BRAM data widths.
-- ECC bits are in upper order bits.
------------------------------------------------------------------------
GEN_ECC_32: if C_AXI_DATA_WIDTH = 32 generate
signal bram_din_a_rev : std_logic_vector(31 downto 0) := (others => '0'); -- Specific to BRAM data width
signal bram_din_ecc_a_rev : std_logic_vector(6 downto 0) := (others => '0'); -- Specific to BRAM data width
begin
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_32
-- Description: Generate ECC bits for checking data read from BRAM.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
-- process (bram_din_a_i) begin
-- for k in 0 to 31 loop
-- bram_din_a_rev(k) <= bram_din_a_i(39-k);
-- end loop;
-- for k in 0 to 6 loop
-- bram_din_ecc_a_rev(0) <= bram_din_a_i(6-k);
-- end loop;
-- end process;
CHK_HANDLER_32: entity work.checkbit_handler
generic map (
C_ENCODE => false, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
-- In 32-bit BRAM use case: DataIn (8:39)
-- CheckIn (1:7)
DataIn => bram_din_a_i(C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH), -- [in std_logic_vector(0 to 31)]
CheckIn => bram_din_a_i(1 to C_INT_ECC_WIDTH), -- [in std_logic_vector(0 to 6)]
--DataIn => bram_din_a_rev, -- [in std_logic_vector(0 to 31)]
--CheckIn => bram_din_ecc_a_rev, -- [in std_logic_vector(0 to 6)]
CheckOut => open, -- [out std_logic_vector(0 to 6)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)]
Syndrome_4 => Syndrome_4, -- [out std_logic_vector(0 to 1)]
Syndrome_6 => Syndrome_6, -- [out std_logic_vector(0 to 5)]
Syndrome_Chk => syndrome_reg_i, -- [out std_logic_vector(0 to 6)]
Enable_ECC => Enable_ECC, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i ); -- [out std_logic]
-- GEN_CORR_32 generate & correct_one_bit instantiation moved to generate
-- of AXI RDATA output register logic.
end generate GEN_ECC_32;
------------------------------------------------------------------------
-- Generate: GEN_ECC_64
-- Purpose: Check ECC data unique for 64-bit BRAM.
-- No extra '0' at MSB of ECC vector for data2mem alignment
-- w/ 64-bit BRAM data widths.
-- ECC bits are in upper order bits.
------------------------------------------------------------------------
GEN_ECC_64: if C_AXI_DATA_WIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_64
-- Description: Generate ECC bits for checking data read from BRAM.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
CHK_HANDLER_64: entity work.checkbit_handler_64
generic map (
C_ENCODE => false, -- [boolean]
C_REG => false, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
Clk => S_AXI_AClk, -- [in std_logic]
-- In 64-bit BRAM use case: DataIn (8:71)
-- CheckIn (0:7)
DataIn => bram_din_a_i (C_INT_ECC_WIDTH to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH-1), -- [in std_logic_vector(0 to 63)]
CheckIn => bram_din_a_i (0 to C_INT_ECC_WIDTH-1), -- [in std_logic_vector(0 to 7)]
CheckOut => open, -- [out std_logic_vector(0 to 7)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 7)]
Syndrome_7 => Syndrome_7,
Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 7)]
Enable_ECC => Enable_ECC, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i ); -- [out std_logic]
-- GEN_CORR_64 generate & correct_one_bit instantiation moved to generate
-- of AXI RDATA output register logic.
end generate GEN_ECC_64;
end generate GEN_HAMMING_ECC;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HSIAO_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
-- Derived from MIG v3.7 Hsiao HDL.
------------------------------------------------------------------------
GEN_HSIAO_ECC: if C_ECC_TYPE = 1 generate
constant ECC_WIDTH : integer := C_INT_ECC_WIDTH;
signal syndrome_ns : std_logic_vector (ECC_WIDTH - 1 downto 0) := (others => '0');
begin
-- Generate ECC check bits and syndrome values based on
-- BRAM read data.
-- Generate appropriate single or double bit error flags.
-- Instantiate ecc_gen_hsiao module, generated from MIG
I_ECC_GEN_HSIAO: entity work.ecc_gen
generic map (
code_width => CODE_WIDTH,
ecc_width => ECC_WIDTH,
data_width => C_AXI_DATA_WIDTH
)
port map (
-- Output
h_rows => h_rows (CODE_WIDTH * ECC_WIDTH - 1 downto 0)
);
GEN_RD_ECC: for m in 0 to ECC_WIDTH - 1 generate
begin
syndrome_ns (m) <= REDUCTION_XOR ( -- bram_din_a_i (0 to CODE_WIDTH-1)
BRAM_RdData (CODE_WIDTH-1 downto 0)
and h_rows ((m*CODE_WIDTH)+CODE_WIDTH-1 downto (m*CODE_WIDTH)));
end generate GEN_RD_ECC;
-- Insert register stage for syndrome.
-- Same as Hamming ECC code. Syndrome value is registered.
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
syndrome_r <= syndrome_ns;
end if;
end process REG_SYNDROME;
Sl_CE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
Sl_UE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and not(REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
end generate GEN_HSIAO_ECC;
-- Capture correctable/uncorrectable error from BRAM read
CORR_REG: process(S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (Enable_ECC = '1') and
(axi_rvalid_int = '1' and AXI_RREADY = '1') then -- Capture error flags
CE_Q <= Sl_CE_i;
UE_Q <= Sl_UE_i;
else
CE_Q <= '0';
UE_Q <= '0';
end if;
end if;
end process CORR_REG;
-- The signal, axi_rdata_en loads the syndrome_reg.
-- Use the AXI RVALID/READY signals to capture state of UE and CE.
-- Since flag generation uses the registered syndrome value.
-- ECC register block gets registered UE or CE conditions to update
-- ECC registers/interrupt/flag outputs.
Sl_CE <= CE_Q;
Sl_UE <= UE_Q;
-- CE_Failing_We <= Sl_CE_i and Enable_ECC and axi_rvalid_set;
CE_Failing_We <= CE_Q;
---------------------------------------------------------------------------
-- Generate BRAM read data vector assignment to always be from Port A
-- in a single port BRAM configuration.
-- Map BRAM_RdData (Port A) (N:0) to bram_din_a_i (0:N)
-- Including read back ECC bits.
--
-- Port A or Port B sourcing done at full_axi module level
---------------------------------------------------------------------------
-- Original design with mux (BRAM vs. Skid Buffer) on input side of checkbit_handler logic.
-- Move mux to enable on AXI RDATA register.
bram_din_a_i (0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0);
-- Map data vector from BRAM to use in correct_one_bit module with
-- register syndrome (post AXI RDATA register).
UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1) <= bram_din_a_i (C_ECC_WIDTH to C_ECC_WIDTH+C_AXI_DATA_WIDTH-1);
end generate GEN_ECC;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_NO_ECC
-- Purpose: Drive default output signals when ECC is diabled.
---------------------------------------------------------------------------
GEN_NO_ECC: if C_ECC = 0 generate
begin
BRAM_Addr_En <= '0';
CE_Failing_We <= '0';
Sl_CE <= '0';
Sl_UE <= '0';
end generate GEN_NO_ECC;
---------------------------------------------------------------------------
--
-- *** BRAM Interface Signals ***
--
---------------------------------------------------------------------------
BRAM_En <= bram_en_int;
---------------------------------------------------------------------------
-- BRAM Address Generate
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_L_BRAM_ADDR
-- Purpose: Generate zeros on lower order address bits adjustable
-- based on BRAM data width.
--
---------------------------------------------------------------------------
GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
BRAM_Addr (i) <= '0';
end generate GEN_L_BRAM_ADDR;
---------------------------------------------------------------------------
--
-- Generate: GEN_BRAM_ADDR
-- Purpose: Assign BRAM address output from address counter.
--
---------------------------------------------------------------------------
GEN_BRAM_ADDR: for i in C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
BRAM_Addr (i) <= bram_addr_int (i);
end generate GEN_BRAM_ADDR;
---------------------------------------------------------------------------
end architecture implementation;
|
-------------------------------------------------------------------------------
-- rd_chnl.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: rd_chnl.vhd
--
-- Description: This file is the top level module for the AXI BRAM
-- controller read channel interfaces. Controls all
-- handshaking and data flow on the AXI read address (AR)
-- and read data (R) channels.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Minor code cleanup.
-- Remove library version # dependency. Replace with work library.
-- ^^^^^^
-- JLJ 2/3/2011 v1.03a
-- ~~~~~~
-- Edits for scalability and support of 512 and 1024-bit data widths.
-- ^^^^^^
-- JLJ 2/14/2011 v1.03a
-- ~~~~~~
-- Initial integration of Hsiao ECC algorithm.
-- Add C_ECC_TYPE top level parameter.
-- Similar edits as wr_chnl on Hsiao ECC code.
-- ^^^^^^
-- JLJ 2/18/2011 v1.03a
-- ~~~~~~
-- Update for usage of ecc_gen.vhd module directly from MIG.
-- Clean-up XST warnings.
-- ^^^^^^
-- JLJ 2/22/2011 v1.03a
-- ~~~~~~
-- Found issue with ECC decoding on read path. Remove MSB '0' usage
-- in syndrome calculation, since h_matrix is based on 32 + 7 = 39 bits.
-- Modify read data signal used in single bit error correction.
-- ^^^^^^
-- JLJ 2/23/2011 v1.03a
-- ~~~~~~
-- Move all MIG functions to package body.
-- ^^^^^^
-- JLJ 3/2/2011 v1.03a
-- ~~~~~~
-- Fix XST handling for DIV functions. Create seperate process when
-- divisor is not constant and a power of two.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Clean-up unused signal, narrow_addr_inc.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs. And general code clean-up.
-- ^^^^^^
-- JLJ 4/21/2011 v1.03a
-- ~~~~~~
-- Code clean up.
-- Add defaults to araddr_pipe_sel & axi_arready_int when in single port mode.
-- Remove use of IF_IS_AXI4 constant.
-- ^^^^^^
-- JLJ 4/22/2011 v1.03a
-- ~~~~~~
-- Code clean up.
-- ^^^^^^
-- JLJ 5/6/2011 v1.03a
-- ~~~~~~
-- Remove usage of C_FAMILY.
-- Hard code C_USE_LUT6 constant.
-- ^^^^^^
-- JLJ 5/26/2011 v1.03a
-- ~~~~~~
-- With CR # 609695, update else clause for narrow_burst_cnt_ld to
-- remove simulation warnings when axi_byte_div_curr_arsize = zero.
-- ^^^^^^
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.wrap_brst;
use work.ua_narrow;
use work.checkbit_handler;
use work.checkbit_handler_64;
use work.correct_one_bit;
use work.correct_one_bit_64;
use work.ecc_gen;
use work.parity;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity rd_chnl is
generic (
-- C_FAMILY : string := "virtex6";
-- Specify the target architecture type
C_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_BRAM_ADDR_ADJUST_FACTOR : integer := 2;
-- Adjust factor to BRAM address width based on data width (in bits)
C_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_AXI_ID_WIDTH : integer := 4;
-- AXI ID vector width
C_S_AXI_SUPPORTS_NARROW : integer := 1;
-- Support for narrow burst operations
C_S_AXI_PROTOCOL : string := "AXI4";
-- Set to "AXI4LITE" to optimize out burst transaction support
C_SINGLE_PORT_BRAM : integer := 0;
-- Enable single port usage of BRAM
C_ECC : integer := 0;
-- Enables or disables ECC functionality
C_ECC_WIDTH : integer := 8;
-- Width of ECC data vector
C_ECC_TYPE : integer := 0 -- v1.03a
-- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code
);
port (
-- AXI Global Signals
S_AXI_AClk : in std_logic;
S_AXI_AResetn : in std_logic;
-- AXI Read Address Channel Signals (AR)
AXI_ARID : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
AXI_ARADDR : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0);
AXI_ARLEN : in std_logic_vector(7 downto 0);
-- Specifies the number of data transfers in the burst
-- "0000 0000" 1 data transfer
-- "0000 0001" 2 data transfers
-- ...
-- "1111 1111" 256 data transfers
AXI_ARSIZE : in std_logic_vector(2 downto 0);
-- Specifies the max number of data bytes to transfer in each data beat
-- "000" 1 byte to transfer
-- "001" 2 bytes to transfer
-- "010" 3 bytes to transfer
-- ...
AXI_ARBURST : in std_logic_vector(1 downto 0);
-- Specifies burst type
-- "00" FIXED = Fixed burst address (handled as INCR)
-- "01" INCR = Increment burst address
-- "10" WRAP = Incrementing address burst that wraps to lower order address at boundary
-- "11" Reserved (not checked)
AXI_ARLOCK : in std_logic;
AXI_ARCACHE : in std_logic_vector(3 downto 0);
AXI_ARPROT : in std_logic_vector(2 downto 0);
AXI_ARVALID : in std_logic;
AXI_ARREADY : out std_logic;
-- AXI Read Data Channel Signals (R)
AXI_RID : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
AXI_RDATA : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0);
AXI_RRESP : out std_logic_vector(1 downto 0);
AXI_RLAST : out std_logic;
AXI_RVALID : out std_logic;
AXI_RREADY : in std_logic;
-- ECC Register Interface Signals
Enable_ECC : in std_logic;
BRAM_Addr_En : out std_logic;
CE_Failing_We : out std_logic := '0';
Sl_CE : out std_logic := '0';
Sl_UE : out std_logic := '0';
-- Single Port Arbitration Signals
Arb2AR_Active : in std_logic;
AR2Arb_Active_Clr : out std_logic := '0';
Sng_BRAM_Addr_Ld_En : out std_logic := '0';
Sng_BRAM_Addr_Ld : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
Sng_BRAM_Addr_Inc : out std_logic := '0';
Sng_BRAM_Addr : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR);
-- BRAM Read Port Interface Signals
BRAM_En : out std_logic;
BRAM_Addr : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0);
BRAM_RdData : in std_logic_vector (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0)
);
end entity rd_chnl;
-------------------------------------------------------------------------------
architecture implementation of rd_chnl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- All functions defined in axi_bram_ctrl_funcs package.
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
constant RESP_OKAY : std_logic_vector (1 downto 0) := "00"; -- Normal access OK response
constant RESP_SLVERR : std_logic_vector (1 downto 0) := "10"; -- Slave error
-- For future support. constant RESP_EXOKAY : std_logic_vector (1 downto 0) := "01"; -- Exclusive access OK response
-- For future support. constant RESP_DECERR : std_logic_vector (1 downto 0) := "11"; -- Decode error
-- Set constants for ARLEN equal to a count of one or two beats.
constant AXI_ARLEN_ONE : std_logic_vector(7 downto 0) := (others => '0');
constant AXI_ARLEN_TWO : std_logic_vector(7 downto 0) := "00000001";
-- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width
-- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00"
-- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000"
-- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000"
-- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000"
-- Move to full_axi module
-- constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_AXI_DATA_WIDTH/8);
-- Not used
-- constant C_BRAM_ADDR_ADJUST : integer := C_AXI_ADDR_WIDTH - C_BRAM_ADDR_ADJUST_FACTOR;
-- Determine maximum size for narrow burst length counter
-- When C_AXI_DATA_WIDTH = 32, minimum narrow width burst is 8 bits
-- resulting in a count 3 downto 0 => so minimum counter width = 2 bits.
-- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst is 8 bits
-- resulting in a count 31 downto 0 => so minimum counter width = 5 bits.
constant C_NARROW_BURST_CNT_LEN : integer := log2 (C_AXI_DATA_WIDTH/8);
constant NARROW_CNT_MAX : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
-- Max length burst count AXI4 specification
constant C_MAX_BRST_CNT : integer := 256;
constant C_BRST_CNT_SIZE : integer := log2 (C_MAX_BRST_CNT);
-- When the burst count = 0
constant C_BRST_CNT_ZERO : std_logic_vector(C_BRST_CNT_SIZE-1 downto 0) := (others => '0');
-- Burst count = 1
constant C_BRST_CNT_ONE : std_logic_vector(7 downto 0) := "00000001";
-- Burst count = 2
constant C_BRST_CNT_TWO : std_logic_vector(7 downto 0) := "00000010";
-- Read data mux select constants (for signal rddata_mux_sel)
-- '0' selects BRAM
-- '1' selects read skid buffer
constant C_RDDATA_MUX_BRAM : std_logic := '0';
constant C_RDDATA_MUX_SKID_BUF : std_logic := '1';
-- Determine the number of bytes based on the AXI data width.
constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8;
-- AXI Burst Types
-- AXI Spec 4.4
constant C_AXI_BURST_WRAP : std_logic_vector (1 downto 0) := "10";
constant C_AXI_BURST_INCR : std_logic_vector (1 downto 0) := "01";
constant C_AXI_BURST_FIXED : std_logic_vector (1 downto 0) := "00";
-- AXI Size Constants
-- constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte
-- constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes
-- constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM
-- constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM
-- constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM
-- constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM
-- constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM
-- constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM
-- Determine max value of ARSIZE based on the AXI data width.
-- Use function in axi_bram_ctrl_funcs package.
constant C_AXI_SIZE_MAX : std_logic_vector (2 downto 0) := Create_Size_Max (C_AXI_DATA_WIDTH);
-- Internal ECC data width size.
constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_AXI_DATA_WIDTH);
-- For use with ECC functions (to use LUT6 components or let synthesis infer the optimal implementation).
-- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6;
-- Remove usage of C_FAMILY.
-- All architectures supporting AXI will support a LUT6.
-- Hard code this internal constant used in ECC algorithm.
constant C_USE_LUT6 : boolean := TRUE;
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Read Address Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type RD_ADDR_SM_TYPE is ( IDLE,
LD_ARADDR
);
signal rd_addr_sm_cs, rd_addr_sm_ns : RD_ADDR_SM_TYPE;
signal ar_active_set : std_logic := '0';
signal ar_active_set_i : std_logic := '0';
signal ar_active_clr : std_logic := '0';
signal ar_active : std_logic := '0';
signal ar_active_d1 : std_logic := '0';
signal ar_active_re : std_logic := '0';
signal axi_araddr_pipe : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal curr_araddr_lsb : std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0');
signal araddr_pipe_ld : std_logic := '0';
signal araddr_pipe_ld_i : std_logic := '0';
signal araddr_pipe_sel : std_logic := '0';
-- '0' indicates mux select from AXI
-- '1' indicates mux select from AR Addr Register
signal axi_araddr_full : std_logic := '0';
signal axi_arready_int : std_logic := '0';
signal axi_early_arready_int : std_logic := '0';
signal axi_aresetn_d1 : std_logic := '0';
signal axi_aresetn_d2 : std_logic := '0';
signal axi_aresetn_re : std_logic := '0';
signal axi_aresetn_re_reg : std_logic := '0';
signal no_ar_ack_cmb : std_logic := '0';
signal no_ar_ack : std_logic := '0';
signal pend_rd_op_cmb : std_logic := '0';
signal pend_rd_op : std_logic := '0';
signal axi_arid_pipe : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_arsize_pipe : std_logic_vector (2 downto 0) := (others => '0');
signal axi_arsize_pipe_4byte : std_logic := '0';
signal axi_arsize_pipe_8byte : std_logic := '0';
signal axi_arsize_pipe_16byte : std_logic := '0';
signal axi_arsize_pipe_32byte : std_logic := '0';
-- v1.03a
signal axi_arsize_pipe_max : std_logic := '0';
signal curr_arsize : std_logic_vector (2 downto 0) := (others => '0');
signal curr_arsize_reg : std_logic_vector (2 downto 0) := (others => '0');
signal axi_arlen_pipe : std_logic_vector(7 downto 0) := (others => '0');
signal axi_arlen_pipe_1_or_2 : std_logic := '0';
signal curr_arlen : std_logic_vector(7 downto 0) := (others => '0');
signal curr_arlen_reg : std_logic_vector(7 downto 0) := (others => '0');
signal axi_arburst_pipe : std_logic_vector(1 downto 0) := (others => '0');
signal axi_arburst_pipe_fixed : std_logic := '0';
signal curr_arburst : std_logic_vector(1 downto 0) := (others => '0');
signal curr_wrap_burst : std_logic := '0';
signal curr_wrap_burst_reg : std_logic := '0';
signal max_wrap_burst : std_logic := '0';
signal curr_incr_burst : std_logic := '0';
signal curr_fixed_burst : std_logic := '0';
signal curr_fixed_burst_reg : std_logic := '0';
-- BRAM Address Counter
signal bram_addr_ld_en : std_logic := '0';
signal bram_addr_ld_en_i : std_logic := '0';
signal bram_addr_ld_en_mod : std_logic := '0';
signal bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_ld_wrap : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_inc : std_logic := '0';
signal bram_addr_inc_mod : std_logic := '0';
signal bram_addr_inc_wrap_mod : std_logic := '0';
-------------------------------------------------------------------------------
-- AXI Read Data Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type RD_DATA_SM_TYPE is ( IDLE,
SNG_ADDR,
SEC_ADDR,
FULL_PIPE,
FULL_THROTTLE,
LAST_ADDR,
LAST_THROTTLE,
LAST_DATA,
LAST_DATA_AR_PEND
);
signal rd_data_sm_cs, rd_data_sm_ns : RD_DATA_SM_TYPE;
signal rd_adv_buf : std_logic := '0';
signal axi_rd_burst : std_logic := '0';
signal axi_rd_burst_two : std_logic := '0';
signal act_rd_burst : std_logic := '0';
signal act_rd_burst_set : std_logic := '0';
signal act_rd_burst_clr : std_logic := '0';
signal act_rd_burst_two : std_logic := '0';
-- Rd Data Buffer/Register
signal rd_skid_buf_ld_cmb : std_logic := '0';
signal rd_skid_buf_ld_reg : std_logic := '0';
signal rd_skid_buf_ld : std_logic := '0';
signal rd_skid_buf_ld_imm : std_logic := '0';
signal rd_skid_buf : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal rddata_mux_sel_cmb : std_logic := '0';
signal rddata_mux_sel : std_logic := '0';
signal axi_rdata_en : std_logic := '0';
signal axi_rdata_mux : std_logic_vector (C_AXI_DATA_WIDTH+8*C_ECC-1 downto 0) := (others => '0');
-- Read Burst Counter
signal brst_cnt_max : std_logic := '0';
signal brst_cnt_max_d1 : std_logic := '0';
signal brst_cnt_max_re : std_logic := '0';
signal end_brst_rd_clr_cmb : std_logic := '0';
signal end_brst_rd_clr : std_logic := '0';
signal end_brst_rd : std_logic := '0';
signal brst_zero : std_logic := '0';
signal brst_one : std_logic := '0';
signal brst_cnt_ld : std_logic_vector (C_BRST_CNT_SIZE-1 downto 0) := (others => '0');
signal brst_cnt_rst : std_logic := '0';
signal brst_cnt_ld_en : std_logic := '0';
signal brst_cnt_ld_en_i : std_logic := '0';
signal brst_cnt_dec : std_logic := '0';
signal brst_cnt : std_logic_vector (C_BRST_CNT_SIZE-1 downto 0) := (others => '0');
-- AXI Read Response Signals
signal axi_rid_temp : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_rid_temp_full : std_logic := '0';
signal axi_rid_temp_full_d1 : std_logic := '0';
signal axi_rid_temp_full_fe : std_logic := '0';
signal axi_rid_temp2 : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_rid_temp2_full : std_logic := '0';
signal axi_b2b_rid_adv : std_logic := '0';
signal axi_rid_int : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_rresp_int : std_logic_vector (1 downto 0) := (others => '0');
signal axi_rvalid_clr_ok : std_logic := '0';
signal axi_rvalid_set_cmb : std_logic := '0';
signal axi_rvalid_set : std_logic := '0';
signal axi_rvalid_int : std_logic := '0';
signal axi_rlast_int : std_logic := '0';
signal axi_rlast_set : std_logic := '0';
-- Internal BRAM Signals
signal bram_en_cmb : std_logic := '0';
signal bram_en_int : std_logic := '0';
signal bram_addr_int : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
-- Narrow Burst Signals
signal curr_narrow_burst_cmb : std_logic := '0';
signal curr_narrow_burst : std_logic := '0';
signal narrow_burst_cnt_ld : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal narrow_burst_cnt_ld_reg : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal narrow_burst_cnt_ld_mod : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal narrow_addr_rst : std_logic := '0';
signal narrow_addr_ld_en : std_logic := '0';
signal narrow_addr_dec : std_logic := '0';
signal narrow_bram_addr_inc : std_logic := '0';
signal narrow_bram_addr_inc_d1 : std_logic := '0';
signal narrow_bram_addr_inc_re : std_logic := '0';
signal narrow_addr_int : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal curr_ua_narrow_wrap : std_logic := '0';
signal curr_ua_narrow_incr : std_logic := '0';
signal ua_narrow_load : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
-- State machine type declarations
type RLAST_SM_TYPE is ( IDLE,
W8_THROTTLE,
W8_2ND_LAST_DATA,
W8_LAST_DATA,
-- W8_LAST_DATA_B2,
W8_THROTTLE_B2
);
signal rlast_sm_cs, rlast_sm_ns : RLAST_SM_TYPE;
signal last_bram_addr : std_logic := '0';
signal set_last_bram_addr : std_logic := '0';
signal alast_bram_addr : std_logic := '0';
signal rd_b2b_elgible : std_logic := '0';
signal rd_b2b_elgible_no_thr_check : std_logic := '0';
signal throttle_last_data : std_logic := '0';
signal disable_b2b_brst_cmb : std_logic := '0';
signal disable_b2b_brst : std_logic := '0';
signal axi_b2b_brst_cmb : std_logic := '0';
signal axi_b2b_brst : std_logic := '0';
signal do_cmplt_burst_cmb : std_logic := '0';
signal do_cmplt_burst : std_logic := '0';
signal do_cmplt_burst_clr : std_logic := '0';
-------------------------------------------------------------------------------
-- ECC Signals
-------------------------------------------------------------------------------
signal UnCorrectedRdData : std_logic_vector (0 to C_AXI_DATA_WIDTH-1) := (others => '0');
-- Move vector from core ECC module to use in AXI RDATA register output
signal Syndrome : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
signal Syndrome_4 : std_logic_vector (0 to 1) := (others => '0'); -- Only used in 32-bit ECC
signal Syndrome_6 : std_logic_vector (0 to 5) := (others => '0'); -- Specific to ECC @ 32-bit data width
signal Syndrome_7 : std_logic_vector (0 to 11) := (others => '0'); -- Specific to ECC @ 64-bit data width
signal syndrome_reg : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
signal syndrome_reg_i : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
signal Sl_UE_i : std_logic := '0';
signal UE_Q : std_logic := '0';
-- v1.03a
-- Hsiao ECC
signal syndrome_r : std_logic_vector (C_INT_ECC_WIDTH - 1 downto 0) := (others => '0');
constant CODE_WIDTH : integer := C_AXI_DATA_WIDTH + C_INT_ECC_WIDTH;
constant ECC_WIDTH : integer := C_INT_ECC_WIDTH;
signal h_rows : std_logic_vector (CODE_WIDTH * ECC_WIDTH - 1 downto 0);
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- AXI Read Address Channel Output Signals
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_ARREADY_DUAL
-- Purpose: Generate AXI_ARREADY when in dual port mode.
---------------------------------------------------------------------------
GEN_ARREADY_DUAL: if C_SINGLE_PORT_BRAM = 0 generate
begin
-- Ensure ARREADY only gets asserted early when acknowledge recognized
-- on AXI read data channel.
AXI_ARREADY <= axi_arready_int or (axi_early_arready_int and rd_adv_buf);
end generate GEN_ARREADY_DUAL;
---------------------------------------------------------------------------
-- Generate: GEN_ARREADY_SNG
-- Purpose: Generate AXI_ARREADY when in single port mode.
---------------------------------------------------------------------------
GEN_ARREADY_SNG: if C_SINGLE_PORT_BRAM = 1 generate
begin
-- ARREADY generated by sng_port_arb module
AXI_ARREADY <= '0';
axi_arready_int <= '0';
end generate GEN_ARREADY_SNG;
---------------------------------------------------------------------------
-- AXI Read Data Channel Output Signals
---------------------------------------------------------------------------
-- UE flag is detected is same clock cycle that read data is presented on
-- the AXI bus. Must drive SLVERR combinatorially to align with corrupted
-- detected data word.
AXI_RRESP <= RESP_SLVERR when (C_ECC = 1 and Sl_UE_i = '1') else axi_rresp_int;
AXI_RVALID <= axi_rvalid_int;
AXI_RID <= axi_rid_int;
AXI_RLAST <= axi_rlast_int;
---------------------------------------------------------------------------
--
-- *** AXI Read Address Channel Interface ***
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_AR_PIPE_SNG
-- Purpose: Only generate pipeline registers when in dual port BRAM mode.
---------------------------------------------------------------------------
GEN_AR_PIPE_SNG: if C_SINGLE_PORT_BRAM = 1 generate
begin
-- Unused AW pipeline (set default values)
araddr_pipe_ld <= '0';
axi_araddr_pipe <= AXI_ARADDR;
axi_arid_pipe <= AXI_ARID;
axi_arsize_pipe <= AXI_ARSIZE;
axi_arlen_pipe <= AXI_ARLEN;
axi_arburst_pipe <= AXI_ARBURST;
axi_arlen_pipe_1_or_2 <= '0';
axi_arburst_pipe_fixed <= '0';
axi_araddr_full <= '0';
end generate GEN_AR_PIPE_SNG;
---------------------------------------------------------------------------
-- Generate: GEN_AR_PIPE_DUAL
-- Purpose: Only generate pipeline registers when in dual port BRAM mode.
---------------------------------------------------------------------------
GEN_AR_PIPE_DUAL: if C_SINGLE_PORT_BRAM = 0 generate
begin
-----------------------------------------------------------------------
-- AXI Read Address Buffer/Register
-- (mimic behavior of address pipeline for AXI_ARID)
-----------------------------------------------------------------------
GEN_ARADDR: for i in C_AXI_ADDR_WIDTH-1 downto 0 generate
begin
REG_ARADDR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- No reset condition to save resources/timing
if (araddr_pipe_ld = '1') then
axi_araddr_pipe (i) <= AXI_ARADDR (i);
else
axi_araddr_pipe (i) <= axi_araddr_pipe (i);
end if;
end if;
end process REG_ARADDR;
end generate GEN_ARADDR;
-------------------------------------------------------------------
-- Register ARID
-- No reset condition to save resources/timing
-------------------------------------------------------------------
REG_ARID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (araddr_pipe_ld = '1') then
axi_arid_pipe <= AXI_ARID;
else
axi_arid_pipe <= axi_arid_pipe;
end if;
end if;
end process REG_ARID;
---------------------------------------------------------------------------
-- In parallel to ARADDR pipeline and ARID
-- Use same control signals to capture AXI_ARSIZE, AXI_ARLEN & AXI_ARBURST.
-- Register AXI_ARSIZE, AXI_ARLEN & AXI_ARBURST
-- No reset condition to save resources/timing
REG_ARCTRL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (araddr_pipe_ld = '1') then
axi_arsize_pipe <= AXI_ARSIZE;
axi_arlen_pipe <= AXI_ARLEN;
axi_arburst_pipe <= AXI_ARBURST;
else
axi_arsize_pipe <= axi_arsize_pipe;
axi_arlen_pipe <= axi_arlen_pipe;
axi_arburst_pipe <= axi_arburst_pipe;
end if;
end if;
end process REG_ARCTRL;
---------------------------------------------------------------------------
-- Create signals that indicate value of AXI_ARLEN in pipeline stage
-- Used to decode length of burst when BRAM address can be loaded early
-- when pipeline is full.
--
-- Add early decode of ARBURST in pipeline.
-- Copy logic from WR_CHNL module (similar logic).
-- Add early decode of ARSIZE = 4 bytes in pipeline.
REG_ARLEN_PIPE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- No reset condition to save resources/timing
if (araddr_pipe_ld = '1') then
-- Create merge to decode ARLEN of ONE or TWO
if (AXI_ARLEN = AXI_ARLEN_ONE) or (AXI_ARLEN = AXI_ARLEN_TWO) then
axi_arlen_pipe_1_or_2 <= '1';
else
axi_arlen_pipe_1_or_2 <= '0';
end if;
-- Early decode on value in pipeline of ARBURST
if (AXI_ARBURST = C_AXI_BURST_FIXED) then
axi_arburst_pipe_fixed <= '1';
else
axi_arburst_pipe_fixed <= '0';
end if;
else
axi_arlen_pipe_1_or_2 <= axi_arlen_pipe_1_or_2;
axi_arburst_pipe_fixed <= axi_arburst_pipe_fixed;
end if;
end if;
end process REG_ARLEN_PIPE;
---------------------------------------------------------------------------
-- Create full flag for ARADDR pipeline
-- Set when read address register is loaded.
-- Cleared when read address stored in register is loaded into BRAM
-- address counter.
REG_RDADDR_FULL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- (bram_addr_ld_en = '1' and araddr_pipe_sel = '1') then
(bram_addr_ld_en = '1' and araddr_pipe_sel = '1' and araddr_pipe_ld = '0') then
axi_araddr_full <= '0';
elsif (araddr_pipe_ld = '1') then
axi_araddr_full <= '1';
else
axi_araddr_full <= axi_araddr_full;
end if;
end if;
end process REG_RDADDR_FULL;
---------------------------------------------------------------------------
end generate GEN_AR_PIPE_DUAL;
---------------------------------------------------------------------------
-- v1.03a
-- Add early decode of ARSIZE = max size in pipeline based on AXI data
-- bus width (use constant, C_AXI_SIZE_MAX)
REG_ARSIZE_PIPE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_arsize_pipe_max <= '0';
elsif (araddr_pipe_ld = '1') then
-- Early decode of ARSIZE in pipeline equal to max # of bytes
-- based on AXI data bus width
if (AXI_ARSIZE = C_AXI_SIZE_MAX) then
axi_arsize_pipe_max <= '1';
else
axi_arsize_pipe_max <= '0';
end if;
else
axi_arsize_pipe_max <= axi_arsize_pipe_max;
end if;
end if;
end process REG_ARSIZE_PIPE;
---------------------------------------------------------------------------
-- Generate: GE_ARREADY
-- Purpose: ARREADY is only created here when in dual port BRAM mode.
---------------------------------------------------------------------------
GEN_ARREADY: if (C_SINGLE_PORT_BRAM = 0) generate
begin
----------------------------------------------------------------------------
-- AXI_ARREADY Output Register
-- Description: Keep AXI_ARREADY output asserted until ARADDR pipeline
-- is full. When a full condition is reached, negate
-- ARREADY as another AR address can not be accepted.
-- Add condition to keep ARReady asserted if loading current
--- ARADDR pipeline value into the BRAM address counter.
-- Indicated by assertion of bram_addr_ld_en & araddr_pipe_sel.
--
----------------------------------------------------------------------------
REG_ARREADY: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_arready_int <= '0';
-- Detect end of S_AXI_AResetn to assert AWREADY and accept
-- new AWADDR values
elsif (axi_aresetn_re_reg = '1') or
-- Add condition for early ARREADY to keep pipeline full
(bram_addr_ld_en = '1' and araddr_pipe_sel = '1' and axi_early_arready_int = '0') then
axi_arready_int <= '1';
-- Add conditional check if ARREADY is asserted (with ARVALID) (one clock cycle later)
-- when the address pipeline is full.
elsif (araddr_pipe_ld = '1') or
(AXI_ARVALID = '1' and axi_arready_int = '1' and axi_araddr_full = '1') then
axi_arready_int <= '0';
else
axi_arready_int <= axi_arready_int;
end if;
end if;
end process REG_ARREADY;
----------------------------------------------------------------------------
REG_EARLY_ARREADY: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_early_arready_int <= '0';
-- Pending ARADDR and ARREADY is not yet asserted to accept
-- operation (due to ARADDR being full)
elsif (AXI_ARVALID = '1' and axi_arready_int = '0' and
axi_araddr_full = '1') and
(alast_bram_addr = '1') and
-- Add check for elgible back-to-back BRAM load
(rd_b2b_elgible = '1') then
axi_early_arready_int <= '1';
else
axi_early_arready_int <= '0';
end if;
end if;
end process REG_EARLY_ARREADY;
---------------------------------------------------------------------------
-- Need to detect end of reset cycle to assert ARREADY on AXI bus
REG_ARESETN: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
axi_aresetn_d1 <= S_AXI_AResetn;
axi_aresetn_d2 <= axi_aresetn_d1;
axi_aresetn_re_reg <= axi_aresetn_re;
end if;
end process REG_ARESETN;
-- Create combinatorial RE detect of S_AXI_AResetn
axi_aresetn_re <= '1' when (S_AXI_AResetn = '1' and axi_aresetn_d1 = '0') else '0';
----------------------------------------------------------------------------
end generate GEN_ARREADY;
---------------------------------------------------------------------------
-- Generate: GEN_DUAL_ADDR_CNT
-- Purpose: Instantiate BRAM address counter unique for wr_chnl logic
-- only when controller configured in dual port mode.
---------------------------------------------------------------------------
GEN_DUAL_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
---------------------------------------------------------------------------
-- Replace I_ADDR_CNT module usage of pf_counter in proc_common library.
-- Only need to use lower 12-bits of address due to max AXI burst size
-- Since AXI guarantees bursts do not cross 4KB boundary, the counting part
-- of I_ADDR_CNT can be reduced to max 4KB.
--
-- No reset on bram_addr_int.
-- Increment ONLY.
REG_ADDR_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (bram_addr_ld_en_mod = '1') then
bram_addr_int <= bram_addr_ld;
elsif (bram_addr_inc_mod = '1') then
bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12) <=
bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12);
bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR) <=
std_logic_vector (unsigned (bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR)) + 1);
end if;
end if;
end process REG_ADDR_CNT;
---------------------------------------------------------------------------
-- Set defaults to shared address counter
-- Only used in single port configurations
Sng_BRAM_Addr_Ld_En <= '0';
Sng_BRAM_Addr_Ld <= (others => '0');
Sng_BRAM_Addr_Inc <= '0';
end generate GEN_DUAL_ADDR_CNT;
---------------------------------------------------------------------------
-- Generate: GEN_SNG_ADDR_CNT
-- Purpose: When configured in single port BRAM mode, address counter
-- is shared with rd_chnl module. Assign output signals here
-- to counter instantiation at full_axi module level.
---------------------------------------------------------------------------
GEN_SNG_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
Sng_BRAM_Addr_Ld_En <= bram_addr_ld_en_mod;
Sng_BRAM_Addr_Ld <= bram_addr_ld;
Sng_BRAM_Addr_Inc <= bram_addr_inc_mod;
bram_addr_int <= Sng_BRAM_Addr;
end generate GEN_SNG_ADDR_CNT;
---------------------------------------------------------------------------
-- BRAM address load mux.
-- Either load BRAM counter directly from AXI bus or from stored registered value
-- Use registered signal to indicate current operation is a WRAP burst
--
-- Match bram_addr_ld to what asserts bram_addr_ld_en_mod
-- Include bram_addr_inc_mod when asserted to use bram_addr_ld_wrap value
-- (otherwise use pipelined or AXI bus value to load BRAM address counter)
bram_addr_ld <= bram_addr_ld_wrap when (max_wrap_burst = '1' and
curr_wrap_burst_reg = '1' and
bram_addr_inc_wrap_mod = '1') else
axi_araddr_pipe (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
when (araddr_pipe_sel = '1') else
AXI_ARADDR (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR);
---------------------------------------------------------------------------
-- On wrap burst max loads (simultaneous BRAM address increment is asserted).
-- Ensure that load has higher priority over increment.
-- Use registered signal to indicate current operation is a WRAP burst
bram_addr_ld_en_mod <= '1' when (bram_addr_ld_en = '1' or
(max_wrap_burst = '1' and
curr_wrap_burst_reg = '1' and
bram_addr_inc_wrap_mod = '1'))
else '0';
-- Create a special bram_addr_inc_mod for use in the bram_addr_ld_en_mod signal
-- logic. No need for the check if the current operation is NOT a fixed AND a wrap
-- burst. The transfer will be one or the other.
-- Found issue when narrow FIXED length burst is incorrectly
-- incrementing BRAM address counter
bram_addr_inc_wrap_mod <= bram_addr_inc when (curr_narrow_burst = '0')
else narrow_bram_addr_inc_re;
----------------------------------------------------------------------------
-- Narrow bursting
--
-- Handle read burst addressing on narrow burst operations
-- Intercept BRAM address increment flag, bram_addr_inc and only
-- increment address when the number of BRAM reads match the width of the
-- AXI data bus.
-- For a 32-bit BRAM, byte burst will increment the BRAM address
-- after four reads from BRAM.
-- For a 256-bit BRAM, a byte burst will increment the BRAM address
-- after 32 reads from BRAM.
-- Based on current operation being a narrow burst, hold off BRAM
-- address increment until narrow burst fits BRAM data width.
-- For non narrow burst operations, use bram_addr_inc from data SM.
--
-- Add in check that burst type is not FIXED, curr_fixed_burst_reg
-- bram_addr_inc_mod <= (bram_addr_inc and not (curr_fixed_burst_reg)) when (curr_narrow_burst = '0') else
-- narrow_bram_addr_inc_re;
--
--
-- Replace w/ below generate statements based on supporting narrow transfers or not.
-- Create generate statement around the signal assignment for bram_addr_inc_mod.
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_INC_MOD_W_NARROW
-- Purpose: Assign signal, bram_addr_inc_mod when narrow transfers
-- are supported in design instantiation.
---------------------------------------------------------------------------
GEN_BRAM_INC_MOD_W_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
-- Found issue when narrow FIXED length burst is incorrectly incrementing BRAM address counter
bram_addr_inc_mod <= (bram_addr_inc and not (curr_fixed_burst_reg)) when (curr_narrow_burst = '0') else
(narrow_bram_addr_inc_re and not (curr_fixed_burst_reg));
end generate GEN_BRAM_INC_MOD_W_NARROW;
---------------------------------------------------------------------------
-- Generate: GEN_WO_NARROW
-- Purpose: Assign signal, bram_addr_inc_mod when narrow transfers
-- are not supported in the design instantiation.
-- Drive default values for narrow counter and logic when
-- narrow operation support is disabled.
---------------------------------------------------------------------------
GEN_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 0) generate
begin
-- Found issue when narrow FIXED length burst is incorrectly incrementing BRAM address counter
bram_addr_inc_mod <= bram_addr_inc and not (curr_fixed_burst_reg);
narrow_addr_rst <= '0';
narrow_burst_cnt_ld_mod <= (others => '0');
narrow_addr_dec <= '0';
narrow_addr_ld_en <= '0';
narrow_bram_addr_inc <= '0';
narrow_bram_addr_inc_d1 <= '0';
narrow_bram_addr_inc_re <= '0';
narrow_addr_int <= (others => '0');
curr_narrow_burst <= '0';
end generate GEN_WO_NARROW;
---------------------------------------------------------------------------
--
-- Only instantiate NARROW_CNT and supporting logic when narrow transfers
-- are supported and utilized by masters in the AXI system.
-- The design parameter, C_S_AXI_SUPPORTS_NARROW will indicate this.
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_NARROW_CNT
-- Purpose: Instantiate narrow counter and logic when narrow
-- operation support is enabled.
---------------------------------------------------------------------------
GEN_NARROW_CNT: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
---------------------------------------------------------------------------
--
-- Generate seperate smaller counter for narrow burst operations
-- Replace I_NARROW_CNT module usage of pf_counter_top from proc_common library.
--
-- Counter size is adjusted based on size of data burst.
--
-- For example, 32-bit data width BRAM, minimum narrow width
-- burst is 8 bits resulting in a count 3 downto 0. So the
-- minimum counter width = 2 bits.
--
-- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst
-- is 8 bits resulting in a count 31 downto 0. So the
-- minimum counter width = 5 bits.
--
-- Size of counter = C_NARROW_BURST_CNT_LEN
--
---------------------------------------------------------------------------
REG_NARROW_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (narrow_addr_rst = '1') then
narrow_addr_int <= (others => '0');
-- Load enable
elsif (narrow_addr_ld_en = '1') then
narrow_addr_int <= narrow_burst_cnt_ld_mod;
-- Decrement ONLY (no increment functionality)
elsif (narrow_addr_dec = '1') then
narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0) <=
std_logic_vector (unsigned (narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0)) - 1);
end if;
end if;
end process REG_NARROW_CNT;
---------------------------------------------------------------------------
narrow_addr_rst <= not (S_AXI_AResetn);
-- Modify narrow burst count load value based on
-- unalignment of AXI address value
narrow_burst_cnt_ld_mod <= ua_narrow_load when (curr_ua_narrow_wrap = '1' or curr_ua_narrow_incr = '1') else
narrow_burst_cnt_ld when (bram_addr_ld_en = '1') else
narrow_burst_cnt_ld_reg;
narrow_addr_dec <= bram_addr_inc when (curr_narrow_burst = '1') else '0';
narrow_addr_ld_en <= (curr_narrow_burst_cmb and bram_addr_ld_en) or narrow_bram_addr_inc_re;
narrow_bram_addr_inc <= '1' when (narrow_addr_int = NARROW_CNT_MAX) and
(curr_narrow_burst = '1')
-- Ensure that narrow address counter doesn't
-- flag max or get loaded to
-- reset narrow counter until AXI read data
-- bus has acknowledged current
-- data on the AXI bus. Use rd_adv_buf signal
-- to indicate the non throttle
-- condition on the AXI bus.
and (bram_addr_inc = '1')
else '0';
----------------------------------------------------------------------------
-- Detect rising edge of narrow_bram_addr_inc
REG_NARROW_BRAM_ADDR_INC: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
narrow_bram_addr_inc_d1 <= '0';
else
narrow_bram_addr_inc_d1 <= narrow_bram_addr_inc;
end if;
end if;
end process REG_NARROW_BRAM_ADDR_INC;
narrow_bram_addr_inc_re <= '1' when (narrow_bram_addr_inc = '1') and
(narrow_bram_addr_inc_d1 = '0')
else '0';
---------------------------------------------------------------------------
end generate GEN_NARROW_CNT;
----------------------------------------------------------------------------
-- Specify current ARSIZE signal
-- Address pipeline MUX
curr_arsize <= axi_arsize_pipe when (araddr_pipe_sel = '1') else AXI_ARSIZE;
REG_ARSIZE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
curr_arsize_reg <= (others => '0');
-- Register curr_arsize when bram_addr_ld_en = '1'
elsif (bram_addr_ld_en = '1') then
curr_arsize_reg <= curr_arsize;
else
curr_arsize_reg <= curr_arsize_reg;
end if;
end if;
end process REG_ARSIZE;
---------------------------------------------------------------------------
-- Generate: GEN_NARROW_EN
-- Purpose: Only instantiate logic to determine if current burst
-- is a narrow burst when narrow bursting logic is supported.
---------------------------------------------------------------------------
GEN_NARROW_EN: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
-----------------------------------------------------------------------
-- Determine "narrow" burst transfers
-- Compare the ARSIZE to the BRAM data width
-----------------------------------------------------------------------
-- v1.03a
-- Detect if current burst operation is of size /= to the full
-- AXI data bus width. If not, then the current operation is a
-- "narrow" burst.
curr_narrow_burst_cmb <= '1' when (curr_arsize /= C_AXI_SIZE_MAX) else '0';
---------------------------------------------------------------------------
-- Register flag indicating the current operation
-- is a narrow read burst
NARROW_BURST_REG: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- Need to reset this flag at end of narrow burst operation
-- Ensure if curr_narrow_burst got set during previous transaction, axi_rlast_set
-- doesn't clear the flag (add check for pend_rd_op negated).
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_set = '1' and pend_rd_op = '0' and bram_addr_ld_en = '0') then
curr_narrow_burst <= '0';
-- Add check for burst operation using ARLEN value
-- Ensure that narrow burst flag does not get set during FIXED burst types
elsif (bram_addr_ld_en = '1') and (curr_arlen /= AXI_ARLEN_ONE) and
(curr_fixed_burst = '0') then
curr_narrow_burst <= curr_narrow_burst_cmb;
end if;
end if;
end process NARROW_BURST_REG;
end generate GEN_NARROW_EN;
---------------------------------------------------------------------------
-- Generate: GEN_NARROW_CNT_LD
-- Purpose: Only instantiate logic to determine narrow burst counter
-- load value when narrow bursts are enabled.
---------------------------------------------------------------------------
GEN_NARROW_CNT_LD: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
signal curr_arsize_unsigned : unsigned (2 downto 0) := (others => '0');
signal axi_byte_div_curr_arsize : integer := 1;
begin
-- v1.03a
-- Create narrow burst counter load value based on current operation
-- "narrow" data width (indicated by value of AWSIZE).
curr_arsize_unsigned <= unsigned (curr_arsize);
-- XST does not support divisors that are not constants and powers of 2.
-- Create process to create a fixed value for divisor.
-- Replace this statement:
-- narrow_burst_cnt_ld <= std_logic_vector (
-- to_unsigned (
-- (C_AXI_DATA_WIDTH_BYTES / (2**(to_integer (curr_arsize_unsigned))) ) - 1,
-- C_NARROW_BURST_CNT_LEN));
-- -- With this new process and subsequent signal assignment:
-- DIV_AWSIZE: process (curr_arsize_unsigned)
-- begin
--
-- case (to_integer (curr_arsize_unsigned)) is
-- when 0 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 1;
-- when 1 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 2;
-- when 2 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 4;
-- when 3 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 8;
-- when 4 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 16;
-- when 5 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 32;
-- when 6 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 64;
-- when 7 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 128;
-- --coverage off
-- when others => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES;
-- --coverage on
-- end case;
--
-- end process DIV_AWSIZE;
-- w/ CR # 609695
-- With this new process and subsequent signal assignment:
DIV_AWSIZE: process (curr_arsize_unsigned)
begin
case (curr_arsize_unsigned) is
when "000" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 1;
when "001" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 2;
when "010" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 4;
when "011" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 8;
when "100" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 16;
when "101" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 32;
when "110" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 64;
when "111" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 128;
--coverage off
when others => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES;
--coverage on
end case;
end process DIV_AWSIZE;
-- v1.03a
-- Replace with new signal assignment.
-- For synthesis to support only divisors that are constant and powers of two.
-- Updated else clause for simulation warnings w/ CR # 609695
narrow_burst_cnt_ld <= std_logic_vector (
to_unsigned (
(axi_byte_div_curr_arsize) - 1, C_NARROW_BURST_CNT_LEN))
when (axi_byte_div_curr_arsize > 0)
else std_logic_vector (to_unsigned (0, C_NARROW_BURST_CNT_LEN));
---------------------------------------------------------------------------
-- Register narrow burst count load indicator
REG_NAR_BRST_CNT_LD: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
narrow_burst_cnt_ld_reg <= (others => '0');
elsif (bram_addr_ld_en = '1') then
narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld;
else
narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld_reg;
end if;
end if;
end process REG_NAR_BRST_CNT_LD;
---------------------------------------------------------------------------
end generate GEN_NARROW_CNT_LD;
----------------------------------------------------------------------------
-- Handling for WRAP burst types
--
-- For WRAP burst types, the counter value will roll over when the burst
-- boundary is reached.
-- Boundary is reached based on ARSIZE and ARLEN.
--
-- Goal is to minimize muxing on initial load of counter value.
-- On WRAP burst types, detect when the max address is reached.
-- When the max address is reached, re-load counter with lower
-- address value set to '0'.
----------------------------------------------------------------------------
-- Detect valid WRAP burst types
curr_wrap_burst <= '1' when (curr_arburst = C_AXI_BURST_WRAP) else '0';
curr_incr_burst <= '1' when (curr_arburst = C_AXI_BURST_INCR) else '0';
curr_fixed_burst <= '1' when (curr_arburst = C_AXI_BURST_FIXED) else '0';
----------------------------------------------------------------------------
-- Register curr_wrap_burst & curr_fixed_burst signals when BRAM
-- address counter is initially loaded
REG_CURR_BRST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
curr_wrap_burst_reg <= '0';
curr_fixed_burst_reg <= '0';
elsif (bram_addr_ld_en = '1') then
curr_wrap_burst_reg <= curr_wrap_burst;
curr_fixed_burst_reg <= curr_fixed_burst;
else
curr_wrap_burst_reg <= curr_wrap_burst_reg;
curr_fixed_burst_reg <= curr_fixed_burst_reg;
end if;
end if;
end process REG_CURR_BRST;
---------------------------------------------------------------------------
-- Instance: I_WRAP_BRST
--
-- Description:
--
-- Instantiate WRAP_BRST module
-- Logic to generate the wrap around value to load into the BRAM address
-- counter on WRAP burst transactions.
-- WRAP value is based on current ARLEN, ARSIZE (for narrows) and
-- data width of BRAM module.
--
---------------------------------------------------------------------------
I_WRAP_BRST : entity work.wrap_brst
generic map (
C_AXI_ADDR_WIDTH => C_AXI_ADDR_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH
)
port map (
S_AXI_AClk => S_AXI_ACLK ,
S_AXI_AResetn => S_AXI_ARESETN ,
curr_axlen => curr_arlen ,
curr_axsize => curr_arsize ,
curr_narrow_burst => curr_narrow_burst ,
narrow_bram_addr_inc_re => narrow_bram_addr_inc_re ,
bram_addr_ld_en => bram_addr_ld_en ,
bram_addr_ld => bram_addr_ld ,
bram_addr_int => bram_addr_int ,
bram_addr_ld_wrap => bram_addr_ld_wrap ,
max_wrap_burst_mod => max_wrap_burst
);
----------------------------------------------------------------------------
-- Specify current ARBURST signal
-- Input address pipeline MUX
curr_arburst <= axi_arburst_pipe when (araddr_pipe_sel = '1') else AXI_ARBURST;
----------------------------------------------------------------------------
-- Specify current AWBURST signal
-- Input address pipeline MUX
curr_arlen <= axi_arlen_pipe when (araddr_pipe_sel = '1') else AXI_ARLEN;
----------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_UA_NARROW
-- Purpose: Only instantiate logic for burst narrow WRAP operations when
-- AXI bus protocol is not set for AXI-LITE and narrow
-- burst operations are supported.
--
---------------------------------------------------------------------------
GEN_UA_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
---------------------------------------------------------------------------
--
-- New logic to detect unaligned address on a narrow WRAP burst transaction.
-- If this condition is met, then the narrow burst counter will be
-- initially loaded with an offset value corresponding to the unalignment
-- in the ARADDR value.
--
--
-- Create a sub module for all logic to determine the narrow burst counter
-- offset value on unaligned WRAP burst operations.
--
-- Module generates the following signals:
--
-- => curr_ua_narrow_wrap, to indicate the current
-- operation is an unaligned narrow WRAP burst.
--
-- => curr_ua_narrow_incr, to load narrow burst counter
-- for unaligned INCR burst operations.
--
-- => ua_narrow_load, narrow counter load value.
-- Sized, (C_NARROW_BURST_CNT_LEN-1 downto 0)
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Instance: I_UA_NARROW
--
-- Description:
--
-- Creates a narrow burst count load value when an operation
-- is an unaligned narrow WRAP or INCR burst type. Used by
-- I_NARROW_CNT module.
--
-- Logic is customized for each C_AXI_DATA_WIDTH.
--
---------------------------------------------------------------------------
I_UA_NARROW : entity work.ua_narrow
generic map (
C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_NARROW_BURST_CNT_LEN => C_NARROW_BURST_CNT_LEN
)
port map (
curr_wrap_burst => curr_wrap_burst , -- in
curr_incr_burst => curr_incr_burst , -- in
bram_addr_ld_en => bram_addr_ld_en , -- in
curr_axlen => curr_arlen , -- in
curr_axsize => curr_arsize , -- in
curr_axaddr_lsb => curr_araddr_lsb , -- in
curr_ua_narrow_wrap => curr_ua_narrow_wrap , -- out
curr_ua_narrow_incr => curr_ua_narrow_incr , -- out
ua_narrow_load => ua_narrow_load -- out
);
-- Use in all C_AXI_DATA_WIDTH generate statements
-- Only probe least significant BRAM address bits
-- C_BRAM_ADDR_ADJUST_FACTOR offset down to 0.
curr_araddr_lsb <= axi_araddr_pipe (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0)
when (araddr_pipe_sel = '1') else
AXI_ARADDR (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0);
end generate GEN_UA_NARROW;
----------------------------------------------------------------------------
--
-- New logic to detect if pending operation in ARADDR pipeline is
-- elgible for back-to-back no "bubble" performance. And BRAM address
-- counter can be loaded upon last BRAM address presented for the current
-- operation.
-- This condition exists when the ARADDR pipeline is full and the pending
-- operation is a burst >= length of two data beats.
-- And not a FIXED burst type (must be INCR or WRAP type).
-- The DATA SM handles detecting a throttle condition and will void
-- the capability to be a back-to-back in performance transaction.
--
-- Add check if new operation is a narrow burst (to be loaded into BRAM
-- counter)
-- Add check for throttling condition on after last BRAM address is
-- presented
--
----------------------------------------------------------------------------
-- v1.03a
rd_b2b_elgible_no_thr_check <= '1' when (axi_araddr_full = '1') and
(axi_arlen_pipe_1_or_2 /= '1') and
(axi_arburst_pipe_fixed /= '1') and
(disable_b2b_brst = '0') and
(axi_arsize_pipe_max = '1')
else '0';
rd_b2b_elgible <= '1' when (rd_b2b_elgible_no_thr_check = '1') and
(throttle_last_data = '0')
else '0';
-- Check if SM is in LAST_THROTTLE state which also indicates we are throttling at
-- the last data beat in the read burst. Ensures that the bursts are not implemented
-- as back-to-back bursts and RVALID will negate upon recognition of RLAST and RID
-- pipeline will be advanced properly.
-- Fix timing path on araddr_pipe_sel generated in RDADDR SM
-- SM uses rd_b2b_elgible signal which checks throttle condition on
-- last data beat to hold off loading new BRAM address counter for next
-- back-to-back operation.
-- Attempt to modify logic in generation of throttle_last_data signal.
throttle_last_data <= '1' when ((brst_zero = '1') and (rd_adv_buf = '0')) or
(rd_data_sm_cs = LAST_THROTTLE)
else '0';
----------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_AR_SNG
-- Purpose: If single port BRAM configuration, set all AR flags from
-- logic generated in sng_port_arb module.
--
---------------------------------------------------------------------------
GEN_AR_SNG: if (C_SINGLE_PORT_BRAM = 1) generate
begin
araddr_pipe_sel <= '0'; -- Unused in single port configuration
ar_active <= Arb2AR_Active;
bram_addr_ld_en <= ar_active_re;
brst_cnt_ld_en <= ar_active_re;
AR2Arb_Active_Clr <= axi_rlast_int and AXI_RREADY;
-- Rising edge detect of Arb2AR_Active
RE_AR_ACT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- Clear ar_active_d1 early w/ ar_active
-- So back to back ar_active assertions see the new transaction
-- and initiate the read transfer.
if (S_AXI_AResetn = C_RESET_ACTIVE) or ((axi_rlast_int and AXI_RREADY) = '1') then
ar_active_d1 <= '0';
else
ar_active_d1 <= ar_active;
end if;
end if;
end process RE_AR_ACT;
ar_active_re <= '1' when (ar_active = '1' and ar_active_d1 = '0') else '0';
end generate GEN_AR_SNG;
---------------------------------------------------------------------------
--
-- Generate: GEN_AW_DUAL
-- Purpose: Generate AW control state machine logic only when AXI4
-- controller is configured for dual port mode. In dual port
-- mode, wr_chnl has full access over AW & port A of BRAM.
--
---------------------------------------------------------------------------
GEN_AR_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate
begin
AR2Arb_Active_Clr <= '0'; -- Only used in single port case
---------------------------------------------------------------------------
-- RD ADDR State Machine
--
-- Description: Central processing unit for AXI write address
-- channel interface handling and handshaking.
--
-- Outputs: araddr_pipe_ld Not Registered
-- araddr_pipe_sel Not Registered
-- bram_addr_ld_en Not Registered
-- brst_cnt_ld_en Not Registered
-- ar_active_set Not Registered
--
-- WR_ADDR_SM_CMB_PROCESS: Combinational process to determine next state.
-- WR_ADDR_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
RD_ADDR_SM_CMB_PROCESS: process ( AXI_ARVALID,
axi_araddr_full,
ar_active,
no_ar_ack,
pend_rd_op,
last_bram_addr,
rd_b2b_elgible,
rd_addr_sm_cs )
begin
-- assign default values for state machine outputs
rd_addr_sm_ns <= rd_addr_sm_cs;
araddr_pipe_ld_i <= '0';
bram_addr_ld_en_i <= '0';
brst_cnt_ld_en_i <= '0';
ar_active_set_i <= '0';
case rd_addr_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Reload BRAM address counter on last BRAM address of current burst
-- if a new address is pending in the AR pipeline and is elgible to
-- be loaded for subsequent back-to-back performance.
if (last_bram_addr = '1' and rd_b2b_elgible = '1') then
-- Load BRAM address counter from pipelined value
bram_addr_ld_en_i <= '1';
brst_cnt_ld_en_i <= '1';
ar_active_set_i <= '1';
-- If loading BRAM counter for subsequent operation
-- AND ARVALID is pending on the bus, go ahead and respond
-- and fill ARADDR pipeline with next operation.
--
-- Asserting the signal to load the ARADDR pipeline here
-- allows the full bandwidth utilization to BRAM on
-- back to back bursts of two data beats.
if (AXI_ARVALID = '1') then
araddr_pipe_ld_i <= '1';
rd_addr_sm_ns <= LD_ARADDR;
else
rd_addr_sm_ns <= IDLE;
end if;
elsif (AXI_ARVALID = '1') then
-- If address pipeline is full
-- ARReady output is negated
-- Remain in this state
--
-- Add check for already pending read operation
-- in data SM, but waiting on throttle (even though ar_active is
-- already set to '0').
if (ar_active = '0') and (no_ar_ack = '0') and (pend_rd_op = '0') then
rd_addr_sm_ns <= IDLE;
bram_addr_ld_en_i <= '1';
brst_cnt_ld_en_i <= '1';
ar_active_set_i <= '1';
-- Address counter is currently busy
else
-- Check if ARADDR pipeline is not full and can be loaded
if (axi_araddr_full = '0') then
rd_addr_sm_ns <= LD_ARADDR;
araddr_pipe_ld_i <= '1';
end if;
end if; -- ar_active
-- Pending operation in pipeline that is waiting
-- until current operation is complete (ar_active = '0')
elsif (axi_araddr_full = '1') and
(ar_active = '0') and
(no_ar_ack = '0') and
(pend_rd_op = '0') then
rd_addr_sm_ns <= IDLE;
-- Load BRAM address counter from pipelined value
bram_addr_ld_en_i <= '1';
brst_cnt_ld_en_i <= '1';
ar_active_set_i <= '1';
end if; -- ARVALID
---------------------------- LD_ARADDR State ---------------------------
when LD_ARADDR =>
-- Check here for subsequent BRAM address load when ARADDR pipe is loaded
-- in previous clock cycle.
--
-- Reload BRAM address counter on last BRAM address of current burst
-- if a new address is pending in the AR pipeline and is elgible to
-- be loaded for subsequent back-to-back performance.
if (last_bram_addr = '1' and rd_b2b_elgible = '1') then
-- Load BRAM address counter from pipelined value
bram_addr_ld_en_i <= '1';
brst_cnt_ld_en_i <= '1';
ar_active_set_i <= '1';
-- If loading BRAM counter for subsequent operation
-- AND ARVALID is pending on the bus, go ahead and respond
-- and fill ARADDR pipeline with next operation.
--
-- Asserting the signal to load the ARADDR pipeline here
-- allows the full bandwidth utilization to BRAM on
-- back to back bursts of two data beats.
if (AXI_ARVALID = '1') then
araddr_pipe_ld_i <= '1';
rd_addr_sm_ns <= LD_ARADDR;
-- Stay in this state another clock cycle
else
rd_addr_sm_ns <= IDLE;
end if;
else
rd_addr_sm_ns <= IDLE;
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
rd_addr_sm_ns <= IDLE;
--coverage on
end case;
end process RD_ADDR_SM_CMB_PROCESS;
---------------------------------------------------------------------------
-- CR # 582705
-- Ensure combinatorial SM output signals do not get set before
-- the end of the reset (and ARREAADY can be set).
bram_addr_ld_en <= bram_addr_ld_en_i and axi_aresetn_d2;
brst_cnt_ld_en <= brst_cnt_ld_en_i and axi_aresetn_d2;
ar_active_set <= ar_active_set_i and axi_aresetn_d2;
araddr_pipe_ld <= araddr_pipe_ld_i and axi_aresetn_d2;
RD_ADDR_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- if (S_AXI_AResetn = C_RESET_ACTIVE) then
-- CR # 582705
-- Ensure that ar_active does not get asserted (from SM) before
-- the end of reset and the ARREADY flag is set.
if (axi_aresetn_d2 = C_RESET_ACTIVE) then
rd_addr_sm_cs <= IDLE;
else
rd_addr_sm_cs <= rd_addr_sm_ns;
end if;
end if;
end process RD_ADDR_SM_REG_PROCESS;
---------------------------------------------------------------------------
-- Assert araddr_pipe_sel outside of SM logic
-- The BRAM address counter will get loaded with value in ARADDR pipeline
-- when data is stored in the ARADDR pipeline.
araddr_pipe_sel <= '1' when (axi_araddr_full = '1') else '0';
---------------------------------------------------------------------------
-- Register for ar_active
REG_AR_ACT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- if (S_AXI_AResetn = C_RESET_ACTIVE) then
-- CR # 582705
if (axi_aresetn_d2 = C_RESET_ACTIVE) then
ar_active <= '0';
elsif (ar_active_set = '1') then
ar_active <= '1';
-- For code coverage closure, ensure priority encoding in if/else clause
-- to prevent checking ar_active_set in reset clause.
elsif (ar_active_clr = '1') then
ar_active <= '0';
else
ar_active <= ar_active;
end if;
end if;
end process REG_AR_ACT;
end generate GEN_AR_DUAL;
---------------------------------------------------------------------------
--
-- REG_BRST_CNT.
-- Read Burst Counter.
-- No need to decrement burst counter.
-- Able to load with fixed burst length value.
-- Replace usage of proc_common_v4_0_2 library with direct HDL.
--
-- Size of counter = C_BRST_CNT_SIZE
-- Max size of burst transfer = 256 data beats
--
---------------------------------------------------------------------------
REG_BRST_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (brst_cnt_rst = '1') then
brst_cnt <= (others => '0');
-- Load burst counter
elsif (brst_cnt_ld_en = '1') then
brst_cnt <= brst_cnt_ld;
-- Decrement ONLY (no increment functionality)
elsif (brst_cnt_dec = '1') then
brst_cnt (C_BRST_CNT_SIZE-1 downto 0) <=
std_logic_vector (unsigned (brst_cnt (C_BRST_CNT_SIZE-1 downto 0)) - 1);
end if;
end if;
end process REG_BRST_CNT;
---------------------------------------------------------------------------
brst_cnt_rst <= not (S_AXI_AResetn);
-- Determine burst count load value
-- Either load BRAM counter directly from AXI bus or from stored registered value.
-- Use mux signal for ARLEN
BRST_CNT_LD_PROCESS : process (curr_arlen)
variable brst_cnt_ld_int : integer := 0;
begin
brst_cnt_ld_int := to_integer (unsigned (curr_arlen (7 downto 0)));
brst_cnt_ld <= std_logic_vector (to_unsigned (brst_cnt_ld_int, 8));
end process BRST_CNT_LD_PROCESS;
----------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_BRST_MAX_W_NARROW
-- Purpose: Generate registered logic for brst_cnt_max when the
-- design instantiation supports narrow operations.
--
---------------------------------------------------------------------------
GEN_BRST_MAX_W_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
REG_BRST_MAX: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_cnt_ld_en = '1')
-- Added with single port (13.1 release)
or (end_brst_rd_clr = '1') then
brst_cnt_max <= '0';
-- Replace usage of brst_cnt in this logic.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
elsif (brst_zero = '1') and (ar_active = '1') and (pend_rd_op = '0') then
-- Hold off assertion of brst_cnt_max on narrow burst transfers
-- Must wait until narrow burst count = 0.
if (curr_narrow_burst = '1') then
if (narrow_bram_addr_inc = '1') then
brst_cnt_max <= '1';
end if;
else
brst_cnt_max <= '1';
end if;
else
brst_cnt_max <= brst_cnt_max;
end if;
end if;
end process REG_BRST_MAX;
end generate GEN_BRST_MAX_W_NARROW;
---------------------------------------------------------------------------
--
-- Generate: GEN_BRST_MAX_WO_NARROW
-- Purpose: Generate registered logic for brst_cnt_max when the
-- design instantiation does not support narrow operations.
--
---------------------------------------------------------------------------
GEN_BRST_MAX_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 0) generate
begin
REG_BRST_MAX: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_cnt_ld_en = '1') then
brst_cnt_max <= '0';
-- Replace usage of brst_cnt in this logic.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
elsif (brst_zero = '1') and (ar_active = '1') and (pend_rd_op = '0') then
-- When narrow operations are not supported in the core
-- configuration, no check for curr_narrow_burst on assertion.
brst_cnt_max <= '1';
else
brst_cnt_max <= brst_cnt_max;
end if;
end if;
end process REG_BRST_MAX;
end generate GEN_BRST_MAX_WO_NARROW;
---------------------------------------------------------------------------
REG_BRST_MAX_D1: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
brst_cnt_max_d1 <= '0';
else
brst_cnt_max_d1 <= brst_cnt_max;
end if;
end if;
end process REG_BRST_MAX_D1;
brst_cnt_max_re <= '1' when (brst_cnt_max = '1') and (brst_cnt_max_d1 = '0') else '0';
-- Set flag that end of burst is reached
-- Need to capture this condition as the burst
-- counter may get reloaded for a subsequent read burst
REG_END_BURST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- SM may assert clear flag early (in case of narrow bursts)
-- Wait until the end_brst_rd flag is asserted to clear the flag.
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(end_brst_rd_clr = '1' and end_brst_rd = '1') then
end_brst_rd <= '0';
elsif (brst_cnt_max_re = '1') then
end_brst_rd <= '1';
end if;
end if;
end process REG_END_BURST;
---------------------------------------------------------------------------
-- Create flag that indicates burst counter is reaching ZEROs (max of burst
-- length)
REG_BURST_ZERO: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
((brst_cnt_ld_en = '1') and (brst_cnt_ld /= C_BRST_CNT_ZERO)) then
brst_zero <= '0';
elsif (brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_ONE) then
brst_zero <= '1';
else
brst_zero <= brst_zero;
end if;
end if;
end process REG_BURST_ZERO;
---------------------------------------------------------------------------
-- Create additional flag that indicates burst counter is reaching ONEs
-- (near end of burst length). Used to disable back-to-back condition in SM.
REG_BURST_ONE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
((brst_cnt_ld_en = '1') and (brst_cnt_ld /= C_BRST_CNT_ONE)) or
((brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_ONE)) then
brst_one <= '0';
elsif ((brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_TWO)) or
((brst_cnt_ld_en = '1') and (brst_cnt_ld = C_BRST_CNT_ONE)) then
brst_one <= '1';
else
brst_one <= brst_one;
end if;
end if;
end process REG_BURST_ONE;
---------------------------------------------------------------------------
-- Register flags for read burst operation
REG_RD_BURST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- Clear axi_rd_burst flags when burst count gets to zeros (unless the burst
-- counter is getting subsequently loaded for the new burst operation)
--
-- Replace usage of brst_cnt in this logic.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_zero = '1' and brst_cnt_ld_en = '0') then
axi_rd_burst <= '0';
axi_rd_burst_two <= '0';
elsif (brst_cnt_ld_en = '1') then
if (curr_arlen /= AXI_ARLEN_ONE and curr_arlen /= AXI_ARLEN_TWO) then
axi_rd_burst <= '1';
else
axi_rd_burst <= '0';
end if;
if (curr_arlen = AXI_ARLEN_TWO) then
axi_rd_burst_two <= '1';
else
axi_rd_burst_two <= '0';
end if;
else
axi_rd_burst <= axi_rd_burst;
axi_rd_burst_two <= axi_rd_burst_two;
end if;
end if;
end process REG_RD_BURST;
---------------------------------------------------------------------------
-- Seeing issue with axi_rd_burst getting cleared too soon
-- on subsquent brst_cnt_ld_en early assertion and pend_rd_op is asserted.
-- Create flag for currently active read burst operation
-- Gets asserted when burst counter is loaded, but does not
-- get cleared until the RD_DATA_SM has completed the read
-- burst operation
REG_ACT_RD_BURST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or (act_rd_burst_clr = '1') then
act_rd_burst <= '0';
act_rd_burst_two <= '0';
elsif (act_rd_burst_set = '1') then
-- If not loading the burst counter for a B2B operation
-- Then act_rd_burst follows axi_rd_burst and
-- act_rd_burst_two follows axi_rd_burst_two.
-- Get registered value of axi_* signal.
if (brst_cnt_ld_en = '0') then
act_rd_burst <= axi_rd_burst;
act_rd_burst_two <= axi_rd_burst_two;
else
-- Otherwise, duplicate logic for axi_* signals if burst counter
-- is getting loaded.
-- For improved code coverage here
-- The act_rd_burst_set signal will never get asserted if the burst
-- size is less than two data beats. So, the conditional check
-- for (curr_arlen /= AXI_ARLEN_ONE) is never evaluated. Removed
-- from this if clause.
if (curr_arlen /= AXI_ARLEN_TWO) then
act_rd_burst <= '1';
else
act_rd_burst <= '0';
end if;
if (curr_arlen = AXI_ARLEN_TWO) then
act_rd_burst_two <= '1';
else
act_rd_burst_two <= '0';
end if;
-- Note: re-code this if/else clause.
end if;
else
act_rd_burst <= act_rd_burst;
act_rd_burst_two <= act_rd_burst_two;
end if;
end if;
end process REG_ACT_RD_BURST;
---------------------------------------------------------------------------
rd_adv_buf <= axi_rvalid_int and AXI_RREADY;
---------------------------------------------------------------------------
-- RD DATA State Machine
--
-- Description: Central processing unit for AXI write data
-- channel interface handling and AXI write data response
-- handshaking.
--
-- Outputs: Name Type
--
-- bram_en_int Registered
-- bram_addr_inc Not Registered
-- brst_cnt_dec Not Registered
-- rddata_mux_sel Registered
-- axi_rdata_en Not Registered
-- axi_rvalid_set Registered
--
--
-- RD_DATA_SM_CMB_PROCESS: Combinational process to determine next state.
-- RD_DATA_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
RD_DATA_SM_CMB_PROCESS: process ( bram_addr_ld_en,
rd_adv_buf,
ar_active,
axi_araddr_full,
rd_b2b_elgible_no_thr_check,
disable_b2b_brst,
curr_arlen,
axi_rd_burst,
axi_rd_burst_two,
act_rd_burst,
act_rd_burst_two,
end_brst_rd,
brst_zero,
brst_one,
axi_b2b_brst,
bram_en_int,
rddata_mux_sel,
end_brst_rd_clr,
no_ar_ack,
pend_rd_op,
axi_rlast_int,
rd_data_sm_cs )
begin
-- assign default values for state machine outputs
rd_data_sm_ns <= rd_data_sm_cs;
bram_en_cmb <= bram_en_int;
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
rd_skid_buf_ld_cmb <= '0';
rd_skid_buf_ld_imm <= '0';
rddata_mux_sel_cmb <= rddata_mux_sel;
-- Change axi_rdata_en generated from SM to be a combinatorial signal
-- Can't afford the latency when throttling on the AXI bus.
axi_rdata_en <= '0';
axi_rvalid_set_cmb <= '0';
end_brst_rd_clr_cmb <= end_brst_rd_clr;
no_ar_ack_cmb <= no_ar_ack;
pend_rd_op_cmb <= pend_rd_op;
act_rd_burst_set <= '0';
act_rd_burst_clr <= '0';
set_last_bram_addr <= '0';
alast_bram_addr <= '0';
axi_b2b_brst_cmb <= axi_b2b_brst;
disable_b2b_brst_cmb <= disable_b2b_brst;
ar_active_clr <= '0';
case rd_data_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Initiate BRAM read when address is available in controller
-- Indicated by load of BRAM address counter
-- Remove use of pend_rd_op signal.
-- Never asserted as we transition back to IDLE
-- Detected in code coverage
if (bram_addr_ld_en = '1') then
-- At start of new read, clear end burst signal
end_brst_rd_clr_cmb <= '0';
-- Initiate BRAM read transfer
bram_en_cmb <= '1';
-- Only count addresses & burst length for read
-- burst operations
-- If currently loading BRAM address counter
-- Must check curr_arlen (mux output from pipe or AXI bus)
-- to determine length of next operation.
-- If ARLEN = 1 data beat, then set last_bram_addr signal
-- Otherwise, increment BRAM address counter.
if (curr_arlen /= AXI_ARLEN_ONE) then
-- Start of new operation, update act_rd_burst and
-- act_rd_burst_two signals
act_rd_burst_set <= '1';
else
-- Set flag for last_bram_addr on transition
-- to SNG_ADDR on single operations.
set_last_bram_addr <= '1';
end if;
-- Go to single active read address state
rd_data_sm_ns <= SNG_ADDR;
end if;
------------------------- SNG_ADDR State --------------------------
when SNG_ADDR =>
-- Clear flag once pending read is recognized
-- Duplicate logic here in case combinatorial flag was getting
-- set as the SM transitioned into this state.
if (pend_rd_op = '1') then
pend_rd_op_cmb <= '0';
end if;
-- At start of new read, clear end burst signal
end_brst_rd_clr_cmb <= '0';
-- Reach this state on first BRAM address & enable assertion
-- For burst operation, create next BRAM address and keep enable
-- asserted
-- Note:
-- No ability to throttle yet as RVALID has not yet been
-- asserted on the AXI bus
-- Reset data mux select between skid buffer and BRAM
-- Ensure read data mux is set for BRAM data
rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM;
-- Assert RVALID on AXI when 1st data beat available
-- from BRAM
axi_rvalid_set_cmb <= '1';
-- Reach this state when BRAM address counter is loaded
-- Use axi_rd_burst and axi_rd_burst_two to indicate if
-- operation is a single data beat burst.
if (axi_rd_burst = '0') and (axi_rd_burst_two = '0') then
-- Proceed directly to get BRAM read data
rd_data_sm_ns <= LAST_ADDR;
-- End of active current read address
ar_active_clr <= '1';
-- Negate BRAM enable
bram_en_cmb <= '0';
-- Load read data skid buffer for BRAM capture
-- in next clock cycle
rd_skid_buf_ld_cmb <= '1';
-- Assert new flag to disable back-to-back bursts
-- due to throttling
disable_b2b_brst_cmb <= '1';
-- Set flag for pending operation if bram_addr_ld_en is asserted (BRAM
-- address is loaded) and we are waiting for the current read burst to complete.
if (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
end if;
-- Read burst
else
-- Increment BRAM address counter (2nd data beat)
bram_addr_inc <= '1';
-- Decrement BRAM burst counter (2nd data beat)
brst_cnt_dec <= '1';
-- Keep BRAM enable asserted
bram_en_cmb <= '1';
rd_data_sm_ns <= SEC_ADDR;
-- Load read data skid buffer for BRAM capture
-- in next clock cycle
rd_skid_buf_ld_cmb <= '1';
-- Start of new operation, update act_rd_burst and
-- act_rd_burst_two signals
act_rd_burst_set <= '1';
-- If new burst is 2 data beats
-- Then disable capability on back-to-back bursts
if (axi_rd_burst_two = '1') then
-- Assert new flag to disable back-to-back bursts
-- due to throttling
disable_b2b_brst_cmb <= '1';
else
-- Support back-to-back for all other burst lengths
disable_b2b_brst_cmb <= '0';
end if;
end if;
------------------------- SEC_ADDR State --------------------------
when SEC_ADDR =>
-- Reach this state when the 2nd incremented address of the burst
-- is presented to the BRAM.
-- Only reach this state when axi_rd_burst = '1',
-- an active read burst.
-- Note:
-- No ability to throttle yet as RVALID has not yet been
-- asserted on the AXI bus
-- Enable AXI read data register
axi_rdata_en <= '1';
-- Only in dual port mode can the address counter get loaded early
if C_SINGLE_PORT_BRAM = 0 then
-- If we see the next address get loaded into the BRAM counter
-- then set flag for pending operation
if (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
end if;
end if;
-- Check here for burst length of two data transfers
-- If so, then the SM will NOT hit the condition of a full
-- pipeline:
-- Operation A) 1st BRAM address data on AXI bus
-- Operation B) 2nd BRAm address data read from BRAM
-- Operation C) 3rd BRAM address presented to BRAM
--
-- Full pipeline condition is hit for any read burst
-- length greater than 2 data beats.
if (axi_rd_burst_two = '1') then
-- No increment of BRAM address
-- or decrement of burst counter
-- Burst counter should be = zero
rd_data_sm_ns <= LAST_ADDR;
-- End of active current read address
ar_active_clr <= '1';
-- Ensure read data mux is set for BRAM data
rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM;
-- Negate BRAM enable
bram_en_cmb <= '0';
-- Load read data skid buffer for BRAM capture
-- in next clock cycle.
-- This signal will negate in the next state
-- if the data is not accepted on the AXI bus.
-- So that no new data from BRAM is registered into the
-- read channel controller.
rd_skid_buf_ld_cmb <= '1';
else
-- Burst length will hit full pipeline condition
-- Increment BRAM address counter (3rd data beat)
bram_addr_inc <= '1';
-- Decrement BRAM burst counter (3rd data beat)
brst_cnt_dec <= '1';
-- Keep BRAM enable asserted
bram_en_cmb <= '1';
rd_data_sm_ns <= FULL_PIPE;
-- Assert almost last BRAM address flag
-- so that ARVALID logic output can remain registered
--
-- Replace usage of brst_cnt with signal, brst_one.
if (brst_one = '1') then
alast_bram_addr <= '1';
end if;
-- Load read data skid buffer for BRAM capture
-- in next clock cycle
rd_skid_buf_ld_cmb <= '1';
end if; -- ARLEN = "0000 0001"
------------------------- FULL_PIPE State -------------------------
when FULL_PIPE =>
-- Reach this state when all three data beats in the burst
-- are active
--
-- Operation A) 1st BRAM address data on AXI bus
-- Operation B) 2nd BRAM address data read from BRAM
-- Operation C) 3rd BRAM address presented to BRAM
-- Ensure read data mux is set for BRAM data
rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM;
-- With new pipelining capability BRAM address counter may be
-- loaded in this state. This only occurs on back-to-back
-- bursts (when enabled).
-- No flag set for pending operation.
-- Modify the if clause here to check for back-to-back burst operations
-- If we load the BRAM address in this state for a subsequent burst, then
-- this condition indicates a back-to-back burst and no need to assert
-- the pending read operation flag.
-- Seeing corner case when pend_rd_op needs to be asserted and cleared
-- in this state. If the BRAM address counter is loaded early, but
-- axi_rlast_set is delayed in getting asserted (all while in this state).
-- The signal, curr_narrow_burst can not get cleared.
-- Only in dual port mode can the address counter get loaded early
if C_SINGLE_PORT_BRAM = 0 then
-- Set flag for pending operation if bram_addr_ld_en is asserted (BRAM
-- address is loaded) and we are waiting for the current read burst to complete.
if (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
-- Clear flag once pending read is recognized and
-- earlier read data phase is complete.
elsif (pend_rd_op = '1') and (axi_rlast_int = '1') then
pend_rd_op_cmb <= '0';
end if;
end if;
-- Check AXI throttling condition
-- If AXI bus advances and accepts read data, SM can
-- proceed with next data beat of burst.
-- If not, then go to FULL_THROTTLE state to wait for
-- AXI_RREADY = '1'.
if (rd_adv_buf = '1') then
-- Assert AXI read data enable for BRAM capture
axi_rdata_en <= '1';
-- Load read data skid buffer for BRAM capture in next clock cycle
rd_skid_buf_ld_cmb <= '1';
-- Assert almost last BRAM address flag
-- so that ARVALID logic output can remain registered
--
-- Replace usage of brst_cnt with signal, brst_one.
if (brst_one = '1') then
alast_bram_addr <= '1';
end if;
-- Check burst counter for max
-- If max burst count is reached, no new addresses
-- presented to BRAM, advance to last capture data states.
--
-- For timing, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (brst_zero = '1') or (end_brst_rd = '1' and axi_b2b_brst = '0') then
-- Check for elgible pending read operation to support back-to-back performance.
-- If so, load BRAM address counter.
--
-- Replace rd_b2b_elgible signal check to remove path from
-- arlen_pipe through rd_b2b_elgible
-- (with data throttle check)
if (rd_b2b_elgible_no_thr_check = '1') then
rd_data_sm_ns <= FULL_PIPE;
-- Set flag to indicate back-to-back read burst
-- RVALID will not clear in this case and remain asserted
axi_b2b_brst_cmb <= '1';
-- Set flag to update active read burst or
-- read burst of two flag
act_rd_burst_set <= '1';
-- Otherwise, complete current transaction
else
-- No increment of BRAM address
-- or decrement of burst counter
-- Burst counter should be = zero
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
rd_data_sm_ns <= LAST_ADDR;
-- Negate BRAM enable
bram_en_cmb <= '0';
-- End of active current read address
ar_active_clr <= '1';
end if;
else
-- Remain in this state until burst count reaches zero
-- Increment BRAM address counter (Nth data beat)
bram_addr_inc <= '1';
-- Decrement BRAM burst counter (Nth data beat)
brst_cnt_dec <= '1';
-- Keep BRAM enable asserted
bram_en_cmb <= '1';
-- Skid buffer load will remain asserted
-- AXI read data register is asserted
end if;
else
-- Throttling condition detected
rd_data_sm_ns <= FULL_THROTTLE;
-- Ensure that AXI read data output register is disabled
-- due to throttle condition.
axi_rdata_en <= '0';
-- Skid buffer gets loaded from BRAM read data in next clock
-- cycle ONLY.
-- Only on transition to THROTTLE state does skid buffer get loaded.
-- Negate load of read data skid buffer for BRAM capture
-- in next clock cycle due to detection of Throttle condition
rd_skid_buf_ld_cmb <= '0';
-- BRAM address is NOT getting incremented
-- (same for burst counter)
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
-- If transitioning to throttle state
-- Then next register enable assertion of the AXI read data
-- output register needs to come from the skid buffer
-- Set read data mux select here for SKID_BUFFER data
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
-- Detect if at end of burst read as we transition to FULL_THROTTLE
-- If so, negate the BRAM enable even if prior to throttle condition
-- on AXI bus. Read skid buffer will hold last beat of data in burst.
--
-- For timing purposes, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (brst_zero = '1') or (end_brst_rd = '1') then
-- No back to back "non bubble" support when AXI master
-- is throttling on current burst.
-- Seperate signal throttle_last_data will be asserted outside SM.
-- End of burst read, negate BRAM enable
bram_en_cmb <= '0';
-- Assert new flag to disable back-to-back bursts
-- due to throttling
disable_b2b_brst_cmb <= '1';
-- Disable B2B capability if throttling detected when
-- burst count is equal to one.
--
-- For timing purposes, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_one, indicating the
-- brst_cnt to be one when decrement.
elsif (brst_one = '1') then
-- Assert new flag to disable back-to-back bursts
-- due to throttling
disable_b2b_brst_cmb <= '1';
-- Throttle, but not end of burst
else
bram_en_cmb <= '1';
end if;
end if; -- rd_adv_buf (RREADY throttle)
------------------------- FULL_THROTTLE State ---------------------
when FULL_THROTTLE =>
-- Reach this state when the AXI bus throttles on the AXI data
-- beat read from BRAM (when the read pipeline is fully active)
-- Flag disable_b2b_brst_cmb should be asserted as we transition
-- to this state. Flag is asserted near the end of a read burst
-- to prevent the back-to-back performance pipelining in the BRAM
-- address counter.
-- Detect if at end of burst read
-- If so, negate the BRAM enable even if prior to throttle condition
-- on AXI bus. Read skid buffer will hold last beat of data in burst.
--
-- For timing, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (brst_zero = '1') or (end_brst_rd = '1') then
bram_en_cmb <= '0';
end if;
-- Set new flag for pending operation if bram_addr_ld_en is asserted (BRAM
-- address is loaded) and we are waiting for the current read burst to complete.
if (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
-- Clear flag once pending read is recognized and
-- earlier read data phase is complete.
elsif (pend_rd_op = '1') and (axi_rlast_int = '1') then
pend_rd_op_cmb <= '0';
end if;
-- Wait for RREADY to be asserted w/ RVALID on AXI bus
if (rd_adv_buf = '1') then
-- Ensure read data mux is set for skid buffer data
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
-- Ensure that AXI read data output register is enabled
axi_rdata_en <= '1';
-- Must reload skid buffer here from BRAM data
-- so if needed can be presented to AXI bus on the following clock cycle
rd_skid_buf_ld_imm <= '1';
-- When detecting end of throttle condition
-- Check first if burst count is complete
-- Check burst counter for max
-- If max burst count is reached, no new addresses
-- presented to BRAM, advance to last capture data states.
--
-- For timing, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (brst_zero = '1') or (end_brst_rd = '1') then
-- No back-to-back performance when AXI master throttles
-- If we reach the end of the burst, proceed to LAST_ADDR state.
-- No increment of BRAM address
-- or decrement of burst counter
-- Burst counter should be = zero
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
rd_data_sm_ns <= LAST_ADDR;
-- Negate BRAM enable
bram_en_cmb <= '0';
-- End of active current read address
ar_active_clr <= '1';
-- Not end of current burst w/ throttle condition
else
-- Go back to FULL_PIPE
rd_data_sm_ns <= FULL_PIPE;
-- Assert almost last BRAM address flag
-- so that ARVALID logic output can remain registered
--
-- For timing purposes, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_one, indicating the
-- brst_cnt to be one when decrement.
if (brst_one = '1') then
alast_bram_addr <= '1';
end if;
-- Increment BRAM address counter (Nth data beat)
bram_addr_inc <= '1';
-- Decrement BRAM burst counter (Nth data beat)
brst_cnt_dec <= '1';
-- Keep BRAM enable asserted
bram_en_cmb <= '1';
end if; -- Burst Max
else
-- Stay in this state
-- Ensure that AXI read data output register is disabled
-- due to throttle condition.
axi_rdata_en <= '0';
-- Ensure that skid buffer is not getting loaded with
-- current read data from BRAM
rd_skid_buf_ld_cmb <= '0';
-- BRAM address is NOT getting incremented
-- (same for burst counter)
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
end if; -- rd_adv_buf (RREADY throttle)
------------------------- LAST_ADDR State -------------------------
when LAST_ADDR =>
-- Reach this state in the clock cycle following the last address
-- presented to the BRAM. Capture the last BRAM data beat in the
-- next clock cycle.
--
-- Data is presented to AXI bus (if no throttling detected) and
-- loaded into the skid buffer.
-- If we reach this state after back to back burst transfers
-- then clear the flag to ensure that RVALID will clear when RLAST
-- is recognized
if (axi_b2b_brst = '1') then
axi_b2b_brst_cmb <= '0';
end if;
-- Clear flag that indicates end of read burst
-- Once we reach this state, we have recognized the burst complete.
--
-- It is getting asserted too early
-- and recognition of the end of the burst is missed when throttling
-- on the last two data beats in the read.
end_brst_rd_clr_cmb <= '1';
-- Set new flag for pending operation if ar_active is asserted (BRAM
-- address has already been loaded) and we are waiting for the current
-- read burst to complete. If those two conditions apply, set this flag.
-- For dual port, support checking for early writes into BRAM address counter
if (C_SINGLE_PORT_BRAM = 0) and ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then
-- Support back-to-backs for single AND dual port modes.
-- if ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then
-- if (ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
end if;
-- Load read data skid buffer for BRAM is asserted on transition
-- into this state. Only gets negated if done with operation
-- as detected in below if clause.
-- Check flag for no subsequent operations
-- Clear that now, with current operation completing
if (no_ar_ack = '1') then
no_ar_ack_cmb <= '0';
end if;
-- Check for single AXI read operations
-- If so, wait for RREADY to be asserted
-- Check for burst and bursts of two as seperate signals.
if (act_rd_burst = '0') and (act_rd_burst_two = '0') then
-- Create rvalid_set to only be asserted for a single clock
-- cycle.
-- Will get set as transitioning to LAST_ADDR on single read operations
-- Only assert RVALID here on single operations
-- Enable AXI read data register
axi_rdata_en <= '1';
-- Data will not yet be acknowledged on AXI
-- in this state.
-- Go to wait for last data beat
rd_data_sm_ns <= LAST_DATA;
-- Set read data mux select for SKID BUF
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
else
-- Only check throttling on AXI during read data burst operations
-- Check AXI throttling condition
-- If AXI bus advances and accepts read data, SM can
-- proceed with next data beat.
-- If not, then go to LAST_THROTTLE state to wait for
-- AXI_RREADY = '1'.
if (rd_adv_buf = '1') then
-- Assert AXI read data enable for BRAM capture
-- in next clock cycle
-- Enable AXI read data register
axi_rdata_en <= '1';
-- Ensure read data mux is set for BRAM data
rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM;
-- Burst counter already at zero. Reached this state due to NO
-- pending ARADDR in the read address pipeline. However, check
-- here for any new read addresses.
-- New ARADDR detected and loaded into BRAM address counter
-- Add check here for previously loaded BRAM address
-- ar_active will be asserted (and qualify that with the
-- condition that the read burst is complete, for narrow reads).
if (bram_addr_ld_en = '1') then
-- Initiate BRAM read transfer
bram_en_cmb <= '1';
-- Instead of transitioning to SNG_ADDR
-- go to wait for last data beat.
rd_data_sm_ns <= LAST_DATA_AR_PEND;
else
-- No pending read address to initiate next read burst
-- Go to capture last data beat from BRAM and present on AXI bus.
rd_data_sm_ns <= LAST_DATA;
end if; -- bram_addr_ld_en (New read burst)
else
-- Throttling condition detected
rd_data_sm_ns <= LAST_THROTTLE;
-- Ensure that AXI read data output register is disabled
-- due to throttle condition.
axi_rdata_en <= '0';
-- Skid buffer gets loaded from BRAM read data in next clock
-- cycle ONLY.
-- Only on transition to THROTTLE state does skid buffer get loaded.
-- Set read data mux select for SKID BUF
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
end if; -- rd_adv_buf (RREADY throttle)
end if; -- AXI read burst
------------------------- LAST_THROTTLE State ---------------------
when LAST_THROTTLE =>
-- Reach this state when the AXI bus throttles on the last data
-- beat read from BRAM
-- Data to be sourced from read skid buffer
-- Add check in LAST_THROTTLE as well as LAST_ADDR
-- as we may miss the setting of this flag for a subsequent operation.
-- For dual port, support checking for early writes into BRAM address counter
if (C_SINGLE_PORT_BRAM = 0) and ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then
-- Support back-to-back for single AND dual port modes.
-- if ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then
pend_rd_op_cmb <= '1';
end if;
-- Wait for RREADY to be asserted w/ RVALID on AXI bus
if (rd_adv_buf = '1') then
-- Assert AXI read data enable for BRAM capture
axi_rdata_en <= '1';
-- Set read data mux select for SKID BUF
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
-- No pending read address to initiate next read burst
-- Go to capture last data beat from BRAM and present on AXI bus.
rd_data_sm_ns <= LAST_DATA;
-- Load read data skid buffer for BRAM capture in next clock cycle
-- of last data read
-- Read Skid buffer already loaded with last data beat from BRAM
-- Does not need to be asserted again in this state
else
-- Stay in this state
-- Ensure that AXI read data output register is disabled
axi_rdata_en <= '0';
-- Ensure that skid buffer is not getting loaded with
-- current read data from BRAM
rd_skid_buf_ld_cmb <= '0';
-- BRAM address is NOT getting incremented
-- (same for burst counter)
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
-- Keep RVALID asserted on AXI
-- No need to assert RVALID again
end if; -- rd_adv_buf (RREADY throttle)
------------------------- LAST_DATA State -------------------------
when LAST_DATA =>
-- Reach this state when last BRAM data beat is
-- presented on AXI bus.
-- For a read burst, RLAST is not asserted until SM reaches
-- this state.
-- Ok to accept new operation if throttling detected
-- during current operation (and flag was previously set
-- to disable the back-to-back performance).
disable_b2b_brst_cmb <= '0';
-- Stay in this state until RREADY is asserted on AXI bus
-- Indicated by assertion of rd_adv_buf
if (rd_adv_buf = '1') then
-- Last data beat acknowledged on AXI bus
-- Check for new read burst or proceed back to IDLE
-- New ARADDR detected and loaded into BRAM address counter
-- Note: this condition may occur when C_SINGLE_PORT_BRAM = 0 or 1
if (bram_addr_ld_en = '1') or (pend_rd_op = '1') then
-- Clear flag once pending read is recognized
if (pend_rd_op = '1') then
pend_rd_op_cmb <= '0';
end if;
-- Initiate BRAM read transfer
bram_en_cmb <= '1';
-- Only count addresses & burst length for read
-- burst operations
-- Go to SNG_ADDR state
rd_data_sm_ns <= SNG_ADDR;
-- If current operation was a burst, clear the active
-- burst flag
if (act_rd_burst = '1') or (act_rd_burst_two = '1') then
act_rd_burst_clr <= '1';
end if;
-- If we are loading the BRAM, then we have to view the curr_arlen
-- signal to determine if the next operation is a single transfer.
-- Or if the BRAM address counter is already loaded (and we reach
-- this if clause due to pend_rd_op then the axi_* signals will indicate
-- if the next operation is a burst or not.
-- If the operation is a single transaction, then set the last_bram_addr
-- signal when we reach SNG_ADDR.
if (bram_addr_ld_en = '1') then
if (curr_arlen = AXI_ARLEN_ONE) then
-- Set flag for last_bram_addr on transition
-- to SNG_ADDR on single operations.
set_last_bram_addr <= '1';
end if;
elsif (pend_rd_op = '1') then
if (axi_rd_burst = '0' and axi_rd_burst_two = '0') then
set_last_bram_addr <= '1';
end if;
end if;
else
-- No pending read address to initiate next read burst.
-- Go to IDLE
rd_data_sm_ns <= IDLE;
-- If current operation was a burst, clear the active
-- burst flag
if (act_rd_burst = '1') or (act_rd_burst_two = '1') then
act_rd_burst_clr <= '1';
end if;
end if;
else
-- Throttling condition detected
-- Ensure that AXI read data output register is disabled
-- due to throttle condition.
axi_rdata_en <= '0';
-- If new ARADDR detected and loaded into BRAM address counter
if (bram_addr_ld_en = '1') then
-- Initiate BRAM read transfer
bram_en_cmb <= '1';
-- Only count addresses & burst length for read
-- burst operations
-- Instead of transitioning to SNG_ADDR
-- to wait for last data beat.
rd_data_sm_ns <= LAST_DATA_AR_PEND;
-- For singles, block any subsequent loads into BRAM address
-- counter from AR SM
no_ar_ack_cmb <= '1';
end if;
end if; -- rd_adv_buf (RREADY throttle)
------------------------ LAST_DATA_AR_PEND --------------------
when LAST_DATA_AR_PEND =>
-- Ok to accept new operation if throttling detected
-- during current operation (and flag was previously set
-- to disable the back-to-back performance).
disable_b2b_brst_cmb <= '0';
-- Reach this state when new BRAM address is loaded into
-- BRAM address counter
-- But waiting for last RREADY/RVALID/RLAST to be asserted
-- Once this occurs, continue with pending AR operation
if (rd_adv_buf = '1') then
-- Go to SNG_ADDR state
rd_data_sm_ns <= SNG_ADDR;
-- If current operation was a burst, clear the active
-- burst flag
if (act_rd_burst = '1') or (act_rd_burst_two = '1') then
act_rd_burst_clr <= '1';
end if;
-- In this state, the BRAM address counter is already loaded,
-- the axi_rd_burst and axi_rd_burst_two signals will indicate
-- if the next operation is a burst or not.
-- If the operation is a single transaction, then set the last_bram_addr
-- signal when we reach SNG_ADDR.
if (axi_rd_burst = '0' and axi_rd_burst_two = '0') then
set_last_bram_addr <= '1';
end if;
-- Code coverage tests are reporting that reaching this state
-- always when axi_rd_burst = '0' and axi_rd_burst_two = '0',
-- so no bursting operations.
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
rd_data_sm_ns <= IDLE;
--coverage on
end case;
end process RD_DATA_SM_CMB_PROCESS;
---------------------------------------------------------------------------
RD_DATA_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
rd_data_sm_cs <= IDLE;
bram_en_int <= '0';
rd_skid_buf_ld_reg <= '0';
rddata_mux_sel <= C_RDDATA_MUX_BRAM;
axi_rvalid_set <= '0';
end_brst_rd_clr <= '0';
no_ar_ack <= '0';
pend_rd_op <= '0';
axi_b2b_brst <= '0';
disable_b2b_brst <= '0';
else
rd_data_sm_cs <= rd_data_sm_ns;
bram_en_int <= bram_en_cmb;
rd_skid_buf_ld_reg <= rd_skid_buf_ld_cmb;
rddata_mux_sel <= rddata_mux_sel_cmb;
axi_rvalid_set <= axi_rvalid_set_cmb;
end_brst_rd_clr <= end_brst_rd_clr_cmb;
no_ar_ack <= no_ar_ack_cmb;
pend_rd_op <= pend_rd_op_cmb;
axi_b2b_brst <= axi_b2b_brst_cmb;
disable_b2b_brst <= disable_b2b_brst_cmb;
end if;
end if;
end process RD_DATA_SM_REG_PROCESS;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Create seperate registered process for last_bram_addr signal.
-- Only asserted for a single clock cycle
-- Gets set when the burst counter is loaded with 0's (for a single data beat operation)
-- (indicated by set_last_bram_addr from DATA SM)
-- or when the burst counter is decrement and the current value = 1
REG_LAST_BRAM_ADDR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
last_bram_addr <= '0';
-- The signal, set_last_bram_addr, is asserted when the DATA SM transitions to SNG_ADDR
-- on a single data beat burst. Can not use condition of loading burst counter
-- with the value of 0's (as the burst counter may be loaded during prior single operation
-- when waiting on last throttle/data beat, ie. rd_adv_buf not yet asserted).
elsif (set_last_bram_addr = '1') or
-- On burst operations at the last BRAM address presented to BRAM
(brst_cnt_dec = '1' and brst_cnt = C_BRST_CNT_ONE) then
last_bram_addr <= '1';
else
last_bram_addr <= '0';
end if;
end if;
end process REG_LAST_BRAM_ADDR;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- *** AXI Read Data Channel Interface ***
--
---------------------------------------------------------------------------
rd_skid_buf_ld <= rd_skid_buf_ld_reg or rd_skid_buf_ld_imm;
---------------------------------------------------------------------------
-- Generate: GEN_RDATA_NO_ECC
-- Purpose: Generation of AXI_RDATA output register without ECC
-- logic (C_ECC = 0 parameterization in design)
---------------------------------------------------------------------------
GEN_RDATA_NO_ECC: if C_ECC = 0 generate
signal axi_rdata_int : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
begin
---------------------------------------------------------------------------
-- AXI RdData Skid Buffer/Register
-- Sized according to size of AXI/BRAM data width
---------------------------------------------------------------------------
REG_RD_BUF: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
rd_skid_buf <= (others => '0');
-- Add immediate load of read skid buffer
-- Occurs in the case when at full throttle and RREADY/RVALID are asserted
elsif (rd_skid_buf_ld = '1') then
rd_skid_buf <= BRAM_RdData (C_AXI_DATA_WIDTH-1 downto 0);
else
rd_skid_buf <= rd_skid_buf;
end if;
end if;
end process REG_RD_BUF;
-- Rd Data Mux (selects between skid buffer and BRAM read data)
-- Select control signal from SM determines register load value
axi_rdata_mux <= BRAM_RdData (C_AXI_DATA_WIDTH-1 downto 0) when (rddata_mux_sel = C_RDDATA_MUX_BRAM) else
rd_skid_buf;
---------------------------------------------------------------------------
-- Generate: GEN_RDATA
-- Purpose: Generate each bit of AXI_RDATA.
---------------------------------------------------------------------------
GEN_RDATA: for i in C_AXI_DATA_WIDTH-1 downto 0 generate
begin
REG_RDATA: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- Clear output after last data beat accepted by requesting AXI master
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- Don't clear RDDATA when a back to back burst is occuring on RLAST & RVALID assertion
-- For improved code coverage, can remove the signal, axi_rvalid_int from this if clause.
-- It will always be asserted in this case.
(axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then
axi_rdata_int (i) <= '0';
elsif (axi_rdata_en = '1') then
axi_rdata_int (i) <= axi_rdata_mux (i);
else
axi_rdata_int (i) <= axi_rdata_int (i);
end if;
end if;
end process REG_RDATA;
end generate GEN_RDATA;
-- If C_ECC = 0, direct output assignment to AXI_RDATA
AXI_RDATA <= axi_rdata_int;
end generate GEN_RDATA_NO_ECC;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_RDATA_ECC
-- Purpose: Generation of AXI_RDATA output register when ECC
-- logic is enabled (C_ECC = 1 parameterization in design)
---------------------------------------------------------------------------
GEN_RDATA_ECC: if C_ECC = 1 generate
subtype syndrome_bits is std_logic_vector(0 to C_INT_ECC_WIDTH-1);
-- 0:6 for 32-bit ECC
-- 0:7 for 64-bit ECC
type correct_data_table_type is array (natural range 0 to C_AXI_DATA_WIDTH-1) of syndrome_bits;
signal rd_skid_buf_i : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi_rdata_int : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi_rdata_int_corr : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
begin
-- Remove GEN_RD_BUF that was doing bit reversal.
-- Replace with direct register assignments. Sized according to AXI data width.
REG_RD_BUF: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
rd_skid_buf_i <= (others => '0');
-- Add immediate load of read skid buffer
-- Occurs in the case when at full throttle and RREADY/RVALID are asserted
elsif (rd_skid_buf_ld = '1') then
rd_skid_buf_i (C_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1);
else
rd_skid_buf_i <= rd_skid_buf_i;
end if;
end if;
end process REG_RD_BUF;
-- Rd Data Mux (selects between skid buffer and BRAM read data)
-- Select control signal from SM determines register load value
-- axi_rdata_mux holds data + ECC bits.
-- Previous mux on input to checkbit_handler logic.
-- Removed now (mux inserted after checkbit_handler logic before register stage)
--
-- axi_rdata_mux <= BRAM_RdData (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) when (rddata_mux_sel = C_RDDATA_MUX_BRAM) else
-- rd_skid_buf_i;
-- Remove GEN_RDATA that was doing bit reversal.
REG_RDATA: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then
axi_rdata_int <= (others => '0');
elsif (axi_rdata_en = '1') then
-- Track uncorrected data vector with AXI RDATA output pipeline
-- Mimic mux logic here (from previous post checkbit XOR logic register)
if (rddata_mux_sel = C_RDDATA_MUX_BRAM) then
axi_rdata_int (C_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1);
else
axi_rdata_int <= rd_skid_buf_i;
end if;
else
axi_rdata_int <= axi_rdata_int;
end if;
end if;
end process REG_RDATA;
-- When C_ECC = 1, correct any single bit errors on output read data.
-- Post register stage to improve timing on ECC logic data path.
-- Use registers in AXI Interconnect IP core.
-- Perform bit swapping on output of correct_one_bit
-- module (axi_rdata_int_corr signal).
-- AXI_RDATA (i) <= axi_rdata_int (i) when (Enable_ECC = '0')
-- else axi_rdata_int_corr (C_AXI_DATA_WIDTH-1-i);
-- Found in HW debug
-- axi_rdata_int is reversed to be returned on AXI bus.
-- AXI_RDATA (i) <= axi_rdata_int (C_AXI_DATA_WIDTH-1-i) when (Enable_ECC = '0')
-- else axi_rdata_int_corr (C_AXI_DATA_WIDTH-1-i);
-- Remove bit reversal on AXI_RDATA output.
AXI_RDATA <= axi_rdata_int when (Enable_ECC = '0' or Sl_UE_i = '1') else axi_rdata_int_corr;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HAMMING_ECC_CORR
--
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
-- Generate statements to correct BRAM read data
-- dependent on ECC type.
------------------------------------------------------------------------
GEN_HAMMING_ECC_CORR: if C_ECC_TYPE = 0 generate
begin
------------------------------------------------------------------------
-- Generate: CHK_ECC_32
-- Purpose: Check ECC data unique for 32-bit BRAM.
------------------------------------------------------------------------
CHK_ECC_32: if C_AXI_DATA_WIDTH = 32 generate
constant correct_data_table_32 : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
signal syndrome_4_reg : std_logic_vector (0 to 1) := (others => '0'); -- Only used in 32-bit ECC
signal syndrome_6_reg : std_logic_vector (0 to 5) := (others => '0'); -- Specific for 32-bit ECC
begin
---------------------------------------------------------------------------
-- Register ECC syndrome value to correct any single bit errors
-- post-register on AXI read data.
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
syndrome_reg <= (others => '0');
syndrome_4_reg <= (others => '0');
syndrome_6_reg <= (others => '0');
-- Align register stage of syndrome with AXI read data pipeline
elsif (axi_rdata_en = '1') then
syndrome_reg <= Syndrome;
syndrome_4_reg <= Syndrome_4;
syndrome_6_reg <= Syndrome_6;
else
syndrome_reg <= syndrome_reg;
syndrome_4_reg <= syndrome_4_reg;
syndrome_6_reg <= syndrome_6_reg;
end if;
end if;
end process REG_SYNDROME;
---------------------------------------------------------------------------
-- Do last XOR on specific syndrome bits after pipeline stage before
-- correct_one_bit module.
syndrome_reg_i (0 to 3) <= syndrome_reg (0 to 3);
PARITY_CHK4: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2)
port map (
InA => syndrome_4_reg (0 to 1), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (4) ); -- [out std_logic]
syndrome_reg_i (5) <= syndrome_reg (5);
PARITY_CHK6: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_6_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (6) ); -- [out std_logic]
---------------------------------------------------------------------------
-- Generate: GEN_CORR_32
-- Purpose: Generate corrected read data based on syndrome value.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
GEN_CORR_32: for i in 0 to C_AXI_DATA_WIDTH-1 generate
begin
-----------------------------------------------------------------------
-- Instance: CORR_ONE_BIT_32
-- Description: Correct output read data based on syndrome vector.
-- A single error can be corrected by decoding the
-- syndrome value.
-- Input signal is declared (N:0).
-- Output signal is (N:0).
-- In order to reuse correct_one_bit module,
-- the single data bit correction is done LSB to MSB
-- in generate statement loop.
-----------------------------------------------------------------------
CORR_ONE_BIT_32: entity work.correct_one_bit
generic map (
C_USE_LUT6 => C_USE_LUT6,
Correct_Value => correct_data_table_32 (i))
port map (
DIn => axi_rdata_int (31-i), -- This is to match with LMB Controller Hamming Encoder logic (Bit Reversal)
Syndrome => syndrome_reg_i,
DCorr => axi_rdata_int_corr (31-i)); -- This is to match with LMB Controller Hamming Encoder logic (Bit Reversal)
end generate GEN_CORR_32;
end generate CHK_ECC_32;
------------------------------------------------------------------------
-- Generate: CHK_ECC_64
-- Purpose: Check ECC data unique for 64-bit BRAM.
------------------------------------------------------------------------
CHK_ECC_64: if C_AXI_DATA_WIDTH = 64 generate
constant correct_data_table_64 : correct_data_table_type := (
0 => "11000001", 1 => "10100001", 2 => "01100001", 3 => "11100001",
4 => "10010001", 5 => "01010001", 6 => "11010001", 7 => "00110001",
8 => "10110001", 9 => "01110001", 10 => "11110001", 11 => "10001001",
12 => "01001001", 13 => "11001001", 14 => "00101001", 15 => "10101001",
16 => "01101001", 17 => "11101001", 18 => "00011001", 19 => "10011001",
20 => "01011001", 21 => "11011001", 22 => "00111001", 23 => "10111001",
24 => "01111001", 25 => "11111001", 26 => "10000101", 27 => "01000101",
28 => "11000101", 29 => "00100101", 30 => "10100101", 31 => "01100101",
32 => "11100101", 33 => "00010101", 34 => "10010101", 35 => "01010101",
36 => "11010101", 37 => "00110101", 38 => "10110101", 39 => "01110101",
40 => "11110101", 41 => "00001101", 42 => "10001101", 43 => "01001101",
44 => "11001101", 45 => "00101101", 46 => "10101101", 47 => "01101101",
48 => "11101101", 49 => "00011101", 50 => "10011101", 51 => "01011101",
52 => "11011101", 53 => "00111101", 54 => "10111101", 55 => "01111101",
56 => "11111101", 57 => "10000011", 58 => "01000011", 59 => "11000011",
60 => "00100011", 61 => "10100011", 62 => "01100011", 63 => "11100011"
);
signal syndrome_7_reg : std_logic_vector (0 to 11) := (others => '0'); -- Specific for 64-bit ECC
signal syndrome_7_a : std_logic;
signal syndrome_7_b : std_logic;
begin
---------------------------------------------------------------------------
-- Register ECC syndrome value to correct any single bit errors
-- post-register on AXI read data.
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- Align register stage of syndrome with AXI read data pipeline
if (axi_rdata_en = '1') then
syndrome_reg <= Syndrome;
syndrome_7_reg <= Syndrome_7;
else
syndrome_reg <= syndrome_reg;
syndrome_7_reg <= syndrome_7_reg;
end if;
end if;
end process REG_SYNDROME;
---------------------------------------------------------------------------
-- Do last XOR on select syndrome bits after pipeline stage
-- before correct_one_bit_64 module.
PARITY_CHK7_A: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_7_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_7_a ); -- [out std_logic]
PARITY_CHK7_B: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_7_reg (6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_7_b ); -- [out std_logic]
-- Do last XOR on Syndrome MSB after pipeline stage before correct_one_bit module
-- PASSES: syndrome_reg_i (7) <= syndrome_reg (7) xor syndrome_7_b_reg;
syndrome_reg_i (7) <= syndrome_7_a xor syndrome_7_b;
syndrome_reg_i (0 to 6) <= syndrome_reg (0 to 6);
---------------------------------------------------------------------------
-- Generate: GEN_CORR_64
-- Purpose: Generate corrected read data based on syndrome value.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
GEN_CORR_64: for i in 0 to C_AXI_DATA_WIDTH-1 generate
begin
-----------------------------------------------------------------------
-- Instance: CORR_ONE_BIT_64
-- Description: Correct output read data based on syndrome vector.
-- A single error can be corrected by decoding the
-- syndrome value.
-----------------------------------------------------------------------
CORR_ONE_BIT_64: entity work.correct_one_bit_64
generic map (
C_USE_LUT6 => C_USE_LUT6,
Correct_Value => correct_data_table_64 (i))
port map (
DIn => axi_rdata_int (i),
Syndrome => syndrome_reg_i,
DCorr => axi_rdata_int_corr (i));
end generate GEN_CORR_64;
end generate CHK_ECC_64;
end generate GEN_HAMMING_ECC_CORR;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HSIAO_ECC_CORR
--
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
-- Derived from MIG v3.7 Hsiao HDL.
-- Generate statements to correct BRAM read data
-- dependent on ECC type.
------------------------------------------------------------------------
GEN_HSIAO_ECC_CORR: if C_ECC_TYPE = 1 generate
type type_int0 is array (C_AXI_DATA_WIDTH - 1 downto 0) of std_logic_vector (ECC_WIDTH - 1 downto 0);
signal h_matrix : type_int0;
signal flip_bits : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0);
signal ecc_rddata_r : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0);
begin
-- Reconstruct H-matrix
H_COL: for n in 0 to C_AXI_DATA_WIDTH - 1 generate
begin
H_BIT: for p in 0 to ECC_WIDTH - 1 generate
begin
h_matrix (n)(p) <= h_rows (p * CODE_WIDTH + n);
end generate H_BIT;
end generate H_COL;
-- Based on syndrome value, determine bits to flip in BRAM read data.
GEN_FLIP_BIT: for r in 0 to C_AXI_DATA_WIDTH - 1 generate
begin
flip_bits (r) <= BOOLEAN_TO_STD_LOGIC (h_matrix (r) = syndrome_r);
end generate GEN_FLIP_BIT;
ecc_rddata_r <= axi_rdata_int;
axi_rdata_int_corr (C_AXI_DATA_WIDTH-1 downto 0) <= -- UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1) xor
ecc_rddata_r (C_AXI_DATA_WIDTH-1 downto 0) xor
flip_bits (C_AXI_DATA_WIDTH-1 downto 0);
end generate GEN_HSIAO_ECC_CORR;
end generate GEN_RDATA_ECC;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_RID_SNG
-- Purpose: Generate RID output pipeline when the core is configured
-- in a single port mode.
---------------------------------------------------------------------------
GEN_RID_SNG: if (C_SINGLE_PORT_BRAM = 1) generate
begin
REG_RID_TEMP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rid_temp <= (others => '0');
elsif (bram_addr_ld_en = '1') then
axi_rid_temp <= AXI_ARID;
else
axi_rid_temp <= axi_rid_temp;
end if;
end if;
end process REG_RID_TEMP;
REG_RID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
axi_rid_int <= (others => '0');
elsif (bram_addr_ld_en = '1') then
axi_rid_int <= AXI_ARID;
elsif (axi_rvalid_set = '1') or (axi_b2b_rid_adv = '1') then
axi_rid_int <= axi_rid_temp;
else
axi_rid_int <= axi_rid_int;
end if;
end if;
end process REG_RID;
-- Advance RID pipeline values
axi_b2b_rid_adv <= '1' when (axi_rlast_int = '1' and
AXI_RREADY = '1' and
axi_b2b_brst = '1')
else '0';
end generate GEN_RID_SNG;
---------------------------------------------------------------------------
-- Generate: GEN_RID
-- Purpose: Generate RID in dual port mode (with read address pipeline).
---------------------------------------------------------------------------
GEN_RID: if (C_SINGLE_PORT_BRAM = 0) generate
begin
---------------------------------------------------------------------------
-- RID Output Register
--
-- Output RID value either comes from pipelined value or directly wrapped
-- ARID value. Determined by address pipeline usage.
---------------------------------------------------------------------------
-- Create intermediate temporary RID output register
REG_RID_TEMP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rid_temp <= (others => '0');
-- When BRAM address counter gets loaded
-- Set output RID value based on address source
elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '0') then
-- If BRAM address counter gets loaded directly from
-- AXI bus, then save ARID value for wrapping to RID
if (araddr_pipe_sel = '0') then
axi_rid_temp <= AXI_ARID;
else
-- Use pipelined AWID value
axi_rid_temp <= axi_arid_pipe;
end if;
-- Add condition to check for temp utilized (temp_full now = '0'), but a
-- pending RID is stored in temp2. Must advance the pipeline.
elsif ((axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and (axi_rid_temp2_full = '1')) or
(axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then
axi_rid_temp <= axi_rid_temp2;
else
axi_rid_temp <= axi_rid_temp;
end if;
end if;
end process REG_RID_TEMP;
-- Create flag that indicates if axi_rid_temp is full
REG_RID_TEMP_FULL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rid_temp_full = '1' and
(axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and
axi_rid_temp2_full = '0') then
axi_rid_temp_full <= '0';
elsif (bram_addr_ld_en = '1') or
((axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and (axi_rid_temp2_full = '1')) or
(axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then
axi_rid_temp_full <= '1';
else
axi_rid_temp_full <= axi_rid_temp_full;
end if;
end if;
end process REG_RID_TEMP_FULL;
-- Create flag to detect falling edge of axi_rid_temp_full flag
REG_RID_TEMP_FULL_D1: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rid_temp_full_d1 <= '0';
else
axi_rid_temp_full_d1 <= axi_rid_temp_full;
end if;
end if;
end process REG_RID_TEMP_FULL_D1;
axi_rid_temp_full_fe <= '1' when (axi_rid_temp_full = '0' and
axi_rid_temp_full_d1 = '1') else '0';
---------------------------------------------------------------------------
-- Create intermediate temporary RID output register
REG_RID_TEMP2: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rid_temp2 <= (others => '0');
-- When BRAM address counter gets loaded
-- Set output RID value based on address source
elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '1') then
-- If BRAM address counter gets loaded directly from
-- AXI bus, then save ARID value for wrapping to RID
if (araddr_pipe_sel = '0') then
axi_rid_temp2 <= AXI_ARID;
else
-- Use pipelined AWID value
axi_rid_temp2 <= axi_arid_pipe;
end if;
else
axi_rid_temp2 <= axi_rid_temp2;
end if;
end if;
end process REG_RID_TEMP2;
-- Create flag that indicates if axi_rid_temp2 is full
REG_RID_TEMP2_FULL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rid_temp2_full = '1' and (axi_rvalid_set = '1' or axi_b2b_rid_adv = '1')) or
(axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then
axi_rid_temp2_full <= '0';
elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '1') then
axi_rid_temp2_full <= '1';
else
axi_rid_temp2_full <= axi_rid_temp2_full;
end if;
end if;
end process REG_RID_TEMP2_FULL;
---------------------------------------------------------------------------
-- Output RID register is enabeld when RVALID is asserted on the AXI bus
-- Clear RID when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
REG_RID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- For improved code coverage, can remove the signal, axi_rvalid_int from statement.
(axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then
axi_rid_int <= (others => '0');
-- Add back to back case to advance RID
elsif (axi_rvalid_set = '1') or (axi_b2b_rid_adv = '1') then
axi_rid_int <= axi_rid_temp;
else
axi_rid_int <= axi_rid_int;
end if;
end if;
end process REG_RID;
-- Advance RID pipeline values
axi_b2b_rid_adv <= '1' when (axi_rlast_int = '1' and
AXI_RREADY = '1' and
axi_b2b_brst = '1')
else '0';
end generate GEN_RID;
---------------------------------------------------------------------------
-- Generate: GEN_RRESP
-- Purpose: Create register output unique when ECC is disabled.
-- Only possible output value = OKAY response.
---------------------------------------------------------------------------
GEN_RRESP: if C_ECC = 0 generate
begin
-----------------------------------------------------------------------
-- AXI_RRESP Output Register
--
-- Set when RVALID is asserted on AXI bus.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking
-- sequence and recognized by AXI requesting master.
-----------------------------------------------------------------------
REG_RRESP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- For improved code coverage, remove signal, axi_rvalid_int, it will always be asserted.
(axi_rlast_int = '1' and AXI_RREADY = '1') then
axi_rresp_int <= (others => '0');
elsif (axi_rvalid_set = '1') then
-- AXI BRAM only supports OK response for normal operations
-- Exclusive operations not yet supported
axi_rresp_int <= RESP_OKAY;
else
axi_rresp_int <= axi_rresp_int;
end if;
end if;
end process REG_RRESP;
end generate GEN_RRESP;
---------------------------------------------------------------------------
-- Generate: GEN_RRESP_ECC
-- Purpose: Create register output unique when ECC is disabled.
-- Only possible output value = OKAY response.
---------------------------------------------------------------------------
GEN_RRESP_ECC: if C_ECC = 1 generate
begin
-----------------------------------------------------------------------
-- AXI_RRESP Output Register
--
-- Set when RVALID is asserted on AXI bus.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking
-- sequence and recognized by AXI requesting master.
-----------------------------------------------------------------------
REG_RRESP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- For improved code coverage, remove signal, axi_rvalid_int, it will always be asserted.
(axi_rlast_int = '1' and AXI_RREADY = '1') then
axi_rresp_int <= (others => '0');
elsif (axi_rvalid_set = '1') then
-- AXI BRAM only supports OK response for normal operations
-- Exclusive operations not yet supported
-- For ECC implementation
-- Check that an uncorrectable error has not occured.
-- If so, then respond with RESP_SLVERR on AXI.
-- Ok to use combinatorial signal here. The Sl_UE_i
-- flag is generated based on the registered syndrome value.
-- if (Sl_UE_i = '1') then
-- axi_rresp_int <= RESP_SLVERR;
-- else
axi_rresp_int <= RESP_OKAY;
-- end if;
else
axi_rresp_int <= axi_rresp_int;
end if;
end if;
end process REG_RRESP;
end generate GEN_RRESP_ECC;
---------------------------------------------------------------------------
-- AXI_RVALID Output Register
--
-- Set AXI_RVALID when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RVALID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- Clear AXI_RVALID at the end of tranfer when able to clear
-- (axi_rlast_int = '1' and axi_rvalid_int = '1' and AXI_RREADY = '1' and
-- For improved code coverage, remove signal axi_rvalid_int.
(axi_rlast_int = '1' and AXI_RREADY = '1' and
-- Added axi_rvalid_clr_ok to check if during a back-to-back burst
-- and the back-to-back is elgible for streaming performance
axi_rvalid_clr_ok = '1') then
axi_rvalid_int <= '0';
elsif (axi_rvalid_set = '1') then
axi_rvalid_int <= '1';
else
axi_rvalid_int <= axi_rvalid_int;
end if;
end if;
end process REG_RVALID;
-- Create flag that gets set when we load BRAM address early in a B2B scenario
-- This will prevent the RVALID from getting cleared at the end of the current burst
-- Otherwise, the RVALID gets cleared after RLAST/RREADY dual assertion
REG_RVALID_CLR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rvalid_clr_ok <= '0';
-- When the new address loaded into the BRAM counter is for a back-to-back operation
-- Do not clear the RVALID
elsif (rd_b2b_elgible = '1' and bram_addr_ld_en = '1') then
axi_rvalid_clr_ok <= '0';
-- Else when we start a new transaction (that is not back-to-back)
-- Then enable the RVALID to get cleared upon RLAST/RREADY
elsif (bram_addr_ld_en = '1') or
(axi_rvalid_clr_ok = '0' and
(disable_b2b_brst = '1' or disable_b2b_brst_cmb = '1') and
last_bram_addr = '1') or
-- Add check for current SM state
-- If LAST_ADDR state reached, no longer performing back-to-back
-- transfers and keeping data streaming on AXI bus.
(rd_data_sm_cs = LAST_ADDR) then
axi_rvalid_clr_ok <= '1';
else
axi_rvalid_clr_ok <= axi_rvalid_clr_ok;
end if;
end if;
end process REG_RVALID_CLR;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- AXI_RLAST Output Register
--
-- Set AXI_RLAST when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RLAST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- To improve code coverage, remove
-- use of axi_rvalid_int (it will always be asserted with RLAST).
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1' and axi_rlast_set = '0') then
axi_rlast_int <= '0';
elsif (axi_rlast_set = '1') then
axi_rlast_int <= '1';
else
axi_rlast_int <= axi_rlast_int;
end if;
end if;
end process REG_RLAST;
---------------------------------------------------------------------------
-- Generate complete flag
do_cmplt_burst_cmb <= '1' when (last_bram_addr = '1' and
axi_rd_burst = '1' and
axi_rd_burst_two = '0') else '0';
-- Register complete flags
REG_CMPLT_BURST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or (do_cmplt_burst_clr = '1') then
do_cmplt_burst <= '0';
elsif (do_cmplt_burst_cmb = '1') then
do_cmplt_burst <= '1';
else
do_cmplt_burst <= do_cmplt_burst;
end if;
end if;
end process REG_CMPLT_BURST;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- RLAST State Machine
--
-- Description: SM to generate axi_rlast_set signal.
-- Created based on IR # 555346 to track when RLAST needs
-- to be asserted for back to back transfers
-- Uses the indication when last BRAM address is presented
-- and then counts the handshaking cycles on the AXI bus
-- (RVALID and RREADY both asserted).
-- Uses rd_adv_buf to perform this operation.
--
-- Output: Name Type
-- axi_rlast_set Not Registered
-- do_cmplt_burst_clr Not Registered
--
--
-- RLAST_SM_CMB_PROCESS: Combinational process to determine next state.
-- RLAST_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
RLAST_SM_CMB_PROCESS: process (
do_cmplt_burst,
last_bram_addr,
rd_adv_buf,
act_rd_burst,
axi_rd_burst,
act_rd_burst_two,
axi_rd_burst_two,
axi_rlast_int,
rlast_sm_cs )
begin
-- assign default values for state machine outputs
rlast_sm_ns <= rlast_sm_cs;
axi_rlast_set <= '0';
do_cmplt_burst_clr <= '0';
case rlast_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- If last read address is presented to BRAM
if (last_bram_addr = '1') then
-- If the operation is a single read operation
if (axi_rd_burst = '0') and (axi_rd_burst_two = '0') then
-- Go to wait for last data beat
rlast_sm_ns <= W8_LAST_DATA;
-- Else the transaction is a burst
else
-- Throttle condition on 3rd to last data beat
if (rd_adv_buf = '0') then
-- If AXI read burst = 2 (only two data beats to capture)
if (axi_rd_burst_two = '1' or act_rd_burst_two = '1') then
rlast_sm_ns <= W8_THROTTLE_B2;
else
rlast_sm_ns <= W8_THROTTLE;
end if;
-- No throttle on 3rd to last data beat
else
-- Only back-to-back support when burst size is greater
-- than two data beats. We will never toggle on a burst > 2
-- when last_bram_addr is asserted (as this is no toggle
-- condition)
-- Go to wait for 2nd to last data beat
rlast_sm_ns <= W8_2ND_LAST_DATA;
do_cmplt_burst_clr <= '1';
end if;
end if;
end if;
------------------------- W8_THROTTLE State -----------------------
when W8_THROTTLE =>
if (rd_adv_buf = '1') then
-- Go to wait for 2nd to last data beat
rlast_sm_ns <= W8_2ND_LAST_DATA;
-- If do_cmplt_burst flag is set, then clear it
if (do_cmplt_burst = '1') then
do_cmplt_burst_clr <= '1';
end if;
end if;
---------------------- W8_2ND_LAST_DATA State ---------------------
when W8_2ND_LAST_DATA =>
if (rd_adv_buf = '1') then
-- Assert RLAST on AXI
axi_rlast_set <= '1';
rlast_sm_ns <= W8_LAST_DATA;
end if;
------------------------- W8_LAST_DATA State ----------------------
when W8_LAST_DATA =>
-- If pending single to complete, keep RLAST asserted
-- Added to only assert axi_rlast_set for a single clock cycle
-- when we enter this state and are here waiting for the
-- throttle on the AXI bus.
if (axi_rlast_int = '1') then
axi_rlast_set <= '0';
else
axi_rlast_set <= '1';
end if;
-- Wait for last data beat to transition back to IDLE
if (rd_adv_buf = '1') then
rlast_sm_ns <= IDLE;
end if;
-------------------------- W8_THROTTLE_B2 ------------------------
when W8_THROTTLE_B2 =>
-- Wait for last data beat to transition back to IDLE
-- and set RLAST
if (rd_adv_buf = '1') then
rlast_sm_ns <= IDLE;
axi_rlast_set <= '1';
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
rlast_sm_ns <= IDLE;
--coverage on
end case;
end process RLAST_SM_CMB_PROCESS;
---------------------------------------------------------------------------
RLAST_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
rlast_sm_cs <= IDLE;
else
rlast_sm_cs <= rlast_sm_ns;
end if;
end if;
end process RLAST_SM_REG_PROCESS;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** ECC Logic ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_ECC
-- Purpose: Generate BRAM ECC write data and check ECC on read operations.
-- Create signals to update ECC registers (lite_ecc_reg module interface).
--
---------------------------------------------------------------------------
GEN_ECC: if C_ECC = 1 generate
signal bram_din_a_i : std_logic_vector(0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) := (others => '0'); -- Set for port data width
signal CE_Q : std_logic := '0';
signal Sl_CE_i : std_logic := '0';
signal bram_en_int_d1 : std_logic := '0';
signal bram_en_int_d2 : std_logic := '0';
begin
-- Generate signal to advance BRAM read address pipeline to
-- capture address for ECC error conditions (in lite_ecc_reg module).
-- BRAM_Addr_En <= bram_addr_inc or narrow_bram_addr_inc_re or
-- ((bram_en_int or bram_en_int_reg) and not (axi_rd_burst) and not (axi_rd_burst_two));
BRAM_Addr_En <= bram_addr_inc or narrow_bram_addr_inc_re or rd_adv_buf or
((bram_en_int or bram_en_int_d1 or bram_en_int_d2) and not (axi_rd_burst) and not (axi_rd_burst_two));
-- Enable 2nd & 3rd pipeline stage for BRAM address storage with single read transfers.
BRAM_EN_REG: process(S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
bram_en_int_d1 <= bram_en_int;
bram_en_int_d2 <= bram_en_int_d1;
end if;
end process BRAM_EN_REG;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HAMMING_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
------------------------------------------------------------------------
GEN_HAMMING_ECC: if C_ECC_TYPE = 0 generate
begin
------------------------------------------------------------------------
-- Generate: GEN_ECC_32
-- Purpose: Check ECC data unique for 32-bit BRAM.
-- Add extra '0' at MSB of ECC vector for data2mem alignment
-- w/ 32-bit BRAM data widths.
-- ECC bits are in upper order bits.
------------------------------------------------------------------------
GEN_ECC_32: if C_AXI_DATA_WIDTH = 32 generate
signal bram_din_a_rev : std_logic_vector(31 downto 0) := (others => '0'); -- Specific to BRAM data width
signal bram_din_ecc_a_rev : std_logic_vector(6 downto 0) := (others => '0'); -- Specific to BRAM data width
begin
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_32
-- Description: Generate ECC bits for checking data read from BRAM.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
-- process (bram_din_a_i) begin
-- for k in 0 to 31 loop
-- bram_din_a_rev(k) <= bram_din_a_i(39-k);
-- end loop;
-- for k in 0 to 6 loop
-- bram_din_ecc_a_rev(0) <= bram_din_a_i(6-k);
-- end loop;
-- end process;
CHK_HANDLER_32: entity work.checkbit_handler
generic map (
C_ENCODE => false, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
-- In 32-bit BRAM use case: DataIn (8:39)
-- CheckIn (1:7)
DataIn => bram_din_a_i(C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH), -- [in std_logic_vector(0 to 31)]
CheckIn => bram_din_a_i(1 to C_INT_ECC_WIDTH), -- [in std_logic_vector(0 to 6)]
--DataIn => bram_din_a_rev, -- [in std_logic_vector(0 to 31)]
--CheckIn => bram_din_ecc_a_rev, -- [in std_logic_vector(0 to 6)]
CheckOut => open, -- [out std_logic_vector(0 to 6)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)]
Syndrome_4 => Syndrome_4, -- [out std_logic_vector(0 to 1)]
Syndrome_6 => Syndrome_6, -- [out std_logic_vector(0 to 5)]
Syndrome_Chk => syndrome_reg_i, -- [out std_logic_vector(0 to 6)]
Enable_ECC => Enable_ECC, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i ); -- [out std_logic]
-- GEN_CORR_32 generate & correct_one_bit instantiation moved to generate
-- of AXI RDATA output register logic.
end generate GEN_ECC_32;
------------------------------------------------------------------------
-- Generate: GEN_ECC_64
-- Purpose: Check ECC data unique for 64-bit BRAM.
-- No extra '0' at MSB of ECC vector for data2mem alignment
-- w/ 64-bit BRAM data widths.
-- ECC bits are in upper order bits.
------------------------------------------------------------------------
GEN_ECC_64: if C_AXI_DATA_WIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_64
-- Description: Generate ECC bits for checking data read from BRAM.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
CHK_HANDLER_64: entity work.checkbit_handler_64
generic map (
C_ENCODE => false, -- [boolean]
C_REG => false, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
Clk => S_AXI_AClk, -- [in std_logic]
-- In 64-bit BRAM use case: DataIn (8:71)
-- CheckIn (0:7)
DataIn => bram_din_a_i (C_INT_ECC_WIDTH to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH-1), -- [in std_logic_vector(0 to 63)]
CheckIn => bram_din_a_i (0 to C_INT_ECC_WIDTH-1), -- [in std_logic_vector(0 to 7)]
CheckOut => open, -- [out std_logic_vector(0 to 7)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 7)]
Syndrome_7 => Syndrome_7,
Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 7)]
Enable_ECC => Enable_ECC, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i ); -- [out std_logic]
-- GEN_CORR_64 generate & correct_one_bit instantiation moved to generate
-- of AXI RDATA output register logic.
end generate GEN_ECC_64;
end generate GEN_HAMMING_ECC;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HSIAO_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
-- Derived from MIG v3.7 Hsiao HDL.
------------------------------------------------------------------------
GEN_HSIAO_ECC: if C_ECC_TYPE = 1 generate
constant ECC_WIDTH : integer := C_INT_ECC_WIDTH;
signal syndrome_ns : std_logic_vector (ECC_WIDTH - 1 downto 0) := (others => '0');
begin
-- Generate ECC check bits and syndrome values based on
-- BRAM read data.
-- Generate appropriate single or double bit error flags.
-- Instantiate ecc_gen_hsiao module, generated from MIG
I_ECC_GEN_HSIAO: entity work.ecc_gen
generic map (
code_width => CODE_WIDTH,
ecc_width => ECC_WIDTH,
data_width => C_AXI_DATA_WIDTH
)
port map (
-- Output
h_rows => h_rows (CODE_WIDTH * ECC_WIDTH - 1 downto 0)
);
GEN_RD_ECC: for m in 0 to ECC_WIDTH - 1 generate
begin
syndrome_ns (m) <= REDUCTION_XOR ( -- bram_din_a_i (0 to CODE_WIDTH-1)
BRAM_RdData (CODE_WIDTH-1 downto 0)
and h_rows ((m*CODE_WIDTH)+CODE_WIDTH-1 downto (m*CODE_WIDTH)));
end generate GEN_RD_ECC;
-- Insert register stage for syndrome.
-- Same as Hamming ECC code. Syndrome value is registered.
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
syndrome_r <= syndrome_ns;
end if;
end process REG_SYNDROME;
Sl_CE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
Sl_UE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and not(REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
end generate GEN_HSIAO_ECC;
-- Capture correctable/uncorrectable error from BRAM read
CORR_REG: process(S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (Enable_ECC = '1') and
(axi_rvalid_int = '1' and AXI_RREADY = '1') then -- Capture error flags
CE_Q <= Sl_CE_i;
UE_Q <= Sl_UE_i;
else
CE_Q <= '0';
UE_Q <= '0';
end if;
end if;
end process CORR_REG;
-- The signal, axi_rdata_en loads the syndrome_reg.
-- Use the AXI RVALID/READY signals to capture state of UE and CE.
-- Since flag generation uses the registered syndrome value.
-- ECC register block gets registered UE or CE conditions to update
-- ECC registers/interrupt/flag outputs.
Sl_CE <= CE_Q;
Sl_UE <= UE_Q;
-- CE_Failing_We <= Sl_CE_i and Enable_ECC and axi_rvalid_set;
CE_Failing_We <= CE_Q;
---------------------------------------------------------------------------
-- Generate BRAM read data vector assignment to always be from Port A
-- in a single port BRAM configuration.
-- Map BRAM_RdData (Port A) (N:0) to bram_din_a_i (0:N)
-- Including read back ECC bits.
--
-- Port A or Port B sourcing done at full_axi module level
---------------------------------------------------------------------------
-- Original design with mux (BRAM vs. Skid Buffer) on input side of checkbit_handler logic.
-- Move mux to enable on AXI RDATA register.
bram_din_a_i (0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0);
-- Map data vector from BRAM to use in correct_one_bit module with
-- register syndrome (post AXI RDATA register).
UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1) <= bram_din_a_i (C_ECC_WIDTH to C_ECC_WIDTH+C_AXI_DATA_WIDTH-1);
end generate GEN_ECC;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_NO_ECC
-- Purpose: Drive default output signals when ECC is diabled.
---------------------------------------------------------------------------
GEN_NO_ECC: if C_ECC = 0 generate
begin
BRAM_Addr_En <= '0';
CE_Failing_We <= '0';
Sl_CE <= '0';
Sl_UE <= '0';
end generate GEN_NO_ECC;
---------------------------------------------------------------------------
--
-- *** BRAM Interface Signals ***
--
---------------------------------------------------------------------------
BRAM_En <= bram_en_int;
---------------------------------------------------------------------------
-- BRAM Address Generate
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_L_BRAM_ADDR
-- Purpose: Generate zeros on lower order address bits adjustable
-- based on BRAM data width.
--
---------------------------------------------------------------------------
GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
BRAM_Addr (i) <= '0';
end generate GEN_L_BRAM_ADDR;
---------------------------------------------------------------------------
--
-- Generate: GEN_BRAM_ADDR
-- Purpose: Assign BRAM address output from address counter.
--
---------------------------------------------------------------------------
GEN_BRAM_ADDR: for i in C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
BRAM_Addr (i) <= bram_addr_int (i);
end generate GEN_BRAM_ADDR;
---------------------------------------------------------------------------
end architecture implementation;
|
--
-- This file is part of top_wireworld
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.my_package.all;
entity wireworld_cell is
generic (
init_state : state_type := t_copper
);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
neighbours : in STD_LOGIC_VECTOR (7 downto 0);
electron_head : out STD_LOGIC;
electron_queue : out STD_LOGIC);
end wireworld_cell;
architecture Behavioral of wireworld_cell is
signal state : state_type := init_state;
signal next_state : state_type;
begin
--state process
process(clk,reset)
begin
if reset = '1' then
state <= init_state;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;
--state transition
process(state,neighbours)
variable a : integer := 0;
begin
case state is
when t_copper => next_state <= t_electron_head ;
a:=0;
for index in 0 to 7 loop
if neighbours(index) = '1' then
a := a + 1;
else
a := a;
end if;
end loop;
if a = 1 or a = 2 then
next_state <= t_electron_head ;
else
next_state <= t_copper;
end if;
when t_electron_head => next_state <= t_electron_queue;
when t_electron_queue => next_state <= t_copper;
end case;
end process;
--output function
electron_head <= '1' when state = t_electron_head else '0';
electron_queue <= '1' when state = t_electron_queue else '0';
end Behavioral;
|
entity repro4 is
end;
architecture behav of repro4 is
begin
process
begin
"foo" (true, false);
end process;
end;
|
library verilog;
use verilog.vl_types.all;
entity View_output_vlg_vec_tst is
end View_output_vlg_vec_tst;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNZ5LMFB5D is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(0 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNZ5LMFB5D is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 32 + 1 ,
width_inr=> 0,
width_outl=> 1,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(31 downto 0) => input,
xin(32) => '0', yout => output
);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNZ5LMFB5D is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(0 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNZ5LMFB5D is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 32 + 1 ,
width_inr=> 0,
width_outl=> 1,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(31 downto 0) => input,
xin(32) => '0', yout => output
);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNZ5LMFB5D is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(0 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNZ5LMFB5D is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 32 + 1 ,
width_inr=> 0,
width_outl=> 1,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(31 downto 0) => input,
xin(32) => '0', yout => output
);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNZ5LMFB5D is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(0 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNZ5LMFB5D is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 32 + 1 ,
width_inr=> 0,
width_outl=> 1,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(31 downto 0) => input,
xin(32) => '0', yout => output
);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNZ5LMFB5D is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(0 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNZ5LMFB5D is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 32 + 1 ,
width_inr=> 0,
width_outl=> 1,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(31 downto 0) => input,
xin(32) => '0', yout => output
);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNZ5LMFB5D is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(0 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNZ5LMFB5D is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 32 + 1 ,
width_inr=> 0,
width_outl=> 1,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(31 downto 0) => input,
xin(32) => '0', yout => output
);
end architecture; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2659.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02659ent IS
END c13s03b01x00p02n01i02659ent;
ARCHITECTURE c13s03b01x00p02n01i02659arch OF c13s03b01x00p02n01i02659ent IS
BEGIN
TESTING: PROCESS
variable >k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02659 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02659arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2659.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02659ent IS
END c13s03b01x00p02n01i02659ent;
ARCHITECTURE c13s03b01x00p02n01i02659arch OF c13s03b01x00p02n01i02659ent IS
BEGIN
TESTING: PROCESS
variable >k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02659 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02659arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2659.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02659ent IS
END c13s03b01x00p02n01i02659ent;
ARCHITECTURE c13s03b01x00p02n01i02659arch OF c13s03b01x00p02n01i02659ent IS
BEGIN
TESTING: PROCESS
variable >k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02659 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02659arch;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based_control_part_pseudo is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
credit_out: out std_logic;
empty_out: out std_logic;
full_out: out std_logic;
read_pointer_in: out std_logic_vector(3 downto 0);
write_pointer_in: out std_logic_vector(3 downto 0);
read_en_out: out std_logic;
write_en_out: out std_logic
);
end FIFO_credit_based_control_part_pseudo;
architecture behavior of FIFO_credit_based_control_part_pseudo is
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
--process (clk, reset)begin
-- if reset = '0' then
-- read_pointer <= "0001";
-- write_pointer <= "0001";
-- FIFO_MEM_1 <= (others=>'0');
-- FIFO_MEM_2 <= (others=>'0');
-- FIFO_MEM_3 <= (others=>'0');
-- FIFO_MEM_4 <= (others=>'0');
-- credit_out <= '0';
-- elsif clk'event and clk = '1' then
-- write_pointer <= write_pointer_in;
-- read_pointer <= read_pointer_in;
-- credit_out <= '0';
-- if write_en = '1' then
-- --write into the memory
-- FIFO_MEM_1 <= FIFO_MEM_1_in;
-- FIFO_MEM_2 <= FIFO_MEM_2_in;
-- FIFO_MEM_3 <= FIFO_MEM_3_in;
-- FIFO_MEM_4 <= FIFO_MEM_4_in;
-- end if;
-- if read_en = '1' then
-- credit_out <= '1';
-- end if;
-- end if;
-- end process;
-- Since generating credit_out is part of the control part and the process with clk and reset is already
-- removed, I am not sure whether it is correct to create another separate process and check read_en in
-- it and based on that generate credit_out or not, something like the following:
process (read_en)
begin
credit_out <= '0';
if read_en = '1' then
credit_out <= '1';
else
credit_out <= '0';
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
read_en_out <= read_en;
write_en_out <= write_en;
full_out <= full;
process(write_en, write_pointer)begin
if write_en = '1'then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, valid_in) begin
if valid_in = '1' and full ='0' then
write_en <= '1';
else
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT gc_command_fifo_top IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(13-1 DOWNTO 0);
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(29-1 DOWNTO 0);
DOUT : OUT std_logic_vector(29-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
library IEEE;
use ieee.std_logic_1164.all;
entity four_to_one_mux_1_bit is
port(
a, b, c, d : in std_logic;
sel : in std_logic_vector(1 downto 0);
output : out std_logic
);
end entity four_to_one_mux_1_bit;
architecture behav of four_to_one_mux_1_bit is
begin
--output <= (a and (not sel(0)) and (not sel(1))) or (b and sel(0) and (not sel(1))) or (c and (not sel(0)) and sel(1)) or (d and sel(0) and sel(1));
output <= a when (sel = "00") else b when (sel = "01") else c when (sel = "10") else d when (sel = "11");
end behav; |
--************************************************************************************************
-- Arrbiter and Address/Data multiplexer for AVR core
-- Version 0.2
-- Designed by Ruslan Lepetenok
-- Modified 27.07.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.MemAccessCtrlPack.all;
entity ArbiterAndMux is port(
--Clock and reset
ireset : in std_logic;
cp2 : in std_logic;
-- Bus masters
busmin : in MastersOutBus_Type;
busmwait : out std_logic_vector(CNumOfBusMasters-1 downto 0);
-- Memory Address,Data and Control
ramadr : out std_logic_vector(15 downto 0);
ramdout : out std_logic_vector(7 downto 0);
ramre : out std_logic;
ramwe : out std_logic;
cpuwait : in std_logic
);
end ArbiterAndMux;
architecture RTL of ArbiterAndMux is
signal sel_mast : std_logic_vector(CNumOfBusMasters-1 downto 0);
signal sel_mast_rg : std_logic_vector(sel_mast'range);
constant c_zero_vect : std_logic_vector(CNumOfBusMasters-1 downto 0) := (others => '0');
begin
StoreBusMNum:process(ireset,cp2)
begin
if (ireset='0') then -- Reset
sel_mast_rg <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if(cpuwait='1') then -- Store selected bus master number
sel_mast_rg <= sel_mast;
end if;
end if;
end process;
-- Fixed priority arbitration
ArbitrationComb:process(busmin) -- Combinatorial
begin
sel_mast <= (others => '0');
for i in 0 to CNumOfBusMasters-1 loop
if(busmin(i).ramre='1' or busmin(i).ramwe='1') then
sel_mast(i) <= '1';
exit;
end if;
end loop;
end process;
MuxComb:process(busmin,sel_mast,sel_mast_rg,cpuwait) -- Combinatorial
begin
ramadr <= (others => '0');
ramdout <= (others => '0');
ramre <= '0';
ramwe <= '0';
for i in 0 to CNumOfBusMasters-1 loop
if(cpuwait='1') then
if(sel_mast_rg(i)='1') then
ramadr <= busmin(i).ramadr;
ramdout <= busmin(i).dout;
ramre <= busmin(i).ramre;
ramwe <= busmin(i).ramwe;
end if;
else -- cpuwait='0'
if(sel_mast(i)='1') then
ramadr <= busmin(i).ramadr;
ramdout <= busmin(i).dout;
ramre <= busmin(i).ramre;
ramwe <= busmin(i).ramwe;
end if;
end if;
end loop;
end process;
WaitGenComb:process(cpuwait,busmin,sel_mast) -- Combinatorial
begin
busmwait <= (others => '0');
if((busmin(busmwait'low).ramre='1' or busmin(busmwait'low).ramwe='1') and cpuwait='1') then
busmwait(busmwait'low) <= '1';
end if;
for i in 1 to CNumOfBusMasters-1 loop
if((busmin(i).ramre='1' or busmin(i).ramwe='1')and(sel_mast(i-1 downto 0)/=c_zero_vect(i-1 downto 0) or cpuwait='1')) then
busmwait(i) <= '1';
end if;
end loop;
end process;
-- For the purpose of test only
--ramdout(sel_mast'range) <= sel_mast;
-- For the purpose of test only
end RTL; |
--************************************************************************************************
-- Arrbiter and Address/Data multiplexer for AVR core
-- Version 0.2
-- Designed by Ruslan Lepetenok
-- Modified 27.07.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.MemAccessCtrlPack.all;
entity ArbiterAndMux is port(
--Clock and reset
ireset : in std_logic;
cp2 : in std_logic;
-- Bus masters
busmin : in MastersOutBus_Type;
busmwait : out std_logic_vector(CNumOfBusMasters-1 downto 0);
-- Memory Address,Data and Control
ramadr : out std_logic_vector(15 downto 0);
ramdout : out std_logic_vector(7 downto 0);
ramre : out std_logic;
ramwe : out std_logic;
cpuwait : in std_logic
);
end ArbiterAndMux;
architecture RTL of ArbiterAndMux is
signal sel_mast : std_logic_vector(CNumOfBusMasters-1 downto 0);
signal sel_mast_rg : std_logic_vector(sel_mast'range);
constant c_zero_vect : std_logic_vector(CNumOfBusMasters-1 downto 0) := (others => '0');
begin
StoreBusMNum:process(ireset,cp2)
begin
if (ireset='0') then -- Reset
sel_mast_rg <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if(cpuwait='1') then -- Store selected bus master number
sel_mast_rg <= sel_mast;
end if;
end if;
end process;
-- Fixed priority arbitration
ArbitrationComb:process(busmin) -- Combinatorial
begin
sel_mast <= (others => '0');
for i in 0 to CNumOfBusMasters-1 loop
if(busmin(i).ramre='1' or busmin(i).ramwe='1') then
sel_mast(i) <= '1';
exit;
end if;
end loop;
end process;
MuxComb:process(busmin,sel_mast,sel_mast_rg,cpuwait) -- Combinatorial
begin
ramadr <= (others => '0');
ramdout <= (others => '0');
ramre <= '0';
ramwe <= '0';
for i in 0 to CNumOfBusMasters-1 loop
if(cpuwait='1') then
if(sel_mast_rg(i)='1') then
ramadr <= busmin(i).ramadr;
ramdout <= busmin(i).dout;
ramre <= busmin(i).ramre;
ramwe <= busmin(i).ramwe;
end if;
else -- cpuwait='0'
if(sel_mast(i)='1') then
ramadr <= busmin(i).ramadr;
ramdout <= busmin(i).dout;
ramre <= busmin(i).ramre;
ramwe <= busmin(i).ramwe;
end if;
end if;
end loop;
end process;
WaitGenComb:process(cpuwait,busmin,sel_mast) -- Combinatorial
begin
busmwait <= (others => '0');
if((busmin(busmwait'low).ramre='1' or busmin(busmwait'low).ramwe='1') and cpuwait='1') then
busmwait(busmwait'low) <= '1';
end if;
for i in 1 to CNumOfBusMasters-1 loop
if((busmin(i).ramre='1' or busmin(i).ramwe='1')and(sel_mast(i-1 downto 0)/=c_zero_vect(i-1 downto 0) or cpuwait='1')) then
busmwait(i) <= '1';
end if;
end loop;
end process;
-- For the purpose of test only
--ramdout(sel_mast'range) <= sel_mast;
-- For the purpose of test only
end RTL; |
--************************************************************************************************
-- Arrbiter and Address/Data multiplexer for AVR core
-- Version 0.2
-- Designed by Ruslan Lepetenok
-- Modified 27.07.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.MemAccessCtrlPack.all;
entity ArbiterAndMux is port(
--Clock and reset
ireset : in std_logic;
cp2 : in std_logic;
-- Bus masters
busmin : in MastersOutBus_Type;
busmwait : out std_logic_vector(CNumOfBusMasters-1 downto 0);
-- Memory Address,Data and Control
ramadr : out std_logic_vector(15 downto 0);
ramdout : out std_logic_vector(7 downto 0);
ramre : out std_logic;
ramwe : out std_logic;
cpuwait : in std_logic
);
end ArbiterAndMux;
architecture RTL of ArbiterAndMux is
signal sel_mast : std_logic_vector(CNumOfBusMasters-1 downto 0);
signal sel_mast_rg : std_logic_vector(sel_mast'range);
constant c_zero_vect : std_logic_vector(CNumOfBusMasters-1 downto 0) := (others => '0');
begin
StoreBusMNum:process(ireset,cp2)
begin
if (ireset='0') then -- Reset
sel_mast_rg <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if(cpuwait='1') then -- Store selected bus master number
sel_mast_rg <= sel_mast;
end if;
end if;
end process;
-- Fixed priority arbitration
ArbitrationComb:process(busmin) -- Combinatorial
begin
sel_mast <= (others => '0');
for i in 0 to CNumOfBusMasters-1 loop
if(busmin(i).ramre='1' or busmin(i).ramwe='1') then
sel_mast(i) <= '1';
exit;
end if;
end loop;
end process;
MuxComb:process(busmin,sel_mast,sel_mast_rg,cpuwait) -- Combinatorial
begin
ramadr <= (others => '0');
ramdout <= (others => '0');
ramre <= '0';
ramwe <= '0';
for i in 0 to CNumOfBusMasters-1 loop
if(cpuwait='1') then
if(sel_mast_rg(i)='1') then
ramadr <= busmin(i).ramadr;
ramdout <= busmin(i).dout;
ramre <= busmin(i).ramre;
ramwe <= busmin(i).ramwe;
end if;
else -- cpuwait='0'
if(sel_mast(i)='1') then
ramadr <= busmin(i).ramadr;
ramdout <= busmin(i).dout;
ramre <= busmin(i).ramre;
ramwe <= busmin(i).ramwe;
end if;
end if;
end loop;
end process;
WaitGenComb:process(cpuwait,busmin,sel_mast) -- Combinatorial
begin
busmwait <= (others => '0');
if((busmin(busmwait'low).ramre='1' or busmin(busmwait'low).ramwe='1') and cpuwait='1') then
busmwait(busmwait'low) <= '1';
end if;
for i in 1 to CNumOfBusMasters-1 loop
if((busmin(i).ramre='1' or busmin(i).ramwe='1')and(sel_mast(i-1 downto 0)/=c_zero_vect(i-1 downto 0) or cpuwait='1')) then
busmwait(i) <= '1';
end if;
end loop;
end process;
-- For the purpose of test only
--ramdout(sel_mast'range) <= sel_mast;
-- For the purpose of test only
end RTL; |
--************************************************************************************************
-- Arrbiter and Address/Data multiplexer for AVR core
-- Version 0.2
-- Designed by Ruslan Lepetenok
-- Modified 27.07.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.MemAccessCtrlPack.all;
entity ArbiterAndMux is port(
--Clock and reset
ireset : in std_logic;
cp2 : in std_logic;
-- Bus masters
busmin : in MastersOutBus_Type;
busmwait : out std_logic_vector(CNumOfBusMasters-1 downto 0);
-- Memory Address,Data and Control
ramadr : out std_logic_vector(15 downto 0);
ramdout : out std_logic_vector(7 downto 0);
ramre : out std_logic;
ramwe : out std_logic;
cpuwait : in std_logic
);
end ArbiterAndMux;
architecture RTL of ArbiterAndMux is
signal sel_mast : std_logic_vector(CNumOfBusMasters-1 downto 0);
signal sel_mast_rg : std_logic_vector(sel_mast'range);
constant c_zero_vect : std_logic_vector(CNumOfBusMasters-1 downto 0) := (others => '0');
begin
StoreBusMNum:process(ireset,cp2)
begin
if (ireset='0') then -- Reset
sel_mast_rg <= (others => '0');
elsif (cp2='1' and cp2'event) then -- Clock
if(cpuwait='1') then -- Store selected bus master number
sel_mast_rg <= sel_mast;
end if;
end if;
end process;
-- Fixed priority arbitration
ArbitrationComb:process(busmin) -- Combinatorial
begin
sel_mast <= (others => '0');
for i in 0 to CNumOfBusMasters-1 loop
if(busmin(i).ramre='1' or busmin(i).ramwe='1') then
sel_mast(i) <= '1';
exit;
end if;
end loop;
end process;
MuxComb:process(busmin,sel_mast,sel_mast_rg,cpuwait) -- Combinatorial
begin
ramadr <= (others => '0');
ramdout <= (others => '0');
ramre <= '0';
ramwe <= '0';
for i in 0 to CNumOfBusMasters-1 loop
if(cpuwait='1') then
if(sel_mast_rg(i)='1') then
ramadr <= busmin(i).ramadr;
ramdout <= busmin(i).dout;
ramre <= busmin(i).ramre;
ramwe <= busmin(i).ramwe;
end if;
else -- cpuwait='0'
if(sel_mast(i)='1') then
ramadr <= busmin(i).ramadr;
ramdout <= busmin(i).dout;
ramre <= busmin(i).ramre;
ramwe <= busmin(i).ramwe;
end if;
end if;
end loop;
end process;
WaitGenComb:process(cpuwait,busmin,sel_mast) -- Combinatorial
begin
busmwait <= (others => '0');
if((busmin(busmwait'low).ramre='1' or busmin(busmwait'low).ramwe='1') and cpuwait='1') then
busmwait(busmwait'low) <= '1';
end if;
for i in 1 to CNumOfBusMasters-1 loop
if((busmin(i).ramre='1' or busmin(i).ramwe='1')and(sel_mast(i-1 downto 0)/=c_zero_vect(i-1 downto 0) or cpuwait='1')) then
busmwait(i) <= '1';
end if;
end loop;
end process;
-- For the purpose of test only
--ramdout(sel_mast'range) <= sel_mast;
-- For the purpose of test only
end RTL; |
-- $Id: sramif_mig_arty.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: sramif_mig_arty - syn
-- Description: SRAM to DDR via MIG for arty
--
-- Dependencies: bplib/mig/sramif2migui_core
-- cdclib/cdc_pulse
-- cdclib/cdc_value
-- migui_arty (generated core)
-- Test bench: tb_tst_sram_arty
-- Target Devices: arty board
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-01-02 1101 1.0 Initial version
-- 2018-11-17 1071 0.1 First draft
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.cdclib.all;
use work.miglib.all;
use work.miglib_arty.all;
entity sramif_mig_arty is -- SRAM to DDR via MIG for arty
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv20; -- address (32 bit word address)
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
CLKMIG : in slbit; -- sys clock for mig core
CLKREF : in slbit; -- ref clock for mig core
TEMP : in slv12; -- xadc die temp for mig core
MONI : out sramif2migui_moni_type;-- monitor signals
DDR3_DQ : inout slv16; -- dram: data in/out
DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR3_ADDR : out slv14; -- dram: address
DDR3_BA : out slv3; -- dram: bank address
DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR3_WE_N : out slbit; -- dram: write enable (act.low)
DDR3_RESET_N : out slbit; -- dram: reset (act.low)
DDR3_CK_P : out slv1; -- dram: clock (diff-p)
DDR3_CK_N : out slv1; -- dram: clock (diff-n)
DDR3_CKE : out slv1; -- dram: clock enable
DDR3_CS_N : out slv1; -- dram: chip select (act.low)
DDR3_DM : out slv2; -- dram: data input mask
DDR3_ODT : out slv1 -- dram: on-die termination
);
end sramif_mig_arty;
architecture syn of sramif_mig_arty is
signal MIG_BUSY : slbit := '0';
signal APP_RDY : slbit := '0';
signal APP_EN : slbit := '0';
signal APP_CMD : slv3 := (others=>'0');
signal APP_ADDR : slv(mig_mawidth-1 downto 0) := (others=>'0');
signal APP_WDF_RDY : slbit := '0';
signal APP_WDF_WREN : slbit := '0';
signal APP_WDF_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
signal APP_WDF_MASK : slv(mig_mwidth-1 downto 0) := (others=>'0');
signal APP_WDF_END : slbit := '0';
signal APP_RD_DATA_VALID : slbit := '0';
signal APP_RD_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
signal APP_RD_DATA_END : slbit := '0';
signal UI_CLK_SYNC_RST : slbit := '0';
signal INIT_CALIB_COMPLETE : slbit := '0';
signal SYS_RST : slbit := '0';
signal SYS_RST_BUSY : slbit := '0';
signal CLKMUI : slbit := '0';
signal TEMP_MUI : slv12 := (others=>'0'); -- xadc die temp; on CLKMUI
begin
SR2MIG: sramif2migui_core -- SRAM to MIG iface -----------------
generic map (
BAWIDTH => mig_bawidth,
MAWIDTH => mig_mawidth)
port map (
CLK => CLK,
RESET => RESET,
REQ => REQ,
WE => WE,
BUSY => MIG_BUSY,
ACK_R => ACK_R,
ACK_W => ACK_W,
ACT_R => ACT_R,
ACT_W => ACT_W,
ADDR => ADDR,
BE => BE,
DI => DI,
DO => DO,
MONI => MONI,
UI_CLK => CLKMUI,
UI_CLK_SYNC_RST => UI_CLK_SYNC_RST,
INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE,
APP_RDY => APP_RDY,
APP_EN => APP_EN,
APP_CMD => APP_CMD,
APP_ADDR => APP_ADDR,
APP_WDF_RDY => APP_WDF_RDY,
APP_WDF_WREN => APP_WDF_WREN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_END => APP_WDF_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END
);
CDC_SYSRST: cdc_pulse
generic map (
POUT_SINGLE => false,
BUSY_WACK => true)
port map (
CLKM => CLK,
RESET => '0',
CLKS => CLKMIG,
PIN => RESET,
BUSY => SYS_RST_BUSY,
POUT => SYS_RST
);
CDC_TEMP: cdc_value
generic map (
DWIDTH => TEMP'length)
port map (
CLKI => CLK,
CLKO => CLKMUI,
DI => TEMP,
DO => TEMP_MUI,
UPDT => open
);
MIG_CTL: migui_arty
port map (
DDR3_DQ => DDR3_DQ,
DDR3_DQS_P => DDR3_DQS_P,
DDR3_DQS_N => DDR3_DQS_N,
DDR3_ADDR => DDR3_ADDR,
DDR3_BA => DDR3_BA,
DDR3_RAS_N => DDR3_RAS_N,
DDR3_CAS_N => DDR3_CAS_N,
DDR3_WE_N => DDR3_WE_N,
DDR3_RESET_N => DDR3_RESET_N,
DDR3_CK_P => DDR3_CK_P,
DDR3_CK_N => DDR3_CK_N,
DDR3_CKE => DDR3_CKE,
DDR3_CS_N => DDR3_CS_N,
DDR3_DM => DDR3_DM,
DDR3_ODT => DDR3_ODT,
APP_ADDR => APP_ADDR,
APP_CMD => APP_CMD,
APP_EN => APP_EN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_END => APP_WDF_END,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_WREN => APP_WDF_WREN,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RDY => APP_RDY,
APP_WDF_RDY => APP_WDF_RDY,
APP_SR_REQ => '0',
APP_REF_REQ => '0',
APP_ZQ_REQ => '0',
APP_SR_ACTIVE => open,
APP_REF_ACK => open,
APP_ZQ_ACK => open,
UI_CLK => CLKMUI,
UI_CLK_SYNC_RST => UI_CLK_SYNC_RST,
INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE,
SYS_CLK_I => CLKMIG,
CLK_REF_I => CLKREF,
DEVICE_TEMP_I => TEMP_MUI,
SYS_RST => SYS_RST
);
BUSY <= MIG_BUSY or SYS_RST_BUSY;
end syn;
|
library verilog;
use verilog.vl_types.all;
entity generic_pll is
generic(
lpm_type : string := "generic_pll";
duty_cycle : integer := 50;
output_clock_frequency: string := "0 ps";
phase_shift : string := "0 ps";
reference_clock_frequency: string := "0 ps";
sim_additional_refclk_cycles_to_lock: integer := 0;
fractional_vco_multiplier: string := "false";
use_khz : integer := 1
);
port(
refclk : in vl_logic;
rst : in vl_logic;
fbclk : in vl_logic;
writerefclkdata : in vl_logic_vector(63 downto 0);
writeoutclkdata : in vl_logic_vector(63 downto 0);
writephaseshiftdata: in vl_logic_vector(63 downto 0);
writedutycycledata: in vl_logic_vector(63 downto 0);
outclk : out vl_logic;
locked : out vl_logic;
fboutclk : out vl_logic;
readrefclkdata : out vl_logic_vector(63 downto 0);
readoutclkdata : out vl_logic_vector(63 downto 0);
readphaseshiftdata: out vl_logic_vector(63 downto 0);
readdutycycledata: out vl_logic_vector(63 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of duty_cycle : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency : constant is 1;
attribute mti_svvh_generic_type of phase_shift : constant is 1;
attribute mti_svvh_generic_type of reference_clock_frequency : constant is 1;
attribute mti_svvh_generic_type of sim_additional_refclk_cycles_to_lock : constant is 1;
attribute mti_svvh_generic_type of fractional_vco_multiplier : constant is 1;
attribute mti_svvh_generic_type of use_khz : constant is 1;
end generic_pll;
|
library verilog;
use verilog.vl_types.all;
entity generic_pll is
generic(
lpm_type : string := "generic_pll";
duty_cycle : integer := 50;
output_clock_frequency: string := "0 ps";
phase_shift : string := "0 ps";
reference_clock_frequency: string := "0 ps";
sim_additional_refclk_cycles_to_lock: integer := 0;
fractional_vco_multiplier: string := "false";
use_khz : integer := 1
);
port(
refclk : in vl_logic;
rst : in vl_logic;
fbclk : in vl_logic;
writerefclkdata : in vl_logic_vector(63 downto 0);
writeoutclkdata : in vl_logic_vector(63 downto 0);
writephaseshiftdata: in vl_logic_vector(63 downto 0);
writedutycycledata: in vl_logic_vector(63 downto 0);
outclk : out vl_logic;
locked : out vl_logic;
fboutclk : out vl_logic;
readrefclkdata : out vl_logic_vector(63 downto 0);
readoutclkdata : out vl_logic_vector(63 downto 0);
readphaseshiftdata: out vl_logic_vector(63 downto 0);
readdutycycledata: out vl_logic_vector(63 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of duty_cycle : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency : constant is 1;
attribute mti_svvh_generic_type of phase_shift : constant is 1;
attribute mti_svvh_generic_type of reference_clock_frequency : constant is 1;
attribute mti_svvh_generic_type of sim_additional_refclk_cycles_to_lock : constant is 1;
attribute mti_svvh_generic_type of fractional_vco_multiplier : constant is 1;
attribute mti_svvh_generic_type of use_khz : constant is 1;
end generic_pll;
|
library verilog;
use verilog.vl_types.all;
entity generic_pll is
generic(
lpm_type : string := "generic_pll";
duty_cycle : integer := 50;
output_clock_frequency: string := "0 ps";
phase_shift : string := "0 ps";
reference_clock_frequency: string := "0 ps";
sim_additional_refclk_cycles_to_lock: integer := 0;
fractional_vco_multiplier: string := "false";
use_khz : integer := 1
);
port(
refclk : in vl_logic;
rst : in vl_logic;
fbclk : in vl_logic;
writerefclkdata : in vl_logic_vector(63 downto 0);
writeoutclkdata : in vl_logic_vector(63 downto 0);
writephaseshiftdata: in vl_logic_vector(63 downto 0);
writedutycycledata: in vl_logic_vector(63 downto 0);
outclk : out vl_logic;
locked : out vl_logic;
fboutclk : out vl_logic;
readrefclkdata : out vl_logic_vector(63 downto 0);
readoutclkdata : out vl_logic_vector(63 downto 0);
readphaseshiftdata: out vl_logic_vector(63 downto 0);
readdutycycledata: out vl_logic_vector(63 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of duty_cycle : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency : constant is 1;
attribute mti_svvh_generic_type of phase_shift : constant is 1;
attribute mti_svvh_generic_type of reference_clock_frequency : constant is 1;
attribute mti_svvh_generic_type of sim_additional_refclk_cycles_to_lock : constant is 1;
attribute mti_svvh_generic_type of fractional_vco_multiplier : constant is 1;
attribute mti_svvh_generic_type of use_khz : constant is 1;
end generic_pll;
|
library verilog;
use verilog.vl_types.all;
entity generic_pll is
generic(
lpm_type : string := "generic_pll";
duty_cycle : integer := 50;
output_clock_frequency: string := "0 ps";
phase_shift : string := "0 ps";
reference_clock_frequency: string := "0 ps";
sim_additional_refclk_cycles_to_lock: integer := 0;
fractional_vco_multiplier: string := "false";
use_khz : integer := 1
);
port(
refclk : in vl_logic;
rst : in vl_logic;
fbclk : in vl_logic;
writerefclkdata : in vl_logic_vector(63 downto 0);
writeoutclkdata : in vl_logic_vector(63 downto 0);
writephaseshiftdata: in vl_logic_vector(63 downto 0);
writedutycycledata: in vl_logic_vector(63 downto 0);
outclk : out vl_logic;
locked : out vl_logic;
fboutclk : out vl_logic;
readrefclkdata : out vl_logic_vector(63 downto 0);
readoutclkdata : out vl_logic_vector(63 downto 0);
readphaseshiftdata: out vl_logic_vector(63 downto 0);
readdutycycledata: out vl_logic_vector(63 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of duty_cycle : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency : constant is 1;
attribute mti_svvh_generic_type of phase_shift : constant is 1;
attribute mti_svvh_generic_type of reference_clock_frequency : constant is 1;
attribute mti_svvh_generic_type of sim_additional_refclk_cycles_to_lock : constant is 1;
attribute mti_svvh_generic_type of fractional_vco_multiplier : constant is 1;
attribute mti_svvh_generic_type of use_khz : constant is 1;
end generic_pll;
|
library verilog;
use verilog.vl_types.all;
entity generic_pll is
generic(
lpm_type : string := "generic_pll";
duty_cycle : integer := 50;
output_clock_frequency: string := "0 ps";
phase_shift : string := "0 ps";
reference_clock_frequency: string := "0 ps";
sim_additional_refclk_cycles_to_lock: integer := 0;
fractional_vco_multiplier: string := "false";
use_khz : integer := 1
);
port(
refclk : in vl_logic;
rst : in vl_logic;
fbclk : in vl_logic;
writerefclkdata : in vl_logic_vector(63 downto 0);
writeoutclkdata : in vl_logic_vector(63 downto 0);
writephaseshiftdata: in vl_logic_vector(63 downto 0);
writedutycycledata: in vl_logic_vector(63 downto 0);
outclk : out vl_logic;
locked : out vl_logic;
fboutclk : out vl_logic;
readrefclkdata : out vl_logic_vector(63 downto 0);
readoutclkdata : out vl_logic_vector(63 downto 0);
readphaseshiftdata: out vl_logic_vector(63 downto 0);
readdutycycledata: out vl_logic_vector(63 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of duty_cycle : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency : constant is 1;
attribute mti_svvh_generic_type of phase_shift : constant is 1;
attribute mti_svvh_generic_type of reference_clock_frequency : constant is 1;
attribute mti_svvh_generic_type of sim_additional_refclk_cycles_to_lock : constant is 1;
attribute mti_svvh_generic_type of fractional_vco_multiplier : constant is 1;
attribute mti_svvh_generic_type of use_khz : constant is 1;
end generic_pll;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity mem_read is
end entity mem_read;
architecture test of mem_read is
attribute trace : string;
subtype byte is bit_vector(7 downto 0);
type byte_vector is array (natural range <>) of byte;
type ram_bus is record
d : byte;
cmd, status, clk : bit;
end record ram_bus;
-- code from book
procedure mem_read ( address : in natural;
result : out byte_vector;
signal memory_bus : inout ram_bus ) is
attribute trace of address : constant is "integer/hex";
attribute trace of result : variable is "byte/multiple/hex";
attribute trace of memory_bus : signal is
"custom/command=rambus.cmd";
-- . . .
begin
-- . . .
-- not in book
report address'trace;
report result'trace;
report memory_bus'trace;
-- end not in book
end procedure mem_read;
-- end code from book
signal memory_bus : ram_bus;
begin
process is
variable address : natural;
variable result : byte_vector(0 to 3);
begin
mem_read ( address, result, memory_bus );
wait;
end process;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity mem_read is
end entity mem_read;
architecture test of mem_read is
attribute trace : string;
subtype byte is bit_vector(7 downto 0);
type byte_vector is array (natural range <>) of byte;
type ram_bus is record
d : byte;
cmd, status, clk : bit;
end record ram_bus;
-- code from book
procedure mem_read ( address : in natural;
result : out byte_vector;
signal memory_bus : inout ram_bus ) is
attribute trace of address : constant is "integer/hex";
attribute trace of result : variable is "byte/multiple/hex";
attribute trace of memory_bus : signal is
"custom/command=rambus.cmd";
-- . . .
begin
-- . . .
-- not in book
report address'trace;
report result'trace;
report memory_bus'trace;
-- end not in book
end procedure mem_read;
-- end code from book
signal memory_bus : ram_bus;
begin
process is
variable address : natural;
variable result : byte_vector(0 to 3);
begin
mem_read ( address, result, memory_bus );
wait;
end process;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity mem_read is
end entity mem_read;
architecture test of mem_read is
attribute trace : string;
subtype byte is bit_vector(7 downto 0);
type byte_vector is array (natural range <>) of byte;
type ram_bus is record
d : byte;
cmd, status, clk : bit;
end record ram_bus;
-- code from book
procedure mem_read ( address : in natural;
result : out byte_vector;
signal memory_bus : inout ram_bus ) is
attribute trace of address : constant is "integer/hex";
attribute trace of result : variable is "byte/multiple/hex";
attribute trace of memory_bus : signal is
"custom/command=rambus.cmd";
-- . . .
begin
-- . . .
-- not in book
report address'trace;
report result'trace;
report memory_bus'trace;
-- end not in book
end procedure mem_read;
-- end code from book
signal memory_bus : ram_bus;
begin
process is
variable address : natural;
variable result : byte_vector(0 to 3);
begin
mem_read ( address, result, memory_bus );
wait;
end process;
end architecture test;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_case_statement_GN4KF5KLTA is
generic ( number_outputs : integer := 5;
hasDefault : natural := 1;
pipeline : natural := 0;
width : integer := 3);
port(
clock : in std_logic;
aclr : in std_logic;
input : in std_logic_vector(2 downto 0);
r0 : out std_logic;
r1 : out std_logic;
r2 : out std_logic;
r3 : out std_logic;
r4 : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_case_statement_GN4KF5KLTA is
begin
caseproc:process( input )
begin
case input is
when "000" =>
r0 <= '1';
r1 <= '0';
r2 <= '0';
r3 <= '0';
r4 <= '0';
when "001" =>
r0 <= '0';
r1 <= '1';
r2 <= '0';
r3 <= '0';
r4 <= '0';
when "010" =>
r0 <= '0';
r1 <= '0';
r2 <= '1';
r3 <= '0';
r4 <= '0';
when "100" =>
r0 <= '0';
r1 <= '0';
r2 <= '0';
r3 <= '1';
r4 <= '0';
when others =>
r0 <= '0';
r1 <= '0';
r2 <= '0';
r3 <= '0';
r4 <= '1';
end case;
end process;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_case_statement_GN4KF5KLTA is
generic ( number_outputs : integer := 5;
hasDefault : natural := 1;
pipeline : natural := 0;
width : integer := 3);
port(
clock : in std_logic;
aclr : in std_logic;
input : in std_logic_vector(2 downto 0);
r0 : out std_logic;
r1 : out std_logic;
r2 : out std_logic;
r3 : out std_logic;
r4 : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_case_statement_GN4KF5KLTA is
begin
caseproc:process( input )
begin
case input is
when "000" =>
r0 <= '1';
r1 <= '0';
r2 <= '0';
r3 <= '0';
r4 <= '0';
when "001" =>
r0 <= '0';
r1 <= '1';
r2 <= '0';
r3 <= '0';
r4 <= '0';
when "010" =>
r0 <= '0';
r1 <= '0';
r2 <= '1';
r3 <= '0';
r4 <= '0';
when "100" =>
r0 <= '0';
r1 <= '0';
r2 <= '0';
r3 <= '1';
r4 <= '0';
when others =>
r0 <= '0';
r1 <= '0';
r2 <= '0';
r3 <= '0';
r4 <= '1';
end case;
end process;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_case_statement_GN4KF5KLTA is
generic ( number_outputs : integer := 5;
hasDefault : natural := 1;
pipeline : natural := 0;
width : integer := 3);
port(
clock : in std_logic;
aclr : in std_logic;
input : in std_logic_vector(2 downto 0);
r0 : out std_logic;
r1 : out std_logic;
r2 : out std_logic;
r3 : out std_logic;
r4 : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_case_statement_GN4KF5KLTA is
begin
caseproc:process( input )
begin
case input is
when "000" =>
r0 <= '1';
r1 <= '0';
r2 <= '0';
r3 <= '0';
r4 <= '0';
when "001" =>
r0 <= '0';
r1 <= '1';
r2 <= '0';
r3 <= '0';
r4 <= '0';
when "010" =>
r0 <= '0';
r1 <= '0';
r2 <= '1';
r3 <= '0';
r4 <= '0';
when "100" =>
r0 <= '0';
r1 <= '0';
r2 <= '0';
r3 <= '1';
r4 <= '0';
when others =>
r0 <= '0';
r1 <= '0';
r2 <= '0';
r3 <= '0';
r4 <= '1';
end case;
end process;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_case_statement_GN4KF5KLTA is
generic ( number_outputs : integer := 5;
hasDefault : natural := 1;
pipeline : natural := 0;
width : integer := 3);
port(
clock : in std_logic;
aclr : in std_logic;
input : in std_logic_vector(2 downto 0);
r0 : out std_logic;
r1 : out std_logic;
r2 : out std_logic;
r3 : out std_logic;
r4 : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_case_statement_GN4KF5KLTA is
begin
caseproc:process( input )
begin
case input is
when "000" =>
r0 <= '1';
r1 <= '0';
r2 <= '0';
r3 <= '0';
r4 <= '0';
when "001" =>
r0 <= '0';
r1 <= '1';
r2 <= '0';
r3 <= '0';
r4 <= '0';
when "010" =>
r0 <= '0';
r1 <= '0';
r2 <= '1';
r3 <= '0';
r4 <= '0';
when "100" =>
r0 <= '0';
r1 <= '0';
r2 <= '0';
r3 <= '1';
r4 <= '0';
when others =>
r0 <= '0';
r1 <= '0';
r2 <= '0';
r3 <= '0';
r4 <= '1';
end case;
end process;
end architecture;
|
------------------------------------------------------------------------------
-- Title : BPM RF channels swapping and de-swapping mode selector
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Select among distinct swapping and de-swapping modes affecting
-- how the swap master clock is propagated to the swap and de-swap
-- output signals.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.swap_pkg.all;
entity swmode_sel is
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic := '1';
-- Swap master clock
clk_swap_i : in std_logic;
-- Swap and de-swap signals
swap_o : out std_logic;
deswap_o : out std_logic;
-- Swap mode setting
swap_mode_i : in t_swap_mode
);
end swmode_sel;
architecture rtl of swmode_sel is
signal swap : std_logic;
signal deswap : std_logic;
begin
p_swap_mode : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
swap <= '0';
deswap <= '0';
else
if en_i = '1' then
case swap_mode_i is
when c_swmode_swap_deswap =>
if clk_swap_i = '1' then
swap <= '1';
deswap <= '1';
else
swap <= '0';
deswap <= '0';
end if;
when c_swmode_static_direct =>
swap <= '0';
deswap <= '0';
when c_swmode_static_inverted =>
swap <= '1';
deswap <= '0';
when c_swmode_rffe_swap =>
if clk_swap_i = '1' then
swap <= '1';
else
swap <= '0';
end if;
deswap <= '0';
when others =>
swap <= '0';
deswap <= '0';
end case;
end if;
end if;
end if;
end process p_swap_mode;
swap_o <= swap;
deswap_o <= deswap;
end rtl;
|
package pack is
type rec is record
a, b : integer;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
x : in integer;
y : out integer;
r : in rec );
end entity;
architecture test of sub is
begin
end architecture;
-------------------------------------------------------------------------------
entity elabr is
end entity;
use work.pack.all;
architecture test of elabr is
signal r1, r2 : rec;
begin
sub_i: entity work.sub
port map (
x => r1.a,
y => r1.b,
r => r2 );
end architecture;
|
package pack is
type rec is record
a, b : integer;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
x : in integer;
y : out integer;
r : in rec );
end entity;
architecture test of sub is
begin
end architecture;
-------------------------------------------------------------------------------
entity elabr is
end entity;
use work.pack.all;
architecture test of elabr is
signal r1, r2 : rec;
begin
sub_i: entity work.sub
port map (
x => r1.a,
y => r1.b,
r => r2 );
end architecture;
|
package pack is
type rec is record
a, b : integer;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
x : in integer;
y : out integer;
r : in rec );
end entity;
architecture test of sub is
begin
end architecture;
-------------------------------------------------------------------------------
entity elabr is
end entity;
use work.pack.all;
architecture test of elabr is
signal r1, r2 : rec;
begin
sub_i: entity work.sub
port map (
x => r1.a,
y => r1.b,
r => r2 );
end architecture;
|
package pack is
type rec is record
a, b : integer;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
x : in integer;
y : out integer;
r : in rec );
end entity;
architecture test of sub is
begin
end architecture;
-------------------------------------------------------------------------------
entity elabr is
end entity;
use work.pack.all;
architecture test of elabr is
signal r1, r2 : rec;
begin
sub_i: entity work.sub
port map (
x => r1.a,
y => r1.b,
r => r2 );
end architecture;
|
package pack is
type rec is record
a, b : integer;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
x : in integer;
y : out integer;
r : in rec );
end entity;
architecture test of sub is
begin
end architecture;
-------------------------------------------------------------------------------
entity elabr is
end entity;
use work.pack.all;
architecture test of elabr is
signal r1, r2 : rec;
begin
sub_i: entity work.sub
port map (
x => r1.a,
y => r1.b,
r => r2 );
end architecture;
|
-- Twofish_cbc_decryption_monte_carlo_testbench_192bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
--
-- description : this file is the testbench for the Decryption Monte Carlo KAT of the twofish cipher with 192 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity cbc_decryption_monte_carlo_testbench192 is
end cbc_decryption_monte_carlo_testbench192;
architecture cbc_decryption192_monte_carlo_testbench_arch of cbc_decryption_monte_carlo_testbench192 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched192
port (
odd_in_tk192,
even_in_tk192 : in std_logic_vector(7 downto 0);
in_key_tk192 : in std_logic_vector(191 downto 0);
out_key_up_tk192,
out_key_down_tk192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched192
port (
in_key_twk192 : in std_logic_vector(191 downto 0);
out_K0_twk192,
out_K1_twk192,
out_K2_twk192,
out_K3_twk192,
out_K4_twk192,
out_K5_twk192,
out_K6_twk192,
out_K7_twk192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_decryption_round192
port (
in1_tdr192,
in2_tdr192,
in3_tdr192,
in4_tdr192,
in_Sfirst_tdr192,
in_Ssecond_tdr192,
in_Sthird_tdr192,
in_key_up_tdr192,
in_key_down_tdr192 : in std_logic_vector(31 downto 0);
out1_tdr192,
out2_tdr192,
out3_tdr192,
out4_tdr192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S192
port (
in_key_ts192 : in std_logic_vector(191 downto 0);
out_Sfirst_ts192,
out_Ssecond_ts192,
out_Sthird_ts192 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_cbc_decryption_monte_carlo_testvalues_192bits.txt";
FILE output_file : text is out "twofish_cbc_decryption_monte_carlo_192bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 0 to 9999) return string is
variable our_text : string (1 to 4) := (others => ' ');
variable thousands,
hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := ((int_number mod 1000) - (int_number mod 100)) / 100;
thousands := (int_number - (int_number mod 1000)) / 1000;
our_text(1) := digit_to_char(thousands);
our_text(2) := digit_to_char(hundreds);
our_text(3) := digit_to_char(tens);
our_text(4) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal twofish_key : std_logic_vector(191 downto 0);
signal key_up,
key_down,
Sfirst,
Ssecond,
Sthird,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched192
port map (
in_key_twk192 => twofish_key,
out_K0_twk192 => K0,
out_K1_twk192 => K1,
out_K2_twk192 => K2,
out_K3_twk192 => K3,
out_K4_twk192 => K4,
out_K5_twk192 => K5,
out_K6_twk192 => K6,
out_K7_twk192 => K7
);
-- performing the input whitening XORs
from_xor0 <= K4 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K5 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K6 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K7 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched192
port map (
odd_in_tk192 => odd_number,
even_in_tk192 => even_number,
in_key_tk192 => twofish_key,
out_key_up_tk192 => key_up,
out_key_down_tk192 => key_down
);
producing_the_Skeys: twofish_S192
port map (
in_key_ts192 => twofish_key,
out_Sfirst_ts192 => Sfirst,
out_Ssecond_ts192 => Ssecond,
out_Sthird_ts192 => Sthird
);
the_decryption_circuit: twofish_decryption_round192
port map (
in1_tdr192 => to_round(127 downto 96),
in2_tdr192 => to_round(95 downto 64),
in3_tdr192 => to_round(63 downto 32),
in4_tdr192 => to_round(31 downto 0),
in_Sfirst_tdr192 => Sfirst,
in_Ssecond_tdr192 => Ssecond,
in_Sthird_tdr192 => Sthird,
in_key_up_tdr192 => key_up,
in_key_down_tdr192 => key_down,
out1_tdr192 => to_encr_reg128(127 downto 96),
out2_tdr192 => to_encr_reg128(95 downto 64),
out3_tdr192 => to_encr_reg128(63 downto 32),
out4_tdr192 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K0 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K1 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K2 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K3 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
cbc_dmc_proc: process
variable key_f, -- key input from file
pt_f, -- plaintext from file
ct_f,
iv_f : line; -- ciphertext from file
variable key_v : std_logic_vector(191 downto 0); -- key vector input
variable pt_v , -- plaintext vector
ct_v,
iv_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable counter_10000 : integer range 0 to 9999 := 0; -- counter for the 10.000 repeats in the 400 next ones
variable counter_400 : integer range 0 to 399 := 0; -- counter for the 400 repeats
variable round : integer range 0 to 16 := 0; -- holds the rounds
variable PT, CT, CV, CTj_1 : std_logic_vector(127 downto 0) := (others => '0');
begin
while not endfile(input_file) loop
readline(input_file, key_f);
readline(input_file, iv_f);
readline(input_file,ct_f);
readline(input_file, pt_f);
hread(key_f,key_v);
hread(iv_f, iv_v);
hread(ct_f,ct_v);
hread(pt_f,pt_v);
twofish_key <= key_v;
CV := iv_v;
CT := ct_v;
for counter_10000 in 0 to 9999 loop
input_data <= CT;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00100110"; -- 38
odd_number <= "00100111"; -- 39
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector((((15-round)*2)+8), 8);
odd_number <= conv_std_logic_vector((((15-round)*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
PT := output_data XOR CV;
CV := CT;
CT := PT;
assert false report "I=" & to_text(counter_400) & " R=" & to_text(counter_10000) severity note;
end loop; -- counter_10000
hwrite(key_f, key_v);
hwrite(iv_f, iv_v);
hwrite(ct_f, ct_v);
hwrite(pt_f, PT);
writeline(output_file,key_f);
writeline(output_file, iv_f);
writeline(output_file,ct_f);
writeline(output_file,pt_f);
assert (pt_v = PT) report "file entry and decryption result DO NOT match!!! :( " severity failure;
assert (pt_v /= PT) report "Decryption I=" & to_text(counter_400) &" OK" severity note;
counter_400 := counter_400 + 1;
end loop;
assert false report "***** CBC Decryption Monte Carlo Test with 192 bits key size ended succesfully! :) *****" severity failure;
end process cbc_dmc_proc;
end cbc_decryption192_monte_carlo_testbench_arch;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlconcat:2.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlconcat;
ENTITY base_zynq_design_xlconcat_0_0 IS
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END base_zynq_design_xlconcat_0_0;
ARCHITECTURE base_zynq_design_xlconcat_0_0_arch OF base_zynq_design_xlconcat_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF base_zynq_design_xlconcat_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlconcat IS
GENERIC (
IN0_WIDTH : INTEGER;
IN1_WIDTH : INTEGER;
IN2_WIDTH : INTEGER;
IN3_WIDTH : INTEGER;
IN4_WIDTH : INTEGER;
IN5_WIDTH : INTEGER;
IN6_WIDTH : INTEGER;
IN7_WIDTH : INTEGER;
IN8_WIDTH : INTEGER;
IN9_WIDTH : INTEGER;
IN10_WIDTH : INTEGER;
IN11_WIDTH : INTEGER;
IN12_WIDTH : INTEGER;
IN13_WIDTH : INTEGER;
IN14_WIDTH : INTEGER;
IN15_WIDTH : INTEGER;
IN16_WIDTH : INTEGER;
IN17_WIDTH : INTEGER;
IN18_WIDTH : INTEGER;
IN19_WIDTH : INTEGER;
IN20_WIDTH : INTEGER;
IN21_WIDTH : INTEGER;
IN22_WIDTH : INTEGER;
IN23_WIDTH : INTEGER;
IN24_WIDTH : INTEGER;
IN25_WIDTH : INTEGER;
IN26_WIDTH : INTEGER;
IN27_WIDTH : INTEGER;
IN28_WIDTH : INTEGER;
IN29_WIDTH : INTEGER;
IN30_WIDTH : INTEGER;
IN31_WIDTH : INTEGER;
dout_width : INTEGER;
NUM_PORTS : INTEGER
);
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In21 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In25 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In26 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In27 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In28 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In29 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In30 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT xlconcat;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF base_zynq_design_xlconcat_0_0_arch: ARCHITECTURE IS "xlconcat,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF base_zynq_design_xlconcat_0_0_arch : ARCHITECTURE IS "base_zynq_design_xlconcat_0_0,xlconcat,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF base_zynq_design_xlconcat_0_0_arch: ARCHITECTURE IS "base_zynq_design_xlconcat_0_0,xlconcat,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=1,NUM_PORTS=1}";
BEGIN
U0 : xlconcat
GENERIC MAP (
IN0_WIDTH => 1,
IN1_WIDTH => 1,
IN2_WIDTH => 1,
IN3_WIDTH => 1,
IN4_WIDTH => 1,
IN5_WIDTH => 1,
IN6_WIDTH => 1,
IN7_WIDTH => 1,
IN8_WIDTH => 1,
IN9_WIDTH => 1,
IN10_WIDTH => 1,
IN11_WIDTH => 1,
IN12_WIDTH => 1,
IN13_WIDTH => 1,
IN14_WIDTH => 1,
IN15_WIDTH => 1,
IN16_WIDTH => 1,
IN17_WIDTH => 1,
IN18_WIDTH => 1,
IN19_WIDTH => 1,
IN20_WIDTH => 1,
IN21_WIDTH => 1,
IN22_WIDTH => 1,
IN23_WIDTH => 1,
IN24_WIDTH => 1,
IN25_WIDTH => 1,
IN26_WIDTH => 1,
IN27_WIDTH => 1,
IN28_WIDTH => 1,
IN29_WIDTH => 1,
IN30_WIDTH => 1,
IN31_WIDTH => 1,
dout_width => 1,
NUM_PORTS => 1
)
PORT MAP (
In0 => In0,
In1 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In2 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
dout => dout
);
END base_zynq_design_xlconcat_0_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tbmem is
end entity tbmem;
architecture TB of tbmem is
begin
DM: process
type t_ram is array(natural range <>) of unsigned;
type p_ram is access t_ram;
variable myram : p_ram;
begin
myram := new t_ram(0 to 31)(15 downto 0);
for i in myram'range loop
myram(i) := TO_UNSIGNED(i, 16);
end loop;
for i in myram'range loop
report integer'image(i) & ": " & TO_HSTRING(myram(i));
end loop;
wait;
end process DM;
end architecture TB;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
QPQNKAwwGXIc5LIu1+x5sjRspWl6//PKSSN5Azf8YHFMDIjjv8ODKAuXr3jEMS+lxNABTG4Rd9GR
65uyZHZq2A==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
ZpxR4ePVP7HhmTvRZ2AkPGrDDKcRuHIh2c1NIs1zmLCHaq517O41+rLG0Z+GpHi+Ss8t721E3/8X
QHRGTbWv6QuGC2V+hB4pQ6jEeoELceJOnItkPA5q7LVuJLop4wEL0rkM9H1RClOhcxpMlCgEpW2t
HrUrnj3FMlYkupj5w0I=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FWGtQlcjFNAdnyZ9GtE+Dyse1Sf1HuK0i60ibMBrA0xxEIfZWI5WH7z75mbReTREt05bSeW1B/MN
OjkYE7uHORZctrnh8m27Sbh81lAnj0tuKP8h4zIA0EKiadPK1KmLhBPccy5oR1WU5X6Ld4M5JeeW
XYXcsb7BlitTUb8D1/YJaCSG5Kfb/50Ko8kcXqMq0mgUou3RBPUa8PDggsS9X36649anU//lR6kz
lzhDUB/i7YDs94rzLGNjABleUDLu32pmnbHEEQTgne1T7lWTr3CSbMXY7hjU7x3U+dhaAC3al6Q4
PtosbgsEZLZzvZFbYIfFhdoZtMcLOo3tP+JuIA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
AA09J5klOFLVWFXfV4ewC9s/7Z8Ll/fE8vDUO/AG49ivQLwO/YezzGgUT7p+f7j0Y05lTShIfZTa
wFlAIV1L9TVu4v9FwV58JXM0ANv33MEhJ/OGl9ZOtE2M2+GwAXfU2cr1y32vcwJs5oeWlOJK+7IA
wHtkHychCbsYxgQPAb4=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
IvTvodVXG5wKteER5MUFQmAZukGr06xST1bkTOkX7gXvpbqU4YlAJuB32fSsS8S9X98THsW8nfrW
ovUeP5uTAhDrabcE5ZNjbhEJYQ7lHPKhtUfSa1t2h5KhPB7mzfhNA0gVlDy4fKUqbudrCpTEBBhX
pxg9e/dNuFSPlrdgGJuNHABdO/XDJZ4sOfG24vEiQeio+MiVSFjrDzO4GjNFoX0dlrV2ppAr69lB
eOz1ta/drcK2lm1aVj7LjuNMhMNOECJY7HBX0aB/tI9jfZEiTvf4tQzFEO9rNkB5FkX6xRWg9fE7
xPh4TvNoWIORWmjfj/1kX8XqYJerx4iIBLkVOw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7472)
`protect data_block
SM9vZ4QWTF5fMFGjXMcS3Lc+42kpgKjSY/cFMEm2/9vhEMeaVtkareqTkivLYcPeN2Lms4bPsClx
JW+MnQsbTmbXa1d7l5XBRCMI02Dk6MzkuSaxPh0d3D9gu4WJKZ4PRSni/nKed1vq78km1MFUIYtF
NsGVYM9Fgkh0oFabc1q9klFEQDUo5QXKzqzt386mVFLKOqrn3p/qGTP1cFtOo7SkRgt1uMbI1QHc
05dIXeSrmMlB06jCmPwurLbSLK9HZd0RdVrWIWv1aZk1ojcqbpdsD0I6s4niSBfE4dvOge7y7eeL
i3d6eZp0VChtpVt0y+HiLMJDHSDdJdmiTCSKPhyqNACi0MPB6qzKGZWKzHUxwnnik4ptbqMxF0FA
1Dox2BXlCk6zzM5IlxoYkr+uE+hFFs1wrlSHBogyEAwVakncuZFPlRfLUtHVoY9QfPa03zUHgK+t
U+QDyPr37SyycE2IZnnX9GuclFOHgkzo0sDPA6V47tQ5rIIgoyoGQAbtHAoE9GvFL985fRTtZw6u
YE87fGowGWaAXinvEUccKF7ZqargHhfJ30N6q5Mx0dRRfw37/ixT2s4w9iw2fZj9g4d7t50XnuFB
xPoNQaQhewQdV2MS27SEY7av6DIuSOmpxZ9muiTCDObqPvsivbSrcv14Q62/EqkdJGMqCxnfUzED
XGJs+Lc30Z6lYU544uzm07X2S1QRbJfbTZZj9rCsuj2WuWEn+O+58AIBuQnTAHjnzM4GHipSZUh3
7SyiHwPXmdrMBiRUid42fjgtICZ3cPEqGh8cFGnc4CuekhP0jm2XjPVffMk5KyF4bIZWw4RYxXLK
LXp71EUnFZXDwaBOdWYaj3Zh/Kj5ShhC642BXk1+p6Yh6XrnKJMLEXRwmnqK15iMT4yI8B8SBE6R
y45NuDUc4RrzE5OYe1tt/kidYCls5LX3w3GV/htdJgkTFTgU2Wee90HBRjyLU+vBL3sEk1VW8viw
pbcl9jsEAzyZVFTd3SBMhCrmyFNNBY85zGPoYJUPt7qh3h3Rq9akuVIpYYbVrtT3BaUZ6HZ76ZP8
HT+z0evlbZgrt63jYV8LGGjLpcv9vVa38Y3b57DnIlu+zX3b42nhZPrhvfSuPQLcgpaSXX86cckU
QckLN0cvJjKBHt/1FJc15GbNwE8EW7NDkIOW2ylvpCuEDeGRv7tQ08x2lnB01kHIC7djFiFWyKwa
XSkKUeaZj1CnwLQiFEkk1j5l0mNHshdHqWoS3boqMESnvG3sc5+WaRhHGLkWZfAYejOGSm+oT1H2
W4+r/8v5sxJtX4K5pHGuMOZW8rMy7wJ31jFNxOOTUDNQMGNEAjVD9ZXqJdTBeAV1LturqSmY1F1k
vaywZfdlQyz4JUG+YTsgv0GMuSB1xBVKzHLzg/E4+3WgEf/ic9hr1apf84Uy+xLtGOwwCHwyt0Q6
D6CDEVUKqKVN5C1TtgsF2D0egXZdas8ONEzPJfd2KTX3rhajD6yK+7XXJ5HhW7twYrrDg3kI3RSx
JUHdY10L14Mnsgbc2gYeFfWlI4jz7uSDLkvBdI27tLefcFJZf8MrwPkJHs1ApU44IEWtedzr64Qf
FWW1zfkLNF7CN749Gjcet76WeyUdhJFjCJqL+hPknR231V3wf56RKxyhgSWUde3DPGAXlX0hHi3o
a9U9aeR/z2/bd57tZGnfpx5i3q03Pp/CXzqJKVReVSHaef8erSW/FPpPxFJzcqdnv6C4EZkaL7gx
ZJUtupBj63GwCRy0FG0B5WXrlS6yRgOSpCK53ZJXBZ5JN73vZIN+z0i9BZW5uNbMcu/hLpubqZPT
+dy7dhbDpVX+UaokJ70x5Q1gGfGyGpDiP6IcC7SSGOfk+Teqc+ggO++9hVZXLcziFDOJF6djm/+U
l7pii13M6YRaCDVDZ9YeK+YIk9KfpFokNCofzu2Pqkg8vmq/cbnhI/oBAptlEDKLVLHH0jcoZleK
0OGEiualhyV3/1Q9SWqjDLsrjQPX9HVLAoDW6scLp3Et8NT197imE1sYD1rY5bldXcg9Ij6uisuX
VSzqEYDhv209Pt/WrnWPPQOT63LMMN+m3bao1HEVxH3U8yaO5qdNidMhbOy8ZEYWtXBAwiVqfhy2
PvM++dLS7ebyHTaWejrCuJEQaSgrmOlFoQb1ExUnA3gMyocbt4tCpJKDwEYmEtndgDqW4KAlBrru
Oua6sLQxyPBXbUiXpw8CMgewl6hLuXPjXmve44re5mQFYOvk5GCETDOcQl7KWhLu/5S4AHuFIxXb
AnDBYw4wXTcMgsok5N+V8n4JDbuAbDbLlg0kxajkiiJMdjjjeNUGplbppSkq372yrxU7OYHJQpAY
FS+VpaOgKpb0XNUgJX1z2/RBZOcKNyrKafXOsO1Z0QGflx9jrdDUauR+ewDawyNQC038/LC6WuHM
pZsnI5Qk5TtV2IQqGk/sjEwNaI+wOcQV6pq1z155r8xkLqTPanBm+c32ZZpcfSX0STRvKwrX/5xL
GHi02L3i9Vsun8pCnY3/MM2QG8TzHDwSH+QeXIr5vtKS0oCt6QKOORxmfu9w6wQWh604+W63MmmN
Yi4+08XobTUDd7cOEq4y+qn4Z5/7ErbOweTH9fl84EUvPZ4yQF1Z29MPvob8uNf7mdZR4Azzta6W
By3AVVUTNmpgizi++E5XemoSWN59ShpWqodAYLIUVXm1NxXbtklhuwdcJTQty/8mlCj4pIleOslc
7/I7j8jGJMuk3UrElqXyrw3W8hu+y059xST26MiLzZJ4cdne+PZgjkmay0mKK25bbavNPio7FhlD
wj5DdCfIrL4IO87DvQWE0wcimRBHg2KFeeqdxREcIWNy8AVDxS1COrUDNuXffwwi+o1Qgi3ChZUu
Jt/kImbraUK/oiMSsWk2Tt+rWVjmIx/wzElfbW2Ni3BOqaT8Uwale1GjmsFF2AWpbfhGwOKSg98F
TxZ3HLvjUQZUuVNULdItSbYZ1osGPNOzm+I0869gAF2YOq5LFocKW+B4Nqlq9BBPuQ9MHR/k3JC9
J/c8r40HiEt3hYbJNQrk2LrCN5cyngz/dyVG6Qnt3cJp6LHhlOiw9Akb4uYvn4O3ng7m6c0qw+0r
SB1JheuRaa6fX6GyNhoWXHobd5RfFVraiHU7nb3CFBU4FdK7yscm7GmAloPPfZ9uwjmMB997JQfm
L33dn3uGCXPg+ORp49aPqZZMN9VNL4sYarvamHdNEKJJjb2KTCMqVrwZoy5IDNQNtuYfZXwzmnvB
rCiMx0D0Se/RzBMpQlt3GBK35izGmCT6vCWWh1myYbtTXueWCRZ1GwuMcxq9HrRoQDIJLssjQZZm
k3bQ3u9kGoBhFSsgD+O5lT74gg94vS/I8nFvvJfPpbSnXleVlKVnjzoIqgh+Loe4puX/kb+WHS95
I3K9W4JeHHKnV93J3ghPVW7o8w1XiPcyWT2bi2nkKSgQQKchcVAeYZ6GdHNE4NpHKpj9pdpPkK1d
Lch8872ZTvq9GMUEkrWN1/Xt/hTNvdik+fLb5Y1YRB2yQt1NcYMmSm6dYcl0iE5KL9zOjx471MUh
6uMYKbup1CZSfTNOAUx1ih1HZBmIhr+yu3Ys68Ko10ypj3RZnoXkvDsS/GUGrYzkF/f/uJG2zrvU
hzZD1oC6ZAbZRIbagfSBgbf7B2p5xeP/gzUqRxTnuXVFFLvE+4jGQrtplveO2tw3HXhGVbU7J4Jc
sxpquoVf6sr7xfkUPIz8jGBtMCWZTca4pgtQL+so/c0DtNvfLv52shOiExcy8Os6Nlx7fWZrIz9d
5jnMfqEG/tTwvZuKVHXnEVVR0ks+6EVkV5xY/o31KMmmeO7bNtuMGv+s/mb1r8sM8xihyTc6OblO
D2h7P3r6IlVEdYYPcHPKDLvE2DavFgL6D/W4PLiMNaFJ52sQElS9DwkJw99Cgxd5cPGZYfHREfjD
bhbrdk6maEh9/mLeNKWB1tMcHpnCoTECeF/ZGyVT7w6t6XWJh9CsdXzHpnyZ8YbFhNnMiLNq3olT
z9woc4+7VITdTD9UBOlPbi8W8bQQGRUcx411kOfka+arAhTZg3GKj/uQCC8ut8oVc4mfKDQkohsW
6MyCAOFF3ZLqnUsulnRy2uCIkBgykirpPhUdhcyxyUDAosJ1TApAA5bF7TaF6+MlT6aHozrc3+dV
Fh9F9/vHsQl0dMjxTzuBfXeqN/7urFW9bvHK3vVy15C8PRYsZKnPyKdIfwr1JVq2F+g5YQmnxzIv
xkGhxyIrjhj4WHp9cGmcBF96E7d1RlRVOmUAimhJxEJL98CaqoqUnZdvsHJLfZCLzZteAFGa8L2b
ahg9sBxp3wsYFltv32rnnMw/fwGlx20O1OB07/oQ0LArrVF+AeOL+oTfraQJBlHDSzvSukU0J+IZ
DKlBwBnSJ52h3L9IiY2V3vQ8KTOmDgH39xEzxBFW85m+x0RE/qrBzG60lPAg2VzQrpWWSTHPf0LC
gu6MlqGDYyW+o+wYNFZWfHvWQSEN0PZP1y3jqC0jX9NqIeE6gkhOPaHrzkQqZtIdQVM3auCrdDrC
BQqI0ns+o7L1kkPqZbC3icwVfD4gLm6L7e+P1gHan1hjlgNfcAA42JuOyINfvoYI3170EhFOcmg5
qug+u6ZFOhEUA9VY9lZoZRT5K6/kkcNYKU4ns4LsaMMfsiKHM79aiMwTfG0atGop2aVjy97naaA+
REBhGH7q7ZxuFfBg4DEbWZsTKY7jhEKdvRD2cpLZ9pU9y6pILHS0QEC1RASLu1fhH1NivcrZpKRQ
SBRrKIMhAVheofzkE6p4wp4j6qFzyghxnsifRcmutl6ct9OTC+UUwLvNWPKIcso0MjWF91NoiCve
oqjnBfN3vV0gep/beeRyQzA7K85kskb6vv6Z4Xwxh1oql35GrMfcD3416WAzg0xA0bHYheK5+IIz
qPrXUR/1P1qft3DZc4mOmw+EWjZ9I5otSLAYrd9q6Fzq0SYJTFUfX3OuIWu7yI1dTDiJUfLPrXJF
oaTIgJBWNUhflADdKuOZkxPG4gG0vwrX29ZAKZ+3+L8uaARlGVEkjD/1Shsb+15sKCMZRvS9D0t3
Oi0P3WqAMB4sSPwPde93s+qNnZLDz9qa3Ey7+CmVxSwVdk+aqah6fxjiwlFfYYwG9Oqupotn0d04
pBHiQGqwWNzLPug1MlUZKysVFq2kQYM4VKriWBRwmp3YAYGZeNbkgb2hTWCpQUH9D/HCovbSy7Eu
a7n66NRBixywVSXcFXalX/zRxqZz95fYqnHFBTmWmpQaSN9JCbK+dqJm6hgujO71WYjes4X4FC+R
KMUpUg+8NrhIpxvZ+ZLq2G1AUvYpCfq+N76JYWBk72Mskr8lLIBhmYEYgVu5HHsXwFr3KRMDd/PE
5vGLw6mzQOZZBaWSJEsKAVsdUgRxpTZS6Vw5f8jZhxxaku2gV1c9vLZMxe/WuXz2TSGQr1gSQgl4
U1B9GwDXV39ekNRPo4/vckhzXD86op/fmZMPlnCteY7opKBIWbDpap6wnVFVl2hh0FJ+/rswdrLh
tFoVJltbUEUDzklolN9axyNhB7tR9yhPaHlMvCuk6GuHh1iyyokvywGAWkJ5XSSARa7HOvSg5I+9
TdGe30GUhVWGfZnYOq7sKg20tLP76RxO7uc99QOiq4rxReLU6AlfgFgcGA0b433OphDLOOYnwiWL
pGDbnXKcRJmjCdNRCl0C4OJ6VssuG7Lpa4c/aulAE7iryA3xIZsOirca2LlCWlQFPOINEcfdjT1r
oLoXiBtDomZ5b5RWck/1q7wMROAU1kv8nreIQdb9a8WXqAE78Sp3nd6JWHJMzAw4CS7rCHVA/8vV
GUHc5Cb73Ug+JJPWgUdNXheyf+jyORixvysWt6lhJDK3f4MmgT5Inm5X/hrT+wKi8of7HnJXkVuK
PZOHG68lrlBv6GwMtVVdPyjdkZg37e4vOwVbQEC/F9KiLrXtzQb6jPrMpiPAzhdoF8kVNOdrVh4s
wvPxs0oUNaRIrkXn+qyMwD/4Pv7Q695/DtnY/F5fBeRgQ+7fnoKdkncvnWPftfRerJrVidSHECEZ
BEBaRbFLfyPQFWklfBmoreHIBfzhRzTBN7T6au8ZRGDlgPrIFkpj2HNR3niEwqx8lWWnBtmfNwiq
eAFPY1jGYzWNABQxw012bMnApJFKrsNzZrnFTOaIcdG9+0NTC1BYCDzY/6r2nG6fm5aKQ8PA3SKo
s7i1FXRWbUphXAKrel9uviqvwt4AOKs1hMyMvPxs4T3qdoAiLNFMcTpU2/3IDZs/WFtrF+lsyOF3
8meXZVS2EfT54OQXoU7RE9z5aAt3MGaM29VmqMeLsrgey5w7hmFIMpDfpIQ9lRDSwYXAQcX5nWa5
rbhvT82cSm4frnOibwSyYirhuK0d1R449moIVpq0jLJDYBtaCPHSXXUFIxv/sX0FVnc3DlnVWOIQ
Q2a8KLaJNPGV7o+twrk07/BT78yF67xdGdcyfIShD9ueicL2hPOqo7qA79Gp8oebQy/5zyibB9dy
IwjUmcF2KBMM4OPClAwS/5gLgbQN/pfJ0p1Y8AaiXX4sBHkBIaKeB52jMYbmNUcD80jIBkcVXqEU
sPy8lwLCdgPFHoBsLJQS7zxMwXrFrVG2vYOX0z19zHsVdacuJ3E2QpMOHPB1BWxywyEq88QMqcaU
Xyq947PPMTndrp5V4DINZznut3BptR3ThStGI3SWN9u7Ip6325Y/nX0GnKO8Nc3mMc1ZuTWgRR/6
JNOyeO1g1nER7tPlmWsj0RqgZqO215386j7WbvDWW2y1jkP2YESHT7xg94AEZdiXqOWxwpgi5mV3
gNS1+sB6B4lCu93BeJ9QOMGc5Re+McGvQ3Q/xa5jyas0jJxpS0Ejsng2DmZrN+vbhyXoECT4tmlA
eMShG62e2epZQhCI/+8sFZ2ukGKUZwMrrATZvWI6G5RdOYi56Rv1NFVyQM6BfavXqKUWEmC5/Eyi
XhnjmBwP0CU0hBDu3Fpl9i1GVoV4i3OIdE1rZNi9ploCUS/s6gddSTpGT2AiwlhHtmVh5xWCzG8P
jBuG042/fp4UzhWGeZIjiZnf4hoMQL/uVTJJa4wyTzO//6VoxoxBNQTxRXKDMCW9VMgE9cG9wofX
Eg2vlZPL9eDYmO7k5R82Xf9+yzq5jlyEMw0RrHtEXRBIzsi+SVNpZAbU2ZcShgPMPILh0jaPhAzS
gNof7vJCmAYDWYoIdpn3V+BSNa2s/+4z1lGdVtMX7Wgfdl/zCaGIpLKdM+23cMvlJgwuWYiImwLs
B9uR0cjDWdh/G7B05L+9/NSCNrR3/4YKhsInNkF49mqrHeTibLfRL3vULfYjsOwIRm7iZBHmTpa0
HxlLnr7H3Szz48CBfAXNBoxfOlWapsodq4qlLVYpGHTLA2eS7ThNBiGDxUdIZnzUjUW0GKNUCLu2
+iWxJnGKLs1ZHI8idCVyA71ghZPpKDYPptN2/TsulXT8ngn7R2F3cDFywvCZCh8Ljfe0XwseDT/r
7RjUWah3YFOJ6e0/yDpaJL74bFrj89w9DNroQuaM+aP239Le8x9ulevRSCi03qqVOmUe3QF4i5HL
XFMb1P/Ep3Ih3KmhD8qtvmemtujgjbv4pYkFJBnX6nhYg9go5ctp9EY+EuCXXdcjUfi5Ck58MwXH
Mw/tERylzRTqcbA87VaSI4xDuxhP7QaSWXA5nDEXc5tpMLU/5SBNqtP1hPKlno1ilSL8lMsRUTZQ
K9qrwwMxcLG+GcuAR4d+7V/FAXSGW1PQJ4C3tXVANFALV4z5sI1yyqyISJ6G7fO8PBFbutRYSyvi
lxo84eq2Q9zBArLPeliacWz129Nac6QmZzr/XDR/Q+UQO8tcELqaUGS7Y3gMb7nQ/y2n/EuMFCA4
YZCPzvQixIHEQiGO17cTlNCk3w9vRz8dkap1vW9OcxDK40B3ZyT64cbyoY+nFyHsoYe+To3+jWLL
dMCRPbVgvHfrbpZGPXdqOVlPWcfG8/4kcBiOUBN5/BF+JZFXr+247pGNuoxKdzrpBzn41uR4qQX9
1hk7tk8oCPwUimhiFSmNxvCFdJ4QfSghS/iXOa/jDCwbukro91oXEIzv6EfDlg/rEGlw/F3+nGVa
brMA24gH5GtRK/zDLzFJxvqoEOJccfPLCsXa+nYbzkx6WKC9oadrzo3bXI57KejhzEmxoBfX4i9H
fSKiCwBW0c1JYGYX3rhhVNyae6+cY1sd0Gzu2lYH+gEL1AqYJbvBiJpftciW132IGRtclFIM1g2M
323hQBkpvX3zNT4F4zPT+xGmwWOALU7oT9JJAx7F/7IfWlsPoeMplh/f6OwOgQKyFHGzIWhe585h
SyCZBptfpyblklWfdFblA5xiwdSRf8HldSuV/jHURqBm9rp6sPGc6ur5iQ7NPPRahXDBaYkUZoRe
EIuyCn8h9EDAgTpgQiYPj0RQfvd+clsa+o8YDO9WZVIvLeSUJl12Z6/VHb2s3XBCzOvsECCDBu8W
ZTCviNC5+0PHqkNbPWljlV8BR+kWnqar4F3mlLCl4nKl0iSR7qnhTQiiawyFj5TM0YJQFtkjZatg
mZINjILDAq9bpep0atJkHBB2OgXN1TYNi3FpvS6ajkE5xA0K5mNoJZ8Fx4e01dDpg3F9DR6UO7t5
P2yfPHhikiIIq7juIP+Ae8mSC+10vOG1zLHNmXHU4wuuKnXAYS/+JOnlKJcJdtNaVPN4BtfCPnpo
EOFTGiPBi6n48GJMRWbMLAkZEtB0+7jCq6pLRm9JZdJnAtQR79Mk9JvYz+tZtpYmf0cN/5osZFER
0R55smCtTMPyiWygx2/hGcCRhUEAQ/MNJ//f2xXc16WZVyh0bxaGAD21MIkSovZNFbMBlrx0f7Rf
gzV3VZcTF0tlg1vZjeWpONjKjHgEIaW/PJdXzX7vYmY0yKmsD8SnT3qvAsOZiiD1qHrSZjqXnOCt
LX6OF5JkONTo3b3m54kgklBMX8C9XTHjEGwpkAI+V9qvlZFZvaIJe/iug+bOSZk/mqno5JuGGHvq
vXqmdgdNQK0dUUFp6aeNVrpLtWck99IbQ75xs+SgDscSrTSDumS+u923jAIheDI5uFnHTteOTjoq
vD6CpAhgS2os2Fhuu7G464CCDytvMPIS2EoRFAgbmrSDCUsQ4b6xruZf3n7mF2+cSDo0SEYYH0mo
yCHVELj5grHu55Z63SJkT4Awr0LCrgkOtbpeMwdS9ZnCsNcojDwMgH0Oh0WqongOMp9kraZ4o1UV
wwDm7iwzPENF67td6bjTLxo6j4B3q8C4z4zaTciAec1VRSvAryEbqrKw1dvkKhrzBNClAAVqDW3L
PB6/EFBJllzqeLzBUZOHkns6BYotoGkX4Ua4N4+hFuYMRLL2o4bF82aoBow7+K4rOmenTe3/awoY
kc1cnytBEdMmIs7sjosmfELqlIOrUrZkgsuufuUH0nxjMTzITd7d1q7k52TCPLkNNFEW7rQ6Y5iT
7vjrbVvncMYWlJL5tG7oY7/Y37dbER2SLHC+A4hpYbSvIzdI2ya9Toe/bRjn9Hy9AoamcFKWJjWx
IVCH4xdrYN6Movu5LEEzyQtZpwopwbLIQzGivtGEiVIr9oMuldmKpDTUFw5XqB7i/Z0wFNmHeHC9
AWkqwcSy8bAanhKg7ks7qD9CYHxO7LZ9eFWiBChWjBjYWlFEuu5WkiLvVLsCia9qHa+jZHMsizc+
Fr48o/E2XtIDUDkFqVsZFhGGiSwrTO2u0eZP0ThDhJ7Q2QbtoFjh3R/FH+O+llnTG6ILBSa86QLc
Y8q+yArl8oWv+O6qDa0IqwYZYRcHLUqsqnFt6azi5ZcjllNQT1jOnDUNReWLBi+4oNg6WfCxuuNK
EdgNJ39h5ffJjneLMimGtu1Qdjeyyx5WPOWbOBBKjGd0MCbVV+/OnOQmmYartt2C/yNGcg011edR
w/HD5ok=
`protect end_protected
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:24:29 02/20/2013
-- Design Name:
-- Module Name: /home/frank/testproject/PCounte_tb.vhd
-- Project Name: testproject
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: pc
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY PCounte_tb IS
END PCounte_tb;
ARCHITECTURE behavior OF PCounte_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT pc
PORT(
clk : IN std_logic;
reset : IN std_logic;
PC_in : IN std_logic_vector(31 downto 0);
PC_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal PC_in : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal PC_out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: pc PORT MAP (
clk => clk,
reset => reset,
PC_in => PC_in,
PC_out => PC_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
PC_in <= (others => '0');
wait for clk_period*10;
PC_in <= PC_out + 4;
wait for clk_period;
wait for 2 ns;
reset <= '1';
wait for 10 ns;
reset <= '0';
wait for 2 ns;
PC_in <= PC_out + 4;
wait for clk_period;
PC_in <= PC_out + 4;
wait for clk_period;
PC_in <= PC_out + 4;
wait;
end process;
END;
|
-------------------------------------------------------------------------
---- ----
---- Company: University of Bonn ----
---- Engineer: Daniel Hahne & John Bieling ----
---- ----
-------------------------------------------------------------------------
---- ----
---- Copyright (C) 2015 Daniel Hahne & John Bieling ----
---- ----
---- This program is free software; you can redistribute it and/or ----
---- modify it under the terms of the GNU General Public License as ----
---- published by the Free Software Foundation; either version 3 of ----
---- the License, or (at your option) any later version. ----
---- ----
---- This program is distributed in the hope that it will be useful, ----
---- but WITHOUT ANY WARRANTY; without even the implied warranty of ----
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----
---- GNU General Public License for more details. ----
---- ----
---- You should have received a copy of the GNU General Public ----
---- License along with this program; if not, see ----
---- <http://www.gnu.org/licenses>. ----
---- ----
-------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rw_register is
Generic (myaddress: natural := 16#FFFF#);
Port ( databus : inout STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
addressbus : in STD_LOGIC_VECTOR (15 downto 0);
writesignal : in STD_LOGIC;
readsignal : in std_logic;
CLK : in STD_LOGIC;
registerbits : out STD_LOGIC_VECTOR (31 downto 0) := (others => '0')
);
end rw_register;
architecture Behavioral of rw_register is
signal memory : STD_LOGIC_VECTOR (31 downto 0) := (others => '0');
begin
registerbits <= memory;
process (CLK) begin
if (rising_edge(CLK)) then
if (addressbus=myaddress) then
if (writesignal='1') then
memory <= databus;
elsif(readsignal='1') then
databus <= memory;
else
databus <= (others => 'Z');
end if;
else
databus <= (others => 'Z');
end if;
end if;
end process;
end Behavioral;
|
-- NEED RESULT: *** An assertion follows with severity level ERROR
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00324
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.4 (5)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00324)
-- ENT00324_Test_Bench(ARCH00324_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
--
-- NOTES:
--
-- Verify that assertion messages match the comment messages output.
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00324 of E00000 is
signal Dummy : Boolean := false;
begin
P1 :
process ( Dummy )
begin
print ("*** An assertion follows with severity level ERROR") ;
end process P1 ;
assert Dummy
report "An assertion with severity ERROR"
severity Severity_Level'Val (2) ;
end ARCH00324 ;
entity ENT00324_Test_Bench is
end ENT00324_Test_Bench ;
architecture ARCH00324_Test_Bench of ENT00324_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00324 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00324_Test_Bench ;
|
library IEEE;
use ieee.std_logic_1164.all;
entity c_register is
generic
(
width : integer := 4
);
port
(
input : in std_logic_vector((width - 1) downto 0);
wr : in std_logic;
clear : in std_logic;
clock : in std_logic;
output : out std_logic_vector((width - 1) downto 0)
);
end c_register;
architecture behavior of c_register is
begin
process (clock, clear, input, wr)
variable interim_val : std_logic_vector((width - 1) downto 0);
begin
if (clear = '1' and clear'event) then
for i in width - 1 downto 0 loop
interim_val(i) := '0';
end loop;
elsif (wr = '1' and clock = '1' and (clock'event or input'event or wr'event)) then
interim_val := input;
end if;
output <= interim_val;
end process;
end behavior; |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0;
USE axi_bram_ctrl_v4_0.axi_bram_ctrl;
ENTITY design_1_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_axi_bram_ctrl_0_0;
ARCHITECTURE design_1_axi_bram_ctrl_0_0_arch OF design_1_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "axi_bram_ctrl,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_bram_ctrl_0_0_arch : ARCHITECTURE IS "design_1_axi_bram_ctrl_0_0,axi_bram_ctrl,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "design_1_axi_bram_ctrl_0_0,axi_bram_ctrl,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_bram_ctrl,x_ipVersion=4.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_BRAM_INST_MODE=EXTERNAL,C_MEMORY_DEPTH=16384,C_BRAM_ADDR_WIDTH=14,C_S_AXI_ADDR_WIDTH=16,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=2,C_S_AXI_PROTOCOL=AXI4,C_S_AXI_SUPPORTS_NARROW_BURST=1,C_SINGLE_PORT_BRAM=1,C_FAMILY=zynq,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32,C_ECC=0,C_ECC_TYPE=0,C_FAULT_INJECT=0,C_ECC_ONOFF_RESET_VALUE=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 16384,
C_BRAM_ADDR_WIDTH => 14,
C_S_AXI_ADDR_WIDTH => 16,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 2,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 1,
C_SINGLE_PORT_BRAM => 1,
C_FAMILY => "zynq",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_1_axi_bram_ctrl_0_0_arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:33:37 03/14/2015
-- Design Name:
-- Module Name: Main - RTL
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-- spec
-- NbN : 50kHz
-- ¬Ë¸x : 0.02ms
-- Åå¬ËÂ\Ô : 5.1ms
-- oÂ\Åáñ] : 1700rpm
entity Main is
port(
clk : in std_logic;
enable : in std_logic;
timing_pulse : in std_logic;
fi_pulse : out std_logic;
sck: in std_logic;
ssel: in std_logic;
mosi : in std_logic;
miso : out std_logic;
iac_pulse : in std_logic := '0';
iac_clockwise : in std_logic := '0';
iac_out : out std_logic_vector(7 downto 0) := (others => '0');
cpu_con : inout std_logic_vector(1 downto 0) := (others => '0'));
end Main;
architecture RTL of Main is
component SerialReceiver
port(
clk : in std_logic;
rx : in std_logic;
data : out std_logic_vector(7 downto 0)
);
end component;
component SerialSender
port(
clk : in std_logic;
tx : out std_logic;
data : in std_logic_vector(7 downto 0);
send : in std_logic;
sending : out std_logic := '0'
);
end component;
component PulseTimer
port(
clk : in std_logic;
enable : in std_logic;
start : in std_logic;
match : in std_logic_vector(7 downto 0);
pulse : out std_logic
);
end component;
component Stopwatch
port(
clk : in std_logic;
stamp_and_reset : in std_logic;
time_stamp : out std_logic_vector(7 downto 0)
);
end component;
component SPISlave
port(
sck : in std_logic;
mosi : in std_logic;
miso : out std_logic;
ssel : in std_logic;
in_data : in std_logic_vector(7 downto 0);
out_data : out std_logic_vector(7 downto 0)
);
end component;
component Stepper
port(
iac_pulse : in std_logic := '0';
iac_clockwise : in std_logic := '0';
iac_out : out std_logic_vector(7 downto 0) := (others => '0')
);
end component;
signal counter_match : std_logic_vector(7 downto 0) := (others => '0');
signal time_stamp : std_logic_vector(7 downto 0);
begin
--cpu_con(0) <= timing_pulse;
st: Stepper port map (
iac_pulse => iac_pulse,
iac_clockwise => iac_clockwise,
iac_out => iac_out
);
sw: Stopwatch port map (
clk => clk,
stamp_and_reset => timing_pulse,
time_stamp => time_stamp
);
spi: SPISlave port map (
sck => sck,
mosi => mosi,
miso => miso,
ssel => ssel,
out_data => counter_match,
in_data => time_stamp
--in_data => std_logic_vector(to_unsigned(123, 8))
);
fi_pulse_gen: PulseTimer port map (
clk => clk,
enable => enable,
start => timing_pulse,
match => counter_match,
pulse => fi_pulse
);
end RTL;
|
CONFIGURATION Reg_Behavior_config OF Reg IS
FOR Behavior
END FOR;
END Reg_Behavior_config; |
CONFIGURATION Reg_Behavior_config OF Reg IS
FOR Behavior
END FOR;
END Reg_Behavior_config; |
CONFIGURATION Reg_Behavior_config OF Reg IS
FOR Behavior
END FOR;
END Reg_Behavior_config; |
-- ########################################################################
-- $Software: busiac
-- $section : hardware component
-- $Id: initiateur.vhd 327 2015-06-03 19:18:19Z ia $
-- $HeadURL: svn://lunix120.ensiie.fr/ia/cours/archi/projet/busiac/vhdl/initiateur.vhd $
-- $Author : Ivan Auge (Email: auge@ensiie.fr)
-- ########################################################################
--
-- This file is part of the BUSIAC software: Copyright (C) 2010 by I. Auge.
--
-- This program is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at your
-- option) any later version.
--
-- BUSIAC software is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY ; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
-- Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with the GNU C Library; see the file COPYING. If not, write to the Free
-- Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
-- ######################################################################*/
-------------------------------------------------------------------------------
-- Ce module transfert tous les messages venant de busin sur busout.
-- De plus, ce module récupère 4 octets B3,B2,B1,B0 1 par 1 sur RS232in et
-- les regroupe pour réaliser un message (0000,addrsrc,addrdest,data)
-- (voir bus.txt) qu'il transfert sur busout.
-- B0 est le premier octet reçu, B3 est le dernier octet reçu.
--
-- addrsrc = 11111111 (255)
-- addrdest = B3
-- data = B2<<16 | B1<<8 | B0
--
-- Du coté busin, il suit le protocole "poignée de main" (signaux: busin,
-- busin_valid, busin_eated).
-- Du coté busout, il suit le protocole "poignée de main" (signaux: busout,
-- busout_valid, busout_eated).
-- Du coté RS232in, il suit le protocole du module RS232in (signaux: Data, Ndata).
--
-- Attention:
-- - il n'y a pas de contrôle de flux du cote RS232in, donc si des données
-- arrive sur Data et que le bus est bloqué, elles seront perdues.
-- - ce module assume que Data reste stable au moins 3 cycles après la pulse Ndata
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY initiateur IS
PORT(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
-- interface busin
busin : in STD_LOGIC_VECTOR(43 DOWNTO 0);
busin_valid : in STD_LOGIC;
busin_eated : out STD_LOGIC;
-- interface busout
busout : OUT STD_LOGIC_VECTOR(43 DOWNTO 0);
busout_valid : OUT STD_LOGIC;
busout_eated : IN STD_LOGIC;
-- interface vers rs232out
Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Ndata : IN STD_LOGIC);
END initiateur;
ARCHITECTURE Montage OF initiateur IS
-- compteur donnant le nombre d'octets a mettre dans R_32
TYPE T_CMD_i IS (NOOP, COUNT, INIT);
SIGNAL CMD_i : T_CMD_i ;
SIGNAL R_i : INTEGER RANGE 0 TO 4;
SIGNAL VT_endLoop: STD_LOGIC;
-- accumule les octets venant de Data.
TYPE T_CMD_32 IS (NOOP, SHIFT);
SIGNAL CMD_32 : T_CMD_32 ;
SIGNAL R_32 : STD_LOGIC_VECTOR (31 DOWNTO 0);
-- Registre de transfert entre busin et busout
TYPE T_CMD_tft IS (INIT, NOOP);
SIGNAL CMD_tft : T_CMD_tft ;
SIGNAL R_tft : STD_LOGIC_VECTOR (43 DOWNTO 0);
-- Sauve une pulse de Ndata qd on est dans les etats de la FSM
-- qui ne teste pas Ndata
TYPE T_CMD_pulse IS (CLEAR, LOAD);
SIGNAL CMD_pulse : T_CMD_pulse ;
SIGNAL R_pulse : STD_LOGIC;
SIGNAL R_data : STD_LOGIC_VECTOR(7 DOWNTO 0);
-- les sources d'ecriture sur busout
SIGNAL busout_rs232 : STD_LOGIC_VECTOR(43 DOWNTO 0);
SIGNAL busout_tft : STD_LOGIC_VECTOR(43 DOWNTO 0);
--Description des �tats
TYPE STATE_TYPE IS (
ST_INIT,ST_WAIT_BUSIN_OR_NDATA,
ST_BUSIN_AND_NDATA_LOADED,
ST_NDATA_LOADED, ST_BUSIN_LOADED,
ST_EndLoop, ST_NDATA_WRITE);
SIGNAL state : STATE_TYPE;
BEGIN
-------------------------------------------------------------------------------
-- Partie Op�rative
-------------------------------------------------------------------------------
PROCESS (clk)
BEGIN IF clk'EVENT AND clk = '1' THEN
-- R_i
if ( CMD_i = INIT ) then
R_i <= 4 ;
elsif ( CMD_i = COUNT ) then
R_i <= R_i - 1;
else
R_i <= R_i;
end if;
-- R_32
if ( CMD_32 = SHIFT ) then
R_32(31 DOWNTO 24) <= R_data;
R_32(23 DOWNTO 16) <= R_32(31 DOWNTO 24);
R_32(15 DOWNTO 8) <= R_32(23 DOWNTO 16);
R_32( 7 DOWNTO 0) <= R_32(15 DOWNTO 8);
else
R_32 <= R_32 ;
end if;
-- R_tft
if ( CMD_tft = INIT ) then
R_tft <= busin ;
else
R_tft <= R_tft ;
end if;
-- R_pulse
if ( CMD_pulse = LOAD ) then
R_pulse <= R_pulse OR Ndata ;
else -- CLEAR
R_pulse <= '0' ;
end if;
-- R_data
if (Ndata = '1') then
R_data <= data;
else
R_data <= R_data;
end if;
END IF; END PROCESS;
VT_endLoop <= '1' when R_i=0 else '0' ;
busout_rs232(43 DOWNTO 40) <= "0000";
busout_rs232(39 DOWNTO 32) <= "11111111";
busout_rs232(31 DOWNTO 0) <= R_32;
busout_tft <= R_tft;
-------------------------------------------------------------------------------
-- Partie Contr�le
-------------------------------------------------------------------------------
-- Inputs: busout_eated Ndata R_pulse VT_endLoop busin_valid
-- Outputs: busout_valid CMD_i CMD_32 busin_eated CMD_tft CMD_pulse busout
-------------------------------------------------------------------------------
-- fonction de transitition
PROCESS (reset,clk)
BEGIN
if reset = '1' then
state <= ST_INIT;
ELSIF clk'EVENT AND clk = '1' THEN
CASE state IS
WHEN ST_INIT =>
state <= ST_WAIT_BUSIN_OR_NDATA;
WHEN ST_WAIT_BUSIN_OR_NDATA =>
IF busin_valid = '1' AND R_pulse = '1' THEN
state <= ST_BUSIN_AND_NDATA_LOADED;
ELSIF R_pulse = '1' THEN
state <= ST_NDATA_LOADED;
ELSIF busin_valid = '1' THEN
state <= ST_BUSIN_LOADED;
END IF;
WHEN ST_BUSIN_LOADED =>
if busout_eated = '1' then
state <= ST_WAIT_BUSIN_OR_NDATA;
END IF;
WHEN ST_BUSIN_AND_NDATA_LOADED =>
if busout_eated = '1' then
state <= ST_NDATA_LOADED;
END IF;
WHEN ST_NDATA_LOADED =>
state <= ST_EndLoop;
WHEN ST_EndLoop =>
IF VT_EndLoop = '1' THEN
state <= ST_NDATA_WRITE;
else
state <= ST_WAIT_BUSIN_OR_NDATA;
END IF;
WHEN ST_NDATA_WRITE =>
if busout_eated = '1' then
state <= ST_WAIT_BUSIN_OR_NDATA;
END IF;
END CASE;
END IF;
END PROCESS;
-- fonction de sortie
WITH state SELECT busout_valid <=
'1' WHEN ST_BUSIN_LOADED,
'1' WHEN ST_NDATA_WRITE,
'0' WHEN OTHERS;
WITH state SELECT CMD_i <=
INIT WHEN ST_INIT,
INIT WHEN ST_NDATA_WRITE,
COUNT WHEN ST_NDATA_LOADED,
NOOP WHEN OTHERS;
WITH state SELECT CMD_32 <=
SHIFT WHEN ST_NDATA_LOADED,
NOOP WHEN OTHERS;
WITH state SELECT busin_eated <=
'1' WHEN ST_WAIT_BUSIN_OR_NDATA,
'0' WHEN OTHERS;
WITH state SELECT CMD_tft <=
INIT WHEN ST_WAIT_BUSIN_OR_NDATA,
NOOP WHEN OTHERS;
WITH state SELECT CMD_pulse <=
CLEAR WHEN ST_NDATA_LOADED,
LOAD WHEN OTHERS;
WITH state SELECT busout <=
busout_rs232 WHEN ST_NDATA_WRITE,
busout_tft WHEN OTHERS;
END Montage;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:10:19 03/04/2014
-- Design Name:
-- Module Name: C:/Users/fafik/Dropbox/infa/xilinx/ethernet/smi_divider_test.vhd
-- Project Name: ethernet
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: SMI_divider
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY smi_divider_test IS
END smi_divider_test;
ARCHITECTURE behavior OF smi_divider_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SMI_divider
PORT(
clk_in : IN std_logic;
clk_out : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk_in : std_logic := '0';
--Outputs
signal clk_out : std_logic;
-- Clock period definitions
constant clk_in_period : time := 10 ns;
constant clk_out_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SMI_divider PORT MAP (
clk_in => clk_in,
clk_out => clk_out
);
-- Clock process definitions
clk_in_process :process
begin
clk_in <= '0';
wait for clk_in_period/2;
clk_in <= '1';
wait for clk_in_period/2;
end process;
END;
|
--------------------------------------------------------------------------------
--
-- File:
-- SerializerN_1.vhd
--
-- Module:
-- SerializerN_1
--
-- Author:
-- Elod Gyorgy
--
-- Date:
-- 10/27/2010
--
-- Description:
-- This module serializes N:1 data LSB-first using cascaded OSERDES
-- primitives.
--
-- Copyright notice:
-- Copyright (C) 2014 Digilent Inc.
--
-- License:
-- This program is free software; distributed under the terms of
-- BSD 3-clause license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-- IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
-- OF THE POSSIBILITY OF SUCH DAMAGE.
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity SerializerN_1 is
Generic ( N : NATURAL := 10;
FAMILY : STRING := "spartan6");
Port ( DP_I : in STD_LOGIC_VECTOR (N-1 downto 0);
CLKDIV_I : in STD_LOGIC; --parallel slow clock
CLKDIV_X2_I : in STD_LOGIC; --double parallel slow clock (CLKDIV_I x 2) REQUIRED ONLY FOR Spartan-6
SERCLK_I : in STD_LOGIC; --serial fast clock (CLK_I = CLKDIV_I x N / 2)
SERSTB_I : in STD_LOGIC; -- REQUIRED ONLY FOR Spartan-6
RST_I : in STD_LOGIC; --async reset
DSP_O : out STD_LOGIC;
DSN_O : out STD_LOGIC);
end SerializerN_1;
architecture Behavioral of SerializerN_1 is
signal intDSOut: std_logic;
signal intDPIn : std_logic_vector(N/2-1 downto 0) ;
signal padDPIn : std_logic_vector(13 downto 0) ;
signal cascade_do, cascade_di, cascade_to, cascade_ti : std_logic;
signal gear, gear_s : std_logic := '0';
signal int_rst : std_logic;
begin
----------------------------------------------------------------------------------
-- Instantiate Output Buffer
----------------------------------------------------------------------------------
io_datax_out : obufds port map (
O => DSP_O,
OB => DSN_O,
I => intDSOut);
family_s6: if FAMILY = "spartan6" generate
begin
----------------------------------------------------------------------------------
-- 2:1 gearbox; SerDes is used in 5:1 ratio, we need to double that; The SerDes
-- parallel input will change twice in a pixel clock, thus the need for pixel
-- clock * 2
----------------------------------------------------------------------------------
process (CLKDIV_I, RST_I)
begin
if (RST_I = '1') then
gear <= '0';
elsif Rising_Edge(CLKDIV_I) then
gear <= not gear;
end if;
end process;
process (CLKDIV_X2_I)
begin
if Rising_Edge(CLKDIV_X2_I) then
gear_s <= gear; --resync gear on x2 domain
end if;
end process;
process (CLKDIV_X2_I)
begin
if Rising_Edge(CLKDIV_X2_I) then
if ((gear xor gear_s) = '1') then
intDPIn <= DP_I(N/2-1 downto 0);
else
intDPIn <= DP_I(N-1 downto N/2);
end if ;
end if;
end process ;
padDPIn(7 downto N/2) <= (others => '0');
padDPIn(N/2-1 downto 0) <= intDPIn(N/2-1 downto 0);
----------------------------------------------------------------------------------
-- Cascaded OSERDES for 5:1 ratio
----------------------------------------------------------------------------------
oserdes_m : OSERDES2 generic map (
DATA_WIDTH => N/2, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "SDR", -- <SDR>, DDR
DATA_RATE_OT => "SDR", -- <SDR>, DDR
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => intDsOut, --master outputs serial data in cascaded setup
OCE => '1',
CLK0 => SERCLK_I,
CLK1 => '0',
IOCE => SERSTB_I,
RST => RST_I, --async reset
CLKDIV => CLKDIV_X2_I, --parallel data transferred at 2x pixel clock (2x 5:1 = 10:1)
D4 => padDPIn(7), --not used in 5:1
D3 => padDPIn(6), --not used in 5:1
D2 => padDPIn(5), --not used in 5:1
D1 => padDPIn(4), --MSB in 5:1
TQ => open, --no tri-state
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => '1', -- Dummy input in Master
SHIFTIN2 => '1', -- Dummy input in Master
SHIFTIN3 => cascade_do, -- Cascade output D data from slave
SHIFTIN4 => cascade_to, -- Cascade output T data from slave
SHIFTOUT1 => cascade_di, -- Cascade input D data to slave
SHIFTOUT2 => cascade_ti, -- Cascade input T data to slave
SHIFTOUT3 => open, -- Dummy output in Master
SHIFTOUT4 => open) ; -- Dummy output in Master
oserdes_s : OSERDES2 generic map(
DATA_WIDTH => N/2, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE_OQ => "SDR", -- <SDR>, DDR
DATA_RATE_OT => "SDR", -- <SDR>, DDR
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
OUTPUT_MODE => "DIFFERENTIAL")
port map (
OQ => open, --slave does not output serial data in cascaded setup
OCE => '1',
CLK0 => SERCLK_I,
CLK1 => '0',
IOCE => SERSTB_I,
RST => RST_I, --async reset
CLKDIV => CLKDIV_X2_I, --parallel data transferred at 2x pixel clock (2x 5:1 = 10:1)
D4 => padDPIn(3),
D3 => padDPIn(2),
D2 => padDPIn(1),
D1 => padDPIn(0),
TQ => open, --no tri-state
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TRAIN => '0',
TCE => '1',
SHIFTIN1 => cascade_di, -- Cascade input D from Master
SHIFTIN2 => cascade_ti, -- Cascade input T from Master
SHIFTIN3 => '1', -- Dummy input in Slave
SHIFTIN4 => '1', -- Dummy input in Slave
SHIFTOUT1 => open, -- Dummy output in Slave
SHIFTOUT2 => open, -- Dummy output in Slave
SHIFTOUT3 => cascade_do, -- Cascade output D data to Master
SHIFTOUT4 => cascade_to) ; -- Cascade output T data to Master
end generate family_s6;
family_7: if FAMILY = "kintex7" or FAMILY = "artix7" or FAMILY = "virtex7" generate
begin
----------------------------------------------------------------------------------
-- Reset should be asserted asynchronously an de-asserted synchronously
----------------------------------------------------------------------------------
process(RST_I, CLKDIV_I)
begin
if (RST_I = '1') then
int_rst <= '1';
elsif Rising_Edge(CLKDIV_I) then
int_rst <= '0';
end if;
end process;
padDPIn(13 downto N) <= (others => '0');
padDPIn(N-1 downto 0) <= DP_I;
----------------------------------------------------------------------------------
-- Cascaded OSERDES for 10:1 ratio (DDR)
----------------------------------------------------------------------------------
oserdese2_master : OSERDESE2
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "SDR",
DATA_WIDTH => N,
TRISTATE_WIDTH => 1,
SERDES_MODE => "MASTER")
port map (
D1 => padDPIn(0),
D2 => padDPIn(1),
D3 => padDPIn(2),
D4 => padDPIn(3),
D5 => padDPIn(4),
D6 => padDPIn(5),
D7 => padDPIn(6),
D8 => padDPIn(7),
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
SHIFTIN1 => cascade_di,
SHIFTIN2 => cascade_ti,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
OCE => '1',
CLK => SERCLK_I,
CLKDIV => CLKDIV_I,
OQ => intDsOut,
TQ => open,
OFB => open,
TBYTEIN => '0',
TBYTEOUT => open,
TFB => open,
TCE => '0',
RST => int_rst);
oserdese2_slave : OSERDESE2
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "SDR",
DATA_WIDTH => N,
TRISTATE_WIDTH => 1,
SERDES_MODE => "SLAVE")
port map (
D1 => '0',
D2 => '0',
D3 => padDPIn(8),
D4 => padDPIn(9),
D5 => padDPIn(10),
D6 => padDPIn(11),
D7 => padDPIn(12),
D8 => padDPIn(13),
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
SHIFTOUT1 => cascade_di,
SHIFTOUT2 => cascade_ti,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
OCE => '1',
CLK => SERCLK_I,
CLKDIV => CLKDIV_I,
OQ => open,
TQ => open,
OFB => open,
TFB => open,
TBYTEIN => '0',
TBYTEOUT => open,
TCE => '0',
RST => int_rst);
end generate family_7;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_aa
--
-- Generated
-- by: wig
-- on: Fri Jul 15 16:37:20 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_aa-e.vhd,v 1.3 2005/07/15 16:20:04 wig Exp $
-- $Date: 2005/07/15 16:20:04 $
-- $Log: ent_aa-e.vhd,v $
-- Revision 1.3 2005/07/15 16:20:04 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_aa
--
entity ent_aa is
-- Generics:
-- No Generated Generics for Entity ent_aa
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_aa
port_aa_1 : out std_ulogic;
port_aa_2 : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
port_aa_3 : out std_ulogic;
port_aa_4 : in std_ulogic;
port_aa_5 : out std_ulogic_vector(3 downto 0);
port_aa_6 : out std_ulogic_vector(3 downto 0);
sig_07 : out std_ulogic_vector(5 downto 0);
sig_08 : out std_ulogic_vector(8 downto 2);
sig_13 : out std_ulogic_vector(4 downto 0)
-- End of Generated Port for Entity ent_aa
);
end ent_aa;
--
-- End of Generated Entity ent_aa
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:07:34 11/19/2013
-- Design Name:
-- Module Name: My_ALU_948282 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity My_ALU_948282 is
Port ( Alu0 : in STD_LOGIC;
Alu1 : in STD_LOGIC;
A_alu : in STD_LOGIC_VECTOR (31 downto 0);
B_alu: in STD_LOGIC_VECTOR (31 downto 0);
B_Inv : in STD_LOGIC;
Result_alu : out STD_LOGIC_VECTOR (31 downto 0));
end My_ALU_948282;
architecture Behavioral of My_ALU_948282 is
component My_32bit4x1Mux_948282 is
Port ( Select1 : in STD_LOGIC;
Select2 : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (31 downto 0);
B : in STD_LOGIC_VECTOR (31 downto 0);
C : in STD_LOGIC_VECTOR (31 downto 0);
D : in STD_LOGIC_VECTOR (31 downto 0);
R : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component My_32bitOr_948282 is
Port ( inA_8282 : in STD_LOGIC_VECTOR (31 downto 0);
inB_8282 : in STD_LOGIC_VECTOR (31 downto 0);
outR_8282 : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component My_32bitAnd_948282 is
Port ( A_8282 : in STD_LOGIC_VECTOR (31 downto 0);
B_8282 : in STD_LOGIC_VECTOR (31 downto 0);
R_8282 : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component My_32bitAdder_948282 is
Port ( A_reg : in STD_LOGIC_VECTOR (31 downto 0);
B_reg : in STD_LOGIC_VECTOR (31 downto 0);
CarryIn : in STD_LOGIC;
CarryOut : out STD_LOGIC;
Result : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component myNOT_948282 is
Port ( i1 : in STD_LOGIC;
o1 : out STD_LOGIC);
end component;
component My_32bit2x1Mux_948282 is
Port ( B_inv : in STD_LOGIC;
B : in STD_LOGIC_VECTOR (31 downto 0);
B_comp : in STD_LOGIC_VECTOR (31 downto 0);
B_out : out STD_LOGIC_VECTOR (31 downto 0));
end component;
signal sigAnd, sigOr, sigAdder, sig5, sigB: std_logic_vector(31 downto 0);
signal sig3b, sig1b, sig1: std_logic_vector(15 downto 0);
signal sig3, sig4, sig6, sig7: std_logic;
begin
u0: My_32bitAnd_948282 port map (A_8282=>A_alu, B_8282=>B_alu, R_8282=>sigAnd);
u1: My_32bitOr_948282 port map (inA_8282=>A_alu, inB_8282=>B_alu, outR_8282=>sigOr);
--sig5 = Not(B);
u2: myNOT_948282 port map (i1=>B_alu(0), o1=>sig5(0));
u3: myNOT_948282 port map (i1=>B_alu(1), o1=>sig5(1));
u4: myNOT_948282 port map (i1=>B_alu(2), o1=>sig5(2));
u5: myNOT_948282 port map (i1=>B_alu(3), o1=>sig5(3));
u6: myNOT_948282 port map (i1=>B_alu(4), o1=>sig5(4));
u7: myNOT_948282 port map (i1=>B_alu(5), o1=>sig5(5));
u8: myNOT_948282 port map (i1=>B_alu(6), o1=>sig5(6));
u9: myNOT_948282 port map (i1=>B_alu(7), o1=>sig5(7));
u10: myNOT_948282 port map (i1=>B_alu(8), o1=>sig5(8));
u11: myNOT_948282 port map (i1=>B_alu(9), o1=>sig5(9));
u12: myNOT_948282 port map (i1=>B_alu(10), o1=>sig5(10));
u13: myNOT_948282 port map (i1=>B_alu(11), o1=>sig5(11));
u14: myNOT_948282 port map (i1=>B_alu(12), o1=>sig5(12));
u15: myNOT_948282 port map (i1=>B_alu(13), o1=>sig5(13));
u16: myNOT_948282 port map (i1=>B_alu(14), o1=>sig5(14));
u17: myNOT_948282 port map (i1=>B_alu(15), o1=>sig5(15));
u18: myNOT_948282 port map (i1=>B_alu(16), o1=>sig5(16));
u19: myNOT_948282 port map (i1=>B_alu(17), o1=>sig5(17));
u20: myNOT_948282 port map (i1=>B_alu(18), o1=>sig5(18));
u21: myNOT_948282 port map (i1=>B_alu(19), o1=>sig5(19));
u22: myNOT_948282 port map (i1=>B_alu(20), o1=>sig5(20));
u23: myNOT_948282 port map (i1=>B_alu(21), o1=>sig5(21));
u24: myNOT_948282 port map (i1=>B_alu(22), o1=>sig5(22));
u25: myNOT_948282 port map (i1=>B_alu(23), o1=>sig5(23));
u26: myNOT_948282 port map (i1=>B_alu(24), o1=>sig5(24));
u27: myNOT_948282 port map (i1=>B_alu(25), o1=>sig5(25));
u28: myNOT_948282 port map (i1=>B_alu(26), o1=>sig5(26));
u29: myNOT_948282 port map (i1=>B_alu(27), o1=>sig5(27));
u30: myNOT_948282 port map (i1=>B_alu(28), o1=>sig5(28));
u31: myNOT_948282 port map (i1=>B_alu(29), o1=>sig5(29));
u32: myNOT_948282 port map (i1=>B_alu(30), o1=>sig5(30));
u33: myNOT_948282 port map (i1=>B_alu(31), o1=>sig5(31));
u34: My_32bit2x1Mux_948282 port map (B_inv=>B_Inv, B=>B_alu, B_comp=>sig5, B_out=>sigB); --sigB in Adder
u35: My_32bitAdder_948282 port map (A_reg=>A_alu, B_reg=>sigB, CarryIn=>B_Inv, CarryOut=>sig3, Result=>sigAdder);
u36: My_32bit4x1Mux_948282 port map (Select1=>Alu1, Select2=>Alu0, A=>sigAnd, B=>sigOr, C=>sigAdder, D=>"00000000000000000000000000000000", R=>Result_alu);
end Behavioral;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
-------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:25:53 12/17/2013
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description: NES (nintendo) controller wishbone driver to access NES data from the EDU board
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity wishbone_nes is
generic(
wb_size : natural := 16; -- Data port size for wishbone
N: integer := 17 --17 bit overflow 131k
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
--nes data signals
nes1_dat : in std_logic;
nes2_dat : in std_logic;
nes_lat : out std_logic;
nes_clk : out std_logic;
nes1_data_out: out std_logic_vector(7 downto 0);
nes2_data_out: out std_logic_vector(7 downto 0)
);
end wishbone_nes;
architecture Behavioral of wishbone_nes is
signal read_ack : std_logic ;
signal write_ack : std_logic ;
signal nes1_data_out_buf: std_logic_vector(7 downto 0);
signal nes2_data_out_buf: std_logic_vector(7 downto 0);
begin
wbs_ack <= read_ack or write_ack;
--WBM-WRITE
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
--sseg_edu_regs <= (others => (others => '0')) ; --RESET REGISTERS HERE
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
--sseg_edu_regs(conv_integer(wbs_address(1 downto 0))) <= wbs_writedata; --WRITE TO REGISTERS HERE
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
--WBM-READ
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
wbs_readdata <= nes2_data_out_buf & nes1_data_out_buf; --MASTER READ FROM REGISTERS HERE
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
nes1: entity work.nes_ctl
port map(
clk => gls_clk,
reset => gls_reset,
nes_dat => nes1_dat,
nes_lat => nes_lat,
nes_clk => nes_clk,
nes_data_out => nes1_data_out_buf
);
nes2: entity work.nes_ctl
port map(
clk => gls_clk,
reset => gls_reset,
nes_dat => nes2_dat,
nes_lat => open,
nes_clk => open,
nes_data_out => nes2_data_out_buf
);
nes1_data_out <= nes1_data_out_buf;
nes2_data_out <= nes2_data_out_buf;
end Behavioral; |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
-------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:25:53 12/17/2013
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description: NES (nintendo) controller wishbone driver to access NES data from the EDU board
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity wishbone_nes is
generic(
wb_size : natural := 16; -- Data port size for wishbone
N: integer := 17 --17 bit overflow 131k
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
--nes data signals
nes1_dat : in std_logic;
nes2_dat : in std_logic;
nes_lat : out std_logic;
nes_clk : out std_logic;
nes1_data_out: out std_logic_vector(7 downto 0);
nes2_data_out: out std_logic_vector(7 downto 0)
);
end wishbone_nes;
architecture Behavioral of wishbone_nes is
signal read_ack : std_logic ;
signal write_ack : std_logic ;
signal nes1_data_out_buf: std_logic_vector(7 downto 0);
signal nes2_data_out_buf: std_logic_vector(7 downto 0);
begin
wbs_ack <= read_ack or write_ack;
--WBM-WRITE
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
--sseg_edu_regs <= (others => (others => '0')) ; --RESET REGISTERS HERE
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
--sseg_edu_regs(conv_integer(wbs_address(1 downto 0))) <= wbs_writedata; --WRITE TO REGISTERS HERE
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
--WBM-READ
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
wbs_readdata <= nes2_data_out_buf & nes1_data_out_buf; --MASTER READ FROM REGISTERS HERE
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
nes1: entity work.nes_ctl
port map(
clk => gls_clk,
reset => gls_reset,
nes_dat => nes1_dat,
nes_lat => nes_lat,
nes_clk => nes_clk,
nes_data_out => nes1_data_out_buf
);
nes2: entity work.nes_ctl
port map(
clk => gls_clk,
reset => gls_reset,
nes_dat => nes2_dat,
nes_lat => open,
nes_clk => open,
nes_data_out => nes2_data_out_buf
);
nes1_data_out <= nes1_data_out_buf;
nes2_data_out <= nes2_data_out_buf;
end Behavioral; |
library verilog;
use verilog.vl_types.all;
entity IF_ID is
port(
clock : in vl_logic;
reset : in vl_logic;
\In\ : in vl_logic_vector(15 downto 0);
InEnable : in vl_logic;
\Out\ : out vl_logic_vector(15 downto 0)
);
end IF_ID;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library WORK;
use WORK.globals.all;
entity DDR_enable is
generic( SIZE : integer := 8 );
port(
din_hi, din_lo : in std_logic_vector( SIZE-1 downto 0 );
enable : in T_ENABLE;
dout_hi, dout_lo : out std_logic_vector( SIZE-1 downto 0 );
rst, clk : in std_logic );
end DDR_enable;
architecture small of DDR_enable is
signal high_data, low_data : std_logic_vector( SIZE-1 downto 0 );
begin
HIGH_FRONT_PROC : process( rst, clk )
begin
if ( rst=RESET_ACTIVE ) then
high_data <= ( others=>'0' );
elsif ( clk'event and clk='1' ) then
if ( enable/=C_DISABLE ) then -- v. 1.2
high_data <= din_hi;
end if;
end if; -- rst, clk
end process; -- HIGH_FRONT_PROC
LOW_FRONT_PROC : process( rst, clk )
begin
if ( rst=RESET_ACTIVE ) then
low_data <= ( others=>'0' );
elsif ( clk'event and clk='0' ) then
if ( enable/=C_DISABLE ) then -- v. 1.2
low_data <= din_lo;
end if;
end if; -- rst, clk
end process; -- HIGH_FRONT_PROC
dout_hi <= high_data;
dout_lo <= low_data;
end small;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library WORK;
use WORK.globals.all;
entity DDR_enable is
generic( SIZE : integer := 8 );
port(
din_hi, din_lo : in std_logic_vector( SIZE-1 downto 0 );
enable : in T_ENABLE;
dout_hi, dout_lo : out std_logic_vector( SIZE-1 downto 0 );
rst, clk : in std_logic );
end DDR_enable;
architecture small of DDR_enable is
signal high_data, low_data : std_logic_vector( SIZE-1 downto 0 );
begin
HIGH_FRONT_PROC : process( rst, clk )
begin
if ( rst=RESET_ACTIVE ) then
high_data <= ( others=>'0' );
elsif ( clk'event and clk='1' ) then
if ( enable/=C_DISABLE ) then -- v. 1.2
high_data <= din_hi;
end if;
end if; -- rst, clk
end process; -- HIGH_FRONT_PROC
LOW_FRONT_PROC : process( rst, clk )
begin
if ( rst=RESET_ACTIVE ) then
low_data <= ( others=>'0' );
elsif ( clk'event and clk='0' ) then
if ( enable/=C_DISABLE ) then -- v. 1.2
low_data <= din_lo;
end if;
end if; -- rst, clk
end process; -- HIGH_FRONT_PROC
dout_hi <= high_data;
dout_lo <= low_data;
end small;
|
ComparadorFinal_inst : ComparadorFinal PORT MAP (
clken => clken_sig,
clock => clock_sig,
dataa => dataa_sig,
datab => datab_sig,
AeB => AeB_sig,
AgB => AgB_sig,
AlB => AlB_sig
);
|
library ieee;
use ieee.std_logic_1164.all;
use work.types.all;
package math is
function mul2(din : byte) return byte;
function mul3(din : byte) return byte;
function mul9(din : byte) return byte;
function mulb(din : byte) return byte;
function muld(din : byte) return byte;
function mule(din : byte) return byte;
end math;
package body math is
function mul2(din : byte) return byte is
variable ret : byte;
begin
ret(0) := din(7);
ret(1) := din(0) xor din(7);
ret(2) := din(1);
ret(3) := din(2) xor din(7);
ret(4) := din(3) xor din(7);
ret(5) := din(4);
ret(6) := din(5);
ret(7) := din(6);
return ret;
end mul2;
function mul3(din : byte) return byte is
variable ret : byte;
begin
ret(0) := din(0) xor din(7);
ret(1) := din(0) xor din(1) xor din(7);
ret(2) := din(1) xor din(2);
ret(3) := din(2) xor din(3) xor din(7);
ret(4) := din(3) xor din(4) xor din(7);
ret(5) := din(4) xor din(5);
ret(6) := din(5) xor din(6);
ret(7) := din(6) xor din(7);
return ret;
end mul3;
function mul9(din : byte) return byte is
variable ret : byte;
begin
ret(0) := din(0) xor din(5);
ret(1) := din(1) xor din(5) xor din(6);
ret(2) := din(2) xor din(6) xor din(7);
ret(3) := din(0) xor din(3) xor din(5) xor din(7);
ret(4) := din(1) xor din(4) xor din(5) xor din(6);
ret(5) := din(2) xor din(5) xor din(6) xor din(7);
ret(6) := din(3) xor din(6) xor din(7);
ret(7) := din(4) xor din(7);
return ret;
end mul9;
function mulb(din : byte) return byte is
variable ret : byte;
begin
ret(0) := din(0) xor din(5) xor din(7);
ret(1) := din(0) xor din(1) xor din(5) xor din(6) xor din(7);
ret(2) := din(1) xor din(2) xor din(6) xor din(7);
ret(3) := din(0) xor din(2) xor din(3) xor din(5);
ret(4) := din(1) xor din(3) xor din(4) xor din(5) xor din(6) xor din(7);
ret(5) := din(2) xor din(4) xor din(5) xor din(6) xor din(7);
ret(6) := din(3) xor din(5) xor din(6) xor din(7);
ret(7) := din(4) xor din(6) xor din(7);
return ret;
end mulb;
function muld(din : byte) return byte is
variable ret : byte;
begin
ret(0) := din(0) xor din(5) xor din(6);
ret(1) := din(1) xor din(5) xor din(7);
ret(2) := din(0) xor din(2) xor din(6);
ret(3) := din(0) xor din(1) xor din(3) xor din(5) xor din(6) xor din(7);
ret(4) := din(1) xor din(2) xor din(4) xor din(5) xor din(7);
ret(5) := din(2) xor din(3) xor din(5) xor din(6);
ret(6) := din(3) xor din(4) xor din(6) xor din(7);
ret(7) := din(4) xor din(5) xor din(7);
return ret;
end muld;
function mule(din : byte) return byte is
variable ret : byte;
begin
ret(0) := din(5) xor din(6) xor din(7);
ret(1) := din(0) xor din(5);
ret(2) := din(0) xor din(1) xor din(6);
ret(3) := din(0) xor din(1) xor din(2) xor din(5) xor din(6);
ret(4) := din(1) xor din(2) xor din(3) xor din(5);
ret(5) := din(2) xor din(3) xor din(4) xor din(6);
ret(6) := din(3) xor din(4) xor din(5) xor din(7);
ret(7) := din(4) xor din(5) xor din(6);
return ret;
end mule;
end math;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: irqmp
-- File: irqmp.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Multi-processor APB interrupt controller. Implements a
-- two-level interrupt controller for 15 interrupts.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.leon3.all;
entity irqmp is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1)
);
end;
architecture rtl of irqmp is
constant REVISION : integer := 3;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_IRQMP, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type mask_type is array (0 to ncpu-1) of std_logic_vector(15 downto 1);
type mask2_type is array (0 to ncpu-1) of std_logic_vector(15 downto 0);
type irl_type is array (0 to ncpu-1) of std_logic_vector(3 downto 0);
type irl2_type is array (0 to ncpu-1) of std_logic_vector(4 downto 0);
type reg_type is record
imask : mask_type;
ilevel : std_logic_vector(15 downto 1);
ipend : std_logic_vector(15 downto 1);
iforce : mask_type;
ibroadcast : std_logic_vector(15 downto 1);
irl : irl_type;
cpurst : std_logic_vector(ncpu-1 downto 0);
end record;
type ereg_type is record
imask : mask2_type;
ipend : std_logic_vector(15 downto 0);
irl : irl2_type;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : reg_type := (
imask => (others => (others => '0')), ilevel => (others => '0'),
ipend => (others => '0'), iforce => (others => (others => '0')),
ibroadcast => (others => '0'), irl => (others => (others => '0')),
cpurst => (others => '0'));
constant ERES : ereg_type := (
imask => (others => (others => '0')), ipend => (others => '0'),
irl => (others => (others => '0')));
function prioritize(b : std_logic_vector(15 downto 0)) return std_logic_vector is
variable a : std_logic_vector(15 downto 0);
variable irl : std_logic_vector(3 downto 0);
variable level : integer range 0 to 15;
begin
irl := "0000"; level := 0; a := b;
for i in 15 downto 0 loop
level := i;
if a(i) = '1' then exit; end if;
end loop;
irl := conv_std_logic_vector(level, 4);
return(irl);
end;
signal r, rin : reg_type;
signal r2, r2in : ereg_type;
begin
comb : process(rst, r, r2, apbi, irqi)
variable v : reg_type;
variable temp : mask_type;
variable prdata : std_logic_vector(31 downto 0);
variable tmpirq : std_logic_vector(15 downto 0);
variable tmpvar : std_logic_vector(15 downto 1);
variable cpurun : std_logic_vector(ncpu-1 downto 0);
variable v2 : ereg_type;
variable irl2 : std_logic_vector(3 downto 0);
variable ipend2 : std_logic_vector(ncpu-1 downto 0);
variable temp2 : mask2_type;
variable neirq : integer;
begin
v := r; v.cpurst := (others => '0');
cpurun := (others => '0'); cpurun(0) := '1';
tmpvar := (others => '0'); ipend2 := (others => '0');
v2 := r2;
-- prioritize interrupts
if eirq /= 0 then
for i in 0 to ncpu-1 loop
temp2(i) := r2.ipend and r2.imask(i);
ipend2(i) := orv(temp2(i));
end loop;
end if;
for i in 0 to ncpu-1 loop
temp(i) := ((r.iforce(i) or r.ipend) and r.imask(i));
if eirq /= 0 then temp(i)(eirq) := temp(i)(eirq) or ipend2(i); end if;
v.irl(i) := prioritize((temp(i) and r.ilevel) & '0');
if v.irl(i) = "0000" then
if eirq /= 0 then temp(i)(eirq) := temp(i)(eirq) or ipend2(i); end if;
v.irl(i) := prioritize((temp(i) and not r.ilevel) & '0');
end if;
end loop;
-- register read
prdata := (others => '0');
case apbi.paddr(7 downto 6) is
when "00" =>
case apbi.paddr(4 downto 2) is
when "000" => prdata(15 downto 1) := r.ilevel;
when "001" =>
prdata(15 downto 1) := r.ipend;
if eirq /= 0 then prdata(31 downto 16) := r2.ipend; end if;
when "010" => prdata(15 downto 1) := r.iforce(0);
when "011" =>
when "100" | "101" =>
prdata(31 downto 28) := conv_std_logic_vector(ncpu-1, 4);
prdata(19 downto 16) := conv_std_logic_vector(eirq, 4);
for i in 0 to ncpu -1 loop prdata(i) := irqi(i).pwd; end loop;
if ncpu > 1 then
prdata(27) := '1';
case apbi.paddr(4 downto 2) is
when "101" =>
prdata := (others => '0');
prdata(15 downto 1) := r.ibroadcast;
when others =>
end case;
end if;
when others =>
end case;
when "01" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
prdata(15 downto 1) := r.imask(i);
if eirq /= 0 then prdata(31 downto 16) := r2.imask(i); end if;
end if;
end loop;
when "10" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
prdata(15 downto 1) := r.iforce(i);
end if;
end loop;
when "11" =>
if eirq /= 0 then
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
prdata(4 downto 0) := r2.irl(i);
end if;
end loop;
end if;
when others =>
end case;
-- register write
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(7 downto 6) is
when "00" =>
case apbi.paddr(4 downto 2) is
when "000" => v.ilevel := apbi.pwdata(15 downto 1);
when "001" => v.ipend := apbi.pwdata(15 downto 1);
if eirq /= 0 then v2.ipend := apbi.pwdata(31 downto 16); end if;
when "010" => v.iforce(0) := apbi.pwdata(15 downto 1);
when "011" => v.ipend := r.ipend and not apbi.pwdata(15 downto 1);
if eirq /= 0 then v2.ipend := r2.ipend and not apbi.pwdata(31 downto 16); end if;
when "100" =>
for i in 0 to ncpu -1 loop v.cpurst(i) := apbi.pwdata(i); end loop;
when others =>
if ncpu > 1 then
case apbi.paddr(4 downto 2) is
when "101" =>
v.ibroadcast := apbi.pwdata(15 downto 1);
when others =>
end case;
end if;
end case;
when "01" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
v.imask(i) := apbi.pwdata(15 downto 1);
if eirq /= 0 then v2.imask(i) := apbi.pwdata(31 downto 16); end if;
end if;
end loop;
when "10" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
v.iforce(i) := (r.iforce(i) or apbi.pwdata(15 downto 1)) and
not apbi.pwdata(31 downto 17);
end if;
end loop;
when others =>
end case;
end if;
-- register new interrupts
for i in 1 to 15 loop
if i > NAHBIRQ-1 then
exit;
end if;
if ncpu = 1 then
v.ipend(i) := v.ipend(i) or apbi.pirq(i);
else
v.ipend(i) := v.ipend(i) or (apbi.pirq(i) and not r.ibroadcast(i));
for j in 0 to ncpu-1 loop
tmpvar := v.iforce(j);
tmpvar(i) := tmpvar(i) or (apbi.pirq(i) and r.ibroadcast(i));
v.iforce(j) := tmpvar;
end loop;
end if;
end loop;
if eirq /= 0 then
for i in 16 to 31 loop
if i > NAHBIRQ-1 then exit; end if;
v2.ipend(i-16) := v2.ipend(i-16) or apbi.pirq(i);
end loop;
end if;
-- interrupt acknowledge
for i in 0 to ncpu-1 loop
if irqi(i).intack = '1' then
tmpirq := decode(irqi(i).irl);
temp(i) := tmpirq(15 downto 1);
v.iforce(i) := v.iforce(i) and not temp(i);
v.ipend := v.ipend and not ((not r.iforce(i)) and temp(i));
if eirq /= 0 then
if eirq = conv_integer(irqi(i).irl) then
v2.irl(i) := orv(temp2(i)) & prioritize(temp2(i));
if v2.irl(i)(4) = '1' then
v2.ipend(conv_integer(v2.irl(i)(3 downto 0))) := '0';
end if;
end if;
end if;
end if;
end loop;
-- reset
if (not RESET_ALL) and (rst = '0') then
v.imask := RRES.imask; v.iforce := RRES.iforce; v.ipend := RRES.ipend;
if ncpu > 1 then
v.ibroadcast := RRES.ibroadcast;
end if;
v2.ipend := ERES.ipend; v2.imask := ERES.imask; v2.irl := ERES.irl;
end if;
apbo.prdata <= prdata;
for i in 0 to ncpu-1 loop
irqo(i).irl <= r.irl(i); irqo(i).rst <= r.cpurst(i);
irqo(i).run <= cpurun(i);
irqo(i).rstvec <= (others => '0'); -- Alternate reset vector
irqo(i).iact <= '0';
irqo(i).index <= conv_std_logic_vector(i, 4);
irqo(i).hrdrst <= '0';
end loop;
rin <= v; r2in <= v2;
end process;
apbo.pirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and (rst = '0') then r <= RRES; end if;
end if;
end process;
dor2regs : if eirq /= 0 generate
regs : process(clk)
begin
if rising_edge(clk) then
r2 <= r2in;
if RESET_ALL and (rst = '0') then r2 <= ERES; end if;
end if;
end process;
end generate;
nor2regs : if eirq = 0 generate
-- r2 <= ((others => "0000000000000000"), "0000000000000000", (others => "00000"));
r2.ipend <= (others => '0');
driveregs: for i in 0 to (ncpu-1) generate
r2.imask(i) <= (others => '0');
r2.irl(i) <= (others => '0');
end generate driveregs;
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("irqmp" &
": Multi-processor Interrupt Controller rev " & tost(REVISION) &
", #cpu " & tost(NCPU) & ", eirq " & tost(eirq));
-- pragma translate_on
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AXIinterfacefor65816_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 7
);
port (
-- Users to add ports here
clk : in std_logic;
tru_clk: in std_logic;
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end AXIinterfacefor65816_v1_0;
architecture arch_imp of AXIinterfacefor65816_v1_0 is
-- component declaration
component AXIinterfacefor65816_v1_0_S00_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 7
);
port (
clk : in std_logic;
tru_clk: in std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component AXIinterfacefor65816_v1_0_S00_AXI;
begin
-- Instantiation of Axi Bus Interface S00_AXI
AXIinterfacefor65816_v1_0_S00_AXI_inst : AXIinterfacefor65816_v1_0_S00_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
clk => clk,
tru_clk => tru_clk,
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWPROT => s00_axi_awprot,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARPROT => s00_axi_arprot,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
|
entity FIFO is
generic (
G_WIDTH : natural := 16
);
port (
I_DATA : in std_logic_vector(G_WIDTH - 1 downto 0);
O_DATA : in std_logic_vector(g_width - 1 downto 0)
);
end entity;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.cpu86pack.ALL;
USE work.cpu86instr.ALL;
ENTITY biufsm IS
PORT(
clk : IN std_logic;
flush_coming : IN std_logic;
flush_req : IN std_logic;
irq_req : IN std_logic;
irq_type : IN std_logic_vector (1 DOWNTO 0);
opc_req : IN std_logic;
read_req : IN std_logic;
reg1freed : IN std_logic; -- Delayed version (1 clk) of reg1free
reg4free : IN std_logic;
regnbok : IN std_logic;
reset : IN std_logic;
w_biufsm_s : IN std_logic;
write_req : IN std_logic;
addrplus4 : OUT std_logic;
biu_error : OUT std_logic;
biu_status : OUT std_logic_vector (2 DOWNTO 0);
irq_ack : OUT std_logic;
irq_clr : OUT std_logic;
latchabus : OUT std_logic;
latchclr : OUT std_logic;
latchm : OUT std_logic;
latcho : OUT std_logic;
latchrw : OUT std_logic;
ldposplus1 : OUT std_logic;
muxabus : OUT std_logic_vector (1 DOWNTO 0);
rdcode_s : OUT std_logic;
rddata_s : OUT std_logic;
regplus1 : OUT std_logic;
rw_ack : OUT std_logic;
wr_s : OUT std_logic;
flush_ack : BUFFER std_logic;
inta1 : BUFFER std_logic
);
END biufsm ;
ARCHITECTURE fsm OF biufsm IS
signal ws_s : std_logic_vector(WS_WIDTH-1 downto 0);
signal oddflag_s : std_logic;
signal rwmem3_s : std_logic; -- Misaligned Read/Write cycle
TYPE STATE_TYPE IS (
Sreset,
Sws,
Smaxws,
Sack,
Srdopc,
Serror,
Swrite,
Swsw,
Smaxwsw,
Sackw,
Swrodd,
Sread,
Srdodd,
Swsr,
Smaxwsr,
Sackr,
Sflush1,
Sfull,
Sint,
Sintws2,
Sflush2,
Sintws1
);
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;
SIGNAL biu_error_int : std_logic ;
SIGNAL biu_status_cld : std_logic_vector (2 DOWNTO 0);
BEGIN
clocked_proc : PROCESS (clk,reset)
BEGIN
IF (reset = '1') THEN
current_state <= Sreset;
biu_error <= '0';
biu_status_cld <= "011";
oddflag_s <= '0';
ws_s <= (others=>'0');
ELSIF (clk'EVENT AND clk = '1') THEN
current_state <= next_state;
biu_error <= biu_error_int;
ws_s <= (others=>'0');
CASE current_state IS
WHEN Sreset =>
biu_status_cld<="000";
WHEN Sws =>
ws_s <= ws_s + '1';
IF (flush_req = '1') THEN
biu_status_cld<="011";
END IF;
WHEN Smaxws =>
IF (flush_req = '1') THEN
biu_status_cld<="011";
END IF;
WHEN Sack =>
oddflag_s<='0';
IF (write_req = '1') THEN
biu_status_cld<="010";
ELSIF (read_req = '1') THEN
biu_status_cld<="001";
ELSIF (flush_req = '1') THEN
biu_status_cld<="011";
ELSIF (irq_req='1' AND opc_req='1') THEN
biu_status_cld<="100";
ELSIF (reg4free = '1' AND
flush_coming='0' AND
irq_req='0') THEN
biu_status_cld<="000";
ELSIF (regnbok = '0' and
reg4free = '0') THEN
ELSE
biu_status_cld<="011";
END IF;
WHEN Srdopc =>
ws_s <= (others=>'0');
IF (flush_req = '1') THEN
biu_status_cld<="011";
END IF;
WHEN Swrite =>
ws_s <= (others=>'0');
oddflag_s<='0';
WHEN Swsw =>
ws_s <= ws_s + '1';
WHEN Sackw =>
IF (rwmem3_s = '1') THEN
ELSIF (flush_req = '1') THEN
biu_status_cld<="011";
ELSIF (irq_req='1' AND opc_req='1') THEN
biu_status_cld<="100";
ELSIF (reg4free = '1' ) THEN
biu_status_cld<="000";
ELSIF (flush_coming='1' OR
(irq_req='1' AND opc_req='0')) THEN
biu_status_cld<="011";
END IF;
WHEN Swrodd =>
ws_s <= (others=>'0');
oddflag_s<='1';
WHEN Sread =>
ws_s <= (others=>'0');
oddflag_s<='0';
WHEN Srdodd =>
ws_s <= (others=>'0');
oddflag_s<='1';
WHEN Swsr =>
ws_s <= ws_s + '1';
WHEN Sackr =>
IF (rwmem3_s = '1') THEN
ELSIF (flush_req='1') THEN
biu_status_cld<="011";
ELSIF (irq_req='1' AND opc_req='1') THEN
biu_status_cld<="100";
ELSIF (reg4free = '1' ) THEN
biu_status_cld<="000";
ELSIF (flush_coming='1' OR
(irq_req='1' AND opc_req='0')) THEN
biu_status_cld<="011";
END IF;
WHEN Sfull =>
IF (write_req='1') THEN
biu_status_cld<="010";
ELSIF (read_req='1') THEN
biu_status_cld<="001";
ELSIF (flush_req = '1') THEN
biu_status_cld<="011";
ELSIF (irq_req='1' AND opc_req='1') THEN
biu_status_cld<="100";
ELSIF (reg4free = '1' AND
flush_coming='0' AND
irq_req='0') THEN
biu_status_cld<="000";
END IF;
WHEN Sintws2 =>
biu_status_cld<="011";
WHEN Sflush2 =>
biu_status_cld<="000";
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END PROCESS clocked_proc;
-----------------------------------------------------------------
nextstate_proc : PROCESS (
current_state,
flush_coming,
flush_req,
irq_req,
irq_type,
opc_req,
read_req,
reg1freed,
reg4free,
regnbok,
rwmem3_s,
write_req,
ws_s
)
-----------------------------------------------------------------
BEGIN
-- Default Assignment
addrplus4 <= '0';
biu_error_int <= '0';
irq_ack <= '0';
irq_clr <= '0';
latchabus <= '0';
latchclr <= '0';
latchm <= '0';
latcho <= '0';
latchrw <= '0';
ldposplus1 <= '0';
muxabus <= "00";
rdcode_s <= '0';
rddata_s <= '0';
regplus1 <= '0';
rw_ack <= '0';
wr_s <= '0';
flush_ack <= '0';
inta1 <= '0';
-- Combined Actions
CASE current_state IS
WHEN Sreset =>
latchrw <= '1' ;
next_state <= Srdopc;
WHEN Sws =>
IF (flush_req = '1') THEN
next_state <= Sflush1;
ELSIF (ws_s=MAX_WS-1) THEN
next_state <= Smaxws;
ELSE
next_state <= Sws;
END IF;
WHEN Smaxws =>
latchabus<='1';
addrplus4<='1';
latchclr <= '1' ;
ldposplus1<='1';
IF (flush_req = '1') THEN
next_state <= Sflush1;
ELSE
next_state <= Sack;
END IF;
WHEN Sack =>
latchm<=reg1freed;
regplus1<='1';
IF (write_req = '1') THEN
muxabus <="01";
latchrw <= '1' ;
next_state <= Swrite;
ELSIF (read_req = '1') THEN
muxabus <="01";
latchrw <= '1' ;
next_state <= Sread;
ELSIF (flush_req = '1') THEN
next_state <= Sflush1;
ELSIF (irq_req='1' AND opc_req='1') THEN
irq_ack<='1';
next_state <= Sint;
ELSIF (reg4free = '1' AND
flush_coming='0' AND
irq_req='0') THEN
latchrw <= '1' ;
next_state <= Srdopc;
ELSIF (regnbok = '0' and
reg4free = '0') THEN
next_state <= Serror;
ELSE
next_state <= Sfull;
END IF;
WHEN Srdopc =>
rdcode_s <= '1';
latcho <= regnbok and opc_req;
IF (flush_req = '1') THEN
next_state <= Sflush1;
ELSIF (ws_s/=MAX_WS) THEN
next_state <= Sws;
ELSE
next_state <= Smaxws;
END IF;
WHEN Serror =>
biu_error_int <= '1';
next_state <= Serror;
WHEN Swrite =>
wr_s <= '1';
IF (ws_s/=MAX_WS) THEN
next_state <= Swsw;
ELSE
next_state <= Smaxwsw;
END IF;
WHEN Swsw =>
latcho <= regnbok and opc_req;
IF (ws_s=MAX_WS-1) THEN
next_state <= Smaxwsw;
ELSE
next_state <= Swsw;
END IF;
WHEN Smaxwsw =>
latcho <= regnbok and opc_req;
latchclr <= '1' ;
rw_ack<= not rwmem3_s;
next_state <= Sackw;
WHEN Sackw =>
latcho <= regnbok and opc_req;
IF (rwmem3_s = '1') THEN
muxabus <="10";
latchrw<='1';
next_state <= Swrodd;
ELSIF (flush_req = '1') THEN
next_state <= Sflush1;
ELSIF (irq_req='1' AND opc_req='1') THEN
irq_ack<='1';
next_state <= Sint;
ELSIF (reg4free = '1' ) THEN
muxabus <="00";
latchrw<='1';
next_state <= Srdopc;
ELSIF (flush_coming='1' OR
(irq_req='1' AND opc_req='0')) THEN
next_state <= Sfull;
ELSIF (regnbok = '0' and
reg4free = '0') THEN
next_state <= Serror;
ELSE
muxabus <="00";
next_state <= Sack;
END IF;
WHEN Swrodd =>
latcho <= regnbok and opc_req;
wr_s <= '1';
IF (ws_s/=MAX_WS) THEN
next_state <= Swsw;
ELSE
next_state <= Smaxwsw;
END IF;
WHEN Sread =>
rddata_s <= '1';
IF (ws_s/=MAX_WS) THEN
next_state <= Swsr;
ELSE
next_state <= Smaxwsr;
END IF;
WHEN Srdodd =>
rddata_s <= '1';
IF (ws_s/=MAX_WS) THEN
next_state <= Swsr;
ELSE
next_state <= Smaxwsr;
END IF;
WHEN Swsr =>
IF (ws_s=MAX_WS-1) THEN
next_state <= Smaxwsr;
ELSE
next_state <= Swsr;
END IF;
WHEN Smaxwsr =>
latchclr <= '1' ;
rw_ack<= not rwmem3_s;
next_state <= Sackr;
WHEN Sackr =>
IF (rwmem3_s = '1') THEN
muxabus <="10";
latchrw <= '1';
next_state <= Srdodd;
ELSIF (flush_req='1') THEN
next_state <= Sflush1;
ELSIF (irq_req='1' AND opc_req='1') THEN
irq_ack<='1';
next_state <= Sint;
ELSIF (reg4free = '1' ) THEN
muxabus <="00";
latchrw<='1';
next_state <= Srdopc;
ELSIF (flush_coming='1' OR
(irq_req='1' AND opc_req='0')) THEN
next_state <= Sfull;
ELSIF (regnbok = '0' and
reg4free = '0') THEN
next_state <= Serror;
ELSE
muxabus <="00";
next_state <= Sack;
END IF;
WHEN Sflush1 =>
flush_ack<='1';
IF (flush_req='0') THEN
muxabus<="01";
next_state <= Sflush2;
ELSE
next_state <= Sflush1;
END IF;
WHEN Sfull =>
latcho <= regnbok and opc_req;
IF (write_req='1') THEN
muxabus <="01";
latchrw <= '1' ;
next_state <= Swrite;
ELSIF (read_req='1') THEN
muxabus <="01";
latchrw <= '1' ;
next_state <= Sread;
ELSIF (flush_req = '1') THEN
next_state <= Sflush1;
ELSIF (irq_req='1' AND opc_req='1') THEN
irq_ack<='1';
next_state <= Sint;
ELSIF (reg4free = '1' AND
flush_coming='0' AND
irq_req='0') THEN
latchrw <= '1' ;
next_state <= Srdopc;
ELSIF (regnbok = '0' and
reg4free = '0') THEN
next_state <= Serror;
ELSE
next_state <= Sfull;
END IF;
WHEN Sint =>
latcho <= opc_req;
if irq_type="00" then inta1<='1';
end if;
irq_ack<='1';
next_state <= Sintws1;
WHEN Sintws2 =>
if irq_type="00" then
inta1<='1';
end if;
irq_clr <= '1';
next_state <= Sfull;
WHEN Sflush2 =>
latchabus<='1';
addrplus4<='0';
latchrw <= '1' ;
muxabus <="01";
next_state <= Srdopc;
WHEN Sintws1 =>
if irq_type="00" then
inta1<='1';
end if;
next_state <= Sintws2;
WHEN OTHERS =>
next_state <= Sreset;
END CASE;
END PROCESS nextstate_proc;
biu_status <= biu_status_cld;
rwmem3_s <= '1' when (w_biufsm_s='1' and oddflag_s='0') else '0';
END fsm;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.cpu86pack.ALL;
USE work.cpu86instr.ALL;
ENTITY biufsm IS
PORT(
clk : IN std_logic;
flush_coming : IN std_logic;
flush_req : IN std_logic;
irq_req : IN std_logic;
irq_type : IN std_logic_vector (1 DOWNTO 0);
opc_req : IN std_logic;
read_req : IN std_logic;
reg1freed : IN std_logic; -- Delayed version (1 clk) of reg1free
reg4free : IN std_logic;
regnbok : IN std_logic;
reset : IN std_logic;
w_biufsm_s : IN std_logic;
write_req : IN std_logic;
addrplus4 : OUT std_logic;
biu_error : OUT std_logic;
biu_status : OUT std_logic_vector (2 DOWNTO 0);
irq_ack : OUT std_logic;
irq_clr : OUT std_logic;
latchabus : OUT std_logic;
latchclr : OUT std_logic;
latchm : OUT std_logic;
latcho : OUT std_logic;
latchrw : OUT std_logic;
ldposplus1 : OUT std_logic;
muxabus : OUT std_logic_vector (1 DOWNTO 0);
rdcode_s : OUT std_logic;
rddata_s : OUT std_logic;
regplus1 : OUT std_logic;
rw_ack : OUT std_logic;
wr_s : OUT std_logic;
flush_ack : BUFFER std_logic;
inta1 : BUFFER std_logic
);
END biufsm ;
ARCHITECTURE fsm OF biufsm IS
signal ws_s : std_logic_vector(WS_WIDTH-1 downto 0);
signal oddflag_s : std_logic;
signal rwmem3_s : std_logic; -- Misaligned Read/Write cycle
TYPE STATE_TYPE IS (
Sreset,
Sws,
Smaxws,
Sack,
Srdopc,
Serror,
Swrite,
Swsw,
Smaxwsw,
Sackw,
Swrodd,
Sread,
Srdodd,
Swsr,
Smaxwsr,
Sackr,
Sflush1,
Sfull,
Sint,
Sintws2,
Sflush2,
Sintws1
);
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;
SIGNAL biu_error_int : std_logic ;
SIGNAL biu_status_cld : std_logic_vector (2 DOWNTO 0);
BEGIN
clocked_proc : PROCESS (clk,reset)
BEGIN
IF (reset = '1') THEN
current_state <= Sreset;
biu_error <= '0';
biu_status_cld <= "011";
oddflag_s <= '0';
ws_s <= (others=>'0');
ELSIF (clk'EVENT AND clk = '1') THEN
current_state <= next_state;
biu_error <= biu_error_int;
ws_s <= (others=>'0');
CASE current_state IS
WHEN Sreset =>
biu_status_cld<="000";
WHEN Sws =>
ws_s <= ws_s + '1';
IF (flush_req = '1') THEN
biu_status_cld<="011";
END IF;
WHEN Smaxws =>
IF (flush_req = '1') THEN
biu_status_cld<="011";
END IF;
WHEN Sack =>
oddflag_s<='0';
IF (write_req = '1') THEN
biu_status_cld<="010";
ELSIF (read_req = '1') THEN
biu_status_cld<="001";
ELSIF (flush_req = '1') THEN
biu_status_cld<="011";
ELSIF (irq_req='1' AND opc_req='1') THEN
biu_status_cld<="100";
ELSIF (reg4free = '1' AND
flush_coming='0' AND
irq_req='0') THEN
biu_status_cld<="000";
ELSIF (regnbok = '0' and
reg4free = '0') THEN
ELSE
biu_status_cld<="011";
END IF;
WHEN Srdopc =>
ws_s <= (others=>'0');
IF (flush_req = '1') THEN
biu_status_cld<="011";
END IF;
WHEN Swrite =>
ws_s <= (others=>'0');
oddflag_s<='0';
WHEN Swsw =>
ws_s <= ws_s + '1';
WHEN Sackw =>
IF (rwmem3_s = '1') THEN
ELSIF (flush_req = '1') THEN
biu_status_cld<="011";
ELSIF (irq_req='1' AND opc_req='1') THEN
biu_status_cld<="100";
ELSIF (reg4free = '1' ) THEN
biu_status_cld<="000";
ELSIF (flush_coming='1' OR
(irq_req='1' AND opc_req='0')) THEN
biu_status_cld<="011";
END IF;
WHEN Swrodd =>
ws_s <= (others=>'0');
oddflag_s<='1';
WHEN Sread =>
ws_s <= (others=>'0');
oddflag_s<='0';
WHEN Srdodd =>
ws_s <= (others=>'0');
oddflag_s<='1';
WHEN Swsr =>
ws_s <= ws_s + '1';
WHEN Sackr =>
IF (rwmem3_s = '1') THEN
ELSIF (flush_req='1') THEN
biu_status_cld<="011";
ELSIF (irq_req='1' AND opc_req='1') THEN
biu_status_cld<="100";
ELSIF (reg4free = '1' ) THEN
biu_status_cld<="000";
ELSIF (flush_coming='1' OR
(irq_req='1' AND opc_req='0')) THEN
biu_status_cld<="011";
END IF;
WHEN Sfull =>
IF (write_req='1') THEN
biu_status_cld<="010";
ELSIF (read_req='1') THEN
biu_status_cld<="001";
ELSIF (flush_req = '1') THEN
biu_status_cld<="011";
ELSIF (irq_req='1' AND opc_req='1') THEN
biu_status_cld<="100";
ELSIF (reg4free = '1' AND
flush_coming='0' AND
irq_req='0') THEN
biu_status_cld<="000";
END IF;
WHEN Sintws2 =>
biu_status_cld<="011";
WHEN Sflush2 =>
biu_status_cld<="000";
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END PROCESS clocked_proc;
-----------------------------------------------------------------
nextstate_proc : PROCESS (
current_state,
flush_coming,
flush_req,
irq_req,
irq_type,
opc_req,
read_req,
reg1freed,
reg4free,
regnbok,
rwmem3_s,
write_req,
ws_s
)
-----------------------------------------------------------------
BEGIN
-- Default Assignment
addrplus4 <= '0';
biu_error_int <= '0';
irq_ack <= '0';
irq_clr <= '0';
latchabus <= '0';
latchclr <= '0';
latchm <= '0';
latcho <= '0';
latchrw <= '0';
ldposplus1 <= '0';
muxabus <= "00";
rdcode_s <= '0';
rddata_s <= '0';
regplus1 <= '0';
rw_ack <= '0';
wr_s <= '0';
flush_ack <= '0';
inta1 <= '0';
-- Combined Actions
CASE current_state IS
WHEN Sreset =>
latchrw <= '1' ;
next_state <= Srdopc;
WHEN Sws =>
IF (flush_req = '1') THEN
next_state <= Sflush1;
ELSIF (ws_s=MAX_WS-1) THEN
next_state <= Smaxws;
ELSE
next_state <= Sws;
END IF;
WHEN Smaxws =>
latchabus<='1';
addrplus4<='1';
latchclr <= '1' ;
ldposplus1<='1';
IF (flush_req = '1') THEN
next_state <= Sflush1;
ELSE
next_state <= Sack;
END IF;
WHEN Sack =>
latchm<=reg1freed;
regplus1<='1';
IF (write_req = '1') THEN
muxabus <="01";
latchrw <= '1' ;
next_state <= Swrite;
ELSIF (read_req = '1') THEN
muxabus <="01";
latchrw <= '1' ;
next_state <= Sread;
ELSIF (flush_req = '1') THEN
next_state <= Sflush1;
ELSIF (irq_req='1' AND opc_req='1') THEN
irq_ack<='1';
next_state <= Sint;
ELSIF (reg4free = '1' AND
flush_coming='0' AND
irq_req='0') THEN
latchrw <= '1' ;
next_state <= Srdopc;
ELSIF (regnbok = '0' and
reg4free = '0') THEN
next_state <= Serror;
ELSE
next_state <= Sfull;
END IF;
WHEN Srdopc =>
rdcode_s <= '1';
latcho <= regnbok and opc_req;
IF (flush_req = '1') THEN
next_state <= Sflush1;
ELSIF (ws_s/=MAX_WS) THEN
next_state <= Sws;
ELSE
next_state <= Smaxws;
END IF;
WHEN Serror =>
biu_error_int <= '1';
next_state <= Serror;
WHEN Swrite =>
wr_s <= '1';
IF (ws_s/=MAX_WS) THEN
next_state <= Swsw;
ELSE
next_state <= Smaxwsw;
END IF;
WHEN Swsw =>
latcho <= regnbok and opc_req;
IF (ws_s=MAX_WS-1) THEN
next_state <= Smaxwsw;
ELSE
next_state <= Swsw;
END IF;
WHEN Smaxwsw =>
latcho <= regnbok and opc_req;
latchclr <= '1' ;
rw_ack<= not rwmem3_s;
next_state <= Sackw;
WHEN Sackw =>
latcho <= regnbok and opc_req;
IF (rwmem3_s = '1') THEN
muxabus <="10";
latchrw<='1';
next_state <= Swrodd;
ELSIF (flush_req = '1') THEN
next_state <= Sflush1;
ELSIF (irq_req='1' AND opc_req='1') THEN
irq_ack<='1';
next_state <= Sint;
ELSIF (reg4free = '1' ) THEN
muxabus <="00";
latchrw<='1';
next_state <= Srdopc;
ELSIF (flush_coming='1' OR
(irq_req='1' AND opc_req='0')) THEN
next_state <= Sfull;
ELSIF (regnbok = '0' and
reg4free = '0') THEN
next_state <= Serror;
ELSE
muxabus <="00";
next_state <= Sack;
END IF;
WHEN Swrodd =>
latcho <= regnbok and opc_req;
wr_s <= '1';
IF (ws_s/=MAX_WS) THEN
next_state <= Swsw;
ELSE
next_state <= Smaxwsw;
END IF;
WHEN Sread =>
rddata_s <= '1';
IF (ws_s/=MAX_WS) THEN
next_state <= Swsr;
ELSE
next_state <= Smaxwsr;
END IF;
WHEN Srdodd =>
rddata_s <= '1';
IF (ws_s/=MAX_WS) THEN
next_state <= Swsr;
ELSE
next_state <= Smaxwsr;
END IF;
WHEN Swsr =>
IF (ws_s=MAX_WS-1) THEN
next_state <= Smaxwsr;
ELSE
next_state <= Swsr;
END IF;
WHEN Smaxwsr =>
latchclr <= '1' ;
rw_ack<= not rwmem3_s;
next_state <= Sackr;
WHEN Sackr =>
IF (rwmem3_s = '1') THEN
muxabus <="10";
latchrw <= '1';
next_state <= Srdodd;
ELSIF (flush_req='1') THEN
next_state <= Sflush1;
ELSIF (irq_req='1' AND opc_req='1') THEN
irq_ack<='1';
next_state <= Sint;
ELSIF (reg4free = '1' ) THEN
muxabus <="00";
latchrw<='1';
next_state <= Srdopc;
ELSIF (flush_coming='1' OR
(irq_req='1' AND opc_req='0')) THEN
next_state <= Sfull;
ELSIF (regnbok = '0' and
reg4free = '0') THEN
next_state <= Serror;
ELSE
muxabus <="00";
next_state <= Sack;
END IF;
WHEN Sflush1 =>
flush_ack<='1';
IF (flush_req='0') THEN
muxabus<="01";
next_state <= Sflush2;
ELSE
next_state <= Sflush1;
END IF;
WHEN Sfull =>
latcho <= regnbok and opc_req;
IF (write_req='1') THEN
muxabus <="01";
latchrw <= '1' ;
next_state <= Swrite;
ELSIF (read_req='1') THEN
muxabus <="01";
latchrw <= '1' ;
next_state <= Sread;
ELSIF (flush_req = '1') THEN
next_state <= Sflush1;
ELSIF (irq_req='1' AND opc_req='1') THEN
irq_ack<='1';
next_state <= Sint;
ELSIF (reg4free = '1' AND
flush_coming='0' AND
irq_req='0') THEN
latchrw <= '1' ;
next_state <= Srdopc;
ELSIF (regnbok = '0' and
reg4free = '0') THEN
next_state <= Serror;
ELSE
next_state <= Sfull;
END IF;
WHEN Sint =>
latcho <= opc_req;
if irq_type="00" then inta1<='1';
end if;
irq_ack<='1';
next_state <= Sintws1;
WHEN Sintws2 =>
if irq_type="00" then
inta1<='1';
end if;
irq_clr <= '1';
next_state <= Sfull;
WHEN Sflush2 =>
latchabus<='1';
addrplus4<='0';
latchrw <= '1' ;
muxabus <="01";
next_state <= Srdopc;
WHEN Sintws1 =>
if irq_type="00" then
inta1<='1';
end if;
next_state <= Sintws2;
WHEN OTHERS =>
next_state <= Sreset;
END CASE;
END PROCESS nextstate_proc;
biu_status <= biu_status_cld;
rwmem3_s <= '1' when (w_biufsm_s='1' and oddflag_s='0') else '0';
END fsm;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.cpu86pack.ALL;
USE work.cpu86instr.ALL;
ENTITY biufsm IS
PORT(
clk : IN std_logic;
flush_coming : IN std_logic;
flush_req : IN std_logic;
irq_req : IN std_logic;
irq_type : IN std_logic_vector (1 DOWNTO 0);
opc_req : IN std_logic;
read_req : IN std_logic;
reg1freed : IN std_logic; -- Delayed version (1 clk) of reg1free
reg4free : IN std_logic;
regnbok : IN std_logic;
reset : IN std_logic;
w_biufsm_s : IN std_logic;
write_req : IN std_logic;
addrplus4 : OUT std_logic;
biu_error : OUT std_logic;
biu_status : OUT std_logic_vector (2 DOWNTO 0);
irq_ack : OUT std_logic;
irq_clr : OUT std_logic;
latchabus : OUT std_logic;
latchclr : OUT std_logic;
latchm : OUT std_logic;
latcho : OUT std_logic;
latchrw : OUT std_logic;
ldposplus1 : OUT std_logic;
muxabus : OUT std_logic_vector (1 DOWNTO 0);
rdcode_s : OUT std_logic;
rddata_s : OUT std_logic;
regplus1 : OUT std_logic;
rw_ack : OUT std_logic;
wr_s : OUT std_logic;
flush_ack : BUFFER std_logic;
inta1 : BUFFER std_logic
);
END biufsm ;
ARCHITECTURE fsm OF biufsm IS
signal ws_s : std_logic_vector(WS_WIDTH-1 downto 0);
signal oddflag_s : std_logic;
signal rwmem3_s : std_logic; -- Misaligned Read/Write cycle
TYPE STATE_TYPE IS (
Sreset,
Sws,
Smaxws,
Sack,
Srdopc,
Serror,
Swrite,
Swsw,
Smaxwsw,
Sackw,
Swrodd,
Sread,
Srdodd,
Swsr,
Smaxwsr,
Sackr,
Sflush1,
Sfull,
Sint,
Sintws2,
Sflush2,
Sintws1
);
SIGNAL current_state : STATE_TYPE;
SIGNAL next_state : STATE_TYPE;
SIGNAL biu_error_int : std_logic ;
SIGNAL biu_status_cld : std_logic_vector (2 DOWNTO 0);
BEGIN
clocked_proc : PROCESS (clk,reset)
BEGIN
IF (reset = '1') THEN
current_state <= Sreset;
biu_error <= '0';
biu_status_cld <= "011";
oddflag_s <= '0';
ws_s <= (others=>'0');
ELSIF (clk'EVENT AND clk = '1') THEN
current_state <= next_state;
biu_error <= biu_error_int;
ws_s <= (others=>'0');
CASE current_state IS
WHEN Sreset =>
biu_status_cld<="000";
WHEN Sws =>
ws_s <= ws_s + '1';
IF (flush_req = '1') THEN
biu_status_cld<="011";
END IF;
WHEN Smaxws =>
IF (flush_req = '1') THEN
biu_status_cld<="011";
END IF;
WHEN Sack =>
oddflag_s<='0';
IF (write_req = '1') THEN
biu_status_cld<="010";
ELSIF (read_req = '1') THEN
biu_status_cld<="001";
ELSIF (flush_req = '1') THEN
biu_status_cld<="011";
ELSIF (irq_req='1' AND opc_req='1') THEN
biu_status_cld<="100";
ELSIF (reg4free = '1' AND
flush_coming='0' AND
irq_req='0') THEN
biu_status_cld<="000";
ELSIF (regnbok = '0' and
reg4free = '0') THEN
ELSE
biu_status_cld<="011";
END IF;
WHEN Srdopc =>
ws_s <= (others=>'0');
IF (flush_req = '1') THEN
biu_status_cld<="011";
END IF;
WHEN Swrite =>
ws_s <= (others=>'0');
oddflag_s<='0';
WHEN Swsw =>
ws_s <= ws_s + '1';
WHEN Sackw =>
IF (rwmem3_s = '1') THEN
ELSIF (flush_req = '1') THEN
biu_status_cld<="011";
ELSIF (irq_req='1' AND opc_req='1') THEN
biu_status_cld<="100";
ELSIF (reg4free = '1' ) THEN
biu_status_cld<="000";
ELSIF (flush_coming='1' OR
(irq_req='1' AND opc_req='0')) THEN
biu_status_cld<="011";
END IF;
WHEN Swrodd =>
ws_s <= (others=>'0');
oddflag_s<='1';
WHEN Sread =>
ws_s <= (others=>'0');
oddflag_s<='0';
WHEN Srdodd =>
ws_s <= (others=>'0');
oddflag_s<='1';
WHEN Swsr =>
ws_s <= ws_s + '1';
WHEN Sackr =>
IF (rwmem3_s = '1') THEN
ELSIF (flush_req='1') THEN
biu_status_cld<="011";
ELSIF (irq_req='1' AND opc_req='1') THEN
biu_status_cld<="100";
ELSIF (reg4free = '1' ) THEN
biu_status_cld<="000";
ELSIF (flush_coming='1' OR
(irq_req='1' AND opc_req='0')) THEN
biu_status_cld<="011";
END IF;
WHEN Sfull =>
IF (write_req='1') THEN
biu_status_cld<="010";
ELSIF (read_req='1') THEN
biu_status_cld<="001";
ELSIF (flush_req = '1') THEN
biu_status_cld<="011";
ELSIF (irq_req='1' AND opc_req='1') THEN
biu_status_cld<="100";
ELSIF (reg4free = '1' AND
flush_coming='0' AND
irq_req='0') THEN
biu_status_cld<="000";
END IF;
WHEN Sintws2 =>
biu_status_cld<="011";
WHEN Sflush2 =>
biu_status_cld<="000";
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END PROCESS clocked_proc;
-----------------------------------------------------------------
nextstate_proc : PROCESS (
current_state,
flush_coming,
flush_req,
irq_req,
irq_type,
opc_req,
read_req,
reg1freed,
reg4free,
regnbok,
rwmem3_s,
write_req,
ws_s
)
-----------------------------------------------------------------
BEGIN
-- Default Assignment
addrplus4 <= '0';
biu_error_int <= '0';
irq_ack <= '0';
irq_clr <= '0';
latchabus <= '0';
latchclr <= '0';
latchm <= '0';
latcho <= '0';
latchrw <= '0';
ldposplus1 <= '0';
muxabus <= "00";
rdcode_s <= '0';
rddata_s <= '0';
regplus1 <= '0';
rw_ack <= '0';
wr_s <= '0';
flush_ack <= '0';
inta1 <= '0';
-- Combined Actions
CASE current_state IS
WHEN Sreset =>
latchrw <= '1' ;
next_state <= Srdopc;
WHEN Sws =>
IF (flush_req = '1') THEN
next_state <= Sflush1;
ELSIF (ws_s=MAX_WS-1) THEN
next_state <= Smaxws;
ELSE
next_state <= Sws;
END IF;
WHEN Smaxws =>
latchabus<='1';
addrplus4<='1';
latchclr <= '1' ;
ldposplus1<='1';
IF (flush_req = '1') THEN
next_state <= Sflush1;
ELSE
next_state <= Sack;
END IF;
WHEN Sack =>
latchm<=reg1freed;
regplus1<='1';
IF (write_req = '1') THEN
muxabus <="01";
latchrw <= '1' ;
next_state <= Swrite;
ELSIF (read_req = '1') THEN
muxabus <="01";
latchrw <= '1' ;
next_state <= Sread;
ELSIF (flush_req = '1') THEN
next_state <= Sflush1;
ELSIF (irq_req='1' AND opc_req='1') THEN
irq_ack<='1';
next_state <= Sint;
ELSIF (reg4free = '1' AND
flush_coming='0' AND
irq_req='0') THEN
latchrw <= '1' ;
next_state <= Srdopc;
ELSIF (regnbok = '0' and
reg4free = '0') THEN
next_state <= Serror;
ELSE
next_state <= Sfull;
END IF;
WHEN Srdopc =>
rdcode_s <= '1';
latcho <= regnbok and opc_req;
IF (flush_req = '1') THEN
next_state <= Sflush1;
ELSIF (ws_s/=MAX_WS) THEN
next_state <= Sws;
ELSE
next_state <= Smaxws;
END IF;
WHEN Serror =>
biu_error_int <= '1';
next_state <= Serror;
WHEN Swrite =>
wr_s <= '1';
IF (ws_s/=MAX_WS) THEN
next_state <= Swsw;
ELSE
next_state <= Smaxwsw;
END IF;
WHEN Swsw =>
latcho <= regnbok and opc_req;
IF (ws_s=MAX_WS-1) THEN
next_state <= Smaxwsw;
ELSE
next_state <= Swsw;
END IF;
WHEN Smaxwsw =>
latcho <= regnbok and opc_req;
latchclr <= '1' ;
rw_ack<= not rwmem3_s;
next_state <= Sackw;
WHEN Sackw =>
latcho <= regnbok and opc_req;
IF (rwmem3_s = '1') THEN
muxabus <="10";
latchrw<='1';
next_state <= Swrodd;
ELSIF (flush_req = '1') THEN
next_state <= Sflush1;
ELSIF (irq_req='1' AND opc_req='1') THEN
irq_ack<='1';
next_state <= Sint;
ELSIF (reg4free = '1' ) THEN
muxabus <="00";
latchrw<='1';
next_state <= Srdopc;
ELSIF (flush_coming='1' OR
(irq_req='1' AND opc_req='0')) THEN
next_state <= Sfull;
ELSIF (regnbok = '0' and
reg4free = '0') THEN
next_state <= Serror;
ELSE
muxabus <="00";
next_state <= Sack;
END IF;
WHEN Swrodd =>
latcho <= regnbok and opc_req;
wr_s <= '1';
IF (ws_s/=MAX_WS) THEN
next_state <= Swsw;
ELSE
next_state <= Smaxwsw;
END IF;
WHEN Sread =>
rddata_s <= '1';
IF (ws_s/=MAX_WS) THEN
next_state <= Swsr;
ELSE
next_state <= Smaxwsr;
END IF;
WHEN Srdodd =>
rddata_s <= '1';
IF (ws_s/=MAX_WS) THEN
next_state <= Swsr;
ELSE
next_state <= Smaxwsr;
END IF;
WHEN Swsr =>
IF (ws_s=MAX_WS-1) THEN
next_state <= Smaxwsr;
ELSE
next_state <= Swsr;
END IF;
WHEN Smaxwsr =>
latchclr <= '1' ;
rw_ack<= not rwmem3_s;
next_state <= Sackr;
WHEN Sackr =>
IF (rwmem3_s = '1') THEN
muxabus <="10";
latchrw <= '1';
next_state <= Srdodd;
ELSIF (flush_req='1') THEN
next_state <= Sflush1;
ELSIF (irq_req='1' AND opc_req='1') THEN
irq_ack<='1';
next_state <= Sint;
ELSIF (reg4free = '1' ) THEN
muxabus <="00";
latchrw<='1';
next_state <= Srdopc;
ELSIF (flush_coming='1' OR
(irq_req='1' AND opc_req='0')) THEN
next_state <= Sfull;
ELSIF (regnbok = '0' and
reg4free = '0') THEN
next_state <= Serror;
ELSE
muxabus <="00";
next_state <= Sack;
END IF;
WHEN Sflush1 =>
flush_ack<='1';
IF (flush_req='0') THEN
muxabus<="01";
next_state <= Sflush2;
ELSE
next_state <= Sflush1;
END IF;
WHEN Sfull =>
latcho <= regnbok and opc_req;
IF (write_req='1') THEN
muxabus <="01";
latchrw <= '1' ;
next_state <= Swrite;
ELSIF (read_req='1') THEN
muxabus <="01";
latchrw <= '1' ;
next_state <= Sread;
ELSIF (flush_req = '1') THEN
next_state <= Sflush1;
ELSIF (irq_req='1' AND opc_req='1') THEN
irq_ack<='1';
next_state <= Sint;
ELSIF (reg4free = '1' AND
flush_coming='0' AND
irq_req='0') THEN
latchrw <= '1' ;
next_state <= Srdopc;
ELSIF (regnbok = '0' and
reg4free = '0') THEN
next_state <= Serror;
ELSE
next_state <= Sfull;
END IF;
WHEN Sint =>
latcho <= opc_req;
if irq_type="00" then inta1<='1';
end if;
irq_ack<='1';
next_state <= Sintws1;
WHEN Sintws2 =>
if irq_type="00" then
inta1<='1';
end if;
irq_clr <= '1';
next_state <= Sfull;
WHEN Sflush2 =>
latchabus<='1';
addrplus4<='0';
latchrw <= '1' ;
muxabus <="01";
next_state <= Srdopc;
WHEN Sintws1 =>
if irq_type="00" then
inta1<='1';
end if;
next_state <= Sintws2;
WHEN OTHERS =>
next_state <= Sreset;
END CASE;
END PROCESS nextstate_proc;
biu_status <= biu_status_cld;
rwmem3_s <= '1' when (w_biufsm_s='1' and oddflag_s='0') else '0';
END fsm;
|
---------------------------------------------------------------------------
-- Company : Automaticaly generated by POD
-- Author(s) :
--
-- Creation Date : 2008-10-20
-- File : Top_i2ctest_tb.vhd
--
-- Abstract :
-- insert a description here
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
--
-- Defines communication functions between imx and fpga:
--
-- write procedures
-- procedure imx_write
-- Params :
-- address : Write address
-- value : value to write
-- gls_clk : clock signal
-- imx_cs_n : Chip select
-- imx_oe_n : Read signal
-- imx_eb3_n : Write signal
-- imx_address : Address signal
-- imx_data : Data signal
-- WSC : Value of imx WSC (see MC9328MXLRM.pdf p169) for sync=0
--
-- read procedures
-- procedure imx_read
-- Params :
-- address : Write address
-- value : value returned
-- gls_clk : clock signal
-- imx_cs_n : Chip select
-- imx_oe_n : Read signal
-- imx_eb3_n : Write signal
-- imx_address : Address signal
-- imx_data : Data signal
-- WSC : Value of imx WSC (see MC9328MXLRM.pdf p169) for sync=0
--
use work.apf_test_pkg.all;
entity top_i2ctest_tb is
end entity top_i2ctest_tb;
architecture RTL of top_i2ctest_tb is
CONSTANT HALF_PERIODE : time := 5.20833333333 ns; -- Half clock period
CONSTANT IRQ_MNGR00_IRQ_MNGR_MASK : std_logic_vector := x"0000";
CONSTANT IRQ_MNGR00_IRQ_MNGR_PENDING_ACK : std_logic_vector := x"0002";
CONSTANT IRQ_MNGR00_ID : std_logic_vector := x"0004";
CONSTANT I2C_PRESCLO : std_logic_vector := x"0020";
CONSTANT I2C_PRESCHI : std_logic_vector := x"0022";
CONSTANT I2C_CTR : std_logic_vector := x"0024";
CONSTANT I2C_CR : std_logic_vector := x"0028";
CONSTANT I2C_TXR : std_logic_vector := x"002a";
CONSTANT I2C_SR : std_logic_vector := x"002c";
CONSTANT I2C_RXR : std_logic_vector := x"002e";
CONSTANT I2C_ID : std_logic_vector := x"0030";
-- Values
CONSTANT PRELo : std_logic_vector := x"00BF";
CONSTANT PREHi : std_logic_vector := x"0000";
-- read/write (accelerometer)
CONSTANT ADDR : std_logic_vector := x"001D"; -- lis3lv02dl
CONSTANT SUBADDR : std_logic_vector := x"0016"; -- OFFSET_X
CONSTANT VALUE : std_logic_vector := x"00BB";
--/* irq position in irqmngr */
CONSTANT IRQ : std_logic_vector := x"0001";
--/* CTR register */
CONSTANT I2C_EN : std_logic_vector := x"0080";
CONSTANT I2C_IEN : std_logic_vector := x"0040";
--/* CR register */
CONSTANT I2C_STA : std_logic_vector := x"0080";
CONSTANT I2C_STO : std_logic_vector := x"0040";
CONSTANT I2C_RD : std_logic_vector := x"0020";
CONSTANT I2C_WR : std_logic_vector := x"0010";
CONSTANT I2C_ACK : std_logic_vector := x"0008";
CONSTANT I2C_IACK : std_logic_vector := x"0001";
--/* read/write bit */
CONSTANT I2C_ADD_READ : std_logic := '1';
CONSTANT I2C_ADD_WRITE : std_logic := '0';
-- i2c
signal i2c_scl : std_logic;
signal i2c_sda : std_logic;
-- imx9328
signal imx9328_wb16_wrapper00_imx_address : std_logic_vector(11 downto 0);
signal imx9328_wb16_wrapper00_imx_cs_n : std_logic;
signal imx9328_wb16_wrapper00_imx_data : std_logic_vector(15 downto 0);
signal imx9328_wb16_wrapper00_imx_eb3_n : std_logic;
signal imx9328_wb16_wrapper00_imx_oe_n : std_logic;
-- irq
signal irq_mngr00_gls_irq : std_logic;
-- rstgen
signal rstgen_syscon00_ext_clk : std_logic;
component top_i2ctest
port (
-- i2c
i2c_scl : inout std_logic;
i2c_sda : inout std_logic;
-- imx9328
imx9328_wb16_wrapper00_imx_address : in std_logic_vector(11 downto 0);
imx9328_wb16_wrapper00_imx_cs_n : in std_logic;
imx9328_wb16_wrapper00_imx_data : inout std_logic_vector(15 downto 0);
imx9328_wb16_wrapper00_imx_eb3_n : in std_logic;
imx9328_wb16_wrapper00_imx_oe_n : in std_logic;
-- irq
irq_mngr00_gls_irq : out std_logic;
-- rstgen
rstgen_syscon00_ext_clk : in std_logic
);
end component top_i2ctest;
begin
top : top_i2ctest
port map(
i2c_scl => i2c_scl,
i2c_sda => i2c_sda,
imx9328_wb16_wrapper00_imx_address => imx9328_wb16_wrapper00_imx_address,
imx9328_wb16_wrapper00_imx_cs_n => imx9328_wb16_wrapper00_imx_cs_n,
imx9328_wb16_wrapper00_imx_data => imx9328_wb16_wrapper00_imx_data,
imx9328_wb16_wrapper00_imx_eb3_n => imx9328_wb16_wrapper00_imx_eb3_n,
imx9328_wb16_wrapper00_imx_oe_n => imx9328_wb16_wrapper00_imx_oe_n,
irq_mngr00_gls_irq => irq_mngr00_gls_irq,
rstgen_syscon00_ext_clk => rstgen_syscon00_ext_clk
);
pullup_p : process
begin
i2c_sda <= 'H';
i2c_scl <= 'H';
end process pullup_p;
stimulis : process
begin
imx9328_wb16_wrapper00_imx_address <= (others => '0');
imx9328_wb16_wrapper00_imx_cs_n <= '1';
imx9328_wb16_wrapper00_imx_data <= (others => 'Z');
imx9328_wb16_wrapper00_imx_eb3_n <= '1';
imx9328_wb16_wrapper00_imx_oe_n <= '1';
-- unmask interrupt for i2c in interrupt manager
imx_write(IRQ_MNGR00_IRQ_MNGR_MASK,IRQ,
rstgen_syscon00_ext_clk,imx9328_wb16_wrapper00_imx_cs_n,
imx9328_wb16_wrapper00_imx_oe_n,imx9328_wb16_wrapper00_imx_eb3_n,
imx9328_wb16_wrapper00_imx_address,imx9328_wb16_wrapper00_imx_data,
4);
--/* set prescale */
imx_write(I2C_PRESCLO,PRELo,
rstgen_syscon00_ext_clk,imx9328_wb16_wrapper00_imx_cs_n,
imx9328_wb16_wrapper00_imx_oe_n,imx9328_wb16_wrapper00_imx_eb3_n,
imx9328_wb16_wrapper00_imx_address,imx9328_wb16_wrapper00_imx_data,
4);
imx_write(I2C_PRESCHI,PREHi,
rstgen_syscon00_ext_clk,imx9328_wb16_wrapper00_imx_cs_n,
imx9328_wb16_wrapper00_imx_oe_n,imx9328_wb16_wrapper00_imx_eb3_n,
imx9328_wb16_wrapper00_imx_address,imx9328_wb16_wrapper00_imx_data,
4);
--/* set core enable and interrupt enable*/
imx_write(I2C_CTR,(I2C_EN or I2C_IEN),
rstgen_syscon00_ext_clk,imx9328_wb16_wrapper00_imx_cs_n,
imx9328_wb16_wrapper00_imx_oe_n,imx9328_wb16_wrapper00_imx_eb3_n,
imx9328_wb16_wrapper00_imx_address,imx9328_wb16_wrapper00_imx_data,
4);
--/* write slave adresse on TXR */
imx_write(I2C_TXR,ADDR(14 downto 0)&I2C_ADD_READ,
rstgen_syscon00_ext_clk,imx9328_wb16_wrapper00_imx_cs_n,
imx9328_wb16_wrapper00_imx_oe_n,imx9328_wb16_wrapper00_imx_eb3_n,
imx9328_wb16_wrapper00_imx_address,imx9328_wb16_wrapper00_imx_data,
4);
--/* and CTR register*/
imx_write(I2C_CTR,(I2C_STA or I2C_WR or I2C_IACK),
rstgen_syscon00_ext_clk,imx9328_wb16_wrapper00_imx_cs_n,
imx9328_wb16_wrapper00_imx_oe_n,imx9328_wb16_wrapper00_imx_eb3_n,
imx9328_wb16_wrapper00_imx_address,imx9328_wb16_wrapper00_imx_data,
4);
wait for 10 us;
assert false report "End of test" severity error;
end process stimulis;
clockp : process
begin
rstgen_syscon00_ext_clk <= '1';
wait for HALF_PERIODE;
rstgen_syscon00_ext_clk <= '0';
wait for HALF_PERIODE;
end process clockp;
end architecture RTL;
|
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- twi_master_1.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity twi_master_1 is
port (
addr : in std_logic_vector(1 downto 0) := (others => '0'); -- avalon_slave_0.address
wr_en : in std_logic := '0'; -- .write
out_data : out std_logic_vector(15 downto 0); -- .readdata
byte_en : in std_logic_vector(1 downto 0) := (others => '0'); -- .byteenable
in_data : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
clk : in std_logic := '0'; -- clock.clk
rst : in std_logic := '0'; -- reset_sink.reset
in_octet : in std_logic_vector(7 downto 0) := (others => '0'); -- avalon_streaming_sink.data
in_valid : in std_logic := '0'; -- .valid
in_ready : out std_logic; -- .ready
out_octet : out std_logic_vector(7 downto 0); -- avalon_streaming_source.data
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
scl_in : in std_logic := '0'; -- conduit_end.export
scl_act : out std_logic; -- .export
sda_in : in std_logic := '0'; -- .export
sda_act : out std_logic; -- .export
sink_irq : in std_logic := '0'; -- .export
source_irq : in std_logic := '0'; -- .export
irq : out std_logic -- .export
);
end entity twi_master_1;
architecture rtl of twi_master_1 is
component twi_master is
port (
addr : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
wr_en : in std_logic := 'X'; -- write
out_data : out std_logic_vector(15 downto 0); -- readdata
byte_en : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
in_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
clk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
in_octet : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
out_octet : out std_logic_vector(7 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
scl_in : in std_logic := 'X'; -- export
scl_act : out std_logic; -- export
sda_in : in std_logic := 'X'; -- export
sda_act : out std_logic; -- export
sink_irq : in std_logic := 'X'; -- export
source_irq : in std_logic := 'X'; -- export
irq : out std_logic -- export
);
end component twi_master;
begin
twi_master_1 : component twi_master
port map (
addr => addr, -- avalon_slave_0.address
wr_en => wr_en, -- .write
out_data => out_data, -- .readdata
byte_en => byte_en, -- .byteenable
in_data => in_data, -- .writedata
clk => clk, -- clock.clk
rst => rst, -- reset_sink.reset
in_octet => in_octet, -- avalon_streaming_sink.data
in_valid => in_valid, -- .valid
in_ready => in_ready, -- .ready
out_octet => out_octet, -- avalon_streaming_source.data
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
scl_in => scl_in, -- conduit_end.export
scl_act => scl_act, -- .export
sda_in => sda_in, -- .export
sda_act => sda_act, -- .export
sink_irq => sink_irq, -- .export
source_irq => source_irq, -- .export
irq => irq -- .export
);
end architecture rtl; -- of twi_master_1
|
----- package mem3 -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE mem3 IS
TYPE mem_type_5 IS array (Integer range <>) OF std_logic_vector(17 downto 0);
TYPE mem_type_6 IS array (Integer range <>) OF std_logic_vector(15 downto 0);
FUNCTION hex2bin (hex: character) RETURN std_logic_vector;
FUNCTION str3_slv12 (hex: string) RETURN std_logic_vector;
FUNCTION data2data (data_w: integer) RETURN integer;
FUNCTION data2addr_w (data_w: integer) RETURN integer;
FUNCTION data2data_w (data_w: integer) RETURN integer;
FUNCTION init_ram (hex: string; DATA_WIDTH_A : integer; DATA_WIDTH_B : integer) RETURN std_logic_vector;
FUNCTION init_ram1 (hex: string) RETURN mem_type_6;
FUNCTION str2slv (str: in string) RETURN std_logic_vector;
FUNCTION Valid_Address (IN_ADDR : in std_logic_vector) return boolean;
END mem3;
PACKAGE BODY mem3 IS
FUNCTION hex2bin (hex: character) RETURN std_logic_vector IS
VARIABLE result : std_logic_vector (3 downto 0);
BEGIN
CASE hex IS
WHEN '0' =>
result := "0000";
WHEN '1' =>
result := "0001";
WHEN '2' =>
result := "0010";
WHEN '3' =>
result := "0011";
WHEN '4' =>
result := "0100";
WHEN '5' =>
result := "0101";
WHEN '6' =>
result := "0110";
WHEN '7' =>
result := "0111";
WHEN '8' =>
result := "1000";
WHEN '9' =>
result := "1001";
WHEN 'A'|'a' =>
result := "1010";
WHEN 'B'|'b' =>
result := "1011";
WHEN 'C'|'c' =>
result := "1100";
WHEN 'D'|'d' =>
result := "1101";
WHEN 'E'|'e' =>
result := "1110";
WHEN 'F'|'f' =>
result := "1111";
WHEN 'X'|'x' =>
result := "XXXX";
WHEN others =>
NULL;
END CASE;
RETURN result;
END;
FUNCTION str5_slv18 (s : string(5 downto 1)) return std_logic_vector is
VARIABLE result : std_logic_vector(17 downto 0);
BEGIN
FOR i in 0 to 3 LOOP
result(((i+1)*4)-1 downto (i*4)) := hex2bin(s(i+1));
END LOOP;
result(17 downto 16) := hex2bin(s(5))(1 downto 0);
RETURN result;
END;
FUNCTION str4_slv16 (s : string(4 downto 1)) return std_logic_vector is
VARIABLE result : std_logic_vector(15 downto 0);
BEGIN
FOR i in 0 to 3 LOOP
result(((i+1)*4)-1 downto (i*4)) := hex2bin(s(i+1));
END LOOP;
RETURN result;
END;
FUNCTION str3_slv12 (hex: string) return std_logic_vector is
VARIABLE result : std_logic_vector(11 downto 0);
BEGIN
FOR i in 0 to 2 LOOP
result(((i+1)*4)-1 downto (i*4)) := hex2bin(hex(i+1));
END LOOP;
RETURN result;
END;
FUNCTION data2addr_w (data_w : integer) return integer is
VARIABLE result : integer;
BEGIN
CASE data_w IS
WHEN 1 =>
result := 13;
WHEN 2 =>
result := 12;
WHEN 4 =>
result := 11;
WHEN 9 =>
result := 10;
WHEN 18 =>
result := 9;
WHEN 36 =>
result := 8;
WHEN others =>
NULL;
END CASE;
RETURN result;
END;
FUNCTION data2data_w (data_w : integer) return integer is
VARIABLE result : integer;
BEGIN
CASE data_w IS
WHEN 1 =>
result := 1;
WHEN 2 =>
result := 2;
WHEN 4 =>
result := 4;
WHEN 9 =>
result := 9;
WHEN 18 =>
result := 18;
WHEN 36 =>
result := 18;
WHEN others =>
NULL;
END CASE;
RETURN result;
END;
FUNCTION data2data (data_w : integer) return integer is
VARIABLE result : integer;
BEGIN
CASE data_w IS
WHEN 1 =>
result := 8;
WHEN 2 =>
result := 4;
WHEN 4 =>
result := 2;
WHEN 9 =>
result := 36864;
WHEN 18 =>
result := 36864;
WHEN 36 =>
result := 36864;
WHEN others =>
NULL;
END CASE;
RETURN result;
END;
FUNCTION init_ram (hex: string; DATA_WIDTH_A : integer; DATA_WIDTH_B : integer) RETURN std_logic_vector IS
CONSTANT length : integer := hex'length;
VARIABLE result1 : mem_type_5 (0 to ((length/5)-1));
VARIABLE result : std_logic_vector(((length*18)/5)-1 downto 0);
BEGIN
FOR i in 0 to ((length/5)-1) LOOP
result1(i) := str5_slv18(hex((i+1)*5 downto (i*5)+1));
END LOOP;
IF (DATA_WIDTH_A >= 9 and DATA_WIDTH_B >= 9) THEN
FOR j in 0 to 511 LOOP
result(((j*18) + 17) downto (j*18)) := result1(j)(17 downto 0);
END LOOP;
ELSE
FOR j in 0 to 511 LOOP
result(((j*18) + 7) downto (j*18)) := result1(j)(7 downto 0);
result((j*18) + 8) := '0';
result(((j*18) + 16) downto ((j*18) + 9)) := result1(j)(15 downto 8);
result((j*18) + 17) := '0';
END LOOP;
END IF;
RETURN result;
END;
FUNCTION init_ram1 (hex: string) RETURN mem_type_6 IS
CONSTANT length : integer := hex'length;
VARIABLE result : mem_type_6 (0 to ((length/4)-1));
BEGIN
FOR i in 0 to ((length/4)-1) LOOP
result(i) := str4_slv16(hex((i+1)*4 downto (i*4)+1));
END LOOP;
RETURN result;
END;
-- String to std_logic_vector
FUNCTION str2slv (
str : in string
) return std_logic_vector is
variable j : integer := str'length;
variable slv : std_logic_vector (str'length downto 1);
begin
for i in str'low to str'high loop
case str(i) is
when '0' => slv(j) := '0';
when '1' => slv(j) := '1';
when 'X' => slv(j) := 'X';
when 'U' => slv(j) := 'U';
when others => slv(j) := 'X';
end case;
j := j - 1;
end loop;
return slv;
end str2slv;
function Valid_Address (
IN_ADDR : in std_logic_vector
) return boolean is
variable v_Valid_Flag : boolean := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Address;
END mem3 ;
--
-----cell dp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
--use ieee.std_logic_unsigned.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
library grlib;
use grlib.stdlib.all;
-- entity declaration --
ENTITY dp8ka IS
GENERIC (
DATA_WIDTH_A : Integer := 18;
DATA_WIDTH_B : Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-- miscellaneous vital GENERICs
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "dp8ka";
-- input SIGNAL delays
tipd_ada12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia17 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia16 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia15 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia14 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia13 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_clka : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cea : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_wea : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csa0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csa1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csa2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_rsta : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib17 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib16 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib15 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib14 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib13 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_clkb : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ceb : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_web : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csb0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csb1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csb2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_rstb : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- propagation delays
-- setup and hold constraints
-- pulse width constraints
tperiod_clka : VitalDelayType := 0.001 ns;
tpw_clka_posedge : VitalDelayType := 0.001 ns;
tpw_clka_negedge : VitalDelayType := 0.001 ns;
tperiod_clkb : VitalDelayType := 0.001 ns;
tpw_clkb_posedge : VitalDelayType := 0.001 ns;
tpw_clkb_negedge : VitalDelayType := 0.001 ns);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
ATTRIBUTE Vital_Level0 OF dp8ka : ENTITY IS TRUE;
END dp8ka ;
-- ARCHITECTURE body --
ARCHITECTURE V OF dp8ka IS
ATTRIBUTE Vital_Level0 OF V : ARCHITECTURE IS TRUE;
--SIGNAL DECLARATIONS----
SIGNAL ada_ipd : std_logic_vector(12 downto 0) := (others => '0');
SIGNAL dia_ipd : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL clka_ipd : std_logic := '0';
SIGNAL cea_ipd : std_logic := '0';
SIGNAL wrea_ipd : std_logic := '0';
SIGNAL csa_ipd : std_logic_vector(2 downto 0) := "000";
SIGNAL rsta_ipd : std_logic := '0';
SIGNAL adb_ipd : std_logic_vector(12 downto 0) := "XXXXXXXXXXXXX";
SIGNAL dib_ipd : std_logic_vector(17 downto 0) := "XXXXXXXXXXXXXXXXXX";
SIGNAL clkb_ipd : std_logic := '0';
SIGNAL ceb_ipd : std_logic := '0';
SIGNAL wreb_ipd : std_logic := '0';
SIGNAL csb_ipd : std_logic_vector(2 downto 0) := "000";
SIGNAL rstb_ipd : std_logic := '0';
SIGNAL csa_en : std_logic := '0';
SIGNAL csb_en : std_logic := '0';
SIGNAL g_reset : std_logic := '0';
CONSTANT ADDR_WIDTH_A : integer := data2addr_w(DATA_WIDTH_A);
CONSTANT ADDR_WIDTH_B : integer := data2addr_w(DATA_WIDTH_B);
CONSTANT new_data_width_a : integer := data2data_w(DATA_WIDTH_A);
CONSTANT new_data_width_b : integer := data2data_w(DATA_WIDTH_B);
CONSTANT div_a : integer := data2data(DATA_WIDTH_A);
CONSTANT div_b : integer := data2data(DATA_WIDTH_B);
SIGNAL dia_node : std_logic_vector((new_data_width_a - 1) downto 0) := (others => '0');
SIGNAL dib_node : std_logic_vector((new_data_width_b - 1) downto 0) := (others => '0');
SIGNAL ada_node : std_logic_vector((ADDR_WIDTH_A - 1) downto 0) := (others => '0');
SIGNAL adb_node : std_logic_vector((ADDR_WIDTH_B - 1) downto 0) := (others => '0');
SIGNAL diab_node : std_logic_vector(35 downto 0) := (others => '0');
SIGNAL rsta_int : std_logic := '0';
SIGNAL rstb_int : std_logic := '0';
SIGNAL rsta_reg : std_logic := '0';
SIGNAL rstb_reg : std_logic := '0';
SIGNAL reseta : std_logic := '0';
SIGNAL resetb : std_logic := '0';
SIGNAL dia_reg : std_logic_vector((new_data_width_a - 1) downto 0) := (others => '0');
SIGNAL dib_reg : std_logic_vector((new_data_width_b - 1) downto 0) := (others => '0');
SIGNAL ada_reg : std_logic_vector((ADDR_WIDTH_A - 1) downto 0);
SIGNAL adb_reg : std_logic_vector((ADDR_WIDTH_B - 1) downto 0);
SIGNAL diab_reg : std_logic_vector(35 downto 0) := (others => '0');
SIGNAL wrena_reg : std_logic := '0';
SIGNAL clka_valid : std_logic := '0';
SIGNAL clkb_valid : std_logic := '0';
SIGNAL clka_valid1 : std_logic := '0';
SIGNAL clkb_valid1 : std_logic := '0';
SIGNAL wrenb_reg : std_logic := '0';
SIGNAL rena_reg : std_logic := '0';
SIGNAL renb_reg : std_logic := '0';
SIGNAL rsta_sig : std_logic := '0';
SIGNAL rstb_sig : std_logic := '0';
SIGNAL doa_node : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_node_tr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_node_wt : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_node_rbr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node_tr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node_wt : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node_rbr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_reg : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_reg : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doab_reg : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_int : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_int : std_logic_vector(17 downto 0) := (others => '0');
CONSTANT initval : string(2560 downto 1) := (
initval_1f(3 to 82)&initval_1e(3 to 82)&initval_1d(3 to 82)&initval_1c(3 to 82)&
initval_1b(3 to 82)&initval_1a(3 to 82)&initval_19(3 to 82)&initval_18(3 to 82)&
initval_17(3 to 82)&initval_16(3 to 82)&initval_15(3 to 82)&initval_14(3 to 82)&
initval_13(3 to 82)&initval_12(3 to 82)&initval_11(3 to 82)&initval_10(3 to 82)&
initval_0f(3 to 82)&initval_0e(3 to 82)&initval_0d(3 to 82)&initval_0c(3 to 82)&
initval_0b(3 to 82)&initval_0a(3 to 82)&initval_09(3 to 82)&initval_08(3 to 82)&
initval_07(3 to 82)&initval_06(3 to 82)&initval_05(3 to 82)&initval_04(3 to 82)&
initval_03(3 to 82)&initval_02(3 to 82)&initval_01(3 to 82)&initval_00(3 to 82));
SIGNAL MEM : std_logic_vector(9215 downto 0) := init_ram (initval, DATA_WIDTH_A, DATA_WIDTH_B);
SIGNAL j : integer := 0;
BEGIN
-----------------------
-- input path delays
-----------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(ada_ipd(0), ada0, tipd_ada0);
VitalWireDelay(ada_ipd(1), ada1, tipd_ada1);
VitalWireDelay(ada_ipd(2), ada2, tipd_ada2);
VitalWireDelay(ada_ipd(3), ada3, tipd_ada3);
VitalWireDelay(ada_ipd(4), ada4, tipd_ada4);
VitalWireDelay(ada_ipd(5), ada5, tipd_ada5);
VitalWireDelay(ada_ipd(6), ada6, tipd_ada6);
VitalWireDelay(ada_ipd(7), ada7, tipd_ada7);
VitalWireDelay(ada_ipd(8), ada8, tipd_ada8);
VitalWireDelay(ada_ipd(9), ada9, tipd_ada9);
VitalWireDelay(ada_ipd(10), ada10, tipd_ada10);
VitalWireDelay(ada_ipd(11), ada11, tipd_ada11);
VitalWireDelay(ada_ipd(12), ada12, tipd_ada12);
VitalWireDelay(dia_ipd(0), dia0, tipd_dia0);
VitalWireDelay(dia_ipd(1), dia1, tipd_dia1);
VitalWireDelay(dia_ipd(2), dia2, tipd_dia2);
VitalWireDelay(dia_ipd(3), dia3, tipd_dia3);
VitalWireDelay(dia_ipd(4), dia4, tipd_dia4);
VitalWireDelay(dia_ipd(5), dia5, tipd_dia5);
VitalWireDelay(dia_ipd(6), dia6, tipd_dia6);
VitalWireDelay(dia_ipd(7), dia7, tipd_dia7);
VitalWireDelay(dia_ipd(8), dia8, tipd_dia8);
VitalWireDelay(dia_ipd(9), dia9, tipd_dia9);
VitalWireDelay(dia_ipd(10), dia10, tipd_dia10);
VitalWireDelay(dia_ipd(11), dia11, tipd_dia11);
VitalWireDelay(dia_ipd(12), dia12, tipd_dia12);
VitalWireDelay(dia_ipd(13), dia13, tipd_dia13);
VitalWireDelay(dia_ipd(14), dia14, tipd_dia14);
VitalWireDelay(dia_ipd(15), dia15, tipd_dia15);
VitalWireDelay(dia_ipd(16), dia16, tipd_dia16);
VitalWireDelay(dia_ipd(17), dia17, tipd_dia17);
VitalWireDelay(clka_ipd, clka, tipd_clka);
VitalWireDelay(wrea_ipd, wea, tipd_wea);
VitalWireDelay(cea_ipd, cea, tipd_cea);
VitalWireDelay(csa_ipd(0), csa0, tipd_csa0);
VitalWireDelay(csa_ipd(1), csa1, tipd_csa1);
VitalWireDelay(csa_ipd(2), csa2, tipd_csa2);
VitalWireDelay(rsta_ipd, rsta, tipd_rsta);
VitalWireDelay(adb_ipd(0), adb0, tipd_adb0);
VitalWireDelay(adb_ipd(1), adb1, tipd_adb1);
VitalWireDelay(adb_ipd(2), adb2, tipd_adb2);
VitalWireDelay(adb_ipd(3), adb3, tipd_adb3);
VitalWireDelay(adb_ipd(4), adb4, tipd_adb4);
VitalWireDelay(adb_ipd(5), adb5, tipd_adb5);
VitalWireDelay(adb_ipd(6), adb6, tipd_adb6);
VitalWireDelay(adb_ipd(7), adb7, tipd_adb7);
VitalWireDelay(adb_ipd(8), adb8, tipd_adb8);
VitalWireDelay(adb_ipd(9), adb9, tipd_adb9);
VitalWireDelay(adb_ipd(10), adb10, tipd_adb10);
VitalWireDelay(adb_ipd(11), adb11, tipd_adb11);
VitalWireDelay(adb_ipd(12), adb12, tipd_adb12);
VitalWireDelay(dib_ipd(0), dib0, tipd_dib0);
VitalWireDelay(dib_ipd(1), dib1, tipd_dib1);
VitalWireDelay(dib_ipd(2), dib2, tipd_dib2);
VitalWireDelay(dib_ipd(3), dib3, tipd_dib3);
VitalWireDelay(dib_ipd(4), dib4, tipd_dib4);
VitalWireDelay(dib_ipd(5), dib5, tipd_dib5);
VitalWireDelay(dib_ipd(6), dib6, tipd_dib6);
VitalWireDelay(dib_ipd(7), dib7, tipd_dib7);
VitalWireDelay(dib_ipd(8), dib8, tipd_dib8);
VitalWireDelay(dib_ipd(9), dib9, tipd_dib9);
VitalWireDelay(dib_ipd(10), dib10, tipd_dib10);
VitalWireDelay(dib_ipd(11), dib11, tipd_dib11);
VitalWireDelay(dib_ipd(12), dib12, tipd_dib12);
VitalWireDelay(dib_ipd(13), dib13, tipd_dib13);
VitalWireDelay(dib_ipd(14), dib14, tipd_dib14);
VitalWireDelay(dib_ipd(15), dib15, tipd_dib15);
VitalWireDelay(dib_ipd(16), dib16, tipd_dib16);
VitalWireDelay(dib_ipd(17), dib17, tipd_dib17);
VitalWireDelay(clkb_ipd, clkb, tipd_clkb);
VitalWireDelay(wreb_ipd, web, tipd_web);
VitalWireDelay(ceb_ipd, ceb, tipd_ceb);
VitalWireDelay(csb_ipd(0), csb0, tipd_csb0);
VitalWireDelay(csb_ipd(1), csb1, tipd_csb1);
VitalWireDelay(csb_ipd(2), csb2, tipd_csb2);
VitalWireDelay(rstb_ipd, rstb, tipd_rstb);
END BLOCK;
GLOBALRESET : PROCESS (purnet, gsrnet)
BEGIN
IF (GSR = "DISABLED") THEN
g_reset <= purnet;
ELSE
g_reset <= purnet AND gsrnet;
END IF;
END PROCESS;
rsta_sig <= rsta_ipd or (not g_reset);
rstb_sig <= rstb_ipd or (not g_reset);
-- set_reset <= g_reset and (not reset_ipd);
ada_node <= ada_ipd(12 downto (13 - ADDR_WIDTH_A));
adb_node <= adb_ipd(12 downto (13 - ADDR_WIDTH_B));
-- chip select A decode
P1 : PROCESS(csa_ipd)
BEGIN
IF (csa_ipd = "000" and CSDECODE_A = "000") THEN
csa_en <= '1';
ELSIF (csa_ipd = "001" and CSDECODE_A = "001") THEN
csa_en <= '1';
ELSIF (csa_ipd = "010" and CSDECODE_A = "010") THEN
csa_en <= '1';
ELSIF (csa_ipd = "011" and CSDECODE_A = "011") THEN
csa_en <= '1';
ELSIF (csa_ipd = "100" and CSDECODE_A = "100") THEN
csa_en <= '1';
ELSIF (csa_ipd = "101" and CSDECODE_A = "101") THEN
csa_en <= '1';
ELSIF (csa_ipd = "110" and CSDECODE_A = "110") THEN
csa_en <= '1';
ELSIF (csa_ipd = "111" and CSDECODE_A = "111") THEN
csa_en <= '1';
ELSE
csa_en <= '0';
END IF;
END PROCESS;
P2 : PROCESS(csb_ipd)
BEGIN
IF (csb_ipd = "000" and CSDECODE_B = "000") THEN
csb_en <= '1';
ELSIF (csb_ipd = "001" and CSDECODE_B = "001") THEN
csb_en <= '1';
ELSIF (csb_ipd = "010" and CSDECODE_B = "010") THEN
csb_en <= '1';
ELSIF (csb_ipd = "011" and CSDECODE_B = "011") THEN
csb_en <= '1';
ELSIF (csb_ipd = "100" and CSDECODE_B = "100") THEN
csb_en <= '1';
ELSIF (csb_ipd = "101" and CSDECODE_B = "101") THEN
csb_en <= '1';
ELSIF (csb_ipd = "110" and CSDECODE_B = "110") THEN
csb_en <= '1';
ELSIF (csb_ipd = "111" and CSDECODE_B = "111") THEN
csb_en <= '1';
ELSE
csb_en <= '0';
END IF;
END PROCESS;
P3 : PROCESS(dia_ipd)
BEGIN
CASE DATA_WIDTH_A IS
WHEN 1 =>
dia_node <= dia_ipd(11 downto 11);
WHEN 2 =>
dia_node <= (dia_ipd(1), dia_ipd(11));
WHEN 4 =>
dia_node <= dia_ipd(3 downto 0);
WHEN 9 =>
dia_node <= dia_ipd(8 downto 0);
WHEN 18 =>
dia_node <= dia_ipd;
WHEN 36 =>
dia_node <= dia_ipd;
WHEN others =>
NULL;
END CASE;
END PROCESS;
P4 : PROCESS(dib_ipd)
BEGIN
CASE DATA_WIDTH_B IS
WHEN 1 =>
dib_node <= dib_ipd(11 downto 11);
WHEN 2 =>
dib_node <= (dib_ipd(1), dib_ipd(11));
WHEN 4 =>
dib_node <= dib_ipd(3 downto 0);
WHEN 9 =>
dib_node <= dib_ipd(8 downto 0);
WHEN 18 =>
dib_node <= dib_ipd;
WHEN 36 =>
dib_node <= dib_ipd;
WHEN others =>
NULL;
END CASE;
END PROCESS;
diab_node <= (dib_ipd & dia_ipd);
P107 : PROCESS(clka_ipd)
BEGIN
IF (clka_ipd'event and clka_ipd = '1' and clka_ipd'last_value = '0') THEN
IF ((g_reset = '0') or (rsta_ipd = '1')) THEN
clka_valid <= '0';
ELSE
IF (cea_ipd = '1') THEN
IF (csa_en = '1') THEN
clka_valid <= '1', '0' after 0.01 ns;
ELSE
clka_valid <= '0';
END IF;
ELSE
clka_valid <= '0';
END IF;
END IF;
END IF;
END PROCESS;
P108 : PROCESS(clkb_ipd)
BEGIN
IF (clkb_ipd'event and clkb_ipd = '1' and clkb_ipd'last_value = '0') THEN
IF ((g_reset = '0') or (rstb_ipd = '1')) THEN
clkb_valid <= '0';
ELSE
IF (ceb_ipd = '1') THEN
IF (csb_en = '1') THEN
clkb_valid <= '1', '0' after 0.01 ns;
ELSE
clkb_valid <= '0';
END IF;
ELSE
clkb_valid <= '0';
END IF;
END IF;
END IF;
END PROCESS;
clka_valid1 <= clka_valid;
clkb_valid1 <= clkb_valid;
P7 : PROCESS(g_reset, rsta_ipd, rstb_ipd, clka_ipd, clkb_ipd)
BEGIN
IF (g_reset = '0') THEN
dia_reg <= (others => '0');
diab_reg <= (others => '0');
ada_reg <= (others => '0');
wrena_reg <= '0';
rena_reg <= '0';
ELSIF (RESETMODE = "ASYNC") THEN
IF (rsta_ipd = '1') THEN
dia_reg <= (others => '0');
diab_reg <= (others => '0');
ada_reg <= (others => '0');
wrena_reg <= '0';
rena_reg <= '0';
ELSIF (clka_ipd'event and clka_ipd = '1') THEN
IF (cea_ipd = '1') THEN
dia_reg <= dia_node;
diab_reg <= diab_node;
ada_reg <= ada_node;
wrena_reg <= (wrea_ipd and csa_en);
rena_reg <= ((not wrea_ipd) and csa_en);
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clka_ipd'event and clka_ipd = '1') THEN
IF (rsta_ipd = '1') THEN
dia_reg <= (others => '0');
diab_reg <= (others => '0');
ada_reg <= (others => '0');
wrena_reg <= '0';
rena_reg <= '0';
ELSIF (cea_ipd = '1') THEN
dia_reg <= dia_node;
diab_reg <= diab_node;
ada_reg <= ada_node;
wrena_reg <= (wrea_ipd and csa_en);
rena_reg <= ((not wrea_ipd) and csa_en);
END IF;
END IF;
END IF;
IF (g_reset = '0') THEN
dib_reg <= (others => '0');
adb_reg <= (others => '0');
wrenb_reg <= '0';
renb_reg <= '0';
ELSIF (RESETMODE = "ASYNC") THEN
IF (rstb_ipd = '1') THEN
dib_reg <= (others => '0');
adb_reg <= (others => '0');
wrenb_reg <= '0';
renb_reg <= '0';
ELSIF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (ceb_ipd = '1') THEN
dib_reg <= dib_node;
adb_reg <= adb_node;
wrenb_reg <= (wreb_ipd and csb_en);
renb_reg <= ((not wreb_ipd) and csb_en);
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (rstb_ipd = '1') THEN
dib_reg <= (others => '0');
adb_reg <= (others => '0');
wrenb_reg <= '0';
renb_reg <= '0';
ELSIF (ceb_ipd = '1') THEN
dib_reg <= dib_node;
adb_reg <= adb_node;
wrenb_reg <= (wreb_ipd and csb_en);
renb_reg <= ((not wreb_ipd) and csb_en);
END IF;
END IF;
END IF;
END PROCESS;
-- Warning for collision
PW : PROCESS(ada_reg, adb_reg, wrena_reg, wrenb_reg, clka_valid, clkb_valid, rena_reg,
renb_reg)
VARIABLE WADDR_A_VALID : boolean := TRUE;
VARIABLE WADDR_B_VALID : boolean := TRUE;
VARIABLE ADDR_A : integer := 0;
VARIABLE ADDR_B : integer := 0;
VARIABLE DN_ADDR_A : integer := 0;
VARIABLE UP_ADDR_A : integer := 0;
VARIABLE DN_ADDR_B : integer := 0;
VARIABLE UP_ADDR_B : integer := 0;
BEGIN
WADDR_A_VALID := Valid_Address (ada_reg);
WADDR_B_VALID := Valid_Address (adb_reg);
IF (WADDR_A_VALID = TRUE) THEN
ADDR_A := conv_integer(ada_reg);
END IF;
IF (WADDR_B_VALID = TRUE) THEN
ADDR_B := conv_integer(adb_reg);
END IF;
DN_ADDR_A := (ADDR_A * DATA_WIDTH_A);
UP_ADDR_A := (((ADDR_A + 1) * DATA_WIDTH_A) - 1);
DN_ADDR_B := (ADDR_B * DATA_WIDTH_B);
UP_ADDR_B := (((ADDR_B + 1) * DATA_WIDTH_B) - 1);
IF ((wrena_reg = '1' and clka_valid = '1') and (wrenb_reg = '1' and clkb_valid = '1')) THEN
IF (not((UP_ADDR_B <= DN_ADDR_A) or (DN_ADDR_B >= UP_ADDR_A))) THEN
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity error;
END IF;
END IF;
-- IF ((wrena_reg = '1' and clka_valid = '1') and (renb_reg = '1' and clkb_valid = '1')) THEN
-- IF (not((UP_ADDR_B <= DN_ADDR_A) or (DN_ADDR_B >= UP_ADDR_A))) THEN
-- assert false
-- report " Write/Read collision! Writing through Port A and reading through Port B from the same memory location may give wrong output."
-- severity warning;
-- END IF;
-- END IF;
-- IF ((rena_reg = '1' and clka_valid = '1') and (wrenb_reg = '1' and clkb_valid = '1')) THEN
-- IF (not((UP_ADDR_A <= DN_ADDR_B) or (DN_ADDR_A >= UP_ADDR_B))) THEN
-- assert false
-- report " Write/Read collision! Writing through Port B and reading through Port A from the same memory location may give wrong output."
-- severity warning;
-- END IF;
-- END IF;
END PROCESS;
-- Writing to the memory
P8 : PROCESS(ada_reg, dia_reg, diab_reg, wrena_reg, dib_reg, adb_reg,
wrenb_reg, clka_valid, clkb_valid)
VARIABLE WADDR_A_VALID : boolean := TRUE;
VARIABLE WADDR_B_VALID : boolean := TRUE;
VARIABLE WADDR_A : integer := 0;
VARIABLE WADDR_B : integer := 0;
VARIABLE dout_node_rbr : std_logic_vector(35 downto 0);
BEGIN
WADDR_A_VALID := Valid_Address (ada_reg);
WADDR_B_VALID := Valid_Address (adb_reg);
IF (WADDR_A_VALID = TRUE) THEN
WADDR_A := conv_integer(ada_reg);
END IF;
IF (WADDR_B_VALID = TRUE) THEN
WADDR_B := conv_integer(adb_reg);
END IF;
IF (DATA_WIDTH_A = 36) THEN
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
dout_node_rbr(i) := MEM((WADDR_A * DATA_WIDTH_A) + i);
END LOOP;
doa_node_rbr <= dout_node_rbr(17 downto 0);
dob_node_rbr <= dout_node_rbr(35 downto 18);
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i) <= diab_reg(i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 9) <= diab_reg(i + 9);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 18) <= diab_reg(i + 18);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 27) <= diab_reg(i + 27);
END LOOP;
END IF;
ELSE
IF (DATA_WIDTH_A = 18) THEN
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i) <= dia_reg(i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 9) <= dia_reg(i + 9);
END LOOP;
END IF;
ELSIF (DATA_WIDTH_A = 9) THEN
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i) <= dia_reg(i);
END LOOP;
END IF;
ELSE
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i) <= dia_reg(i);
END LOOP;
END IF;
END IF;
IF (DATA_WIDTH_B = 18) THEN
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_B * DATA_WIDTH_B) + i) <= dib_reg(i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_B * DATA_WIDTH_B) + i + 9) <= dib_reg(i + 9);
END LOOP;
END IF;
ELSIF (DATA_WIDTH_B = 9) THEN
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
MEM((WADDR_B * DATA_WIDTH_B) + i) <= dib_reg(i);
END LOOP;
END IF;
ELSE
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i) <= dib_reg(i);
END LOOP;
END IF;
END IF;
END IF;
END PROCESS;
P9 : PROCESS(ada_reg, rena_reg, adb_reg, renb_reg, MEM, clka_valid1, clkb_valid1, rsta_sig, rstb_sig, doa_node_rbr, dob_node_rbr)
VARIABLE RADDR_A_VALID : boolean := TRUE;
VARIABLE RADDR_B_VALID : boolean := TRUE;
VARIABLE RADDR_A : integer := 0;
VARIABLE RADDR_B : integer := 0;
VARIABLE dout_node_tr : std_logic_vector(35 downto 0);
VARIABLE dout_node_wt : std_logic_vector(35 downto 0);
BEGIN
RADDR_A_VALID := Valid_Address (ada_reg);
RADDR_B_VALID := Valid_Address (adb_reg);
IF (RADDR_A_VALID = TRUE) THEN
RADDR_A := conv_integer(ada_reg);
END IF;
IF (RADDR_B_VALID = TRUE) THEN
RADDR_B := conv_integer(adb_reg);
END IF;
IF (DATA_WIDTH_B = 36) THEN
IF (rstb_sig = '1') THEN
IF (RESETMODE = "SYNC") THEN
IF (clkb_ipd = '1') THEN
doa_node <= (others => '0');
dob_node <= (others => '0');
END IF;
ELSIF (RESETMODE = "ASYNC") THEN
doa_node <= (others => '0');
dob_node <= (others => '0');
END IF;
ELSIF (clkb_valid1'event and clkb_valid1 = '1') THEN
IF (renb_reg = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dout_node_tr(i) := MEM((RADDR_B * DATA_WIDTH_B) + i);
END LOOP;
doa_node <= dout_node_tr(17 downto 0);
dob_node <= dout_node_tr(35 downto 18);
ELSIF (renb_reg = '0') THEN
IF (WRITEMODE_B = "WRITETHROUGH") THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dout_node_wt(i) := MEM((RADDR_B * DATA_WIDTH_B) + i);
END LOOP;
doa_node <= dout_node_wt(17 downto 0);
dob_node <= dout_node_wt(35 downto 18);
ELSIF (WRITEMODE_B = "READBEFOREWRITE") THEN
doa_node <= doa_node_rbr;
dob_node <= dob_node_rbr;
END IF;
END IF;
END IF;
ELSE
IF (rsta_sig = '1') THEN
IF (RESETMODE = "SYNC") THEN
IF (clka_ipd = '1') THEN
doa_node <= (others => '0');
END IF;
ELSIF (RESETMODE = "ASYNC") THEN
doa_node <= (others => '0');
END IF;
ELSIF (clka_valid1'event and clka_valid1 = '1') THEN
IF (rena_reg = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node(i) <= MEM((RADDR_A * DATA_WIDTH_A) + (RADDR_A / div_a) + i);
END LOOP;
ELSIF (rena_reg = '0') THEN
IF (WRITEMODE_A = "WRITETHROUGH") THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node(i) <= MEM((RADDR_A * DATA_WIDTH_A) + (RADDR_A / div_a) + i);
END LOOP;
ELSIF (WRITEMODE_A = "READBEFOREWRITE") THEN
doa_node <= doa_node_rbr;
END IF;
END IF;
END IF;
IF (rstb_sig = '1') THEN
IF (RESETMODE = "SYNC") THEN
IF (clkb_ipd = '1') THEN
dob_node <= (others => '0');
END IF;
ELSIF (RESETMODE = "ASYNC") THEN
dob_node <= (others => '0');
END IF;
ELSIF (clkb_valid1'event and clkb_valid1 = '1') THEN
IF (renb_reg = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node(i) <= MEM((RADDR_B * DATA_WIDTH_B) + (RADDR_B / div_b) + i);
END LOOP;
ELSIF (renb_reg = '0') THEN
IF (WRITEMODE_B = "WRITETHROUGH") THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node(i) <= MEM((RADDR_B * DATA_WIDTH_B) + (RADDR_B / div_b) + i);
END LOOP;
ELSIF (WRITEMODE_B = "READBEFOREWRITE") THEN
dob_node <= dob_node_rbr;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
P10 : PROCESS(g_reset, rsta_ipd, rstb_ipd, clka_ipd, clkb_ipd)
BEGIN
IF (g_reset = '0') THEN
doa_reg <= (others => '0');
ELSIF (RESETMODE = "ASYNC") THEN
IF (rsta_ipd = '1') THEN
doa_reg <= (others => '0');
ELSIF (clka_ipd'event and clka_ipd = '1') THEN
IF (cea_ipd = '1') THEN
doa_reg <= doa_node;
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clka_ipd'event and clka_ipd = '1') THEN
IF (cea_ipd = '1') THEN
IF (rsta_ipd = '1') THEN
doa_reg <= (others => '0');
ELSIF (rsta_ipd = '0') THEN
doa_reg <= doa_node;
END IF;
END IF;
END IF;
END IF;
IF (g_reset = '0') THEN
dob_reg <= (others => '0');
doab_reg <= (others => '0');
ELSIF (RESETMODE = "ASYNC") THEN
IF (rstb_ipd = '1') THEN
dob_reg <= (others => '0');
doab_reg <= (others => '0');
ELSIF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (ceb_ipd = '1') THEN
dob_reg <= dob_node;
doab_reg <= doa_node;
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (ceb_ipd = '1') THEN
IF (rstb_ipd = '1') THEN
dob_reg <= (others => '0');
doab_reg <= (others => '0');
ELSIF (rstb_ipd = '0') THEN
dob_reg <= dob_node;
doab_reg <= doa_node;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
P11 : PROCESS(doa_node, dob_node, doa_reg, dob_reg, doab_reg)
BEGIN
IF (REGMODE_A = "OUTREG") THEN
IF (DATA_WIDTH_B = 36) THEN
doa_int <= doab_reg;
ELSE
doa_int <= doa_reg;
END IF;
ELSE
doa_int <= doa_node;
END IF;
IF (REGMODE_B = "OUTREG") THEN
dob_int <= dob_reg;
ELSE
dob_int <= dob_node;
END IF;
END PROCESS;
(doa17, doa16, doa15, doa14, doa13, doa12, doa11, doa10, doa9, doa8, doa7, doa6,
doa5, doa4, doa3, doa2, doa1, doa0) <= doa_int;
(dob17, dob16, dob15, dob14, dob13, dob12, dob11, dob10, dob9, dob8, dob7, dob6,
dob5, dob4, dob3, dob2, dob1, dob0) <= dob_int;
END V;
--
-----cell sp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
-- entity declaration --
ENTITY sp8ka IS
GENERIC (
DATA_WIDTH : Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000");
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
ATTRIBUTE Vital_Level0 OF sp8ka : ENTITY IS TRUE;
END sp8ka ;
architecture V of sp8ka is
signal lo: std_logic := '0';
signal hi: std_logic := '1';
component dp8ka
GENERIC(
DATA_WIDTH_A : in Integer;
DATA_WIDTH_B : in Integer;
REGMODE_A : in String;
REGMODE_B : in String;
RESETMODE : in String;
CSDECODE_A : in String;
CSDECODE_B : in String;
WRITEMODE_A : in String;
WRITEMODE_B : in String;
GSR : in String;
initval_00 : in string;
initval_01 : in string;
initval_02 : in string;
initval_03 : in string;
initval_04 : in string;
initval_05 : in string;
initval_06 : in string;
initval_07 : in string;
initval_08 : in string;
initval_09 : in string;
initval_0a : in string;
initval_0b : in string;
initval_0c : in string;
initval_0d : in string;
initval_0e : in string;
initval_0f : in string;
initval_10 : in string;
initval_11 : in string;
initval_12 : in string;
initval_13 : in string;
initval_14 : in string;
initval_15 : in string;
initval_16 : in string;
initval_17 : in string;
initval_18 : in string;
initval_19 : in string;
initval_1a : in string;
initval_1b : in string;
initval_1c : in string;
initval_1d : in string;
initval_1e : in string;
initval_1f : in string);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic;
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic;
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic;
ada9, ada10, ada11, ada12 : in std_logic;
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic;
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic;
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic;
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic;
adb9, adb10, adb11, adb12 : in std_logic;
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic;
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic;
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic;
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic;
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic
);
END COMPONENT;
begin
-- component instantiation statements
dp8ka_inst : dp8ka
generic map (DATA_WIDTH_A => DATA_WIDTH,
DATA_WIDTH_B => DATA_WIDTH,
REGMODE_A => REGMODE,
REGMODE_B => REGMODE,
RESETMODE => RESETMODE,
CSDECODE_A => CSDECODE,
CSDECODE_B => CSDECODE,
WRITEMODE_A => WRITEMODE,
WRITEMODE_B => WRITEMODE,
GSR => GSR,
initval_00 => initval_00,
initval_01 => initval_01,
initval_02 => initval_02,
initval_03 => initval_03,
initval_04 => initval_04,
initval_05 => initval_05,
initval_06 => initval_06,
initval_07 => initval_07,
initval_08 => initval_08,
initval_09 => initval_09,
initval_0a => initval_0a,
initval_0b => initval_0b,
initval_0c => initval_0c,
initval_0d => initval_0d,
initval_0e => initval_0e,
initval_0f => initval_0f,
initval_10 => initval_10,
initval_11 => initval_11,
initval_12 => initval_12,
initval_13 => initval_13,
initval_14 => initval_14,
initval_15 => initval_15,
initval_16 => initval_16,
initval_17 => initval_17,
initval_18 => initval_18,
initval_19 => initval_19,
initval_1a => initval_1a,
initval_1b => initval_1b,
initval_1c => initval_1c,
initval_1d => initval_1d,
initval_1e => initval_1e,
initval_1f => initval_1f)
port map (dia0 => di0, dia1 => di1, dia2 => di2, dia3 => di3,
dia4 => di4, dia5 => di5, dia6 => di6, dia7 => di7, dia8 => di8,
dia9 => di9, dia10 => di10, dia11 => di11, dia12 => di12, dia13 => di13,
dia14 => di14, dia15 => di15, dia16 => di16, dia17 => di17, dib0 => lo,
dib1 => lo, dib2 => lo, dib3 => lo, dib4 => lo, dib5 => lo,
dib6 => lo, dib7 => lo, dib8 => lo, dib9 => lo, dib10 => lo,
dib11 => lo, dib12 => lo, dib13 => lo, dib14 => lo, dib15 => lo,
dib16 => lo, dib17 => lo,
cea => ce, clka => clk, wea => we, csa0 => cs0, csa1 => cs1, csa2 => cs2,
rsta => rst, ada0 => ad0, ada1 => ad1, ada2 => ad2, ada3 => ad3,
ada4 => ad4, ada5 => ad5, ada6 => ad6, ada7 => ad7, ada8 => ad8,
ada9 => ad9, ada10 => ad10, ada11 => ad11, ada12 => ad12,
ceb => lo, clkb => lo, web => lo, csb0 => lo, csb1 => lo, csb2 => lo,
rstb => hi, adb0 => lo, adb1 => lo, adb2 => lo, adb3 => lo,
adb4 => lo, adb5 => lo, adb6 => lo, adb7 => lo, adb8 => lo,
adb9 => lo, adb10 => lo, adb11 => lo, adb12 => lo,
dob0 => open, dob1 => open, dob2 => open, dob3 => open,
dob4 => open, dob5 => open, dob6 => open, dob7 => open, dob8 => open,
dob9 => open, dob10 => open, dob11 => open, dob12 => open, dob13 => open,
dob14 => open, dob15 => open, dob16 => open, dob17 => open, doa0 => do0,
doa1 => do1, doa2 => do2, doa3 => do3, doa4 => do4, doa5 => do5,
doa6 => do6, doa7 => do7, doa8 => do8, doa9 => do9, doa10 => do10,
doa11 => do11, doa12 => do12, doa13 => do13, doa14 => do14, doa15 => do15,
doa16 => do16, doa17 => do17);
end V;
--
-----cell pdp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
-- entity declaration --
ENTITY pdp8ka IS
GENERIC (
DATA_WIDTH_W : Integer := 18;
DATA_WIDTH_R : Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_W : String := "000";
CSDECODE_R : String := "000";
GSR : String := "ENABLED";
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000");
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
di18, di19, di20, di21, di22, di23, di24, di25, di26 : in std_logic := 'X';
di27, di28, di29, di30, di31, di32, di33, di34, di35 : in std_logic := 'X';
adw0, adw1, adw2, adw3, adw4, adw5, adw6, adw7, adw8 : in std_logic := 'X';
adw9, adw10, adw11, adw12 : in std_logic := 'X';
cew, clkw, we, csw0, csw1, csw2 : in std_logic := 'X';
adr0, adr1, adr2, adr3, adr4, adr5, adr6, adr7, adr8 : in std_logic := 'X';
adr9, adr10, adr11, adr12 : in std_logic := 'X';
cer, clkr, csr0, csr1, csr2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X';
do18, do19, do20, do21, do22, do23, do24, do25, do26 : out std_logic := 'X';
do27, do28, do29, do30, do31, do32, do33, do34, do35 : out std_logic := 'X'
);
ATTRIBUTE Vital_Level0 OF pdp8ka : ENTITY IS TRUE;
END pdp8ka ;
architecture V of pdp8ka is
signal lo: std_logic := '0';
component dp8ka
GENERIC(
DATA_WIDTH_A : in Integer;
DATA_WIDTH_B : in Integer;
REGMODE_A : in String;
REGMODE_B : in String;
RESETMODE : in String;
CSDECODE_A : in String;
CSDECODE_B : in String;
GSR : in String;
initval_00 : in string;
initval_01 : in string;
initval_02 : in string;
initval_03 : in string;
initval_04 : in string;
initval_05 : in string;
initval_06 : in string;
initval_07 : in string;
initval_08 : in string;
initval_09 : in string;
initval_0a : in string;
initval_0b : in string;
initval_0c : in string;
initval_0d : in string;
initval_0e : in string;
initval_0f : in string;
initval_10 : in string;
initval_11 : in string;
initval_12 : in string;
initval_13 : in string;
initval_14 : in string;
initval_15 : in string;
initval_16 : in string;
initval_17 : in string;
initval_18 : in string;
initval_19 : in string;
initval_1a : in string;
initval_1b : in string;
initval_1c : in string;
initval_1d : in string;
initval_1e : in string;
initval_1f : in string);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic;
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic;
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic;
ada9, ada10, ada11, ada12 : in std_logic;
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic;
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic;
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic;
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic;
adb9, adb10, adb11, adb12 : in std_logic;
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic;
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic;
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic;
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic;
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic
);
END COMPONENT;
begin
-- component instantiation statements
dp8ka_inst : dp8ka
generic map (DATA_WIDTH_A => DATA_WIDTH_W,
DATA_WIDTH_B => DATA_WIDTH_R,
REGMODE_A => REGMODE,
REGMODE_B => REGMODE,
RESETMODE => RESETMODE,
CSDECODE_A => CSDECODE_W,
CSDECODE_B => CSDECODE_R,
GSR => GSR,
initval_00 => initval_00,
initval_01 => initval_01,
initval_02 => initval_02,
initval_03 => initval_03,
initval_04 => initval_04,
initval_05 => initval_05,
initval_06 => initval_06,
initval_07 => initval_07,
initval_08 => initval_08,
initval_09 => initval_09,
initval_0a => initval_0a,
initval_0b => initval_0b,
initval_0c => initval_0c,
initval_0d => initval_0d,
initval_0e => initval_0e,
initval_0f => initval_0f,
initval_10 => initval_10,
initval_11 => initval_11,
initval_12 => initval_12,
initval_13 => initval_13,
initval_14 => initval_14,
initval_15 => initval_15,
initval_16 => initval_16,
initval_17 => initval_17,
initval_18 => initval_18,
initval_19 => initval_19,
initval_1a => initval_1a,
initval_1b => initval_1b,
initval_1c => initval_1c,
initval_1d => initval_1d,
initval_1e => initval_1e,
initval_1f => initval_1f)
port map (dia0 => di0, dia1 => di1, dia2 => di2, dia3 => di3,
dia4 => di4, dia5 => di5, dia6 => di6, dia7 => di7, dia8 => di8,
dia9 => di9, dia10 => di10, dia11 => di11, dia12 => di12, dia13 => di13,
dia14 => di14, dia15 => di15, dia16 => di16, dia17 => di17, dib0 => di18,
dib1 => di19, dib2 => di20, dib3 => di21, dib4 => di22, dib5 => di23,
dib6 => di24, dib7 => di25, dib8 => di26, dib9 => di27, dib10 => di28,
dib11 => di29, dib12 => di30, dib13 => di31, dib14 => di32, dib15 => di33,
dib16 => di34, dib17 => di35,
cea => cew, clka => clkw, wea => we, csa0 => csw0, csa1 => csw1, csa2 => csw2,
rsta => rst, ada0 => adw0, ada1 => adw1, ada2 => adw2, ada3 => adw3,
ada4 => adw4, ada5 => adw5, ada6 => adw6, ada7 => adw7, ada8 => adw8,
ada9 => adw9, ada10 => adw10, ada11 => adw11, ada12 => adw12,
ceb => cer, clkb => clkr, web => lo, csb0 => csr0, csb1 => csr1, csb2 => csr2,
rstb => rst, adb0 => adr0, adb1 => adr1, adb2 => adr2, adb3 => adr3,
adb4 => adr4, adb5 => adr5, adb6 => adr6, adb7 => adr7, adb8 => adr8,
adb9 => adr9, adb10 => adr10, adb11 => adr11, adb12 => adr12,
dob0 => do0, dob1 => do1, dob2 => do2, dob3 => do3,
dob4 => do4, dob5 => do5, dob6 => do6, dob7 => do7, dob8 => do8,
dob9 => do9, dob10 => do10, dob11 => do11, dob12 => do12, dob13 => do13,
dob14 => do14, dob15 => do15, dob16 => do16, dob17 => do17, doa0 => do18,
doa1 => do19, doa2 => do20, doa3 => do21, doa4 => do22, doa5 => do23,
doa6 => do24, doa7 => do25, doa8 => do26, doa9 => do27, doa10 => do28,
doa11 => do29, doa12 => do30, doa13 => do31, doa14 => do32, doa15 => do33,
doa16 => do34, doa17 => do35);
end V;
|
----- package mem3 -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE mem3 IS
TYPE mem_type_5 IS array (Integer range <>) OF std_logic_vector(17 downto 0);
TYPE mem_type_6 IS array (Integer range <>) OF std_logic_vector(15 downto 0);
FUNCTION hex2bin (hex: character) RETURN std_logic_vector;
FUNCTION str3_slv12 (hex: string) RETURN std_logic_vector;
FUNCTION data2data (data_w: integer) RETURN integer;
FUNCTION data2addr_w (data_w: integer) RETURN integer;
FUNCTION data2data_w (data_w: integer) RETURN integer;
FUNCTION init_ram (hex: string; DATA_WIDTH_A : integer; DATA_WIDTH_B : integer) RETURN std_logic_vector;
FUNCTION init_ram1 (hex: string) RETURN mem_type_6;
FUNCTION str2slv (str: in string) RETURN std_logic_vector;
FUNCTION Valid_Address (IN_ADDR : in std_logic_vector) return boolean;
END mem3;
PACKAGE BODY mem3 IS
FUNCTION hex2bin (hex: character) RETURN std_logic_vector IS
VARIABLE result : std_logic_vector (3 downto 0);
BEGIN
CASE hex IS
WHEN '0' =>
result := "0000";
WHEN '1' =>
result := "0001";
WHEN '2' =>
result := "0010";
WHEN '3' =>
result := "0011";
WHEN '4' =>
result := "0100";
WHEN '5' =>
result := "0101";
WHEN '6' =>
result := "0110";
WHEN '7' =>
result := "0111";
WHEN '8' =>
result := "1000";
WHEN '9' =>
result := "1001";
WHEN 'A'|'a' =>
result := "1010";
WHEN 'B'|'b' =>
result := "1011";
WHEN 'C'|'c' =>
result := "1100";
WHEN 'D'|'d' =>
result := "1101";
WHEN 'E'|'e' =>
result := "1110";
WHEN 'F'|'f' =>
result := "1111";
WHEN 'X'|'x' =>
result := "XXXX";
WHEN others =>
NULL;
END CASE;
RETURN result;
END;
FUNCTION str5_slv18 (s : string(5 downto 1)) return std_logic_vector is
VARIABLE result : std_logic_vector(17 downto 0);
BEGIN
FOR i in 0 to 3 LOOP
result(((i+1)*4)-1 downto (i*4)) := hex2bin(s(i+1));
END LOOP;
result(17 downto 16) := hex2bin(s(5))(1 downto 0);
RETURN result;
END;
FUNCTION str4_slv16 (s : string(4 downto 1)) return std_logic_vector is
VARIABLE result : std_logic_vector(15 downto 0);
BEGIN
FOR i in 0 to 3 LOOP
result(((i+1)*4)-1 downto (i*4)) := hex2bin(s(i+1));
END LOOP;
RETURN result;
END;
FUNCTION str3_slv12 (hex: string) return std_logic_vector is
VARIABLE result : std_logic_vector(11 downto 0);
BEGIN
FOR i in 0 to 2 LOOP
result(((i+1)*4)-1 downto (i*4)) := hex2bin(hex(i+1));
END LOOP;
RETURN result;
END;
FUNCTION data2addr_w (data_w : integer) return integer is
VARIABLE result : integer;
BEGIN
CASE data_w IS
WHEN 1 =>
result := 13;
WHEN 2 =>
result := 12;
WHEN 4 =>
result := 11;
WHEN 9 =>
result := 10;
WHEN 18 =>
result := 9;
WHEN 36 =>
result := 8;
WHEN others =>
NULL;
END CASE;
RETURN result;
END;
FUNCTION data2data_w (data_w : integer) return integer is
VARIABLE result : integer;
BEGIN
CASE data_w IS
WHEN 1 =>
result := 1;
WHEN 2 =>
result := 2;
WHEN 4 =>
result := 4;
WHEN 9 =>
result := 9;
WHEN 18 =>
result := 18;
WHEN 36 =>
result := 18;
WHEN others =>
NULL;
END CASE;
RETURN result;
END;
FUNCTION data2data (data_w : integer) return integer is
VARIABLE result : integer;
BEGIN
CASE data_w IS
WHEN 1 =>
result := 8;
WHEN 2 =>
result := 4;
WHEN 4 =>
result := 2;
WHEN 9 =>
result := 36864;
WHEN 18 =>
result := 36864;
WHEN 36 =>
result := 36864;
WHEN others =>
NULL;
END CASE;
RETURN result;
END;
FUNCTION init_ram (hex: string; DATA_WIDTH_A : integer; DATA_WIDTH_B : integer) RETURN std_logic_vector IS
CONSTANT length : integer := hex'length;
VARIABLE result1 : mem_type_5 (0 to ((length/5)-1));
VARIABLE result : std_logic_vector(((length*18)/5)-1 downto 0);
BEGIN
FOR i in 0 to ((length/5)-1) LOOP
result1(i) := str5_slv18(hex((i+1)*5 downto (i*5)+1));
END LOOP;
IF (DATA_WIDTH_A >= 9 and DATA_WIDTH_B >= 9) THEN
FOR j in 0 to 511 LOOP
result(((j*18) + 17) downto (j*18)) := result1(j)(17 downto 0);
END LOOP;
ELSE
FOR j in 0 to 511 LOOP
result(((j*18) + 7) downto (j*18)) := result1(j)(7 downto 0);
result((j*18) + 8) := '0';
result(((j*18) + 16) downto ((j*18) + 9)) := result1(j)(15 downto 8);
result((j*18) + 17) := '0';
END LOOP;
END IF;
RETURN result;
END;
FUNCTION init_ram1 (hex: string) RETURN mem_type_6 IS
CONSTANT length : integer := hex'length;
VARIABLE result : mem_type_6 (0 to ((length/4)-1));
BEGIN
FOR i in 0 to ((length/4)-1) LOOP
result(i) := str4_slv16(hex((i+1)*4 downto (i*4)+1));
END LOOP;
RETURN result;
END;
-- String to std_logic_vector
FUNCTION str2slv (
str : in string
) return std_logic_vector is
variable j : integer := str'length;
variable slv : std_logic_vector (str'length downto 1);
begin
for i in str'low to str'high loop
case str(i) is
when '0' => slv(j) := '0';
when '1' => slv(j) := '1';
when 'X' => slv(j) := 'X';
when 'U' => slv(j) := 'U';
when others => slv(j) := 'X';
end case;
j := j - 1;
end loop;
return slv;
end str2slv;
function Valid_Address (
IN_ADDR : in std_logic_vector
) return boolean is
variable v_Valid_Flag : boolean := TRUE;
begin
for i in IN_ADDR'high downto IN_ADDR'low loop
if (IN_ADDR(i) /= '0' and IN_ADDR(i) /= '1') then
v_Valid_Flag := FALSE;
end if;
end loop;
return v_Valid_Flag;
end Valid_Address;
END mem3 ;
--
-----cell dp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
--use ieee.std_logic_unsigned.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
library grlib;
use grlib.stdlib.all;
-- entity declaration --
ENTITY dp8ka IS
GENERIC (
DATA_WIDTH_A : Integer := 18;
DATA_WIDTH_B : Integer := 18;
REGMODE_A : String := "NOREG";
REGMODE_B : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_A : String := "000";
CSDECODE_B : String := "000";
WRITEMODE_A : String := "NORMAL";
WRITEMODE_B : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-- miscellaneous vital GENERICs
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "dp8ka";
-- input SIGNAL delays
tipd_ada12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ada0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia17 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia16 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia15 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia14 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia13 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dia0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_clka : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_cea : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_wea : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csa0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csa1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csa2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_rsta : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_adb0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib17 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib16 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib15 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib14 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib13 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib12 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib11 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib10 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib9 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib8 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib7 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib6 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib5 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib4 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib3 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_dib0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_clkb : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_ceb : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_web : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csb0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csb1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_csb2 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_rstb : VitalDelayType01 := (0.0 ns, 0.0 ns);
-- propagation delays
-- setup and hold constraints
-- pulse width constraints
tperiod_clka : VitalDelayType := 0.001 ns;
tpw_clka_posedge : VitalDelayType := 0.001 ns;
tpw_clka_negedge : VitalDelayType := 0.001 ns;
tperiod_clkb : VitalDelayType := 0.001 ns;
tpw_clkb_posedge : VitalDelayType := 0.001 ns;
tpw_clkb_negedge : VitalDelayType := 0.001 ns);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic := 'X';
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic := 'X';
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic := 'X';
ada9, ada10, ada11, ada12 : in std_logic := 'X';
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic := 'X';
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic := 'X';
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic := 'X';
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic := 'X';
adb9, adb10, adb11, adb12 : in std_logic := 'X';
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic := 'X';
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic := 'X';
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic := 'X';
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic := 'X';
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic := 'X'
);
ATTRIBUTE Vital_Level0 OF dp8ka : ENTITY IS TRUE;
END dp8ka ;
-- ARCHITECTURE body --
ARCHITECTURE V OF dp8ka IS
ATTRIBUTE Vital_Level0 OF V : ARCHITECTURE IS TRUE;
--SIGNAL DECLARATIONS----
SIGNAL ada_ipd : std_logic_vector(12 downto 0) := (others => '0');
SIGNAL dia_ipd : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL clka_ipd : std_logic := '0';
SIGNAL cea_ipd : std_logic := '0';
SIGNAL wrea_ipd : std_logic := '0';
SIGNAL csa_ipd : std_logic_vector(2 downto 0) := "000";
SIGNAL rsta_ipd : std_logic := '0';
SIGNAL adb_ipd : std_logic_vector(12 downto 0) := "XXXXXXXXXXXXX";
SIGNAL dib_ipd : std_logic_vector(17 downto 0) := "XXXXXXXXXXXXXXXXXX";
SIGNAL clkb_ipd : std_logic := '0';
SIGNAL ceb_ipd : std_logic := '0';
SIGNAL wreb_ipd : std_logic := '0';
SIGNAL csb_ipd : std_logic_vector(2 downto 0) := "000";
SIGNAL rstb_ipd : std_logic := '0';
SIGNAL csa_en : std_logic := '0';
SIGNAL csb_en : std_logic := '0';
SIGNAL g_reset : std_logic := '0';
CONSTANT ADDR_WIDTH_A : integer := data2addr_w(DATA_WIDTH_A);
CONSTANT ADDR_WIDTH_B : integer := data2addr_w(DATA_WIDTH_B);
CONSTANT new_data_width_a : integer := data2data_w(DATA_WIDTH_A);
CONSTANT new_data_width_b : integer := data2data_w(DATA_WIDTH_B);
CONSTANT div_a : integer := data2data(DATA_WIDTH_A);
CONSTANT div_b : integer := data2data(DATA_WIDTH_B);
SIGNAL dia_node : std_logic_vector((new_data_width_a - 1) downto 0) := (others => '0');
SIGNAL dib_node : std_logic_vector((new_data_width_b - 1) downto 0) := (others => '0');
SIGNAL ada_node : std_logic_vector((ADDR_WIDTH_A - 1) downto 0) := (others => '0');
SIGNAL adb_node : std_logic_vector((ADDR_WIDTH_B - 1) downto 0) := (others => '0');
SIGNAL diab_node : std_logic_vector(35 downto 0) := (others => '0');
SIGNAL rsta_int : std_logic := '0';
SIGNAL rstb_int : std_logic := '0';
SIGNAL rsta_reg : std_logic := '0';
SIGNAL rstb_reg : std_logic := '0';
SIGNAL reseta : std_logic := '0';
SIGNAL resetb : std_logic := '0';
SIGNAL dia_reg : std_logic_vector((new_data_width_a - 1) downto 0) := (others => '0');
SIGNAL dib_reg : std_logic_vector((new_data_width_b - 1) downto 0) := (others => '0');
SIGNAL ada_reg : std_logic_vector((ADDR_WIDTH_A - 1) downto 0);
SIGNAL adb_reg : std_logic_vector((ADDR_WIDTH_B - 1) downto 0);
SIGNAL diab_reg : std_logic_vector(35 downto 0) := (others => '0');
SIGNAL wrena_reg : std_logic := '0';
SIGNAL clka_valid : std_logic := '0';
SIGNAL clkb_valid : std_logic := '0';
SIGNAL clka_valid1 : std_logic := '0';
SIGNAL clkb_valid1 : std_logic := '0';
SIGNAL wrenb_reg : std_logic := '0';
SIGNAL rena_reg : std_logic := '0';
SIGNAL renb_reg : std_logic := '0';
SIGNAL rsta_sig : std_logic := '0';
SIGNAL rstb_sig : std_logic := '0';
SIGNAL doa_node : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_node_tr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_node_wt : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_node_rbr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node_tr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node_wt : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_node_rbr : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_reg : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_reg : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doab_reg : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL doa_int : std_logic_vector(17 downto 0) := (others => '0');
SIGNAL dob_int : std_logic_vector(17 downto 0) := (others => '0');
CONSTANT initval : string(2560 downto 1) := (
initval_1f(3 to 82)&initval_1e(3 to 82)&initval_1d(3 to 82)&initval_1c(3 to 82)&
initval_1b(3 to 82)&initval_1a(3 to 82)&initval_19(3 to 82)&initval_18(3 to 82)&
initval_17(3 to 82)&initval_16(3 to 82)&initval_15(3 to 82)&initval_14(3 to 82)&
initval_13(3 to 82)&initval_12(3 to 82)&initval_11(3 to 82)&initval_10(3 to 82)&
initval_0f(3 to 82)&initval_0e(3 to 82)&initval_0d(3 to 82)&initval_0c(3 to 82)&
initval_0b(3 to 82)&initval_0a(3 to 82)&initval_09(3 to 82)&initval_08(3 to 82)&
initval_07(3 to 82)&initval_06(3 to 82)&initval_05(3 to 82)&initval_04(3 to 82)&
initval_03(3 to 82)&initval_02(3 to 82)&initval_01(3 to 82)&initval_00(3 to 82));
SIGNAL MEM : std_logic_vector(9215 downto 0) := init_ram (initval, DATA_WIDTH_A, DATA_WIDTH_B);
SIGNAL j : integer := 0;
BEGIN
-----------------------
-- input path delays
-----------------------
WireDelay : BLOCK
BEGIN
VitalWireDelay(ada_ipd(0), ada0, tipd_ada0);
VitalWireDelay(ada_ipd(1), ada1, tipd_ada1);
VitalWireDelay(ada_ipd(2), ada2, tipd_ada2);
VitalWireDelay(ada_ipd(3), ada3, tipd_ada3);
VitalWireDelay(ada_ipd(4), ada4, tipd_ada4);
VitalWireDelay(ada_ipd(5), ada5, tipd_ada5);
VitalWireDelay(ada_ipd(6), ada6, tipd_ada6);
VitalWireDelay(ada_ipd(7), ada7, tipd_ada7);
VitalWireDelay(ada_ipd(8), ada8, tipd_ada8);
VitalWireDelay(ada_ipd(9), ada9, tipd_ada9);
VitalWireDelay(ada_ipd(10), ada10, tipd_ada10);
VitalWireDelay(ada_ipd(11), ada11, tipd_ada11);
VitalWireDelay(ada_ipd(12), ada12, tipd_ada12);
VitalWireDelay(dia_ipd(0), dia0, tipd_dia0);
VitalWireDelay(dia_ipd(1), dia1, tipd_dia1);
VitalWireDelay(dia_ipd(2), dia2, tipd_dia2);
VitalWireDelay(dia_ipd(3), dia3, tipd_dia3);
VitalWireDelay(dia_ipd(4), dia4, tipd_dia4);
VitalWireDelay(dia_ipd(5), dia5, tipd_dia5);
VitalWireDelay(dia_ipd(6), dia6, tipd_dia6);
VitalWireDelay(dia_ipd(7), dia7, tipd_dia7);
VitalWireDelay(dia_ipd(8), dia8, tipd_dia8);
VitalWireDelay(dia_ipd(9), dia9, tipd_dia9);
VitalWireDelay(dia_ipd(10), dia10, tipd_dia10);
VitalWireDelay(dia_ipd(11), dia11, tipd_dia11);
VitalWireDelay(dia_ipd(12), dia12, tipd_dia12);
VitalWireDelay(dia_ipd(13), dia13, tipd_dia13);
VitalWireDelay(dia_ipd(14), dia14, tipd_dia14);
VitalWireDelay(dia_ipd(15), dia15, tipd_dia15);
VitalWireDelay(dia_ipd(16), dia16, tipd_dia16);
VitalWireDelay(dia_ipd(17), dia17, tipd_dia17);
VitalWireDelay(clka_ipd, clka, tipd_clka);
VitalWireDelay(wrea_ipd, wea, tipd_wea);
VitalWireDelay(cea_ipd, cea, tipd_cea);
VitalWireDelay(csa_ipd(0), csa0, tipd_csa0);
VitalWireDelay(csa_ipd(1), csa1, tipd_csa1);
VitalWireDelay(csa_ipd(2), csa2, tipd_csa2);
VitalWireDelay(rsta_ipd, rsta, tipd_rsta);
VitalWireDelay(adb_ipd(0), adb0, tipd_adb0);
VitalWireDelay(adb_ipd(1), adb1, tipd_adb1);
VitalWireDelay(adb_ipd(2), adb2, tipd_adb2);
VitalWireDelay(adb_ipd(3), adb3, tipd_adb3);
VitalWireDelay(adb_ipd(4), adb4, tipd_adb4);
VitalWireDelay(adb_ipd(5), adb5, tipd_adb5);
VitalWireDelay(adb_ipd(6), adb6, tipd_adb6);
VitalWireDelay(adb_ipd(7), adb7, tipd_adb7);
VitalWireDelay(adb_ipd(8), adb8, tipd_adb8);
VitalWireDelay(adb_ipd(9), adb9, tipd_adb9);
VitalWireDelay(adb_ipd(10), adb10, tipd_adb10);
VitalWireDelay(adb_ipd(11), adb11, tipd_adb11);
VitalWireDelay(adb_ipd(12), adb12, tipd_adb12);
VitalWireDelay(dib_ipd(0), dib0, tipd_dib0);
VitalWireDelay(dib_ipd(1), dib1, tipd_dib1);
VitalWireDelay(dib_ipd(2), dib2, tipd_dib2);
VitalWireDelay(dib_ipd(3), dib3, tipd_dib3);
VitalWireDelay(dib_ipd(4), dib4, tipd_dib4);
VitalWireDelay(dib_ipd(5), dib5, tipd_dib5);
VitalWireDelay(dib_ipd(6), dib6, tipd_dib6);
VitalWireDelay(dib_ipd(7), dib7, tipd_dib7);
VitalWireDelay(dib_ipd(8), dib8, tipd_dib8);
VitalWireDelay(dib_ipd(9), dib9, tipd_dib9);
VitalWireDelay(dib_ipd(10), dib10, tipd_dib10);
VitalWireDelay(dib_ipd(11), dib11, tipd_dib11);
VitalWireDelay(dib_ipd(12), dib12, tipd_dib12);
VitalWireDelay(dib_ipd(13), dib13, tipd_dib13);
VitalWireDelay(dib_ipd(14), dib14, tipd_dib14);
VitalWireDelay(dib_ipd(15), dib15, tipd_dib15);
VitalWireDelay(dib_ipd(16), dib16, tipd_dib16);
VitalWireDelay(dib_ipd(17), dib17, tipd_dib17);
VitalWireDelay(clkb_ipd, clkb, tipd_clkb);
VitalWireDelay(wreb_ipd, web, tipd_web);
VitalWireDelay(ceb_ipd, ceb, tipd_ceb);
VitalWireDelay(csb_ipd(0), csb0, tipd_csb0);
VitalWireDelay(csb_ipd(1), csb1, tipd_csb1);
VitalWireDelay(csb_ipd(2), csb2, tipd_csb2);
VitalWireDelay(rstb_ipd, rstb, tipd_rstb);
END BLOCK;
GLOBALRESET : PROCESS (purnet, gsrnet)
BEGIN
IF (GSR = "DISABLED") THEN
g_reset <= purnet;
ELSE
g_reset <= purnet AND gsrnet;
END IF;
END PROCESS;
rsta_sig <= rsta_ipd or (not g_reset);
rstb_sig <= rstb_ipd or (not g_reset);
-- set_reset <= g_reset and (not reset_ipd);
ada_node <= ada_ipd(12 downto (13 - ADDR_WIDTH_A));
adb_node <= adb_ipd(12 downto (13 - ADDR_WIDTH_B));
-- chip select A decode
P1 : PROCESS(csa_ipd)
BEGIN
IF (csa_ipd = "000" and CSDECODE_A = "000") THEN
csa_en <= '1';
ELSIF (csa_ipd = "001" and CSDECODE_A = "001") THEN
csa_en <= '1';
ELSIF (csa_ipd = "010" and CSDECODE_A = "010") THEN
csa_en <= '1';
ELSIF (csa_ipd = "011" and CSDECODE_A = "011") THEN
csa_en <= '1';
ELSIF (csa_ipd = "100" and CSDECODE_A = "100") THEN
csa_en <= '1';
ELSIF (csa_ipd = "101" and CSDECODE_A = "101") THEN
csa_en <= '1';
ELSIF (csa_ipd = "110" and CSDECODE_A = "110") THEN
csa_en <= '1';
ELSIF (csa_ipd = "111" and CSDECODE_A = "111") THEN
csa_en <= '1';
ELSE
csa_en <= '0';
END IF;
END PROCESS;
P2 : PROCESS(csb_ipd)
BEGIN
IF (csb_ipd = "000" and CSDECODE_B = "000") THEN
csb_en <= '1';
ELSIF (csb_ipd = "001" and CSDECODE_B = "001") THEN
csb_en <= '1';
ELSIF (csb_ipd = "010" and CSDECODE_B = "010") THEN
csb_en <= '1';
ELSIF (csb_ipd = "011" and CSDECODE_B = "011") THEN
csb_en <= '1';
ELSIF (csb_ipd = "100" and CSDECODE_B = "100") THEN
csb_en <= '1';
ELSIF (csb_ipd = "101" and CSDECODE_B = "101") THEN
csb_en <= '1';
ELSIF (csb_ipd = "110" and CSDECODE_B = "110") THEN
csb_en <= '1';
ELSIF (csb_ipd = "111" and CSDECODE_B = "111") THEN
csb_en <= '1';
ELSE
csb_en <= '0';
END IF;
END PROCESS;
P3 : PROCESS(dia_ipd)
BEGIN
CASE DATA_WIDTH_A IS
WHEN 1 =>
dia_node <= dia_ipd(11 downto 11);
WHEN 2 =>
dia_node <= (dia_ipd(1), dia_ipd(11));
WHEN 4 =>
dia_node <= dia_ipd(3 downto 0);
WHEN 9 =>
dia_node <= dia_ipd(8 downto 0);
WHEN 18 =>
dia_node <= dia_ipd;
WHEN 36 =>
dia_node <= dia_ipd;
WHEN others =>
NULL;
END CASE;
END PROCESS;
P4 : PROCESS(dib_ipd)
BEGIN
CASE DATA_WIDTH_B IS
WHEN 1 =>
dib_node <= dib_ipd(11 downto 11);
WHEN 2 =>
dib_node <= (dib_ipd(1), dib_ipd(11));
WHEN 4 =>
dib_node <= dib_ipd(3 downto 0);
WHEN 9 =>
dib_node <= dib_ipd(8 downto 0);
WHEN 18 =>
dib_node <= dib_ipd;
WHEN 36 =>
dib_node <= dib_ipd;
WHEN others =>
NULL;
END CASE;
END PROCESS;
diab_node <= (dib_ipd & dia_ipd);
P107 : PROCESS(clka_ipd)
BEGIN
IF (clka_ipd'event and clka_ipd = '1' and clka_ipd'last_value = '0') THEN
IF ((g_reset = '0') or (rsta_ipd = '1')) THEN
clka_valid <= '0';
ELSE
IF (cea_ipd = '1') THEN
IF (csa_en = '1') THEN
clka_valid <= '1', '0' after 0.01 ns;
ELSE
clka_valid <= '0';
END IF;
ELSE
clka_valid <= '0';
END IF;
END IF;
END IF;
END PROCESS;
P108 : PROCESS(clkb_ipd)
BEGIN
IF (clkb_ipd'event and clkb_ipd = '1' and clkb_ipd'last_value = '0') THEN
IF ((g_reset = '0') or (rstb_ipd = '1')) THEN
clkb_valid <= '0';
ELSE
IF (ceb_ipd = '1') THEN
IF (csb_en = '1') THEN
clkb_valid <= '1', '0' after 0.01 ns;
ELSE
clkb_valid <= '0';
END IF;
ELSE
clkb_valid <= '0';
END IF;
END IF;
END IF;
END PROCESS;
clka_valid1 <= clka_valid;
clkb_valid1 <= clkb_valid;
P7 : PROCESS(g_reset, rsta_ipd, rstb_ipd, clka_ipd, clkb_ipd)
BEGIN
IF (g_reset = '0') THEN
dia_reg <= (others => '0');
diab_reg <= (others => '0');
ada_reg <= (others => '0');
wrena_reg <= '0';
rena_reg <= '0';
ELSIF (RESETMODE = "ASYNC") THEN
IF (rsta_ipd = '1') THEN
dia_reg <= (others => '0');
diab_reg <= (others => '0');
ada_reg <= (others => '0');
wrena_reg <= '0';
rena_reg <= '0';
ELSIF (clka_ipd'event and clka_ipd = '1') THEN
IF (cea_ipd = '1') THEN
dia_reg <= dia_node;
diab_reg <= diab_node;
ada_reg <= ada_node;
wrena_reg <= (wrea_ipd and csa_en);
rena_reg <= ((not wrea_ipd) and csa_en);
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clka_ipd'event and clka_ipd = '1') THEN
IF (rsta_ipd = '1') THEN
dia_reg <= (others => '0');
diab_reg <= (others => '0');
ada_reg <= (others => '0');
wrena_reg <= '0';
rena_reg <= '0';
ELSIF (cea_ipd = '1') THEN
dia_reg <= dia_node;
diab_reg <= diab_node;
ada_reg <= ada_node;
wrena_reg <= (wrea_ipd and csa_en);
rena_reg <= ((not wrea_ipd) and csa_en);
END IF;
END IF;
END IF;
IF (g_reset = '0') THEN
dib_reg <= (others => '0');
adb_reg <= (others => '0');
wrenb_reg <= '0';
renb_reg <= '0';
ELSIF (RESETMODE = "ASYNC") THEN
IF (rstb_ipd = '1') THEN
dib_reg <= (others => '0');
adb_reg <= (others => '0');
wrenb_reg <= '0';
renb_reg <= '0';
ELSIF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (ceb_ipd = '1') THEN
dib_reg <= dib_node;
adb_reg <= adb_node;
wrenb_reg <= (wreb_ipd and csb_en);
renb_reg <= ((not wreb_ipd) and csb_en);
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (rstb_ipd = '1') THEN
dib_reg <= (others => '0');
adb_reg <= (others => '0');
wrenb_reg <= '0';
renb_reg <= '0';
ELSIF (ceb_ipd = '1') THEN
dib_reg <= dib_node;
adb_reg <= adb_node;
wrenb_reg <= (wreb_ipd and csb_en);
renb_reg <= ((not wreb_ipd) and csb_en);
END IF;
END IF;
END IF;
END PROCESS;
-- Warning for collision
PW : PROCESS(ada_reg, adb_reg, wrena_reg, wrenb_reg, clka_valid, clkb_valid, rena_reg,
renb_reg)
VARIABLE WADDR_A_VALID : boolean := TRUE;
VARIABLE WADDR_B_VALID : boolean := TRUE;
VARIABLE ADDR_A : integer := 0;
VARIABLE ADDR_B : integer := 0;
VARIABLE DN_ADDR_A : integer := 0;
VARIABLE UP_ADDR_A : integer := 0;
VARIABLE DN_ADDR_B : integer := 0;
VARIABLE UP_ADDR_B : integer := 0;
BEGIN
WADDR_A_VALID := Valid_Address (ada_reg);
WADDR_B_VALID := Valid_Address (adb_reg);
IF (WADDR_A_VALID = TRUE) THEN
ADDR_A := conv_integer(ada_reg);
END IF;
IF (WADDR_B_VALID = TRUE) THEN
ADDR_B := conv_integer(adb_reg);
END IF;
DN_ADDR_A := (ADDR_A * DATA_WIDTH_A);
UP_ADDR_A := (((ADDR_A + 1) * DATA_WIDTH_A) - 1);
DN_ADDR_B := (ADDR_B * DATA_WIDTH_B);
UP_ADDR_B := (((ADDR_B + 1) * DATA_WIDTH_B) - 1);
IF ((wrena_reg = '1' and clka_valid = '1') and (wrenb_reg = '1' and clkb_valid = '1')) THEN
IF (not((UP_ADDR_B <= DN_ADDR_A) or (DN_ADDR_B >= UP_ADDR_A))) THEN
assert false
report " Write collision! Writing in the same memory location using Port A and Port B will cause the memory content invalid."
severity error;
END IF;
END IF;
-- IF ((wrena_reg = '1' and clka_valid = '1') and (renb_reg = '1' and clkb_valid = '1')) THEN
-- IF (not((UP_ADDR_B <= DN_ADDR_A) or (DN_ADDR_B >= UP_ADDR_A))) THEN
-- assert false
-- report " Write/Read collision! Writing through Port A and reading through Port B from the same memory location may give wrong output."
-- severity warning;
-- END IF;
-- END IF;
-- IF ((rena_reg = '1' and clka_valid = '1') and (wrenb_reg = '1' and clkb_valid = '1')) THEN
-- IF (not((UP_ADDR_A <= DN_ADDR_B) or (DN_ADDR_A >= UP_ADDR_B))) THEN
-- assert false
-- report " Write/Read collision! Writing through Port B and reading through Port A from the same memory location may give wrong output."
-- severity warning;
-- END IF;
-- END IF;
END PROCESS;
-- Writing to the memory
P8 : PROCESS(ada_reg, dia_reg, diab_reg, wrena_reg, dib_reg, adb_reg,
wrenb_reg, clka_valid, clkb_valid)
VARIABLE WADDR_A_VALID : boolean := TRUE;
VARIABLE WADDR_B_VALID : boolean := TRUE;
VARIABLE WADDR_A : integer := 0;
VARIABLE WADDR_B : integer := 0;
VARIABLE dout_node_rbr : std_logic_vector(35 downto 0);
BEGIN
WADDR_A_VALID := Valid_Address (ada_reg);
WADDR_B_VALID := Valid_Address (adb_reg);
IF (WADDR_A_VALID = TRUE) THEN
WADDR_A := conv_integer(ada_reg);
END IF;
IF (WADDR_B_VALID = TRUE) THEN
WADDR_B := conv_integer(adb_reg);
END IF;
IF (DATA_WIDTH_A = 36) THEN
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
dout_node_rbr(i) := MEM((WADDR_A * DATA_WIDTH_A) + i);
END LOOP;
doa_node_rbr <= dout_node_rbr(17 downto 0);
dob_node_rbr <= dout_node_rbr(35 downto 18);
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i) <= diab_reg(i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 9) <= diab_reg(i + 9);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 18) <= diab_reg(i + 18);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 27) <= diab_reg(i + 27);
END LOOP;
END IF;
ELSE
IF (DATA_WIDTH_A = 18) THEN
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i) <= dia_reg(i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i + 9) <= dia_reg(i + 9);
END LOOP;
END IF;
ELSIF (DATA_WIDTH_A = 9) THEN
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
MEM((WADDR_A * DATA_WIDTH_A) + i) <= dia_reg(i);
END LOOP;
END IF;
ELSE
IF (wrena_reg = '1' and clka_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node_rbr(i) <= MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
MEM((WADDR_A * DATA_WIDTH_A) + (WADDR_A / div_a) + i) <= dia_reg(i);
END LOOP;
END IF;
END IF;
IF (DATA_WIDTH_B = 18) THEN
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_B * DATA_WIDTH_B) + i) <= dib_reg(i);
END LOOP;
FOR i IN 0 TO 8 LOOP
MEM((WADDR_B * DATA_WIDTH_B) + i + 9) <= dib_reg(i + 9);
END LOOP;
END IF;
ELSIF (DATA_WIDTH_B = 9) THEN
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
MEM((WADDR_B * DATA_WIDTH_B) + i) <= dib_reg(i);
END LOOP;
END IF;
ELSE
IF (wrenb_reg = '1' and clkb_valid = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node_rbr(i) <= MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i);
END LOOP;
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
MEM((WADDR_B * DATA_WIDTH_B) + (WADDR_B / div_b) + i) <= dib_reg(i);
END LOOP;
END IF;
END IF;
END IF;
END PROCESS;
P9 : PROCESS(ada_reg, rena_reg, adb_reg, renb_reg, MEM, clka_valid1, clkb_valid1, rsta_sig, rstb_sig, doa_node_rbr, dob_node_rbr)
VARIABLE RADDR_A_VALID : boolean := TRUE;
VARIABLE RADDR_B_VALID : boolean := TRUE;
VARIABLE RADDR_A : integer := 0;
VARIABLE RADDR_B : integer := 0;
VARIABLE dout_node_tr : std_logic_vector(35 downto 0);
VARIABLE dout_node_wt : std_logic_vector(35 downto 0);
BEGIN
RADDR_A_VALID := Valid_Address (ada_reg);
RADDR_B_VALID := Valid_Address (adb_reg);
IF (RADDR_A_VALID = TRUE) THEN
RADDR_A := conv_integer(ada_reg);
END IF;
IF (RADDR_B_VALID = TRUE) THEN
RADDR_B := conv_integer(adb_reg);
END IF;
IF (DATA_WIDTH_B = 36) THEN
IF (rstb_sig = '1') THEN
IF (RESETMODE = "SYNC") THEN
IF (clkb_ipd = '1') THEN
doa_node <= (others => '0');
dob_node <= (others => '0');
END IF;
ELSIF (RESETMODE = "ASYNC") THEN
doa_node <= (others => '0');
dob_node <= (others => '0');
END IF;
ELSIF (clkb_valid1'event and clkb_valid1 = '1') THEN
IF (renb_reg = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dout_node_tr(i) := MEM((RADDR_B * DATA_WIDTH_B) + i);
END LOOP;
doa_node <= dout_node_tr(17 downto 0);
dob_node <= dout_node_tr(35 downto 18);
ELSIF (renb_reg = '0') THEN
IF (WRITEMODE_B = "WRITETHROUGH") THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dout_node_wt(i) := MEM((RADDR_B * DATA_WIDTH_B) + i);
END LOOP;
doa_node <= dout_node_wt(17 downto 0);
dob_node <= dout_node_wt(35 downto 18);
ELSIF (WRITEMODE_B = "READBEFOREWRITE") THEN
doa_node <= doa_node_rbr;
dob_node <= dob_node_rbr;
END IF;
END IF;
END IF;
ELSE
IF (rsta_sig = '1') THEN
IF (RESETMODE = "SYNC") THEN
IF (clka_ipd = '1') THEN
doa_node <= (others => '0');
END IF;
ELSIF (RESETMODE = "ASYNC") THEN
doa_node <= (others => '0');
END IF;
ELSIF (clka_valid1'event and clka_valid1 = '1') THEN
IF (rena_reg = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node(i) <= MEM((RADDR_A * DATA_WIDTH_A) + (RADDR_A / div_a) + i);
END LOOP;
ELSIF (rena_reg = '0') THEN
IF (WRITEMODE_A = "WRITETHROUGH") THEN
FOR i IN 0 TO (DATA_WIDTH_A - 1) LOOP
doa_node(i) <= MEM((RADDR_A * DATA_WIDTH_A) + (RADDR_A / div_a) + i);
END LOOP;
ELSIF (WRITEMODE_A = "READBEFOREWRITE") THEN
doa_node <= doa_node_rbr;
END IF;
END IF;
END IF;
IF (rstb_sig = '1') THEN
IF (RESETMODE = "SYNC") THEN
IF (clkb_ipd = '1') THEN
dob_node <= (others => '0');
END IF;
ELSIF (RESETMODE = "ASYNC") THEN
dob_node <= (others => '0');
END IF;
ELSIF (clkb_valid1'event and clkb_valid1 = '1') THEN
IF (renb_reg = '1') THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node(i) <= MEM((RADDR_B * DATA_WIDTH_B) + (RADDR_B / div_b) + i);
END LOOP;
ELSIF (renb_reg = '0') THEN
IF (WRITEMODE_B = "WRITETHROUGH") THEN
FOR i IN 0 TO (DATA_WIDTH_B - 1) LOOP
dob_node(i) <= MEM((RADDR_B * DATA_WIDTH_B) + (RADDR_B / div_b) + i);
END LOOP;
ELSIF (WRITEMODE_B = "READBEFOREWRITE") THEN
dob_node <= dob_node_rbr;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
P10 : PROCESS(g_reset, rsta_ipd, rstb_ipd, clka_ipd, clkb_ipd)
BEGIN
IF (g_reset = '0') THEN
doa_reg <= (others => '0');
ELSIF (RESETMODE = "ASYNC") THEN
IF (rsta_ipd = '1') THEN
doa_reg <= (others => '0');
ELSIF (clka_ipd'event and clka_ipd = '1') THEN
IF (cea_ipd = '1') THEN
doa_reg <= doa_node;
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clka_ipd'event and clka_ipd = '1') THEN
IF (cea_ipd = '1') THEN
IF (rsta_ipd = '1') THEN
doa_reg <= (others => '0');
ELSIF (rsta_ipd = '0') THEN
doa_reg <= doa_node;
END IF;
END IF;
END IF;
END IF;
IF (g_reset = '0') THEN
dob_reg <= (others => '0');
doab_reg <= (others => '0');
ELSIF (RESETMODE = "ASYNC") THEN
IF (rstb_ipd = '1') THEN
dob_reg <= (others => '0');
doab_reg <= (others => '0');
ELSIF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (ceb_ipd = '1') THEN
dob_reg <= dob_node;
doab_reg <= doa_node;
END IF;
END IF;
ELSIF (RESETMODE = "SYNC") THEN
IF (clkb_ipd'event and clkb_ipd = '1') THEN
IF (ceb_ipd = '1') THEN
IF (rstb_ipd = '1') THEN
dob_reg <= (others => '0');
doab_reg <= (others => '0');
ELSIF (rstb_ipd = '0') THEN
dob_reg <= dob_node;
doab_reg <= doa_node;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
P11 : PROCESS(doa_node, dob_node, doa_reg, dob_reg, doab_reg)
BEGIN
IF (REGMODE_A = "OUTREG") THEN
IF (DATA_WIDTH_B = 36) THEN
doa_int <= doab_reg;
ELSE
doa_int <= doa_reg;
END IF;
ELSE
doa_int <= doa_node;
END IF;
IF (REGMODE_B = "OUTREG") THEN
dob_int <= dob_reg;
ELSE
dob_int <= dob_node;
END IF;
END PROCESS;
(doa17, doa16, doa15, doa14, doa13, doa12, doa11, doa10, doa9, doa8, doa7, doa6,
doa5, doa4, doa3, doa2, doa1, doa0) <= doa_int;
(dob17, dob16, dob15, dob14, dob13, dob12, dob11, dob10, dob9, dob8, dob7, dob6,
dob5, dob4, dob3, dob2, dob1, dob0) <= dob_int;
END V;
--
-----cell sp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
-- entity declaration --
ENTITY sp8ka IS
GENERIC (
DATA_WIDTH : Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE : String := "000";
WRITEMODE : String := "NORMAL";
GSR : String := "ENABLED";
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000");
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
ad0, ad1, ad2, ad3, ad4, ad5, ad6, ad7, ad8 : in std_logic := 'X';
ad9, ad10, ad11, ad12 : in std_logic := 'X';
ce, clk, we, cs0, cs1, cs2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X'
);
ATTRIBUTE Vital_Level0 OF sp8ka : ENTITY IS TRUE;
END sp8ka ;
architecture V of sp8ka is
signal lo: std_logic := '0';
signal hi: std_logic := '1';
component dp8ka
GENERIC(
DATA_WIDTH_A : in Integer;
DATA_WIDTH_B : in Integer;
REGMODE_A : in String;
REGMODE_B : in String;
RESETMODE : in String;
CSDECODE_A : in String;
CSDECODE_B : in String;
WRITEMODE_A : in String;
WRITEMODE_B : in String;
GSR : in String;
initval_00 : in string;
initval_01 : in string;
initval_02 : in string;
initval_03 : in string;
initval_04 : in string;
initval_05 : in string;
initval_06 : in string;
initval_07 : in string;
initval_08 : in string;
initval_09 : in string;
initval_0a : in string;
initval_0b : in string;
initval_0c : in string;
initval_0d : in string;
initval_0e : in string;
initval_0f : in string;
initval_10 : in string;
initval_11 : in string;
initval_12 : in string;
initval_13 : in string;
initval_14 : in string;
initval_15 : in string;
initval_16 : in string;
initval_17 : in string;
initval_18 : in string;
initval_19 : in string;
initval_1a : in string;
initval_1b : in string;
initval_1c : in string;
initval_1d : in string;
initval_1e : in string;
initval_1f : in string);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic;
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic;
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic;
ada9, ada10, ada11, ada12 : in std_logic;
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic;
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic;
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic;
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic;
adb9, adb10, adb11, adb12 : in std_logic;
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic;
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic;
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic;
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic;
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic
);
END COMPONENT;
begin
-- component instantiation statements
dp8ka_inst : dp8ka
generic map (DATA_WIDTH_A => DATA_WIDTH,
DATA_WIDTH_B => DATA_WIDTH,
REGMODE_A => REGMODE,
REGMODE_B => REGMODE,
RESETMODE => RESETMODE,
CSDECODE_A => CSDECODE,
CSDECODE_B => CSDECODE,
WRITEMODE_A => WRITEMODE,
WRITEMODE_B => WRITEMODE,
GSR => GSR,
initval_00 => initval_00,
initval_01 => initval_01,
initval_02 => initval_02,
initval_03 => initval_03,
initval_04 => initval_04,
initval_05 => initval_05,
initval_06 => initval_06,
initval_07 => initval_07,
initval_08 => initval_08,
initval_09 => initval_09,
initval_0a => initval_0a,
initval_0b => initval_0b,
initval_0c => initval_0c,
initval_0d => initval_0d,
initval_0e => initval_0e,
initval_0f => initval_0f,
initval_10 => initval_10,
initval_11 => initval_11,
initval_12 => initval_12,
initval_13 => initval_13,
initval_14 => initval_14,
initval_15 => initval_15,
initval_16 => initval_16,
initval_17 => initval_17,
initval_18 => initval_18,
initval_19 => initval_19,
initval_1a => initval_1a,
initval_1b => initval_1b,
initval_1c => initval_1c,
initval_1d => initval_1d,
initval_1e => initval_1e,
initval_1f => initval_1f)
port map (dia0 => di0, dia1 => di1, dia2 => di2, dia3 => di3,
dia4 => di4, dia5 => di5, dia6 => di6, dia7 => di7, dia8 => di8,
dia9 => di9, dia10 => di10, dia11 => di11, dia12 => di12, dia13 => di13,
dia14 => di14, dia15 => di15, dia16 => di16, dia17 => di17, dib0 => lo,
dib1 => lo, dib2 => lo, dib3 => lo, dib4 => lo, dib5 => lo,
dib6 => lo, dib7 => lo, dib8 => lo, dib9 => lo, dib10 => lo,
dib11 => lo, dib12 => lo, dib13 => lo, dib14 => lo, dib15 => lo,
dib16 => lo, dib17 => lo,
cea => ce, clka => clk, wea => we, csa0 => cs0, csa1 => cs1, csa2 => cs2,
rsta => rst, ada0 => ad0, ada1 => ad1, ada2 => ad2, ada3 => ad3,
ada4 => ad4, ada5 => ad5, ada6 => ad6, ada7 => ad7, ada8 => ad8,
ada9 => ad9, ada10 => ad10, ada11 => ad11, ada12 => ad12,
ceb => lo, clkb => lo, web => lo, csb0 => lo, csb1 => lo, csb2 => lo,
rstb => hi, adb0 => lo, adb1 => lo, adb2 => lo, adb3 => lo,
adb4 => lo, adb5 => lo, adb6 => lo, adb7 => lo, adb8 => lo,
adb9 => lo, adb10 => lo, adb11 => lo, adb12 => lo,
dob0 => open, dob1 => open, dob2 => open, dob3 => open,
dob4 => open, dob5 => open, dob6 => open, dob7 => open, dob8 => open,
dob9 => open, dob10 => open, dob11 => open, dob12 => open, dob13 => open,
dob14 => open, dob15 => open, dob16 => open, dob17 => open, doa0 => do0,
doa1 => do1, doa2 => do2, doa3 => do3, doa4 => do4, doa5 => do5,
doa6 => do6, doa7 => do7, doa8 => do8, doa9 => do9, doa10 => do10,
doa11 => do11, doa12 => do12, doa13 => do13, doa14 => do14, doa15 => do15,
doa16 => do16, doa17 => do17);
end V;
--
-----cell pdp8ka----
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;
use ieee.vital_primitives.all;
library ec;
use ec.global.gsrnet;
use ec.global.purnet;
use ec.mem3.all;
-- entity declaration --
ENTITY pdp8ka IS
GENERIC (
DATA_WIDTH_W : Integer := 18;
DATA_WIDTH_R : Integer := 18;
REGMODE : String := "NOREG";
RESETMODE : String := "ASYNC";
CSDECODE_W : String := "000";
CSDECODE_R : String := "000";
GSR : String := "ENABLED";
initval_00 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_01 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_02 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_03 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_04 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_05 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_06 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_07 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_08 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_09 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_0f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_10 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_11 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_12 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_13 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_14 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_15 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_16 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_17 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_18 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_19 : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1a : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1b : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1c : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1d : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1e : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
initval_1f : String := "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000");
PORT(
di0, di1, di2, di3, di4, di5, di6, di7, di8 : in std_logic := 'X';
di9, di10, di11, di12, di13, di14, di15, di16, di17 : in std_logic := 'X';
di18, di19, di20, di21, di22, di23, di24, di25, di26 : in std_logic := 'X';
di27, di28, di29, di30, di31, di32, di33, di34, di35 : in std_logic := 'X';
adw0, adw1, adw2, adw3, adw4, adw5, adw6, adw7, adw8 : in std_logic := 'X';
adw9, adw10, adw11, adw12 : in std_logic := 'X';
cew, clkw, we, csw0, csw1, csw2 : in std_logic := 'X';
adr0, adr1, adr2, adr3, adr4, adr5, adr6, adr7, adr8 : in std_logic := 'X';
adr9, adr10, adr11, adr12 : in std_logic := 'X';
cer, clkr, csr0, csr1, csr2, rst : in std_logic := 'X';
do0, do1, do2, do3, do4, do5, do6, do7, do8 : out std_logic := 'X';
do9, do10, do11, do12, do13, do14, do15, do16, do17 : out std_logic := 'X';
do18, do19, do20, do21, do22, do23, do24, do25, do26 : out std_logic := 'X';
do27, do28, do29, do30, do31, do32, do33, do34, do35 : out std_logic := 'X'
);
ATTRIBUTE Vital_Level0 OF pdp8ka : ENTITY IS TRUE;
END pdp8ka ;
architecture V of pdp8ka is
signal lo: std_logic := '0';
component dp8ka
GENERIC(
DATA_WIDTH_A : in Integer;
DATA_WIDTH_B : in Integer;
REGMODE_A : in String;
REGMODE_B : in String;
RESETMODE : in String;
CSDECODE_A : in String;
CSDECODE_B : in String;
GSR : in String;
initval_00 : in string;
initval_01 : in string;
initval_02 : in string;
initval_03 : in string;
initval_04 : in string;
initval_05 : in string;
initval_06 : in string;
initval_07 : in string;
initval_08 : in string;
initval_09 : in string;
initval_0a : in string;
initval_0b : in string;
initval_0c : in string;
initval_0d : in string;
initval_0e : in string;
initval_0f : in string;
initval_10 : in string;
initval_11 : in string;
initval_12 : in string;
initval_13 : in string;
initval_14 : in string;
initval_15 : in string;
initval_16 : in string;
initval_17 : in string;
initval_18 : in string;
initval_19 : in string;
initval_1a : in string;
initval_1b : in string;
initval_1c : in string;
initval_1d : in string;
initval_1e : in string;
initval_1f : in string);
PORT(
dia0, dia1, dia2, dia3, dia4, dia5, dia6, dia7, dia8 : in std_logic;
dia9, dia10, dia11, dia12, dia13, dia14, dia15, dia16, dia17 : in std_logic;
ada0, ada1, ada2, ada3, ada4, ada5, ada6, ada7, ada8 : in std_logic;
ada9, ada10, ada11, ada12 : in std_logic;
cea, clka, wea, csa0, csa1, csa2, rsta : in std_logic;
dib0, dib1, dib2, dib3, dib4, dib5, dib6, dib7, dib8 : in std_logic;
dib9, dib10, dib11, dib12, dib13, dib14, dib15, dib16, dib17 : in std_logic;
adb0, adb1, adb2, adb3, adb4, adb5, adb6, adb7, adb8 : in std_logic;
adb9, adb10, adb11, adb12 : in std_logic;
ceb, clkb, web, csb0, csb1, csb2, rstb : in std_logic;
doa0, doa1, doa2, doa3, doa4, doa5, doa6, doa7, doa8 : out std_logic;
doa9, doa10, doa11, doa12, doa13, doa14, doa15, doa16, doa17 : out std_logic;
dob0, dob1, dob2, dob3, dob4, dob5, dob6, dob7, dob8 : out std_logic;
dob9, dob10, dob11, dob12, dob13, dob14, dob15, dob16, dob17 : out std_logic
);
END COMPONENT;
begin
-- component instantiation statements
dp8ka_inst : dp8ka
generic map (DATA_WIDTH_A => DATA_WIDTH_W,
DATA_WIDTH_B => DATA_WIDTH_R,
REGMODE_A => REGMODE,
REGMODE_B => REGMODE,
RESETMODE => RESETMODE,
CSDECODE_A => CSDECODE_W,
CSDECODE_B => CSDECODE_R,
GSR => GSR,
initval_00 => initval_00,
initval_01 => initval_01,
initval_02 => initval_02,
initval_03 => initval_03,
initval_04 => initval_04,
initval_05 => initval_05,
initval_06 => initval_06,
initval_07 => initval_07,
initval_08 => initval_08,
initval_09 => initval_09,
initval_0a => initval_0a,
initval_0b => initval_0b,
initval_0c => initval_0c,
initval_0d => initval_0d,
initval_0e => initval_0e,
initval_0f => initval_0f,
initval_10 => initval_10,
initval_11 => initval_11,
initval_12 => initval_12,
initval_13 => initval_13,
initval_14 => initval_14,
initval_15 => initval_15,
initval_16 => initval_16,
initval_17 => initval_17,
initval_18 => initval_18,
initval_19 => initval_19,
initval_1a => initval_1a,
initval_1b => initval_1b,
initval_1c => initval_1c,
initval_1d => initval_1d,
initval_1e => initval_1e,
initval_1f => initval_1f)
port map (dia0 => di0, dia1 => di1, dia2 => di2, dia3 => di3,
dia4 => di4, dia5 => di5, dia6 => di6, dia7 => di7, dia8 => di8,
dia9 => di9, dia10 => di10, dia11 => di11, dia12 => di12, dia13 => di13,
dia14 => di14, dia15 => di15, dia16 => di16, dia17 => di17, dib0 => di18,
dib1 => di19, dib2 => di20, dib3 => di21, dib4 => di22, dib5 => di23,
dib6 => di24, dib7 => di25, dib8 => di26, dib9 => di27, dib10 => di28,
dib11 => di29, dib12 => di30, dib13 => di31, dib14 => di32, dib15 => di33,
dib16 => di34, dib17 => di35,
cea => cew, clka => clkw, wea => we, csa0 => csw0, csa1 => csw1, csa2 => csw2,
rsta => rst, ada0 => adw0, ada1 => adw1, ada2 => adw2, ada3 => adw3,
ada4 => adw4, ada5 => adw5, ada6 => adw6, ada7 => adw7, ada8 => adw8,
ada9 => adw9, ada10 => adw10, ada11 => adw11, ada12 => adw12,
ceb => cer, clkb => clkr, web => lo, csb0 => csr0, csb1 => csr1, csb2 => csr2,
rstb => rst, adb0 => adr0, adb1 => adr1, adb2 => adr2, adb3 => adr3,
adb4 => adr4, adb5 => adr5, adb6 => adr6, adb7 => adr7, adb8 => adr8,
adb9 => adr9, adb10 => adr10, adb11 => adr11, adb12 => adr12,
dob0 => do0, dob1 => do1, dob2 => do2, dob3 => do3,
dob4 => do4, dob5 => do5, dob6 => do6, dob7 => do7, dob8 => do8,
dob9 => do9, dob10 => do10, dob11 => do11, dob12 => do12, dob13 => do13,
dob14 => do14, dob15 => do15, dob16 => do16, dob17 => do17, doa0 => do18,
doa1 => do19, doa2 => do20, doa3 => do21, doa4 => do22, doa5 => do23,
doa6 => do24, doa7 => do25, doa8 => do26, doa9 => do27, doa10 => do28,
doa11 => do29, doa12 => do30, doa13 => do31, doa14 => do32, doa15 => do33,
doa16 => do34, doa17 => do35);
end V;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY LatchSR_AA_TB IS
END LatchSR_AA_TB;
ARCHITECTURE behavior OF LatchSR_AA_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT LatchSR_AA
PORT(
S : IN std_logic;
R : IN std_logic;
Q : OUT std_logic;
Qn : OUT std_logic
);
END COMPONENT;
--Inputs
signal S : std_logic := '0';
signal R : std_logic := '0';
--Outputs
signal Q : std_logic;
signal Qn : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: LatchSR_AA PORT MAP (
S => S,
R => R,
Q => Q,
Qn => Qn
);
-- Stimulus process
stim_proc: process
begin
-- S = '1' y R = '1';
R <= '1';
S <= '1';
wait for 100 ns;
-- S = '1' y R = '0';
R <= '0';
wait for 100 ns;
-- S = '0' y R = '1';
R <= '1';
S <= '0';
wait for 100 ns;
-- S = '0' y R = '0';
R <= '0';
wait;
end process;
END;
|
-------------------------------------------------------------------------------
--
-- File: top.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This is the top module of the USB_Device IP core. It is designed to work
-- with an ULPI PHY and, together, to implement the Electrical layer and the
-- Protocol layer of the USB 2.0 device. It exports an AXI Lite slave
-- interface to communicate with the processor. An integrated DMA engine is
-- suposed to connect to the system memory through an AXI4 interface.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top is
-- Port ( );
port (
S_AXI_ACLK : IN std_logic;
INTERRUPT : OUT STD_LOGIC;
--ULPI Interface
ulpi_clk : in STD_LOGIC;
ulpi_data : inout STD_LOGIC_VECTOR(7 downto 0);
ulpi_dir : in STD_LOGIC;
ulpi_nxt : in STD_LOGIC;
ulpi_stp : out STD_LOGIC;
led : out STD_LOGIC;
ulpi_resetn : out STD_LOGIC;
--AXI4 exported by the AXI DMA Controller
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
--AXI Lite Slave interface; Access to Control Registers
S_AXI_ARESETN : IN std_logic;
S_AXI_AWADDR : IN std_logic_vector(31 downto 0);
S_AXI_AWPROT : IN std_logic_vector(2 downto 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_WDATA : IN std_logic_vector(31 downto 0);
S_AXI_WSTRB : IN std_logic_vector(3 downto 0);
S_AXI_WVALID : IN std_logic;
S_AXI_BREADY : IN std_logic;
S_AXI_ARADDR : IN std_logic_vector(31 downto 0);
S_AXI_ARPROT : IN std_logic_vector(2 downto 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_RREADY : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BRESP : OUT std_logic_vector(1 downto 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RDATA : OUT std_logic_vector(31 downto 0);
S_AXI_RRESP : OUT std_logic_vector(1 downto 0);
S_AXI_RVALID : OUT std_logic
);
end top;
architecture Behavioral of top is
COMPONENT Control_Registers
PORT(
S_AXI_ACLK : IN std_logic;
S_AXI_ARESETN : IN std_logic;
S_AXI_AWADDR : IN std_logic_vector(31 downto 0);
S_AXI_AWPROT : IN std_logic_vector(2 downto 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_WDATA : IN std_logic_vector(31 downto 0);
S_AXI_WSTRB : IN std_logic_vector(3 downto 0);
S_AXI_WVALID : IN std_logic;
S_AXI_BREADY : IN std_logic;
S_AXI_ARADDR : IN std_logic_vector(31 downto 0);
S_AXI_ARPROT : IN std_logic_vector(2 downto 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_RREADY : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BRESP : OUT std_logic_vector(1 downto 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RDATA : OUT std_logic_vector(31 downto 0);
S_AXI_RRESP : OUT std_logic_vector(1 downto 0);
S_AXI_RVALID : OUT std_logic;
USBSCFG_rd : out std_logic_vector(31 downto 0);
USBCMD_rd : out std_logic_vector(31 downto 0);
USBCMD_SUTW_wr : in std_logic;
USBCMD_SUTW_wr_en : in std_logic;
USBCMD_ATDTW_wr : in std_logic;
USBCMD_ATDTW_wr_en : in std_logic;
USBSTS_rd : out std_logic_vector(31 downto 0);
USBSTS_wr_UI : in std_logic;
USBSTS_wr_NAKI : in std_logic;
USBSTS_wr_SLI : in std_logic;
USBSTS_wr_SRI : in std_logic;
USBSTS_wr_URI : in std_logic;
USBSTS_wr_PCI : in std_logic;
USBSTS_wr_en_NAK : in std_logic;
USBSTS_wr_en_SLI : in std_logic;
USBSTS_wr_en_SRI : in std_logic;
USBSTS_wr_en_URI : in std_logic;
USBSTS_wr_en_PCI : in std_logic;
USBSTS_wr_en_UI : in std_logic;
USBINTR_rd : out std_logic_vector(31 downto 0);
FRINDEX_rd : out std_logic_vector(31 downto 0);
FRINDEX_wr : in std_logic_vector(10 downto 0);
FRINDEX_wr_en : in std_logic;
a_DEVICEADDR_rd : out std_logic_vector(31 downto 0);
a_DEVICEADDR_IPush : out std_logic;
ENDPOINTLISTADDR_rd : out std_logic_vector(31 downto 0);
ENDPTNAK_rd : out std_logic_vector(31 downto 0);
ENDPTNAK_wr : in std_logic_vector(31 downto 0);
ENDPTNAK_wr_en : in std_logic;
ENDPTNAKEN_rd : out std_logic_vector(31 downto 0);
CONFIGFLAG_rd : out std_logic_vector(31 downto 0);
PORTSC1_rd : out std_logic_vector(31 downto 0);
PORTSC1_PSPD_Wr : in std_logic_vector(1 downto 0);
PORTSC1_PSPD_wr_en : in std_logic;
OTGSC_rd : out std_logic_vector(31 downto 0);
USBMODE_rd : out std_logic_vector(31 downto 0);
ENDPTSETUPSTAT_rd : out std_logic_vector(31 downto 0);
ENDPTSETUPSTAT_wr : in std_logic_vector(31 downto 0);
ENDPTSETUPSTAT_wr_en : in std_logic;
ENDPTPRIME_rd : out std_logic_vector(31 downto 0);
ENDPTPRIME_clear : in std_logic_vector(31 downto 0);
ENDPTPRIME_clear_en : in std_logic;
ENDPTPRIME_set : in std_logic_vector(31 downto 0);
ENDPTPRIME_set_en : in std_logic;
EMDPTFLUSH_rd : out std_logic_vector(31 downto 0);
EMDPTFLUSH_clear : in std_logic_vector(31 downto 0);
EMDPTFLUSH_clear_en : in std_logic;
EMDPTFLUSH_set : in std_logic_vector(31 downto 0);
EMDPTFLUSH_set_en : in std_logic;
ENDPTSTAT_wr : in std_logic_vector(31 downto 0);
ENDPTCOMPLETE_rd : out std_logic_vector(31 downto 0);
ENDPTCOMPLETE_wr : in std_logic_vector(31 downto 0);
ENDPTCOMPLETE_wr_en : in std_logic;
ENDPTCTRL0_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL1_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL2_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL3_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL4_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL5_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL6_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL7_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL8_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL9_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL10_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL11_rd : out std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT DMA_Transfer_Manager
PORT(
Axi_Resetn : IN STD_LOGIC;
Axi_Clk : IN STD_LOGIC;
ind_statte_axistream : out std_logic_vector(4 downto 0);
DEBUG_REG_DATA : OUT std_logic_vector(31 downto 0);
state_ind_dma : out STD_LOGIC_VECTOR(4 downto 0);
state_ind_arb : out std_logic_vector(5 downto 0);
a_M_Axi_Awaddr : out std_logic_vector(9 downto 0);
a_M_Axi_Awprot : out std_logic_vector(2 downto 0);
a_M_Axi_Awvalid : out std_logic;
a_M_Axi_Awready : in std_logic;
a_M_Axi_Wdata : out std_logic_vector(31 downto 0);
a_M_Axi_Wstrb : out std_logic_vector(3 downto 0);
a_M_Axi_Wvalid : out std_logic;
a_M_Axi_Wready : in std_logic;
a_M_Axi_Bresp : in std_logic_vector(1 downto 0);
a_M_Axi_Bvalid : in std_logic;
a_M_Axi_Bready : out std_logic;
a_M_Axi_Araddr : out std_logic_vector(9 downto 0);
a_M_Axi_Arprot : out std_logic_vector(2 downto 0);
a_M_Axi_Arvalid : out std_logic;
a_M_Axi_Arready : in std_logic;
a_M_Axi_Rdata : in std_logic_vector(31 downto 0);
a_M_Axi_Rresp : in std_logic_vector(1 downto 0);
a_M_Axi_Rvalid : in std_logic;
a_M_Axi_Rready : out std_logic;
a_S_Axis_MM2S_Tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_S_Axis_MM2S_Tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
a_S_Axis_MM2S_Tvalid : IN STD_LOGIC;
a_S_Axis_MM2S_Tready : OUT STD_LOGIC;
a_S_Axis_MM2S_Tlast : IN STD_LOGIC;
a_M_Axis_S2MM_Tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a_M_Axis_S2MM_Tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
a_M_Axis_S2MM_Tvalid : OUT STD_LOGIC;
a_M_Axis_S2MM_Tready : IN STD_LOGIC;
a_M_Axis_S2MM_Tlast : OUT STD_LOGIC;
RX_COMMAND_FIFO_RD_EN : OUT std_logic;
RX_COMMAND_FIFO_DOUT : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
RX_COMMAND_FIFO_EMPTY : IN std_logic;
RX_COMMAND_FIFO_VALID : IN std_logic;
a_Axis_MM2S_Mux_Ctrl : OUT STD_LOGIC;
a_Axis_S2MM_Mux_Ctrl : OUT STD_LOGIC;
a_Send_Zero_Length_Packet_Set : OUT STD_LOGIC_VECTOR(31 downto 0);
a_Send_Zero_Length_Packet_Set_En : OUT STD_LOGIC;
a_Send_Zero_Length_Packet_Ack_Rd : IN STD_LOGIC_VECTOR(31 downto 0);
a_Send_Zero_Length_Packet_Ack_Clear : OUT STD_LOGIC_VECTOR(31 downto 0);
a_Send_Zero_Length_Packet_Ack_Clear_En : OUT STD_LOGIC;
a_Arb_dQH_Setup_Buffer_Bytes_3_0_Wr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_Arb_dQH_Setup_Buffer_Bytes_7_4_Wr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_In_Packet_Complete_Rd : IN STD_LOGIC_VECTOR(31 downto 0);
a_In_Packet_Complete_Clear : OUT STD_LOGIC_VECTOR(31 downto 0);
a_In_Packet_Complete_Clear_En : OUT STD_LOGIC;
a_In_Token_Received_Rd : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_In_Token_Received_Clear : OUT STD_LOGIC_VECTOR(31 downto 0);
a_In_Token_Received_Clear_En : OUT STD_LOGIC;
a_Resend : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_Resend_Clear : OUT STD_LOGIC_VECTOR(31 downto 0);
a_Resend_Clear_En : OUT STD_LOGIC;
a_Cnt_Bytes_Sent : IN std_logic_vector(12 downto 0);
a_Cnt_Bytes_Sent_oValid : IN std_logic;
a_Pe_Endpt_Nr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
a_Arb_Endpt_Nr : out std_logic_vector(4 downto 0);
arb_tx_fifo_s_aresetn : OUT std_logic;
a_USBSTS_Wr_UI : OUT std_logic;
a_USBSTS_Wr_en_UI : OUT std_logic;
a_USBMODE_Rd : in std_logic_vector(31 downto 0);
a_USBCMD_SUTW_Wr : out std_logic;
a_USBCMD_SUTW_Wr_En : out std_logic;
a_USBCMD_ATDTW_Wr : out std_logic;
a_USBCMD_ATDTW_Wr_En : out std_logic;
a_EMDPTFLUSH_Rd : in std_logic_vector(31 downto 0);
a_EMDPTFLUSH_Set : out std_logic_vector(31 downto 0);
a_EMDPTFLUSH_Set_En : out std_logic;
a_ENDPTPRIME_Rd : in std_logic_vector(31 downto 0);
a_ENDPTPRIME_Clear : out std_logic_vector(31 downto 0);
a_ENDPTPRIME_Clear_En : out std_logic;
a_ENDPTPRIME_Set : out std_logic_vector(31 downto 0);
a_ENDPTPRIME_Set_En : out std_logic;
a_ENDPTSTAT_Wr : out std_logic_vector(31 downto 0);
a_ENDPTCOMPLETE_Wr : out std_logic_vector(31 downto 0);
a_ENDPTCOMPLETE_Wr_En : out std_logic;
a_ENDPTSETUPSTAT_Wr : out std_logic_vector(31 downto 0);
a_ENDPTSETUPSTAT_Wr_En : out std_logic;
a_Arb_ENDPTSETUP_RECEIVED_Rd : in std_logic_vector(31 downto 0);
a_Arb_ENDPTSETUP_RECEIVED_Clear : out std_logic_vector(31 downto 0);
a_Arb_ENDPTSETUP_RECEIVED_Clear_En : out std_logic;
a_Arb_ENDPTSETUP_RECEIVED_Ack : in std_logic;
a_ENDPOINTLISTADDR_Rd : in std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT axi_dma_0
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT FIFO
PORT(
resetn : IN STD_LOGIC;
rx_fifo_s_aresetn : IN std_logic;
rx_fifo_m_aclk : IN std_logic;
rx_fifo_s_aclk : IN std_logic;
rx_fifo_s_axis_tvalid : IN std_logic;
rx_fifo_s_axis_tdata : IN std_logic_vector(31 downto 0);
rx_fifo_s_axis_tkeep : IN std_logic_vector (3 downto 0);
rx_fifo_s_axis_tlast : IN std_logic;
rx_fifo_s_axis_tuser : IN std_logic_vector(3 downto 0);
rx_fifo_m_axis_tready : IN std_logic;
rx_fifo_s_axis_tready : OUT std_logic;
rx_fifo_m_axis_tvalid : OUT std_logic;
rx_fifo_m_axis_tdata : OUT std_logic_vector(31 downto 0);
rx_fifo_m_axis_tlast : OUT std_logic;
rx_fifo_m_axis_tuser : OUT std_logic_vector(3 downto 0);
rx_fifo_m_axis_tkeep : OUT std_logic_vector(3 downto 0);
rx_fifo_axis_overflow : OUT std_logic;
rx_fifo_axis_underflow : OUT std_logic
);
END COMPONENT;
COMPONENT Protocol_Engine
PORT(
axi_clk : IN std_logic;
Axi_ResetN : in STD_LOGIC;
Ulpi_Clk : in STD_LOGIC;
u_ResetN : in STD_LOGIC;
ulpi_reset : out STD_LOGIC;
u_Ulpi_Data : inout STD_LOGIC_VECTOR(7 downto 0);
u_Ulpi_Dir : in STD_LOGIC;
u_Ulpi_Nxt : in STD_LOGIC;
u_Ulpi_Stp : out STD_LOGIC;
led : out STD_LOGIC;
a_Arb_Endpt_Nr : in std_logic_vector(4 downto 0); --!!!!! bits need to be synchronised
Tx_Fifo_S_Aresetn : IN STD_LOGIC;
a_Tx_Fifo_S_Aclk : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tvalid : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tready : OUT STD_LOGIC;
a_Tx_Fifo_S_Axis_Tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_Tx_Fifo_S_Axis_Tlast : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tkeep : IN std_logic_vector(3 downto 0);
a_Tx_Fifo_S_Axis_Tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
tx_fifo_axis_overflow : OUT STD_LOGIC;
tx_fifo_axis_underflow : OUT STD_LOGIC;
u_Rx_Fifo_s_Aclk : OUT std_logic;
u_Rx_Fifo_s_Axis_Tready : IN std_logic;
u_Rx_Fifo_s_Axis_Tvalid : OUT std_logic;
u_Rx_Fifo_s_Axis_Tdata : OUT std_logic_vector(31 downto 0);
u_Rx_Fifo_s_Axis_Tkeep : OUT std_logic_vector (3 downto 0);
u_Rx_Fifo_s_Axis_Tlast : OUT std_logic;
u_Rx_Fifo_Axis_Overflow : IN std_logic;
u_Rx_Fifo_Axis_Underflow : IN std_logic;
u_Command_Fifo_Rd_En : IN std_logic;
u_Command_Fifo_Dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
u_Command_Fifo_Empty : OUT std_logic;
u_Command_Fifo_Valid : OUT std_logic;
u_USBADRA : in STD_LOGIC_VECTOR (7 downto 0);
u_Endp_Nr_Arb : IN STD_LOGIC_VECTOR(4 DOWNTO 0); --new
u_Endp_Nr_Arb_Ack : OUT std_logic;
u_Endp_Nr_Arb_Valid : IN std_logic;
u_Endp_Type : in STD_LOGIC_VECTOR(47 downto 0);
u_Endp_Stall : IN STD_LOGIC_VECTOR(23 downto 0);
u_USBCMD_RS : in std_logic;
-- endp_enable : IN STD_LOGIC(11 downto 0); --new
a_In_Packet_Complete_oData : OUT std_logic_vector(31 downto 0);
a_In_Packet_Complete_Set_En : OUT std_logic;
u_Send_Zero_Length_Packet_Rd : IN STD_LOGIC_VECTOR(31 downto 0);
a_Send_Zero_Length_Packet_Clear_oData : OUT STD_LOGIC_VECTOR(31 downto 0);
a_Send_Zero_Length_Packet_Clear_En : OUT STD_LOGIC;
a_Send_Zero_Length_Packet_Ack_oData : OUT STD_LOGIC_VECTOR(31 downto 0);
a_Send_Zero_Length_Packet_Ack_Set_En : OUT STD_LOGIC;
a_Cnt_Bytes_Sent_oData : out std_logic_vector(12 downto 0); --new
a_Cnt_Bytes_Sent_oValid : OUT std_logic;
a_In_Token_Received_oData : OUT std_logic_vector(31 downto 0); --new
a_In_Token_Received_Set_En : OUT std_logic; --new
a_Resend_oData : OUT STD_LOGIC_VECTOR(31 downto 0);
a_Resend_Wr_En : OUT std_logic;
a_Endpt_Nr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --new + 1 bit
u_Endp_Nr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
a_FRINDEX_oData : out std_logic_vector(10 downto 0);
a_FRINDEX_Wr_En : out std_logic;
a_Setup_Buffer_Bytes_3_0_oData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a_Setup_Buffer_Bytes_7_4_oData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a_PORTSC1_PSPD_oData : out std_logic_vector(1 downto 0);
a_PORTSC1_PSPD_Wr_En : out std_logic;
a_ENDPTNAK_oData : out std_logic_vector(31 downto 0);
a_ENDPTNAK_Wr_En : out std_logic;
a_ENDPTSETUP_RECEIVED_oData : out std_logic_vector(31 downto 0);
a_ENDPTSETUP_RECEIVED_Wr_En : out std_logic;
a_USBSTS_NAKI_oData : out std_logic;
a_USBSTS_NAKI_Wr_En : out std_logic;
a_USBSTS_SLI_oData : out std_logic;
a_USBSTS_SLI_Wr_En : out std_logic;
a_USBSTS_SRI_oData : out std_logic;
a_USBSTS_SRI_Wr_En : out std_logic;
a_USBSTS_URI_oData : out std_logic;
a_USBSTS_URI_Wr_En : out std_logic;
a_USBSTS_PCI_oData : out std_logic;
a_USBSTS_PCI_Wr_En : out std_logic;
state_ind : out STD_LOGIC_VECTOR(5 downto 0);
state_ind_pd : out STD_LOGIC_VECTOR(6 downto 0);
state_ind_hs : out STD_LOGIC_VECTOR(4 downto 0)
);
END COMPONENT;
COMPONENT ResetBridge
Generic (
kPolarity : std_logic);
PORT(
aRst : IN std_logic;
OutClk : IN std_logic;
oRst : OUT std_logic
);
END COMPONENT;
type ENDPOINTCTRL_REGISTERS is array (11 downto 0) of std_logic_vector(31 downto 0);
signal ENDPTCTRL : ENDPOINTCTRL_REGISTERS;
signal Ulpi_Clk_MMCM_Clkin : STD_LOGIC;
signal Ulpi_Clk_MMCM_Clkfbin : STD_LOGIC;
signal Ulpi_Clk_MMCM_Clkfbout : STD_LOGIC;
signal Ulpi_Clk_MMCM_Clkout0 : STD_LOGIC;
signal Ulpi_Clk_MMCM_Locked : STD_LOGIC;
signal Ulpi_ResetN_oRst : STD_LOGIC;
signal u_ResetN : STD_LOGIC;
signal u_MMCM_Rst : STD_LOGIC;
signal a_Axi_Reset : STD_LOGIC;
signal a_Axi_DMA_Tstvec : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_MM2S_Introut : STD_LOGIC;
signal a_S2MM_Introut : STD_LOGIC;
signal a_S2MM_Prmry_Reset_Out_N : STD_LOGIC;
signal a_MM2S_Prmry_Reset_Out_N : STD_LOGIC;
------------------------------------------------------------------------
signal a_Axis_MM2S_Mux_Ctrl, a_Axis_S2MM_Mux_Ctrl : STD_LOGIC;
signal a_Setup_Buffer_Bytes_3_0_Wr : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_Setup_Buffer_Bytes_7_4_Wr : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_Pe_Endpt_Nr, pe_endpt_nr_ulpi_clk : STD_LOGIC_VECTOR(4 DOWNTO 0);
signal a_DMA_S_Axis_S2MM_Tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_DMA_S_Axis_S2MM_Tkeep : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal a_DMA_S_Axis_S2MM_Tvalid : STD_LOGIC;
signal a_DMA_S_Axis_S2MM_Tready : STD_LOGIC;
signal a_DMA_S_Axis_S2MM_Tlast : STD_LOGIC;
signal a_DMA_M_Axis_MM2S_Tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_DMA_M_Axis_MM2S_Tkeep : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal a_DMA_M_Axis_MM2S_Tvalid : STD_LOGIC;
signal a_DMA_M_Axis_MM2S_Tready : STD_LOGIC;
signal a_DMA_M_Axis_MM2S_Tlast : STD_LOGIC;
signal a_FIFO_Axis_S2MM_Tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_FIFO_Axis_S2MM_Tkeep : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal a_FIFO_Axis_S2MM_Tvalid : STD_LOGIC;
signal a_FIFO_Axis_S2MM_Tready : STD_LOGIC;
signal a_FIFO_Axis_S2MM_Tlast : STD_LOGIC;
signal a_FIFO_Axis_MM2S_Tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_FIFO_Axis_MM2S_Tkeep : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal a_FIFO_Axis_MM2S_Tvalid : STD_LOGIC;
signal a_FIFO_Axis_MM2S_Tready : STD_LOGIC;
signal a_FIFO_Axis_MM2S_Tlast : STD_LOGIC;
signal a_Arb_Axis_S2MM_Tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_Arb_Axis_S2MM_Tkeep : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal a_Arb_Axis_S2MM_Tvalid : STD_LOGIC;
signal a_Arb_Axis_S2MM_Tready : STD_LOGIC;
signal a_Arb_Axis_S2MM_Tlast : STD_LOGIC;
signal a_Arb_Axis_MM2S_Tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_Arb_Axis_MM2S_Tkeep : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal a_Arb_Axis_MM2S_Tvalid : STD_LOGIC;
signal a_Arb_Axis_MM2S_Tready : STD_LOGIC;
signal a_Arb_Axis_MM2S_Tlast : STD_LOGIC;
------------------------------------------------------------------------
signal u_Rx_Fifo_s_Aclk : STD_LOGIC;
signal u_Rx_Fifo_s_Axis_Tready : STD_LOGIC;
signal u_Rx_Fifo_s_Axis_Tvalid : STD_LOGIC;
signal u_Rx_Fifo_s_Axis_Tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal u_Rx_Fifo_s_Axis_Tkeep : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal u_Rx_Fifo_s_Axis_Tlast : STD_LOGIC;
signal u_Rx_Fifo_Axis_Overflow : std_logic;
signal u_Rx_Fifo_Axis_Underflow : std_logic;
signal tx_fifo_reset_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
signal u_Command_Fifo_Rd_En : std_logic;
signal u_Command_Fifo_Dout : STD_LOGIC_VECTOR(23 DOWNTO 0);
signal u_Command_Fifo_Empty : std_logic;
signal u_Command_Fifo_Valid : std_logic;
signal a_DMA_Axilite_Awaddr : std_logic_vector(9 downto 0);
signal a_DMA_Axilite_Awprot : std_logic_vector(2 downto 0);
signal a_DMA_Axilite_Awvalid : std_logic;
signal a_DMA_Axilite_Awready : std_logic;
signal a_DMA_Axilite_Wdata : std_logic_vector(31 downto 0);
signal a_DMA_Axilite_Wstrb : std_logic_vector(3 downto 0);
signal a_DMA_Axilite_Wvalid : std_logic;
signal a_DMA_Axilite_Wready : std_logic;
signal a_DMA_Axilite_Bresp : std_logic_vector(1 downto 0);
signal a_DMA_Axilite_Bvalid : std_logic;
signal a_DMA_Axilite_Bready : std_logic;
signal a_DMA_Axilite_Araddr : std_logic_vector(9 downto 0);
signal a_DMA_Axilite_Arprot : std_logic_vector(2 downto 0);
signal a_DMA_Axilite_Arvalid : std_logic;
signal a_DMA_Axilite_Arready : std_logic;
signal a_DMA_Axilite_Rdata : std_logic_vector(31 downto 0);
signal a_DMA_Axilite_Rresp : std_logic_vector(1 downto 0);
signal a_DMA_Axilite_Rvalid : std_logic;
signal a_DMA_Axilite_Ready : std_logic;
signal arb_tx_fifo_s_aresetn : std_logic;
signal a_SBUSCFG_Rd : std_logic_vector(31 downto 0);
signal a_USBCMD_Rd : std_logic_vector(31 downto 0);
signal a_USBCMD_SUTW_Wr : std_logic;
signal a_USBCMD_SUTW_Wr_En : std_logic;
signal a_USBCMD_ATDTW_Wr : std_logic;
signal a_USBCMD_ATDTW_Wr_En : std_logic;
signal a_USBSTS_Rd : std_logic_vector(31 downto 0);
signal a_USBSTS_Wr_NAKI : std_logic;
signal a_USBSTS_Wr_SLI : std_logic;
signal a_USBSTS_Wr_SRI : std_logic;
signal a_USBSTS_Wr_URI : std_logic;
signal a_USBSTS_Wr_PCI : std_logic;
signal a_USBSTS_Wr_En_NAK : std_logic;
signal a_USBSTS_Wr_En_SLI : std_logic;
signal a_USBSTS_Wr_En_SRI : std_logic;
signal a_USBSTS_Wr_En_URI : std_logic;
signal a_USBSTS_Wr_En_PCI : std_logic;
signal a_USBSTS_Wr_UI : std_logic;
signal a_USBSTS_Wr_en_UI : std_logic;
signal a_USBINTR_Rd : std_logic_vector(31 downto 0);
signal a_FRINDEX_Rd : std_logic_vector(31 downto 0);
signal a_FRINDEX_Wr : std_logic_vector(10 downto 0);
signal a_FRINDEX_Wr_En : std_logic;
signal a_DEVICEADDR_rd, u_DEVICEADDR_rd : std_logic_vector(31 downto 0);
signal a_DEVICEADDR_IPush : std_logic;
signal a_DEVICEADDR_IRdy : std_logic;
signal u_DEVICEADDR_oValid : std_logic;
signal a_ENDPOINTLISTADDR_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTNAK_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTNAK_Wr : std_logic_vector(31 downto 0);
signal a_ENDPTNAK_Wr_En : std_logic;
signal a_ENDPTNAKEN_Rd : std_logic_vector(31 downto 0);
signal a_CONFIGFLAG_Rd : std_logic_vector(31 downto 0);
signal a_PORTSC1_Rd : std_logic_vector(31 downto 0);
signal a_PORTSC1_PSPD_Wr : std_logic_vector(1 downto 0);
signal a_PORTSC1_PSPD_Wr_En : std_logic;
signal a_OTGSC_Rd : std_logic_vector(31 downto 0);
signal a_USBMODE_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTSETUPSTAT_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTSETUPSTAT_Wr : std_logic_vector(31 downto 0);
signal a_ENDPTSETUPSTAT_Wr_En : std_logic;
signal a_PE_ENDPTSETUP_RECEIVED_Wr : std_logic_vector(31 downto 0);
signal a_PE_ENDPTSETUP_RECEIVED_Wr_En : std_logic;
signal a_Arb_ENDPTSETUP_RECEIVED_Rd : std_logic_vector(31 downto 0);
signal a_Arb_ENDPTSETUP_RECEIVED_Clear : std_logic_vector(31 downto 0);
signal a_Arb_ENDPTSETUP_RECEIVED_Clear_En : std_logic;
signal a_Arb_ENDPTSETUP_RECEIVED_Ack : std_logic;
signal a_ENDPTPRIME_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTPRIME_Clear : std_logic_vector(31 downto 0);
signal a_ENDPTPRIME_Clear_En : std_logic;
signal a_ENDPTPRIME_Set : std_logic_vector(31 downto 0);
signal a_ENDPTPRIME_Set_En : std_logic;
signal a_EMDPTFLUSH_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTFLUSH_Clear, a_EMDPTFLUSH_Set : std_logic_vector(31 downto 0);
signal a_ENDPTFLUSH_Clear_En, a_EMDPTFLUSH_Set_En : std_logic;
signal a_ENDPTSTAT_Wr : std_logic_vector(31 downto 0);
signal a_ENDPTCOMPLETE_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCOMPLETE_Wr : std_logic_vector(31 downto 0);
signal a_ENDPTCOMPLETE_Wr_En : std_logic;
signal a_ENDPTCTRL0_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL1_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL2_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL3_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL4_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL5_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL6_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL7_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL8_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL9_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL10_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL11_Rd : std_logic_vector(31 downto 0);
signal a_USBCMD_RS, u_USBCMD_RS : std_logic;
signal a_In_Packet_Complete_Set : std_logic_vector(31 downto 0);
signal a_In_Packet_Complete_Set_En : std_logic;
signal a_In_Packet_Complete_Rd : std_logic_vector(31 downto 0);
signal a_In_Packet_Complete_Clear : STD_LOGIC_VECTOR(31 downto 0);
signal a_In_Packet_Complete_Clear_En : STD_LOGIC;
signal a_Send_Zero_Length_Packet_iData, u_Send_Zero_Length_Packet_oData, a_Send_Zero_Length_Packet_iData_q : STD_LOGIC_VECTOR(31 downto 0);
signal a_Send_Zero_Length_Packet_iPush, a_Send_Zero_Length_Packet_iRdy, u_Send_Zero_Length_Packet_oValid : std_logic;
signal a_Send_Zero_Length_Packet_Set : STD_LOGIC_VECTOR(31 downto 0);
signal a_Send_Zero_Length_Packet_Set_En : STD_LOGIC;
signal a_Send_Zero_Length_Packet_Clear : STD_LOGIC_VECTOR(31 downto 0);
signal a_Send_Zero_Length_Packet_Clear_En : STD_LOGIC;
signal a_Send_Zero_Length_Packet_Ack_Rd : STD_LOGIC_VECTOR(31 downto 0);
signal a_Send_Zero_Length_Packet_Ack_Clear : STD_LOGIC_VECTOR(31 downto 0);
signal a_Send_Zero_Length_Packet_Ack_Clear_En : STD_LOGIC;
signal a_Send_Zero_Length_Packet_Ack_Set : STD_LOGIC_VECTOR(31 downto 0);
signal a_Send_Zero_Length_Packet_Ack_Set_En : STD_LOGIC;
signal a_In_Token_Received_Set, a_In_Token_Received_Rd, a_In_Token_Received_Clear : STD_LOGIC_VECTOR(31 downto 0);
signal a_In_Token_Received_Set_En, a_In_Token_Received_Clear_En : STD_LOGIC;
signal a_Cnt_Bytes_Sent : std_logic_vector(12 downto 0);
signal a_Cnt_Bytes_Sent_oValid : STD_LOGIC;
signal a_Arb_Endpt_Nr : std_logic_vector(4 downto 0);
signal a_Endpt_Type_iData, u_Endpt_Type_oData, a_Endpt_Type_iData_q : std_logic_vector(47 downto 0);
signal a_Endpt_Type_iPush, a_Endpt_Type_iRdy, u_Endpt_Type_oValid : std_logic;
signal a_Endpt_Enable_iData, u_Endpt_Enable_oData, a_Endpt_Enable_iData_q : std_logic_vector(23 downto 0);
signal a_Endpt_Enable_iPush, a_Endpt_Enable_iRdy, u_Endpt_Enable_oValid : std_logic;
signal a_Endpt_Stall_iData, u_Endpt_Stall_oData, a_Endpt_Stall_iData_q : std_logic_vector(23 downto 0);
signal a_Endpt_Stall_iPush, a_Endpt_Stall_iRdy, u_Endpt_Stall_oValid : std_logic;
signal a_INTERRUPT_Loc : std_logic;
signal DEBUG_REG_DATA : std_logic_vector(31 downto 0);
signal a_USBSTS_UI_Change : std_logic;
signal a_Resend : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_Resend_Clear : STD_LOGIC_VECTOR(31 downto 0);
signal a_Resend_Clear_En : STD_LOGIC;
signal a_Resend_oData : STD_LOGIC_VECTOR(31 downto 0);
signal a_Resend_Wr_En : STD_LOGIC;
attribute clock_buffer_type : string;
attribute clock_buffer_type of ulpi_clk : signal is "none";
signal state_ind : STD_LOGIC_VECTOR(5 downto 0);
signal state_ind_pd : STD_LOGIC_VECTOR(6 downto 0);
signal state_ind_hs : STD_LOGIC_VECTOR(4 downto 0);
signal state_ind_dma : STD_LOGIC_VECTOR(4 downto 0);
signal state_ind_arb : std_logic_vector(5 downto 0);
signal ind_statte_axistream : std_logic_vector(4 downto 0);
-- attribute mark_debug : string;
-- attribute keep : string;
-- attribute mark_debug of u_USBCMD_RS : signal is "true";
-- attribute keep of u_USBCMD_RS : signal is "true";
begin
ulpi_resetn <= S_AXI_ARESETN;
a_Axi_Reset <= not S_AXI_ARESETN;
a_USBCMD_RS <= a_USBCMD_Rd(0);
led <= '0';
u_ResetN <= Ulpi_ResetN_oRst and (Ulpi_Clk_MMCM_Locked);
Inst_ResetBridge: ResetBridge
GENERIC MAP (
kPolarity => '0')
PORT MAP(
aRst => S_AXI_ARESETN,
OutClk => Ulpi_Clk_MMCM_Clkout0,
oRst => Ulpi_ResetN_oRst
);
u_MMCM_Rst <= '0';
-- This module implements the control registers required by USB Device IP.
-- Control Registers data is written/read over an AXI Lite interface
Inst_Control_Registers: Control_Registers PORT MAP(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWPROT => S_AXI_AWPROT,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARPROT => S_AXI_ARPROT,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
USBSCFG_rd => a_SBUSCFG_Rd,
USBCMD_rd => a_USBCMD_Rd,
USBCMD_SUTW_wr => a_USBCMD_SUTW_Wr,
USBCMD_SUTW_wr_en => a_USBCMD_SUTW_Wr_En,
USBCMD_ATDTW_wr => a_USBCMD_ATDTW_Wr,
USBCMD_ATDTW_wr_en => a_USBCMD_ATDTW_Wr_En,
USBSTS_rd => a_USBSTS_Rd,
USBSTS_wr_UI => a_USBSTS_Wr_UI,
USBSTS_wr_NAKI => a_USBSTS_Wr_NAKI,
USBSTS_wr_SLI => a_USBSTS_Wr_SLI,
USBSTS_wr_SRI => a_USBSTS_Wr_SRI,
USBSTS_wr_URI => a_USBSTS_Wr_URI,
USBSTS_wr_PCI => a_USBSTS_Wr_PCI,
USBSTS_wr_en_NAK => a_USBSTS_Wr_En_NAK,
USBSTS_wr_en_SLI => a_USBSTS_Wr_En_SLI,
USBSTS_wr_en_SRI => a_USBSTS_Wr_En_SRI,
USBSTS_wr_en_URI => a_USBSTS_Wr_En_URI,
USBSTS_wr_en_PCI => a_USBSTS_Wr_En_PCI,
USBSTS_wr_en_UI => a_USBSTS_Wr_en_UI,
USBINTR_rd => a_USBINTR_Rd,
FRINDEX_rd => a_FRINDEX_Rd,
FRINDEX_wr => a_FRINDEX_Wr,
FRINDEX_wr_en => a_FRINDEX_Wr_En,
a_DEVICEADDR_rd => a_DEVICEADDR_rd,
a_DEVICEADDR_IPush => a_DEVICEADDR_IPush,
ENDPOINTLISTADDR_rd => a_ENDPOINTLISTADDR_Rd,
ENDPTNAK_rd => a_ENDPTNAK_Rd,
ENDPTNAK_wr => a_ENDPTNAK_Wr,
ENDPTNAK_wr_en => a_ENDPTNAK_Wr_En,
ENDPTNAKEN_rd => a_ENDPTNAKEN_Rd,
CONFIGFLAG_rd => a_CONFIGFLAG_Rd,
PORTSC1_rd => a_PORTSC1_Rd,
PORTSC1_PSPD_wr => a_PORTSC1_PSPD_Wr,
PORTSC1_PSPD_wr_en => a_PORTSC1_PSPD_Wr_En,
OTGSC_rd => a_OTGSC_Rd,
USBMODE_rd => a_USBMODE_Rd,
ENDPTSETUPSTAT_rd => a_ENDPTSETUPSTAT_Rd,
ENDPTSETUPSTAT_wr => a_ENDPTSETUPSTAT_Wr,
ENDPTSETUPSTAT_wr_en => a_ENDPTSETUPSTAT_Wr_En,
ENDPTPRIME_rd => a_ENDPTPRIME_Rd,
ENDPTPRIME_clear => a_ENDPTPRIME_Clear,
ENDPTPRIME_clear_en => a_ENDPTPRIME_Clear_En,
ENDPTPRIME_set => a_ENDPTPRIME_Set,
ENDPTPRIME_set_en => a_ENDPTPRIME_Set_En,
EMDPTFLUSH_rd => a_EMDPTFLUSH_Rd,
EMDPTFLUSH_clear => a_ENDPTFLUSH_Clear,
EMDPTFLUSH_clear_en => a_ENDPTFLUSH_Clear_En,
EMDPTFLUSH_set => a_EMDPTFLUSH_Set,
EMDPTFLUSH_set_en => a_EMDPTFLUSH_Set_En,
ENDPTSTAT_wr => a_ENDPTSTAT_Wr,
ENDPTCOMPLETE_rd => a_ENDPTCOMPLETE_Rd,
ENDPTCOMPLETE_wr => a_ENDPTCOMPLETE_Wr,
ENDPTCOMPLETE_wr_en => a_ENDPTCOMPLETE_Wr_En,
ENDPTCTRL0_rd => a_ENDPTCTRL0_Rd,
ENDPTCTRL1_rd => a_ENDPTCTRL1_Rd,
ENDPTCTRL2_rd => a_ENDPTCTRL2_Rd,
ENDPTCTRL3_rd => a_ENDPTCTRL3_Rd,
ENDPTCTRL4_rd => a_ENDPTCTRL4_Rd,
ENDPTCTRL5_rd => a_ENDPTCTRL5_Rd,
ENDPTCTRL6_rd => a_ENDPTCTRL6_Rd,
ENDPTCTRL7_rd => a_ENDPTCTRL7_Rd,
ENDPTCTRL8_rd => a_ENDPTCTRL8_Rd,
ENDPTCTRL9_rd => a_ENDPTCTRL9_Rd,
ENDPTCTRL10_rd => a_ENDPTCTRL10_Rd,
ENDPTCTRL11_rd => a_ENDPTCTRL11_Rd
);
-- This module manages all transfers from main memory to local buffers through
-- DMA, both control data (Queue Heads, Transfer Descriptors)and packet data.
Inst_DMA_Transfer_Manager: DMA_Transfer_Manager PORT MAP(
Axi_Clk => S_AXI_ACLK,
Axi_Resetn => S_AXI_ARESETN,
ind_statte_axistream => ind_statte_axistream,
state_ind_dma => state_ind_dma,
state_ind_arb => state_ind_arb,
a_M_Axi_Awaddr => a_DMA_Axilite_Awaddr,
a_M_Axi_Awprot => a_DMA_Axilite_Awprot,
a_M_Axi_Awvalid => a_DMA_Axilite_Awvalid,
a_M_Axi_Awready => a_DMA_Axilite_Awready,
a_M_Axi_Wdata => a_DMA_Axilite_Wdata,
a_M_Axi_Wstrb => a_DMA_Axilite_Wstrb,
a_M_Axi_Wvalid => a_DMA_Axilite_Wvalid,
a_M_Axi_Wready => a_DMA_Axilite_Wready,
a_M_Axi_Bresp => a_DMA_Axilite_Bresp,
a_M_Axi_Bvalid => a_DMA_Axilite_Bvalid,
a_M_Axi_Bready => a_DMA_Axilite_Bready,
a_M_Axi_Araddr => a_DMA_Axilite_Araddr,
a_M_Axi_Arprot => a_DMA_Axilite_Arprot,
a_M_Axi_Arvalid => a_DMA_Axilite_Arvalid,
a_M_Axi_Arready => a_DMA_Axilite_Arready,
a_M_Axi_Rdata => a_DMA_Axilite_Rdata,
a_M_Axi_Rresp => a_DMA_Axilite_Rresp,
a_M_Axi_Rvalid => a_DMA_Axilite_Rvalid,
a_M_Axi_Rready => a_DMA_Axilite_Ready,
a_S_Axis_MM2S_Tdata => a_Arb_Axis_MM2S_Tdata,
a_S_Axis_MM2S_Tkeep => a_Arb_Axis_MM2S_Tkeep,
a_S_Axis_MM2S_Tvalid => a_Arb_Axis_MM2S_Tvalid,
a_S_Axis_MM2S_Tready => a_Arb_Axis_MM2S_Tready,
a_S_Axis_MM2S_Tlast => a_Arb_Axis_MM2S_Tlast,
a_M_Axis_S2MM_Tdata => a_Arb_Axis_S2MM_Tdata,
a_M_Axis_S2MM_Tkeep => a_Arb_Axis_S2MM_Tkeep,
a_M_Axis_S2MM_Tvalid => a_Arb_Axis_S2MM_Tvalid,
a_M_Axis_S2MM_Tready => a_Arb_Axis_S2MM_Tready,
a_M_Axis_S2MM_Tlast => a_Arb_Axis_S2MM_Tlast,
RX_COMMAND_FIFO_RD_EN => u_Command_Fifo_Rd_En,
RX_COMMAND_FIFO_DOUT => u_Command_Fifo_Dout,
RX_COMMAND_FIFO_EMPTY => u_Command_Fifo_Empty,
RX_COMMAND_FIFO_VALID => u_Command_Fifo_Valid,
a_Axis_MM2S_Mux_Ctrl => a_Axis_MM2S_Mux_Ctrl,
a_Axis_S2MM_Mux_Ctrl => a_Axis_S2MM_Mux_Ctrl,
a_Send_Zero_Length_Packet_Set => a_Send_Zero_Length_Packet_Set,
a_Send_Zero_Length_Packet_Set_En => a_Send_Zero_Length_Packet_Set_En,
a_Send_Zero_Length_Packet_Ack_Rd => a_Send_Zero_Length_Packet_Ack_Rd,
a_Send_Zero_Length_Packet_Ack_Clear => a_Send_Zero_Length_Packet_Ack_Clear,
a_Send_Zero_Length_Packet_Ack_Clear_En => a_Send_Zero_Length_Packet_Ack_Clear_En,
a_Arb_dQH_Setup_Buffer_Bytes_3_0_Wr => a_Setup_Buffer_Bytes_3_0_Wr,
a_Arb_dQH_Setup_Buffer_Bytes_7_4_Wr => a_Setup_Buffer_Bytes_7_4_Wr,
a_In_Packet_Complete_Rd => a_In_Packet_Complete_Rd,
a_In_Packet_Complete_Clear => a_In_Packet_Complete_Clear,
a_In_Packet_Complete_Clear_En => a_In_Packet_Complete_Clear_En,
a_In_Token_Received_Rd => a_In_Token_Received_Rd,
a_In_Token_Received_Clear => a_In_Token_Received_Clear,
a_In_Token_Received_Clear_En => a_In_Token_Received_Clear_En,
a_Cnt_Bytes_Sent => a_Cnt_Bytes_Sent,
a_Cnt_Bytes_Sent_oValid => a_Cnt_Bytes_Sent_oValid,
a_Pe_Endpt_Nr => a_Pe_Endpt_Nr,
a_Arb_Endpt_Nr => a_Arb_Endpt_Nr,
a_Resend => a_Resend,
a_Resend_Clear => a_Resend_Clear,
a_Resend_Clear_En => a_Resend_Clear_En,
arb_tx_fifo_s_aresetn => arb_tx_fifo_s_aresetn,
a_USBSTS_Wr_UI => a_USBSTS_Wr_UI,
a_USBSTS_Wr_en_UI => a_USBSTS_Wr_en_UI,
a_USBMODE_Rd => a_USBMODE_Rd,
a_USBCMD_SUTW_Wr => a_USBCMD_SUTW_Wr,
a_USBCMD_SUTW_Wr_En => a_USBCMD_SUTW_Wr_En,
a_USBCMD_ATDTW_Wr => a_USBCMD_ATDTW_Wr,
a_USBCMD_ATDTW_Wr_En => a_USBCMD_ATDTW_Wr_En,
a_EMDPTFLUSH_Rd => a_EMDPTFLUSH_Rd,
a_EMDPTFLUSH_Set => a_EMDPTFLUSH_Set,
a_EMDPTFLUSH_Set_En => a_EMDPTFLUSH_Set_En,
a_ENDPTPRIME_Rd => a_ENDPTPRIME_Rd,
a_ENDPTPRIME_Clear => a_ENDPTPRIME_Clear,
a_ENDPTPRIME_Clear_En => a_ENDPTPRIME_Clear_En,
a_ENDPTPRIME_Set => a_ENDPTPRIME_Set,
a_ENDPTPRIME_Set_En => a_ENDPTPRIME_Set_En,
a_ENDPTSTAT_Wr => a_ENDPTSTAT_Wr,
a_ENDPTCOMPLETE_Wr => a_ENDPTCOMPLETE_Wr,
a_ENDPTCOMPLETE_Wr_En => a_ENDPTCOMPLETE_Wr_En,
a_ENDPTSETUPSTAT_Wr => a_ENDPTSETUPSTAT_Wr,
a_ENDPTSETUPSTAT_Wr_En => a_ENDPTSETUPSTAT_Wr_En,
a_Arb_ENDPTSETUP_RECEIVED_Rd => a_Arb_ENDPTSETUP_RECEIVED_Rd,
a_Arb_ENDPTSETUP_RECEIVED_Clear => a_Arb_ENDPTSETUP_RECEIVED_Clear,
a_Arb_ENDPTSETUP_RECEIVED_Clear_En => a_Arb_ENDPTSETUP_RECEIVED_Clear_En,
a_Arb_ENDPTSETUP_RECEIVED_Ack => a_Arb_ENDPTSETUP_RECEIVED_Ack,
a_ENDPOINTLISTADDR_Rd => a_ENDPOINTLISTADDR_Rd
);
--AXI DMA Controller
your_instance_name: axi_dma_0 PORT MAP (
s_axi_lite_aclk => S_AXI_ACLK,
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => S_AXI_ARESETN,
s_axi_lite_awvalid => a_DMA_Axilite_Awvalid,
s_axi_lite_awready => a_DMA_Axilite_Awready,
s_axi_lite_awaddr => a_DMA_Axilite_Awaddr,
s_axi_lite_wvalid => a_DMA_Axilite_Wvalid,
s_axi_lite_wready => a_DMA_Axilite_Wready,
s_axi_lite_wdata => a_DMA_Axilite_Wdata,
s_axi_lite_bresp => a_DMA_Axilite_Bresp,
s_axi_lite_bvalid => a_DMA_Axilite_Bvalid,
s_axi_lite_bready => a_DMA_Axilite_Bready,
s_axi_lite_arvalid => a_DMA_Axilite_Arvalid,
s_axi_lite_arready => a_DMA_Axilite_Arready,
s_axi_lite_araddr => a_DMA_Axilite_Araddr,
s_axi_lite_rvalid => a_DMA_Axilite_Rvalid,
s_axi_lite_rready => a_DMA_Axilite_Ready,
s_axi_lite_rdata => a_DMA_Axilite_Rdata,
s_axi_lite_rresp => a_DMA_Axilite_Rresp,
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => a_MM2S_Prmry_Reset_Out_N,
m_axis_mm2s_tdata => a_DMA_M_Axis_MM2S_Tdata,
m_axis_mm2s_tkeep => a_DMA_M_Axis_MM2S_Tkeep,
m_axis_mm2s_tvalid => a_DMA_M_Axis_MM2S_Tvalid,
m_axis_mm2s_tready => a_DMA_M_Axis_MM2S_Tready,
m_axis_mm2s_tlast => a_DMA_M_Axis_MM2S_Tlast,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => a_S2MM_Prmry_Reset_Out_N,
s_axis_s2mm_tdata => a_DMA_S_Axis_S2MM_Tdata,
s_axis_s2mm_tkeep => a_DMA_S_Axis_S2MM_Tkeep,
s_axis_s2mm_tvalid => a_DMA_S_Axis_S2MM_Tvalid,
s_axis_s2mm_tready => a_DMA_S_Axis_S2MM_Tready,
s_axis_s2mm_tlast => a_DMA_S_Axis_S2MM_Tlast,
mm2s_introut => a_MM2S_Introut,
s2mm_introut => a_S2MM_Introut,
axi_dma_tstvec => a_Axi_DMA_Tstvec
);
--Receive Packet FIFO
Inst_FIFO: FIFO PORT MAP(
resetn => S_AXI_ARESETN,
rx_fifo_s_aresetn => S_AXI_ARESETN,
rx_fifo_m_aclk => m_axi_mm2s_aclk,
rx_fifo_s_aclk => u_Rx_Fifo_s_Aclk ,
rx_fifo_s_axis_tvalid => u_Rx_Fifo_s_Axis_Tvalid,
rx_fifo_s_axis_tready => u_Rx_Fifo_s_Axis_Tready,
rx_fifo_s_axis_tdata => u_Rx_Fifo_s_Axis_Tdata,
rx_fifo_s_axis_tkeep => u_Rx_Fifo_s_Axis_Tkeep,
rx_fifo_s_axis_tlast => u_Rx_Fifo_s_Axis_Tlast,
rx_fifo_s_axis_tuser => "0000",
rx_fifo_m_axis_tvalid => a_FIFO_Axis_S2MM_Tvalid,
rx_fifo_m_axis_tready => a_FIFO_Axis_S2MM_Tready,
rx_fifo_m_axis_tdata => a_FIFO_Axis_S2MM_Tdata,
rx_fifo_m_axis_tlast => a_FIFO_Axis_S2MM_Tlast,
rx_fifo_m_axis_tkeep => a_FIFO_Axis_S2MM_Tkeep,
rx_fifo_m_axis_tuser => open,
rx_fifo_axis_overflow => u_Rx_Fifo_Axis_Overflow,
rx_fifo_axis_underflow => u_Rx_Fifo_Axis_Underflow
);
-- This module instantiates all the necessary modules to implement ULPI
-- communication, Speed negotiation , Reset and Suspend. Packet data is
-- sent/received over AXI Stream. Synchronization modules for registers
-- that corss the ULPI Clock domain to AXI clock domain is implemented
-- here
Inst_Protocol_Engine: Protocol_Engine PORT MAP(
Axi_Clk => S_AXI_ACLK,
axi_resetn => S_AXI_ARESETN,
Ulpi_Clk => Ulpi_Clk_MMCM_Clkout0,
u_ResetN => u_ResetN,
ulpi_reset => open,
u_Ulpi_Data => ulpi_data,
u_Ulpi_Dir => ulpi_dir,
u_Ulpi_Nxt => ulpi_nxt,
u_Ulpi_Stp => ulpi_stp,
led => open,
a_Arb_Endpt_Nr => a_Arb_Endpt_Nr,
Tx_Fifo_S_Aresetn => arb_tx_fifo_s_aresetn,
a_Tx_Fifo_S_Aclk => m_axi_s2mm_aclk,
a_Tx_Fifo_S_Axis_Tvalid => a_FIFO_Axis_MM2S_Tvalid,
a_Tx_Fifo_S_Axis_Tready => a_FIFO_Axis_MM2S_Tready,
a_Tx_Fifo_S_Axis_Tdata => a_FIFO_Axis_MM2S_Tdata,
a_Tx_Fifo_S_Axis_Tlast => a_FIFO_Axis_MM2S_Tlast,
a_Tx_Fifo_S_Axis_Tkeep => a_FIFO_Axis_MM2S_Tkeep,
a_Tx_Fifo_S_Axis_Tuser => "0000",
tx_fifo_axis_overflow => open,
tx_fifo_axis_underflow => open,
u_Rx_Fifo_s_Aclk => u_Rx_Fifo_s_Aclk ,
u_Rx_Fifo_s_Axis_Tready => u_Rx_Fifo_s_Axis_Tready,
u_Rx_Fifo_s_Axis_Tvalid => u_Rx_Fifo_s_Axis_Tvalid,
u_Rx_Fifo_s_Axis_Tdata => u_Rx_Fifo_s_Axis_Tdata,
u_Rx_Fifo_s_Axis_Tkeep => u_Rx_Fifo_s_Axis_Tkeep,
u_Rx_Fifo_s_Axis_Tlast => u_Rx_Fifo_s_Axis_Tlast,
u_Rx_Fifo_Axis_Overflow => u_Rx_Fifo_Axis_Overflow,
u_Rx_Fifo_Axis_Underflow => u_Rx_Fifo_Axis_Underflow,
u_Command_Fifo_Rd_En => u_Command_Fifo_Rd_En,
u_Command_Fifo_Dout => u_Command_Fifo_Dout,
u_Command_Fifo_Empty => u_Command_Fifo_Empty,
u_Command_Fifo_Valid => u_Command_Fifo_Valid,
a_FRINDEX_oData => a_FRINDEX_Wr,
a_FRINDEX_Wr_En => a_FRINDEX_Wr_En,
a_Setup_Buffer_Bytes_3_0_oData => a_Setup_Buffer_Bytes_3_0_Wr,
a_Setup_Buffer_Bytes_7_4_oData => a_Setup_Buffer_Bytes_7_4_Wr,
a_PORTSC1_PSPD_oData => a_PORTSC1_PSPD_Wr,
a_PORTSC1_PSPD_Wr_En => a_PORTSC1_PSPD_Wr_En,
a_ENDPTNAK_oData => a_ENDPTNAK_Wr,
a_ENDPTNAK_Wr_En => a_ENDPTNAK_Wr_En,
a_ENDPTSETUP_RECEIVED_oData => a_PE_ENDPTSETUP_RECEIVED_Wr,
a_ENDPTSETUP_RECEIVED_Wr_En => a_PE_ENDPTSETUP_RECEIVED_Wr_En,
a_USBSTS_NAKI_oData => a_USBSTS_Wr_NAKI,
a_USBSTS_SLI_oData => a_USBSTS_Wr_SLI,
a_USBSTS_SRI_oData => a_USBSTS_Wr_SRI,
a_USBSTS_URI_oData => a_USBSTS_Wr_URI,
a_USBSTS_PCI_oData => a_USBSTS_Wr_PCI,
a_USBSTS_NAKI_Wr_En => a_USBSTS_Wr_En_NAK,
a_USBSTS_SLI_Wr_En => a_USBSTS_Wr_En_SLI,
a_USBSTS_SRI_Wr_En => a_USBSTS_Wr_En_SRI,
a_USBSTS_URI_Wr_En => a_USBSTS_Wr_En_URI,
a_USBSTS_PCI_Wr_En => a_USBSTS_Wr_En_PCI,
u_Send_Zero_Length_Packet_Rd => u_Send_Zero_Length_Packet_oData,
a_Send_Zero_Length_Packet_Clear_oData => a_Send_Zero_Length_Packet_Clear,
a_Send_Zero_Length_Packet_Clear_En => a_Send_Zero_Length_Packet_Clear_En,
a_Send_Zero_Length_Packet_Ack_oData => a_Send_Zero_Length_Packet_Ack_Set,
a_Send_Zero_Length_Packet_Ack_Set_En => a_Send_Zero_Length_Packet_Ack_Set_En,
a_In_Packet_Complete_oData => a_In_Packet_Complete_Set,
a_In_Packet_Complete_Set_En => a_In_Packet_Complete_Set_En,
a_Cnt_Bytes_Sent_oData => a_Cnt_Bytes_Sent,
a_Cnt_Bytes_Sent_oValid => a_Cnt_Bytes_Sent_oValid,
a_In_Token_Received_oData => a_In_Token_Received_Set,
a_In_Token_Received_Set_En => a_In_Token_Received_Set_En,
a_Resend_oData => a_Resend_oData,
a_Resend_Wr_En => a_Resend_Wr_En,
a_Endpt_Nr => a_Pe_Endpt_Nr,
u_Endp_Nr => pe_endpt_nr_ulpi_clk,
u_Endp_Nr_Arb => "00000",
u_Endp_Nr_Arb_Ack => open,
u_Endp_Nr_Arb_Valid => '0',
u_USBCMD_RS => u_USBCMD_RS,
u_Endp_Type => u_Endpt_Type_oData,
u_Endp_Stall => u_Endpt_Stall_oData,
u_USBADRA => u_DEVICEADDR_rd(31 downto 24),
-- endp_enable => pe_endpt_enable,
state_ind => state_ind,
state_ind_hs => state_ind_hs,
state_ind_pd => state_ind_pd
);
-- ULPI clock deskew
Ulpi_Clk_MMCM_Clkin <= ulpi_clk;
MMCME2_BASE_inst: MMCME2_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- Jitter programming (OPTIMIZED, HIGH, LOW)
CLKFBOUT_MULT_F => 10.0, -- Multiply value for all CLKOUT (2.000-64.000).
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB (-360.000-360.000).
CLKIN1_PERIOD => 0.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
-- CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT6_DIVIDE => 1,
CLKOUT0_DIVIDE_F => 10.0, -- Divide amount for CLKOUT0 (1.000-128.000).
-- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
CLKOUT6_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
CLKOUT6_PHASE => 0.0,
CLKOUT4_CASCADE => FALSE, -- Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
DIVCLK_DIVIDE => 1, -- Master division value (1-106)
REF_JITTER1 => 0.0, -- Reference input jitter in UI (0.000-0.999).
STARTUP_WAIT => FALSE -- Delays DONE until MMCM is locked (FALSE, TRUE)
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => Ulpi_Clk_MMCM_Clkout0, -- 1-bit output: CLKOUT0
CLKOUT0B => open, -- 1-bit output: Inverted CLKOUT0
CLKOUT1 => open, -- 1-bit output: CLKOUT1
CLKOUT1B => open, -- 1-bit output: Inverted CLKOUT1
CLKOUT2 => open, -- 1-bit output: CLKOUT2
CLKOUT2B => open, -- 1-bit output: Inverted CLKOUT2
CLKOUT3 => open, -- 1-bit output: CLKOUT3
CLKOUT3B => open, -- 1-bit output: Inverted CLKOUT3
CLKOUT4 => open, -- 1-bit output: CLKOUT4
CLKOUT5 => open, -- 1-bit output: CLKOUT5
CLKOUT6 => open, -- 1-bit output: CLKOUT6
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => Ulpi_Clk_MMCM_Clkfbout, -- 1-bit output: Feedback clock
CLKFBOUTB => open, -- 1-bit output: Inverted CLKFBOUT
-- Status Ports: 1-bit (each) output: MMCM status ports
LOCKED => Ulpi_Clk_MMCM_Locked, -- 1-bit output: LOCK
-- Clock Inputs: 1-bit (each) input: Clock input
CLKIN1 => Ulpi_Clk_MMCM_Clkin, -- 1-bit input: Clock
-- Control Ports: 1-bit (each) input: MMCM control ports
PWRDWN => '0', -- 1-bit input: Power-down
RST => u_MMCM_Rst, -- 1-bit input: Reset
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => Ulpi_Clk_MMCM_Clkfbin -- 1-bit input: Feedback clock
);
BUFG_inst : BUFG
port map (
O => Ulpi_Clk_MMCM_Clkfbin, -- 1-bit output: Clock output
I => Ulpi_Clk_MMCM_Clkfbout -- 1-bit input: Clock input
);
--DMA needs to write/read to/from both packet FIFOs and context memory; "MUX" implemented below
a_DMA_S_Axis_S2MM_Tdata <= a_Arb_Axis_S2MM_Tdata when (a_Axis_S2MM_Mux_Ctrl = '1') else
a_FIFO_Axis_S2MM_Tdata;
a_DMA_S_Axis_S2MM_Tkeep <= a_Arb_Axis_S2MM_Tkeep when (a_Axis_S2MM_Mux_Ctrl = '1') else
a_FIFO_Axis_S2MM_Tkeep;
a_DMA_S_Axis_S2MM_Tvalid <= a_Arb_Axis_S2MM_Tvalid when (a_Axis_S2MM_Mux_Ctrl = '1') else
a_FIFO_Axis_S2MM_Tvalid;
a_Arb_Axis_S2MM_Tready <= a_DMA_S_Axis_S2MM_Tready when (a_Axis_S2MM_Mux_Ctrl = '1') else
'0';
a_FIFO_Axis_S2MM_Tready <= a_DMA_S_Axis_S2MM_Tready when (a_Axis_S2MM_Mux_Ctrl = '0') else
'0';
a_DMA_S_Axis_S2MM_Tlast <= a_Arb_Axis_S2MM_Tlast when (a_Axis_S2MM_Mux_Ctrl = '1') else
a_FIFO_Axis_S2MM_Tlast;
a_Arb_Axis_MM2S_Tdata <= a_DMA_M_Axis_MM2S_Tdata when (a_Axis_MM2S_Mux_Ctrl = '1') else (others => '0');
a_FIFO_Axis_MM2S_Tdata <= a_DMA_M_Axis_MM2S_Tdata when (a_Axis_MM2S_Mux_Ctrl = '0') else (others => '0');
a_Arb_Axis_MM2S_Tkeep <= a_DMA_M_Axis_MM2S_Tkeep when (a_Axis_MM2S_Mux_Ctrl = '1') else (others => '0');
a_FIFO_Axis_MM2S_Tkeep <= a_DMA_M_Axis_MM2S_Tkeep when (a_Axis_MM2S_Mux_Ctrl = '0') else (others => '0');
a_Arb_Axis_MM2S_Tvalid <= a_DMA_M_Axis_MM2S_Tvalid when (a_Axis_MM2S_Mux_Ctrl = '1') else '0';
a_FIFO_Axis_MM2S_Tvalid <= a_DMA_M_Axis_MM2S_Tvalid when (a_Axis_MM2S_Mux_Ctrl = '0') else '0';
a_DMA_M_Axis_MM2S_Tready <= a_Arb_Axis_MM2S_Tready when (a_Axis_MM2S_Mux_Ctrl = '1') else
a_FIFO_Axis_MM2S_Tready;
a_Arb_Axis_MM2S_Tlast <= a_DMA_M_Axis_MM2S_Tlast when (a_Axis_MM2S_Mux_Ctrl = '1') else '0';
a_FIFO_Axis_MM2S_Tlast <= a_DMA_M_Axis_MM2S_Tlast when (a_Axis_MM2S_Mux_Ctrl = '0') else '0';
--------------------------------------------------------------------------------------------------
ENDPTCTRL(0) <= a_ENDPTCTRL0_Rd;
ENDPTCTRL(1) <= a_ENDPTCTRL1_Rd;
ENDPTCTRL(2) <= a_ENDPTCTRL2_Rd;
ENDPTCTRL(3) <= a_ENDPTCTRL3_Rd;
ENDPTCTRL(4) <= a_ENDPTCTRL4_Rd;
ENDPTCTRL(5) <= a_ENDPTCTRL5_Rd;
ENDPTCTRL(6) <= a_ENDPTCTRL6_Rd;
ENDPTCTRL(7) <= a_ENDPTCTRL7_Rd;
ENDPTCTRL(8) <= a_ENDPTCTRL8_Rd;
ENDPTCTRL(9) <= a_ENDPTCTRL9_Rd;
ENDPTCTRL(10) <= a_ENDPTCTRL10_Rd;
ENDPTCTRL(11) <= a_ENDPTCTRL11_Rd;
ENDP_TYPE_PROC: process (ENDPTCTRL)
begin
for endpt_type_index in 0 to 11 loop
a_Endpt_Type_iData((endpt_type_index*4+3) downto endpt_type_index*4) <= ENDPTCTRL(endpt_type_index)(19 downto 18) & ENDPTCTRL(endpt_type_index)(3 downto 2);
a_Endpt_Stall_iData((endpt_type_index*2+1) downto endpt_type_index*2) <= ENDPTCTRL(endpt_type_index)(16) & ENDPTCTRL(endpt_type_index)(0);
a_Endpt_Enable_iData((endpt_type_index*2+1) downto endpt_type_index*2) <= ENDPTCTRL(endpt_type_index)(23) & ENDPTCTRL(endpt_type_index)(7);
end loop;
end process;
TX_FIFO_RESET_PROC: process (ENDPTCTRL)
begin
for tx_fifo_reset_index in 0 to 11 loop
tx_fifo_reset_vector(tx_fifo_reset_index) <= (not(a_EMDPTFLUSH_Rd(tx_fifo_reset_index+16)) and arb_tx_fifo_s_aresetn);
end loop;
end process;
--Synchronization modules for data that crosses the AXI clock domain to ULPI clock domain
ENDPT_TYPE_IPUSH_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_Endpt_Type_iData_q <= (others => '0');
a_Endpt_Type_iPush <= '0';
else
a_Endpt_Type_iData_q <= a_Endpt_Type_iData;
if(a_Endpt_Type_iData_q /= a_Endpt_Type_iData and a_Endpt_Type_iRdy = '1') then
a_Endpt_Type_iPush <= '1';
else
a_Endpt_Type_iPush <= '0';
end if;
end if;
end if;
end process;
ENDPT_STALL_IPUSH_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_Endpt_Stall_iData_q <= (others => '0');
a_Endpt_Stall_iPush <= '0';
else
a_Endpt_Stall_iData_q <= a_Endpt_Stall_iData;
if(a_Endpt_Stall_iData_q /= a_Endpt_Stall_iData and a_Endpt_Stall_iRdy = '1') then
a_Endpt_Stall_iPush <= '1';
else
a_Endpt_Stall_iPush <= '0';
end if;
end if;
end if;
end process;
ENDPT_ENABLE_IPUSH_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_Endpt_Enable_iData_q <= (others => '0');
a_Endpt_Enable_iPush <= '0';
else
a_Endpt_Enable_iData_q <= a_Endpt_Enable_iData;
if(a_Endpt_Enable_iData_q /= a_Endpt_Enable_iData and a_Endpt_Enable_iRdy = '1') then
a_Endpt_Enable_iPush <= '1';
else
a_Endpt_Enable_iPush <= '0';
end if;
end if;
end if;
end process;
ZERO_LENGTH_PUSH_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_Send_Zero_Length_Packet_iData_q <= (others => '0');
a_Send_Zero_Length_Packet_iPush <= '0';
else
a_Send_Zero_Length_Packet_iData_q <= a_Send_Zero_Length_Packet_iData;
if(a_Send_Zero_Length_Packet_iData_q /= a_Send_Zero_Length_Packet_iData and a_Send_Zero_Length_Packet_iRdy = '1') then
a_Send_Zero_Length_Packet_iPush <= '1';
else
a_Send_Zero_Length_Packet_iPush <= '0';
end if;
end if;
end if;
end process;
SyncAsyncPushT_USBCMD_RS: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aReset => a_Axi_Reset,
aIn => a_USBCMD_RS,
OutClk => Ulpi_Clk_MMCM_Clkout0,
oOut => u_USBCMD_RS
);
Inst_HandshakeData_endpt_type: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 48)
PORT MAP(
InClk => S_AXI_ACLK,
OutClk => Ulpi_Clk_MMCM_Clkout0,
iData => a_Endpt_Type_iData,
oData => u_Endpt_Type_oData,
iPush => a_Endpt_Type_iPush,
iRdy => a_Endpt_Type_iRdy,
oAck => u_Endpt_Type_oValid,
oValid => u_Endpt_Type_oValid,
aReset => a_Axi_Reset
);
Inst_HandshakeData_endpt_stall: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 24)
PORT MAP(
InClk => S_AXI_ACLK,
OutClk => Ulpi_Clk_MMCM_Clkout0,
iData => a_Endpt_Stall_iData,
oData => u_Endpt_Stall_oData,
iPush => a_Endpt_Stall_iPush,
iRdy => a_Endpt_Stall_iRdy,
oAck => u_Endpt_Stall_oValid,
oValid => u_Endpt_Stall_oValid,
aReset => a_Axi_Reset
);
Inst_HandshakeData_endpt_enable: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 24)
PORT MAP(
InClk => S_AXI_ACLK,
OutClk => Ulpi_Clk_MMCM_Clkout0,
iData => a_Endpt_Enable_iData,
oData => u_Endpt_Enable_oData,
iPush => a_Endpt_Enable_iPush,
iRdy => a_Endpt_Enable_iRdy,
oAck => u_Endpt_Enable_oValid,
oValid => u_Endpt_Enable_oValid,
aReset => a_Axi_Reset
);
Inst_HandshakeData_send_zero_length_packet: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => S_AXI_ACLK,
OutClk => Ulpi_Clk_MMCM_Clkout0,
iData => a_Send_Zero_Length_Packet_iData,
oData => u_Send_Zero_Length_Packet_oData,
iPush => a_Send_Zero_Length_Packet_iPush,
iRdy => a_Send_Zero_Length_Packet_iRdy,
oAck => u_Send_Zero_Length_Packet_oValid,
oValid => u_Send_Zero_Length_Packet_oValid,
aReset => a_Axi_Reset
);
Inst_HandshakeData_DEVICEADDR: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => S_AXI_ACLK,
OutClk => Ulpi_Clk_MMCM_Clkout0,
iData => a_DEVICEADDR_rd,
oData => u_DEVICEADDR_rd,
iPush => a_DEVICEADDR_IPush,
iRdy => a_DEVICEADDR_IRdy,
oAck => u_DEVICEADDR_oValid,
oValid => u_DEVICEADDR_oValid,
aReset => a_Axi_Reset
);
--Interrupts
a_USBSTS_UI_Change <= a_ENDPTSETUPSTAT_Wr_En or a_ENDPTCOMPLETE_Wr_En;
INTERRUPT_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_INTERRUPT_Loc <= '0';
else
if ((a_USBINTR_Rd and a_USBSTS_Rd) /= "00000000000000000000000000000000") then
if (a_USBSTS_UI_Change = '1') then
a_INTERRUPT_Loc <= '0';
else
a_INTERRUPT_Loc <= '1';
end if;
else
a_INTERRUPT_Loc <= '0';
end if;
end if;
end if;
end process;
INTERRUPT <= a_INTERRUPT_Loc;
--Status Registers, Hanshake between Protocol_Engine and DMA_Transfer_Manager
ENDPT_FLUSH_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_ENDPTFLUSH_Clear <= (others => '0');
a_ENDPTFLUSH_Clear_En <= '0';
else
if(a_EMDPTFLUSH_Rd /= "00000000000000000000000000000000") then
a_ENDPTFLUSH_Clear_En <= '1';
a_ENDPTFLUSH_Clear <= (others => '0');
else
a_ENDPTFLUSH_Clear_En <= '0';
end if;
end if;
end if;
end process;
ENDPTSETUP_RECEIVED_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_Arb_ENDPTSETUP_RECEIVED_Rd <= (others => '0');
a_Arb_ENDPTSETUP_RECEIVED_Ack <= '0';
else
if (a_PE_ENDPTSETUP_RECEIVED_Wr_En = '1') then
a_Arb_ENDPTSETUP_RECEIVED_Rd <= a_PE_ENDPTSETUP_RECEIVED_Wr;
a_Arb_ENDPTSETUP_RECEIVED_Ack <= '0';
elsif(a_Arb_ENDPTSETUP_RECEIVED_Clear_En = '1') then
a_Arb_ENDPTSETUP_RECEIVED_Rd <= a_Arb_ENDPTSETUP_RECEIVED_Rd and a_Arb_ENDPTSETUP_RECEIVED_Clear;
a_Arb_ENDPTSETUP_RECEIVED_Ack <= '1';
else
a_Arb_ENDPTSETUP_RECEIVED_Ack <= '0';
end if;
end if;
end if;
end process;
PACKET_IN_COMPLETE_RD_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_In_Packet_Complete_Rd <= (others => '0');
else
if (a_In_Packet_Complete_Set_En = '1') then
a_In_Packet_Complete_Rd <= a_In_Packet_Complete_Rd or a_In_Packet_Complete_Set;
elsif(a_In_Packet_Complete_Clear_En = '1') then
a_In_Packet_Complete_Rd <= a_In_Packet_Complete_Rd and a_In_Packet_Complete_Clear;
end if;
end if;
end if;
end process;
SEND_ZERO_LENGTH_RD_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_Send_Zero_Length_Packet_iData <= (others => '0');
else
if (a_Send_Zero_Length_Packet_Set_En = '1') then
a_Send_Zero_Length_Packet_iData <= a_Send_Zero_Length_Packet_iData or a_Send_Zero_Length_Packet_Set;
elsif(a_Send_Zero_Length_Packet_Clear_En = '1') then
a_Send_Zero_Length_Packet_iData <= a_Send_Zero_Length_Packet_iData and a_Send_Zero_Length_Packet_Clear;
end if;
end if;
end if;
end process;
SEND_ZERO_LENGTH_ACK_RD_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_Send_Zero_Length_Packet_Ack_Rd <= (others => '0');
else
if (a_Send_Zero_Length_Packet_Ack_Set_En = '1') then
a_Send_Zero_Length_Packet_Ack_Rd <= a_Send_Zero_Length_Packet_Ack_Rd or a_Send_Zero_Length_Packet_Ack_Set;
elsif(a_Send_Zero_Length_Packet_Ack_Clear_En = '1') then
a_Send_Zero_Length_Packet_Ack_Rd <= a_Send_Zero_Length_Packet_Ack_Rd and a_Send_Zero_Length_Packet_Ack_Clear;
end if;
end if;
end if;
end process;
RESEND_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_Resend <= (others => '0');
else
if (a_Resend_Wr_En = '1') then
a_Resend <= a_Resend or a_Resend_oData;
elsif(a_Resend_Clear_En = '1') then
a_Resend <= a_Resend and a_Resend_Clear;
end if;
end if;
end if;
end process;
PE_IN_TOKEN_RECEIVED_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_In_Token_Received_Rd <= (others => '0');
else
if (a_In_Token_Received_Set_En = '1') then
a_In_Token_Received_Rd <= a_In_Token_Received_Rd or a_In_Token_Received_Set;
elsif(a_In_Token_Received_Clear_En = '1') then
a_In_Token_Received_Rd <= a_In_Token_Received_Rd and a_In_Token_Received_Clear;
end if;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: top.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This is the top module of the USB_Device IP core. It is designed to work
-- with an ULPI PHY and, together, to implement the Electrical layer and the
-- Protocol layer of the USB 2.0 device. It exports an AXI Lite slave
-- interface to communicate with the processor. An integrated DMA engine is
-- suposed to connect to the system memory through an AXI4 interface.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top is
-- Port ( );
port (
S_AXI_ACLK : IN std_logic;
INTERRUPT : OUT STD_LOGIC;
--ULPI Interface
ulpi_clk : in STD_LOGIC;
ulpi_data : inout STD_LOGIC_VECTOR(7 downto 0);
ulpi_dir : in STD_LOGIC;
ulpi_nxt : in STD_LOGIC;
ulpi_stp : out STD_LOGIC;
led : out STD_LOGIC;
ulpi_resetn : out STD_LOGIC;
--AXI4 exported by the AXI DMA Controller
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
--AXI Lite Slave interface; Access to Control Registers
S_AXI_ARESETN : IN std_logic;
S_AXI_AWADDR : IN std_logic_vector(31 downto 0);
S_AXI_AWPROT : IN std_logic_vector(2 downto 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_WDATA : IN std_logic_vector(31 downto 0);
S_AXI_WSTRB : IN std_logic_vector(3 downto 0);
S_AXI_WVALID : IN std_logic;
S_AXI_BREADY : IN std_logic;
S_AXI_ARADDR : IN std_logic_vector(31 downto 0);
S_AXI_ARPROT : IN std_logic_vector(2 downto 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_RREADY : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BRESP : OUT std_logic_vector(1 downto 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RDATA : OUT std_logic_vector(31 downto 0);
S_AXI_RRESP : OUT std_logic_vector(1 downto 0);
S_AXI_RVALID : OUT std_logic
);
end top;
architecture Behavioral of top is
COMPONENT Control_Registers
PORT(
S_AXI_ACLK : IN std_logic;
S_AXI_ARESETN : IN std_logic;
S_AXI_AWADDR : IN std_logic_vector(31 downto 0);
S_AXI_AWPROT : IN std_logic_vector(2 downto 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_WDATA : IN std_logic_vector(31 downto 0);
S_AXI_WSTRB : IN std_logic_vector(3 downto 0);
S_AXI_WVALID : IN std_logic;
S_AXI_BREADY : IN std_logic;
S_AXI_ARADDR : IN std_logic_vector(31 downto 0);
S_AXI_ARPROT : IN std_logic_vector(2 downto 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_RREADY : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BRESP : OUT std_logic_vector(1 downto 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RDATA : OUT std_logic_vector(31 downto 0);
S_AXI_RRESP : OUT std_logic_vector(1 downto 0);
S_AXI_RVALID : OUT std_logic;
USBSCFG_rd : out std_logic_vector(31 downto 0);
USBCMD_rd : out std_logic_vector(31 downto 0);
USBCMD_SUTW_wr : in std_logic;
USBCMD_SUTW_wr_en : in std_logic;
USBCMD_ATDTW_wr : in std_logic;
USBCMD_ATDTW_wr_en : in std_logic;
USBSTS_rd : out std_logic_vector(31 downto 0);
USBSTS_wr_UI : in std_logic;
USBSTS_wr_NAKI : in std_logic;
USBSTS_wr_SLI : in std_logic;
USBSTS_wr_SRI : in std_logic;
USBSTS_wr_URI : in std_logic;
USBSTS_wr_PCI : in std_logic;
USBSTS_wr_en_NAK : in std_logic;
USBSTS_wr_en_SLI : in std_logic;
USBSTS_wr_en_SRI : in std_logic;
USBSTS_wr_en_URI : in std_logic;
USBSTS_wr_en_PCI : in std_logic;
USBSTS_wr_en_UI : in std_logic;
USBINTR_rd : out std_logic_vector(31 downto 0);
FRINDEX_rd : out std_logic_vector(31 downto 0);
FRINDEX_wr : in std_logic_vector(10 downto 0);
FRINDEX_wr_en : in std_logic;
a_DEVICEADDR_rd : out std_logic_vector(31 downto 0);
a_DEVICEADDR_IPush : out std_logic;
ENDPOINTLISTADDR_rd : out std_logic_vector(31 downto 0);
ENDPTNAK_rd : out std_logic_vector(31 downto 0);
ENDPTNAK_wr : in std_logic_vector(31 downto 0);
ENDPTNAK_wr_en : in std_logic;
ENDPTNAKEN_rd : out std_logic_vector(31 downto 0);
CONFIGFLAG_rd : out std_logic_vector(31 downto 0);
PORTSC1_rd : out std_logic_vector(31 downto 0);
PORTSC1_PSPD_Wr : in std_logic_vector(1 downto 0);
PORTSC1_PSPD_wr_en : in std_logic;
OTGSC_rd : out std_logic_vector(31 downto 0);
USBMODE_rd : out std_logic_vector(31 downto 0);
ENDPTSETUPSTAT_rd : out std_logic_vector(31 downto 0);
ENDPTSETUPSTAT_wr : in std_logic_vector(31 downto 0);
ENDPTSETUPSTAT_wr_en : in std_logic;
ENDPTPRIME_rd : out std_logic_vector(31 downto 0);
ENDPTPRIME_clear : in std_logic_vector(31 downto 0);
ENDPTPRIME_clear_en : in std_logic;
ENDPTPRIME_set : in std_logic_vector(31 downto 0);
ENDPTPRIME_set_en : in std_logic;
EMDPTFLUSH_rd : out std_logic_vector(31 downto 0);
EMDPTFLUSH_clear : in std_logic_vector(31 downto 0);
EMDPTFLUSH_clear_en : in std_logic;
EMDPTFLUSH_set : in std_logic_vector(31 downto 0);
EMDPTFLUSH_set_en : in std_logic;
ENDPTSTAT_wr : in std_logic_vector(31 downto 0);
ENDPTCOMPLETE_rd : out std_logic_vector(31 downto 0);
ENDPTCOMPLETE_wr : in std_logic_vector(31 downto 0);
ENDPTCOMPLETE_wr_en : in std_logic;
ENDPTCTRL0_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL1_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL2_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL3_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL4_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL5_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL6_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL7_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL8_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL9_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL10_rd : out std_logic_vector(31 downto 0);
ENDPTCTRL11_rd : out std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT DMA_Transfer_Manager
PORT(
Axi_Resetn : IN STD_LOGIC;
Axi_Clk : IN STD_LOGIC;
ind_statte_axistream : out std_logic_vector(4 downto 0);
DEBUG_REG_DATA : OUT std_logic_vector(31 downto 0);
state_ind_dma : out STD_LOGIC_VECTOR(4 downto 0);
state_ind_arb : out std_logic_vector(5 downto 0);
a_M_Axi_Awaddr : out std_logic_vector(9 downto 0);
a_M_Axi_Awprot : out std_logic_vector(2 downto 0);
a_M_Axi_Awvalid : out std_logic;
a_M_Axi_Awready : in std_logic;
a_M_Axi_Wdata : out std_logic_vector(31 downto 0);
a_M_Axi_Wstrb : out std_logic_vector(3 downto 0);
a_M_Axi_Wvalid : out std_logic;
a_M_Axi_Wready : in std_logic;
a_M_Axi_Bresp : in std_logic_vector(1 downto 0);
a_M_Axi_Bvalid : in std_logic;
a_M_Axi_Bready : out std_logic;
a_M_Axi_Araddr : out std_logic_vector(9 downto 0);
a_M_Axi_Arprot : out std_logic_vector(2 downto 0);
a_M_Axi_Arvalid : out std_logic;
a_M_Axi_Arready : in std_logic;
a_M_Axi_Rdata : in std_logic_vector(31 downto 0);
a_M_Axi_Rresp : in std_logic_vector(1 downto 0);
a_M_Axi_Rvalid : in std_logic;
a_M_Axi_Rready : out std_logic;
a_S_Axis_MM2S_Tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_S_Axis_MM2S_Tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
a_S_Axis_MM2S_Tvalid : IN STD_LOGIC;
a_S_Axis_MM2S_Tready : OUT STD_LOGIC;
a_S_Axis_MM2S_Tlast : IN STD_LOGIC;
a_M_Axis_S2MM_Tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a_M_Axis_S2MM_Tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
a_M_Axis_S2MM_Tvalid : OUT STD_LOGIC;
a_M_Axis_S2MM_Tready : IN STD_LOGIC;
a_M_Axis_S2MM_Tlast : OUT STD_LOGIC;
RX_COMMAND_FIFO_RD_EN : OUT std_logic;
RX_COMMAND_FIFO_DOUT : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
RX_COMMAND_FIFO_EMPTY : IN std_logic;
RX_COMMAND_FIFO_VALID : IN std_logic;
a_Axis_MM2S_Mux_Ctrl : OUT STD_LOGIC;
a_Axis_S2MM_Mux_Ctrl : OUT STD_LOGIC;
a_Send_Zero_Length_Packet_Set : OUT STD_LOGIC_VECTOR(31 downto 0);
a_Send_Zero_Length_Packet_Set_En : OUT STD_LOGIC;
a_Send_Zero_Length_Packet_Ack_Rd : IN STD_LOGIC_VECTOR(31 downto 0);
a_Send_Zero_Length_Packet_Ack_Clear : OUT STD_LOGIC_VECTOR(31 downto 0);
a_Send_Zero_Length_Packet_Ack_Clear_En : OUT STD_LOGIC;
a_Arb_dQH_Setup_Buffer_Bytes_3_0_Wr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_Arb_dQH_Setup_Buffer_Bytes_7_4_Wr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_In_Packet_Complete_Rd : IN STD_LOGIC_VECTOR(31 downto 0);
a_In_Packet_Complete_Clear : OUT STD_LOGIC_VECTOR(31 downto 0);
a_In_Packet_Complete_Clear_En : OUT STD_LOGIC;
a_In_Token_Received_Rd : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_In_Token_Received_Clear : OUT STD_LOGIC_VECTOR(31 downto 0);
a_In_Token_Received_Clear_En : OUT STD_LOGIC;
a_Resend : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_Resend_Clear : OUT STD_LOGIC_VECTOR(31 downto 0);
a_Resend_Clear_En : OUT STD_LOGIC;
a_Cnt_Bytes_Sent : IN std_logic_vector(12 downto 0);
a_Cnt_Bytes_Sent_oValid : IN std_logic;
a_Pe_Endpt_Nr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
a_Arb_Endpt_Nr : out std_logic_vector(4 downto 0);
arb_tx_fifo_s_aresetn : OUT std_logic;
a_USBSTS_Wr_UI : OUT std_logic;
a_USBSTS_Wr_en_UI : OUT std_logic;
a_USBMODE_Rd : in std_logic_vector(31 downto 0);
a_USBCMD_SUTW_Wr : out std_logic;
a_USBCMD_SUTW_Wr_En : out std_logic;
a_USBCMD_ATDTW_Wr : out std_logic;
a_USBCMD_ATDTW_Wr_En : out std_logic;
a_EMDPTFLUSH_Rd : in std_logic_vector(31 downto 0);
a_EMDPTFLUSH_Set : out std_logic_vector(31 downto 0);
a_EMDPTFLUSH_Set_En : out std_logic;
a_ENDPTPRIME_Rd : in std_logic_vector(31 downto 0);
a_ENDPTPRIME_Clear : out std_logic_vector(31 downto 0);
a_ENDPTPRIME_Clear_En : out std_logic;
a_ENDPTPRIME_Set : out std_logic_vector(31 downto 0);
a_ENDPTPRIME_Set_En : out std_logic;
a_ENDPTSTAT_Wr : out std_logic_vector(31 downto 0);
a_ENDPTCOMPLETE_Wr : out std_logic_vector(31 downto 0);
a_ENDPTCOMPLETE_Wr_En : out std_logic;
a_ENDPTSETUPSTAT_Wr : out std_logic_vector(31 downto 0);
a_ENDPTSETUPSTAT_Wr_En : out std_logic;
a_Arb_ENDPTSETUP_RECEIVED_Rd : in std_logic_vector(31 downto 0);
a_Arb_ENDPTSETUP_RECEIVED_Clear : out std_logic_vector(31 downto 0);
a_Arb_ENDPTSETUP_RECEIVED_Clear_En : out std_logic;
a_Arb_ENDPTSETUP_RECEIVED_Ack : in std_logic;
a_ENDPOINTLISTADDR_Rd : in std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT axi_dma_0
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT FIFO
PORT(
resetn : IN STD_LOGIC;
rx_fifo_s_aresetn : IN std_logic;
rx_fifo_m_aclk : IN std_logic;
rx_fifo_s_aclk : IN std_logic;
rx_fifo_s_axis_tvalid : IN std_logic;
rx_fifo_s_axis_tdata : IN std_logic_vector(31 downto 0);
rx_fifo_s_axis_tkeep : IN std_logic_vector (3 downto 0);
rx_fifo_s_axis_tlast : IN std_logic;
rx_fifo_s_axis_tuser : IN std_logic_vector(3 downto 0);
rx_fifo_m_axis_tready : IN std_logic;
rx_fifo_s_axis_tready : OUT std_logic;
rx_fifo_m_axis_tvalid : OUT std_logic;
rx_fifo_m_axis_tdata : OUT std_logic_vector(31 downto 0);
rx_fifo_m_axis_tlast : OUT std_logic;
rx_fifo_m_axis_tuser : OUT std_logic_vector(3 downto 0);
rx_fifo_m_axis_tkeep : OUT std_logic_vector(3 downto 0);
rx_fifo_axis_overflow : OUT std_logic;
rx_fifo_axis_underflow : OUT std_logic
);
END COMPONENT;
COMPONENT Protocol_Engine
PORT(
axi_clk : IN std_logic;
Axi_ResetN : in STD_LOGIC;
Ulpi_Clk : in STD_LOGIC;
u_ResetN : in STD_LOGIC;
ulpi_reset : out STD_LOGIC;
u_Ulpi_Data : inout STD_LOGIC_VECTOR(7 downto 0);
u_Ulpi_Dir : in STD_LOGIC;
u_Ulpi_Nxt : in STD_LOGIC;
u_Ulpi_Stp : out STD_LOGIC;
led : out STD_LOGIC;
a_Arb_Endpt_Nr : in std_logic_vector(4 downto 0); --!!!!! bits need to be synchronised
Tx_Fifo_S_Aresetn : IN STD_LOGIC;
a_Tx_Fifo_S_Aclk : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tvalid : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tready : OUT STD_LOGIC;
a_Tx_Fifo_S_Axis_Tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_Tx_Fifo_S_Axis_Tlast : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tkeep : IN std_logic_vector(3 downto 0);
a_Tx_Fifo_S_Axis_Tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
tx_fifo_axis_overflow : OUT STD_LOGIC;
tx_fifo_axis_underflow : OUT STD_LOGIC;
u_Rx_Fifo_s_Aclk : OUT std_logic;
u_Rx_Fifo_s_Axis_Tready : IN std_logic;
u_Rx_Fifo_s_Axis_Tvalid : OUT std_logic;
u_Rx_Fifo_s_Axis_Tdata : OUT std_logic_vector(31 downto 0);
u_Rx_Fifo_s_Axis_Tkeep : OUT std_logic_vector (3 downto 0);
u_Rx_Fifo_s_Axis_Tlast : OUT std_logic;
u_Rx_Fifo_Axis_Overflow : IN std_logic;
u_Rx_Fifo_Axis_Underflow : IN std_logic;
u_Command_Fifo_Rd_En : IN std_logic;
u_Command_Fifo_Dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
u_Command_Fifo_Empty : OUT std_logic;
u_Command_Fifo_Valid : OUT std_logic;
u_USBADRA : in STD_LOGIC_VECTOR (7 downto 0);
u_Endp_Nr_Arb : IN STD_LOGIC_VECTOR(4 DOWNTO 0); --new
u_Endp_Nr_Arb_Ack : OUT std_logic;
u_Endp_Nr_Arb_Valid : IN std_logic;
u_Endp_Type : in STD_LOGIC_VECTOR(47 downto 0);
u_Endp_Stall : IN STD_LOGIC_VECTOR(23 downto 0);
u_USBCMD_RS : in std_logic;
-- endp_enable : IN STD_LOGIC(11 downto 0); --new
a_In_Packet_Complete_oData : OUT std_logic_vector(31 downto 0);
a_In_Packet_Complete_Set_En : OUT std_logic;
u_Send_Zero_Length_Packet_Rd : IN STD_LOGIC_VECTOR(31 downto 0);
a_Send_Zero_Length_Packet_Clear_oData : OUT STD_LOGIC_VECTOR(31 downto 0);
a_Send_Zero_Length_Packet_Clear_En : OUT STD_LOGIC;
a_Send_Zero_Length_Packet_Ack_oData : OUT STD_LOGIC_VECTOR(31 downto 0);
a_Send_Zero_Length_Packet_Ack_Set_En : OUT STD_LOGIC;
a_Cnt_Bytes_Sent_oData : out std_logic_vector(12 downto 0); --new
a_Cnt_Bytes_Sent_oValid : OUT std_logic;
a_In_Token_Received_oData : OUT std_logic_vector(31 downto 0); --new
a_In_Token_Received_Set_En : OUT std_logic; --new
a_Resend_oData : OUT STD_LOGIC_VECTOR(31 downto 0);
a_Resend_Wr_En : OUT std_logic;
a_Endpt_Nr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --new + 1 bit
u_Endp_Nr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
a_FRINDEX_oData : out std_logic_vector(10 downto 0);
a_FRINDEX_Wr_En : out std_logic;
a_Setup_Buffer_Bytes_3_0_oData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a_Setup_Buffer_Bytes_7_4_oData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a_PORTSC1_PSPD_oData : out std_logic_vector(1 downto 0);
a_PORTSC1_PSPD_Wr_En : out std_logic;
a_ENDPTNAK_oData : out std_logic_vector(31 downto 0);
a_ENDPTNAK_Wr_En : out std_logic;
a_ENDPTSETUP_RECEIVED_oData : out std_logic_vector(31 downto 0);
a_ENDPTSETUP_RECEIVED_Wr_En : out std_logic;
a_USBSTS_NAKI_oData : out std_logic;
a_USBSTS_NAKI_Wr_En : out std_logic;
a_USBSTS_SLI_oData : out std_logic;
a_USBSTS_SLI_Wr_En : out std_logic;
a_USBSTS_SRI_oData : out std_logic;
a_USBSTS_SRI_Wr_En : out std_logic;
a_USBSTS_URI_oData : out std_logic;
a_USBSTS_URI_Wr_En : out std_logic;
a_USBSTS_PCI_oData : out std_logic;
a_USBSTS_PCI_Wr_En : out std_logic;
state_ind : out STD_LOGIC_VECTOR(5 downto 0);
state_ind_pd : out STD_LOGIC_VECTOR(6 downto 0);
state_ind_hs : out STD_LOGIC_VECTOR(4 downto 0)
);
END COMPONENT;
COMPONENT ResetBridge
Generic (
kPolarity : std_logic);
PORT(
aRst : IN std_logic;
OutClk : IN std_logic;
oRst : OUT std_logic
);
END COMPONENT;
type ENDPOINTCTRL_REGISTERS is array (11 downto 0) of std_logic_vector(31 downto 0);
signal ENDPTCTRL : ENDPOINTCTRL_REGISTERS;
signal Ulpi_Clk_MMCM_Clkin : STD_LOGIC;
signal Ulpi_Clk_MMCM_Clkfbin : STD_LOGIC;
signal Ulpi_Clk_MMCM_Clkfbout : STD_LOGIC;
signal Ulpi_Clk_MMCM_Clkout0 : STD_LOGIC;
signal Ulpi_Clk_MMCM_Locked : STD_LOGIC;
signal Ulpi_ResetN_oRst : STD_LOGIC;
signal u_ResetN : STD_LOGIC;
signal u_MMCM_Rst : STD_LOGIC;
signal a_Axi_Reset : STD_LOGIC;
signal a_Axi_DMA_Tstvec : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_MM2S_Introut : STD_LOGIC;
signal a_S2MM_Introut : STD_LOGIC;
signal a_S2MM_Prmry_Reset_Out_N : STD_LOGIC;
signal a_MM2S_Prmry_Reset_Out_N : STD_LOGIC;
------------------------------------------------------------------------
signal a_Axis_MM2S_Mux_Ctrl, a_Axis_S2MM_Mux_Ctrl : STD_LOGIC;
signal a_Setup_Buffer_Bytes_3_0_Wr : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_Setup_Buffer_Bytes_7_4_Wr : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_Pe_Endpt_Nr, pe_endpt_nr_ulpi_clk : STD_LOGIC_VECTOR(4 DOWNTO 0);
signal a_DMA_S_Axis_S2MM_Tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_DMA_S_Axis_S2MM_Tkeep : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal a_DMA_S_Axis_S2MM_Tvalid : STD_LOGIC;
signal a_DMA_S_Axis_S2MM_Tready : STD_LOGIC;
signal a_DMA_S_Axis_S2MM_Tlast : STD_LOGIC;
signal a_DMA_M_Axis_MM2S_Tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_DMA_M_Axis_MM2S_Tkeep : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal a_DMA_M_Axis_MM2S_Tvalid : STD_LOGIC;
signal a_DMA_M_Axis_MM2S_Tready : STD_LOGIC;
signal a_DMA_M_Axis_MM2S_Tlast : STD_LOGIC;
signal a_FIFO_Axis_S2MM_Tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_FIFO_Axis_S2MM_Tkeep : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal a_FIFO_Axis_S2MM_Tvalid : STD_LOGIC;
signal a_FIFO_Axis_S2MM_Tready : STD_LOGIC;
signal a_FIFO_Axis_S2MM_Tlast : STD_LOGIC;
signal a_FIFO_Axis_MM2S_Tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_FIFO_Axis_MM2S_Tkeep : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal a_FIFO_Axis_MM2S_Tvalid : STD_LOGIC;
signal a_FIFO_Axis_MM2S_Tready : STD_LOGIC;
signal a_FIFO_Axis_MM2S_Tlast : STD_LOGIC;
signal a_Arb_Axis_S2MM_Tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_Arb_Axis_S2MM_Tkeep : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal a_Arb_Axis_S2MM_Tvalid : STD_LOGIC;
signal a_Arb_Axis_S2MM_Tready : STD_LOGIC;
signal a_Arb_Axis_S2MM_Tlast : STD_LOGIC;
signal a_Arb_Axis_MM2S_Tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_Arb_Axis_MM2S_Tkeep : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal a_Arb_Axis_MM2S_Tvalid : STD_LOGIC;
signal a_Arb_Axis_MM2S_Tready : STD_LOGIC;
signal a_Arb_Axis_MM2S_Tlast : STD_LOGIC;
------------------------------------------------------------------------
signal u_Rx_Fifo_s_Aclk : STD_LOGIC;
signal u_Rx_Fifo_s_Axis_Tready : STD_LOGIC;
signal u_Rx_Fifo_s_Axis_Tvalid : STD_LOGIC;
signal u_Rx_Fifo_s_Axis_Tdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal u_Rx_Fifo_s_Axis_Tkeep : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal u_Rx_Fifo_s_Axis_Tlast : STD_LOGIC;
signal u_Rx_Fifo_Axis_Overflow : std_logic;
signal u_Rx_Fifo_Axis_Underflow : std_logic;
signal tx_fifo_reset_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
signal u_Command_Fifo_Rd_En : std_logic;
signal u_Command_Fifo_Dout : STD_LOGIC_VECTOR(23 DOWNTO 0);
signal u_Command_Fifo_Empty : std_logic;
signal u_Command_Fifo_Valid : std_logic;
signal a_DMA_Axilite_Awaddr : std_logic_vector(9 downto 0);
signal a_DMA_Axilite_Awprot : std_logic_vector(2 downto 0);
signal a_DMA_Axilite_Awvalid : std_logic;
signal a_DMA_Axilite_Awready : std_logic;
signal a_DMA_Axilite_Wdata : std_logic_vector(31 downto 0);
signal a_DMA_Axilite_Wstrb : std_logic_vector(3 downto 0);
signal a_DMA_Axilite_Wvalid : std_logic;
signal a_DMA_Axilite_Wready : std_logic;
signal a_DMA_Axilite_Bresp : std_logic_vector(1 downto 0);
signal a_DMA_Axilite_Bvalid : std_logic;
signal a_DMA_Axilite_Bready : std_logic;
signal a_DMA_Axilite_Araddr : std_logic_vector(9 downto 0);
signal a_DMA_Axilite_Arprot : std_logic_vector(2 downto 0);
signal a_DMA_Axilite_Arvalid : std_logic;
signal a_DMA_Axilite_Arready : std_logic;
signal a_DMA_Axilite_Rdata : std_logic_vector(31 downto 0);
signal a_DMA_Axilite_Rresp : std_logic_vector(1 downto 0);
signal a_DMA_Axilite_Rvalid : std_logic;
signal a_DMA_Axilite_Ready : std_logic;
signal arb_tx_fifo_s_aresetn : std_logic;
signal a_SBUSCFG_Rd : std_logic_vector(31 downto 0);
signal a_USBCMD_Rd : std_logic_vector(31 downto 0);
signal a_USBCMD_SUTW_Wr : std_logic;
signal a_USBCMD_SUTW_Wr_En : std_logic;
signal a_USBCMD_ATDTW_Wr : std_logic;
signal a_USBCMD_ATDTW_Wr_En : std_logic;
signal a_USBSTS_Rd : std_logic_vector(31 downto 0);
signal a_USBSTS_Wr_NAKI : std_logic;
signal a_USBSTS_Wr_SLI : std_logic;
signal a_USBSTS_Wr_SRI : std_logic;
signal a_USBSTS_Wr_URI : std_logic;
signal a_USBSTS_Wr_PCI : std_logic;
signal a_USBSTS_Wr_En_NAK : std_logic;
signal a_USBSTS_Wr_En_SLI : std_logic;
signal a_USBSTS_Wr_En_SRI : std_logic;
signal a_USBSTS_Wr_En_URI : std_logic;
signal a_USBSTS_Wr_En_PCI : std_logic;
signal a_USBSTS_Wr_UI : std_logic;
signal a_USBSTS_Wr_en_UI : std_logic;
signal a_USBINTR_Rd : std_logic_vector(31 downto 0);
signal a_FRINDEX_Rd : std_logic_vector(31 downto 0);
signal a_FRINDEX_Wr : std_logic_vector(10 downto 0);
signal a_FRINDEX_Wr_En : std_logic;
signal a_DEVICEADDR_rd, u_DEVICEADDR_rd : std_logic_vector(31 downto 0);
signal a_DEVICEADDR_IPush : std_logic;
signal a_DEVICEADDR_IRdy : std_logic;
signal u_DEVICEADDR_oValid : std_logic;
signal a_ENDPOINTLISTADDR_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTNAK_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTNAK_Wr : std_logic_vector(31 downto 0);
signal a_ENDPTNAK_Wr_En : std_logic;
signal a_ENDPTNAKEN_Rd : std_logic_vector(31 downto 0);
signal a_CONFIGFLAG_Rd : std_logic_vector(31 downto 0);
signal a_PORTSC1_Rd : std_logic_vector(31 downto 0);
signal a_PORTSC1_PSPD_Wr : std_logic_vector(1 downto 0);
signal a_PORTSC1_PSPD_Wr_En : std_logic;
signal a_OTGSC_Rd : std_logic_vector(31 downto 0);
signal a_USBMODE_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTSETUPSTAT_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTSETUPSTAT_Wr : std_logic_vector(31 downto 0);
signal a_ENDPTSETUPSTAT_Wr_En : std_logic;
signal a_PE_ENDPTSETUP_RECEIVED_Wr : std_logic_vector(31 downto 0);
signal a_PE_ENDPTSETUP_RECEIVED_Wr_En : std_logic;
signal a_Arb_ENDPTSETUP_RECEIVED_Rd : std_logic_vector(31 downto 0);
signal a_Arb_ENDPTSETUP_RECEIVED_Clear : std_logic_vector(31 downto 0);
signal a_Arb_ENDPTSETUP_RECEIVED_Clear_En : std_logic;
signal a_Arb_ENDPTSETUP_RECEIVED_Ack : std_logic;
signal a_ENDPTPRIME_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTPRIME_Clear : std_logic_vector(31 downto 0);
signal a_ENDPTPRIME_Clear_En : std_logic;
signal a_ENDPTPRIME_Set : std_logic_vector(31 downto 0);
signal a_ENDPTPRIME_Set_En : std_logic;
signal a_EMDPTFLUSH_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTFLUSH_Clear, a_EMDPTFLUSH_Set : std_logic_vector(31 downto 0);
signal a_ENDPTFLUSH_Clear_En, a_EMDPTFLUSH_Set_En : std_logic;
signal a_ENDPTSTAT_Wr : std_logic_vector(31 downto 0);
signal a_ENDPTCOMPLETE_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCOMPLETE_Wr : std_logic_vector(31 downto 0);
signal a_ENDPTCOMPLETE_Wr_En : std_logic;
signal a_ENDPTCTRL0_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL1_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL2_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL3_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL4_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL5_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL6_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL7_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL8_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL9_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL10_Rd : std_logic_vector(31 downto 0);
signal a_ENDPTCTRL11_Rd : std_logic_vector(31 downto 0);
signal a_USBCMD_RS, u_USBCMD_RS : std_logic;
signal a_In_Packet_Complete_Set : std_logic_vector(31 downto 0);
signal a_In_Packet_Complete_Set_En : std_logic;
signal a_In_Packet_Complete_Rd : std_logic_vector(31 downto 0);
signal a_In_Packet_Complete_Clear : STD_LOGIC_VECTOR(31 downto 0);
signal a_In_Packet_Complete_Clear_En : STD_LOGIC;
signal a_Send_Zero_Length_Packet_iData, u_Send_Zero_Length_Packet_oData, a_Send_Zero_Length_Packet_iData_q : STD_LOGIC_VECTOR(31 downto 0);
signal a_Send_Zero_Length_Packet_iPush, a_Send_Zero_Length_Packet_iRdy, u_Send_Zero_Length_Packet_oValid : std_logic;
signal a_Send_Zero_Length_Packet_Set : STD_LOGIC_VECTOR(31 downto 0);
signal a_Send_Zero_Length_Packet_Set_En : STD_LOGIC;
signal a_Send_Zero_Length_Packet_Clear : STD_LOGIC_VECTOR(31 downto 0);
signal a_Send_Zero_Length_Packet_Clear_En : STD_LOGIC;
signal a_Send_Zero_Length_Packet_Ack_Rd : STD_LOGIC_VECTOR(31 downto 0);
signal a_Send_Zero_Length_Packet_Ack_Clear : STD_LOGIC_VECTOR(31 downto 0);
signal a_Send_Zero_Length_Packet_Ack_Clear_En : STD_LOGIC;
signal a_Send_Zero_Length_Packet_Ack_Set : STD_LOGIC_VECTOR(31 downto 0);
signal a_Send_Zero_Length_Packet_Ack_Set_En : STD_LOGIC;
signal a_In_Token_Received_Set, a_In_Token_Received_Rd, a_In_Token_Received_Clear : STD_LOGIC_VECTOR(31 downto 0);
signal a_In_Token_Received_Set_En, a_In_Token_Received_Clear_En : STD_LOGIC;
signal a_Cnt_Bytes_Sent : std_logic_vector(12 downto 0);
signal a_Cnt_Bytes_Sent_oValid : STD_LOGIC;
signal a_Arb_Endpt_Nr : std_logic_vector(4 downto 0);
signal a_Endpt_Type_iData, u_Endpt_Type_oData, a_Endpt_Type_iData_q : std_logic_vector(47 downto 0);
signal a_Endpt_Type_iPush, a_Endpt_Type_iRdy, u_Endpt_Type_oValid : std_logic;
signal a_Endpt_Enable_iData, u_Endpt_Enable_oData, a_Endpt_Enable_iData_q : std_logic_vector(23 downto 0);
signal a_Endpt_Enable_iPush, a_Endpt_Enable_iRdy, u_Endpt_Enable_oValid : std_logic;
signal a_Endpt_Stall_iData, u_Endpt_Stall_oData, a_Endpt_Stall_iData_q : std_logic_vector(23 downto 0);
signal a_Endpt_Stall_iPush, a_Endpt_Stall_iRdy, u_Endpt_Stall_oValid : std_logic;
signal a_INTERRUPT_Loc : std_logic;
signal DEBUG_REG_DATA : std_logic_vector(31 downto 0);
signal a_USBSTS_UI_Change : std_logic;
signal a_Resend : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal a_Resend_Clear : STD_LOGIC_VECTOR(31 downto 0);
signal a_Resend_Clear_En : STD_LOGIC;
signal a_Resend_oData : STD_LOGIC_VECTOR(31 downto 0);
signal a_Resend_Wr_En : STD_LOGIC;
attribute clock_buffer_type : string;
attribute clock_buffer_type of ulpi_clk : signal is "none";
signal state_ind : STD_LOGIC_VECTOR(5 downto 0);
signal state_ind_pd : STD_LOGIC_VECTOR(6 downto 0);
signal state_ind_hs : STD_LOGIC_VECTOR(4 downto 0);
signal state_ind_dma : STD_LOGIC_VECTOR(4 downto 0);
signal state_ind_arb : std_logic_vector(5 downto 0);
signal ind_statte_axistream : std_logic_vector(4 downto 0);
-- attribute mark_debug : string;
-- attribute keep : string;
-- attribute mark_debug of u_USBCMD_RS : signal is "true";
-- attribute keep of u_USBCMD_RS : signal is "true";
begin
ulpi_resetn <= S_AXI_ARESETN;
a_Axi_Reset <= not S_AXI_ARESETN;
a_USBCMD_RS <= a_USBCMD_Rd(0);
led <= '0';
u_ResetN <= Ulpi_ResetN_oRst and (Ulpi_Clk_MMCM_Locked);
Inst_ResetBridge: ResetBridge
GENERIC MAP (
kPolarity => '0')
PORT MAP(
aRst => S_AXI_ARESETN,
OutClk => Ulpi_Clk_MMCM_Clkout0,
oRst => Ulpi_ResetN_oRst
);
u_MMCM_Rst <= '0';
-- This module implements the control registers required by USB Device IP.
-- Control Registers data is written/read over an AXI Lite interface
Inst_Control_Registers: Control_Registers PORT MAP(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWPROT => S_AXI_AWPROT,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARPROT => S_AXI_ARPROT,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
USBSCFG_rd => a_SBUSCFG_Rd,
USBCMD_rd => a_USBCMD_Rd,
USBCMD_SUTW_wr => a_USBCMD_SUTW_Wr,
USBCMD_SUTW_wr_en => a_USBCMD_SUTW_Wr_En,
USBCMD_ATDTW_wr => a_USBCMD_ATDTW_Wr,
USBCMD_ATDTW_wr_en => a_USBCMD_ATDTW_Wr_En,
USBSTS_rd => a_USBSTS_Rd,
USBSTS_wr_UI => a_USBSTS_Wr_UI,
USBSTS_wr_NAKI => a_USBSTS_Wr_NAKI,
USBSTS_wr_SLI => a_USBSTS_Wr_SLI,
USBSTS_wr_SRI => a_USBSTS_Wr_SRI,
USBSTS_wr_URI => a_USBSTS_Wr_URI,
USBSTS_wr_PCI => a_USBSTS_Wr_PCI,
USBSTS_wr_en_NAK => a_USBSTS_Wr_En_NAK,
USBSTS_wr_en_SLI => a_USBSTS_Wr_En_SLI,
USBSTS_wr_en_SRI => a_USBSTS_Wr_En_SRI,
USBSTS_wr_en_URI => a_USBSTS_Wr_En_URI,
USBSTS_wr_en_PCI => a_USBSTS_Wr_En_PCI,
USBSTS_wr_en_UI => a_USBSTS_Wr_en_UI,
USBINTR_rd => a_USBINTR_Rd,
FRINDEX_rd => a_FRINDEX_Rd,
FRINDEX_wr => a_FRINDEX_Wr,
FRINDEX_wr_en => a_FRINDEX_Wr_En,
a_DEVICEADDR_rd => a_DEVICEADDR_rd,
a_DEVICEADDR_IPush => a_DEVICEADDR_IPush,
ENDPOINTLISTADDR_rd => a_ENDPOINTLISTADDR_Rd,
ENDPTNAK_rd => a_ENDPTNAK_Rd,
ENDPTNAK_wr => a_ENDPTNAK_Wr,
ENDPTNAK_wr_en => a_ENDPTNAK_Wr_En,
ENDPTNAKEN_rd => a_ENDPTNAKEN_Rd,
CONFIGFLAG_rd => a_CONFIGFLAG_Rd,
PORTSC1_rd => a_PORTSC1_Rd,
PORTSC1_PSPD_wr => a_PORTSC1_PSPD_Wr,
PORTSC1_PSPD_wr_en => a_PORTSC1_PSPD_Wr_En,
OTGSC_rd => a_OTGSC_Rd,
USBMODE_rd => a_USBMODE_Rd,
ENDPTSETUPSTAT_rd => a_ENDPTSETUPSTAT_Rd,
ENDPTSETUPSTAT_wr => a_ENDPTSETUPSTAT_Wr,
ENDPTSETUPSTAT_wr_en => a_ENDPTSETUPSTAT_Wr_En,
ENDPTPRIME_rd => a_ENDPTPRIME_Rd,
ENDPTPRIME_clear => a_ENDPTPRIME_Clear,
ENDPTPRIME_clear_en => a_ENDPTPRIME_Clear_En,
ENDPTPRIME_set => a_ENDPTPRIME_Set,
ENDPTPRIME_set_en => a_ENDPTPRIME_Set_En,
EMDPTFLUSH_rd => a_EMDPTFLUSH_Rd,
EMDPTFLUSH_clear => a_ENDPTFLUSH_Clear,
EMDPTFLUSH_clear_en => a_ENDPTFLUSH_Clear_En,
EMDPTFLUSH_set => a_EMDPTFLUSH_Set,
EMDPTFLUSH_set_en => a_EMDPTFLUSH_Set_En,
ENDPTSTAT_wr => a_ENDPTSTAT_Wr,
ENDPTCOMPLETE_rd => a_ENDPTCOMPLETE_Rd,
ENDPTCOMPLETE_wr => a_ENDPTCOMPLETE_Wr,
ENDPTCOMPLETE_wr_en => a_ENDPTCOMPLETE_Wr_En,
ENDPTCTRL0_rd => a_ENDPTCTRL0_Rd,
ENDPTCTRL1_rd => a_ENDPTCTRL1_Rd,
ENDPTCTRL2_rd => a_ENDPTCTRL2_Rd,
ENDPTCTRL3_rd => a_ENDPTCTRL3_Rd,
ENDPTCTRL4_rd => a_ENDPTCTRL4_Rd,
ENDPTCTRL5_rd => a_ENDPTCTRL5_Rd,
ENDPTCTRL6_rd => a_ENDPTCTRL6_Rd,
ENDPTCTRL7_rd => a_ENDPTCTRL7_Rd,
ENDPTCTRL8_rd => a_ENDPTCTRL8_Rd,
ENDPTCTRL9_rd => a_ENDPTCTRL9_Rd,
ENDPTCTRL10_rd => a_ENDPTCTRL10_Rd,
ENDPTCTRL11_rd => a_ENDPTCTRL11_Rd
);
-- This module manages all transfers from main memory to local buffers through
-- DMA, both control data (Queue Heads, Transfer Descriptors)and packet data.
Inst_DMA_Transfer_Manager: DMA_Transfer_Manager PORT MAP(
Axi_Clk => S_AXI_ACLK,
Axi_Resetn => S_AXI_ARESETN,
ind_statte_axistream => ind_statte_axistream,
state_ind_dma => state_ind_dma,
state_ind_arb => state_ind_arb,
a_M_Axi_Awaddr => a_DMA_Axilite_Awaddr,
a_M_Axi_Awprot => a_DMA_Axilite_Awprot,
a_M_Axi_Awvalid => a_DMA_Axilite_Awvalid,
a_M_Axi_Awready => a_DMA_Axilite_Awready,
a_M_Axi_Wdata => a_DMA_Axilite_Wdata,
a_M_Axi_Wstrb => a_DMA_Axilite_Wstrb,
a_M_Axi_Wvalid => a_DMA_Axilite_Wvalid,
a_M_Axi_Wready => a_DMA_Axilite_Wready,
a_M_Axi_Bresp => a_DMA_Axilite_Bresp,
a_M_Axi_Bvalid => a_DMA_Axilite_Bvalid,
a_M_Axi_Bready => a_DMA_Axilite_Bready,
a_M_Axi_Araddr => a_DMA_Axilite_Araddr,
a_M_Axi_Arprot => a_DMA_Axilite_Arprot,
a_M_Axi_Arvalid => a_DMA_Axilite_Arvalid,
a_M_Axi_Arready => a_DMA_Axilite_Arready,
a_M_Axi_Rdata => a_DMA_Axilite_Rdata,
a_M_Axi_Rresp => a_DMA_Axilite_Rresp,
a_M_Axi_Rvalid => a_DMA_Axilite_Rvalid,
a_M_Axi_Rready => a_DMA_Axilite_Ready,
a_S_Axis_MM2S_Tdata => a_Arb_Axis_MM2S_Tdata,
a_S_Axis_MM2S_Tkeep => a_Arb_Axis_MM2S_Tkeep,
a_S_Axis_MM2S_Tvalid => a_Arb_Axis_MM2S_Tvalid,
a_S_Axis_MM2S_Tready => a_Arb_Axis_MM2S_Tready,
a_S_Axis_MM2S_Tlast => a_Arb_Axis_MM2S_Tlast,
a_M_Axis_S2MM_Tdata => a_Arb_Axis_S2MM_Tdata,
a_M_Axis_S2MM_Tkeep => a_Arb_Axis_S2MM_Tkeep,
a_M_Axis_S2MM_Tvalid => a_Arb_Axis_S2MM_Tvalid,
a_M_Axis_S2MM_Tready => a_Arb_Axis_S2MM_Tready,
a_M_Axis_S2MM_Tlast => a_Arb_Axis_S2MM_Tlast,
RX_COMMAND_FIFO_RD_EN => u_Command_Fifo_Rd_En,
RX_COMMAND_FIFO_DOUT => u_Command_Fifo_Dout,
RX_COMMAND_FIFO_EMPTY => u_Command_Fifo_Empty,
RX_COMMAND_FIFO_VALID => u_Command_Fifo_Valid,
a_Axis_MM2S_Mux_Ctrl => a_Axis_MM2S_Mux_Ctrl,
a_Axis_S2MM_Mux_Ctrl => a_Axis_S2MM_Mux_Ctrl,
a_Send_Zero_Length_Packet_Set => a_Send_Zero_Length_Packet_Set,
a_Send_Zero_Length_Packet_Set_En => a_Send_Zero_Length_Packet_Set_En,
a_Send_Zero_Length_Packet_Ack_Rd => a_Send_Zero_Length_Packet_Ack_Rd,
a_Send_Zero_Length_Packet_Ack_Clear => a_Send_Zero_Length_Packet_Ack_Clear,
a_Send_Zero_Length_Packet_Ack_Clear_En => a_Send_Zero_Length_Packet_Ack_Clear_En,
a_Arb_dQH_Setup_Buffer_Bytes_3_0_Wr => a_Setup_Buffer_Bytes_3_0_Wr,
a_Arb_dQH_Setup_Buffer_Bytes_7_4_Wr => a_Setup_Buffer_Bytes_7_4_Wr,
a_In_Packet_Complete_Rd => a_In_Packet_Complete_Rd,
a_In_Packet_Complete_Clear => a_In_Packet_Complete_Clear,
a_In_Packet_Complete_Clear_En => a_In_Packet_Complete_Clear_En,
a_In_Token_Received_Rd => a_In_Token_Received_Rd,
a_In_Token_Received_Clear => a_In_Token_Received_Clear,
a_In_Token_Received_Clear_En => a_In_Token_Received_Clear_En,
a_Cnt_Bytes_Sent => a_Cnt_Bytes_Sent,
a_Cnt_Bytes_Sent_oValid => a_Cnt_Bytes_Sent_oValid,
a_Pe_Endpt_Nr => a_Pe_Endpt_Nr,
a_Arb_Endpt_Nr => a_Arb_Endpt_Nr,
a_Resend => a_Resend,
a_Resend_Clear => a_Resend_Clear,
a_Resend_Clear_En => a_Resend_Clear_En,
arb_tx_fifo_s_aresetn => arb_tx_fifo_s_aresetn,
a_USBSTS_Wr_UI => a_USBSTS_Wr_UI,
a_USBSTS_Wr_en_UI => a_USBSTS_Wr_en_UI,
a_USBMODE_Rd => a_USBMODE_Rd,
a_USBCMD_SUTW_Wr => a_USBCMD_SUTW_Wr,
a_USBCMD_SUTW_Wr_En => a_USBCMD_SUTW_Wr_En,
a_USBCMD_ATDTW_Wr => a_USBCMD_ATDTW_Wr,
a_USBCMD_ATDTW_Wr_En => a_USBCMD_ATDTW_Wr_En,
a_EMDPTFLUSH_Rd => a_EMDPTFLUSH_Rd,
a_EMDPTFLUSH_Set => a_EMDPTFLUSH_Set,
a_EMDPTFLUSH_Set_En => a_EMDPTFLUSH_Set_En,
a_ENDPTPRIME_Rd => a_ENDPTPRIME_Rd,
a_ENDPTPRIME_Clear => a_ENDPTPRIME_Clear,
a_ENDPTPRIME_Clear_En => a_ENDPTPRIME_Clear_En,
a_ENDPTPRIME_Set => a_ENDPTPRIME_Set,
a_ENDPTPRIME_Set_En => a_ENDPTPRIME_Set_En,
a_ENDPTSTAT_Wr => a_ENDPTSTAT_Wr,
a_ENDPTCOMPLETE_Wr => a_ENDPTCOMPLETE_Wr,
a_ENDPTCOMPLETE_Wr_En => a_ENDPTCOMPLETE_Wr_En,
a_ENDPTSETUPSTAT_Wr => a_ENDPTSETUPSTAT_Wr,
a_ENDPTSETUPSTAT_Wr_En => a_ENDPTSETUPSTAT_Wr_En,
a_Arb_ENDPTSETUP_RECEIVED_Rd => a_Arb_ENDPTSETUP_RECEIVED_Rd,
a_Arb_ENDPTSETUP_RECEIVED_Clear => a_Arb_ENDPTSETUP_RECEIVED_Clear,
a_Arb_ENDPTSETUP_RECEIVED_Clear_En => a_Arb_ENDPTSETUP_RECEIVED_Clear_En,
a_Arb_ENDPTSETUP_RECEIVED_Ack => a_Arb_ENDPTSETUP_RECEIVED_Ack,
a_ENDPOINTLISTADDR_Rd => a_ENDPOINTLISTADDR_Rd
);
--AXI DMA Controller
your_instance_name: axi_dma_0 PORT MAP (
s_axi_lite_aclk => S_AXI_ACLK,
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => S_AXI_ARESETN,
s_axi_lite_awvalid => a_DMA_Axilite_Awvalid,
s_axi_lite_awready => a_DMA_Axilite_Awready,
s_axi_lite_awaddr => a_DMA_Axilite_Awaddr,
s_axi_lite_wvalid => a_DMA_Axilite_Wvalid,
s_axi_lite_wready => a_DMA_Axilite_Wready,
s_axi_lite_wdata => a_DMA_Axilite_Wdata,
s_axi_lite_bresp => a_DMA_Axilite_Bresp,
s_axi_lite_bvalid => a_DMA_Axilite_Bvalid,
s_axi_lite_bready => a_DMA_Axilite_Bready,
s_axi_lite_arvalid => a_DMA_Axilite_Arvalid,
s_axi_lite_arready => a_DMA_Axilite_Arready,
s_axi_lite_araddr => a_DMA_Axilite_Araddr,
s_axi_lite_rvalid => a_DMA_Axilite_Rvalid,
s_axi_lite_rready => a_DMA_Axilite_Ready,
s_axi_lite_rdata => a_DMA_Axilite_Rdata,
s_axi_lite_rresp => a_DMA_Axilite_Rresp,
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => a_MM2S_Prmry_Reset_Out_N,
m_axis_mm2s_tdata => a_DMA_M_Axis_MM2S_Tdata,
m_axis_mm2s_tkeep => a_DMA_M_Axis_MM2S_Tkeep,
m_axis_mm2s_tvalid => a_DMA_M_Axis_MM2S_Tvalid,
m_axis_mm2s_tready => a_DMA_M_Axis_MM2S_Tready,
m_axis_mm2s_tlast => a_DMA_M_Axis_MM2S_Tlast,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => a_S2MM_Prmry_Reset_Out_N,
s_axis_s2mm_tdata => a_DMA_S_Axis_S2MM_Tdata,
s_axis_s2mm_tkeep => a_DMA_S_Axis_S2MM_Tkeep,
s_axis_s2mm_tvalid => a_DMA_S_Axis_S2MM_Tvalid,
s_axis_s2mm_tready => a_DMA_S_Axis_S2MM_Tready,
s_axis_s2mm_tlast => a_DMA_S_Axis_S2MM_Tlast,
mm2s_introut => a_MM2S_Introut,
s2mm_introut => a_S2MM_Introut,
axi_dma_tstvec => a_Axi_DMA_Tstvec
);
--Receive Packet FIFO
Inst_FIFO: FIFO PORT MAP(
resetn => S_AXI_ARESETN,
rx_fifo_s_aresetn => S_AXI_ARESETN,
rx_fifo_m_aclk => m_axi_mm2s_aclk,
rx_fifo_s_aclk => u_Rx_Fifo_s_Aclk ,
rx_fifo_s_axis_tvalid => u_Rx_Fifo_s_Axis_Tvalid,
rx_fifo_s_axis_tready => u_Rx_Fifo_s_Axis_Tready,
rx_fifo_s_axis_tdata => u_Rx_Fifo_s_Axis_Tdata,
rx_fifo_s_axis_tkeep => u_Rx_Fifo_s_Axis_Tkeep,
rx_fifo_s_axis_tlast => u_Rx_Fifo_s_Axis_Tlast,
rx_fifo_s_axis_tuser => "0000",
rx_fifo_m_axis_tvalid => a_FIFO_Axis_S2MM_Tvalid,
rx_fifo_m_axis_tready => a_FIFO_Axis_S2MM_Tready,
rx_fifo_m_axis_tdata => a_FIFO_Axis_S2MM_Tdata,
rx_fifo_m_axis_tlast => a_FIFO_Axis_S2MM_Tlast,
rx_fifo_m_axis_tkeep => a_FIFO_Axis_S2MM_Tkeep,
rx_fifo_m_axis_tuser => open,
rx_fifo_axis_overflow => u_Rx_Fifo_Axis_Overflow,
rx_fifo_axis_underflow => u_Rx_Fifo_Axis_Underflow
);
-- This module instantiates all the necessary modules to implement ULPI
-- communication, Speed negotiation , Reset and Suspend. Packet data is
-- sent/received over AXI Stream. Synchronization modules for registers
-- that corss the ULPI Clock domain to AXI clock domain is implemented
-- here
Inst_Protocol_Engine: Protocol_Engine PORT MAP(
Axi_Clk => S_AXI_ACLK,
axi_resetn => S_AXI_ARESETN,
Ulpi_Clk => Ulpi_Clk_MMCM_Clkout0,
u_ResetN => u_ResetN,
ulpi_reset => open,
u_Ulpi_Data => ulpi_data,
u_Ulpi_Dir => ulpi_dir,
u_Ulpi_Nxt => ulpi_nxt,
u_Ulpi_Stp => ulpi_stp,
led => open,
a_Arb_Endpt_Nr => a_Arb_Endpt_Nr,
Tx_Fifo_S_Aresetn => arb_tx_fifo_s_aresetn,
a_Tx_Fifo_S_Aclk => m_axi_s2mm_aclk,
a_Tx_Fifo_S_Axis_Tvalid => a_FIFO_Axis_MM2S_Tvalid,
a_Tx_Fifo_S_Axis_Tready => a_FIFO_Axis_MM2S_Tready,
a_Tx_Fifo_S_Axis_Tdata => a_FIFO_Axis_MM2S_Tdata,
a_Tx_Fifo_S_Axis_Tlast => a_FIFO_Axis_MM2S_Tlast,
a_Tx_Fifo_S_Axis_Tkeep => a_FIFO_Axis_MM2S_Tkeep,
a_Tx_Fifo_S_Axis_Tuser => "0000",
tx_fifo_axis_overflow => open,
tx_fifo_axis_underflow => open,
u_Rx_Fifo_s_Aclk => u_Rx_Fifo_s_Aclk ,
u_Rx_Fifo_s_Axis_Tready => u_Rx_Fifo_s_Axis_Tready,
u_Rx_Fifo_s_Axis_Tvalid => u_Rx_Fifo_s_Axis_Tvalid,
u_Rx_Fifo_s_Axis_Tdata => u_Rx_Fifo_s_Axis_Tdata,
u_Rx_Fifo_s_Axis_Tkeep => u_Rx_Fifo_s_Axis_Tkeep,
u_Rx_Fifo_s_Axis_Tlast => u_Rx_Fifo_s_Axis_Tlast,
u_Rx_Fifo_Axis_Overflow => u_Rx_Fifo_Axis_Overflow,
u_Rx_Fifo_Axis_Underflow => u_Rx_Fifo_Axis_Underflow,
u_Command_Fifo_Rd_En => u_Command_Fifo_Rd_En,
u_Command_Fifo_Dout => u_Command_Fifo_Dout,
u_Command_Fifo_Empty => u_Command_Fifo_Empty,
u_Command_Fifo_Valid => u_Command_Fifo_Valid,
a_FRINDEX_oData => a_FRINDEX_Wr,
a_FRINDEX_Wr_En => a_FRINDEX_Wr_En,
a_Setup_Buffer_Bytes_3_0_oData => a_Setup_Buffer_Bytes_3_0_Wr,
a_Setup_Buffer_Bytes_7_4_oData => a_Setup_Buffer_Bytes_7_4_Wr,
a_PORTSC1_PSPD_oData => a_PORTSC1_PSPD_Wr,
a_PORTSC1_PSPD_Wr_En => a_PORTSC1_PSPD_Wr_En,
a_ENDPTNAK_oData => a_ENDPTNAK_Wr,
a_ENDPTNAK_Wr_En => a_ENDPTNAK_Wr_En,
a_ENDPTSETUP_RECEIVED_oData => a_PE_ENDPTSETUP_RECEIVED_Wr,
a_ENDPTSETUP_RECEIVED_Wr_En => a_PE_ENDPTSETUP_RECEIVED_Wr_En,
a_USBSTS_NAKI_oData => a_USBSTS_Wr_NAKI,
a_USBSTS_SLI_oData => a_USBSTS_Wr_SLI,
a_USBSTS_SRI_oData => a_USBSTS_Wr_SRI,
a_USBSTS_URI_oData => a_USBSTS_Wr_URI,
a_USBSTS_PCI_oData => a_USBSTS_Wr_PCI,
a_USBSTS_NAKI_Wr_En => a_USBSTS_Wr_En_NAK,
a_USBSTS_SLI_Wr_En => a_USBSTS_Wr_En_SLI,
a_USBSTS_SRI_Wr_En => a_USBSTS_Wr_En_SRI,
a_USBSTS_URI_Wr_En => a_USBSTS_Wr_En_URI,
a_USBSTS_PCI_Wr_En => a_USBSTS_Wr_En_PCI,
u_Send_Zero_Length_Packet_Rd => u_Send_Zero_Length_Packet_oData,
a_Send_Zero_Length_Packet_Clear_oData => a_Send_Zero_Length_Packet_Clear,
a_Send_Zero_Length_Packet_Clear_En => a_Send_Zero_Length_Packet_Clear_En,
a_Send_Zero_Length_Packet_Ack_oData => a_Send_Zero_Length_Packet_Ack_Set,
a_Send_Zero_Length_Packet_Ack_Set_En => a_Send_Zero_Length_Packet_Ack_Set_En,
a_In_Packet_Complete_oData => a_In_Packet_Complete_Set,
a_In_Packet_Complete_Set_En => a_In_Packet_Complete_Set_En,
a_Cnt_Bytes_Sent_oData => a_Cnt_Bytes_Sent,
a_Cnt_Bytes_Sent_oValid => a_Cnt_Bytes_Sent_oValid,
a_In_Token_Received_oData => a_In_Token_Received_Set,
a_In_Token_Received_Set_En => a_In_Token_Received_Set_En,
a_Resend_oData => a_Resend_oData,
a_Resend_Wr_En => a_Resend_Wr_En,
a_Endpt_Nr => a_Pe_Endpt_Nr,
u_Endp_Nr => pe_endpt_nr_ulpi_clk,
u_Endp_Nr_Arb => "00000",
u_Endp_Nr_Arb_Ack => open,
u_Endp_Nr_Arb_Valid => '0',
u_USBCMD_RS => u_USBCMD_RS,
u_Endp_Type => u_Endpt_Type_oData,
u_Endp_Stall => u_Endpt_Stall_oData,
u_USBADRA => u_DEVICEADDR_rd(31 downto 24),
-- endp_enable => pe_endpt_enable,
state_ind => state_ind,
state_ind_hs => state_ind_hs,
state_ind_pd => state_ind_pd
);
-- ULPI clock deskew
Ulpi_Clk_MMCM_Clkin <= ulpi_clk;
MMCME2_BASE_inst: MMCME2_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- Jitter programming (OPTIMIZED, HIGH, LOW)
CLKFBOUT_MULT_F => 10.0, -- Multiply value for all CLKOUT (2.000-64.000).
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB (-360.000-360.000).
CLKIN1_PERIOD => 0.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
-- CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT6_DIVIDE => 1,
CLKOUT0_DIVIDE_F => 10.0, -- Divide amount for CLKOUT0 (1.000-128.000).
-- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
CLKOUT6_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
CLKOUT6_PHASE => 0.0,
CLKOUT4_CASCADE => FALSE, -- Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
DIVCLK_DIVIDE => 1, -- Master division value (1-106)
REF_JITTER1 => 0.0, -- Reference input jitter in UI (0.000-0.999).
STARTUP_WAIT => FALSE -- Delays DONE until MMCM is locked (FALSE, TRUE)
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => Ulpi_Clk_MMCM_Clkout0, -- 1-bit output: CLKOUT0
CLKOUT0B => open, -- 1-bit output: Inverted CLKOUT0
CLKOUT1 => open, -- 1-bit output: CLKOUT1
CLKOUT1B => open, -- 1-bit output: Inverted CLKOUT1
CLKOUT2 => open, -- 1-bit output: CLKOUT2
CLKOUT2B => open, -- 1-bit output: Inverted CLKOUT2
CLKOUT3 => open, -- 1-bit output: CLKOUT3
CLKOUT3B => open, -- 1-bit output: Inverted CLKOUT3
CLKOUT4 => open, -- 1-bit output: CLKOUT4
CLKOUT5 => open, -- 1-bit output: CLKOUT5
CLKOUT6 => open, -- 1-bit output: CLKOUT6
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => Ulpi_Clk_MMCM_Clkfbout, -- 1-bit output: Feedback clock
CLKFBOUTB => open, -- 1-bit output: Inverted CLKFBOUT
-- Status Ports: 1-bit (each) output: MMCM status ports
LOCKED => Ulpi_Clk_MMCM_Locked, -- 1-bit output: LOCK
-- Clock Inputs: 1-bit (each) input: Clock input
CLKIN1 => Ulpi_Clk_MMCM_Clkin, -- 1-bit input: Clock
-- Control Ports: 1-bit (each) input: MMCM control ports
PWRDWN => '0', -- 1-bit input: Power-down
RST => u_MMCM_Rst, -- 1-bit input: Reset
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => Ulpi_Clk_MMCM_Clkfbin -- 1-bit input: Feedback clock
);
BUFG_inst : BUFG
port map (
O => Ulpi_Clk_MMCM_Clkfbin, -- 1-bit output: Clock output
I => Ulpi_Clk_MMCM_Clkfbout -- 1-bit input: Clock input
);
--DMA needs to write/read to/from both packet FIFOs and context memory; "MUX" implemented below
a_DMA_S_Axis_S2MM_Tdata <= a_Arb_Axis_S2MM_Tdata when (a_Axis_S2MM_Mux_Ctrl = '1') else
a_FIFO_Axis_S2MM_Tdata;
a_DMA_S_Axis_S2MM_Tkeep <= a_Arb_Axis_S2MM_Tkeep when (a_Axis_S2MM_Mux_Ctrl = '1') else
a_FIFO_Axis_S2MM_Tkeep;
a_DMA_S_Axis_S2MM_Tvalid <= a_Arb_Axis_S2MM_Tvalid when (a_Axis_S2MM_Mux_Ctrl = '1') else
a_FIFO_Axis_S2MM_Tvalid;
a_Arb_Axis_S2MM_Tready <= a_DMA_S_Axis_S2MM_Tready when (a_Axis_S2MM_Mux_Ctrl = '1') else
'0';
a_FIFO_Axis_S2MM_Tready <= a_DMA_S_Axis_S2MM_Tready when (a_Axis_S2MM_Mux_Ctrl = '0') else
'0';
a_DMA_S_Axis_S2MM_Tlast <= a_Arb_Axis_S2MM_Tlast when (a_Axis_S2MM_Mux_Ctrl = '1') else
a_FIFO_Axis_S2MM_Tlast;
a_Arb_Axis_MM2S_Tdata <= a_DMA_M_Axis_MM2S_Tdata when (a_Axis_MM2S_Mux_Ctrl = '1') else (others => '0');
a_FIFO_Axis_MM2S_Tdata <= a_DMA_M_Axis_MM2S_Tdata when (a_Axis_MM2S_Mux_Ctrl = '0') else (others => '0');
a_Arb_Axis_MM2S_Tkeep <= a_DMA_M_Axis_MM2S_Tkeep when (a_Axis_MM2S_Mux_Ctrl = '1') else (others => '0');
a_FIFO_Axis_MM2S_Tkeep <= a_DMA_M_Axis_MM2S_Tkeep when (a_Axis_MM2S_Mux_Ctrl = '0') else (others => '0');
a_Arb_Axis_MM2S_Tvalid <= a_DMA_M_Axis_MM2S_Tvalid when (a_Axis_MM2S_Mux_Ctrl = '1') else '0';
a_FIFO_Axis_MM2S_Tvalid <= a_DMA_M_Axis_MM2S_Tvalid when (a_Axis_MM2S_Mux_Ctrl = '0') else '0';
a_DMA_M_Axis_MM2S_Tready <= a_Arb_Axis_MM2S_Tready when (a_Axis_MM2S_Mux_Ctrl = '1') else
a_FIFO_Axis_MM2S_Tready;
a_Arb_Axis_MM2S_Tlast <= a_DMA_M_Axis_MM2S_Tlast when (a_Axis_MM2S_Mux_Ctrl = '1') else '0';
a_FIFO_Axis_MM2S_Tlast <= a_DMA_M_Axis_MM2S_Tlast when (a_Axis_MM2S_Mux_Ctrl = '0') else '0';
--------------------------------------------------------------------------------------------------
ENDPTCTRL(0) <= a_ENDPTCTRL0_Rd;
ENDPTCTRL(1) <= a_ENDPTCTRL1_Rd;
ENDPTCTRL(2) <= a_ENDPTCTRL2_Rd;
ENDPTCTRL(3) <= a_ENDPTCTRL3_Rd;
ENDPTCTRL(4) <= a_ENDPTCTRL4_Rd;
ENDPTCTRL(5) <= a_ENDPTCTRL5_Rd;
ENDPTCTRL(6) <= a_ENDPTCTRL6_Rd;
ENDPTCTRL(7) <= a_ENDPTCTRL7_Rd;
ENDPTCTRL(8) <= a_ENDPTCTRL8_Rd;
ENDPTCTRL(9) <= a_ENDPTCTRL9_Rd;
ENDPTCTRL(10) <= a_ENDPTCTRL10_Rd;
ENDPTCTRL(11) <= a_ENDPTCTRL11_Rd;
ENDP_TYPE_PROC: process (ENDPTCTRL)
begin
for endpt_type_index in 0 to 11 loop
a_Endpt_Type_iData((endpt_type_index*4+3) downto endpt_type_index*4) <= ENDPTCTRL(endpt_type_index)(19 downto 18) & ENDPTCTRL(endpt_type_index)(3 downto 2);
a_Endpt_Stall_iData((endpt_type_index*2+1) downto endpt_type_index*2) <= ENDPTCTRL(endpt_type_index)(16) & ENDPTCTRL(endpt_type_index)(0);
a_Endpt_Enable_iData((endpt_type_index*2+1) downto endpt_type_index*2) <= ENDPTCTRL(endpt_type_index)(23) & ENDPTCTRL(endpt_type_index)(7);
end loop;
end process;
TX_FIFO_RESET_PROC: process (ENDPTCTRL)
begin
for tx_fifo_reset_index in 0 to 11 loop
tx_fifo_reset_vector(tx_fifo_reset_index) <= (not(a_EMDPTFLUSH_Rd(tx_fifo_reset_index+16)) and arb_tx_fifo_s_aresetn);
end loop;
end process;
--Synchronization modules for data that crosses the AXI clock domain to ULPI clock domain
ENDPT_TYPE_IPUSH_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_Endpt_Type_iData_q <= (others => '0');
a_Endpt_Type_iPush <= '0';
else
a_Endpt_Type_iData_q <= a_Endpt_Type_iData;
if(a_Endpt_Type_iData_q /= a_Endpt_Type_iData and a_Endpt_Type_iRdy = '1') then
a_Endpt_Type_iPush <= '1';
else
a_Endpt_Type_iPush <= '0';
end if;
end if;
end if;
end process;
ENDPT_STALL_IPUSH_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_Endpt_Stall_iData_q <= (others => '0');
a_Endpt_Stall_iPush <= '0';
else
a_Endpt_Stall_iData_q <= a_Endpt_Stall_iData;
if(a_Endpt_Stall_iData_q /= a_Endpt_Stall_iData and a_Endpt_Stall_iRdy = '1') then
a_Endpt_Stall_iPush <= '1';
else
a_Endpt_Stall_iPush <= '0';
end if;
end if;
end if;
end process;
ENDPT_ENABLE_IPUSH_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_Endpt_Enable_iData_q <= (others => '0');
a_Endpt_Enable_iPush <= '0';
else
a_Endpt_Enable_iData_q <= a_Endpt_Enable_iData;
if(a_Endpt_Enable_iData_q /= a_Endpt_Enable_iData and a_Endpt_Enable_iRdy = '1') then
a_Endpt_Enable_iPush <= '1';
else
a_Endpt_Enable_iPush <= '0';
end if;
end if;
end if;
end process;
ZERO_LENGTH_PUSH_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_Send_Zero_Length_Packet_iData_q <= (others => '0');
a_Send_Zero_Length_Packet_iPush <= '0';
else
a_Send_Zero_Length_Packet_iData_q <= a_Send_Zero_Length_Packet_iData;
if(a_Send_Zero_Length_Packet_iData_q /= a_Send_Zero_Length_Packet_iData and a_Send_Zero_Length_Packet_iRdy = '1') then
a_Send_Zero_Length_Packet_iPush <= '1';
else
a_Send_Zero_Length_Packet_iPush <= '0';
end if;
end if;
end if;
end process;
SyncAsyncPushT_USBCMD_RS: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aReset => a_Axi_Reset,
aIn => a_USBCMD_RS,
OutClk => Ulpi_Clk_MMCM_Clkout0,
oOut => u_USBCMD_RS
);
Inst_HandshakeData_endpt_type: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 48)
PORT MAP(
InClk => S_AXI_ACLK,
OutClk => Ulpi_Clk_MMCM_Clkout0,
iData => a_Endpt_Type_iData,
oData => u_Endpt_Type_oData,
iPush => a_Endpt_Type_iPush,
iRdy => a_Endpt_Type_iRdy,
oAck => u_Endpt_Type_oValid,
oValid => u_Endpt_Type_oValid,
aReset => a_Axi_Reset
);
Inst_HandshakeData_endpt_stall: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 24)
PORT MAP(
InClk => S_AXI_ACLK,
OutClk => Ulpi_Clk_MMCM_Clkout0,
iData => a_Endpt_Stall_iData,
oData => u_Endpt_Stall_oData,
iPush => a_Endpt_Stall_iPush,
iRdy => a_Endpt_Stall_iRdy,
oAck => u_Endpt_Stall_oValid,
oValid => u_Endpt_Stall_oValid,
aReset => a_Axi_Reset
);
Inst_HandshakeData_endpt_enable: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 24)
PORT MAP(
InClk => S_AXI_ACLK,
OutClk => Ulpi_Clk_MMCM_Clkout0,
iData => a_Endpt_Enable_iData,
oData => u_Endpt_Enable_oData,
iPush => a_Endpt_Enable_iPush,
iRdy => a_Endpt_Enable_iRdy,
oAck => u_Endpt_Enable_oValid,
oValid => u_Endpt_Enable_oValid,
aReset => a_Axi_Reset
);
Inst_HandshakeData_send_zero_length_packet: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => S_AXI_ACLK,
OutClk => Ulpi_Clk_MMCM_Clkout0,
iData => a_Send_Zero_Length_Packet_iData,
oData => u_Send_Zero_Length_Packet_oData,
iPush => a_Send_Zero_Length_Packet_iPush,
iRdy => a_Send_Zero_Length_Packet_iRdy,
oAck => u_Send_Zero_Length_Packet_oValid,
oValid => u_Send_Zero_Length_Packet_oValid,
aReset => a_Axi_Reset
);
Inst_HandshakeData_DEVICEADDR: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => S_AXI_ACLK,
OutClk => Ulpi_Clk_MMCM_Clkout0,
iData => a_DEVICEADDR_rd,
oData => u_DEVICEADDR_rd,
iPush => a_DEVICEADDR_IPush,
iRdy => a_DEVICEADDR_IRdy,
oAck => u_DEVICEADDR_oValid,
oValid => u_DEVICEADDR_oValid,
aReset => a_Axi_Reset
);
--Interrupts
a_USBSTS_UI_Change <= a_ENDPTSETUPSTAT_Wr_En or a_ENDPTCOMPLETE_Wr_En;
INTERRUPT_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_INTERRUPT_Loc <= '0';
else
if ((a_USBINTR_Rd and a_USBSTS_Rd) /= "00000000000000000000000000000000") then
if (a_USBSTS_UI_Change = '1') then
a_INTERRUPT_Loc <= '0';
else
a_INTERRUPT_Loc <= '1';
end if;
else
a_INTERRUPT_Loc <= '0';
end if;
end if;
end if;
end process;
INTERRUPT <= a_INTERRUPT_Loc;
--Status Registers, Hanshake between Protocol_Engine and DMA_Transfer_Manager
ENDPT_FLUSH_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_ENDPTFLUSH_Clear <= (others => '0');
a_ENDPTFLUSH_Clear_En <= '0';
else
if(a_EMDPTFLUSH_Rd /= "00000000000000000000000000000000") then
a_ENDPTFLUSH_Clear_En <= '1';
a_ENDPTFLUSH_Clear <= (others => '0');
else
a_ENDPTFLUSH_Clear_En <= '0';
end if;
end if;
end if;
end process;
ENDPTSETUP_RECEIVED_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_Arb_ENDPTSETUP_RECEIVED_Rd <= (others => '0');
a_Arb_ENDPTSETUP_RECEIVED_Ack <= '0';
else
if (a_PE_ENDPTSETUP_RECEIVED_Wr_En = '1') then
a_Arb_ENDPTSETUP_RECEIVED_Rd <= a_PE_ENDPTSETUP_RECEIVED_Wr;
a_Arb_ENDPTSETUP_RECEIVED_Ack <= '0';
elsif(a_Arb_ENDPTSETUP_RECEIVED_Clear_En = '1') then
a_Arb_ENDPTSETUP_RECEIVED_Rd <= a_Arb_ENDPTSETUP_RECEIVED_Rd and a_Arb_ENDPTSETUP_RECEIVED_Clear;
a_Arb_ENDPTSETUP_RECEIVED_Ack <= '1';
else
a_Arb_ENDPTSETUP_RECEIVED_Ack <= '0';
end if;
end if;
end if;
end process;
PACKET_IN_COMPLETE_RD_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_In_Packet_Complete_Rd <= (others => '0');
else
if (a_In_Packet_Complete_Set_En = '1') then
a_In_Packet_Complete_Rd <= a_In_Packet_Complete_Rd or a_In_Packet_Complete_Set;
elsif(a_In_Packet_Complete_Clear_En = '1') then
a_In_Packet_Complete_Rd <= a_In_Packet_Complete_Rd and a_In_Packet_Complete_Clear;
end if;
end if;
end if;
end process;
SEND_ZERO_LENGTH_RD_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_Send_Zero_Length_Packet_iData <= (others => '0');
else
if (a_Send_Zero_Length_Packet_Set_En = '1') then
a_Send_Zero_Length_Packet_iData <= a_Send_Zero_Length_Packet_iData or a_Send_Zero_Length_Packet_Set;
elsif(a_Send_Zero_Length_Packet_Clear_En = '1') then
a_Send_Zero_Length_Packet_iData <= a_Send_Zero_Length_Packet_iData and a_Send_Zero_Length_Packet_Clear;
end if;
end if;
end if;
end process;
SEND_ZERO_LENGTH_ACK_RD_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_Send_Zero_Length_Packet_Ack_Rd <= (others => '0');
else
if (a_Send_Zero_Length_Packet_Ack_Set_En = '1') then
a_Send_Zero_Length_Packet_Ack_Rd <= a_Send_Zero_Length_Packet_Ack_Rd or a_Send_Zero_Length_Packet_Ack_Set;
elsif(a_Send_Zero_Length_Packet_Ack_Clear_En = '1') then
a_Send_Zero_Length_Packet_Ack_Rd <= a_Send_Zero_Length_Packet_Ack_Rd and a_Send_Zero_Length_Packet_Ack_Clear;
end if;
end if;
end if;
end process;
RESEND_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_Resend <= (others => '0');
else
if (a_Resend_Wr_En = '1') then
a_Resend <= a_Resend or a_Resend_oData;
elsif(a_Resend_Clear_En = '1') then
a_Resend <= a_Resend and a_Resend_Clear;
end if;
end if;
end if;
end process;
PE_IN_TOKEN_RECEIVED_PROC: process (S_AXI_ACLK)
begin
if (S_AXI_ACLK' event and S_AXI_ACLK = '1') then
if (S_AXI_ARESETN = '0') then
a_In_Token_Received_Rd <= (others => '0');
else
if (a_In_Token_Received_Set_En = '1') then
a_In_Token_Received_Rd <= a_In_Token_Received_Rd or a_In_Token_Received_Set;
elsif(a_In_Token_Received_Clear_En = '1') then
a_In_Token_Received_Rd <= a_In_Token_Received_Rd and a_In_Token_Received_Clear;
end if;
end if;
end if;
end process;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_t_e
--
-- Generated
-- by: wig
-- on: Tue Mar 30 18:39:52 2004
-- cmd: H:\work\mix_new\MIX\mix_0.pl -strip -nodelta ../../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-conf-c.vhd,v 1.1 2004/04/06 11:19:57 wig Exp $
-- $Date: 2004/04/06 11:19:57 $
-- $Log: inst_t_e-rtl-conf-c.vhd,v $
-- Revision 1.1 2004/04/06 11:19:57 wig
-- Adding result/autoopen
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.39 2004/03/30 11:05:58 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.28 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_t_e_rtl_conf / inst_t_e
--
configuration inst_t_e_rtl_conf of inst_t_e is
for rtl
-- Generated Configuration
for inst_a : inst_a_e
use configuration work.inst_a_e_rtl_conf;
end for;
-- __I_NO_CONFIG_VERILOG --for inst_e : inst_e_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_e_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end inst_t_e_rtl_conf;
--
-- End of Generated Configuration inst_t_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PGhjRVxpO1h8dnZCIbe1IUJq0Nv+WyLpeUbi8ffEVp0wMGEDTip7moZ6C/UDlMnkSvw2dhhfL+uj
CVDYn8YwIg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
FrkB8aU9gSNE85A40/TRenh4XALobCk0pFYa4vDGE3VhjeXEs2fAgEk6FEj3tmPUK337uoD6C5Iw
wfEretMQVsZ4i7woq3r6xmpe/He4R6yUxICsQeTtiSEcwHY7qUmMNRuU3/sj2T0Ur6A6g1RTA25P
ja9j+buNrE1JnNWIFDw=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Lm9LAzaC6cCmaWJsnWGYEMphZSuLOljrJ7QvNpDMz5e4mAMatD2o4MyvKAU4BeahW9nGkL88k69F
LMtAV95oTwET5Qzj/5/xWjSJ6z8ejYeRLwQI8NBiYt92rKPximPYWMy3a8k8q/mEVKgj8NFlC6rR
70qnVQmUOUE+1apwLIHeW+hTaw0ue1s9vBJ4SgeZUEL1cHrfcwGS0EHQ/Z6R+2W+/TFj3HKlPqxR
7hP3S8ME1uK2n8ViJj9bRL+pI/6Fg/VDbX7c1J5Bpjptvh9fGZ+UvB546gPJO4jZK7exQknsv5TD
VdE1ut7IvqBs7cgnBhXZy8L4jPxpMmHZPrLX+w==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
SUAJoM//nKzLs02jwOK93htq9CaAIq2RgJLj6CYZBAOFAoORXGmO2h1ROQuFfk5zCWlhZJzXSqeF
LonLYtVBK7MIK08dUa10JwVbt0uq9MEBRX92ywk63bZosqzNkhyon/jWDYf97EZhMwQUOMn3e1ev
cG5fp9XafOKlKivrngU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cgCuw8o+AJynkb4Bi4S/YmSEWkCQAjEYQJ7eeQiQL0YrML7SYM6qczOTwYsYQYFbioZlXpNlBTRK
fkWgQ7AnV+10Eb91pW+CvOO7UFttLdO6uw3Vs5j1eJeN7ldwHHsS3w2CQYXHjneHf11lMQNXgvUg
pX0DMC8P6JPWzl1pFNX9jotmPeufVC6aEofxnPoI8XXFGpgKExHXqC68NQQLnWc98rbrhoMCORgG
xuoOBSPUisjJwsOY9Ae+BphkTo4YpNMYLYeW/bU2doe874Hl34E5elvHqmav1nhE9LV9GQvL9zw0
Dr01/AH749VEydEbpK1HU7oHvtM1Siiezi4E9w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5856)
`protect data_block
Gbv6eVrj8mncVusmlvyExc63VkGYzXvVzaUoJrNUudbYyhodB2nbz3thDzDnrVvZSETnfKEdLas3
MtjU6hvHUhdm13RTBVhLscBDxsUN8kaw0QzULCzkspi1HiZ4et1EXbgaUowBLhb403Wk2J+m0sc7
Ok0fA0fUtK8MmSTuMeAgIjsruzFSeqOFyLmqRHdGVljLIS3aOq//uKOhQAhvkUfWVDqqbYhYMxkG
71U/q4thi3pjPlU6n2EGti23wrrERANdVUWTmuWgE6gekB/lY+7covzZ/HYp2nG6rXrdKNVDrb0s
u09sPHBdgxipXmO8+7yaCU15Z5AJ3eCRmozw6af73hjp/1Os8YcJglpMDqVnDAy01ofdjnbe7bN7
5WzCfz/iQ7ZXGSweByC7aW38wHhdRKSFrxr6n5fvQukI2W/w3DfYbDIJF9g0ekqQxaqqrZqS7Zyn
qgDycDeSApuDfm3mxFdxK8kBNFjEpxXQ+tzcJHGAISLFjhI/WbOKHTCV0YNRGMpeffSfLXIyy4Zb
t7IN8wMxJ9DRK1LyTiKVBKM34fHF15XVRUOekEC4z0wtY4bfUfe1KeB09hipM/dqg5WJ9Fp5O/24
fA+XYP/h8RhSWErC3BEffXuS9+cZNFYpnT8Fp1wkDiiQ5xWevvjoi/RVLJeL8YGlhdA/uG3vA2Nk
Oi32VmWP8VtOKzdlyqN+KnIWPOlOMDvMjPmgNjowsj6yswvnC7iez0CkWRkf68wgNxZdDziGzvBY
EjwAiYllvFE48Yp0C0yun7ewEVTZH3MGIGO+vi62HvhbfUNGf9TVEDgOFne+GcGSToABeasdiO5c
8nhNAmNEYslH+3KzbkKQvIrlsMIoJwVJCK7IeSTtp80P+l7sHaVlMLgFaPoDdY2rUX0NrFGOvKl7
4uvramdJV2d2wpTs+JX/q9fNbHYwQUmz5fAOiyEc/cOepGv6oG5eKdcSw1+zigoBzgspkx0FUm2u
uIapoYMRJZ7y5iYlAxtP684v0kDFm8uVOV54q9gYYPCZX5osB7SVT6a0ytUE2IoiU5AiMmO0EwsR
/vpnCL3u6eevqbCFhEdqxPVXhV30PwLBvbV0UTiVS19Pd6LlULfbjSf/IglUMUSQ2bUN7rzSZuZG
AkkcsLXnskQR9pMlR+oLMXhVPO+lp5vnzuG6itVUqLNYJtXkoOzFg9jSHotStDfu5VvSbe32zwph
aSprV5sog2ycubiFGeCwQ9iKD1nLXqHCZeTEk4PT72JfaT8DcIA5k9LBPlGm8eRwMSz5No94tOvy
c3Q8BexgER1oFgeTsReykqCMQy678zfNbD6VJGflR95LN6nZwShzbbGh7dNWQKcpLpZm7SOv0R19
wawgxM1Ztuyi0AGTwMC6PuVBpvSWnqEyqF5K9bb/+ECffnFP4L0c1HsHV1v7uRS+ngFZkfmgloC4
BisgXILeTQroQZnYNiQepO8jdgUdsVglt/2WAWUnQtDCcrFbwHJGinrQ7hcwlPRvKXElLUOf3u+q
++MGPpI3mkRcNIEAh0L0daxX4RvxH2inWRQ8TdnlRpXS4ksk2x2NACrVcVkrow4FfCrw6b1MksER
qzM0FLtad4ud36n27ZPcJZKIGXzG3MgAgIFiY5P5tHhVgWvmzFaYTOFZD/Bwx0fzimNTQCuJn4as
TynQ2M6Aft6Be92AaRYM61Rm3P9QHKAZlwKJGtNjnlXW5eWePaNc71Yv4bh1GWz8dtqEsX0kRWgV
Bx9eqlPx/qRykHR4a3ft7/5BbQuybyFAIwAgLjr/9pjDsaj0Pll9VxAiKX+f9J9OPVpR5MS9Txhb
jmXavSpSgeJHoCUIokmWW6rcKSOmiQsp3lp4QdIssAPKH778UTFqRRHjeC8N5k6izyo2s/IzIQ1u
aRGiQbly5lFR9w2MhYS26mpEmTCnTMUjD5GH5ZaYjdkh8PB2M94NUEG8OkusRjO5OuEv8DwQO2iZ
TTHWZXPzbNs6g2hVQeiinW2DV4NYpeBjf1krjfrkIqWJ1W8N/cCksHZuaspIvaPGYGrNhI9PRJaw
sXEZArTIhQF/CCF7XiPYhmwGuExFfRRs/xBqxWAkCrcZ+F4YcmHIcwRLDnKJCoIc/7qhajBlWK0k
DGaJRWt/q2Q2N8ec2j3fB/yOrHJvY9zWN7rp2eMV5bjJ5JoJoLQ2C19dZ+E9q9s1hy5I4wx33m/Q
Kt0Ad72hsOzTL5X2SJeJuq7Cxm9DG/ajOKvhbMGLHPfH8GtZRRprHvnP8DK8dRwM5i3OlTN92Ug8
WurzWY/cZjY+0JL7N55FIDB/q5c2jXa2IZ5EEJOwYy3TgDOcehQrAv3PyzjCLO3dLyAs1JXtoPbn
MukGR6O2FacD7lG0fh979yTZ2RqSFePrUDCbV5R733mNrBPUPPtKZVrjjUxR+NtXFCioNnNv3I6u
f5evSaJnI60TQ4xS/Xi8lnu1i4u+FC80tCDsbn1mXMSM0iEwcdWRWcczh84+7WVaQZjzi4pjLNF/
VU7/hmhrPUsk3rhQq2FT8/IAsyPvcBbVkBpmLSxyZJ0R7+WwkHheq+WnKQIhyZ5vLuqs/3qOFYaQ
amLLwQxMiJVZc69IVc9tv9E0Woy8pBSeRs2jmwBZgiI0htu81kjjEuXmvyC2bkgey221R/6cnAP8
k9Tem/pOrgTyCUZ1kKZTuYKdmy2X1W9yS3BtG6op4do51j9LHtJq+h3yLo8gLKl8zOBA8NHxDNQg
q0Qb9TQtv8nAcA1H1OavcQiyRq4wccnD6FifWl2BYgLKJJbUNh3MCjSETQVtc+UZ6A0O/EZH3TQI
0AjT1MlS/weY0UOw+U4OFOTs2EzFkmmGkhCsmc6kX9oimBhnWBtnjb+HSE9FeqCrrFV5RxJBdQeo
PfPTRz8frP+eTt4K/IT4AsiuhTrUk+9fBfKs1GZ3qp/fYLKU291Q+jWCzdxwm9wJ9nxCDCZ4tKKd
JMiJp7JkVZkaFBo0g2CwUb7OmzvXG9SQKfaVHwGbkycdSlz/ZlgS9wSVnoBcK7AM3BH1HiGT2sNX
HgnEdfyQsZKgk/a8BP1HHFWKbiqnJnQKl6hPjry2/MNVbjN1S+2iM98KutChJdyTuKJl5gUYsKdd
SOltMwhJmtisjRW7bjcguSw6EO0ZBhqzqakr5/bSZcVq7kWa2vDpmhzN3O/M4JDwlOXgdfrS5Lgc
WttzofCoolt+l3fBr2Foed4ARxIYa8l5aVvppFavMTIvWfAJXA/Z1E0RC++4/nYRfeSWJyGtpWlE
j0J4IDSwObeY331JhnnAMuV0LbkpDOjxOCaslrlqViLrRKbfk34YRktYlO7fD0Sw2zCR6ZzLg06w
5oknzpZO8VaE9F0RM6EOMIeyZ2wlngTBiB8tK0POxf8iafZ0uyFkpSYdPplt3K2dYEmL+rgQ5hST
kSOK0WprauXIEmWANAvXmfuy80WXhb3qUK4MlYf9LDYAB1bldp/ivdLDnzODErsTDZkIz2viayuB
QrTGwgF5MIwm+vORNui9kwvcGkfAGwBjhfzG9gFFSweuLjwkNZ4sljoqoQqNJ2+wUBmPqHWoKA8e
ShtmtSVf9rCT7Q9Hw494arFK+fYiOcLPn+SFTxJwOLoYq3KO+eM9efxmm6IGCuZ8x2UArVc0chj1
UX6d0vlnKuloI1Iyv3QG/XyfA+iOlodPgZHELUXkDpYRxqeA+R0asGk2UNNCbqwiDzcMsi6+GeV0
Pra5fCjToiCWzP0KsUS1inzfHoHPv0WWwoOgtUHf1P8KdWWDA1BSe1Y4VV5+0dmBXFS98QB48Qfu
Zv53L5h8kks4RdkjQjfSh/P6rnxGFfHD4EJwTfvS+3TfYhc418cekzV0wZIQtt8ieNk5N2gqMZQW
6FV83qpiGJs9Frhtd4yYWiv6EQIXbsJB82ry0kncqqihtXTkwYvY6e7M+Wgngz6dk+QC8YrlO0pk
7SBzN8PImhNRuF/NmR1AY44TcsKSNb16hbLZzJeh4xLstFoqT4BSuczEvTsME39Hjdd4HK6T28+i
XpahsSgfj0NHeHmSapA3Gl5mneDzn9c0cW1fz3Ivm6cCq/q/WNo5O/ku3Ux2IT2L0t2MTIhYTDit
Wbfng1cBsDMkSxhwTvOPHFVkZS8EMTSXzKmMIVQEapX0tv11UgNn3ZuiP+dqWALvYVpR27oe9lew
2DAAyzY1zD9pW/a+AoWklXrJWQ5MBOYMk1Vx4XTSN/wYWBu1Ha0vCkUgZ64CpSyfnWN0ZDvhaeOe
yOoUmPRWHpd75aCeLm8Fzu91fUKIEVTvDplgSw0UhVgR1vZSuRxeGSLjNj0gOf8ebqE9PmDaB5cd
uOoT9jCCdc64Tt8XPFXIjv63JrzDpnbOkveEFhSqNjXEJFUXIbKZvGFEQhxSqe/CHWLsstjdDbgS
gUNmC19AiNgQITXtMK5cKjquLzQw182jIl+COVdU16xfzhPG7k5sa2M7mSkyHhaZjyxcz3mj/NtY
S5t3WxYZ9tyWYaKGX3yllbo7FdWPJWmD6i2NlkAAjk9hAqkVt9WchGKegCbFLcJ5QQYsqSAfslkw
eKyKgrQKHWG6Rj1pH0bYE411oHP/0MTqp6lne/nd9ZONk5KcW+oQ7HVGk0iCK/SKfgDjF5Uoj2n1
dL1V08pMLpYfpF+guRhxnf1yS1DJPErkJOeySKZBtEblTiSnnltuf1j2sJiHBb+zNdpv4XH1qhIT
VmGRANlKQli6Y+OBLTNuxVykgxeZ4jp6Q42JEZodDN137kxv7TpYcaKCOUbal8QMDiyMhcNu8l/U
oSInNa8bgK0P+E3JYe/LBfdy6B3iLX4d689wS0F9a0cYhRzDNK7fr9Bb1e7iMgyDKD4bWMJ6bL8X
Pq13rx823LJ0p/LNouN3BgtcNAXBwfPsk65Mdclika8VXKNCzCznPuC9pHo/vaupac9ZWWWry6Zy
P/vQ1JDY7hTPB66OixVfi9xQtVR6yz4gIlygNmIZHRRghXyeOcbGwrDlWhbbtJZ28mlJ4sd+OhTP
WFPwqpsPGz82E54GNR/gC0JEOepz0W2f4iArnQy4ISTPhd2laRdTA5O/CZ6xiJfyN366Ze4a5XBx
uzhhI0LDN8BAXz/dV0s/E3brRNbowg+UHp4ucJhkX7k+xWsqoKbgDb98j/QRCEbta/U+X62FROV+
euZOYElp+WBC+JofFpVh/zUtSv7HrrQcn9tK+wDIa12zrH60ESomyWYwBlrbanGY52r82JIMv69A
Pq1Q8jqBHUUUOMV3/tLhFGap6U/wjLUqKTw0vFFYsrbLfQ6EJK/d7QURBLsW8+JZbLUWit/8bmvp
QvoC/480keigGlDYoziJxCaiKSl9wXX1q5j08SFKV7Iy/+m64taGom77vjFCxtWiuoNdtZz0pgxm
X06aY8PfLomDbRA/S8ll/3XPnWsrqu9OxEtD/lx7jz38XIfN9nT74lUzkUiL+VUQ1SyV47EA6NPT
FDK3QikakInA+96MPwNNEBzdkwcJgCV5l33pKhwFcK23h96OoYqWU3f0VD//O9vEZPX1bTh0A7yr
/jfu/P/WfV7XlpQfyq9/haeFX4M0BVsEmXpYNIrF6d5+I5jqs6ETwNDmV9lDj/9YMUmJHp5SN1FY
4+AFPc2x32UemGYfIcrDlIMw9LCzQL9HVeLHFk2NXjr5dLBt3SkZCiHdpcmgbCOUdKg9v9kWbw/O
yBTDTLQXG9oZFqS1Gd1nYPVrPdcwhCxL0e6/xjDIjMq/xPZm2IMB4Qa1i3Apt+c6xR3dlrtSkBiK
Hoi5T04p/aHZaL/jB0v675hRBGuHcpQhBabnQtmlA0DepQVv1HGmSTqzfffvl73V7V77Xzm1Nehn
q9bWl8x/n4p6ytvFwEC4M5/jfExW5PeJK1EsVABDds4s6ULIyGWDfSkMP4AC0ImTGnKG2jf7iSp7
obq67kRSrnY85IT8SgZ+YNkKPKx4s5+bOFbRObnT8M3MUNBACx3v1o/o3oInqjznh1XQZ76HiI/N
VK/v1D7R8LuYZTQ/WbaI0nQMGCs3ovjyZXKKPsivDhTH+gRJ89JfEUH88LbDOFInJQrYJA/OaukG
KX+7fIj89KAieA05orEvz7zDqPuLwuIkSYzmuFascLGqvjUzBBiZ1PPmci24iMylsPmBe2QtLG4D
zu7H+sfUXaDUBA7YsXmsu80oAaErBoxqNrvnu2POhO5hZTybn2B/08s1R3oLxOWkC5TMgOGckVlE
5MVH3Al9M6e7LGRjy5vavnjNxnpMe2zkVPPdSxVX87zENZ1mn9Fqw0X+6lKVN3y74DO0EId7jWiE
fRrC8jMTyhEW0UrlKOufRnN2vfa5WB/hJm7BQsqKBawxjODijSSLtF3hrbcWjFcxSWyAbrwYH9WP
CnsJLp4HnpN2mVvexKNvQeHztVUUdffcf8Pjtc1Ge6G+ZtBC6Ks9bCrIuct8aHsU9EHg9vKCPckp
t6wTnrLQpn1b5SSvMq+asSOp46bz9I5pEtekq63WbDMyf9H90d7tr3gqr4l7Q78+qsAiBdOfKZe7
SBbsn03iT4TYxbjj+ZXH+CtvU0a2UnqRslQbZEHaNNgMz4iJybVT5zauhkxZFS2T8beEPuPRK+DD
G9i2H+F6zQwHWM5PpydsHfhW+InDL3IrmqFuaNLYSjbgmKsjaYsO5nPBeogtoxzDXVD6y0TkdB90
Zyk+83qhWn77fmdgK0MvGX9JsShn+DGk6K3Y/efQKbmZGeLZZO1lj2NPqRKCWqNFQO9CJxvSrR0w
5rfZtmguC6i54cSGh/3JjCzL0bi5fvHpK5eb64yNAUiOov7rTqUmheSj5R4v/rqqowBUFOMI/uv8
7g34cI/QCiIueEIsfoihfTTT1988xGvk/dfUVZSpjdhgK+RVfxPuaYzD8it1yyrjfrWbVrde5eP6
U0McX1pUtohBpZLPKh+hkZET2x4/3tr4rjHk3M+PlvEiqTDSEvGqmHL3m+pC/kdWmzirNxu/Z+Wx
O+kSMajwTpAtXn9/tuGlJnLhYhG5jpRAK6ieNZ+EWHS0mYlDsd2JhQ8J/vgyZ3V21G192c+lpFaJ
pGUwIaQGu31qYTjXxrD8xn5fOsZtbWRADYC2v1R6qyU9RJRNbiQ4YrKTLCGm/gs1gFacTBu8SHRn
K8XNSD367nLxaxAA1MCxSfNl+rfow5TBA0/06hMNFb2FfEMDfIyqDGqVG5QlEndFb3Tdco8wFEGs
z56HjAbAPPCt6yCnsqvoRj100/6VcP1lIJSJEwfvK6iNLFcpWieVndwSrdKoMZmtD9+EOReE5pAu
Ht1h2Ss/3g+bEx5nh05sl2OJm1DawAy8DvuE1g8Aw8G6k2Ic86dOpaqjkDpCso2cKPYUOoR46hI1
LAcnqMG6xta/5ZqwMvgGDNXaPIsFtTlJ+An0cDthb8XDN1JaCQ4qvznM9uOTDnXLolTP82jleFRV
ONHpDpdIUWNetnYovd8xCJ8LY9rc0vslWTKSVZYKCbJGv9SkrajWAEIqMGbN3utLmMcZIX8i967C
TE6StUaHC2YCyVslcMiJsiWS/l9BYP4TNqTTxZgdBTVglgd57rXzOE/2cDDjFBColnwueBGVRKDU
ZThzAliSIe2CgKUzlrvSv/+1iWJVEgp2qN60LG/TjmLZYIWpKE9ApGgX+NzZ77qBBbedDh1dUswj
YFUA7b3b7L0odiqtmSCfZjQ23iE/tTUX1qkGASJzwbfxPXxJOj1pmBukvggapV5At+KmN440/AsJ
bGJA5OoqMsf85rBSJK6PkL2+uVUoZKpxRIQq89uHjNtZhaOByO8dp3LG
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PGhjRVxpO1h8dnZCIbe1IUJq0Nv+WyLpeUbi8ffEVp0wMGEDTip7moZ6C/UDlMnkSvw2dhhfL+uj
CVDYn8YwIg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
FrkB8aU9gSNE85A40/TRenh4XALobCk0pFYa4vDGE3VhjeXEs2fAgEk6FEj3tmPUK337uoD6C5Iw
wfEretMQVsZ4i7woq3r6xmpe/He4R6yUxICsQeTtiSEcwHY7qUmMNRuU3/sj2T0Ur6A6g1RTA25P
ja9j+buNrE1JnNWIFDw=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Lm9LAzaC6cCmaWJsnWGYEMphZSuLOljrJ7QvNpDMz5e4mAMatD2o4MyvKAU4BeahW9nGkL88k69F
LMtAV95oTwET5Qzj/5/xWjSJ6z8ejYeRLwQI8NBiYt92rKPximPYWMy3a8k8q/mEVKgj8NFlC6rR
70qnVQmUOUE+1apwLIHeW+hTaw0ue1s9vBJ4SgeZUEL1cHrfcwGS0EHQ/Z6R+2W+/TFj3HKlPqxR
7hP3S8ME1uK2n8ViJj9bRL+pI/6Fg/VDbX7c1J5Bpjptvh9fGZ+UvB546gPJO4jZK7exQknsv5TD
VdE1ut7IvqBs7cgnBhXZy8L4jPxpMmHZPrLX+w==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
SUAJoM//nKzLs02jwOK93htq9CaAIq2RgJLj6CYZBAOFAoORXGmO2h1ROQuFfk5zCWlhZJzXSqeF
LonLYtVBK7MIK08dUa10JwVbt0uq9MEBRX92ywk63bZosqzNkhyon/jWDYf97EZhMwQUOMn3e1ev
cG5fp9XafOKlKivrngU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cgCuw8o+AJynkb4Bi4S/YmSEWkCQAjEYQJ7eeQiQL0YrML7SYM6qczOTwYsYQYFbioZlXpNlBTRK
fkWgQ7AnV+10Eb91pW+CvOO7UFttLdO6uw3Vs5j1eJeN7ldwHHsS3w2CQYXHjneHf11lMQNXgvUg
pX0DMC8P6JPWzl1pFNX9jotmPeufVC6aEofxnPoI8XXFGpgKExHXqC68NQQLnWc98rbrhoMCORgG
xuoOBSPUisjJwsOY9Ae+BphkTo4YpNMYLYeW/bU2doe874Hl34E5elvHqmav1nhE9LV9GQvL9zw0
Dr01/AH749VEydEbpK1HU7oHvtM1Siiezi4E9w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5856)
`protect data_block
Gbv6eVrj8mncVusmlvyExc63VkGYzXvVzaUoJrNUudbYyhodB2nbz3thDzDnrVvZSETnfKEdLas3
MtjU6hvHUhdm13RTBVhLscBDxsUN8kaw0QzULCzkspi1HiZ4et1EXbgaUowBLhb403Wk2J+m0sc7
Ok0fA0fUtK8MmSTuMeAgIjsruzFSeqOFyLmqRHdGVljLIS3aOq//uKOhQAhvkUfWVDqqbYhYMxkG
71U/q4thi3pjPlU6n2EGti23wrrERANdVUWTmuWgE6gekB/lY+7covzZ/HYp2nG6rXrdKNVDrb0s
u09sPHBdgxipXmO8+7yaCU15Z5AJ3eCRmozw6af73hjp/1Os8YcJglpMDqVnDAy01ofdjnbe7bN7
5WzCfz/iQ7ZXGSweByC7aW38wHhdRKSFrxr6n5fvQukI2W/w3DfYbDIJF9g0ekqQxaqqrZqS7Zyn
qgDycDeSApuDfm3mxFdxK8kBNFjEpxXQ+tzcJHGAISLFjhI/WbOKHTCV0YNRGMpeffSfLXIyy4Zb
t7IN8wMxJ9DRK1LyTiKVBKM34fHF15XVRUOekEC4z0wtY4bfUfe1KeB09hipM/dqg5WJ9Fp5O/24
fA+XYP/h8RhSWErC3BEffXuS9+cZNFYpnT8Fp1wkDiiQ5xWevvjoi/RVLJeL8YGlhdA/uG3vA2Nk
Oi32VmWP8VtOKzdlyqN+KnIWPOlOMDvMjPmgNjowsj6yswvnC7iez0CkWRkf68wgNxZdDziGzvBY
EjwAiYllvFE48Yp0C0yun7ewEVTZH3MGIGO+vi62HvhbfUNGf9TVEDgOFne+GcGSToABeasdiO5c
8nhNAmNEYslH+3KzbkKQvIrlsMIoJwVJCK7IeSTtp80P+l7sHaVlMLgFaPoDdY2rUX0NrFGOvKl7
4uvramdJV2d2wpTs+JX/q9fNbHYwQUmz5fAOiyEc/cOepGv6oG5eKdcSw1+zigoBzgspkx0FUm2u
uIapoYMRJZ7y5iYlAxtP684v0kDFm8uVOV54q9gYYPCZX5osB7SVT6a0ytUE2IoiU5AiMmO0EwsR
/vpnCL3u6eevqbCFhEdqxPVXhV30PwLBvbV0UTiVS19Pd6LlULfbjSf/IglUMUSQ2bUN7rzSZuZG
AkkcsLXnskQR9pMlR+oLMXhVPO+lp5vnzuG6itVUqLNYJtXkoOzFg9jSHotStDfu5VvSbe32zwph
aSprV5sog2ycubiFGeCwQ9iKD1nLXqHCZeTEk4PT72JfaT8DcIA5k9LBPlGm8eRwMSz5No94tOvy
c3Q8BexgER1oFgeTsReykqCMQy678zfNbD6VJGflR95LN6nZwShzbbGh7dNWQKcpLpZm7SOv0R19
wawgxM1Ztuyi0AGTwMC6PuVBpvSWnqEyqF5K9bb/+ECffnFP4L0c1HsHV1v7uRS+ngFZkfmgloC4
BisgXILeTQroQZnYNiQepO8jdgUdsVglt/2WAWUnQtDCcrFbwHJGinrQ7hcwlPRvKXElLUOf3u+q
++MGPpI3mkRcNIEAh0L0daxX4RvxH2inWRQ8TdnlRpXS4ksk2x2NACrVcVkrow4FfCrw6b1MksER
qzM0FLtad4ud36n27ZPcJZKIGXzG3MgAgIFiY5P5tHhVgWvmzFaYTOFZD/Bwx0fzimNTQCuJn4as
TynQ2M6Aft6Be92AaRYM61Rm3P9QHKAZlwKJGtNjnlXW5eWePaNc71Yv4bh1GWz8dtqEsX0kRWgV
Bx9eqlPx/qRykHR4a3ft7/5BbQuybyFAIwAgLjr/9pjDsaj0Pll9VxAiKX+f9J9OPVpR5MS9Txhb
jmXavSpSgeJHoCUIokmWW6rcKSOmiQsp3lp4QdIssAPKH778UTFqRRHjeC8N5k6izyo2s/IzIQ1u
aRGiQbly5lFR9w2MhYS26mpEmTCnTMUjD5GH5ZaYjdkh8PB2M94NUEG8OkusRjO5OuEv8DwQO2iZ
TTHWZXPzbNs6g2hVQeiinW2DV4NYpeBjf1krjfrkIqWJ1W8N/cCksHZuaspIvaPGYGrNhI9PRJaw
sXEZArTIhQF/CCF7XiPYhmwGuExFfRRs/xBqxWAkCrcZ+F4YcmHIcwRLDnKJCoIc/7qhajBlWK0k
DGaJRWt/q2Q2N8ec2j3fB/yOrHJvY9zWN7rp2eMV5bjJ5JoJoLQ2C19dZ+E9q9s1hy5I4wx33m/Q
Kt0Ad72hsOzTL5X2SJeJuq7Cxm9DG/ajOKvhbMGLHPfH8GtZRRprHvnP8DK8dRwM5i3OlTN92Ug8
WurzWY/cZjY+0JL7N55FIDB/q5c2jXa2IZ5EEJOwYy3TgDOcehQrAv3PyzjCLO3dLyAs1JXtoPbn
MukGR6O2FacD7lG0fh979yTZ2RqSFePrUDCbV5R733mNrBPUPPtKZVrjjUxR+NtXFCioNnNv3I6u
f5evSaJnI60TQ4xS/Xi8lnu1i4u+FC80tCDsbn1mXMSM0iEwcdWRWcczh84+7WVaQZjzi4pjLNF/
VU7/hmhrPUsk3rhQq2FT8/IAsyPvcBbVkBpmLSxyZJ0R7+WwkHheq+WnKQIhyZ5vLuqs/3qOFYaQ
amLLwQxMiJVZc69IVc9tv9E0Woy8pBSeRs2jmwBZgiI0htu81kjjEuXmvyC2bkgey221R/6cnAP8
k9Tem/pOrgTyCUZ1kKZTuYKdmy2X1W9yS3BtG6op4do51j9LHtJq+h3yLo8gLKl8zOBA8NHxDNQg
q0Qb9TQtv8nAcA1H1OavcQiyRq4wccnD6FifWl2BYgLKJJbUNh3MCjSETQVtc+UZ6A0O/EZH3TQI
0AjT1MlS/weY0UOw+U4OFOTs2EzFkmmGkhCsmc6kX9oimBhnWBtnjb+HSE9FeqCrrFV5RxJBdQeo
PfPTRz8frP+eTt4K/IT4AsiuhTrUk+9fBfKs1GZ3qp/fYLKU291Q+jWCzdxwm9wJ9nxCDCZ4tKKd
JMiJp7JkVZkaFBo0g2CwUb7OmzvXG9SQKfaVHwGbkycdSlz/ZlgS9wSVnoBcK7AM3BH1HiGT2sNX
HgnEdfyQsZKgk/a8BP1HHFWKbiqnJnQKl6hPjry2/MNVbjN1S+2iM98KutChJdyTuKJl5gUYsKdd
SOltMwhJmtisjRW7bjcguSw6EO0ZBhqzqakr5/bSZcVq7kWa2vDpmhzN3O/M4JDwlOXgdfrS5Lgc
WttzofCoolt+l3fBr2Foed4ARxIYa8l5aVvppFavMTIvWfAJXA/Z1E0RC++4/nYRfeSWJyGtpWlE
j0J4IDSwObeY331JhnnAMuV0LbkpDOjxOCaslrlqViLrRKbfk34YRktYlO7fD0Sw2zCR6ZzLg06w
5oknzpZO8VaE9F0RM6EOMIeyZ2wlngTBiB8tK0POxf8iafZ0uyFkpSYdPplt3K2dYEmL+rgQ5hST
kSOK0WprauXIEmWANAvXmfuy80WXhb3qUK4MlYf9LDYAB1bldp/ivdLDnzODErsTDZkIz2viayuB
QrTGwgF5MIwm+vORNui9kwvcGkfAGwBjhfzG9gFFSweuLjwkNZ4sljoqoQqNJ2+wUBmPqHWoKA8e
ShtmtSVf9rCT7Q9Hw494arFK+fYiOcLPn+SFTxJwOLoYq3KO+eM9efxmm6IGCuZ8x2UArVc0chj1
UX6d0vlnKuloI1Iyv3QG/XyfA+iOlodPgZHELUXkDpYRxqeA+R0asGk2UNNCbqwiDzcMsi6+GeV0
Pra5fCjToiCWzP0KsUS1inzfHoHPv0WWwoOgtUHf1P8KdWWDA1BSe1Y4VV5+0dmBXFS98QB48Qfu
Zv53L5h8kks4RdkjQjfSh/P6rnxGFfHD4EJwTfvS+3TfYhc418cekzV0wZIQtt8ieNk5N2gqMZQW
6FV83qpiGJs9Frhtd4yYWiv6EQIXbsJB82ry0kncqqihtXTkwYvY6e7M+Wgngz6dk+QC8YrlO0pk
7SBzN8PImhNRuF/NmR1AY44TcsKSNb16hbLZzJeh4xLstFoqT4BSuczEvTsME39Hjdd4HK6T28+i
XpahsSgfj0NHeHmSapA3Gl5mneDzn9c0cW1fz3Ivm6cCq/q/WNo5O/ku3Ux2IT2L0t2MTIhYTDit
Wbfng1cBsDMkSxhwTvOPHFVkZS8EMTSXzKmMIVQEapX0tv11UgNn3ZuiP+dqWALvYVpR27oe9lew
2DAAyzY1zD9pW/a+AoWklXrJWQ5MBOYMk1Vx4XTSN/wYWBu1Ha0vCkUgZ64CpSyfnWN0ZDvhaeOe
yOoUmPRWHpd75aCeLm8Fzu91fUKIEVTvDplgSw0UhVgR1vZSuRxeGSLjNj0gOf8ebqE9PmDaB5cd
uOoT9jCCdc64Tt8XPFXIjv63JrzDpnbOkveEFhSqNjXEJFUXIbKZvGFEQhxSqe/CHWLsstjdDbgS
gUNmC19AiNgQITXtMK5cKjquLzQw182jIl+COVdU16xfzhPG7k5sa2M7mSkyHhaZjyxcz3mj/NtY
S5t3WxYZ9tyWYaKGX3yllbo7FdWPJWmD6i2NlkAAjk9hAqkVt9WchGKegCbFLcJ5QQYsqSAfslkw
eKyKgrQKHWG6Rj1pH0bYE411oHP/0MTqp6lne/nd9ZONk5KcW+oQ7HVGk0iCK/SKfgDjF5Uoj2n1
dL1V08pMLpYfpF+guRhxnf1yS1DJPErkJOeySKZBtEblTiSnnltuf1j2sJiHBb+zNdpv4XH1qhIT
VmGRANlKQli6Y+OBLTNuxVykgxeZ4jp6Q42JEZodDN137kxv7TpYcaKCOUbal8QMDiyMhcNu8l/U
oSInNa8bgK0P+E3JYe/LBfdy6B3iLX4d689wS0F9a0cYhRzDNK7fr9Bb1e7iMgyDKD4bWMJ6bL8X
Pq13rx823LJ0p/LNouN3BgtcNAXBwfPsk65Mdclika8VXKNCzCznPuC9pHo/vaupac9ZWWWry6Zy
P/vQ1JDY7hTPB66OixVfi9xQtVR6yz4gIlygNmIZHRRghXyeOcbGwrDlWhbbtJZ28mlJ4sd+OhTP
WFPwqpsPGz82E54GNR/gC0JEOepz0W2f4iArnQy4ISTPhd2laRdTA5O/CZ6xiJfyN366Ze4a5XBx
uzhhI0LDN8BAXz/dV0s/E3brRNbowg+UHp4ucJhkX7k+xWsqoKbgDb98j/QRCEbta/U+X62FROV+
euZOYElp+WBC+JofFpVh/zUtSv7HrrQcn9tK+wDIa12zrH60ESomyWYwBlrbanGY52r82JIMv69A
Pq1Q8jqBHUUUOMV3/tLhFGap6U/wjLUqKTw0vFFYsrbLfQ6EJK/d7QURBLsW8+JZbLUWit/8bmvp
QvoC/480keigGlDYoziJxCaiKSl9wXX1q5j08SFKV7Iy/+m64taGom77vjFCxtWiuoNdtZz0pgxm
X06aY8PfLomDbRA/S8ll/3XPnWsrqu9OxEtD/lx7jz38XIfN9nT74lUzkUiL+VUQ1SyV47EA6NPT
FDK3QikakInA+96MPwNNEBzdkwcJgCV5l33pKhwFcK23h96OoYqWU3f0VD//O9vEZPX1bTh0A7yr
/jfu/P/WfV7XlpQfyq9/haeFX4M0BVsEmXpYNIrF6d5+I5jqs6ETwNDmV9lDj/9YMUmJHp5SN1FY
4+AFPc2x32UemGYfIcrDlIMw9LCzQL9HVeLHFk2NXjr5dLBt3SkZCiHdpcmgbCOUdKg9v9kWbw/O
yBTDTLQXG9oZFqS1Gd1nYPVrPdcwhCxL0e6/xjDIjMq/xPZm2IMB4Qa1i3Apt+c6xR3dlrtSkBiK
Hoi5T04p/aHZaL/jB0v675hRBGuHcpQhBabnQtmlA0DepQVv1HGmSTqzfffvl73V7V77Xzm1Nehn
q9bWl8x/n4p6ytvFwEC4M5/jfExW5PeJK1EsVABDds4s6ULIyGWDfSkMP4AC0ImTGnKG2jf7iSp7
obq67kRSrnY85IT8SgZ+YNkKPKx4s5+bOFbRObnT8M3MUNBACx3v1o/o3oInqjznh1XQZ76HiI/N
VK/v1D7R8LuYZTQ/WbaI0nQMGCs3ovjyZXKKPsivDhTH+gRJ89JfEUH88LbDOFInJQrYJA/OaukG
KX+7fIj89KAieA05orEvz7zDqPuLwuIkSYzmuFascLGqvjUzBBiZ1PPmci24iMylsPmBe2QtLG4D
zu7H+sfUXaDUBA7YsXmsu80oAaErBoxqNrvnu2POhO5hZTybn2B/08s1R3oLxOWkC5TMgOGckVlE
5MVH3Al9M6e7LGRjy5vavnjNxnpMe2zkVPPdSxVX87zENZ1mn9Fqw0X+6lKVN3y74DO0EId7jWiE
fRrC8jMTyhEW0UrlKOufRnN2vfa5WB/hJm7BQsqKBawxjODijSSLtF3hrbcWjFcxSWyAbrwYH9WP
CnsJLp4HnpN2mVvexKNvQeHztVUUdffcf8Pjtc1Ge6G+ZtBC6Ks9bCrIuct8aHsU9EHg9vKCPckp
t6wTnrLQpn1b5SSvMq+asSOp46bz9I5pEtekq63WbDMyf9H90d7tr3gqr4l7Q78+qsAiBdOfKZe7
SBbsn03iT4TYxbjj+ZXH+CtvU0a2UnqRslQbZEHaNNgMz4iJybVT5zauhkxZFS2T8beEPuPRK+DD
G9i2H+F6zQwHWM5PpydsHfhW+InDL3IrmqFuaNLYSjbgmKsjaYsO5nPBeogtoxzDXVD6y0TkdB90
Zyk+83qhWn77fmdgK0MvGX9JsShn+DGk6K3Y/efQKbmZGeLZZO1lj2NPqRKCWqNFQO9CJxvSrR0w
5rfZtmguC6i54cSGh/3JjCzL0bi5fvHpK5eb64yNAUiOov7rTqUmheSj5R4v/rqqowBUFOMI/uv8
7g34cI/QCiIueEIsfoihfTTT1988xGvk/dfUVZSpjdhgK+RVfxPuaYzD8it1yyrjfrWbVrde5eP6
U0McX1pUtohBpZLPKh+hkZET2x4/3tr4rjHk3M+PlvEiqTDSEvGqmHL3m+pC/kdWmzirNxu/Z+Wx
O+kSMajwTpAtXn9/tuGlJnLhYhG5jpRAK6ieNZ+EWHS0mYlDsd2JhQ8J/vgyZ3V21G192c+lpFaJ
pGUwIaQGu31qYTjXxrD8xn5fOsZtbWRADYC2v1R6qyU9RJRNbiQ4YrKTLCGm/gs1gFacTBu8SHRn
K8XNSD367nLxaxAA1MCxSfNl+rfow5TBA0/06hMNFb2FfEMDfIyqDGqVG5QlEndFb3Tdco8wFEGs
z56HjAbAPPCt6yCnsqvoRj100/6VcP1lIJSJEwfvK6iNLFcpWieVndwSrdKoMZmtD9+EOReE5pAu
Ht1h2Ss/3g+bEx5nh05sl2OJm1DawAy8DvuE1g8Aw8G6k2Ic86dOpaqjkDpCso2cKPYUOoR46hI1
LAcnqMG6xta/5ZqwMvgGDNXaPIsFtTlJ+An0cDthb8XDN1JaCQ4qvznM9uOTDnXLolTP82jleFRV
ONHpDpdIUWNetnYovd8xCJ8LY9rc0vslWTKSVZYKCbJGv9SkrajWAEIqMGbN3utLmMcZIX8i967C
TE6StUaHC2YCyVslcMiJsiWS/l9BYP4TNqTTxZgdBTVglgd57rXzOE/2cDDjFBColnwueBGVRKDU
ZThzAliSIe2CgKUzlrvSv/+1iWJVEgp2qN60LG/TjmLZYIWpKE9ApGgX+NzZ77qBBbedDh1dUswj
YFUA7b3b7L0odiqtmSCfZjQ23iE/tTUX1qkGASJzwbfxPXxJOj1pmBukvggapV5At+KmN440/AsJ
bGJA5OoqMsf85rBSJK6PkL2+uVUoZKpxRIQq89uHjNtZhaOByO8dp3LG
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PGhjRVxpO1h8dnZCIbe1IUJq0Nv+WyLpeUbi8ffEVp0wMGEDTip7moZ6C/UDlMnkSvw2dhhfL+uj
CVDYn8YwIg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
FrkB8aU9gSNE85A40/TRenh4XALobCk0pFYa4vDGE3VhjeXEs2fAgEk6FEj3tmPUK337uoD6C5Iw
wfEretMQVsZ4i7woq3r6xmpe/He4R6yUxICsQeTtiSEcwHY7qUmMNRuU3/sj2T0Ur6A6g1RTA25P
ja9j+buNrE1JnNWIFDw=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Lm9LAzaC6cCmaWJsnWGYEMphZSuLOljrJ7QvNpDMz5e4mAMatD2o4MyvKAU4BeahW9nGkL88k69F
LMtAV95oTwET5Qzj/5/xWjSJ6z8ejYeRLwQI8NBiYt92rKPximPYWMy3a8k8q/mEVKgj8NFlC6rR
70qnVQmUOUE+1apwLIHeW+hTaw0ue1s9vBJ4SgeZUEL1cHrfcwGS0EHQ/Z6R+2W+/TFj3HKlPqxR
7hP3S8ME1uK2n8ViJj9bRL+pI/6Fg/VDbX7c1J5Bpjptvh9fGZ+UvB546gPJO4jZK7exQknsv5TD
VdE1ut7IvqBs7cgnBhXZy8L4jPxpMmHZPrLX+w==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
SUAJoM//nKzLs02jwOK93htq9CaAIq2RgJLj6CYZBAOFAoORXGmO2h1ROQuFfk5zCWlhZJzXSqeF
LonLYtVBK7MIK08dUa10JwVbt0uq9MEBRX92ywk63bZosqzNkhyon/jWDYf97EZhMwQUOMn3e1ev
cG5fp9XafOKlKivrngU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cgCuw8o+AJynkb4Bi4S/YmSEWkCQAjEYQJ7eeQiQL0YrML7SYM6qczOTwYsYQYFbioZlXpNlBTRK
fkWgQ7AnV+10Eb91pW+CvOO7UFttLdO6uw3Vs5j1eJeN7ldwHHsS3w2CQYXHjneHf11lMQNXgvUg
pX0DMC8P6JPWzl1pFNX9jotmPeufVC6aEofxnPoI8XXFGpgKExHXqC68NQQLnWc98rbrhoMCORgG
xuoOBSPUisjJwsOY9Ae+BphkTo4YpNMYLYeW/bU2doe874Hl34E5elvHqmav1nhE9LV9GQvL9zw0
Dr01/AH749VEydEbpK1HU7oHvtM1Siiezi4E9w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5856)
`protect data_block
Gbv6eVrj8mncVusmlvyExc63VkGYzXvVzaUoJrNUudbYyhodB2nbz3thDzDnrVvZSETnfKEdLas3
MtjU6hvHUhdm13RTBVhLscBDxsUN8kaw0QzULCzkspi1HiZ4et1EXbgaUowBLhb403Wk2J+m0sc7
Ok0fA0fUtK8MmSTuMeAgIjsruzFSeqOFyLmqRHdGVljLIS3aOq//uKOhQAhvkUfWVDqqbYhYMxkG
71U/q4thi3pjPlU6n2EGti23wrrERANdVUWTmuWgE6gekB/lY+7covzZ/HYp2nG6rXrdKNVDrb0s
u09sPHBdgxipXmO8+7yaCU15Z5AJ3eCRmozw6af73hjp/1Os8YcJglpMDqVnDAy01ofdjnbe7bN7
5WzCfz/iQ7ZXGSweByC7aW38wHhdRKSFrxr6n5fvQukI2W/w3DfYbDIJF9g0ekqQxaqqrZqS7Zyn
qgDycDeSApuDfm3mxFdxK8kBNFjEpxXQ+tzcJHGAISLFjhI/WbOKHTCV0YNRGMpeffSfLXIyy4Zb
t7IN8wMxJ9DRK1LyTiKVBKM34fHF15XVRUOekEC4z0wtY4bfUfe1KeB09hipM/dqg5WJ9Fp5O/24
fA+XYP/h8RhSWErC3BEffXuS9+cZNFYpnT8Fp1wkDiiQ5xWevvjoi/RVLJeL8YGlhdA/uG3vA2Nk
Oi32VmWP8VtOKzdlyqN+KnIWPOlOMDvMjPmgNjowsj6yswvnC7iez0CkWRkf68wgNxZdDziGzvBY
EjwAiYllvFE48Yp0C0yun7ewEVTZH3MGIGO+vi62HvhbfUNGf9TVEDgOFne+GcGSToABeasdiO5c
8nhNAmNEYslH+3KzbkKQvIrlsMIoJwVJCK7IeSTtp80P+l7sHaVlMLgFaPoDdY2rUX0NrFGOvKl7
4uvramdJV2d2wpTs+JX/q9fNbHYwQUmz5fAOiyEc/cOepGv6oG5eKdcSw1+zigoBzgspkx0FUm2u
uIapoYMRJZ7y5iYlAxtP684v0kDFm8uVOV54q9gYYPCZX5osB7SVT6a0ytUE2IoiU5AiMmO0EwsR
/vpnCL3u6eevqbCFhEdqxPVXhV30PwLBvbV0UTiVS19Pd6LlULfbjSf/IglUMUSQ2bUN7rzSZuZG
AkkcsLXnskQR9pMlR+oLMXhVPO+lp5vnzuG6itVUqLNYJtXkoOzFg9jSHotStDfu5VvSbe32zwph
aSprV5sog2ycubiFGeCwQ9iKD1nLXqHCZeTEk4PT72JfaT8DcIA5k9LBPlGm8eRwMSz5No94tOvy
c3Q8BexgER1oFgeTsReykqCMQy678zfNbD6VJGflR95LN6nZwShzbbGh7dNWQKcpLpZm7SOv0R19
wawgxM1Ztuyi0AGTwMC6PuVBpvSWnqEyqF5K9bb/+ECffnFP4L0c1HsHV1v7uRS+ngFZkfmgloC4
BisgXILeTQroQZnYNiQepO8jdgUdsVglt/2WAWUnQtDCcrFbwHJGinrQ7hcwlPRvKXElLUOf3u+q
++MGPpI3mkRcNIEAh0L0daxX4RvxH2inWRQ8TdnlRpXS4ksk2x2NACrVcVkrow4FfCrw6b1MksER
qzM0FLtad4ud36n27ZPcJZKIGXzG3MgAgIFiY5P5tHhVgWvmzFaYTOFZD/Bwx0fzimNTQCuJn4as
TynQ2M6Aft6Be92AaRYM61Rm3P9QHKAZlwKJGtNjnlXW5eWePaNc71Yv4bh1GWz8dtqEsX0kRWgV
Bx9eqlPx/qRykHR4a3ft7/5BbQuybyFAIwAgLjr/9pjDsaj0Pll9VxAiKX+f9J9OPVpR5MS9Txhb
jmXavSpSgeJHoCUIokmWW6rcKSOmiQsp3lp4QdIssAPKH778UTFqRRHjeC8N5k6izyo2s/IzIQ1u
aRGiQbly5lFR9w2MhYS26mpEmTCnTMUjD5GH5ZaYjdkh8PB2M94NUEG8OkusRjO5OuEv8DwQO2iZ
TTHWZXPzbNs6g2hVQeiinW2DV4NYpeBjf1krjfrkIqWJ1W8N/cCksHZuaspIvaPGYGrNhI9PRJaw
sXEZArTIhQF/CCF7XiPYhmwGuExFfRRs/xBqxWAkCrcZ+F4YcmHIcwRLDnKJCoIc/7qhajBlWK0k
DGaJRWt/q2Q2N8ec2j3fB/yOrHJvY9zWN7rp2eMV5bjJ5JoJoLQ2C19dZ+E9q9s1hy5I4wx33m/Q
Kt0Ad72hsOzTL5X2SJeJuq7Cxm9DG/ajOKvhbMGLHPfH8GtZRRprHvnP8DK8dRwM5i3OlTN92Ug8
WurzWY/cZjY+0JL7N55FIDB/q5c2jXa2IZ5EEJOwYy3TgDOcehQrAv3PyzjCLO3dLyAs1JXtoPbn
MukGR6O2FacD7lG0fh979yTZ2RqSFePrUDCbV5R733mNrBPUPPtKZVrjjUxR+NtXFCioNnNv3I6u
f5evSaJnI60TQ4xS/Xi8lnu1i4u+FC80tCDsbn1mXMSM0iEwcdWRWcczh84+7WVaQZjzi4pjLNF/
VU7/hmhrPUsk3rhQq2FT8/IAsyPvcBbVkBpmLSxyZJ0R7+WwkHheq+WnKQIhyZ5vLuqs/3qOFYaQ
amLLwQxMiJVZc69IVc9tv9E0Woy8pBSeRs2jmwBZgiI0htu81kjjEuXmvyC2bkgey221R/6cnAP8
k9Tem/pOrgTyCUZ1kKZTuYKdmy2X1W9yS3BtG6op4do51j9LHtJq+h3yLo8gLKl8zOBA8NHxDNQg
q0Qb9TQtv8nAcA1H1OavcQiyRq4wccnD6FifWl2BYgLKJJbUNh3MCjSETQVtc+UZ6A0O/EZH3TQI
0AjT1MlS/weY0UOw+U4OFOTs2EzFkmmGkhCsmc6kX9oimBhnWBtnjb+HSE9FeqCrrFV5RxJBdQeo
PfPTRz8frP+eTt4K/IT4AsiuhTrUk+9fBfKs1GZ3qp/fYLKU291Q+jWCzdxwm9wJ9nxCDCZ4tKKd
JMiJp7JkVZkaFBo0g2CwUb7OmzvXG9SQKfaVHwGbkycdSlz/ZlgS9wSVnoBcK7AM3BH1HiGT2sNX
HgnEdfyQsZKgk/a8BP1HHFWKbiqnJnQKl6hPjry2/MNVbjN1S+2iM98KutChJdyTuKJl5gUYsKdd
SOltMwhJmtisjRW7bjcguSw6EO0ZBhqzqakr5/bSZcVq7kWa2vDpmhzN3O/M4JDwlOXgdfrS5Lgc
WttzofCoolt+l3fBr2Foed4ARxIYa8l5aVvppFavMTIvWfAJXA/Z1E0RC++4/nYRfeSWJyGtpWlE
j0J4IDSwObeY331JhnnAMuV0LbkpDOjxOCaslrlqViLrRKbfk34YRktYlO7fD0Sw2zCR6ZzLg06w
5oknzpZO8VaE9F0RM6EOMIeyZ2wlngTBiB8tK0POxf8iafZ0uyFkpSYdPplt3K2dYEmL+rgQ5hST
kSOK0WprauXIEmWANAvXmfuy80WXhb3qUK4MlYf9LDYAB1bldp/ivdLDnzODErsTDZkIz2viayuB
QrTGwgF5MIwm+vORNui9kwvcGkfAGwBjhfzG9gFFSweuLjwkNZ4sljoqoQqNJ2+wUBmPqHWoKA8e
ShtmtSVf9rCT7Q9Hw494arFK+fYiOcLPn+SFTxJwOLoYq3KO+eM9efxmm6IGCuZ8x2UArVc0chj1
UX6d0vlnKuloI1Iyv3QG/XyfA+iOlodPgZHELUXkDpYRxqeA+R0asGk2UNNCbqwiDzcMsi6+GeV0
Pra5fCjToiCWzP0KsUS1inzfHoHPv0WWwoOgtUHf1P8KdWWDA1BSe1Y4VV5+0dmBXFS98QB48Qfu
Zv53L5h8kks4RdkjQjfSh/P6rnxGFfHD4EJwTfvS+3TfYhc418cekzV0wZIQtt8ieNk5N2gqMZQW
6FV83qpiGJs9Frhtd4yYWiv6EQIXbsJB82ry0kncqqihtXTkwYvY6e7M+Wgngz6dk+QC8YrlO0pk
7SBzN8PImhNRuF/NmR1AY44TcsKSNb16hbLZzJeh4xLstFoqT4BSuczEvTsME39Hjdd4HK6T28+i
XpahsSgfj0NHeHmSapA3Gl5mneDzn9c0cW1fz3Ivm6cCq/q/WNo5O/ku3Ux2IT2L0t2MTIhYTDit
Wbfng1cBsDMkSxhwTvOPHFVkZS8EMTSXzKmMIVQEapX0tv11UgNn3ZuiP+dqWALvYVpR27oe9lew
2DAAyzY1zD9pW/a+AoWklXrJWQ5MBOYMk1Vx4XTSN/wYWBu1Ha0vCkUgZ64CpSyfnWN0ZDvhaeOe
yOoUmPRWHpd75aCeLm8Fzu91fUKIEVTvDplgSw0UhVgR1vZSuRxeGSLjNj0gOf8ebqE9PmDaB5cd
uOoT9jCCdc64Tt8XPFXIjv63JrzDpnbOkveEFhSqNjXEJFUXIbKZvGFEQhxSqe/CHWLsstjdDbgS
gUNmC19AiNgQITXtMK5cKjquLzQw182jIl+COVdU16xfzhPG7k5sa2M7mSkyHhaZjyxcz3mj/NtY
S5t3WxYZ9tyWYaKGX3yllbo7FdWPJWmD6i2NlkAAjk9hAqkVt9WchGKegCbFLcJ5QQYsqSAfslkw
eKyKgrQKHWG6Rj1pH0bYE411oHP/0MTqp6lne/nd9ZONk5KcW+oQ7HVGk0iCK/SKfgDjF5Uoj2n1
dL1V08pMLpYfpF+guRhxnf1yS1DJPErkJOeySKZBtEblTiSnnltuf1j2sJiHBb+zNdpv4XH1qhIT
VmGRANlKQli6Y+OBLTNuxVykgxeZ4jp6Q42JEZodDN137kxv7TpYcaKCOUbal8QMDiyMhcNu8l/U
oSInNa8bgK0P+E3JYe/LBfdy6B3iLX4d689wS0F9a0cYhRzDNK7fr9Bb1e7iMgyDKD4bWMJ6bL8X
Pq13rx823LJ0p/LNouN3BgtcNAXBwfPsk65Mdclika8VXKNCzCznPuC9pHo/vaupac9ZWWWry6Zy
P/vQ1JDY7hTPB66OixVfi9xQtVR6yz4gIlygNmIZHRRghXyeOcbGwrDlWhbbtJZ28mlJ4sd+OhTP
WFPwqpsPGz82E54GNR/gC0JEOepz0W2f4iArnQy4ISTPhd2laRdTA5O/CZ6xiJfyN366Ze4a5XBx
uzhhI0LDN8BAXz/dV0s/E3brRNbowg+UHp4ucJhkX7k+xWsqoKbgDb98j/QRCEbta/U+X62FROV+
euZOYElp+WBC+JofFpVh/zUtSv7HrrQcn9tK+wDIa12zrH60ESomyWYwBlrbanGY52r82JIMv69A
Pq1Q8jqBHUUUOMV3/tLhFGap6U/wjLUqKTw0vFFYsrbLfQ6EJK/d7QURBLsW8+JZbLUWit/8bmvp
QvoC/480keigGlDYoziJxCaiKSl9wXX1q5j08SFKV7Iy/+m64taGom77vjFCxtWiuoNdtZz0pgxm
X06aY8PfLomDbRA/S8ll/3XPnWsrqu9OxEtD/lx7jz38XIfN9nT74lUzkUiL+VUQ1SyV47EA6NPT
FDK3QikakInA+96MPwNNEBzdkwcJgCV5l33pKhwFcK23h96OoYqWU3f0VD//O9vEZPX1bTh0A7yr
/jfu/P/WfV7XlpQfyq9/haeFX4M0BVsEmXpYNIrF6d5+I5jqs6ETwNDmV9lDj/9YMUmJHp5SN1FY
4+AFPc2x32UemGYfIcrDlIMw9LCzQL9HVeLHFk2NXjr5dLBt3SkZCiHdpcmgbCOUdKg9v9kWbw/O
yBTDTLQXG9oZFqS1Gd1nYPVrPdcwhCxL0e6/xjDIjMq/xPZm2IMB4Qa1i3Apt+c6xR3dlrtSkBiK
Hoi5T04p/aHZaL/jB0v675hRBGuHcpQhBabnQtmlA0DepQVv1HGmSTqzfffvl73V7V77Xzm1Nehn
q9bWl8x/n4p6ytvFwEC4M5/jfExW5PeJK1EsVABDds4s6ULIyGWDfSkMP4AC0ImTGnKG2jf7iSp7
obq67kRSrnY85IT8SgZ+YNkKPKx4s5+bOFbRObnT8M3MUNBACx3v1o/o3oInqjznh1XQZ76HiI/N
VK/v1D7R8LuYZTQ/WbaI0nQMGCs3ovjyZXKKPsivDhTH+gRJ89JfEUH88LbDOFInJQrYJA/OaukG
KX+7fIj89KAieA05orEvz7zDqPuLwuIkSYzmuFascLGqvjUzBBiZ1PPmci24iMylsPmBe2QtLG4D
zu7H+sfUXaDUBA7YsXmsu80oAaErBoxqNrvnu2POhO5hZTybn2B/08s1R3oLxOWkC5TMgOGckVlE
5MVH3Al9M6e7LGRjy5vavnjNxnpMe2zkVPPdSxVX87zENZ1mn9Fqw0X+6lKVN3y74DO0EId7jWiE
fRrC8jMTyhEW0UrlKOufRnN2vfa5WB/hJm7BQsqKBawxjODijSSLtF3hrbcWjFcxSWyAbrwYH9WP
CnsJLp4HnpN2mVvexKNvQeHztVUUdffcf8Pjtc1Ge6G+ZtBC6Ks9bCrIuct8aHsU9EHg9vKCPckp
t6wTnrLQpn1b5SSvMq+asSOp46bz9I5pEtekq63WbDMyf9H90d7tr3gqr4l7Q78+qsAiBdOfKZe7
SBbsn03iT4TYxbjj+ZXH+CtvU0a2UnqRslQbZEHaNNgMz4iJybVT5zauhkxZFS2T8beEPuPRK+DD
G9i2H+F6zQwHWM5PpydsHfhW+InDL3IrmqFuaNLYSjbgmKsjaYsO5nPBeogtoxzDXVD6y0TkdB90
Zyk+83qhWn77fmdgK0MvGX9JsShn+DGk6K3Y/efQKbmZGeLZZO1lj2NPqRKCWqNFQO9CJxvSrR0w
5rfZtmguC6i54cSGh/3JjCzL0bi5fvHpK5eb64yNAUiOov7rTqUmheSj5R4v/rqqowBUFOMI/uv8
7g34cI/QCiIueEIsfoihfTTT1988xGvk/dfUVZSpjdhgK+RVfxPuaYzD8it1yyrjfrWbVrde5eP6
U0McX1pUtohBpZLPKh+hkZET2x4/3tr4rjHk3M+PlvEiqTDSEvGqmHL3m+pC/kdWmzirNxu/Z+Wx
O+kSMajwTpAtXn9/tuGlJnLhYhG5jpRAK6ieNZ+EWHS0mYlDsd2JhQ8J/vgyZ3V21G192c+lpFaJ
pGUwIaQGu31qYTjXxrD8xn5fOsZtbWRADYC2v1R6qyU9RJRNbiQ4YrKTLCGm/gs1gFacTBu8SHRn
K8XNSD367nLxaxAA1MCxSfNl+rfow5TBA0/06hMNFb2FfEMDfIyqDGqVG5QlEndFb3Tdco8wFEGs
z56HjAbAPPCt6yCnsqvoRj100/6VcP1lIJSJEwfvK6iNLFcpWieVndwSrdKoMZmtD9+EOReE5pAu
Ht1h2Ss/3g+bEx5nh05sl2OJm1DawAy8DvuE1g8Aw8G6k2Ic86dOpaqjkDpCso2cKPYUOoR46hI1
LAcnqMG6xta/5ZqwMvgGDNXaPIsFtTlJ+An0cDthb8XDN1JaCQ4qvznM9uOTDnXLolTP82jleFRV
ONHpDpdIUWNetnYovd8xCJ8LY9rc0vslWTKSVZYKCbJGv9SkrajWAEIqMGbN3utLmMcZIX8i967C
TE6StUaHC2YCyVslcMiJsiWS/l9BYP4TNqTTxZgdBTVglgd57rXzOE/2cDDjFBColnwueBGVRKDU
ZThzAliSIe2CgKUzlrvSv/+1iWJVEgp2qN60LG/TjmLZYIWpKE9ApGgX+NzZ77qBBbedDh1dUswj
YFUA7b3b7L0odiqtmSCfZjQ23iE/tTUX1qkGASJzwbfxPXxJOj1pmBukvggapV5At+KmN440/AsJ
bGJA5OoqMsf85rBSJK6PkL2+uVUoZKpxRIQq89uHjNtZhaOByO8dp3LG
`protect end_protected
|
library verilog;
use verilog.vl_types.all;
entity acb_96_bit is
generic(
ANALOG_QUAD_NUM : integer := 6;
ACB_BYTES_NUM_PER_QUAD: integer := 12;
WARNING_MSGS_ON : integer := 1
);
port(
ACB_RST : in vl_logic;
ACB_WEN : in vl_logic;
ACB_ADDR : in vl_logic_vector(7 downto 0);
ACB_WDATA : in vl_logic_vector(7 downto 0);
ACB_RDATA : out vl_logic_vector(7 downto 0);
AQO_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQO_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQO_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQO_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ0_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
AQ1_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQ1_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQ1_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQ1_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ1_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
AQ2_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQ2_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQ2_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQ2_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ2_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
AQ3_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQ3_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQ3_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQ3_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ3_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
AQ4_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQ4_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQ4_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQ4_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ4_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
AQ5_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQ5_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQ5_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQ5_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ5_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
DAC0_CONFIG : out vl_logic_vector(1 downto 0);
DAC1_CONFIG : out vl_logic_vector(1 downto 0);
DAC2_CONFIG : out vl_logic_vector(1 downto 0)
);
end acb_96_bit;
|
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