content stringlengths 1 1.04M ⌀ |
|---|
-- Does not saturate currently, only provides built in VHDL addition.
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity AdderSat is
generic (
wordLength : natural := 12
);
port (
a : in std_logic_vector(wordLength-1 downto 0);
b : in std_logic_vector(wordLength-1 downto 0);
... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-... |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-... |
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: filtering_alogrithm_single - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
---------------------------------... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity bbtas_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end bbtas_jed;
architecture behaviour of bbtas_jed is
constant st0: std_logic_vector(2 downto 0) :... |
-- NEED RESULT: ARCH00557: Variable declarations - scalar globally static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
------------------------------------------------... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1_jed is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(5 downto 0)
);
end s1_jed;
architecture behaviour of s1_jed is
constant st0: std_logic_vector(4 downto 0) := "11100"... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos (rodrigo4zevedo@gmail.com)
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity ReedSolomonEncoder is
Po... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- c_0_0 opt232
cfg.gridConf(0)(0).procConf.AluOpxS := alu_pass0;
-- i.0
cfg.gridConf(0)(0).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(0).routConf.i(0).LocalxE(LOCAL_SW) := '1';
-- c_0_1 op13
cfg.gridConf(0)(1).procConf.AluOpxS := alu_add;
-- i.0
cfg.gridConf(0)(1).procConf.OpMuxS(0) := I_NOREG;
cfg.gridConf(0)(1... |
architecture RTL of FIFO is
begin
-- These are passing
a <= b; -- Comment 1
a <= when c = '0' else '1'; -- Comment 2
a <= b; -- Comment 3
a <= when c = '0' else '1'; -- Comment 4
-- Failing variations
a <= b;-- Comment 1
a <= when c = '0' else '1'; -- Co... |
-------------------------------------------------------------------------------
-- rd_chnl.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of ... |
-------------------------------------------------------------------------------
-- rd_chnl.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of ... |
--
-- This file is part of top_wireworld
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either versio... |
entity repro4 is
end;
architecture behav of repro4 is
begin
process
begin
"foo" (true, false);
end process;
end;
|
library verilog;
use verilog.vl_types.all;
entity View_output_vlg_vec_tst is
end View_output_vlg_vec_tst;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNZ5LMFB5D is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNZ5LMFB5D is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNZ5LMFB5D is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNZ5LMFB5D is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNZ5LMFB5D is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNZ5LMFB5D is
generic ( round : natural := 0;
saturate : natural := 0);
port(
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based_control_part_pseudo is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
library IEEE;
use ieee.std_logic_1164.all;
entity four_to_one_mux_1_bit is
port(
a, b, c, d : in std_logic;
sel : in std_logic_vector(1 downto 0);
output : out std_logic
);
end entity four_to_one_mux_1_bit;
architecture behav of four_to_one_mux_1_bit is
begin
--output <= (a and (not sel(0)) and (not sel(1)... |
--************************************************************************************************
-- Arrbiter and Address/Data multiplexer for AVR core
-- Version 0.2
-- Designed by Ruslan Lepetenok
-- Modified 27.07.2005
--************************************************************************************... |
--************************************************************************************************
-- Arrbiter and Address/Data multiplexer for AVR core
-- Version 0.2
-- Designed by Ruslan Lepetenok
-- Modified 27.07.2005
--************************************************************************************... |
--************************************************************************************************
-- Arrbiter and Address/Data multiplexer for AVR core
-- Version 0.2
-- Designed by Ruslan Lepetenok
-- Modified 27.07.2005
--************************************************************************************... |
--************************************************************************************************
-- Arrbiter and Address/Data multiplexer for AVR core
-- Version 0.2
-- Designed by Ruslan Lepetenok
-- Modified 27.07.2005
--************************************************************************************... |
-- $Id: sramif_mig_arty.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: sramif_mig_arty - syn
-- Description: ... |
library verilog;
use verilog.vl_types.all;
entity generic_pll is
generic(
lpm_type : string := "generic_pll";
duty_cycle : integer := 50;
output_clock_frequency: string := "0 ps";
phase_shift : string := "0 ps";
reference_clock_frequency: string := "0 ps";... |
library verilog;
use verilog.vl_types.all;
entity generic_pll is
generic(
lpm_type : string := "generic_pll";
duty_cycle : integer := 50;
output_clock_frequency: string := "0 ps";
phase_shift : string := "0 ps";
reference_clock_frequency: string := "0 ps";... |
library verilog;
use verilog.vl_types.all;
entity generic_pll is
generic(
lpm_type : string := "generic_pll";
duty_cycle : integer := 50;
output_clock_frequency: string := "0 ps";
phase_shift : string := "0 ps";
reference_clock_frequency: string := "0 ps";... |
library verilog;
use verilog.vl_types.all;
entity generic_pll is
generic(
lpm_type : string := "generic_pll";
duty_cycle : integer := 50;
output_clock_frequency: string := "0 ps";
phase_shift : string := "0 ps";
reference_clock_frequency: string := "0 ps";... |
library verilog;
use verilog.vl_types.all;
entity generic_pll is
generic(
lpm_type : string := "generic_pll";
duty_cycle : integer := 50;
output_clock_frequency: string := "0 ps";
phase_shift : string := "0 ps";
reference_clock_frequency: string := "0 ps";... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_case_statement_GN4KF5KLTA is
generic ( number_outputs : integer := 5;
hasDefault : nat... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_case_statement_GN4KF5KLTA is
generic ( number_outputs : integer := 5;
hasDefault : nat... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_case_statement_GN4KF5KLTA is
generic ( number_outputs : integer := 5;
hasDefault : nat... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_case_statement_GN4KF5KLTA is
generic ( number_outputs : integer := 5;
hasDefault : nat... |
------------------------------------------------------------------------------
-- Title : BPM RF channels swapping and de-swapping mode selector
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-... |
package pack is
type rec is record
a, b : integer;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
x : in integer;
y : out integer;
r : in rec );
end entity;
architecture ... |
package pack is
type rec is record
a, b : integer;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
x : in integer;
y : out integer;
r : in rec );
end entity;
architecture ... |
package pack is
type rec is record
a, b : integer;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
x : in integer;
y : out integer;
r : in rec );
end entity;
architecture ... |
package pack is
type rec is record
a, b : integer;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
x : in integer;
y : out integer;
r : in rec );
end entity;
architecture ... |
package pack is
type rec is record
a, b : integer;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
x : in integer;
y : out integer;
r : in rec );
end entity;
architecture ... |
-- Twofish_cbc_decryption_monte_carlo_testbench_192bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at y... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tbmem is
end entity tbmem;
architecture TB of tbmem is
begin
DM: process
type t_ram is array(natural range <>) of unsigned;
type p_ram is access t_ram;
variable myram : p_ram;
begin
myram := new t_ram... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:24:29 02/20/2013
-- Design Name:
-- Module Name: /home/frank/testproject/PCounte_tb.vhd
-- Project Name: testproject
-- Target Device:
-- Tool versions:
-- Description:
--
-- ... |
-------------------------------------------------------------------------
---- ----
---- Company: University of Bonn ----
---- Engineer: Daniel Hahne & John Bieling ----
---- ... |
-- NEED RESULT: *** An assertion follows with severity level ERROR
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-----------------------------------------------------------------------... |
library IEEE;
use ieee.std_logic_1164.all;
entity c_register is
generic
(
width : integer := 4
);
port
(
input : in std_logic_vector((width - 1) downto 0);
wr : in std_logic;
clear : in std_logic;
clock : in std_logic;
output : out std_logic_vector((width - 1) downto 0)
);
end c_register;
architectu... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:33:37 03/14/2015
-- Design Name:
-- Module Name: Main - RTL
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Rev... |
CONFIGURATION Reg_Behavior_config OF Reg IS
FOR Behavior
END FOR;
END Reg_Behavior_config; |
CONFIGURATION Reg_Behavior_config OF Reg IS
FOR Behavior
END FOR;
END Reg_Behavior_config; |
CONFIGURATION Reg_Behavior_config OF Reg IS
FOR Behavior
END FOR;
END Reg_Behavior_config; |
-- ########################################################################
-- $Software: busiac
-- $section : hardware component
-- $Id: initiateur.vhd 327 2015-06-03 19:18:19Z ia $
-- $HeadURL: svn://lunix120.ensiie.fr/ia/cours/archi/projet/busiac/vhdl/initiateur.vhd $
-- $Author : Ivan Auge (Email: auge@ens... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:10:19 03/04/2014
-- Design Name:
-- Module Name: C:/Users/fafik/Dropbox/infa/xilinx/ethernet/smi_divider_test.vhd
-- Project Name: ethernet
-- Target Device:
-- Tool versions:
-- ... |
--------------------------------------------------------------------------------
--
-- File:
-- SerializerN_1.vhd
--
-- Module:
-- SerializerN_1
--
-- Author:
-- Elod Gyorgy
--
-- Date:
-- 10/27/2010
--
-- Description:
-- This module serializes N:1 data LSB-first using cascaded OSERDES... |
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_aa
--
-- Generated
-- by: wig
-- on: Fri Jul 15 16:37:20 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id:... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:07:34 11/19/2013
-- Design Name:
-- Module Name: My_ALU_948282 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- R... |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Fre... |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Fre... |
library verilog;
use verilog.vl_types.all;
entity IF_ID is
port(
clock : in vl_logic;
reset : in vl_logic;
\In\ : in vl_logic_vector(15 downto 0);
InEnable : in vl_logic;
\Out\ : out vl_logic_vector(15 downto ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library WORK;
use WORK.globals.all;
entity DDR_enable is
generic( SIZE : integer := 8 );
port(
din_hi, din_lo : in std_logic_vector( SIZE-1 downto 0 );
enable : in T_ENABLE;
dout_hi, dout_lo : out std_logic_vecto... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library WORK;
use WORK.globals.all;
entity DDR_enable is
generic( SIZE : integer := 8 );
port(
din_hi, din_lo : in std_logic_vector( SIZE-1 downto 0 );
enable : in T_ENABLE;
dout_hi, dout_lo : out std_logic_vecto... |
ComparadorFinal_inst : ComparadorFinal PORT MAP (
clken => clken_sig,
clock => clock_sig,
dataa => dataa_sig,
datab => datab_sig,
AeB => AeB_sig,
AgB => AgB_sig,
AlB => AlB_sig
);
|
library ieee;
use ieee.std_logic_1164.all;
use work.types.all;
package math is
function mul2(din : byte) return byte;
function mul3(din : byte) return byte;
function mul9(din : byte) return byte;
function mulb(din : byte) return byte;
function muld(din : byte) return byte;
function mule(din : byte) return byte;... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AXIinterfacefor65816_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_DATA_WIDTH : ... |
entity FIFO is
generic (
G_WIDTH : natural := 16
);
port (
I_DATA : in std_logic_vector(G_WIDTH - 1 downto 0);
O_DATA : in std_logic_vector(g_width - 1 downto 0)
);
end entity;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- ... |
---------------------------------------------------------------------------
-- Company : Automaticaly generated by POD
-- Author(s) :
--
-- Creation Date : 2008-10-20
-- File : Top_i2ctest_tb.vhd
--
-- Abstract :
-- insert a description here
--
---------------------------------------------------------... |
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- twi_master_1.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
u... |
----- package mem3 -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE mem3 IS
TYPE mem_type_5 IS array (Integer range <>) OF std_logic_vector(17 downto 0);
TYPE mem_type_6 IS array (Integer range <>) OF std_logic_vector(15 downto 0);
FUNCTION hex2bin (hex: character) RETURN std_logic_vector;
FUNC... |
----- package mem3 -----
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE mem3 IS
TYPE mem_type_5 IS array (Integer range <>) OF std_logic_vector(17 downto 0);
TYPE mem_type_6 IS array (Integer range <>) OF std_logic_vector(15 downto 0);
FUNCTION hex2bin (hex: character) RETURN std_logic_vector;
FUNC... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY LatchSR_AA_TB IS
END LatchSR_AA_TB;
ARCHITECTURE behavior OF LatchSR_AA_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT LatchSR_AA
PORT(
S : IN std_logic;
R : IN std_logic;
Q : OUT std_logic;
... |
-------------------------------------------------------------------------------
--
-- File: top.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent In... |
-------------------------------------------------------------------------------
--
-- File: top.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent In... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_t_e
--
-- Generated
-- by: wig
-- on: Tue Mar 30 18:39:52 2004
-- cmd: H:\work\mix_new\MIX\mix_0.pl -strip -nodelta ../../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library verilog;
use verilog.vl_types.all;
entity acb_96_bit is
generic(
ANALOG_QUAD_NUM : integer := 6;
ACB_BYTES_NUM_PER_QUAD: integer := 12;
WARNING_MSGS_ON : integer := 1
);
port(
ACB_RST : in vl_logic;
ACB_WEN : in vl_logic;
ACB_AD... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.