content stringlengths 1 1.04M ⌀ |
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library verilog;
use verilog.vl_types.all;
entity acb_96_bit is
generic(
ANALOG_QUAD_NUM : integer := 6;
ACB_BYTES_NUM_PER_QUAD: integer := 12;
WARNING_MSGS_ON : integer := 1
);
port(
ACB_RST : in vl_logic;
ACB_WEN : in vl_logic;
ACB_ADDR : in vl_logic_vector(7 downto 0);
ACB_WDATA : in vl_logic_vector(7 downto 0);
ACB_RDATA : out vl_logic_vector(7 downto 0);
AQO_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQO_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQO_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQO_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ0_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
AQ1_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQ1_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQ1_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQ1_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ1_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
AQ2_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQ2_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQ2_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQ2_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ2_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
AQ3_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQ3_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQ3_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQ3_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ3_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
AQ4_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQ4_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQ4_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQ4_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ4_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
AQ5_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQ5_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQ5_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQ5_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ5_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
DAC0_CONFIG : out vl_logic_vector(1 downto 0);
DAC1_CONFIG : out vl_logic_vector(1 downto 0);
DAC2_CONFIG : out vl_logic_vector(1 downto 0)
);
end acb_96_bit;
|
library verilog;
use verilog.vl_types.all;
entity acb_96_bit is
generic(
ANALOG_QUAD_NUM : integer := 6;
ACB_BYTES_NUM_PER_QUAD: integer := 12;
WARNING_MSGS_ON : integer := 1
);
port(
ACB_RST : in vl_logic;
ACB_WEN : in vl_logic;
ACB_ADDR : in vl_logic_vector(7 downto 0);
ACB_WDATA : in vl_logic_vector(7 downto 0);
ACB_RDATA : out vl_logic_vector(7 downto 0);
AQO_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQO_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQO_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQO_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ0_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
AQ1_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQ1_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQ1_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQ1_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ1_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
AQ2_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQ2_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQ2_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQ2_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ2_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
AQ3_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQ3_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQ3_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQ3_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ3_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
AQ4_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQ4_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQ4_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQ4_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ4_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
AQ5_AV1_CONFIG : out vl_logic_vector(3 downto 0);
AQ5_AV2_CONFIG : out vl_logic_vector(3 downto 0);
AQ5_AC_CONFIG : out vl_logic_vector(7 downto 0);
AQ5_AT_CONFIG : out vl_logic_vector(7 downto 0);
AQ5_DAC_MUX_SEL : out vl_logic_vector(1 downto 0);
DAC0_CONFIG : out vl_logic_vector(1 downto 0);
DAC1_CONFIG : out vl_logic_vector(1 downto 0);
DAC2_CONFIG : out vl_logic_vector(1 downto 0)
);
end acb_96_bit;
|
library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
i : in bit;
o : out bit
);
end;
architecture a of ent is
signal test : std_logic_vector(7 downto 0);
alias a : std_logic_vector(7 downto 0) is test;
begin
process(i)
begin
if a = x"00" then
end if;
o <= i;
end process;
end;
|
entity test is
end test;
architecture only of test is
procedure proc (
constant a : in bit_vector;
constant l : in integer ) is
type dyn is range a'left downto 0;
begin
assert dyn'left = l report "TEST FAILED" severity FAILURE;
end proc;
begin -- only
doit: process
begin -- process doit
proc( "0000", 3 );
proc( "00000", 4 );
report "TEST PASSED";
wait;
end process doit;
end only;
|
entity test is
end test;
architecture only of test is
procedure proc (
constant a : in bit_vector;
constant l : in integer ) is
type dyn is range a'left downto 0;
begin
assert dyn'left = l report "TEST FAILED" severity FAILURE;
end proc;
begin -- only
doit: process
begin -- process doit
proc( "0000", 3 );
proc( "00000", 4 );
report "TEST PASSED";
wait;
end process doit;
end only;
|
entity test is
end test;
architecture only of test is
procedure proc (
constant a : in bit_vector;
constant l : in integer ) is
type dyn is range a'left downto 0;
begin
assert dyn'left = l report "TEST FAILED" severity FAILURE;
end proc;
begin -- only
doit: process
begin -- process doit
proc( "0000", 3 );
proc( "00000", 4 );
report "TEST PASSED";
wait;
end process doit;
end only;
|
----------------------------------------------------------------------------------
-- Company: Open Source
-- Engineer: Steven T. Seppala ( rad- )
--
-- Create Date: 01/26/2016 03:26:56 PM
-- Design Name:
-- Module Name: 65C816 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
-- This is a soft-core implementation of a 65C816. There will be initally 92
--of the 256 OpCodes useable. Please refer to DOC 1A for reference.
--
-- Dependencies:
-- For testing purposes there will be an AXI interface into this module.
--This should be provided with all the source HDL.
--If this module is being used in conjunction with another module and there is no need
--to access or view the inner workings of this module, no other dependancies occour.
--
-- Revision: V .1 -- 26 Jan 2016 STS
--
-- Revision 0.01 - File Created
-- Additional Comments:
-- The SNES CPU (65c816) uses little endian.
-- Revision 0.5 - Decode Table and Addressing Modes
-- The decode process and addressing mode assigning table
-- processes have been crated.
-- NOTE : Memory accesses will be passed from this
-- module to a C_FLAG program for reading/writing.
-- Revision 1.0 - 18 Feb 2016
-- Main Modules finished.
-- Revision 1.1 - 3 March 2016
-- Tests passed. Main is now implemented.
--
----------------------------------------------------------------------------------
-- ██████ ███████ ███████ ████████
-- ██░░░░██ ██░░░░░██ ░██░░░░██ ░██░░░░░
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--░░██ ██░░██ ██ ░██ ░░██ ░██
-- ░░██████ ░░███████ ░██ ░░██░████████
-- ░░░░░░ ░░░░░░░ ░░ ░░ ░░░░░░░░
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--░██░██ ██░██ ██░░░░░██ ░██░░░░██ ░██ ░██░██ ░██░░░░░
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--░██ ░░███ ░██░██ ░██░██ ░██░██ ░██░██ ░███████
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--░░ ░░ ░░░░░░░ ░░░░░░░ ░░░░░░░ ░░░░░░░░ ░░░░░░░░
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.SNES65816func.all;
entity Soft_65C816 is
Port ( clk :in STD_LOGIC; -- Main CLK for system
tru_clk :in std_logic; -- True clk for system
reset :in std_logic; -- Reset Signal
Addr_Bus :out STD_LOGIC_VECTOR (23 downto 0);-- Address Bus
D_BUS :in STD_LOGIC_VECTOR (31 downto 0);-- Data Bus IN
D_BUS_out :out STD_LOGIC_VECTOR (23 downto 0);-- Data Bus OUT
EMULATION_SELECT :out STD_LOGIC; -- Emulation Bit
RDY :out STD_LOGIC;
DATA_RDY :in STD_LOGIC;
REG_A :out std_logic_vector(15 downto 0);
REG_X :out std_logic_vector(15 downto 0);
REG_Y :out std_logic_vector(15 downto 0);
REG_SP :out std_logic_vector(15 downto 0);
REG_PC :out std_logic_vector(15 downto 0);
REG_Proc :out std_logic_vector(7 downto 0);
REG_DBR :out std_logic_vector(7 downto 0);
state_machine :out std_logic_vector(15 downto 0);
RW :out std_logic ; -- Read or write bit
VPB :out STD_LOGIC);
end Soft_65C816;
architecture Behavioral of Soft_65C816 is
--state machine states
type state_machine_states is (s0, s1, s2, s3, s4, s5 , sc, sa, sm, sp, sf, ss, sn, se, si, calculate_memory_pointer, s6);
signal state : state_machine_states;
--One hot sounter for state machine location/control
signal state_machine_onehot : std_logic_vector (15 downto 0);
--chunk pull vector
signal chunk_pull : std_logic_vector (31 downto 0);
--vector with info about the opcode
signal instruction_info : std_logic_vector (11 downto 0);
signal op_code : std_logic_vector (7 downto 0);
-- This will have the instructions arguments assigned to it.
signal instrction_args : std_logic_vector (31 downto 0);
-- This signal must be run with a 3.58 MHz CLK.
-- It is just a counter, but it must count at 3.58 MHz.
signal tru_cpu : std_logic_vector (3 downto 0);
-- This is essentially a latch enable,
-- it will count for as many cycles as the
-- operation would take on a true 65816
signal tru_clk_cntr : std_logic_vector(3 downto 0);
-- This will hold the instruction size, so the PC can correctly
-- be incrimented.
signal instruction_size : std_logic_vector (3 downto 0);
-- Memory pointer for pulling and pushing values
signal memory_pointer : std_logic_vector ( 23 downto 0);
-- This signal holds the values from the memory locations
-- requested.
signal requested_values : std_logic_vector (31 downto 0);
-- This will hold type info so the correct
-- execution state can be determined.
signal type_info : std_logic_vector (3 downto 0);
--
-- Process Control Signals
--
signal addressing_done, addressing_on, decode_on, decode_done, memory_calculate_done, memory_calculate_on : STD_LOGIC;
signal memory_done:std_logic;
signal math_done : std_logic;
signal pc_done : std_logic;
signal flag_done : std_logic;
signal store_back: std_logic;
signal push_to_stack : std_logic;
signal ready_up : std_logic;
signal stack_done: std_logic;
signal exchange_done: std_logic;
signal data_enable : std_logic;
--
-- REGISTER DECLARATIONS
--
-- Program Counter : PC
-- PC Bank Register : PBR
signal PC : std_logic_vector (23 downto 0);
alias PBR : std_logic_vector (7 downto 0) is PC (23 downto 16);
alias ProgramCntr : std_logic_vector (15 downto 0) is PC (15 downto 0);
-- Accumulator : A_REG
-- Direct Page Register: DP
-- Stack Pointer : SP
-- X & Y_REG Are Index Registers
signal A_REG, DP, StackPointer, X_REG, Y_REG : std_logic_vector ( 15 downto 0);
-- StackPointer is vaid from 00:0000 to 00:FFFF
-- Processor Status : P
-- Data Bank Register : DBR
signal P : std_logic_vector ( 7 downto 0);
signal DBR : std_logic_vector ( 7 downto 0);
alias N : STD_LOGIC is P(7); -- Negative Flag
alias V : STD_LOGIC is P(6); -- Overflow Flag
alias M : STD_LOGIC is P(5); -- Memory Select
alias X_FLAG : STD_LOGIC is P(4); -- Index Register
alias D_FLAG : STD_LOGIC is P(3); -- Decimal Mode
alias I : STD_LOGIC is P(2); -- IRQ Disable
alias Z : STD_LOGIC is P(1); -- Zero Result
alias C_FLAG : STD_LOGIC is P(0); -- Carry Flag / Emulation Mode
--
-- END REGISTER DECLARATIONS
--
--
-- Memory signals
--
signal effective_memory_pointer : std_logic_vector (23 downto 0);
signal write_back_location : std_logic_vector (23 downto 0);
signal write_back_value : std_logic_vector(15 downto 0);
signal write_back_bank : std_logic_vector(7 downto 0);
signal adr_type : integer range 0 to 25;
signal push_val : std_logic_vector(23 downto 0);
signal read_out : std_logic_vector(15 downto 0);
signal read_out_bank : std_logic_vector(7 downto 0);
signal address_out : std_logic_vector(23 downto 0);
--
--
-- Constant Signals
--
--
constant zeros : std_logic_vector (15 downto 1) := ( B"0000_0000_0000_000");
begin
state_machine <= state_machine_onehot;
D_BUS_out <= read_out_bank & read_out;
Addr_Bus<= address_out;
REG_A <= A_REG;
REG_X <= X_REG;
REG_Y <= Y_REG;
REG_SP <= StackPointer;
REG_PC <= ProgramCntr;
REG_Proc <= P;
REG_DBR <= DBR;
--
-- This is the true CPU clock for the processor
-- It runs at a multiple of 3.58 MHz and allows s6 to continue
-- to s1.
slow_clock:
process(tru_clk, clk, reset) is
begin
if reset = '1' then
tru_clk_cntr <= (others => '0');
ready_up <= '0';
elsif rising_edge(clk) then
if (tru_clk_cntr = tru_cpu) and (tru_clk = '1') then
ready_up <= '1' ;
end if;
end if;
if falling_edge(clk) then
if ready_up ='1' then
tru_clk_cntr <= (others => '0');
end if;
end if;
if rising_edge(tru_clk) then
tru_clk_cntr <= std_logic_vector(unsigned(tru_clk_cntr) + 1);
end if;
end process;
--
-- This is a 16 bit microprocessor with variable length instructions, the PC will
-- depend on the current instruction size.
-- Thus the PC will get
--
--
state_machine_process:
process (clk, reset) is
variable effective_memeory_pointer_temp : std_logic_vector (23 downto 0);
variable pointer_calculation_done : std_logic;
variable math_temp : std_logic_vector (16 downto 0);
variable stack_temp : std_logic_vector (16 downto 0);
variable xfr_temp : std_logic_vector (16 downto 0);
variable mem_temp : std_logic_vector (16 downto 0);
variable flag_temp : std_logic_vector (16 downto 0);
variable check_done : std_logic;
begin
if reset = '1' then
--TODO: RESET
state <= s0; -- reset to s0
chunk_pull <= (others => 'Z'); -- clear chunk pull
op_code <= (others => 'Z'); -- set opcode hi-Z
StackPointer <= X"0100"; -- Initialize Stack pointer
A_REG <= (others => '0');
X_REG <= (others => '0');
Y_REG <= (others => '0');
PC <= (others => '0');
DBR <= X"00";
DP <= X"0000";
N <= '0';
V <= '0';
M <= '1';
X_FLAG <= '1';
D_FLAG <= '0';
I <= '1';
Z <= '0';
C_FLAG <= '1'; -- This is the emulation flag on reset.
elsif rising_edge(clk) then
case state is
when s0 =>
if state_machine_onehot = "0000000000000001" then
state <= s1;
else
state <= s0;
end if;
state_machine_onehot <= "0000000000000001";
write_back_value <=X"0000";
write_back_bank <=X"00";
address_out <=PC;
check_done := '0';
rdy <= '1';
RW <= '0';
when s1 =>
if state_machine_onehot = "0000000000000010" then
state <= s2;
else
state <= s1;
end if;
data_enable <= '1';
if data_rdy ='0' and chunk_pull /= "ZZZZZZZZZZZZZZZZZ" then
chunk_pull <= D_BUS;
state_machine_onehot <= "0000000000000010";
rdy <= '0';
end if;
when s2 =>
if ((addressing_done = '1') and (decode_done = '1') and (state_machine_onehot = "0000000000000100")) then
state <= s3;
else
state <= s2;
end if;
addressing_on <= '1';
decode_on <= '1';
-- This should send the OPCode from chunkpull
-- to the opcode_info process, which inturn
-- will give us everything we need to know about how
-- to execute the instruction.
if data_enable = '1' then
op_code <= chunk_pull(31 downto 24);
state_machine_onehot <= "0000000000000100";
data_enable <= '0';
end if;
when s3 =>
if state_machine_onehot = "0000000000001000" then
state <= s4;
else
state <= s3;
end if;
data_enable <= '1';
addressing_on <= '0';
decode_on <= '0';
instruction_size <= instruction_info(11 downto 8);
tru_cpu <= instruction_info(7 downto 4);
type_info <= instruction_info( 3 downto 0);
state_machine_onehot <= "0000000000001000";
when s4 =>
if ((state_machine_onehot = "0000000000010000") and (memory_calculate_done = '1'))then
state <= calculate_memory_pointer;
else
state <= s4;
end if;
PC <= std_logic_vector(unsigned(PC) + unsigned(instruction_size));
state_machine_onehot <= "0000000000010000";
memory_calculate_on <= '1';
when calculate_memory_pointer =>
if pointer_calculation_done = '1' then
state <= s5;
end if;
memory_calculate_on <= '0';
case adr_type is
when 0 =>
if ((op_code = X"20") or (op_code = X"4c")) then
effective_memory_pointer(23 downto 16) <= PBR;
effective_memory_pointer(15 downto 0) <= memory_pointer(15 downto 0);
else
effective_memory_pointer(23 downto 16) <= DBR;
effective_memory_pointer(15 downto 0) <= memory_pointer(15 downto 0);
end if;
pointer_calculation_done := '1';
when 1 =>
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
when 2 =>
effective_memeory_pointer_temp(23 downto 16) := DBR;
effective_memeory_pointer_temp(15 downto 0) := memory_pointer(15 downto 0);
effective_memory_pointer <= std_logic_vector(unsigned(effective_memeory_pointer_temp) + unsigned(X_REG));
pointer_calculation_done := '1';
when 3 =>
effective_memeory_pointer_temp(23 downto 16) := DBR;
effective_memeory_pointer_temp(15 downto 0) := memory_pointer(15 downto 0);
effective_memory_pointer <= std_logic_vector(unsigned(effective_memeory_pointer_temp) + unsigned(Y_REG));
pointer_calculation_done := '1';
when 4 =>
effective_memory_pointer <= memory_pointer;
pointer_calculation_done := '1';
when 5 =>
effective_memory_pointer <= std_logic_vector(unsigned(memory_pointer) + unsigned(X_REG));
pointer_calculation_done := '1';
when 6 =>
effective_memory_pointer(23 downto 16) <= PBR;
effective_memory_pointer(15 downto 0) <= memory_pointer(15 downto 0);
pointer_calculation_done := '1';
when 7 =>
effective_memory_pointer(23 downto 16) <= PBR;
effective_memory_pointer(15 downto 0) <= memory_pointer(15 downto 0) + X_REG;
pointer_calculation_done := '1';
when 8 =>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 9 =>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= StackPointer + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 10=>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= DP + X_REG + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 11=>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= DP + Y_REG + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 12=>
effective_memory_pointer(23 downto 16) <= DBR;
effective_memory_pointer(15 downto 0) <= DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 13=>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 14=>
effective_memory_pointer(23 downto 16) <= DBR;
effective_memory_pointer(15 downto 0) <= StackPointer + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 15=>
effective_memory_pointer(23 downto 16) <= DBR;
effective_memory_pointer(15 downto 0) <= X_REG + DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 16=>
effective_memory_pointer(23 downto 16) <= DBR;
effective_memory_pointer(15 downto 0) <= DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 17=>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 18=>
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
when 19=>
-- These program counter relative operations are calculated in the
-- PC state of execution.
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
when 20=>
-- These program counter relative operations are calculated in the
-- PC state of execution.
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
when 21=>
-- Stack Operations are handled in the stack state or where neccicary
effective_memory_pointer <= X"00" & StackPointer;
pointer_calculation_done := '1';
when 22=>
-- Block operations are not implemented yet
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
when 23 =>
requested_values <= X"00" & memory_pointer;
pointer_calculation_done := '1';
when others =>
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
end case;
when s5 =>
pointer_calculation_done := '0';
state_machine_onehot <= "0000000000100000";
if state_machine_onehot = "0000000000100000" then
-- Go to fan out based on type info,
-- if type info is not 0 - 8, then count it
-- as a NOP
--
if type_info = X"0" then
state <= sa;
elsif type_info = X"1" then
state <= sp;
elsif type_info = X"2" then
state <= sm;
elsif type_info = X"3" then
state <= sc;
elsif type_info = X"4" then
state <= sf;
elsif type_info = X"5" then
state <= ss;
elsif type_info = X"6" then
state <= sn;
elsif type_info = X"7" then
state <= se;
elsif type_info = X"8" then
state <= si;
-- if state can not be defined treat it as a NOP
else
state <= sn;
end if;
end if;
when sc =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sc;
end if;
state_machine_onehot <= "0000000001000000";
--
-- Arithmatic State Start
--
when sa =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sa;
end if;
-- ADC
if op_code = X"6D" or
op_code = X"7D" or
op_code = X"79" or
op_code = X"6F" or
op_code = X"7F" or
op_code = X"17" or
op_code = X"65" or
op_code = X"63" or
op_code = X"75" or
op_code = X"72" or
op_code = X"67" or
op_code = X"73" or
op_code = X"61" or
op_code = X"71" or
op_code = X"77" or
op_code = X"69" then
math_temp := ('0' & requested_values(15 downto 0)) + A_REG + ( zeros & C_FLAG);
if ((math_temp = "00000000000000000" ) or (math_temp = "10000000000000000")) then
Z <= '1';
N <= math_temp (15);
V <= math_temp (16);
C_FLAG <= math_temp (16) xor (not math_temp(16));
A_REG <= math_temp(15 downto 0);
math_done <= '1';
elsif math_temp /= "ZZZZZZZZZZZZZZZZZ" then
Z <= '0';
N <= math_temp (15);
V <= math_temp (16);
C_FLAG <= math_temp (16) xor (not math_temp(16));
A_REG <= math_temp(15 downto 0);
math_done <= '1';
end if;
-- AND
elsif op_code = X"2D" or
op_code = X"3E" or
op_code = X"39" or
op_code = X"2F" or
op_code = X"3F" or
op_code = X"25" or
op_code = X"23" or
op_code = X"36" or
op_code = X"32" or
op_code = X"27" or
op_code = X"33" or
op_code = X"91" or
op_code = X"31" or
op_code = X"37" or
op_code = X"29" then
math_temp := '0' & ( A_REG and requested_values(15 downto 0));
if math_temp = "00000000000000000" then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
A_REG <= math_temp(15 downto 0 );
math_done <= '1';
-- ASL
elsif
op_code = X"0E" or
op_code = X"1E" or
op_code = X"06" or
op_code = X"16" then
math_temp := requested_values(15 downto 0) & '0';
C_FLAG <= requested_values(15);
store_back <= '1';
if math_temp(15 downto 0) = "0000000000000000" then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
math_done <= '1';
elsif op_code = X"0A" then
math_temp := A_REG( 15 downto 0) & '0';
C_FLAG <= A_REG(15);
if math_temp(15 downto 0) = ("0000000000000000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
A_REG <= math_temp(15 downto 0);
math_done <= '1';
-- CMP
elsif
op_code = X"CD" or
op_code = X"DD" or
op_code = X"D9" or
op_code = X"CF" or
op_code = X"DF" or
op_code = X"C5" or
op_code = X"C3" or
op_code = X"D5" or
op_code = X"D2" or
op_code = X"C7" or
op_code = X"D3" or
op_code = X"C1" or
op_code = X"D1" or
op_code = X"D7" or
op_code = X"C9" then
math_temp := A_REG - ('0' & requested_values(15 downto 0));
if (A_REG < requested_values) then
C_FLAG <= '0';
else
C_FLAG <= '1';
end if;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
math_done <= '1';
-- CPX
elsif
op_code = X"EC" or
op_code = X"E4" or
op_code = X"E0" then
math_temp := X_REG - ('0' & requested_values(15 downto 0));
if (X_REG < requested_values) then
C_FLAG <= '0';
else
C_FLAG <= '1';
end if;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
math_done <= '1';
-- CPY
elsif
op_code = X"CC" or
op_code = X"C4" or
op_code = X"C0" then
math_temp := Y_REG - ('0' & requested_values(15 downto 0));
if (Y_REG < requested_values) then
C_FLAG <= '0';
else
C_FLAG <= '1';
end if;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
math_done <= '1';
-- DEX
elsif
op_code = X"CA" then
math_temp := '0' & X_REG - 1;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
X_REG <= math_temp(15 downto 0);
math_done <= '1';
-- DEY
elsif
op_code = X"88" then
math_temp := '0' & Y_REG - 1;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
Y_REG <= math_temp(15 downto 0);
math_done <= '1';
-- EOR
elsif
op_code = X"4D" or
op_code = X"5D" or
op_code = X"59" or
op_code = X"4F" or
op_code = X"5F" or
op_code = X"5D" or
op_code = X"45" or
op_code = X"43" or
op_code = X"55" or
op_code = X"52" or
op_code = X"47" or
op_code = X"53" or
op_code = X"41" or
op_code = X"51" or
op_code = X"57" or
op_code = X"49" then
math_temp := '0' & (requested_values(15 downto 0) xor A_REG);
if math_temp = ('0'&(X"0000")) then
Z <= '1';
else
Z <= '0';
end if;
N <= math_temp(15);
store_back <= '1';
math_done <= '1';
-- INX
elsif
op_code = X"E8" then
math_temp := '0' & X_REG + 1;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
X_REG <= math_temp(15 downto 0);
math_done <= '1';
-- INY
elsif
op_code = X"C8" then
math_temp := '0' & Y_REG + 1;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
Y_REG <= math_temp(15 downto 0);
math_done <= '1';
-- LSR
elsif
op_code = X"4A" then
math_temp := '0' & A_REG;
N <= '0';
C_FLAG <= A_REG(0);
if math_temp = ('0' & X"0000") then
Z <= '0';
else
Z <= '1';
end if;
A_REG <= math_temp (16 downto 1);
math_done <= '1';
elsif
op_code = X"4E" or
op_code = X"5E" or
op_code = X"46" or
op_code = X"56" then
math_temp := '0' & requested_values(15 downto 0);
store_back <= '1';
N <= '0';
C_FLAG <= requested_values(0);
if math_temp = ('0' & X"0000") then
Z <= '0';
else
Z <= '1';
end if;
math_done <= '1';
-- ORA
elsif
op_code = X"0D" or
op_code = X"1D" or
op_code = X"19" or
op_code = X"0F" or
op_code = X"1F" or
op_code = X"05" or
op_code = X"03" or
op_code = X"15" or
op_code = X"12" or
op_code = X"07" or
op_code = X"13" or
op_code = X"01" or
op_code = X"11" or
op_code = X"17" or
op_code = X"09" then
math_temp := '0' & (requested_values(15 downto 0) or A_REG);
A_REG <= math_temp(15 downto 0);
if math_temp = ('0' & X"0000") then
Z <= '1';
else
Z <= '0';
end if;
N <= math_temp(15);
store_back <= '1';
math_done <= '1';
-- ROL
elsif
op_code = X"2A" then
math_temp := A_REG & C_FLAG;
C_FLAG <= A_REG (15);
N <= math_temp(15);
if math_temp(16 downto 1) = X"0000" then
Z <= '1';
else
Z <= '0';
end if;
A_REG <= math_temp (15 downto 0);
math_done <= '1';
elsif
op_code = X"2E" or
op_code = X"3E" or
op_code = X"26" or
op_code = X"36" then
math_temp := requested_values(15 downto 0) & C_FLAG;
C_FLAG <= A_REG (15);
N <= math_temp(15);
store_back <= '1';
if math_temp(16 downto 1) = (X"0000") then
Z <= '1';
else
Z <= '0';
end if;
math_done <= '1';
-- ROR
elsif
op_code = X"6A" then
math_temp := C_FLAG & A_REG;
C_FLAG <= A_REG (0);
N <= math_temp(15);
if math_temp(16 downto 1) = (X"0000") then
Z <= '1';
else
Z <= '0';
end if;
A_REG <= math_temp (16 downto 1);
math_done <= '1';
elsif
op_code = X"6E" or
op_code = X"7E" or
op_code = X"66" or
op_code = X"76" then
math_temp := C_FLAG & requested_values(15 downto 0) ;
C_FLAG <= requested_values (0);
N <= math_temp(15);
store_back <= '1';
if math_temp(16 downto 1) = (X"0000") then
Z <= '1';
else
Z <= '0';
end if;
math_done <= '1';
-- SBC
elsif
op_code = X"ED" or
op_code = X"FD" or
op_code = X"F9" or
op_code = X"FF" or
op_code = X"E5" or
op_code = X"E3" or
op_code = X"F5" or
op_code = X"F2" or
op_code = X"E7" or
op_code = X"F3" or
op_code = X"E1" or
op_code = X"F1" or
op_code = X"F7" or
op_code = X"E9" then
math_temp := A_REG - ('0' & requested_values(15 downto 0)) - ( ('0' & zeros) & C_FLAG);
if ((math_temp = ('0' & X"0000")) or (math_temp = "10000000000000000")) then
Z <= '1';
N <= math_temp (15);
V <= math_temp (16);
C_FLAG <= math_temp (16) xor (not math_temp(16));
else
Z <= '0';
N <= math_temp (15);
V <= math_temp (16);
C_FLAG <= math_temp (16) xor (not math_temp(16));
end if;
A_REG <= math_temp(15 downto 0);
math_done <= '1';
end if;
if (store_back = '1') and (math_done = '1') then
write_back_value <= math_temp (15 downto 0);
write_back_location <= effective_memory_pointer;
state_machine_onehot <= "0000000001000000";
elsif math_done = '1' then
state_machine_onehot <= "0000000001000000";
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END OF ARITHMATIC STATE
--
--
-- START MEMORY MANIPULATION STATE
--
when sm =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sm;
end if;
-- DEC
if op_code = X"CE" or
op_code= X"DE" or
op_code= X"C6" or
op_code= X"D6" then
mem_temp := '0' & requested_values(15 downto 0) - 1 ;
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
write_back_value <= mem_temp(15 downto 0);
memory_done <= '1';
store_back <= '1';
elsif op_code = X"3A" then
mem_temp := '0' & A_REG - 1 ;
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
A_REG <= mem_temp(15 downto 0);
memory_done <= '1';
-- INC
elsif op_code= X"1A" then
mem_temp := '0' & A_REG + 1 ;
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
A_REG <= mem_temp(15 downto 0);
memory_done <= '1';
elsif op_code = X"EE" or
op_code= X"FE" or
op_code= X"E6" or
op_code= X"F6" then
mem_temp := '0' & requested_values(15 downto 0) + 1 ;
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
write_back_value <= mem_temp(15 downto 0);
memory_done <= '1';
store_back <= '1';
-- LDA
elsif op_code = X"AD" or
op_code= X"BD" or
op_code = X"B9" or
op_code = X"AF" or
op_code = X"BF" or
op_code = X"A5" or
op_code = X"A3" or
op_code = X"B5" or
op_code = X"B2" or
op_code = X"A7" or
op_code = X"B3" or
op_code = X"A1" or
op_code = X"B1" or
op_code = X"B7" then
mem_temp := '0' & requested_values(15 downto 0);
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
A_REG <= mem_temp(15 downto 0);
memory_done <= '1';
elsif op_code = X"A9" then
mem_temp := '0' & requested_values(15 downto 0);
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
A_REG <= mem_temp(15 downto 0);
memory_done <= '1';
-- LDX
elsif op_code = X"AE" or
op_code= X"BE" or
op_code= X"A6" or
op_code= X"B6" or
op_code= X"A2" then
mem_temp := '0' & requested_values(15 downto 0);
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
X_REG <= mem_temp(15 downto 0);
memory_done <= '1';
-- LDY
elsif op_code = X"AC" or
op_code= X"BC" or
op_code= X"A4" or
op_code= X"B4" or
op_code= X"A0" then
mem_temp := '0' & requested_values(15 downto 0);
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
Y_REG <= mem_temp(15 downto 0);
memory_done <= '1';
-- STA
elsif op_code = X"8D" or
op_code= X"9D" or
op_code= X"8F" or
op_code= X"9F" or
op_code= X"85" or
op_code= X"83" or
op_code= X"95" or
op_code= X"92" or
op_code= X"87" or
op_code= X"93" or
op_code= X"81" or
op_code= X"91" or
op_code= X"97" then
mem_temp := '0' & A_REG;
write_back_value <= mem_temp(15 downto 0);
store_back <= '1';
memory_done <= '1';
-- STX
elsif op_code = X"8E" or
op_code= X"86" or
op_code= X"96" then
mem_temp := '0' & X_REG;
write_back_value <= mem_temp(15 downto 0);
store_back <= '1';
memory_done <= '1';
-- STY
elsif op_code = X"8C" or
op_code= X"84" or
op_code= X"94" then
mem_temp :='0' & Y_REG;
write_back_value <= mem_temp(15 downto 0);
store_back <= '1';
memory_done <= '1';
end if;
if (memory_done = '1') and (store_back = '1') then
state_machine_onehot <= "0000000001000000";
write_back_location <= effective_memory_pointer;
elsif (memory_done = '1') and (store_back = '0') then
state_machine_onehot <= "0000000001000000";
store_back <= '0';
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END MEMORY MANIPULATION STATE
--
--
-- START PC MANIPULATION STATE
--
when sp =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sp;
end if;
-- BCC
if op_code = X"90" then
if C_FLAG = '0' then
PC <= PC + std_logic_vector((resize(signed(memory_pointer(7 downto 0)), 16)));
else
PC <= PC;
end if;
pc_done <= '1';
-- BEQ
elsif op_code = X"F0" then
if Z = '1' then
PC <= PC + std_logic_vector((resize(signed(memory_pointer(7 downto 0)), 16)));
else
PC <= PC;
end if;
pc_done <= '1';
-- BMI
elsif op_code = X"30" then
if N = '1' then
PC <= PC + std_logic_vector(resize(signed(memory_pointer(7 downto 0)), 16));
else
PC <= PC;
end if;
pc_done <= '1';
-- BNE
elsif op_code = X"D0" then
if Z = '0' then
PC <= PC + std_logic_vector(resize(signed(memory_pointer(7 downto 0)), 16));
else
PC <= PC;
end if;
pc_done <= '1';
-- BPL
elsif op_code = X"10" then
if N = '0' then
PC <= PC + std_logic_vector(resize(signed(memory_pointer(7 downto 0)), 16));
else
PC <= PC;
end if;
pc_done <= '1';
-- BVC
elsif op_code = X"50" then
if V = '0' then
PC <= PC + std_logic_vector(resize(signed(memory_pointer(7 downto 0)), 16));
else
PC <= PC;
end if;
pc_done <= '1';
-- BVS
elsif op_code = X"70" then
if V = '1' then
PC <= PC + std_logic_vector(resize(signed(memory_pointer(7 downto 0)), 16));
else
PC <= PC;
end if;
pc_done <= '1';
-- JMP
elsif
op_code = X"4C" then
PC <= effective_memory_pointer;
pc_done <= '1';
elsif
op_code = X"5C" then
PC <= requested_values(23 downto 0);
pc_done <= '1';
elsif
op_code = X"6C" or
op_code = X"7C" then
PC <= requested_values(23 downto 0);
pc_done <= '1';
-- JSR
elsif op_code = X"20" or
op_code = X"FC" then
write_back_value <= ProgramCntr;
write_back_bank <= PBR;
PC <= requested_values(23 downto 0);
push_to_stack <= '1';
pc_done <= '1';
-- RTS
elsif op_code = X"60" then
ProgramCntr <= requested_values(15 downto 0);
StackPointer <= StackPointer - 2;
pc_done <= '1';
end if;
if (pc_done = '1') then
state_machine_onehot <= "0000000001000000";
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END PC MANIPULATION STATE
--
--
-- START FLAGC MANIPULATION STATE
--
when sf =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sf;
end if;
-- BIT
if op_code = X"2C" or
op_code = X"3C" or
op_code = X"24" or
op_code = X"34" then
flag_temp := '0' & (A_REG and requested_values(15 downto 0));
if flag_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= flag_temp(15);
V <= flag_temp(14);
else
V <= flag_temp(14);
N <= flag_temp(15);
Z <= '0';
end if;
flag_done <= '1';
elsif op_code = X"89" then
flag_temp := '0' & (A_REG and requested_values(15 downto 0));
if flag_temp(15 downto 0) = (X"0000") then
Z <= '1';
else
Z <= '0';
end if;
flag_done <= '1';
-- CLC
elsif op_code = X"18" then
C_FLAG <= '0';
flag_done <= '1';
-- CLD
elsif op_code = X"D8" then
D_FLAG <= '0';
flag_done <= '1';
-- CLI
elsif op_code = X"58" then
I <= '0';
flag_done <= '1';
-- CLV
elsif op_code = X"B8" then
V <= '0';
flag_done <= '1';
-- SEC
elsif op_code = X"38" then
C_FLAG <= '1';
flag_done <= '1';
-- SED
elsif op_code = X"F8" then
D_FLAG <= '0';
flag_done <= '1';
-- SEI
elsif op_code = X"78" then
I <= '1';
flag_done <= '1';
end if;
if flag_done = '1' then
state_machine_onehot <= "0000000001000000";
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END FLAG MANIPULATION STATE
--
--
-- STACK MANIPULATION STATE
--
when ss =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= ss;
end if;
-- PHA
if op_code = X"48" then
StackPointer <= StackPointer + 2;
push_to_stack <= '1';
write_back_value <= A_REG;
stack_done <= '1';
-- PHP
elsif op_code = X"08" then
StackPointer <= StackPointer + 1;
push_to_stack <= '1';
write_back_value <= X"00" & P;
stack_done <= '1';
-- PLA
elsif op_code = X"68" then
StackPointer <= StackPointer - 2;
stack_temp := '0' & requested_values(15 downto 0);
if stack_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= stack_temp(15);
else
N <= stack_temp(15);
Z <= '0';
end if;
A_REG <= stack_temp(15 downto 0);
stack_done <= '1';
-- PLP
elsif op_code = X"28" then
StackPointer <= StackPointer - 1;
stack_temp := '0' & requested_values(15 downto 0);
if stack_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= stack_temp(15);
else
N <= stack_temp(15);
Z <= '0';
end if;
P <= stack_temp(7 downto 0);
stack_done <= '1';
end if;
if (stack_done = '1') and (store_back = '1') then
write_back_location <= effective_memory_pointer;
state_machine_onehot <= "0000000001000000";
elsif (stack_done = '1') then
state_machine_onehot <= "0000000001000000";
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END STACK MANIPULATION STATE
--
--
-- START NOP STATE
--
when sn =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sn;
end if;
state_machine_onehot <= "0000000001000000";
--
-- END NOP STATE
--
--
-- START EXCHANGE STATE
--
when se =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= se;
end if;
-- TAX
if op_code = X"AA" then
xfr_temp := '0' & A_REG;
if xfr_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= xfr_temp(15);
else
N <= xfr_temp(15);
Z <= '0';
end if;
X_REG <= xfr_temp(15 downto 0);
exchange_done <= '1';
-- TAY
elsif op_code = X"AB" then
xfr_temp := '0' & A_REG;
if xfr_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= xfr_temp(15);
else
N <= xfr_temp(15);
Z <= '0';
end if;
Y_REG <= xfr_temp(15 downto 0);
exchange_done <= '1';
-- TYA
elsif op_code = X"98" then
xfr_temp := '0' & Y_REG;
if xfr_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= xfr_temp(15);
else
N <= xfr_temp(15);
Z <= '0';
end if;
A_REG <= xfr_temp(15 downto 0);
exchange_done <= '1';
-- TSX
elsif op_code = X"BA" then
xfr_temp := '0' & StackPointer;
if xfr_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= xfr_temp(15);
else
N <= xfr_temp(15);
Z <= '0';
end if;
X_REG <= xfr_temp(15 downto 0);
exchange_done <= '1';
-- TXA
elsif
op_code = X"8A" then
xfr_temp := '0' & X_REG;
if xfr_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= xfr_temp(15);
else
N <= xfr_temp(15);
Z <= '0';
end if;
A_REG <= xfr_temp(15 downto 0);
exchange_done <= '1';
-- TXS
elsif
op_code = X"9A" then
xfr_temp := '0' & X_REG;
StackPointer <= xfr_temp(15 downto 0);
exchange_done <= '1';
end if;
if (exchange_done = '1') then
state_machine_onehot <= "0000000001000000";
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END EXCHANGE STATE
--
--
-- START INTERUPT STATE
--
when si =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= si;
end if;
-- RTI
if op_code = X"40" then
ProgramCntr <= requested_values(23 downto 8);
P <= requested_values(7 downto 0);
end if;
state_machine_onehot <= "0000000001000000";
--
-- END INTRRUPT STATE
--
when s6 =>
if (state_machine_onehot = "0000000010000000") and (ready_up = '1') then
state <= s0;
else
state <= state;
end if;
math_done <= '0';
memory_done <= '0';
pc_done <= '0';
flag_done <= '0';
stack_done <= '0';
exchange_done <= '0';
if (store_back = '1') then
READ_OUT <= write_back_value;
ADDRESS_OUT <= write_back_location;
store_back <= '0';
check_done := '1';
RW <= '1';
state_machine_onehot <= "0000000010000000";
elsif (push_to_stack = '1') then
read_out <= write_back_value;
read_out_bank <= write_back_bank;
address_out <= X"00" & StackPointer;
push_to_stack <= '0';
check_done := '1';
RW <= '1';
state_machine_onehot <= "0000000010000000";
else
check_done := '1';
state_machine_onehot <= "0000000010000000";
end if;
when others =>
state_machine_onehot <= "0000000000000010";
end case;
end if;
end process;
--
-- This process will look at the opcode
-- and determine the addressing mode of
-- the specific instruction being requested
-- and then pass it onto the adr_type vector.
--
Addressing_Mode:
process (addressing_on) is
begin
addressing_done <= '0';
if (addressing_on = '1') then
-- Refer to 65000 Programmers Manual for explanation
-- of addressing modes.
--
-- Symbol Addressing Mode Symbol Addressing Mode
-- 0 -> a absolute
-- 1 -> A_REG accumulator
-- 2 -> a,x absolute indexed with X
-- 3 -> a,y absolute indexed with Y_REG
-- 4 -> al absolute long
-- 5 -> al,x absolute long indexed
-- 6 -> (a) absolute indirect
-- 7 -> (a,x) absolute indexed indirect
-- 8 -> d direct
-- 9 -> d,s stack relative
-- 10 -> d,x direct indexed with x
-- 11 -> d,y direct indexed with y
-- 12 -> (d) direct indirect
-- 13 -> [d] direct indirect long
-- 14 -> (d,s),y stack relative indirect indexed
-- 15 -> (d,x) direct indexed indirect
-- 16 -> (d),y direct indirect indexed
-- 17 -> [d].y direct indirect long indexed
-- 18 -> i implied
-- 19 -> r program counter relative
-- 20 -> rl program counter relative long
-- 21 -> s stack
-- 22 -> xyc block move
-- 23 -> # immediate
--
--
case op_code is
when X"6d" | X"2d" | X"0e" | X"2c" | X"cd" | X"ec" | X"cc" | X"ce" | X"4d" | X"ee" | X"4c" | X"20" | X"ad" | X"ae" | X"ac" | X"4e" | X"0d" | X"2e" | X"6e" | X"ed" | X"8d" | X"8e" | X"8c" | X"9c" | X"1c" | X"0c" =>
adr_type <= 0;
when X"0a" | X"3A" | X"1a" | X"4a" | X"2a" | X"6a" | X"3b" | X"ba" | X"8a" | X"9a" | X"9b" | X"98" | X"bb" | X"cb" | X"42" | X"eb" | X"fb" =>
adr_type <= 1;
when X"7d" | X"3e" | X"1e" | X"3c" | X"dd" | X"de" | X"5d" | X"fe" | X"bd" | X"bc" | X"5e" | X"1d" | X"7e" | X"fd" | X"9d" | X"9e" =>
adr_type <= 2;
when X"6f" | X"2f" | X"cf" | X"4f" | X"5c" | X"22" | X"af" | X"0f" | X"8f" =>
adr_type <= 3;
when X"79" | X"39" | X"d9" | X"59" | X"b9" | X"be" | X"19" | X"f9" =>
adr_type <= 4;
when X"7f" | X"3f" | X"df" | X"5f" | X"bf" | X"1f" | X"ff" | X"9f" =>
adr_type <= 5;
when X"dc" | X"6c" =>
adr_type <= 6;
when X"7c" | X"fc" =>
adr_type <= 7;
when X"65" | X"25" | X"06" | X"24" | X"c5" | X"e4" | X"c4" | X"c6" | X"45" | X"e6" | X"a5" | X"a6" | X"a4" | X"46" | X"05" | X"26" | X"66" | X"e5" | X"85" | X"86" | X"84" | X"64" | X"14" | X"04" =>
adr_type <= 8;
when X"63" | X"23" | X"c3" | X"43" | X"a3" | X"03" | X"e3" | X"83" =>
adr_type <= 9;
when X"75" | X"36" | X"16" | X"34" | X"d5" | X"d6" | X"55" | X"f6" | X"b5" | X"b4" | X"56" | X"15" | X"76" | X"f5" | X"95" | X"94" | X"74" =>
adr_type <= 10;
when X"b6" | X"96" =>
adr_type <= 11;
when X"72" | X"32" | X"d2" | X"52" | X"b2" | X"12" | X"f2" | X"92" =>
adr_type <= 12;
when X"67" | X"27" | X"c7" | X"47" | X"a7" | X"07" | X"e7" | X"87" =>
adr_type <= 13;
when X"73" | X"33" | X"d3" | X"53" | X"b3" | X"13" | X"f3" | X"93" =>
adr_type <= 14;
when X"61" | X"c1" | X"41" | X"a1" | X"01" | X"e1" | X"81" =>
adr_type <= 15;
when X"71" | X"31" | X"d1" | X"51" | X"b1" | X"11" | X"f1" | X"91" =>
adr_type <= 16;
when X"77" | X"37" | X"d7" | X"57" | X"b7" | X"17" | X"f7" | X"97" =>
adr_type <= 17;
when X"18" | X"d8" | X"58" | X"b8" | X"ca" | X"88" | X"e8" | X"c8" | X"ea" | X"38" | X"f8" | X"78" | X"db" | X"aa" | X"5b" | X"1b" | X"7b" =>
adr_type <= 18;
when X"b0" | X"f0" | X"90" | X"d0" | X"10" | X"80" | X"50" | X"70" =>
adr_type <= 19;
when X"82" =>
adr_type <= 20;
when X"00" | X"02" | X"f4" | X"d4" | X"62" | X"48" | X"8b" | X"0b" | X"4b" | X"08" | X"da" | X"5a" | X"68" | X"ab" | X"2b" | X"28" | X"fa" | X"7a" | X"40" | X"6b" | X"60" =>
adr_type <= 21;
when X"54" | X"44" =>
adr_type <= 22;
when X"69" | X"29" | X"89" | X"c9" | X"e0" | X"c0" | X"49" | X"a9" | X"a2" | X"a0" | X"09" | X"c2" | X"e9" | X"e2" =>
adr_type <= 23;
when others =>
adr_type <= 0;
end case;
addressing_done <= '1';
end if;
end process;
--
-- This process reverses the byte order
-- of instruction arguments so that
-- a memory pointer or argument can
-- be precisely used
--
memory_pointer_calculation:
process (memory_calculate_on) is
begin
memory_calculate_done <= '0';
if memory_calculate_on = '1' then
case instruction_size is
when X"2" =>
memory_pointer <= X"0000" & chunk_pull (23 downto 16);
when X"3" =>
memory_pointer <= X"00" & chunk_pull (23 downto 16) & chunk_pull(15 downto 8);
when X"4" =>
memory_pointer <= chunk_pull (23 downto 16) & chunk_pull(15 downto 8) & chunk_pull (7 downto 0);
when others =>
memory_pointer <= (others => '0');
end case;
memory_calculate_done <= '1';
end if;
end process;
--
-- This process will decode the OPcode byte.
-- It will then assign instruction_info all relevent data.
--
opcode_info:
process (decode_on) is
begin
decode_done <= '0';
if reset = '1' then
instruction_info <= (others => '0');-- clear instruction info
elsif (decode_on = '1') then
--
--
-- intstruction_info syntax is
-- bytes + cycles + type
--
-- Flags (on reset) :
-- N V M X D I Z C_FLAG/E
-- P = * * 1 1 0 1 * */1
-- * = Not Initialized
-- STP and WAI instructions are cleared.
-- Type Table:
-- 0 -> Arithmatic
-- 1 -> PC
-- 2 -> Memory
-- 3 -> Coprocessor
-- 4 -> Flag
-- 5 -> Stack
-- 6 -> NOP (and non used)
-- 7 -> Exchange
-- 8 -> Interrupt
--
--
--
--
case op_code is
--
-- BRK (break)
-- pc+2 onto stack, processor status onto stack
-- Also set I flag = 1
--
-- !!!!!!!!!!!!! TODO: Implemented as a NOP for now due to issues with interrupts
-- !!!!!!!!!!!!!!!!!!!!!!!!!!! X"270" is now X"126"
when X"00" =>
instruction_info <= X"126";
-- ADC
-- The following are Add memory to accumulator with cary
-- A_REG + M + C_FLAG -> A_REG, C_FLAG
--
when X"69" =>
instruction_info <= X"220";
when X"65" =>
instruction_info <= X"230";
when X"75" =>
instruction_info <= X"240";
when X"6D" =>
instruction_info <= X"340";
when X"7D" =>
instruction_info <= X"340";
when X"79" =>
instruction_info <= X"340";
when X"61" =>
instruction_info <= X"260";
when X"71" =>
instruction_info <= X"250";
-- AND
-- The follwing are logical AND's with accumulator
-- A_REG and M -> A_REG
--
--
when X"29" =>
instruction_info <= X"220";
when X"25" =>
instruction_info <= X"230";
when X"35" =>
instruction_info <= X"240";
when X"2D" =>
instruction_info <= X"340";
when X"3D" =>
instruction_info <= X"340";
when X"39" =>
instruction_info <= X"340";
when X"21" =>
instruction_info <= X"260";
when X"31" =>
instruction_info <= X"250";
--
-- The following are ASL
-- left shift by one
-- memory or accumulator
--
when X"0A" =>
instruction_info <= X"120";
when X"06" =>
instruction_info <= X"250";
when X"16" =>
instruction_info <= X"260";
when X"0E" =>
instruction_info <= X"360";
when X"1E" =>
instruction_info <= X"370";
-- BCC
-- Branch on carry clear
-- when carry flag = 0, branch
-- * + 1 cycle if branch happens
when X"90" =>
instruction_info <= X"221";
-- BEQ
-- branch on zero flag set
-- * + 1 cycle if branch happens
when X"F0" =>
instruction_info <= X"221";
-- BIT
-- Accumulator AND'd with memory,
-- bit 7 of memory goes to Negative flag
-- bit 6 of memoyr goes to overflow flag
-- If A_REG and M = 0 then Z = 1 , else 0
when X"24" =>
instruction_info <= X"234";
when X"2C" =>
instruction_info <= X"344";
-- BMI
-- Branch On Negative Flag Set
-- * + 1 Cycle If Can Branch
when X"30" =>
instruction_info <= X"221";
-- BNE
-- Branch on zero flag not set
-- * + 1 cycle if can do
--
when X"D0" =>
instruction_info <= X"221";
-- BPL
-- Brnach when N flag not set.
-- * + 1 cycle if can do
--
when X"10" =>
instruction_info <= X"221";
-- BVC
-- Branch on V flag = 0
-- * +1 cycle if can do
when X"50" =>
instruction_info <= X"221";
-- BVS
-- Branch when V flag set
-- * + 1 cycle if can do
when X"70" =>
instruction_info <= X"221";
-- CLC
-- Clear the carry flag
--
when X"18" =>
instruction_info <= X"124";
-- CLD
-- Clear the decimal flag
--
when X"D8" =>
instruction_info <= X"124";
-- CLI
-- Clear interupt bit
--
when X"58" =>
instruction_info <= X"124";
-- CLV
-- Clear the overflow flag
--
when X"B8" =>
instruction_info <= X"124";
-- CMP
-- Compar memory and accumulator
-- Set N, Z, or C_FLAG flag accordingly
-- A_REG - M
--
when X"c9" =>
instruction_info <= X"220";
when X"c5" =>
instruction_info <= X"230";
when X"D5" =>
instruction_info <= X"240";
when X"DD" =>
instruction_info <= X"340";
when X"d9" =>
instruction_info <= X"340";
when X"c1" =>
instruction_info <= X"260";
when X"d1" =>
instruction_info <= X"250";
-- CPX
-- Compary memory and X reg
-- X - M and set N, Z, C_FLAG flags as needed
--
when X"E0" =>
instruction_info <= X"220";
when X"E4" =>
instruction_info <= X"230";
when X"EC" =>
instruction_info <= X"340";
-- CPY
-- Compary memory and Y_REG reg
-- Y_REG - M
-- Set N, Z, and C_FLAG flags as needed.
--
when X"C0" =>
instruction_info <= X"220";
when X"C4" =>
instruction_info <= X"230";
when X"cc" =>
instruction_info <= X"340";
-- DEC
-- Decrimeent memory by 1
-- M - 1 -> M
-- Use N & Z flags
when X"C6" =>
instruction_info <= X"252";
when X"D6" =>
instruction_info <= X"262";
when X"ce" =>
instruction_info <= X"362";
when X"de" =>
instruction_info <= X"372";
-- DEX
-- Decriment X reg by 1
-- X - 1 -> X
-- use N & Z flags
when X"CA" =>
instruction_info <= X"120";
-- DEY
-- Decriment Y_REG reg by 1
-- Y_REG - 1 -> Y_REG
-- N & Z flags
--
when X"88" =>
instruction_info <= X"120";
-- EOR
-- Acc XOR Mem -> Acc
-- N and Z flags
--
when X"49" =>
instruction_info <= X"220";
when X"45" =>
instruction_info <= X"230";
when X"55" =>
instruction_info <= X"240";
when X"4d" =>
instruction_info <= X"340";
when X"5d" =>
instruction_info <= X"340";
when X"59" =>
instruction_info <= X"340";
when X"41" =>
instruction_info <= X"260";
when X"51" =>
instruction_info <= X"250";
-- INC
-- Incriment memory by one
-- M + 1 -> M
-- N & Z flags
--
when X"E6" =>
instruction_info <= X"252";
when X"F6" =>
instruction_info <= X"262";
when X"ee" =>
instruction_info <= X"362";
when X"fe" =>
instruction_info <= X"372";
-- INX
-- Incriment X by one
-- X + 1 -> X
-- N & Z flags
--
when X"e8" =>
instruction_info <= X"120";
-- INY
-- Incriment Y_REG by one
-- Y_REG + 1 -> Y_REG
-- N & Z flags
--
when X"c8" =>
instruction_info <= X"120";
--
--
-- JMP
-- JUMP INSTRUCTIONS
--=======================================================================
-- JMP
-- Jump to location
-- PC + 1 -> PCL
-- PC + 2 -> PCH
--JMP absolute
--take contents of memory location
--1 byte from opcode and store into
--PC LOW, then take the very next byte
--and store into PC HIGH
-- REVERSE BYTE ORDER AND MAKE NEW PC
when X"4c" =>
instruction_info <= X"331";
--JMP indirect
-- starts out the same as above, but
-- instead of getting the opcode at the new PC,
-- a new PC is again fetched in the same way.
-- making this a jump to a jump.
when X"6c" =>
instruction_info <= X"351";
--=======================================================================
--
--
--
--
-- JSR
-- Jump to subroutine
-- PC + 2 -> stack
-- PC + 1 -> PCL
-- PC + 2 -> PCH
--
when X"20" =>
instruction_info <= X"361";
-- LDA
-- Load accumulator with memory
-- M -> A_REG
-- N & Z flags
when X"a9" =>
instruction_info <= X"222";
when X"a5" =>
instruction_info <= X"232";
when X"b5" =>
instruction_info <= X"242";
when X"ad" =>
instruction_info <= X"342";
when X"bd" =>
instruction_info <= X"342";
when X"b9" =>
instruction_info <= X"342";
when X"a1" =>
instruction_info <= X"262";
when X"b1" =>
instruction_info <= X"252";
-- LDX
-- Load X with memory
-- M -> X
-- N & Z flags
--
when X"a2" =>
instruction_info <= X"222";
when X"a6" =>
instruction_info <= X"232";
when X"b6" =>
instruction_info <= X"242";
when X"ae" =>
instruction_info <= X"342";
when X"be" =>
instruction_info <= X"342";
-- LDY
-- Load Y_REG with memory
-- M -> Y_REG
-- N & Z Flags
--
when X"a0" =>
instruction_info <= X"222";
when X"a4" =>
instruction_info <= X"232";
when X"b4" =>
instruction_info <= X"242";
when X"ac" =>
instruction_info <= X"342";
when X"bc" =>
instruction_info <= X"342";
-- LSR
-- Right shift one bit
-- 0 -> [bits] -> C_FLAG
-- C_FLAG & Z flag, N flag zerod
--
when X"4a" =>
instruction_info <= X"120";
when X"46" =>
instruction_info <= X"250";
when X"56" =>
instruction_info <= X"260";
when X"4e" =>
instruction_info <= X"360";
when X"5e" =>
instruction_info <= X"370";
-- NOP
-- No operation
--
when X"ea" =>
instruction_info <= X"126";
-- ORA
-- Or with accumulator
-- A_REG (or) M -> A_REG
-- N & Z flags
--
when X"09" =>
instruction_info <= X"220";
when X"05" =>
instruction_info <= X"230";
when X"15" =>
instruction_info <= X"240";
when X"0d" =>
instruction_info <= X"340";
when X"1d" =>
instruction_info <= X"340";
when X"19" =>
instruction_info <= X"340";
when X"01" =>
instruction_info <= X"260";
when X"11" =>
instruction_info <= X"250";
-- PHA
-- Push accumuator to stack
-- A_REG -> STACK
-- NO FLAGS
when X"48" =>
instruction_info <= X"135";
-- PHP
-- Push processor status on stack
-- P -> STACK
when X"08" =>
instruction_info <= X"135";
-- PLA
-- Pull accumulator from stack
-- STACK -> A_REG
-- N & Z flags
--
when X"68" =>
instruction_info <= X"145";
-- PLP
-- Pull processor status from stack
-- STACK -> P
-- ALL FLAGS CAN CHANGE
when X"28" =>
instruction_info <= X"145";
-- ROL
-- Rotate one bit left
-- [bit 7] -> C_FLAG FLAG
-- [ <- bits 6 - 0] [C_FLAG FLAG (becomes 0 bit)]
-- N & Z & C_FLAG FLAGS
--
when X"2a" =>
instruction_info <= X"120";
when X"26" =>
instruction_info <= X"250";
when X"36" =>
instruction_info <= X"260";
when X"2e" =>
instruction_info <= X"360";
when X"3e" =>
instruction_info <= X"270";
-- ROR
-- Rotate right one
-- [C_FLAG FLAG -> bit 7] [bits 7 - 1 ] [bit 0 becomes C_FLAG flag]
-- N & Z & C_FLAG
--
when X"6a" =>
instruction_info <= X"120";
when X"66" =>
instruction_info <= X"250";
when X"76" =>
instruction_info <= X"260";
when X"6e" =>
instruction_info <= X"360";
when X"7e" =>
instruction_info <= X"370";
-- RTI
-- Return from Interrupt
-- STACK -> P
-- STACK -> PC
-- FLAGS FROM STACK
--
when X"40" =>
instruction_info <= X"168";
-- RTS
-- Reutrn from subroutine
-- STACK -> PC
-- PC + 1 -> PC
-- NO FLAGS
--
when X"60" =>
instruction_info <= X"161";
-- SBC
-- Subtract memory from accumulator w/ borrow
-- A_REG - M - (not) C_FLAG -> Accumulator
-- N & Z & C_FLAG & V Flags
--
when X"e9" =>
instruction_info <= X"220";
when X"e5" =>
instruction_info <= X"230";
when X"f5" =>
instruction_info <= X"240";
when X"ed" =>
instruction_info <= X"340";
when X"fd" =>
instruction_info <= X"340";
when X"f9" =>
instruction_info <= X"340";
when X"e1" =>
instruction_info <= X"260";
when X"f1" =>
instruction_info <= X"250";
-- SEC
-- Set carry flag
-- 1 -> C_FLAG
-- C_FLAG Flag
--
when X"38" =>
instruction_info <= X"124";
-- SED
-- Set decimal flag
-- 1 -> D
-- D flag
--
when X"f8" =>
instruction_info <= X"124";
-- SEI
-- Set interrupt disable flag
-- 1 -> I
-- I FLAG
when X"78" =>
instruction_info <= X"124";
-- STA
-- Store accumulator in memory
-- A_REG -> M
-- no flags
--
when X"85" =>
instruction_info <= X"232";
when X"95" =>
instruction_info <= X"242";
when X"8d" =>
instruction_info <= X"342";
when X"9d" =>
instruction_info <= X"352";
when X"99" =>
instruction_info <= X"352";
when X"81" =>
instruction_info <= X"262";
when X"91" =>
instruction_info <= X"262";
-- STX
-- Store X in memory
-- X -> M
--
when X"86" =>
instruction_info <= X"232";
when X"96" =>
instruction_info <= X"242";
when X"8e" =>
instruction_info <= X"342";
-- STY
-- Store y in memory
-- Y_REG -> M
--
when X"84" =>
instruction_info <= X"232";
when X"94" =>
instruction_info <= X"242";
when X"8c" =>
instruction_info <= X"342";
-- TAX
-- Transfer A_REG to X
-- A_REG -> X
-- N & Z
--
when X"AA" =>
instruction_info <= X"127";
-- TAY
-- X-fer A_REG to Y_REG
-- A_REG -> Y_REG
-- N & Z
--
when X"a8" =>
instruction_info <= X"127";
-- TYA
-- X-fer Y_REG to A_REG
-- Y_REG -> A_REG
-- N & Z
--
when X"98" =>
instruction_info <= X"127";
-- TSX
-- X-fer stack pointer to X
-- S -> X
-- N & Z
--
when X"ba" =>
instruction_info <= X"127";
-- TXA
-- X-fer X to Accumulator
-- X -> A_REG
-- N & Z
--
when X"8A" =>
instruction_info <= X"127";
-- TXS
-- X-fer X to stack pointer
-- X -> S
--
when X"9a" =>
instruction_info <= X"127";
-- XBA
-- Exchange B & A_REG Accumulators
-- A_REG <-> B
-- Remeber that A_REG is the lower 8 bits of C_FLAG
-- and that B is the upper 8 bits of C_FLAG
--
when X"EB" =>
instruction_info <= X"137";
-- XCE
-- Exchange Carry and Emulation flags
-- E Flag <-> C_FLAG Flag
-- Even though this manipulates
-- flag bits, note that it is
-- EXCHANGE type instruction for
-- this implementation.
--
when X"FB" =>
instruction_info <= X"127";
--
-- All other instructions are NOP's
--
when others =>
instruction_info <= X"126";
end case;
decode_done <= '1';
end if;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Company: Open Source
-- Engineer: Steven T. Seppala ( rad- )
--
-- Create Date: 01/26/2016 03:26:56 PM
-- Design Name:
-- Module Name: 65C816 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
-- This is a soft-core implementation of a 65C816. There will be initally 92
--of the 256 OpCodes useable. Please refer to DOC 1A for reference.
--
-- Dependencies:
-- For testing purposes there will be an AXI interface into this module.
--This should be provided with all the source HDL.
--If this module is being used in conjunction with another module and there is no need
--to access or view the inner workings of this module, no other dependancies occour.
--
-- Revision: V .1 -- 26 Jan 2016 STS
--
-- Revision 0.01 - File Created
-- Additional Comments:
-- The SNES CPU (65c816) uses little endian.
-- Revision 0.5 - Decode Table and Addressing Modes
-- The decode process and addressing mode assigning table
-- processes have been crated.
-- NOTE : Memory accesses will be passed from this
-- module to a C_FLAG program for reading/writing.
-- Revision 1.0 - 18 Feb 2016
-- Main Modules finished.
-- Revision 1.1 - 3 March 2016
-- Tests passed. Main is now implemented.
--
----------------------------------------------------------------------------------
-- ██████ ███████ ███████ ████████
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--░░██ ██░░██ ██ ░██ ░░██ ░██
-- ░░██████ ░░███████ ░██ ░░██░████████
-- ░░░░░░ ░░░░░░░ ░░ ░░ ░░░░░░░░
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--░██░██ ██░██ ██░░░░░██ ░██░░░░██ ░██ ░██░██ ░██░░░░░
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.SNES65816func.all;
entity Soft_65C816 is
Port ( clk :in STD_LOGIC; -- Main CLK for system
tru_clk :in std_logic; -- True clk for system
reset :in std_logic; -- Reset Signal
Addr_Bus :out STD_LOGIC_VECTOR (23 downto 0);-- Address Bus
D_BUS :in STD_LOGIC_VECTOR (31 downto 0);-- Data Bus IN
D_BUS_out :out STD_LOGIC_VECTOR (23 downto 0);-- Data Bus OUT
EMULATION_SELECT :out STD_LOGIC; -- Emulation Bit
RDY :out STD_LOGIC;
DATA_RDY :in STD_LOGIC;
REG_A :out std_logic_vector(15 downto 0);
REG_X :out std_logic_vector(15 downto 0);
REG_Y :out std_logic_vector(15 downto 0);
REG_SP :out std_logic_vector(15 downto 0);
REG_PC :out std_logic_vector(15 downto 0);
REG_Proc :out std_logic_vector(7 downto 0);
REG_DBR :out std_logic_vector(7 downto 0);
state_machine :out std_logic_vector(15 downto 0);
RW :out std_logic ; -- Read or write bit
VPB :out STD_LOGIC);
end Soft_65C816;
architecture Behavioral of Soft_65C816 is
--state machine states
type state_machine_states is (s0, s1, s2, s3, s4, s5 , sc, sa, sm, sp, sf, ss, sn, se, si, calculate_memory_pointer, s6);
signal state : state_machine_states;
--One hot sounter for state machine location/control
signal state_machine_onehot : std_logic_vector (15 downto 0);
--chunk pull vector
signal chunk_pull : std_logic_vector (31 downto 0);
--vector with info about the opcode
signal instruction_info : std_logic_vector (11 downto 0);
signal op_code : std_logic_vector (7 downto 0);
-- This will have the instructions arguments assigned to it.
signal instrction_args : std_logic_vector (31 downto 0);
-- This signal must be run with a 3.58 MHz CLK.
-- It is just a counter, but it must count at 3.58 MHz.
signal tru_cpu : std_logic_vector (3 downto 0);
-- This is essentially a latch enable,
-- it will count for as many cycles as the
-- operation would take on a true 65816
signal tru_clk_cntr : std_logic_vector(3 downto 0);
-- This will hold the instruction size, so the PC can correctly
-- be incrimented.
signal instruction_size : std_logic_vector (3 downto 0);
-- Memory pointer for pulling and pushing values
signal memory_pointer : std_logic_vector ( 23 downto 0);
-- This signal holds the values from the memory locations
-- requested.
signal requested_values : std_logic_vector (31 downto 0);
-- This will hold type info so the correct
-- execution state can be determined.
signal type_info : std_logic_vector (3 downto 0);
--
-- Process Control Signals
--
signal addressing_done, addressing_on, decode_on, decode_done, memory_calculate_done, memory_calculate_on : STD_LOGIC;
signal memory_done:std_logic;
signal math_done : std_logic;
signal pc_done : std_logic;
signal flag_done : std_logic;
signal store_back: std_logic;
signal push_to_stack : std_logic;
signal ready_up : std_logic;
signal stack_done: std_logic;
signal exchange_done: std_logic;
signal data_enable : std_logic;
--
-- REGISTER DECLARATIONS
--
-- Program Counter : PC
-- PC Bank Register : PBR
signal PC : std_logic_vector (23 downto 0);
alias PBR : std_logic_vector (7 downto 0) is PC (23 downto 16);
alias ProgramCntr : std_logic_vector (15 downto 0) is PC (15 downto 0);
-- Accumulator : A_REG
-- Direct Page Register: DP
-- Stack Pointer : SP
-- X & Y_REG Are Index Registers
signal A_REG, DP, StackPointer, X_REG, Y_REG : std_logic_vector ( 15 downto 0);
-- StackPointer is vaid from 00:0000 to 00:FFFF
-- Processor Status : P
-- Data Bank Register : DBR
signal P : std_logic_vector ( 7 downto 0);
signal DBR : std_logic_vector ( 7 downto 0);
alias N : STD_LOGIC is P(7); -- Negative Flag
alias V : STD_LOGIC is P(6); -- Overflow Flag
alias M : STD_LOGIC is P(5); -- Memory Select
alias X_FLAG : STD_LOGIC is P(4); -- Index Register
alias D_FLAG : STD_LOGIC is P(3); -- Decimal Mode
alias I : STD_LOGIC is P(2); -- IRQ Disable
alias Z : STD_LOGIC is P(1); -- Zero Result
alias C_FLAG : STD_LOGIC is P(0); -- Carry Flag / Emulation Mode
--
-- END REGISTER DECLARATIONS
--
--
-- Memory signals
--
signal effective_memory_pointer : std_logic_vector (23 downto 0);
signal write_back_location : std_logic_vector (23 downto 0);
signal write_back_value : std_logic_vector(15 downto 0);
signal write_back_bank : std_logic_vector(7 downto 0);
signal adr_type : integer range 0 to 25;
signal push_val : std_logic_vector(23 downto 0);
signal read_out : std_logic_vector(15 downto 0);
signal read_out_bank : std_logic_vector(7 downto 0);
signal address_out : std_logic_vector(23 downto 0);
--
--
-- Constant Signals
--
--
constant zeros : std_logic_vector (15 downto 1) := ( B"0000_0000_0000_000");
begin
state_machine <= state_machine_onehot;
D_BUS_out <= read_out_bank & read_out;
Addr_Bus<= address_out;
REG_A <= A_REG;
REG_X <= X_REG;
REG_Y <= Y_REG;
REG_SP <= StackPointer;
REG_PC <= ProgramCntr;
REG_Proc <= P;
REG_DBR <= DBR;
--
-- This is the true CPU clock for the processor
-- It runs at a multiple of 3.58 MHz and allows s6 to continue
-- to s1.
slow_clock:
process(tru_clk, clk, reset) is
begin
if reset = '1' then
tru_clk_cntr <= (others => '0');
ready_up <= '0';
elsif rising_edge(clk) then
if (tru_clk_cntr = tru_cpu) and (tru_clk = '1') then
ready_up <= '1' ;
end if;
end if;
if falling_edge(clk) then
if ready_up ='1' then
tru_clk_cntr <= (others => '0');
end if;
end if;
if rising_edge(tru_clk) then
tru_clk_cntr <= std_logic_vector(unsigned(tru_clk_cntr) + 1);
end if;
end process;
--
-- This is a 16 bit microprocessor with variable length instructions, the PC will
-- depend on the current instruction size.
-- Thus the PC will get
--
--
state_machine_process:
process (clk, reset) is
variable effective_memeory_pointer_temp : std_logic_vector (23 downto 0);
variable pointer_calculation_done : std_logic;
variable math_temp : std_logic_vector (16 downto 0);
variable stack_temp : std_logic_vector (16 downto 0);
variable xfr_temp : std_logic_vector (16 downto 0);
variable mem_temp : std_logic_vector (16 downto 0);
variable flag_temp : std_logic_vector (16 downto 0);
variable check_done : std_logic;
begin
if reset = '1' then
--TODO: RESET
state <= s0; -- reset to s0
chunk_pull <= (others => 'Z'); -- clear chunk pull
op_code <= (others => 'Z'); -- set opcode hi-Z
StackPointer <= X"0100"; -- Initialize Stack pointer
A_REG <= (others => '0');
X_REG <= (others => '0');
Y_REG <= (others => '0');
PC <= (others => '0');
DBR <= X"00";
DP <= X"0000";
N <= '0';
V <= '0';
M <= '1';
X_FLAG <= '1';
D_FLAG <= '0';
I <= '1';
Z <= '0';
C_FLAG <= '1'; -- This is the emulation flag on reset.
elsif rising_edge(clk) then
case state is
when s0 =>
if state_machine_onehot = "0000000000000001" then
state <= s1;
else
state <= s0;
end if;
state_machine_onehot <= "0000000000000001";
write_back_value <=X"0000";
write_back_bank <=X"00";
address_out <=PC;
check_done := '0';
rdy <= '1';
RW <= '0';
when s1 =>
if state_machine_onehot = "0000000000000010" then
state <= s2;
else
state <= s1;
end if;
data_enable <= '1';
if data_rdy ='0' and chunk_pull /= "ZZZZZZZZZZZZZZZZZ" then
chunk_pull <= D_BUS;
state_machine_onehot <= "0000000000000010";
rdy <= '0';
end if;
when s2 =>
if ((addressing_done = '1') and (decode_done = '1') and (state_machine_onehot = "0000000000000100")) then
state <= s3;
else
state <= s2;
end if;
addressing_on <= '1';
decode_on <= '1';
-- This should send the OPCode from chunkpull
-- to the opcode_info process, which inturn
-- will give us everything we need to know about how
-- to execute the instruction.
if data_enable = '1' then
op_code <= chunk_pull(31 downto 24);
state_machine_onehot <= "0000000000000100";
data_enable <= '0';
end if;
when s3 =>
if state_machine_onehot = "0000000000001000" then
state <= s4;
else
state <= s3;
end if;
data_enable <= '1';
addressing_on <= '0';
decode_on <= '0';
instruction_size <= instruction_info(11 downto 8);
tru_cpu <= instruction_info(7 downto 4);
type_info <= instruction_info( 3 downto 0);
state_machine_onehot <= "0000000000001000";
when s4 =>
if ((state_machine_onehot = "0000000000010000") and (memory_calculate_done = '1'))then
state <= calculate_memory_pointer;
else
state <= s4;
end if;
PC <= std_logic_vector(unsigned(PC) + unsigned(instruction_size));
state_machine_onehot <= "0000000000010000";
memory_calculate_on <= '1';
when calculate_memory_pointer =>
if pointer_calculation_done = '1' then
state <= s5;
end if;
memory_calculate_on <= '0';
case adr_type is
when 0 =>
if ((op_code = X"20") or (op_code = X"4c")) then
effective_memory_pointer(23 downto 16) <= PBR;
effective_memory_pointer(15 downto 0) <= memory_pointer(15 downto 0);
else
effective_memory_pointer(23 downto 16) <= DBR;
effective_memory_pointer(15 downto 0) <= memory_pointer(15 downto 0);
end if;
pointer_calculation_done := '1';
when 1 =>
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
when 2 =>
effective_memeory_pointer_temp(23 downto 16) := DBR;
effective_memeory_pointer_temp(15 downto 0) := memory_pointer(15 downto 0);
effective_memory_pointer <= std_logic_vector(unsigned(effective_memeory_pointer_temp) + unsigned(X_REG));
pointer_calculation_done := '1';
when 3 =>
effective_memeory_pointer_temp(23 downto 16) := DBR;
effective_memeory_pointer_temp(15 downto 0) := memory_pointer(15 downto 0);
effective_memory_pointer <= std_logic_vector(unsigned(effective_memeory_pointer_temp) + unsigned(Y_REG));
pointer_calculation_done := '1';
when 4 =>
effective_memory_pointer <= memory_pointer;
pointer_calculation_done := '1';
when 5 =>
effective_memory_pointer <= std_logic_vector(unsigned(memory_pointer) + unsigned(X_REG));
pointer_calculation_done := '1';
when 6 =>
effective_memory_pointer(23 downto 16) <= PBR;
effective_memory_pointer(15 downto 0) <= memory_pointer(15 downto 0);
pointer_calculation_done := '1';
when 7 =>
effective_memory_pointer(23 downto 16) <= PBR;
effective_memory_pointer(15 downto 0) <= memory_pointer(15 downto 0) + X_REG;
pointer_calculation_done := '1';
when 8 =>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 9 =>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= StackPointer + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 10=>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= DP + X_REG + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 11=>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= DP + Y_REG + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 12=>
effective_memory_pointer(23 downto 16) <= DBR;
effective_memory_pointer(15 downto 0) <= DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 13=>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 14=>
effective_memory_pointer(23 downto 16) <= DBR;
effective_memory_pointer(15 downto 0) <= StackPointer + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 15=>
effective_memory_pointer(23 downto 16) <= DBR;
effective_memory_pointer(15 downto 0) <= X_REG + DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 16=>
effective_memory_pointer(23 downto 16) <= DBR;
effective_memory_pointer(15 downto 0) <= DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 17=>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 18=>
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
when 19=>
-- These program counter relative operations are calculated in the
-- PC state of execution.
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
when 20=>
-- These program counter relative operations are calculated in the
-- PC state of execution.
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
when 21=>
-- Stack Operations are handled in the stack state or where neccicary
effective_memory_pointer <= X"00" & StackPointer;
pointer_calculation_done := '1';
when 22=>
-- Block operations are not implemented yet
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
when 23 =>
requested_values <= X"00" & memory_pointer;
pointer_calculation_done := '1';
when others =>
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
end case;
when s5 =>
pointer_calculation_done := '0';
state_machine_onehot <= "0000000000100000";
if state_machine_onehot = "0000000000100000" then
-- Go to fan out based on type info,
-- if type info is not 0 - 8, then count it
-- as a NOP
--
if type_info = X"0" then
state <= sa;
elsif type_info = X"1" then
state <= sp;
elsif type_info = X"2" then
state <= sm;
elsif type_info = X"3" then
state <= sc;
elsif type_info = X"4" then
state <= sf;
elsif type_info = X"5" then
state <= ss;
elsif type_info = X"6" then
state <= sn;
elsif type_info = X"7" then
state <= se;
elsif type_info = X"8" then
state <= si;
-- if state can not be defined treat it as a NOP
else
state <= sn;
end if;
end if;
when sc =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sc;
end if;
state_machine_onehot <= "0000000001000000";
--
-- Arithmatic State Start
--
when sa =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sa;
end if;
-- ADC
if op_code = X"6D" or
op_code = X"7D" or
op_code = X"79" or
op_code = X"6F" or
op_code = X"7F" or
op_code = X"17" or
op_code = X"65" or
op_code = X"63" or
op_code = X"75" or
op_code = X"72" or
op_code = X"67" or
op_code = X"73" or
op_code = X"61" or
op_code = X"71" or
op_code = X"77" or
op_code = X"69" then
math_temp := ('0' & requested_values(15 downto 0)) + A_REG + ( zeros & C_FLAG);
if ((math_temp = "00000000000000000" ) or (math_temp = "10000000000000000")) then
Z <= '1';
N <= math_temp (15);
V <= math_temp (16);
C_FLAG <= math_temp (16) xor (not math_temp(16));
A_REG <= math_temp(15 downto 0);
math_done <= '1';
elsif math_temp /= "ZZZZZZZZZZZZZZZZZ" then
Z <= '0';
N <= math_temp (15);
V <= math_temp (16);
C_FLAG <= math_temp (16) xor (not math_temp(16));
A_REG <= math_temp(15 downto 0);
math_done <= '1';
end if;
-- AND
elsif op_code = X"2D" or
op_code = X"3E" or
op_code = X"39" or
op_code = X"2F" or
op_code = X"3F" or
op_code = X"25" or
op_code = X"23" or
op_code = X"36" or
op_code = X"32" or
op_code = X"27" or
op_code = X"33" or
op_code = X"91" or
op_code = X"31" or
op_code = X"37" or
op_code = X"29" then
math_temp := '0' & ( A_REG and requested_values(15 downto 0));
if math_temp = "00000000000000000" then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
A_REG <= math_temp(15 downto 0 );
math_done <= '1';
-- ASL
elsif
op_code = X"0E" or
op_code = X"1E" or
op_code = X"06" or
op_code = X"16" then
math_temp := requested_values(15 downto 0) & '0';
C_FLAG <= requested_values(15);
store_back <= '1';
if math_temp(15 downto 0) = "0000000000000000" then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
math_done <= '1';
elsif op_code = X"0A" then
math_temp := A_REG( 15 downto 0) & '0';
C_FLAG <= A_REG(15);
if math_temp(15 downto 0) = ("0000000000000000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
A_REG <= math_temp(15 downto 0);
math_done <= '1';
-- CMP
elsif
op_code = X"CD" or
op_code = X"DD" or
op_code = X"D9" or
op_code = X"CF" or
op_code = X"DF" or
op_code = X"C5" or
op_code = X"C3" or
op_code = X"D5" or
op_code = X"D2" or
op_code = X"C7" or
op_code = X"D3" or
op_code = X"C1" or
op_code = X"D1" or
op_code = X"D7" or
op_code = X"C9" then
math_temp := A_REG - ('0' & requested_values(15 downto 0));
if (A_REG < requested_values) then
C_FLAG <= '0';
else
C_FLAG <= '1';
end if;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
math_done <= '1';
-- CPX
elsif
op_code = X"EC" or
op_code = X"E4" or
op_code = X"E0" then
math_temp := X_REG - ('0' & requested_values(15 downto 0));
if (X_REG < requested_values) then
C_FLAG <= '0';
else
C_FLAG <= '1';
end if;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
math_done <= '1';
-- CPY
elsif
op_code = X"CC" or
op_code = X"C4" or
op_code = X"C0" then
math_temp := Y_REG - ('0' & requested_values(15 downto 0));
if (Y_REG < requested_values) then
C_FLAG <= '0';
else
C_FLAG <= '1';
end if;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
math_done <= '1';
-- DEX
elsif
op_code = X"CA" then
math_temp := '0' & X_REG - 1;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
X_REG <= math_temp(15 downto 0);
math_done <= '1';
-- DEY
elsif
op_code = X"88" then
math_temp := '0' & Y_REG - 1;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
Y_REG <= math_temp(15 downto 0);
math_done <= '1';
-- EOR
elsif
op_code = X"4D" or
op_code = X"5D" or
op_code = X"59" or
op_code = X"4F" or
op_code = X"5F" or
op_code = X"5D" or
op_code = X"45" or
op_code = X"43" or
op_code = X"55" or
op_code = X"52" or
op_code = X"47" or
op_code = X"53" or
op_code = X"41" or
op_code = X"51" or
op_code = X"57" or
op_code = X"49" then
math_temp := '0' & (requested_values(15 downto 0) xor A_REG);
if math_temp = ('0'&(X"0000")) then
Z <= '1';
else
Z <= '0';
end if;
N <= math_temp(15);
store_back <= '1';
math_done <= '1';
-- INX
elsif
op_code = X"E8" then
math_temp := '0' & X_REG + 1;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
X_REG <= math_temp(15 downto 0);
math_done <= '1';
-- INY
elsif
op_code = X"C8" then
math_temp := '0' & Y_REG + 1;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
Y_REG <= math_temp(15 downto 0);
math_done <= '1';
-- LSR
elsif
op_code = X"4A" then
math_temp := '0' & A_REG;
N <= '0';
C_FLAG <= A_REG(0);
if math_temp = ('0' & X"0000") then
Z <= '0';
else
Z <= '1';
end if;
A_REG <= math_temp (16 downto 1);
math_done <= '1';
elsif
op_code = X"4E" or
op_code = X"5E" or
op_code = X"46" or
op_code = X"56" then
math_temp := '0' & requested_values(15 downto 0);
store_back <= '1';
N <= '0';
C_FLAG <= requested_values(0);
if math_temp = ('0' & X"0000") then
Z <= '0';
else
Z <= '1';
end if;
math_done <= '1';
-- ORA
elsif
op_code = X"0D" or
op_code = X"1D" or
op_code = X"19" or
op_code = X"0F" or
op_code = X"1F" or
op_code = X"05" or
op_code = X"03" or
op_code = X"15" or
op_code = X"12" or
op_code = X"07" or
op_code = X"13" or
op_code = X"01" or
op_code = X"11" or
op_code = X"17" or
op_code = X"09" then
math_temp := '0' & (requested_values(15 downto 0) or A_REG);
A_REG <= math_temp(15 downto 0);
if math_temp = ('0' & X"0000") then
Z <= '1';
else
Z <= '0';
end if;
N <= math_temp(15);
store_back <= '1';
math_done <= '1';
-- ROL
elsif
op_code = X"2A" then
math_temp := A_REG & C_FLAG;
C_FLAG <= A_REG (15);
N <= math_temp(15);
if math_temp(16 downto 1) = X"0000" then
Z <= '1';
else
Z <= '0';
end if;
A_REG <= math_temp (15 downto 0);
math_done <= '1';
elsif
op_code = X"2E" or
op_code = X"3E" or
op_code = X"26" or
op_code = X"36" then
math_temp := requested_values(15 downto 0) & C_FLAG;
C_FLAG <= A_REG (15);
N <= math_temp(15);
store_back <= '1';
if math_temp(16 downto 1) = (X"0000") then
Z <= '1';
else
Z <= '0';
end if;
math_done <= '1';
-- ROR
elsif
op_code = X"6A" then
math_temp := C_FLAG & A_REG;
C_FLAG <= A_REG (0);
N <= math_temp(15);
if math_temp(16 downto 1) = (X"0000") then
Z <= '1';
else
Z <= '0';
end if;
A_REG <= math_temp (16 downto 1);
math_done <= '1';
elsif
op_code = X"6E" or
op_code = X"7E" or
op_code = X"66" or
op_code = X"76" then
math_temp := C_FLAG & requested_values(15 downto 0) ;
C_FLAG <= requested_values (0);
N <= math_temp(15);
store_back <= '1';
if math_temp(16 downto 1) = (X"0000") then
Z <= '1';
else
Z <= '0';
end if;
math_done <= '1';
-- SBC
elsif
op_code = X"ED" or
op_code = X"FD" or
op_code = X"F9" or
op_code = X"FF" or
op_code = X"E5" or
op_code = X"E3" or
op_code = X"F5" or
op_code = X"F2" or
op_code = X"E7" or
op_code = X"F3" or
op_code = X"E1" or
op_code = X"F1" or
op_code = X"F7" or
op_code = X"E9" then
math_temp := A_REG - ('0' & requested_values(15 downto 0)) - ( ('0' & zeros) & C_FLAG);
if ((math_temp = ('0' & X"0000")) or (math_temp = "10000000000000000")) then
Z <= '1';
N <= math_temp (15);
V <= math_temp (16);
C_FLAG <= math_temp (16) xor (not math_temp(16));
else
Z <= '0';
N <= math_temp (15);
V <= math_temp (16);
C_FLAG <= math_temp (16) xor (not math_temp(16));
end if;
A_REG <= math_temp(15 downto 0);
math_done <= '1';
end if;
if (store_back = '1') and (math_done = '1') then
write_back_value <= math_temp (15 downto 0);
write_back_location <= effective_memory_pointer;
state_machine_onehot <= "0000000001000000";
elsif math_done = '1' then
state_machine_onehot <= "0000000001000000";
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END OF ARITHMATIC STATE
--
--
-- START MEMORY MANIPULATION STATE
--
when sm =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sm;
end if;
-- DEC
if op_code = X"CE" or
op_code= X"DE" or
op_code= X"C6" or
op_code= X"D6" then
mem_temp := '0' & requested_values(15 downto 0) - 1 ;
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
write_back_value <= mem_temp(15 downto 0);
memory_done <= '1';
store_back <= '1';
elsif op_code = X"3A" then
mem_temp := '0' & A_REG - 1 ;
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
A_REG <= mem_temp(15 downto 0);
memory_done <= '1';
-- INC
elsif op_code= X"1A" then
mem_temp := '0' & A_REG + 1 ;
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
A_REG <= mem_temp(15 downto 0);
memory_done <= '1';
elsif op_code = X"EE" or
op_code= X"FE" or
op_code= X"E6" or
op_code= X"F6" then
mem_temp := '0' & requested_values(15 downto 0) + 1 ;
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
write_back_value <= mem_temp(15 downto 0);
memory_done <= '1';
store_back <= '1';
-- LDA
elsif op_code = X"AD" or
op_code= X"BD" or
op_code = X"B9" or
op_code = X"AF" or
op_code = X"BF" or
op_code = X"A5" or
op_code = X"A3" or
op_code = X"B5" or
op_code = X"B2" or
op_code = X"A7" or
op_code = X"B3" or
op_code = X"A1" or
op_code = X"B1" or
op_code = X"B7" then
mem_temp := '0' & requested_values(15 downto 0);
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
A_REG <= mem_temp(15 downto 0);
memory_done <= '1';
elsif op_code = X"A9" then
mem_temp := '0' & requested_values(15 downto 0);
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
A_REG <= mem_temp(15 downto 0);
memory_done <= '1';
-- LDX
elsif op_code = X"AE" or
op_code= X"BE" or
op_code= X"A6" or
op_code= X"B6" or
op_code= X"A2" then
mem_temp := '0' & requested_values(15 downto 0);
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
X_REG <= mem_temp(15 downto 0);
memory_done <= '1';
-- LDY
elsif op_code = X"AC" or
op_code= X"BC" or
op_code= X"A4" or
op_code= X"B4" or
op_code= X"A0" then
mem_temp := '0' & requested_values(15 downto 0);
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
Y_REG <= mem_temp(15 downto 0);
memory_done <= '1';
-- STA
elsif op_code = X"8D" or
op_code= X"9D" or
op_code= X"8F" or
op_code= X"9F" or
op_code= X"85" or
op_code= X"83" or
op_code= X"95" or
op_code= X"92" or
op_code= X"87" or
op_code= X"93" or
op_code= X"81" or
op_code= X"91" or
op_code= X"97" then
mem_temp := '0' & A_REG;
write_back_value <= mem_temp(15 downto 0);
store_back <= '1';
memory_done <= '1';
-- STX
elsif op_code = X"8E" or
op_code= X"86" or
op_code= X"96" then
mem_temp := '0' & X_REG;
write_back_value <= mem_temp(15 downto 0);
store_back <= '1';
memory_done <= '1';
-- STY
elsif op_code = X"8C" or
op_code= X"84" or
op_code= X"94" then
mem_temp :='0' & Y_REG;
write_back_value <= mem_temp(15 downto 0);
store_back <= '1';
memory_done <= '1';
end if;
if (memory_done = '1') and (store_back = '1') then
state_machine_onehot <= "0000000001000000";
write_back_location <= effective_memory_pointer;
elsif (memory_done = '1') and (store_back = '0') then
state_machine_onehot <= "0000000001000000";
store_back <= '0';
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END MEMORY MANIPULATION STATE
--
--
-- START PC MANIPULATION STATE
--
when sp =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sp;
end if;
-- BCC
if op_code = X"90" then
if C_FLAG = '0' then
PC <= PC + std_logic_vector((resize(signed(memory_pointer(7 downto 0)), 16)));
else
PC <= PC;
end if;
pc_done <= '1';
-- BEQ
elsif op_code = X"F0" then
if Z = '1' then
PC <= PC + std_logic_vector((resize(signed(memory_pointer(7 downto 0)), 16)));
else
PC <= PC;
end if;
pc_done <= '1';
-- BMI
elsif op_code = X"30" then
if N = '1' then
PC <= PC + std_logic_vector(resize(signed(memory_pointer(7 downto 0)), 16));
else
PC <= PC;
end if;
pc_done <= '1';
-- BNE
elsif op_code = X"D0" then
if Z = '0' then
PC <= PC + std_logic_vector(resize(signed(memory_pointer(7 downto 0)), 16));
else
PC <= PC;
end if;
pc_done <= '1';
-- BPL
elsif op_code = X"10" then
if N = '0' then
PC <= PC + std_logic_vector(resize(signed(memory_pointer(7 downto 0)), 16));
else
PC <= PC;
end if;
pc_done <= '1';
-- BVC
elsif op_code = X"50" then
if V = '0' then
PC <= PC + std_logic_vector(resize(signed(memory_pointer(7 downto 0)), 16));
else
PC <= PC;
end if;
pc_done <= '1';
-- BVS
elsif op_code = X"70" then
if V = '1' then
PC <= PC + std_logic_vector(resize(signed(memory_pointer(7 downto 0)), 16));
else
PC <= PC;
end if;
pc_done <= '1';
-- JMP
elsif
op_code = X"4C" then
PC <= effective_memory_pointer;
pc_done <= '1';
elsif
op_code = X"5C" then
PC <= requested_values(23 downto 0);
pc_done <= '1';
elsif
op_code = X"6C" or
op_code = X"7C" then
PC <= requested_values(23 downto 0);
pc_done <= '1';
-- JSR
elsif op_code = X"20" or
op_code = X"FC" then
write_back_value <= ProgramCntr;
write_back_bank <= PBR;
PC <= requested_values(23 downto 0);
push_to_stack <= '1';
pc_done <= '1';
-- RTS
elsif op_code = X"60" then
ProgramCntr <= requested_values(15 downto 0);
StackPointer <= StackPointer - 2;
pc_done <= '1';
end if;
if (pc_done = '1') then
state_machine_onehot <= "0000000001000000";
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END PC MANIPULATION STATE
--
--
-- START FLAGC MANIPULATION STATE
--
when sf =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sf;
end if;
-- BIT
if op_code = X"2C" or
op_code = X"3C" or
op_code = X"24" or
op_code = X"34" then
flag_temp := '0' & (A_REG and requested_values(15 downto 0));
if flag_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= flag_temp(15);
V <= flag_temp(14);
else
V <= flag_temp(14);
N <= flag_temp(15);
Z <= '0';
end if;
flag_done <= '1';
elsif op_code = X"89" then
flag_temp := '0' & (A_REG and requested_values(15 downto 0));
if flag_temp(15 downto 0) = (X"0000") then
Z <= '1';
else
Z <= '0';
end if;
flag_done <= '1';
-- CLC
elsif op_code = X"18" then
C_FLAG <= '0';
flag_done <= '1';
-- CLD
elsif op_code = X"D8" then
D_FLAG <= '0';
flag_done <= '1';
-- CLI
elsif op_code = X"58" then
I <= '0';
flag_done <= '1';
-- CLV
elsif op_code = X"B8" then
V <= '0';
flag_done <= '1';
-- SEC
elsif op_code = X"38" then
C_FLAG <= '1';
flag_done <= '1';
-- SED
elsif op_code = X"F8" then
D_FLAG <= '0';
flag_done <= '1';
-- SEI
elsif op_code = X"78" then
I <= '1';
flag_done <= '1';
end if;
if flag_done = '1' then
state_machine_onehot <= "0000000001000000";
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END FLAG MANIPULATION STATE
--
--
-- STACK MANIPULATION STATE
--
when ss =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= ss;
end if;
-- PHA
if op_code = X"48" then
StackPointer <= StackPointer + 2;
push_to_stack <= '1';
write_back_value <= A_REG;
stack_done <= '1';
-- PHP
elsif op_code = X"08" then
StackPointer <= StackPointer + 1;
push_to_stack <= '1';
write_back_value <= X"00" & P;
stack_done <= '1';
-- PLA
elsif op_code = X"68" then
StackPointer <= StackPointer - 2;
stack_temp := '0' & requested_values(15 downto 0);
if stack_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= stack_temp(15);
else
N <= stack_temp(15);
Z <= '0';
end if;
A_REG <= stack_temp(15 downto 0);
stack_done <= '1';
-- PLP
elsif op_code = X"28" then
StackPointer <= StackPointer - 1;
stack_temp := '0' & requested_values(15 downto 0);
if stack_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= stack_temp(15);
else
N <= stack_temp(15);
Z <= '0';
end if;
P <= stack_temp(7 downto 0);
stack_done <= '1';
end if;
if (stack_done = '1') and (store_back = '1') then
write_back_location <= effective_memory_pointer;
state_machine_onehot <= "0000000001000000";
elsif (stack_done = '1') then
state_machine_onehot <= "0000000001000000";
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END STACK MANIPULATION STATE
--
--
-- START NOP STATE
--
when sn =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sn;
end if;
state_machine_onehot <= "0000000001000000";
--
-- END NOP STATE
--
--
-- START EXCHANGE STATE
--
when se =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= se;
end if;
-- TAX
if op_code = X"AA" then
xfr_temp := '0' & A_REG;
if xfr_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= xfr_temp(15);
else
N <= xfr_temp(15);
Z <= '0';
end if;
X_REG <= xfr_temp(15 downto 0);
exchange_done <= '1';
-- TAY
elsif op_code = X"AB" then
xfr_temp := '0' & A_REG;
if xfr_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= xfr_temp(15);
else
N <= xfr_temp(15);
Z <= '0';
end if;
Y_REG <= xfr_temp(15 downto 0);
exchange_done <= '1';
-- TYA
elsif op_code = X"98" then
xfr_temp := '0' & Y_REG;
if xfr_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= xfr_temp(15);
else
N <= xfr_temp(15);
Z <= '0';
end if;
A_REG <= xfr_temp(15 downto 0);
exchange_done <= '1';
-- TSX
elsif op_code = X"BA" then
xfr_temp := '0' & StackPointer;
if xfr_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= xfr_temp(15);
else
N <= xfr_temp(15);
Z <= '0';
end if;
X_REG <= xfr_temp(15 downto 0);
exchange_done <= '1';
-- TXA
elsif
op_code = X"8A" then
xfr_temp := '0' & X_REG;
if xfr_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= xfr_temp(15);
else
N <= xfr_temp(15);
Z <= '0';
end if;
A_REG <= xfr_temp(15 downto 0);
exchange_done <= '1';
-- TXS
elsif
op_code = X"9A" then
xfr_temp := '0' & X_REG;
StackPointer <= xfr_temp(15 downto 0);
exchange_done <= '1';
end if;
if (exchange_done = '1') then
state_machine_onehot <= "0000000001000000";
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END EXCHANGE STATE
--
--
-- START INTERUPT STATE
--
when si =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= si;
end if;
-- RTI
if op_code = X"40" then
ProgramCntr <= requested_values(23 downto 8);
P <= requested_values(7 downto 0);
end if;
state_machine_onehot <= "0000000001000000";
--
-- END INTRRUPT STATE
--
when s6 =>
if (state_machine_onehot = "0000000010000000") and (ready_up = '1') then
state <= s0;
else
state <= state;
end if;
math_done <= '0';
memory_done <= '0';
pc_done <= '0';
flag_done <= '0';
stack_done <= '0';
exchange_done <= '0';
if (store_back = '1') then
READ_OUT <= write_back_value;
ADDRESS_OUT <= write_back_location;
store_back <= '0';
check_done := '1';
RW <= '1';
state_machine_onehot <= "0000000010000000";
elsif (push_to_stack = '1') then
read_out <= write_back_value;
read_out_bank <= write_back_bank;
address_out <= X"00" & StackPointer;
push_to_stack <= '0';
check_done := '1';
RW <= '1';
state_machine_onehot <= "0000000010000000";
else
check_done := '1';
state_machine_onehot <= "0000000010000000";
end if;
when others =>
state_machine_onehot <= "0000000000000010";
end case;
end if;
end process;
--
-- This process will look at the opcode
-- and determine the addressing mode of
-- the specific instruction being requested
-- and then pass it onto the adr_type vector.
--
Addressing_Mode:
process (addressing_on) is
begin
addressing_done <= '0';
if (addressing_on = '1') then
-- Refer to 65000 Programmers Manual for explanation
-- of addressing modes.
--
-- Symbol Addressing Mode Symbol Addressing Mode
-- 0 -> a absolute
-- 1 -> A_REG accumulator
-- 2 -> a,x absolute indexed with X
-- 3 -> a,y absolute indexed with Y_REG
-- 4 -> al absolute long
-- 5 -> al,x absolute long indexed
-- 6 -> (a) absolute indirect
-- 7 -> (a,x) absolute indexed indirect
-- 8 -> d direct
-- 9 -> d,s stack relative
-- 10 -> d,x direct indexed with x
-- 11 -> d,y direct indexed with y
-- 12 -> (d) direct indirect
-- 13 -> [d] direct indirect long
-- 14 -> (d,s),y stack relative indirect indexed
-- 15 -> (d,x) direct indexed indirect
-- 16 -> (d),y direct indirect indexed
-- 17 -> [d].y direct indirect long indexed
-- 18 -> i implied
-- 19 -> r program counter relative
-- 20 -> rl program counter relative long
-- 21 -> s stack
-- 22 -> xyc block move
-- 23 -> # immediate
--
--
case op_code is
when X"6d" | X"2d" | X"0e" | X"2c" | X"cd" | X"ec" | X"cc" | X"ce" | X"4d" | X"ee" | X"4c" | X"20" | X"ad" | X"ae" | X"ac" | X"4e" | X"0d" | X"2e" | X"6e" | X"ed" | X"8d" | X"8e" | X"8c" | X"9c" | X"1c" | X"0c" =>
adr_type <= 0;
when X"0a" | X"3A" | X"1a" | X"4a" | X"2a" | X"6a" | X"3b" | X"ba" | X"8a" | X"9a" | X"9b" | X"98" | X"bb" | X"cb" | X"42" | X"eb" | X"fb" =>
adr_type <= 1;
when X"7d" | X"3e" | X"1e" | X"3c" | X"dd" | X"de" | X"5d" | X"fe" | X"bd" | X"bc" | X"5e" | X"1d" | X"7e" | X"fd" | X"9d" | X"9e" =>
adr_type <= 2;
when X"6f" | X"2f" | X"cf" | X"4f" | X"5c" | X"22" | X"af" | X"0f" | X"8f" =>
adr_type <= 3;
when X"79" | X"39" | X"d9" | X"59" | X"b9" | X"be" | X"19" | X"f9" =>
adr_type <= 4;
when X"7f" | X"3f" | X"df" | X"5f" | X"bf" | X"1f" | X"ff" | X"9f" =>
adr_type <= 5;
when X"dc" | X"6c" =>
adr_type <= 6;
when X"7c" | X"fc" =>
adr_type <= 7;
when X"65" | X"25" | X"06" | X"24" | X"c5" | X"e4" | X"c4" | X"c6" | X"45" | X"e6" | X"a5" | X"a6" | X"a4" | X"46" | X"05" | X"26" | X"66" | X"e5" | X"85" | X"86" | X"84" | X"64" | X"14" | X"04" =>
adr_type <= 8;
when X"63" | X"23" | X"c3" | X"43" | X"a3" | X"03" | X"e3" | X"83" =>
adr_type <= 9;
when X"75" | X"36" | X"16" | X"34" | X"d5" | X"d6" | X"55" | X"f6" | X"b5" | X"b4" | X"56" | X"15" | X"76" | X"f5" | X"95" | X"94" | X"74" =>
adr_type <= 10;
when X"b6" | X"96" =>
adr_type <= 11;
when X"72" | X"32" | X"d2" | X"52" | X"b2" | X"12" | X"f2" | X"92" =>
adr_type <= 12;
when X"67" | X"27" | X"c7" | X"47" | X"a7" | X"07" | X"e7" | X"87" =>
adr_type <= 13;
when X"73" | X"33" | X"d3" | X"53" | X"b3" | X"13" | X"f3" | X"93" =>
adr_type <= 14;
when X"61" | X"c1" | X"41" | X"a1" | X"01" | X"e1" | X"81" =>
adr_type <= 15;
when X"71" | X"31" | X"d1" | X"51" | X"b1" | X"11" | X"f1" | X"91" =>
adr_type <= 16;
when X"77" | X"37" | X"d7" | X"57" | X"b7" | X"17" | X"f7" | X"97" =>
adr_type <= 17;
when X"18" | X"d8" | X"58" | X"b8" | X"ca" | X"88" | X"e8" | X"c8" | X"ea" | X"38" | X"f8" | X"78" | X"db" | X"aa" | X"5b" | X"1b" | X"7b" =>
adr_type <= 18;
when X"b0" | X"f0" | X"90" | X"d0" | X"10" | X"80" | X"50" | X"70" =>
adr_type <= 19;
when X"82" =>
adr_type <= 20;
when X"00" | X"02" | X"f4" | X"d4" | X"62" | X"48" | X"8b" | X"0b" | X"4b" | X"08" | X"da" | X"5a" | X"68" | X"ab" | X"2b" | X"28" | X"fa" | X"7a" | X"40" | X"6b" | X"60" =>
adr_type <= 21;
when X"54" | X"44" =>
adr_type <= 22;
when X"69" | X"29" | X"89" | X"c9" | X"e0" | X"c0" | X"49" | X"a9" | X"a2" | X"a0" | X"09" | X"c2" | X"e9" | X"e2" =>
adr_type <= 23;
when others =>
adr_type <= 0;
end case;
addressing_done <= '1';
end if;
end process;
--
-- This process reverses the byte order
-- of instruction arguments so that
-- a memory pointer or argument can
-- be precisely used
--
memory_pointer_calculation:
process (memory_calculate_on) is
begin
memory_calculate_done <= '0';
if memory_calculate_on = '1' then
case instruction_size is
when X"2" =>
memory_pointer <= X"0000" & chunk_pull (23 downto 16);
when X"3" =>
memory_pointer <= X"00" & chunk_pull (23 downto 16) & chunk_pull(15 downto 8);
when X"4" =>
memory_pointer <= chunk_pull (23 downto 16) & chunk_pull(15 downto 8) & chunk_pull (7 downto 0);
when others =>
memory_pointer <= (others => '0');
end case;
memory_calculate_done <= '1';
end if;
end process;
--
-- This process will decode the OPcode byte.
-- It will then assign instruction_info all relevent data.
--
opcode_info:
process (decode_on) is
begin
decode_done <= '0';
if reset = '1' then
instruction_info <= (others => '0');-- clear instruction info
elsif (decode_on = '1') then
--
--
-- intstruction_info syntax is
-- bytes + cycles + type
--
-- Flags (on reset) :
-- N V M X D I Z C_FLAG/E
-- P = * * 1 1 0 1 * */1
-- * = Not Initialized
-- STP and WAI instructions are cleared.
-- Type Table:
-- 0 -> Arithmatic
-- 1 -> PC
-- 2 -> Memory
-- 3 -> Coprocessor
-- 4 -> Flag
-- 5 -> Stack
-- 6 -> NOP (and non used)
-- 7 -> Exchange
-- 8 -> Interrupt
--
--
--
--
case op_code is
--
-- BRK (break)
-- pc+2 onto stack, processor status onto stack
-- Also set I flag = 1
--
-- !!!!!!!!!!!!! TODO: Implemented as a NOP for now due to issues with interrupts
-- !!!!!!!!!!!!!!!!!!!!!!!!!!! X"270" is now X"126"
when X"00" =>
instruction_info <= X"126";
-- ADC
-- The following are Add memory to accumulator with cary
-- A_REG + M + C_FLAG -> A_REG, C_FLAG
--
when X"69" =>
instruction_info <= X"220";
when X"65" =>
instruction_info <= X"230";
when X"75" =>
instruction_info <= X"240";
when X"6D" =>
instruction_info <= X"340";
when X"7D" =>
instruction_info <= X"340";
when X"79" =>
instruction_info <= X"340";
when X"61" =>
instruction_info <= X"260";
when X"71" =>
instruction_info <= X"250";
-- AND
-- The follwing are logical AND's with accumulator
-- A_REG and M -> A_REG
--
--
when X"29" =>
instruction_info <= X"220";
when X"25" =>
instruction_info <= X"230";
when X"35" =>
instruction_info <= X"240";
when X"2D" =>
instruction_info <= X"340";
when X"3D" =>
instruction_info <= X"340";
when X"39" =>
instruction_info <= X"340";
when X"21" =>
instruction_info <= X"260";
when X"31" =>
instruction_info <= X"250";
--
-- The following are ASL
-- left shift by one
-- memory or accumulator
--
when X"0A" =>
instruction_info <= X"120";
when X"06" =>
instruction_info <= X"250";
when X"16" =>
instruction_info <= X"260";
when X"0E" =>
instruction_info <= X"360";
when X"1E" =>
instruction_info <= X"370";
-- BCC
-- Branch on carry clear
-- when carry flag = 0, branch
-- * + 1 cycle if branch happens
when X"90" =>
instruction_info <= X"221";
-- BEQ
-- branch on zero flag set
-- * + 1 cycle if branch happens
when X"F0" =>
instruction_info <= X"221";
-- BIT
-- Accumulator AND'd with memory,
-- bit 7 of memory goes to Negative flag
-- bit 6 of memoyr goes to overflow flag
-- If A_REG and M = 0 then Z = 1 , else 0
when X"24" =>
instruction_info <= X"234";
when X"2C" =>
instruction_info <= X"344";
-- BMI
-- Branch On Negative Flag Set
-- * + 1 Cycle If Can Branch
when X"30" =>
instruction_info <= X"221";
-- BNE
-- Branch on zero flag not set
-- * + 1 cycle if can do
--
when X"D0" =>
instruction_info <= X"221";
-- BPL
-- Brnach when N flag not set.
-- * + 1 cycle if can do
--
when X"10" =>
instruction_info <= X"221";
-- BVC
-- Branch on V flag = 0
-- * +1 cycle if can do
when X"50" =>
instruction_info <= X"221";
-- BVS
-- Branch when V flag set
-- * + 1 cycle if can do
when X"70" =>
instruction_info <= X"221";
-- CLC
-- Clear the carry flag
--
when X"18" =>
instruction_info <= X"124";
-- CLD
-- Clear the decimal flag
--
when X"D8" =>
instruction_info <= X"124";
-- CLI
-- Clear interupt bit
--
when X"58" =>
instruction_info <= X"124";
-- CLV
-- Clear the overflow flag
--
when X"B8" =>
instruction_info <= X"124";
-- CMP
-- Compar memory and accumulator
-- Set N, Z, or C_FLAG flag accordingly
-- A_REG - M
--
when X"c9" =>
instruction_info <= X"220";
when X"c5" =>
instruction_info <= X"230";
when X"D5" =>
instruction_info <= X"240";
when X"DD" =>
instruction_info <= X"340";
when X"d9" =>
instruction_info <= X"340";
when X"c1" =>
instruction_info <= X"260";
when X"d1" =>
instruction_info <= X"250";
-- CPX
-- Compary memory and X reg
-- X - M and set N, Z, C_FLAG flags as needed
--
when X"E0" =>
instruction_info <= X"220";
when X"E4" =>
instruction_info <= X"230";
when X"EC" =>
instruction_info <= X"340";
-- CPY
-- Compary memory and Y_REG reg
-- Y_REG - M
-- Set N, Z, and C_FLAG flags as needed.
--
when X"C0" =>
instruction_info <= X"220";
when X"C4" =>
instruction_info <= X"230";
when X"cc" =>
instruction_info <= X"340";
-- DEC
-- Decrimeent memory by 1
-- M - 1 -> M
-- Use N & Z flags
when X"C6" =>
instruction_info <= X"252";
when X"D6" =>
instruction_info <= X"262";
when X"ce" =>
instruction_info <= X"362";
when X"de" =>
instruction_info <= X"372";
-- DEX
-- Decriment X reg by 1
-- X - 1 -> X
-- use N & Z flags
when X"CA" =>
instruction_info <= X"120";
-- DEY
-- Decriment Y_REG reg by 1
-- Y_REG - 1 -> Y_REG
-- N & Z flags
--
when X"88" =>
instruction_info <= X"120";
-- EOR
-- Acc XOR Mem -> Acc
-- N and Z flags
--
when X"49" =>
instruction_info <= X"220";
when X"45" =>
instruction_info <= X"230";
when X"55" =>
instruction_info <= X"240";
when X"4d" =>
instruction_info <= X"340";
when X"5d" =>
instruction_info <= X"340";
when X"59" =>
instruction_info <= X"340";
when X"41" =>
instruction_info <= X"260";
when X"51" =>
instruction_info <= X"250";
-- INC
-- Incriment memory by one
-- M + 1 -> M
-- N & Z flags
--
when X"E6" =>
instruction_info <= X"252";
when X"F6" =>
instruction_info <= X"262";
when X"ee" =>
instruction_info <= X"362";
when X"fe" =>
instruction_info <= X"372";
-- INX
-- Incriment X by one
-- X + 1 -> X
-- N & Z flags
--
when X"e8" =>
instruction_info <= X"120";
-- INY
-- Incriment Y_REG by one
-- Y_REG + 1 -> Y_REG
-- N & Z flags
--
when X"c8" =>
instruction_info <= X"120";
--
--
-- JMP
-- JUMP INSTRUCTIONS
--=======================================================================
-- JMP
-- Jump to location
-- PC + 1 -> PCL
-- PC + 2 -> PCH
--JMP absolute
--take contents of memory location
--1 byte from opcode and store into
--PC LOW, then take the very next byte
--and store into PC HIGH
-- REVERSE BYTE ORDER AND MAKE NEW PC
when X"4c" =>
instruction_info <= X"331";
--JMP indirect
-- starts out the same as above, but
-- instead of getting the opcode at the new PC,
-- a new PC is again fetched in the same way.
-- making this a jump to a jump.
when X"6c" =>
instruction_info <= X"351";
--=======================================================================
--
--
--
--
-- JSR
-- Jump to subroutine
-- PC + 2 -> stack
-- PC + 1 -> PCL
-- PC + 2 -> PCH
--
when X"20" =>
instruction_info <= X"361";
-- LDA
-- Load accumulator with memory
-- M -> A_REG
-- N & Z flags
when X"a9" =>
instruction_info <= X"222";
when X"a5" =>
instruction_info <= X"232";
when X"b5" =>
instruction_info <= X"242";
when X"ad" =>
instruction_info <= X"342";
when X"bd" =>
instruction_info <= X"342";
when X"b9" =>
instruction_info <= X"342";
when X"a1" =>
instruction_info <= X"262";
when X"b1" =>
instruction_info <= X"252";
-- LDX
-- Load X with memory
-- M -> X
-- N & Z flags
--
when X"a2" =>
instruction_info <= X"222";
when X"a6" =>
instruction_info <= X"232";
when X"b6" =>
instruction_info <= X"242";
when X"ae" =>
instruction_info <= X"342";
when X"be" =>
instruction_info <= X"342";
-- LDY
-- Load Y_REG with memory
-- M -> Y_REG
-- N & Z Flags
--
when X"a0" =>
instruction_info <= X"222";
when X"a4" =>
instruction_info <= X"232";
when X"b4" =>
instruction_info <= X"242";
when X"ac" =>
instruction_info <= X"342";
when X"bc" =>
instruction_info <= X"342";
-- LSR
-- Right shift one bit
-- 0 -> [bits] -> C_FLAG
-- C_FLAG & Z flag, N flag zerod
--
when X"4a" =>
instruction_info <= X"120";
when X"46" =>
instruction_info <= X"250";
when X"56" =>
instruction_info <= X"260";
when X"4e" =>
instruction_info <= X"360";
when X"5e" =>
instruction_info <= X"370";
-- NOP
-- No operation
--
when X"ea" =>
instruction_info <= X"126";
-- ORA
-- Or with accumulator
-- A_REG (or) M -> A_REG
-- N & Z flags
--
when X"09" =>
instruction_info <= X"220";
when X"05" =>
instruction_info <= X"230";
when X"15" =>
instruction_info <= X"240";
when X"0d" =>
instruction_info <= X"340";
when X"1d" =>
instruction_info <= X"340";
when X"19" =>
instruction_info <= X"340";
when X"01" =>
instruction_info <= X"260";
when X"11" =>
instruction_info <= X"250";
-- PHA
-- Push accumuator to stack
-- A_REG -> STACK
-- NO FLAGS
when X"48" =>
instruction_info <= X"135";
-- PHP
-- Push processor status on stack
-- P -> STACK
when X"08" =>
instruction_info <= X"135";
-- PLA
-- Pull accumulator from stack
-- STACK -> A_REG
-- N & Z flags
--
when X"68" =>
instruction_info <= X"145";
-- PLP
-- Pull processor status from stack
-- STACK -> P
-- ALL FLAGS CAN CHANGE
when X"28" =>
instruction_info <= X"145";
-- ROL
-- Rotate one bit left
-- [bit 7] -> C_FLAG FLAG
-- [ <- bits 6 - 0] [C_FLAG FLAG (becomes 0 bit)]
-- N & Z & C_FLAG FLAGS
--
when X"2a" =>
instruction_info <= X"120";
when X"26" =>
instruction_info <= X"250";
when X"36" =>
instruction_info <= X"260";
when X"2e" =>
instruction_info <= X"360";
when X"3e" =>
instruction_info <= X"270";
-- ROR
-- Rotate right one
-- [C_FLAG FLAG -> bit 7] [bits 7 - 1 ] [bit 0 becomes C_FLAG flag]
-- N & Z & C_FLAG
--
when X"6a" =>
instruction_info <= X"120";
when X"66" =>
instruction_info <= X"250";
when X"76" =>
instruction_info <= X"260";
when X"6e" =>
instruction_info <= X"360";
when X"7e" =>
instruction_info <= X"370";
-- RTI
-- Return from Interrupt
-- STACK -> P
-- STACK -> PC
-- FLAGS FROM STACK
--
when X"40" =>
instruction_info <= X"168";
-- RTS
-- Reutrn from subroutine
-- STACK -> PC
-- PC + 1 -> PC
-- NO FLAGS
--
when X"60" =>
instruction_info <= X"161";
-- SBC
-- Subtract memory from accumulator w/ borrow
-- A_REG - M - (not) C_FLAG -> Accumulator
-- N & Z & C_FLAG & V Flags
--
when X"e9" =>
instruction_info <= X"220";
when X"e5" =>
instruction_info <= X"230";
when X"f5" =>
instruction_info <= X"240";
when X"ed" =>
instruction_info <= X"340";
when X"fd" =>
instruction_info <= X"340";
when X"f9" =>
instruction_info <= X"340";
when X"e1" =>
instruction_info <= X"260";
when X"f1" =>
instruction_info <= X"250";
-- SEC
-- Set carry flag
-- 1 -> C_FLAG
-- C_FLAG Flag
--
when X"38" =>
instruction_info <= X"124";
-- SED
-- Set decimal flag
-- 1 -> D
-- D flag
--
when X"f8" =>
instruction_info <= X"124";
-- SEI
-- Set interrupt disable flag
-- 1 -> I
-- I FLAG
when X"78" =>
instruction_info <= X"124";
-- STA
-- Store accumulator in memory
-- A_REG -> M
-- no flags
--
when X"85" =>
instruction_info <= X"232";
when X"95" =>
instruction_info <= X"242";
when X"8d" =>
instruction_info <= X"342";
when X"9d" =>
instruction_info <= X"352";
when X"99" =>
instruction_info <= X"352";
when X"81" =>
instruction_info <= X"262";
when X"91" =>
instruction_info <= X"262";
-- STX
-- Store X in memory
-- X -> M
--
when X"86" =>
instruction_info <= X"232";
when X"96" =>
instruction_info <= X"242";
when X"8e" =>
instruction_info <= X"342";
-- STY
-- Store y in memory
-- Y_REG -> M
--
when X"84" =>
instruction_info <= X"232";
when X"94" =>
instruction_info <= X"242";
when X"8c" =>
instruction_info <= X"342";
-- TAX
-- Transfer A_REG to X
-- A_REG -> X
-- N & Z
--
when X"AA" =>
instruction_info <= X"127";
-- TAY
-- X-fer A_REG to Y_REG
-- A_REG -> Y_REG
-- N & Z
--
when X"a8" =>
instruction_info <= X"127";
-- TYA
-- X-fer Y_REG to A_REG
-- Y_REG -> A_REG
-- N & Z
--
when X"98" =>
instruction_info <= X"127";
-- TSX
-- X-fer stack pointer to X
-- S -> X
-- N & Z
--
when X"ba" =>
instruction_info <= X"127";
-- TXA
-- X-fer X to Accumulator
-- X -> A_REG
-- N & Z
--
when X"8A" =>
instruction_info <= X"127";
-- TXS
-- X-fer X to stack pointer
-- X -> S
--
when X"9a" =>
instruction_info <= X"127";
-- XBA
-- Exchange B & A_REG Accumulators
-- A_REG <-> B
-- Remeber that A_REG is the lower 8 bits of C_FLAG
-- and that B is the upper 8 bits of C_FLAG
--
when X"EB" =>
instruction_info <= X"137";
-- XCE
-- Exchange Carry and Emulation flags
-- E Flag <-> C_FLAG Flag
-- Even though this manipulates
-- flag bits, note that it is
-- EXCHANGE type instruction for
-- this implementation.
--
when X"FB" =>
instruction_info <= X"127";
--
-- All other instructions are NOP's
--
when others =>
instruction_info <= X"126";
end case;
decode_done <= '1';
end if;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Company: Open Source
-- Engineer: Steven T. Seppala ( rad- )
--
-- Create Date: 01/26/2016 03:26:56 PM
-- Design Name:
-- Module Name: 65C816 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
-- This is a soft-core implementation of a 65C816. There will be initally 92
--of the 256 OpCodes useable. Please refer to DOC 1A for reference.
--
-- Dependencies:
-- For testing purposes there will be an AXI interface into this module.
--This should be provided with all the source HDL.
--If this module is being used in conjunction with another module and there is no need
--to access or view the inner workings of this module, no other dependancies occour.
--
-- Revision: V .1 -- 26 Jan 2016 STS
--
-- Revision 0.01 - File Created
-- Additional Comments:
-- The SNES CPU (65c816) uses little endian.
-- Revision 0.5 - Decode Table and Addressing Modes
-- The decode process and addressing mode assigning table
-- processes have been crated.
-- NOTE : Memory accesses will be passed from this
-- module to a C_FLAG program for reading/writing.
-- Revision 1.0 - 18 Feb 2016
-- Main Modules finished.
-- Revision 1.1 - 3 March 2016
-- Tests passed. Main is now implemented.
--
----------------------------------------------------------------------------------
-- ██████ ███████ ███████ ████████
-- ██░░░░██ ██░░░░░██ ░██░░░░██ ░██░░░░░
-- ██ ░░ ██ ░░██░██ ░██ ░██
--░██ ░██ ░██░███████ ░███████
--░██ ░██ ░██░██░░░██ ░██░░░░
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.SNES65816func.all;
entity Soft_65C816 is
Port ( clk :in STD_LOGIC; -- Main CLK for system
tru_clk :in std_logic; -- True clk for system
reset :in std_logic; -- Reset Signal
Addr_Bus :out STD_LOGIC_VECTOR (23 downto 0);-- Address Bus
D_BUS :in STD_LOGIC_VECTOR (31 downto 0);-- Data Bus IN
D_BUS_out :out STD_LOGIC_VECTOR (23 downto 0);-- Data Bus OUT
EMULATION_SELECT :out STD_LOGIC; -- Emulation Bit
RDY :out STD_LOGIC;
DATA_RDY :in STD_LOGIC;
REG_A :out std_logic_vector(15 downto 0);
REG_X :out std_logic_vector(15 downto 0);
REG_Y :out std_logic_vector(15 downto 0);
REG_SP :out std_logic_vector(15 downto 0);
REG_PC :out std_logic_vector(15 downto 0);
REG_Proc :out std_logic_vector(7 downto 0);
REG_DBR :out std_logic_vector(7 downto 0);
state_machine :out std_logic_vector(15 downto 0);
RW :out std_logic ; -- Read or write bit
VPB :out STD_LOGIC);
end Soft_65C816;
architecture Behavioral of Soft_65C816 is
--state machine states
type state_machine_states is (s0, s1, s2, s3, s4, s5 , sc, sa, sm, sp, sf, ss, sn, se, si, calculate_memory_pointer, s6);
signal state : state_machine_states;
--One hot sounter for state machine location/control
signal state_machine_onehot : std_logic_vector (15 downto 0);
--chunk pull vector
signal chunk_pull : std_logic_vector (31 downto 0);
--vector with info about the opcode
signal instruction_info : std_logic_vector (11 downto 0);
signal op_code : std_logic_vector (7 downto 0);
-- This will have the instructions arguments assigned to it.
signal instrction_args : std_logic_vector (31 downto 0);
-- This signal must be run with a 3.58 MHz CLK.
-- It is just a counter, but it must count at 3.58 MHz.
signal tru_cpu : std_logic_vector (3 downto 0);
-- This is essentially a latch enable,
-- it will count for as many cycles as the
-- operation would take on a true 65816
signal tru_clk_cntr : std_logic_vector(3 downto 0);
-- This will hold the instruction size, so the PC can correctly
-- be incrimented.
signal instruction_size : std_logic_vector (3 downto 0);
-- Memory pointer for pulling and pushing values
signal memory_pointer : std_logic_vector ( 23 downto 0);
-- This signal holds the values from the memory locations
-- requested.
signal requested_values : std_logic_vector (31 downto 0);
-- This will hold type info so the correct
-- execution state can be determined.
signal type_info : std_logic_vector (3 downto 0);
--
-- Process Control Signals
--
signal addressing_done, addressing_on, decode_on, decode_done, memory_calculate_done, memory_calculate_on : STD_LOGIC;
signal memory_done:std_logic;
signal math_done : std_logic;
signal pc_done : std_logic;
signal flag_done : std_logic;
signal store_back: std_logic;
signal push_to_stack : std_logic;
signal ready_up : std_logic;
signal stack_done: std_logic;
signal exchange_done: std_logic;
signal data_enable : std_logic;
--
-- REGISTER DECLARATIONS
--
-- Program Counter : PC
-- PC Bank Register : PBR
signal PC : std_logic_vector (23 downto 0);
alias PBR : std_logic_vector (7 downto 0) is PC (23 downto 16);
alias ProgramCntr : std_logic_vector (15 downto 0) is PC (15 downto 0);
-- Accumulator : A_REG
-- Direct Page Register: DP
-- Stack Pointer : SP
-- X & Y_REG Are Index Registers
signal A_REG, DP, StackPointer, X_REG, Y_REG : std_logic_vector ( 15 downto 0);
-- StackPointer is vaid from 00:0000 to 00:FFFF
-- Processor Status : P
-- Data Bank Register : DBR
signal P : std_logic_vector ( 7 downto 0);
signal DBR : std_logic_vector ( 7 downto 0);
alias N : STD_LOGIC is P(7); -- Negative Flag
alias V : STD_LOGIC is P(6); -- Overflow Flag
alias M : STD_LOGIC is P(5); -- Memory Select
alias X_FLAG : STD_LOGIC is P(4); -- Index Register
alias D_FLAG : STD_LOGIC is P(3); -- Decimal Mode
alias I : STD_LOGIC is P(2); -- IRQ Disable
alias Z : STD_LOGIC is P(1); -- Zero Result
alias C_FLAG : STD_LOGIC is P(0); -- Carry Flag / Emulation Mode
--
-- END REGISTER DECLARATIONS
--
--
-- Memory signals
--
signal effective_memory_pointer : std_logic_vector (23 downto 0);
signal write_back_location : std_logic_vector (23 downto 0);
signal write_back_value : std_logic_vector(15 downto 0);
signal write_back_bank : std_logic_vector(7 downto 0);
signal adr_type : integer range 0 to 25;
signal push_val : std_logic_vector(23 downto 0);
signal read_out : std_logic_vector(15 downto 0);
signal read_out_bank : std_logic_vector(7 downto 0);
signal address_out : std_logic_vector(23 downto 0);
--
--
-- Constant Signals
--
--
constant zeros : std_logic_vector (15 downto 1) := ( B"0000_0000_0000_000");
begin
state_machine <= state_machine_onehot;
D_BUS_out <= read_out_bank & read_out;
Addr_Bus<= address_out;
REG_A <= A_REG;
REG_X <= X_REG;
REG_Y <= Y_REG;
REG_SP <= StackPointer;
REG_PC <= ProgramCntr;
REG_Proc <= P;
REG_DBR <= DBR;
--
-- This is the true CPU clock for the processor
-- It runs at a multiple of 3.58 MHz and allows s6 to continue
-- to s1.
slow_clock:
process(tru_clk, clk, reset) is
begin
if reset = '1' then
tru_clk_cntr <= (others => '0');
ready_up <= '0';
elsif rising_edge(clk) then
if (tru_clk_cntr = tru_cpu) and (tru_clk = '1') then
ready_up <= '1' ;
end if;
end if;
if falling_edge(clk) then
if ready_up ='1' then
tru_clk_cntr <= (others => '0');
end if;
end if;
if rising_edge(tru_clk) then
tru_clk_cntr <= std_logic_vector(unsigned(tru_clk_cntr) + 1);
end if;
end process;
--
-- This is a 16 bit microprocessor with variable length instructions, the PC will
-- depend on the current instruction size.
-- Thus the PC will get
--
--
state_machine_process:
process (clk, reset) is
variable effective_memeory_pointer_temp : std_logic_vector (23 downto 0);
variable pointer_calculation_done : std_logic;
variable math_temp : std_logic_vector (16 downto 0);
variable stack_temp : std_logic_vector (16 downto 0);
variable xfr_temp : std_logic_vector (16 downto 0);
variable mem_temp : std_logic_vector (16 downto 0);
variable flag_temp : std_logic_vector (16 downto 0);
variable check_done : std_logic;
begin
if reset = '1' then
--TODO: RESET
state <= s0; -- reset to s0
chunk_pull <= (others => 'Z'); -- clear chunk pull
op_code <= (others => 'Z'); -- set opcode hi-Z
StackPointer <= X"0100"; -- Initialize Stack pointer
A_REG <= (others => '0');
X_REG <= (others => '0');
Y_REG <= (others => '0');
PC <= (others => '0');
DBR <= X"00";
DP <= X"0000";
N <= '0';
V <= '0';
M <= '1';
X_FLAG <= '1';
D_FLAG <= '0';
I <= '1';
Z <= '0';
C_FLAG <= '1'; -- This is the emulation flag on reset.
elsif rising_edge(clk) then
case state is
when s0 =>
if state_machine_onehot = "0000000000000001" then
state <= s1;
else
state <= s0;
end if;
state_machine_onehot <= "0000000000000001";
write_back_value <=X"0000";
write_back_bank <=X"00";
address_out <=PC;
check_done := '0';
rdy <= '1';
RW <= '0';
when s1 =>
if state_machine_onehot = "0000000000000010" then
state <= s2;
else
state <= s1;
end if;
data_enable <= '1';
if data_rdy ='0' and chunk_pull /= "ZZZZZZZZZZZZZZZZZ" then
chunk_pull <= D_BUS;
state_machine_onehot <= "0000000000000010";
rdy <= '0';
end if;
when s2 =>
if ((addressing_done = '1') and (decode_done = '1') and (state_machine_onehot = "0000000000000100")) then
state <= s3;
else
state <= s2;
end if;
addressing_on <= '1';
decode_on <= '1';
-- This should send the OPCode from chunkpull
-- to the opcode_info process, which inturn
-- will give us everything we need to know about how
-- to execute the instruction.
if data_enable = '1' then
op_code <= chunk_pull(31 downto 24);
state_machine_onehot <= "0000000000000100";
data_enable <= '0';
end if;
when s3 =>
if state_machine_onehot = "0000000000001000" then
state <= s4;
else
state <= s3;
end if;
data_enable <= '1';
addressing_on <= '0';
decode_on <= '0';
instruction_size <= instruction_info(11 downto 8);
tru_cpu <= instruction_info(7 downto 4);
type_info <= instruction_info( 3 downto 0);
state_machine_onehot <= "0000000000001000";
when s4 =>
if ((state_machine_onehot = "0000000000010000") and (memory_calculate_done = '1'))then
state <= calculate_memory_pointer;
else
state <= s4;
end if;
PC <= std_logic_vector(unsigned(PC) + unsigned(instruction_size));
state_machine_onehot <= "0000000000010000";
memory_calculate_on <= '1';
when calculate_memory_pointer =>
if pointer_calculation_done = '1' then
state <= s5;
end if;
memory_calculate_on <= '0';
case adr_type is
when 0 =>
if ((op_code = X"20") or (op_code = X"4c")) then
effective_memory_pointer(23 downto 16) <= PBR;
effective_memory_pointer(15 downto 0) <= memory_pointer(15 downto 0);
else
effective_memory_pointer(23 downto 16) <= DBR;
effective_memory_pointer(15 downto 0) <= memory_pointer(15 downto 0);
end if;
pointer_calculation_done := '1';
when 1 =>
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
when 2 =>
effective_memeory_pointer_temp(23 downto 16) := DBR;
effective_memeory_pointer_temp(15 downto 0) := memory_pointer(15 downto 0);
effective_memory_pointer <= std_logic_vector(unsigned(effective_memeory_pointer_temp) + unsigned(X_REG));
pointer_calculation_done := '1';
when 3 =>
effective_memeory_pointer_temp(23 downto 16) := DBR;
effective_memeory_pointer_temp(15 downto 0) := memory_pointer(15 downto 0);
effective_memory_pointer <= std_logic_vector(unsigned(effective_memeory_pointer_temp) + unsigned(Y_REG));
pointer_calculation_done := '1';
when 4 =>
effective_memory_pointer <= memory_pointer;
pointer_calculation_done := '1';
when 5 =>
effective_memory_pointer <= std_logic_vector(unsigned(memory_pointer) + unsigned(X_REG));
pointer_calculation_done := '1';
when 6 =>
effective_memory_pointer(23 downto 16) <= PBR;
effective_memory_pointer(15 downto 0) <= memory_pointer(15 downto 0);
pointer_calculation_done := '1';
when 7 =>
effective_memory_pointer(23 downto 16) <= PBR;
effective_memory_pointer(15 downto 0) <= memory_pointer(15 downto 0) + X_REG;
pointer_calculation_done := '1';
when 8 =>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 9 =>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= StackPointer + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 10=>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= DP + X_REG + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 11=>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= DP + Y_REG + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 12=>
effective_memory_pointer(23 downto 16) <= DBR;
effective_memory_pointer(15 downto 0) <= DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 13=>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 14=>
effective_memory_pointer(23 downto 16) <= DBR;
effective_memory_pointer(15 downto 0) <= StackPointer + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 15=>
effective_memory_pointer(23 downto 16) <= DBR;
effective_memory_pointer(15 downto 0) <= X_REG + DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 16=>
effective_memory_pointer(23 downto 16) <= DBR;
effective_memory_pointer(15 downto 0) <= DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 17=>
effective_memory_pointer(23 downto 16) <= (others => '0');
effective_memory_pointer(15 downto 0) <= DP + memory_pointer(7 downto 0);
pointer_calculation_done := '1';
when 18=>
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
when 19=>
-- These program counter relative operations are calculated in the
-- PC state of execution.
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
when 20=>
-- These program counter relative operations are calculated in the
-- PC state of execution.
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
when 21=>
-- Stack Operations are handled in the stack state or where neccicary
effective_memory_pointer <= X"00" & StackPointer;
pointer_calculation_done := '1';
when 22=>
-- Block operations are not implemented yet
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
when 23 =>
requested_values <= X"00" & memory_pointer;
pointer_calculation_done := '1';
when others =>
effective_memory_pointer <= (others => 'Z');
pointer_calculation_done := '1';
end case;
when s5 =>
pointer_calculation_done := '0';
state_machine_onehot <= "0000000000100000";
if state_machine_onehot = "0000000000100000" then
-- Go to fan out based on type info,
-- if type info is not 0 - 8, then count it
-- as a NOP
--
if type_info = X"0" then
state <= sa;
elsif type_info = X"1" then
state <= sp;
elsif type_info = X"2" then
state <= sm;
elsif type_info = X"3" then
state <= sc;
elsif type_info = X"4" then
state <= sf;
elsif type_info = X"5" then
state <= ss;
elsif type_info = X"6" then
state <= sn;
elsif type_info = X"7" then
state <= se;
elsif type_info = X"8" then
state <= si;
-- if state can not be defined treat it as a NOP
else
state <= sn;
end if;
end if;
when sc =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sc;
end if;
state_machine_onehot <= "0000000001000000";
--
-- Arithmatic State Start
--
when sa =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sa;
end if;
-- ADC
if op_code = X"6D" or
op_code = X"7D" or
op_code = X"79" or
op_code = X"6F" or
op_code = X"7F" or
op_code = X"17" or
op_code = X"65" or
op_code = X"63" or
op_code = X"75" or
op_code = X"72" or
op_code = X"67" or
op_code = X"73" or
op_code = X"61" or
op_code = X"71" or
op_code = X"77" or
op_code = X"69" then
math_temp := ('0' & requested_values(15 downto 0)) + A_REG + ( zeros & C_FLAG);
if ((math_temp = "00000000000000000" ) or (math_temp = "10000000000000000")) then
Z <= '1';
N <= math_temp (15);
V <= math_temp (16);
C_FLAG <= math_temp (16) xor (not math_temp(16));
A_REG <= math_temp(15 downto 0);
math_done <= '1';
elsif math_temp /= "ZZZZZZZZZZZZZZZZZ" then
Z <= '0';
N <= math_temp (15);
V <= math_temp (16);
C_FLAG <= math_temp (16) xor (not math_temp(16));
A_REG <= math_temp(15 downto 0);
math_done <= '1';
end if;
-- AND
elsif op_code = X"2D" or
op_code = X"3E" or
op_code = X"39" or
op_code = X"2F" or
op_code = X"3F" or
op_code = X"25" or
op_code = X"23" or
op_code = X"36" or
op_code = X"32" or
op_code = X"27" or
op_code = X"33" or
op_code = X"91" or
op_code = X"31" or
op_code = X"37" or
op_code = X"29" then
math_temp := '0' & ( A_REG and requested_values(15 downto 0));
if math_temp = "00000000000000000" then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
A_REG <= math_temp(15 downto 0 );
math_done <= '1';
-- ASL
elsif
op_code = X"0E" or
op_code = X"1E" or
op_code = X"06" or
op_code = X"16" then
math_temp := requested_values(15 downto 0) & '0';
C_FLAG <= requested_values(15);
store_back <= '1';
if math_temp(15 downto 0) = "0000000000000000" then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
math_done <= '1';
elsif op_code = X"0A" then
math_temp := A_REG( 15 downto 0) & '0';
C_FLAG <= A_REG(15);
if math_temp(15 downto 0) = ("0000000000000000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
A_REG <= math_temp(15 downto 0);
math_done <= '1';
-- CMP
elsif
op_code = X"CD" or
op_code = X"DD" or
op_code = X"D9" or
op_code = X"CF" or
op_code = X"DF" or
op_code = X"C5" or
op_code = X"C3" or
op_code = X"D5" or
op_code = X"D2" or
op_code = X"C7" or
op_code = X"D3" or
op_code = X"C1" or
op_code = X"D1" or
op_code = X"D7" or
op_code = X"C9" then
math_temp := A_REG - ('0' & requested_values(15 downto 0));
if (A_REG < requested_values) then
C_FLAG <= '0';
else
C_FLAG <= '1';
end if;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
math_done <= '1';
-- CPX
elsif
op_code = X"EC" or
op_code = X"E4" or
op_code = X"E0" then
math_temp := X_REG - ('0' & requested_values(15 downto 0));
if (X_REG < requested_values) then
C_FLAG <= '0';
else
C_FLAG <= '1';
end if;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
math_done <= '1';
-- CPY
elsif
op_code = X"CC" or
op_code = X"C4" or
op_code = X"C0" then
math_temp := Y_REG - ('0' & requested_values(15 downto 0));
if (Y_REG < requested_values) then
C_FLAG <= '0';
else
C_FLAG <= '1';
end if;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
math_done <= '1';
-- DEX
elsif
op_code = X"CA" then
math_temp := '0' & X_REG - 1;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
X_REG <= math_temp(15 downto 0);
math_done <= '1';
-- DEY
elsif
op_code = X"88" then
math_temp := '0' & Y_REG - 1;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
Y_REG <= math_temp(15 downto 0);
math_done <= '1';
-- EOR
elsif
op_code = X"4D" or
op_code = X"5D" or
op_code = X"59" or
op_code = X"4F" or
op_code = X"5F" or
op_code = X"5D" or
op_code = X"45" or
op_code = X"43" or
op_code = X"55" or
op_code = X"52" or
op_code = X"47" or
op_code = X"53" or
op_code = X"41" or
op_code = X"51" or
op_code = X"57" or
op_code = X"49" then
math_temp := '0' & (requested_values(15 downto 0) xor A_REG);
if math_temp = ('0'&(X"0000")) then
Z <= '1';
else
Z <= '0';
end if;
N <= math_temp(15);
store_back <= '1';
math_done <= '1';
-- INX
elsif
op_code = X"E8" then
math_temp := '0' & X_REG + 1;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
X_REG <= math_temp(15 downto 0);
math_done <= '1';
-- INY
elsif
op_code = X"C8" then
math_temp := '0' & Y_REG + 1;
if math_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= math_temp(15);
else
N <= math_temp(15);
Z <= '0';
end if;
Y_REG <= math_temp(15 downto 0);
math_done <= '1';
-- LSR
elsif
op_code = X"4A" then
math_temp := '0' & A_REG;
N <= '0';
C_FLAG <= A_REG(0);
if math_temp = ('0' & X"0000") then
Z <= '0';
else
Z <= '1';
end if;
A_REG <= math_temp (16 downto 1);
math_done <= '1';
elsif
op_code = X"4E" or
op_code = X"5E" or
op_code = X"46" or
op_code = X"56" then
math_temp := '0' & requested_values(15 downto 0);
store_back <= '1';
N <= '0';
C_FLAG <= requested_values(0);
if math_temp = ('0' & X"0000") then
Z <= '0';
else
Z <= '1';
end if;
math_done <= '1';
-- ORA
elsif
op_code = X"0D" or
op_code = X"1D" or
op_code = X"19" or
op_code = X"0F" or
op_code = X"1F" or
op_code = X"05" or
op_code = X"03" or
op_code = X"15" or
op_code = X"12" or
op_code = X"07" or
op_code = X"13" or
op_code = X"01" or
op_code = X"11" or
op_code = X"17" or
op_code = X"09" then
math_temp := '0' & (requested_values(15 downto 0) or A_REG);
A_REG <= math_temp(15 downto 0);
if math_temp = ('0' & X"0000") then
Z <= '1';
else
Z <= '0';
end if;
N <= math_temp(15);
store_back <= '1';
math_done <= '1';
-- ROL
elsif
op_code = X"2A" then
math_temp := A_REG & C_FLAG;
C_FLAG <= A_REG (15);
N <= math_temp(15);
if math_temp(16 downto 1) = X"0000" then
Z <= '1';
else
Z <= '0';
end if;
A_REG <= math_temp (15 downto 0);
math_done <= '1';
elsif
op_code = X"2E" or
op_code = X"3E" or
op_code = X"26" or
op_code = X"36" then
math_temp := requested_values(15 downto 0) & C_FLAG;
C_FLAG <= A_REG (15);
N <= math_temp(15);
store_back <= '1';
if math_temp(16 downto 1) = (X"0000") then
Z <= '1';
else
Z <= '0';
end if;
math_done <= '1';
-- ROR
elsif
op_code = X"6A" then
math_temp := C_FLAG & A_REG;
C_FLAG <= A_REG (0);
N <= math_temp(15);
if math_temp(16 downto 1) = (X"0000") then
Z <= '1';
else
Z <= '0';
end if;
A_REG <= math_temp (16 downto 1);
math_done <= '1';
elsif
op_code = X"6E" or
op_code = X"7E" or
op_code = X"66" or
op_code = X"76" then
math_temp := C_FLAG & requested_values(15 downto 0) ;
C_FLAG <= requested_values (0);
N <= math_temp(15);
store_back <= '1';
if math_temp(16 downto 1) = (X"0000") then
Z <= '1';
else
Z <= '0';
end if;
math_done <= '1';
-- SBC
elsif
op_code = X"ED" or
op_code = X"FD" or
op_code = X"F9" or
op_code = X"FF" or
op_code = X"E5" or
op_code = X"E3" or
op_code = X"F5" or
op_code = X"F2" or
op_code = X"E7" or
op_code = X"F3" or
op_code = X"E1" or
op_code = X"F1" or
op_code = X"F7" or
op_code = X"E9" then
math_temp := A_REG - ('0' & requested_values(15 downto 0)) - ( ('0' & zeros) & C_FLAG);
if ((math_temp = ('0' & X"0000")) or (math_temp = "10000000000000000")) then
Z <= '1';
N <= math_temp (15);
V <= math_temp (16);
C_FLAG <= math_temp (16) xor (not math_temp(16));
else
Z <= '0';
N <= math_temp (15);
V <= math_temp (16);
C_FLAG <= math_temp (16) xor (not math_temp(16));
end if;
A_REG <= math_temp(15 downto 0);
math_done <= '1';
end if;
if (store_back = '1') and (math_done = '1') then
write_back_value <= math_temp (15 downto 0);
write_back_location <= effective_memory_pointer;
state_machine_onehot <= "0000000001000000";
elsif math_done = '1' then
state_machine_onehot <= "0000000001000000";
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END OF ARITHMATIC STATE
--
--
-- START MEMORY MANIPULATION STATE
--
when sm =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sm;
end if;
-- DEC
if op_code = X"CE" or
op_code= X"DE" or
op_code= X"C6" or
op_code= X"D6" then
mem_temp := '0' & requested_values(15 downto 0) - 1 ;
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
write_back_value <= mem_temp(15 downto 0);
memory_done <= '1';
store_back <= '1';
elsif op_code = X"3A" then
mem_temp := '0' & A_REG - 1 ;
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
A_REG <= mem_temp(15 downto 0);
memory_done <= '1';
-- INC
elsif op_code= X"1A" then
mem_temp := '0' & A_REG + 1 ;
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
A_REG <= mem_temp(15 downto 0);
memory_done <= '1';
elsif op_code = X"EE" or
op_code= X"FE" or
op_code= X"E6" or
op_code= X"F6" then
mem_temp := '0' & requested_values(15 downto 0) + 1 ;
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
write_back_value <= mem_temp(15 downto 0);
memory_done <= '1';
store_back <= '1';
-- LDA
elsif op_code = X"AD" or
op_code= X"BD" or
op_code = X"B9" or
op_code = X"AF" or
op_code = X"BF" or
op_code = X"A5" or
op_code = X"A3" or
op_code = X"B5" or
op_code = X"B2" or
op_code = X"A7" or
op_code = X"B3" or
op_code = X"A1" or
op_code = X"B1" or
op_code = X"B7" then
mem_temp := '0' & requested_values(15 downto 0);
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
A_REG <= mem_temp(15 downto 0);
memory_done <= '1';
elsif op_code = X"A9" then
mem_temp := '0' & requested_values(15 downto 0);
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
A_REG <= mem_temp(15 downto 0);
memory_done <= '1';
-- LDX
elsif op_code = X"AE" or
op_code= X"BE" or
op_code= X"A6" or
op_code= X"B6" or
op_code= X"A2" then
mem_temp := '0' & requested_values(15 downto 0);
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
X_REG <= mem_temp(15 downto 0);
memory_done <= '1';
-- LDY
elsif op_code = X"AC" or
op_code= X"BC" or
op_code= X"A4" or
op_code= X"B4" or
op_code= X"A0" then
mem_temp := '0' & requested_values(15 downto 0);
if mem_temp (15 downto 0) = (X"0000") then
Z <= '1';
N <= mem_temp(15);
else
N <= mem_temp(15);
Z <= '0';
end if;
Y_REG <= mem_temp(15 downto 0);
memory_done <= '1';
-- STA
elsif op_code = X"8D" or
op_code= X"9D" or
op_code= X"8F" or
op_code= X"9F" or
op_code= X"85" or
op_code= X"83" or
op_code= X"95" or
op_code= X"92" or
op_code= X"87" or
op_code= X"93" or
op_code= X"81" or
op_code= X"91" or
op_code= X"97" then
mem_temp := '0' & A_REG;
write_back_value <= mem_temp(15 downto 0);
store_back <= '1';
memory_done <= '1';
-- STX
elsif op_code = X"8E" or
op_code= X"86" or
op_code= X"96" then
mem_temp := '0' & X_REG;
write_back_value <= mem_temp(15 downto 0);
store_back <= '1';
memory_done <= '1';
-- STY
elsif op_code = X"8C" or
op_code= X"84" or
op_code= X"94" then
mem_temp :='0' & Y_REG;
write_back_value <= mem_temp(15 downto 0);
store_back <= '1';
memory_done <= '1';
end if;
if (memory_done = '1') and (store_back = '1') then
state_machine_onehot <= "0000000001000000";
write_back_location <= effective_memory_pointer;
elsif (memory_done = '1') and (store_back = '0') then
state_machine_onehot <= "0000000001000000";
store_back <= '0';
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END MEMORY MANIPULATION STATE
--
--
-- START PC MANIPULATION STATE
--
when sp =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sp;
end if;
-- BCC
if op_code = X"90" then
if C_FLAG = '0' then
PC <= PC + std_logic_vector((resize(signed(memory_pointer(7 downto 0)), 16)));
else
PC <= PC;
end if;
pc_done <= '1';
-- BEQ
elsif op_code = X"F0" then
if Z = '1' then
PC <= PC + std_logic_vector((resize(signed(memory_pointer(7 downto 0)), 16)));
else
PC <= PC;
end if;
pc_done <= '1';
-- BMI
elsif op_code = X"30" then
if N = '1' then
PC <= PC + std_logic_vector(resize(signed(memory_pointer(7 downto 0)), 16));
else
PC <= PC;
end if;
pc_done <= '1';
-- BNE
elsif op_code = X"D0" then
if Z = '0' then
PC <= PC + std_logic_vector(resize(signed(memory_pointer(7 downto 0)), 16));
else
PC <= PC;
end if;
pc_done <= '1';
-- BPL
elsif op_code = X"10" then
if N = '0' then
PC <= PC + std_logic_vector(resize(signed(memory_pointer(7 downto 0)), 16));
else
PC <= PC;
end if;
pc_done <= '1';
-- BVC
elsif op_code = X"50" then
if V = '0' then
PC <= PC + std_logic_vector(resize(signed(memory_pointer(7 downto 0)), 16));
else
PC <= PC;
end if;
pc_done <= '1';
-- BVS
elsif op_code = X"70" then
if V = '1' then
PC <= PC + std_logic_vector(resize(signed(memory_pointer(7 downto 0)), 16));
else
PC <= PC;
end if;
pc_done <= '1';
-- JMP
elsif
op_code = X"4C" then
PC <= effective_memory_pointer;
pc_done <= '1';
elsif
op_code = X"5C" then
PC <= requested_values(23 downto 0);
pc_done <= '1';
elsif
op_code = X"6C" or
op_code = X"7C" then
PC <= requested_values(23 downto 0);
pc_done <= '1';
-- JSR
elsif op_code = X"20" or
op_code = X"FC" then
write_back_value <= ProgramCntr;
write_back_bank <= PBR;
PC <= requested_values(23 downto 0);
push_to_stack <= '1';
pc_done <= '1';
-- RTS
elsif op_code = X"60" then
ProgramCntr <= requested_values(15 downto 0);
StackPointer <= StackPointer - 2;
pc_done <= '1';
end if;
if (pc_done = '1') then
state_machine_onehot <= "0000000001000000";
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END PC MANIPULATION STATE
--
--
-- START FLAGC MANIPULATION STATE
--
when sf =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sf;
end if;
-- BIT
if op_code = X"2C" or
op_code = X"3C" or
op_code = X"24" or
op_code = X"34" then
flag_temp := '0' & (A_REG and requested_values(15 downto 0));
if flag_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= flag_temp(15);
V <= flag_temp(14);
else
V <= flag_temp(14);
N <= flag_temp(15);
Z <= '0';
end if;
flag_done <= '1';
elsif op_code = X"89" then
flag_temp := '0' & (A_REG and requested_values(15 downto 0));
if flag_temp(15 downto 0) = (X"0000") then
Z <= '1';
else
Z <= '0';
end if;
flag_done <= '1';
-- CLC
elsif op_code = X"18" then
C_FLAG <= '0';
flag_done <= '1';
-- CLD
elsif op_code = X"D8" then
D_FLAG <= '0';
flag_done <= '1';
-- CLI
elsif op_code = X"58" then
I <= '0';
flag_done <= '1';
-- CLV
elsif op_code = X"B8" then
V <= '0';
flag_done <= '1';
-- SEC
elsif op_code = X"38" then
C_FLAG <= '1';
flag_done <= '1';
-- SED
elsif op_code = X"F8" then
D_FLAG <= '0';
flag_done <= '1';
-- SEI
elsif op_code = X"78" then
I <= '1';
flag_done <= '1';
end if;
if flag_done = '1' then
state_machine_onehot <= "0000000001000000";
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END FLAG MANIPULATION STATE
--
--
-- STACK MANIPULATION STATE
--
when ss =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= ss;
end if;
-- PHA
if op_code = X"48" then
StackPointer <= StackPointer + 2;
push_to_stack <= '1';
write_back_value <= A_REG;
stack_done <= '1';
-- PHP
elsif op_code = X"08" then
StackPointer <= StackPointer + 1;
push_to_stack <= '1';
write_back_value <= X"00" & P;
stack_done <= '1';
-- PLA
elsif op_code = X"68" then
StackPointer <= StackPointer - 2;
stack_temp := '0' & requested_values(15 downto 0);
if stack_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= stack_temp(15);
else
N <= stack_temp(15);
Z <= '0';
end if;
A_REG <= stack_temp(15 downto 0);
stack_done <= '1';
-- PLP
elsif op_code = X"28" then
StackPointer <= StackPointer - 1;
stack_temp := '0' & requested_values(15 downto 0);
if stack_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= stack_temp(15);
else
N <= stack_temp(15);
Z <= '0';
end if;
P <= stack_temp(7 downto 0);
stack_done <= '1';
end if;
if (stack_done = '1') and (store_back = '1') then
write_back_location <= effective_memory_pointer;
state_machine_onehot <= "0000000001000000";
elsif (stack_done = '1') then
state_machine_onehot <= "0000000001000000";
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END STACK MANIPULATION STATE
--
--
-- START NOP STATE
--
when sn =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= sn;
end if;
state_machine_onehot <= "0000000001000000";
--
-- END NOP STATE
--
--
-- START EXCHANGE STATE
--
when se =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= se;
end if;
-- TAX
if op_code = X"AA" then
xfr_temp := '0' & A_REG;
if xfr_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= xfr_temp(15);
else
N <= xfr_temp(15);
Z <= '0';
end if;
X_REG <= xfr_temp(15 downto 0);
exchange_done <= '1';
-- TAY
elsif op_code = X"AB" then
xfr_temp := '0' & A_REG;
if xfr_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= xfr_temp(15);
else
N <= xfr_temp(15);
Z <= '0';
end if;
Y_REG <= xfr_temp(15 downto 0);
exchange_done <= '1';
-- TYA
elsif op_code = X"98" then
xfr_temp := '0' & Y_REG;
if xfr_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= xfr_temp(15);
else
N <= xfr_temp(15);
Z <= '0';
end if;
A_REG <= xfr_temp(15 downto 0);
exchange_done <= '1';
-- TSX
elsif op_code = X"BA" then
xfr_temp := '0' & StackPointer;
if xfr_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= xfr_temp(15);
else
N <= xfr_temp(15);
Z <= '0';
end if;
X_REG <= xfr_temp(15 downto 0);
exchange_done <= '1';
-- TXA
elsif
op_code = X"8A" then
xfr_temp := '0' & X_REG;
if xfr_temp(15 downto 0) = (X"0000") then
Z <= '1';
N <= xfr_temp(15);
else
N <= xfr_temp(15);
Z <= '0';
end if;
A_REG <= xfr_temp(15 downto 0);
exchange_done <= '1';
-- TXS
elsif
op_code = X"9A" then
xfr_temp := '0' & X_REG;
StackPointer <= xfr_temp(15 downto 0);
exchange_done <= '1';
end if;
if (exchange_done = '1') then
state_machine_onehot <= "0000000001000000";
else
state_machine_onehot <= state_machine_onehot;
end if;
--
-- END EXCHANGE STATE
--
--
-- START INTERUPT STATE
--
when si =>
if state_machine_onehot = "0000000001000000" then
state <= s6;
else
state <= si;
end if;
-- RTI
if op_code = X"40" then
ProgramCntr <= requested_values(23 downto 8);
P <= requested_values(7 downto 0);
end if;
state_machine_onehot <= "0000000001000000";
--
-- END INTRRUPT STATE
--
when s6 =>
if (state_machine_onehot = "0000000010000000") and (ready_up = '1') then
state <= s0;
else
state <= state;
end if;
math_done <= '0';
memory_done <= '0';
pc_done <= '0';
flag_done <= '0';
stack_done <= '0';
exchange_done <= '0';
if (store_back = '1') then
READ_OUT <= write_back_value;
ADDRESS_OUT <= write_back_location;
store_back <= '0';
check_done := '1';
RW <= '1';
state_machine_onehot <= "0000000010000000";
elsif (push_to_stack = '1') then
read_out <= write_back_value;
read_out_bank <= write_back_bank;
address_out <= X"00" & StackPointer;
push_to_stack <= '0';
check_done := '1';
RW <= '1';
state_machine_onehot <= "0000000010000000";
else
check_done := '1';
state_machine_onehot <= "0000000010000000";
end if;
when others =>
state_machine_onehot <= "0000000000000010";
end case;
end if;
end process;
--
-- This process will look at the opcode
-- and determine the addressing mode of
-- the specific instruction being requested
-- and then pass it onto the adr_type vector.
--
Addressing_Mode:
process (addressing_on) is
begin
addressing_done <= '0';
if (addressing_on = '1') then
-- Refer to 65000 Programmers Manual for explanation
-- of addressing modes.
--
-- Symbol Addressing Mode Symbol Addressing Mode
-- 0 -> a absolute
-- 1 -> A_REG accumulator
-- 2 -> a,x absolute indexed with X
-- 3 -> a,y absolute indexed with Y_REG
-- 4 -> al absolute long
-- 5 -> al,x absolute long indexed
-- 6 -> (a) absolute indirect
-- 7 -> (a,x) absolute indexed indirect
-- 8 -> d direct
-- 9 -> d,s stack relative
-- 10 -> d,x direct indexed with x
-- 11 -> d,y direct indexed with y
-- 12 -> (d) direct indirect
-- 13 -> [d] direct indirect long
-- 14 -> (d,s),y stack relative indirect indexed
-- 15 -> (d,x) direct indexed indirect
-- 16 -> (d),y direct indirect indexed
-- 17 -> [d].y direct indirect long indexed
-- 18 -> i implied
-- 19 -> r program counter relative
-- 20 -> rl program counter relative long
-- 21 -> s stack
-- 22 -> xyc block move
-- 23 -> # immediate
--
--
case op_code is
when X"6d" | X"2d" | X"0e" | X"2c" | X"cd" | X"ec" | X"cc" | X"ce" | X"4d" | X"ee" | X"4c" | X"20" | X"ad" | X"ae" | X"ac" | X"4e" | X"0d" | X"2e" | X"6e" | X"ed" | X"8d" | X"8e" | X"8c" | X"9c" | X"1c" | X"0c" =>
adr_type <= 0;
when X"0a" | X"3A" | X"1a" | X"4a" | X"2a" | X"6a" | X"3b" | X"ba" | X"8a" | X"9a" | X"9b" | X"98" | X"bb" | X"cb" | X"42" | X"eb" | X"fb" =>
adr_type <= 1;
when X"7d" | X"3e" | X"1e" | X"3c" | X"dd" | X"de" | X"5d" | X"fe" | X"bd" | X"bc" | X"5e" | X"1d" | X"7e" | X"fd" | X"9d" | X"9e" =>
adr_type <= 2;
when X"6f" | X"2f" | X"cf" | X"4f" | X"5c" | X"22" | X"af" | X"0f" | X"8f" =>
adr_type <= 3;
when X"79" | X"39" | X"d9" | X"59" | X"b9" | X"be" | X"19" | X"f9" =>
adr_type <= 4;
when X"7f" | X"3f" | X"df" | X"5f" | X"bf" | X"1f" | X"ff" | X"9f" =>
adr_type <= 5;
when X"dc" | X"6c" =>
adr_type <= 6;
when X"7c" | X"fc" =>
adr_type <= 7;
when X"65" | X"25" | X"06" | X"24" | X"c5" | X"e4" | X"c4" | X"c6" | X"45" | X"e6" | X"a5" | X"a6" | X"a4" | X"46" | X"05" | X"26" | X"66" | X"e5" | X"85" | X"86" | X"84" | X"64" | X"14" | X"04" =>
adr_type <= 8;
when X"63" | X"23" | X"c3" | X"43" | X"a3" | X"03" | X"e3" | X"83" =>
adr_type <= 9;
when X"75" | X"36" | X"16" | X"34" | X"d5" | X"d6" | X"55" | X"f6" | X"b5" | X"b4" | X"56" | X"15" | X"76" | X"f5" | X"95" | X"94" | X"74" =>
adr_type <= 10;
when X"b6" | X"96" =>
adr_type <= 11;
when X"72" | X"32" | X"d2" | X"52" | X"b2" | X"12" | X"f2" | X"92" =>
adr_type <= 12;
when X"67" | X"27" | X"c7" | X"47" | X"a7" | X"07" | X"e7" | X"87" =>
adr_type <= 13;
when X"73" | X"33" | X"d3" | X"53" | X"b3" | X"13" | X"f3" | X"93" =>
adr_type <= 14;
when X"61" | X"c1" | X"41" | X"a1" | X"01" | X"e1" | X"81" =>
adr_type <= 15;
when X"71" | X"31" | X"d1" | X"51" | X"b1" | X"11" | X"f1" | X"91" =>
adr_type <= 16;
when X"77" | X"37" | X"d7" | X"57" | X"b7" | X"17" | X"f7" | X"97" =>
adr_type <= 17;
when X"18" | X"d8" | X"58" | X"b8" | X"ca" | X"88" | X"e8" | X"c8" | X"ea" | X"38" | X"f8" | X"78" | X"db" | X"aa" | X"5b" | X"1b" | X"7b" =>
adr_type <= 18;
when X"b0" | X"f0" | X"90" | X"d0" | X"10" | X"80" | X"50" | X"70" =>
adr_type <= 19;
when X"82" =>
adr_type <= 20;
when X"00" | X"02" | X"f4" | X"d4" | X"62" | X"48" | X"8b" | X"0b" | X"4b" | X"08" | X"da" | X"5a" | X"68" | X"ab" | X"2b" | X"28" | X"fa" | X"7a" | X"40" | X"6b" | X"60" =>
adr_type <= 21;
when X"54" | X"44" =>
adr_type <= 22;
when X"69" | X"29" | X"89" | X"c9" | X"e0" | X"c0" | X"49" | X"a9" | X"a2" | X"a0" | X"09" | X"c2" | X"e9" | X"e2" =>
adr_type <= 23;
when others =>
adr_type <= 0;
end case;
addressing_done <= '1';
end if;
end process;
--
-- This process reverses the byte order
-- of instruction arguments so that
-- a memory pointer or argument can
-- be precisely used
--
memory_pointer_calculation:
process (memory_calculate_on) is
begin
memory_calculate_done <= '0';
if memory_calculate_on = '1' then
case instruction_size is
when X"2" =>
memory_pointer <= X"0000" & chunk_pull (23 downto 16);
when X"3" =>
memory_pointer <= X"00" & chunk_pull (23 downto 16) & chunk_pull(15 downto 8);
when X"4" =>
memory_pointer <= chunk_pull (23 downto 16) & chunk_pull(15 downto 8) & chunk_pull (7 downto 0);
when others =>
memory_pointer <= (others => '0');
end case;
memory_calculate_done <= '1';
end if;
end process;
--
-- This process will decode the OPcode byte.
-- It will then assign instruction_info all relevent data.
--
opcode_info:
process (decode_on) is
begin
decode_done <= '0';
if reset = '1' then
instruction_info <= (others => '0');-- clear instruction info
elsif (decode_on = '1') then
--
--
-- intstruction_info syntax is
-- bytes + cycles + type
--
-- Flags (on reset) :
-- N V M X D I Z C_FLAG/E
-- P = * * 1 1 0 1 * */1
-- * = Not Initialized
-- STP and WAI instructions are cleared.
-- Type Table:
-- 0 -> Arithmatic
-- 1 -> PC
-- 2 -> Memory
-- 3 -> Coprocessor
-- 4 -> Flag
-- 5 -> Stack
-- 6 -> NOP (and non used)
-- 7 -> Exchange
-- 8 -> Interrupt
--
--
--
--
case op_code is
--
-- BRK (break)
-- pc+2 onto stack, processor status onto stack
-- Also set I flag = 1
--
-- !!!!!!!!!!!!! TODO: Implemented as a NOP for now due to issues with interrupts
-- !!!!!!!!!!!!!!!!!!!!!!!!!!! X"270" is now X"126"
when X"00" =>
instruction_info <= X"126";
-- ADC
-- The following are Add memory to accumulator with cary
-- A_REG + M + C_FLAG -> A_REG, C_FLAG
--
when X"69" =>
instruction_info <= X"220";
when X"65" =>
instruction_info <= X"230";
when X"75" =>
instruction_info <= X"240";
when X"6D" =>
instruction_info <= X"340";
when X"7D" =>
instruction_info <= X"340";
when X"79" =>
instruction_info <= X"340";
when X"61" =>
instruction_info <= X"260";
when X"71" =>
instruction_info <= X"250";
-- AND
-- The follwing are logical AND's with accumulator
-- A_REG and M -> A_REG
--
--
when X"29" =>
instruction_info <= X"220";
when X"25" =>
instruction_info <= X"230";
when X"35" =>
instruction_info <= X"240";
when X"2D" =>
instruction_info <= X"340";
when X"3D" =>
instruction_info <= X"340";
when X"39" =>
instruction_info <= X"340";
when X"21" =>
instruction_info <= X"260";
when X"31" =>
instruction_info <= X"250";
--
-- The following are ASL
-- left shift by one
-- memory or accumulator
--
when X"0A" =>
instruction_info <= X"120";
when X"06" =>
instruction_info <= X"250";
when X"16" =>
instruction_info <= X"260";
when X"0E" =>
instruction_info <= X"360";
when X"1E" =>
instruction_info <= X"370";
-- BCC
-- Branch on carry clear
-- when carry flag = 0, branch
-- * + 1 cycle if branch happens
when X"90" =>
instruction_info <= X"221";
-- BEQ
-- branch on zero flag set
-- * + 1 cycle if branch happens
when X"F0" =>
instruction_info <= X"221";
-- BIT
-- Accumulator AND'd with memory,
-- bit 7 of memory goes to Negative flag
-- bit 6 of memoyr goes to overflow flag
-- If A_REG and M = 0 then Z = 1 , else 0
when X"24" =>
instruction_info <= X"234";
when X"2C" =>
instruction_info <= X"344";
-- BMI
-- Branch On Negative Flag Set
-- * + 1 Cycle If Can Branch
when X"30" =>
instruction_info <= X"221";
-- BNE
-- Branch on zero flag not set
-- * + 1 cycle if can do
--
when X"D0" =>
instruction_info <= X"221";
-- BPL
-- Brnach when N flag not set.
-- * + 1 cycle if can do
--
when X"10" =>
instruction_info <= X"221";
-- BVC
-- Branch on V flag = 0
-- * +1 cycle if can do
when X"50" =>
instruction_info <= X"221";
-- BVS
-- Branch when V flag set
-- * + 1 cycle if can do
when X"70" =>
instruction_info <= X"221";
-- CLC
-- Clear the carry flag
--
when X"18" =>
instruction_info <= X"124";
-- CLD
-- Clear the decimal flag
--
when X"D8" =>
instruction_info <= X"124";
-- CLI
-- Clear interupt bit
--
when X"58" =>
instruction_info <= X"124";
-- CLV
-- Clear the overflow flag
--
when X"B8" =>
instruction_info <= X"124";
-- CMP
-- Compar memory and accumulator
-- Set N, Z, or C_FLAG flag accordingly
-- A_REG - M
--
when X"c9" =>
instruction_info <= X"220";
when X"c5" =>
instruction_info <= X"230";
when X"D5" =>
instruction_info <= X"240";
when X"DD" =>
instruction_info <= X"340";
when X"d9" =>
instruction_info <= X"340";
when X"c1" =>
instruction_info <= X"260";
when X"d1" =>
instruction_info <= X"250";
-- CPX
-- Compary memory and X reg
-- X - M and set N, Z, C_FLAG flags as needed
--
when X"E0" =>
instruction_info <= X"220";
when X"E4" =>
instruction_info <= X"230";
when X"EC" =>
instruction_info <= X"340";
-- CPY
-- Compary memory and Y_REG reg
-- Y_REG - M
-- Set N, Z, and C_FLAG flags as needed.
--
when X"C0" =>
instruction_info <= X"220";
when X"C4" =>
instruction_info <= X"230";
when X"cc" =>
instruction_info <= X"340";
-- DEC
-- Decrimeent memory by 1
-- M - 1 -> M
-- Use N & Z flags
when X"C6" =>
instruction_info <= X"252";
when X"D6" =>
instruction_info <= X"262";
when X"ce" =>
instruction_info <= X"362";
when X"de" =>
instruction_info <= X"372";
-- DEX
-- Decriment X reg by 1
-- X - 1 -> X
-- use N & Z flags
when X"CA" =>
instruction_info <= X"120";
-- DEY
-- Decriment Y_REG reg by 1
-- Y_REG - 1 -> Y_REG
-- N & Z flags
--
when X"88" =>
instruction_info <= X"120";
-- EOR
-- Acc XOR Mem -> Acc
-- N and Z flags
--
when X"49" =>
instruction_info <= X"220";
when X"45" =>
instruction_info <= X"230";
when X"55" =>
instruction_info <= X"240";
when X"4d" =>
instruction_info <= X"340";
when X"5d" =>
instruction_info <= X"340";
when X"59" =>
instruction_info <= X"340";
when X"41" =>
instruction_info <= X"260";
when X"51" =>
instruction_info <= X"250";
-- INC
-- Incriment memory by one
-- M + 1 -> M
-- N & Z flags
--
when X"E6" =>
instruction_info <= X"252";
when X"F6" =>
instruction_info <= X"262";
when X"ee" =>
instruction_info <= X"362";
when X"fe" =>
instruction_info <= X"372";
-- INX
-- Incriment X by one
-- X + 1 -> X
-- N & Z flags
--
when X"e8" =>
instruction_info <= X"120";
-- INY
-- Incriment Y_REG by one
-- Y_REG + 1 -> Y_REG
-- N & Z flags
--
when X"c8" =>
instruction_info <= X"120";
--
--
-- JMP
-- JUMP INSTRUCTIONS
--=======================================================================
-- JMP
-- Jump to location
-- PC + 1 -> PCL
-- PC + 2 -> PCH
--JMP absolute
--take contents of memory location
--1 byte from opcode and store into
--PC LOW, then take the very next byte
--and store into PC HIGH
-- REVERSE BYTE ORDER AND MAKE NEW PC
when X"4c" =>
instruction_info <= X"331";
--JMP indirect
-- starts out the same as above, but
-- instead of getting the opcode at the new PC,
-- a new PC is again fetched in the same way.
-- making this a jump to a jump.
when X"6c" =>
instruction_info <= X"351";
--=======================================================================
--
--
--
--
-- JSR
-- Jump to subroutine
-- PC + 2 -> stack
-- PC + 1 -> PCL
-- PC + 2 -> PCH
--
when X"20" =>
instruction_info <= X"361";
-- LDA
-- Load accumulator with memory
-- M -> A_REG
-- N & Z flags
when X"a9" =>
instruction_info <= X"222";
when X"a5" =>
instruction_info <= X"232";
when X"b5" =>
instruction_info <= X"242";
when X"ad" =>
instruction_info <= X"342";
when X"bd" =>
instruction_info <= X"342";
when X"b9" =>
instruction_info <= X"342";
when X"a1" =>
instruction_info <= X"262";
when X"b1" =>
instruction_info <= X"252";
-- LDX
-- Load X with memory
-- M -> X
-- N & Z flags
--
when X"a2" =>
instruction_info <= X"222";
when X"a6" =>
instruction_info <= X"232";
when X"b6" =>
instruction_info <= X"242";
when X"ae" =>
instruction_info <= X"342";
when X"be" =>
instruction_info <= X"342";
-- LDY
-- Load Y_REG with memory
-- M -> Y_REG
-- N & Z Flags
--
when X"a0" =>
instruction_info <= X"222";
when X"a4" =>
instruction_info <= X"232";
when X"b4" =>
instruction_info <= X"242";
when X"ac" =>
instruction_info <= X"342";
when X"bc" =>
instruction_info <= X"342";
-- LSR
-- Right shift one bit
-- 0 -> [bits] -> C_FLAG
-- C_FLAG & Z flag, N flag zerod
--
when X"4a" =>
instruction_info <= X"120";
when X"46" =>
instruction_info <= X"250";
when X"56" =>
instruction_info <= X"260";
when X"4e" =>
instruction_info <= X"360";
when X"5e" =>
instruction_info <= X"370";
-- NOP
-- No operation
--
when X"ea" =>
instruction_info <= X"126";
-- ORA
-- Or with accumulator
-- A_REG (or) M -> A_REG
-- N & Z flags
--
when X"09" =>
instruction_info <= X"220";
when X"05" =>
instruction_info <= X"230";
when X"15" =>
instruction_info <= X"240";
when X"0d" =>
instruction_info <= X"340";
when X"1d" =>
instruction_info <= X"340";
when X"19" =>
instruction_info <= X"340";
when X"01" =>
instruction_info <= X"260";
when X"11" =>
instruction_info <= X"250";
-- PHA
-- Push accumuator to stack
-- A_REG -> STACK
-- NO FLAGS
when X"48" =>
instruction_info <= X"135";
-- PHP
-- Push processor status on stack
-- P -> STACK
when X"08" =>
instruction_info <= X"135";
-- PLA
-- Pull accumulator from stack
-- STACK -> A_REG
-- N & Z flags
--
when X"68" =>
instruction_info <= X"145";
-- PLP
-- Pull processor status from stack
-- STACK -> P
-- ALL FLAGS CAN CHANGE
when X"28" =>
instruction_info <= X"145";
-- ROL
-- Rotate one bit left
-- [bit 7] -> C_FLAG FLAG
-- [ <- bits 6 - 0] [C_FLAG FLAG (becomes 0 bit)]
-- N & Z & C_FLAG FLAGS
--
when X"2a" =>
instruction_info <= X"120";
when X"26" =>
instruction_info <= X"250";
when X"36" =>
instruction_info <= X"260";
when X"2e" =>
instruction_info <= X"360";
when X"3e" =>
instruction_info <= X"270";
-- ROR
-- Rotate right one
-- [C_FLAG FLAG -> bit 7] [bits 7 - 1 ] [bit 0 becomes C_FLAG flag]
-- N & Z & C_FLAG
--
when X"6a" =>
instruction_info <= X"120";
when X"66" =>
instruction_info <= X"250";
when X"76" =>
instruction_info <= X"260";
when X"6e" =>
instruction_info <= X"360";
when X"7e" =>
instruction_info <= X"370";
-- RTI
-- Return from Interrupt
-- STACK -> P
-- STACK -> PC
-- FLAGS FROM STACK
--
when X"40" =>
instruction_info <= X"168";
-- RTS
-- Reutrn from subroutine
-- STACK -> PC
-- PC + 1 -> PC
-- NO FLAGS
--
when X"60" =>
instruction_info <= X"161";
-- SBC
-- Subtract memory from accumulator w/ borrow
-- A_REG - M - (not) C_FLAG -> Accumulator
-- N & Z & C_FLAG & V Flags
--
when X"e9" =>
instruction_info <= X"220";
when X"e5" =>
instruction_info <= X"230";
when X"f5" =>
instruction_info <= X"240";
when X"ed" =>
instruction_info <= X"340";
when X"fd" =>
instruction_info <= X"340";
when X"f9" =>
instruction_info <= X"340";
when X"e1" =>
instruction_info <= X"260";
when X"f1" =>
instruction_info <= X"250";
-- SEC
-- Set carry flag
-- 1 -> C_FLAG
-- C_FLAG Flag
--
when X"38" =>
instruction_info <= X"124";
-- SED
-- Set decimal flag
-- 1 -> D
-- D flag
--
when X"f8" =>
instruction_info <= X"124";
-- SEI
-- Set interrupt disable flag
-- 1 -> I
-- I FLAG
when X"78" =>
instruction_info <= X"124";
-- STA
-- Store accumulator in memory
-- A_REG -> M
-- no flags
--
when X"85" =>
instruction_info <= X"232";
when X"95" =>
instruction_info <= X"242";
when X"8d" =>
instruction_info <= X"342";
when X"9d" =>
instruction_info <= X"352";
when X"99" =>
instruction_info <= X"352";
when X"81" =>
instruction_info <= X"262";
when X"91" =>
instruction_info <= X"262";
-- STX
-- Store X in memory
-- X -> M
--
when X"86" =>
instruction_info <= X"232";
when X"96" =>
instruction_info <= X"242";
when X"8e" =>
instruction_info <= X"342";
-- STY
-- Store y in memory
-- Y_REG -> M
--
when X"84" =>
instruction_info <= X"232";
when X"94" =>
instruction_info <= X"242";
when X"8c" =>
instruction_info <= X"342";
-- TAX
-- Transfer A_REG to X
-- A_REG -> X
-- N & Z
--
when X"AA" =>
instruction_info <= X"127";
-- TAY
-- X-fer A_REG to Y_REG
-- A_REG -> Y_REG
-- N & Z
--
when X"a8" =>
instruction_info <= X"127";
-- TYA
-- X-fer Y_REG to A_REG
-- Y_REG -> A_REG
-- N & Z
--
when X"98" =>
instruction_info <= X"127";
-- TSX
-- X-fer stack pointer to X
-- S -> X
-- N & Z
--
when X"ba" =>
instruction_info <= X"127";
-- TXA
-- X-fer X to Accumulator
-- X -> A_REG
-- N & Z
--
when X"8A" =>
instruction_info <= X"127";
-- TXS
-- X-fer X to stack pointer
-- X -> S
--
when X"9a" =>
instruction_info <= X"127";
-- XBA
-- Exchange B & A_REG Accumulators
-- A_REG <-> B
-- Remeber that A_REG is the lower 8 bits of C_FLAG
-- and that B is the upper 8 bits of C_FLAG
--
when X"EB" =>
instruction_info <= X"137";
-- XCE
-- Exchange Carry and Emulation flags
-- E Flag <-> C_FLAG Flag
-- Even though this manipulates
-- flag bits, note that it is
-- EXCHANGE type instruction for
-- this implementation.
--
when X"FB" =>
instruction_info <= X"127";
--
-- All other instructions are NOP's
--
when others =>
instruction_info <= X"126";
end case;
decode_done <= '1';
end if;
end process;
end architecture;
|
-- rc filter test bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity rc_filt_tb is
end rc_filt_tb;
architecture behav of rc_filt_tb is
component rc_filt
generic (
time_const : positive;
iowidth : positive;
procwidth : positive;
pd_min : std_logic;
pd_max : std_logic
);
port (
clk : in std_logic;
inclk : in std_logic;
outclk : out std_logic;
rst : in std_logic;
d : in std_logic_vector(iowidth-1 downto 0);
q : out std_logic_vector(iowidth-1 downto 0)
);
end component;
signal clk : std_logic := '0';
signal inclk : std_logic := '0';
signal outclk : std_logic;
signal rst : std_logic := '1';
signal d : std_logic_vector(7 downto 0) := (others => '0');
signal q : std_logic_vector(7 downto 0);
begin
dut : rc_filt
generic map (time_const => 10, iowidth => 8, procwidth => 12, pd_min => '0', pd_max => '0')
port map (clk, inclk, outclk, rst, d, q);
clk <= not clk after 50 ns;
rst <= '0' after 200 ns;
in_file : process
variable input : integer;
variable l : line;
file vector_file : text is in "rc_filt_test.txt";
begin
wait until rst <= '0';
while not endfile(vector_file) loop
readline(vector_file, l);
read(l, input);
wait until rising_edge(clk);
inclk <= '1';
d <= std_logic_vector(to_unsigned(input, 8));
end loop;
end process;
out_file : process
variable lo : line;
file output_file : text is out "rc_filt_out.txt";
begin
wait until rising_edge(clk);
if outclk = '1' then
write(lo, to_integer(unsigned(q)));
writeline(output_file, lo);
end if;
end process;
end behav;
|
entity Or2 is
port (x, y: in BIT; z: out BIT);
end entity Or2;
architecture gate1 of Or2 is
begin
z <= x or y;
end architecture gate1;
|
architecture RTL of FIFO is
begin
process
begin
for x in (0 to 30) loop
end loop;
loop
end loop;
-- Violations below
for x in (0 to 30)loop
end loop;
for x in (0 to 30) loop
end loop;
end process;
end;
|
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26160)
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26160)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26160)
`protect data_block
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26160)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26160)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26160)
`protect data_block
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect end_protected
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--============================================================================--
-- Design unit : DMA2AHB_TestPackage (package declaration)
--
-- File name : dma2ahb_tp.vhd
--
-- Purpose : Interface package for AMBA AHB master interface with DMA input
--
-- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
-- 13th May 1999, issue A, first release, ARM Limited
-- The document can be retrieved from http://www.arm.com
-- AMBA is a trademark of ARM Limited.
-- ARM is a registered trademark of ARM Limited.
--
-- Note : Naming convention according to AMBA(TM) Specification:
-- Signal names are in upper case, except for the following:
-- A lower case 'n' in the name indicates that the signal
-- is active low.
-- Constant names are in upper case.
-- The least significant bit of an array is located to the right,
-- carrying the index number zero.
--
-- Limitations : See DMA2AHB VHDL core
--
-- Library : {independent}
--
-- Authors : Aeroflex Gaisler AB
--
-- Contact : mailto:support@gaisler.com
-- http://www.gaisler.com
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit.
--
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 1.4 SH 1 Jul 2005 New package
-- 1.5 SH 1 Sep 2005 New library TOPNET
-- 1.6 SH 20 Sep 2005 Added transparent HSIZE support
-- 1.8 SH 10 Nov 2005 Updated DMA2AHB interface usage
-- 1.9 SH 4 Jan 2006 Burst routines added
-- Fault reporting priority and timing improved
-- 1.9.1 SH 12 Jan 2006 Correct DmaComp8
-- 1.9.2 SH ## ### #### Corrected compare to allow pull-up
-- Adjusted printouts
-- 1.9.3 JA 14 Dec 2007 Support for halfword and byte bursts
-- 1.9.4 MI 4 Aug 2008 Support for Lock
-- 1.9.5 SH 4 Mar 2011 Modifed burst accesses to mimic real hw
--------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Numeric_Std.all;
library Std;
use Std.Standard.all;
use Std.TextIO.all;
library GRLIB;
use GRLIB.AMBA.all;
use GRLIB.STDIO.all;
use GRLIB.DMA2AHB_Package.all;
use GRLIB.STDLIB.all;
package DMA2AHB_TestPackage is
-----------------------------------------------------------------------------
-- Vector of words
-----------------------------------------------------------------------------
type Data_Vector is array (Natural range <> ) of
Std_Logic_Vector(32-1 downto 0);
-----------------------------------------------------------------------------
-- Constants for comparison
-----------------------------------------------------------------------------
constant DontCare32: Std_Logic_Vector(31 downto 0) := (others => '-');
constant DontCare24: Std_Logic_Vector(23 downto 0) := (others => '-');
constant DontCare16: Std_Logic_Vector(15 downto 0) := (others => '-');
constant DontCare8: Std_Logic_Vector( 7 downto 0) := (others => '-');
----------------------------------------------------------------------------
-- Constant for calculating burst lengths
----------------------------------------------------------------------------
constant WordSize: integer := 32;
-----------------------------------------------------------------------------
-- Initialize AHB interface
-----------------------------------------------------------------------------
procedure DMAInit(
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
constant InstancePath: in String := "DMAInit";
constant ScreenOutput: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite16(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet16(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead16(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead16";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp16(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(15 downto 0);
variable RxData: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite8(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet8(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead8(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead8";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp8(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector( 7 downto 0);
variable RxData: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuietBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuietBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAReadBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False);
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMACompBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable CxData: in Data_Vector;
variable RxData: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False);
end package DMA2AHB_TestPackage;
package body DMA2AHB_TestPackage is
-----------------------------------------------------------------------------
-- Compare function handling '-'
-----------------------------------------------------------------------------
function Compare(O, C: in Std_Logic_Vector) return Boolean is
variable T: Std_Logic_Vector(O'Range) := C;
variable Result: Boolean;
begin
Result := True;
for i in O'Range loop
if not (To_X01(O(i))=T(i) or T(i)='-' or T(i)='U') then
Result := False;
end if;
end loop;
return Result;
end function Compare;
-----------------------------------------------------------------------------
-- Function declarations
-----------------------------------------------------------------------------
function Conv_Std_Logic_Vector(
constant i: Integer;
w: Integer)
return Std_Logic_Vector is
variable tmp: Std_Logic_Vector(w-1 downto 0);
begin
tmp := Std_Logic_Vector(To_UnSigned(i, w));
return(tmp);
end;
-----------------------------------------------------------------------------
-- Function declarations
-----------------------------------------------------------------------------
function Conv_Integer(
constant i: Std_Logic_Vector)
return Integer is
variable tmp: Integer;
begin
tmp := To_Integer(UnSigned(i));
return(tmp);
end;
-----------------------------------------------------------------------------
-- Synchronisation with respect to clock and with output offset
-----------------------------------------------------------------------------
procedure Synchronise(
signal Clock: in Std_ULogic;
constant Offset: in Time := 5 ns;
constant Enable: in Boolean := True) is
begin
if Enable then
wait until Clock = '1'; -- synchronise
if Offset > 0 ns then
wait for Offset; -- output offset delay
end if;
end if;
end procedure Synchronise;
-----------------------------------------------------------------------------
-- Initialize AHB interface
-----------------------------------------------------------------------------
procedure DMAInit(
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
constant InstancePath: in String := "DMAInit";
constant ScreenOutput: in Boolean := False) is
variable L: Line;
begin
Synchronise(HCLK);
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Request <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Store <= '0';
dmai.Data <= (others => '0');
dmai.Size <= "10";
dmai.Lock <= '0';
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB initalised"));
WriteLine(Output, L);
end if;
end procedure DMAInit;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False) is
variable L: Line;
begin
-- do not synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Address <= Address;
dmai.Request <= '1';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Store <= '1';
dmai.Data <= Data;
if Size=32 then
dmai.Size <= HSIZE32;
elsif Size=16 then
dmai.Size <= HSIZE16;
elsif Size=8 then
dmai.Size <= HSIZE8;
else
report "Unsupported data width"
severity Failure;
end if;
if Lock then
dmai.Lock <= '1';
else
dmai.Lock <= '0';
end if;
wait for 1 ns;
if dmao.Grant='0' then
while dmao.Grant='0' loop
Synchronise(HCLK, 0 ns);
end loop;
else
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Data <= Data;
loop
Synchronise(HCLK);
while dmao.Ready='0' and dmao.Retry='0' and dmao.Fault='0' loop
Synchronise(HCLK);
end loop;
if dmao.Fault='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" ERROR reponse "));
WriteLine(Output, L);
end if;
TP := False;
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
dmai.Lock <= '0';
Synchronise(HCLK);
Synchronise(HCLK);
exit;
elsif dmao.Ready='1' then
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
dmai.Lock <= '0';
exit;
end if;
if dmao.Retry='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" RETRY/SPLIT reponse "));
WriteLine(Output, L);
end if;
end if;
end loop;
end procedure DMAWriteQuiet;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False) is
variable OK: Boolean := True;
variable L: Line;
begin
DMAWriteQuiet(Address, Data, HCLK, dmai, dmao, OK,
InstancePath, True, cBack2Back, Size, Lock);
if ScreenOutput and OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
elsif not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
end if;
end procedure DMAWrite;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False) is
variable L: Line;
begin
-- do not Synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Address <= Address;
dmai.Request <= '1';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Store <= '0';
dmai.Data <= (others => '0');
if Size=32 then
dmai.Size <= HSIZE32;
elsif Size=16 then
dmai.Size <= HSIZE16;
elsif Size=8 then
dmai.Size <= HSIZE8;
else
report "Unsupported data width"
severity Failure;
end if;
if Lock then
dmai.Lock <= '1';
else
dmai.Lock <= '0';
end if;
wait for 1 ns;
if dmao.Grant='0' then
while dmao.Grant='0' loop
Synchronise(HCLK, 0 ns);
end loop;
else
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
loop
Synchronise(HCLK);
while dmao.Ready='0' and dmao.Retry='0' and dmao.Fault='0' loop
Synchronise(HCLK);
end loop;
if dmao.Fault='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" ERROR reponse "));
WriteLine(Output, L);
end if;
TP := False;
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
Data := (others => 'X');
Synchronise(HCLK);
Synchronise(HCLK);
exit;
elsif dmao.Ready='1' then
Data := dmao.Data;
dmai.Address <= (others => '0');
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
exit;
end if;
if dmao.Retry='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" RETRY/SPLIT reponse "));
WriteLine(Output, L);
end if;
end if;
end loop;
end procedure DMAQuiet;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False) is
variable OK: Boolean := True;
variable L: Line;
variable Temp: Std_Logic_Vector(31 downto 0);
begin
DMAQuiet(Address, Temp, HCLK, dmai, dmao, OK,
InstancePath, True, cBack2Back, Size, Lock);
if ScreenOutput and OK then
Data := Temp;
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : data: "));
HWrite(L, Temp);
WriteLine(Output, L);
elsif OK then
Data := Temp;
else
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
Data := (others => '-');
TP := False;
end if;
end procedure DMARead;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(31 downto 0);
variable RxData: out Std_Logic_Vector(31 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Lock: in Boolean := False) is
variable OK: Boolean := True;
variable L: Line;
variable Data: Std_Logic_Vector(31 downto 0);
begin
DMAQuiet(Address, Data, HCLK, dmai, dmao, OK,
InstancePath, True, cBack2Back, Size, Lock);
if not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
RxData := (others => '-');
elsif not Compare(Data, CxData) then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : data: "));
HWrite(L, Data);
Write (L, String'(" : expected: "));
HWrite(L, CxData);
Write (L, String'(" # Error #"));
WriteLine(Output, L);
TP := False;
RxData := Data;
elsif ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write(L, String'(" : data: "));
HWrite(L, Data);
WriteLine(Output, L);
RxData := Data;
else
RxData := Data;
end if;
end procedure DMAComp;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuiet16(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
begin
DMAWriteQuiet(Address, Data & Data, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 16, Lock);
end procedure DMAWriteQuiet16;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite16(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
begin
DMAWrite(Address, Data & Data, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 16, Lock);
end procedure DMAWrite16;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet16(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
variable Tmp: Std_Logic_Vector(31 downto 0);
begin
DMAQuiet(Address, Tmp, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 16, Lock);
if Address(1)='0' then
Data := Tmp(31 downto 16);
else
Data := Tmp(15 downto 0);
end if;
end procedure DMAQuiet16;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead16(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead16";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
variable Tmp: Std_Logic_Vector(31 downto 0);
begin
DMARead(Address, Tmp, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 16, Lock);
if Address(1)='0' then
Data := Tmp(31 downto 16);
else
Data := Tmp(15 downto 0);
end if;
end procedure DMARead16;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp16(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector(15 downto 0);
variable RxData: out Std_Logic_Vector(15 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp16";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
variable TmpRx: Std_Logic_Vector(31 downto 0);
variable TmpCx: Std_Logic_Vector(31 downto 0);
begin
if Address(1)='0' then
TmpCx := CxData & "----------------";
else
TmpCx := "----------------" & CxData;
end if;
DMAComp(Address, TmpCx, TmpRx, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 16, Lock);
if Address(1)='0' then
RxData := TmpRx(31 downto 16);
else
RxData := TmpRx(15 downto 0);
end if;
end procedure DMAComp16;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuiet8(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
begin
DMAWriteQuiet(Address, Data & Data & Data & Data, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 8, Lock);
end procedure DMAWriteQuiet8;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWrite8(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
begin
DMAWrite(Address, Data & Data & Data & Data, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 8, Lock);
end procedure DMAWrite8;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuiet8(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
variable Tmp: Std_Logic_Vector(31 downto 0);
begin
DMAQuiet(Address, Tmp, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 8, Lock);
if Address(1 downto 0)="00" then
Data := Tmp(31 downto 24);
elsif Address(1 downto 0)="01" then
Data := Tmp(23 downto 16);
elsif Address(1 downto 0)="10" then
Data := Tmp(15 downto 8);
else
Data := Tmp( 7 downto 0);
end if;
end procedure DMAQuiet8;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMARead8(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead8";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
variable Tmp: Std_Logic_Vector(31 downto 0);
begin
DMARead(Address, Tmp, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 8, Lock);
if Address(1 downto 0)="00" then
Data := Tmp(31 downto 24);
elsif Address(1 downto 0)="01" then
Data := Tmp(23 downto 16);
elsif Address(1 downto 0)="10" then
Data := Tmp(15 downto 8);
else
Data := Tmp( 7 downto 0);
end if;
end procedure DMARead8;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAComp8(
constant Address: in Std_Logic_Vector(31 downto 0);
constant CxData: in Std_Logic_Vector( 7 downto 0);
variable RxData: out Std_Logic_Vector( 7 downto 0);
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp8";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Lock: in Boolean := False) is
variable TmpRx: Std_Logic_Vector(31 downto 0);
variable TmpCx: Std_Logic_Vector(31 downto 0);
begin
if Address(1 downto 0)="00" then
TmpCx := CxData & "--------" & "--------" & "--------";
elsif Address(1 downto 0)="01" then
TmpCx := "--------" & CxData & "--------" & "--------";
elsif Address(1 downto 0)="10" then
TmpCx := "--------" & "--------" & CxData & "--------";
else
TmpCx := "--------" & "--------" & "--------" & CxData;
end if;
DMAComp(Address, TmpCx, TmpRx, HCLK, dmai, dmao, TP,
InstancePath, ScreenOutput, cBack2Back, 8, Lock);
if Address(1 downto 0)="00" then
RxData := TmpRx(31 downto 24);
elsif Address(1 downto 0)="01" then
RxData := TmpRx(23 downto 16);
elsif Address(1 downto 0)="10" then
RxData := TmpRx(15 downto 8);
else
RxData := TmpRx( 7 downto 0);
end if;
end procedure DMAComp8;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteQuietBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False) is
variable L: Line;
constant Count: Integer := Data'Length*WordSize/Size;
variable GCount: Integer := Data'Length*WordSize/Size;
variable DCount: Integer := 1;
begin
-- do not synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Address <= Address;
dmai.Data <= (others => '0');
dmai.Request <= '1';
dmai.Store <= '1';
if Count > 1 then
dmai.Burst <= '1';
else
dmai.Burst <= '0';
end if;
if Beat=1 then
dmai.Beat <= HINCR;
elsif Beat=4 then
dmai.Beat <= HINCR4;
elsif Beat=8 then
dmai.Beat <= HINCR8;
elsif Beat=16 then
dmai.Beat <= HINCR16;
else
report "Unsupported beat"
severity Failure;
end if;
if Size=32 then
dmai.Size <= HSIZE32;
elsif Size=16 then
dmai.Size <= HSIZE16;
elsif Size=8 then
dmai.Size <= HSIZE8;
else
report "Unsupported data width"
severity Failure;
end if;
if Lock then
dmai.Lock <= '1';
else
dmai.Lock <= '0';
end if;
-- wait for first grant, indicating start of accesses
Synchronise(HCLK, 0 ns);
if dmao.Grant='0' then
while dmao.Grant='0' loop
Synchronise(HCLK, 0 ns);
end loop;
end if;
GCount := GCount-1;
-- first data
if Size=32 then
dmai.Data <= Data(0);
elsif Size=16 then
dmai.Data <= Data(0)(31 downto 16) & Data(0)(31 downto 16);
elsif Size=8 then
dmai.Data <= Data(0)(31 downto 24) & Data(0)(31 downto 24) &
Data(0)(31 downto 24) & Data(0)(31 downto 24);
end if;
loop
-- remove request when all grants received
if dmao.Grant='1' then
if GCount=0 then
dmai.Reset <= '0';
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
else
GCount := GCount-1;
end if;
end if;
Synchronise(HCLK, 0 ns);
while dmao.Grant='0' and dmao.Ready='0' and dmao.OKAY='0' and dmao.Retry='0' and dmao.Fault='0' loop
Synchronise(HCLK, 0 ns);
end loop;
if dmao.Fault='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+(DCount-1)*Beat*Size/8, 32));
Write (L, String'(" ERROR response "));
WriteLine(Output, L);
end if;
TP := False;
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
Synchronise(HCLK, 0 ns);
Synchronise(HCLK, 0 ns);
exit;
elsif dmao.OKAY='1' then
-- for each OKAY, provide new data
if DCount=Count then
dmai.Address <= (others => '0');
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
Synchronise(HCLK, 0 ns);
while dmao.Ready='0' loop
Synchronise(HCLK, 0 ns);
end loop;
if GCount/=0 then
report "DMAWriteQuietBurst: Too few grants received!"
severity Failure;
end if;
exit;
else
if Size=32 then
dmai.Data <= Data(DCount);
elsif Size=16 then
dmai.Data <= Data(DCount/2)((31-16*(DCount mod 2)) downto (16-(16*(DCount mod 2)))) &
Data(DCount/2)((31-16*(DCount mod 2)) downto (16-(16*(DCount mod 2))));
elsif Size=8 then
dmai.Data <= Data(DCount/4)((31-8*(DCount mod 4)) downto (24-(8*(DCount mod 4)))) &
Data(DCount/4)((31-8*(DCount mod 4)) downto (24-(8*(DCount mod 4)))) &
Data(DCount/4)((31-8*(DCount mod 4)) downto (24-(8*(DCount mod 4)))) &
Data(DCount/4)((31-8*(DCount mod 4)) downto (24-(8*(DCount mod 4))));
end if;
DCount := DCount+1;
end if;
end if;
if dmao.Retry='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+(DCount-1)*Beat*Size/8, 32));
Write (L, String'(" RETRY/SPLIT response "));
WriteLine(Output, L);
end if;
end if;
end loop;
end procedure DMAWriteQuietBurst;
-----------------------------------------------------------------------------
-- AMBA AHB write access
-----------------------------------------------------------------------------
procedure DMAWriteBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
constant Data: in Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAWrite";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False) is
variable OK: Boolean := True;
variable L: Line;
begin
DMAWriteQuietBurst(Address, Data, HCLK, dmai, dmao, OK,
InstancePath, ScreenOutput, cBack2Back, Size, Beat, Lock);
if ScreenOutput and OK then
for i in 0 to Data'Length-1 loop
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+i*Beat*Size/8, 32));
Write (L, String'(" : data: "));
HWrite(L, Data(i));
WriteLine(Output, L);
end loop;
elsif not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB write access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
end if;
end procedure DMAWriteBurst;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAQuietBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAQuiet";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False) is
variable L: Line;
constant Count: Integer := Data'Length*WordSize/Size;
variable GCount: Integer := Data'Length*WordSize/Size;
variable DCount: Integer := 1;
variable DataPart: Integer := 0;
begin
-- do not synchronise when a back-to-back access is requested
if not cBack2Back then
Synchronise(HCLK);
end if;
dmai.Reset <= '0';
dmai.Address <= Address;
dmai.Data <= (others => '0');
dmai.Request <= '1';
dmai.Store <= '0';
if Count > 1 then
dmai.Burst <= '1';
else
dmai.Burst <= '0';
end if;
if Beat=1 then
dmai.Beat <= HINCR;
elsif Beat=4 then
dmai.Beat <= HINCR4;
elsif Beat=8 then
dmai.Beat <= HINCR8;
elsif Beat=16 then
dmai.Beat <= HINCR16;
else
report "Unsupported beat"
severity Failure;
end if;
if Size=32 then
dmai.Size <= HSIZE32;
elsif Size=16 then
dmai.Size <= HSIZE16;
if Address(1 downto 0) = "00" then
DataPart := 0;
else
DataPart := 1;
end if;
elsif Size=8 then
dmai.Size <= HSIZE8;
if Address(1 downto 0) = "00" then
DataPart := 0;
elsif Address(1 downto 0) = "01" then
DataPart := 1;
elsif Address(1 downto 0) = "10" then
DataPart := 2;
else
DataPart := 3;
end if;
else
report "Unsupported data width"
severity Failure;
end if;
if Lock then
dmai.Lock <= '1';
else
dmai.Lock <= '0';
end if;
-- wait for first grant, indicating start of accesses
Synchronise(HCLK, 0 ns);
if dmao.Grant='0' then
while dmao.Grant='0' loop
Synchronise(HCLK, 0 ns);
end loop;
end if;
GCount := GCount-1;
loop
-- remove request when all grants received
if dmao.Grant='1' then
if GCount=0 then
dmai.Reset <= '0';
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
else
GCount := GCount-1;
end if;
end if;
Synchronise(HCLK, 0 ns);
while dmao.Grant='0' and dmao.Ready='0' and dmao.Retry='0' and dmao.Fault='0' loop
Synchronise(HCLK, 0 ns);
end loop;
if dmao.Fault='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+(DCount-1)*Beat*Size/8, 32));
Write (L, String'(" ERROR response"));
WriteLine(Output, L);
end if;
TP := False;
dmai.Reset <= '0';
dmai.Address <= (others => '0');
dmai.Data <= (others => '0');
dmai.Request <= '0';
dmai.Store <= '0';
dmai.Burst <= '0';
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
Synchronise(HCLK);
Synchronise(HCLK);
exit;
elsif dmao.Ready='1' then
-- for each READY, store data
if Size=32 then
Data(DCount-1) := dmao.Data;
elsif Size=16 then
Data((DCount-1)/2)((31-16*((DCount-1) mod 2)) downto (16-(16*((DCount-1) mod 2)))) :=
dmao.Data((31-16*DataPart) downto (16-16*DataPart));
DataPart := (DataPart + 1) mod 2;
elsif Size=8 then
Data((DCount-1)/4)((31-8*((DCount-1) mod 4)) downto (24-(8*((DCount-1) mod 4)))) :=
dmao.Data((31-8*DataPart) downto (24-8*DataPart));
DataPart := (DataPart + 1) mod 4;
end if;
if DCount=Count then
dmai.Address <= (others => '0');
dmai.Beat <= (others => '0');
dmai.Size <= (others => '0');
if GCount/=0 then
report "DMAQuietBurst: Too few grants received!"
severity Failure;
end if;
exit;
else
DCount := DCount+1;
end if;
end if;
if dmao.Retry='1' then
if ScreenOutput then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+(DCount-1)*Beat*Size/8, 32));
Write (L, String'(" RETRY/SPLIT response "));
WriteLine(Output, L);
end if;
end if;
end loop;
end procedure DMAQuietBurst;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMAReadBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable Data: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMARead";
constant ScreenOutput: in Boolean := True;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False) is
variable OK: Boolean := True;
variable L: Line;
variable Temp: Data_Vector(0 to Data'Length-1);
begin
DMAQuietBurst(Address, Temp, HCLK, dmai, dmao, OK,
InstancePath, ScreenOutput, cBack2Back, Size, Beat, Lock);
if ScreenOutput and OK then
Data := Temp;
for i in 0 to Data'Length-1 loop
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+i*Beat*Size/8, 32));
Write (L, String'(" : data: "));
HWrite(L, Temp(i));
WriteLine(Output, L);
end loop;
elsif OK then
Data := Temp;
else
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
Temp := (others => (others => '-'));
Data := Temp;
TP := False;
end if;
end procedure DMAReadBurst;
-----------------------------------------------------------------------------
-- AMBA AHB read access
-----------------------------------------------------------------------------
procedure DMACompBurst(
constant Address: in Std_Logic_Vector(31 downto 0);
variable CxData: in Data_Vector;
variable RxData: out Data_Vector;
signal HCLK: in Std_ULogic;
signal dmai: out dma_in_type;
signal dmao: in dma_out_type;
variable TP: inout Boolean;
constant InstancePath: in String := "DMAComp";
constant ScreenOutput: in Boolean := False;
constant cBack2Back: in Boolean := False;
constant Size: in Integer := 32;
constant Beat: in Integer := 1;
constant Lock: in Boolean := False) is
variable OK: Boolean := True;
variable L: Line;
variable Data: Data_Vector(0 to CxData'Length-1);
begin
DMAQuietBurst(Address, Data, HCLK, dmai, dmao, OK,
InstancePath, ScreenOutput, cBack2Back, Size, Beat, Lock);
if not OK then
Write (L, Now, Right, 15);
Write (L, " : " & InstancePath);
Write (L, String'(" : AHB read access, address: "));
HWrite(L, Address);
Write (L, String'(" : ## Failed ##"));
WriteLine(Output, L);
TP := False;
Data := (others => (others => '-'));
RxData := Data;
else
for i in 0 to Data'Length-1 loop
if not Compare(Data(i), CxData(i)) then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+i*Beat*Size/8, 32));
Write(L, String'(" : data: "));
HWrite(L, Data(i));
Write(L, String'(" : expected: "));
HWrite(L, CxData(i));
Write(L, String'(" # Error #"));
WriteLine(Output, L);
TP := False;
elsif ScreenOutput then
Write(L, Now, Right, 15);
Write(L, " : " & InstancePath);
Write(L, String'(" : AHB read access, address: "));
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+i*Beat*Size/8, 32));
Write(L, String'(" : data: "));
HWrite(L, Data(i));
WriteLine(Output, L);
end if;
end loop;
RxData := Data;
end if;
end procedure DMACompBurst;
end package body DMA2AHB_TestPackage; --======================================--
|
----------------------------------------------------------------------------------
-- Engineer: Noxet
--
-- Module Name: string_generator - Behavioral
-- Description:
-- A state machine to generate potential passwords
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity string_generator is
port (
clk : in std_logic;
rstn : in std_logic; -- active low reset ofc
i_start : in std_logic;
i_halt : in std_logic;
o_md5_start : out std_logic; -- when we write a string to md5 we also start them
o_done : out std_logic;
o_length : out std_logic_vector(2 downto 0); -- max 6 chars
o_string : out std_logic_vector(47 downto 0) -- 6 char string
);
end string_generator;
architecture Behavioral of string_generator is
type states is (init, c0, c1, c2, c3, c4, c5);
signal state_c, state_n : states;
constant low_chr : unsigned(7 downto 0) := x"61"; -- First character (a)
constant high_chr : unsigned(7 downto 0) := x"7A"; -- Last character generated (z)
signal chr0_c, chr1_c, chr2_c, chr3_c, chr4_c, chr5_c : unsigned(7 downto 0);
signal chr0_n, chr1_n, chr2_n, chr3_n, chr4_n, chr5_n : unsigned(7 downto 0);
signal len_c, len_n : unsigned(2 downto 0);
begin
clk_proc: process(clk)
begin
if rising_edge(clk) then
if rstn = '0' then
state_c <= init;
chr0_c <= (others => '0');
chr1_c <= (others => '0');
chr2_c <= (others => '0');
chr3_c <= (others => '0');
chr4_c <= (others => '0');
chr5_c <= (others => '0');
len_c <= (others => '0');
else
--if i_halt = '0' then -- only update when not halted
state_c <= state_n;
chr0_c <= chr0_n;
chr1_c <= chr1_n;
chr2_c <= chr2_n;
chr3_c <= chr3_n;
chr4_c <= chr4_n;
chr5_c <= chr5_n;
len_c <= len_n;
--end if;
end if;
end if;
end process clk_proc;
fsm_proc: process (i_start, state_c, chr0_c, chr1_c, chr2_c, chr3_c, chr4_c, chr5_c, len_c, i_halt)
begin
-- defaults
state_n <= state_c;
chr0_n <= chr0_c;
chr1_n <= chr1_c;
chr2_n <= chr2_c;
chr3_n <= chr3_c;
chr4_n <= chr4_c;
chr5_n <= chr5_c;
len_n <= len_c;
o_done <= '0';
o_md5_start <= '0';
if i_halt = '0' then
case state_c is
when init =>
chr0_n <= (others => '0');
chr1_n <= (others => '0');
chr2_n <= (others => '0');
chr3_n <= (others => '0');
chr4_n <= (others => '0');
chr5_n <= (others => '0');
len_n <= (others => '0');
o_md5_start <= '0'; -- don't run the md5 in init
if i_start = '1' then
state_n <= c0;
end if;
when c0 =>
chr0_n <= chr0_c + 1;
o_md5_start <= '1'; -- we are not halting so we have to start the next md5
if chr0_c = 0 then
chr0_n <= low_chr; -- set 'a' as the first character
len_n <= len_c + 1; -- string size grows by 1 when we use a new character
end if;
if chr0_c = high_chr then
chr0_n <= low_chr;
state_n <= c1;
end if;
when c1 =>
chr1_n <= chr1_c + 1;
state_n <= c0;
o_md5_start <= '1';
if chr1_c = 0 then
chr1_n <= low_chr;
len_n <= len_c + 1;
end if;
if chr1_c = high_chr then
chr1_n <= low_chr;
state_n <= c2;
end if;
when c2 =>
chr2_n <= chr2_c + 1;
state_n <= c0;
o_md5_start <= '1';
if chr2_c = 0 then
chr2_n <= low_chr;
len_n <= len_c + 1;
end if;
if chr2_c = high_chr then
chr2_n <= low_chr;
state_n <= c3;
end if;
when c3 =>
chr3_n <= chr3_c + 1;
state_n <= c0;
o_md5_start <= '1';
if chr3_c = 0 then
chr3_n <= low_chr;
len_n <= len_c + 1;
end if;
if chr3_c = high_chr then
chr3_n <= low_chr;
state_n <= c4;
end if;
when c4 =>
chr4_n <= chr4_c + 1;
state_n <= c0;
o_md5_start <= '1';
if chr4_c = 0 then
chr4_n <= low_chr;
len_n <= len_c + 1;
end if;
if chr4_c = high_chr then
chr4_n <= low_chr;
state_n <= c5;
end if;
when c5 =>
chr5_n <= chr5_c + 1;
state_n <= c0;
o_md5_start <= '1';
if chr5_c = 0 then
chr5_n <= low_chr;
len_n <= len_c + 1;
end if;
if chr5_c = high_chr then
chr5_n <= low_chr;
state_n <= init;
o_done <= '1'; -- We have now generated all possible passwords
end if;
when others => null;
end case;
end if;
end process;
-- Output logic
o_string <= std_logic_vector(chr5_c & chr4_c & chr3_c & chr2_c & chr1_c & chr0_c);
o_length <= std_logic_vector(len_c);
end Behavioral;
|
entity sub_ent is
end entity;
architecture a of sub_ent is
begin
end architecture a;
entity test is
end entity;
architecture test1 of test is
begin
entity work.sub_ent; -- unlabeled entity instantiation
end architecture;
architecture test2 of test is
begin
fg1: for ii in 0 to 0 generate
begin
end generate;
block -- unlabeled block
begin
end block;
end architecture;
architecture test3 of test is
component comp is port (a: boolean);
end component;
signal s_ok: boolean;
begin
comp port map (a => s_ok); -- unlabeled component instantiation
end architecture;
architecture test5 of test is
begin
if true generate -- unlabeled if-generate
begin
end generate;
end architecture;
architecture test6 of test is
component comp is port (a: boolean);
end component;
signal s_ok: boolean;
begin
-- include labeled testcases to make sure they are ok
e1: entity work.sub_ent;
b1: block
begin
end block;
c1: comp port map (a => s_ok);
ig1: if true generate
begin
end generate;
for ii in 0 to 0 generate -- unlabeled for-generate
begin
end generate;
end architecture;
|
entity sub_ent is
end entity;
architecture a of sub_ent is
begin
end architecture a;
entity test is
end entity;
architecture test1 of test is
begin
entity work.sub_ent; -- unlabeled entity instantiation
end architecture;
architecture test2 of test is
begin
fg1: for ii in 0 to 0 generate
begin
end generate;
block -- unlabeled block
begin
end block;
end architecture;
architecture test3 of test is
component comp is port (a: boolean);
end component;
signal s_ok: boolean;
begin
comp port map (a => s_ok); -- unlabeled component instantiation
end architecture;
architecture test5 of test is
begin
if true generate -- unlabeled if-generate
begin
end generate;
end architecture;
architecture test6 of test is
component comp is port (a: boolean);
end component;
signal s_ok: boolean;
begin
-- include labeled testcases to make sure they are ok
e1: entity work.sub_ent;
b1: block
begin
end block;
c1: comp port map (a => s_ok);
ig1: if true generate
begin
end generate;
for ii in 0 to 0 generate -- unlabeled for-generate
begin
end generate;
end architecture;
|
entity sub_ent is
end entity;
architecture a of sub_ent is
begin
end architecture a;
entity test is
end entity;
architecture test1 of test is
begin
entity work.sub_ent; -- unlabeled entity instantiation
end architecture;
architecture test2 of test is
begin
fg1: for ii in 0 to 0 generate
begin
end generate;
block -- unlabeled block
begin
end block;
end architecture;
architecture test3 of test is
component comp is port (a: boolean);
end component;
signal s_ok: boolean;
begin
comp port map (a => s_ok); -- unlabeled component instantiation
end architecture;
architecture test5 of test is
begin
if true generate -- unlabeled if-generate
begin
end generate;
end architecture;
architecture test6 of test is
component comp is port (a: boolean);
end component;
signal s_ok: boolean;
begin
-- include labeled testcases to make sure they are ok
e1: entity work.sub_ent;
b1: block
begin
end block;
c1: comp port map (a => s_ok);
ig1: if true generate
begin
end generate;
for ii in 0 to 0 generate -- unlabeled for-generate
begin
end generate;
end architecture;
|
entity sub_ent is
end entity;
architecture a of sub_ent is
begin
end architecture a;
entity test is
end entity;
architecture test1 of test is
begin
entity work.sub_ent; -- unlabeled entity instantiation
end architecture;
architecture test2 of test is
begin
fg1: for ii in 0 to 0 generate
begin
end generate;
block -- unlabeled block
begin
end block;
end architecture;
architecture test3 of test is
component comp is port (a: boolean);
end component;
signal s_ok: boolean;
begin
comp port map (a => s_ok); -- unlabeled component instantiation
end architecture;
architecture test5 of test is
begin
if true generate -- unlabeled if-generate
begin
end generate;
end architecture;
architecture test6 of test is
component comp is port (a: boolean);
end component;
signal s_ok: boolean;
begin
-- include labeled testcases to make sure they are ok
e1: entity work.sub_ent;
b1: block
begin
end block;
c1: comp port map (a => s_ok);
ig1: if true generate
begin
end generate;
for ii in 0 to 0 generate -- unlabeled for-generate
begin
end generate;
end architecture;
|
entity sub_ent is
end entity;
architecture a of sub_ent is
begin
end architecture a;
entity test is
end entity;
architecture test1 of test is
begin
entity work.sub_ent; -- unlabeled entity instantiation
end architecture;
architecture test2 of test is
begin
fg1: for ii in 0 to 0 generate
begin
end generate;
block -- unlabeled block
begin
end block;
end architecture;
architecture test3 of test is
component comp is port (a: boolean);
end component;
signal s_ok: boolean;
begin
comp port map (a => s_ok); -- unlabeled component instantiation
end architecture;
architecture test5 of test is
begin
if true generate -- unlabeled if-generate
begin
end generate;
end architecture;
architecture test6 of test is
component comp is port (a: boolean);
end component;
signal s_ok: boolean;
begin
-- include labeled testcases to make sure they are ok
e1: entity work.sub_ent;
b1: block
begin
end block;
c1: comp port map (a => s_ok);
ig1: if true generate
begin
end generate;
for ii in 0 to 0 generate -- unlabeled for-generate
begin
end generate;
end architecture;
|
entity tb is
end tb;
architecture behav of tb is
signal s : bit;
begin
postponed assert s = '0' severity failure;
process
begin
s <= '1';
wait for 0 ns;
s <= '0';
wait;
end process;
end behav;
|
entity tb is
end tb;
architecture behav of tb is
signal s : bit;
begin
postponed assert s = '0' severity failure;
process
begin
s <= '1';
wait for 0 ns;
s <= '0';
wait;
end process;
end behav;
|
architecture RTL of FIFO is
begin
block_label : block is begin end block block_label;
BLOCK_LABEL : BLOCK is BEGIN END BLOCK BLOCK_LABEL;
end architecture RTL;
|
-- File name: key_scheduler.vhd
-- Created: 2009-03-30
-- Author: Matt Swanson
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: Rijndael KeyScheduler
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity key_scheduler is
port (
clk : in std_logic;
nrst : in std_logic;
go : in std_logic;
round : in round_type;
key_data : in byte;
key_index : in g_index;
key_load : in std_logic;
round_key : out key_type;
done : out std_logic
);
type rcon_array is array (0 to 10) of byte;
constant rcon_tbl : rcon_array :=
(
x"8d", x"01", x"02", x"04", x"08", x"10", x"20", x"40",
x"80", x"1b", x"36"
);
end key_scheduler;
architecture behavioral of key_scheduler is
type state_type is (
idle, load_key, rotate, sub_bytes, add_cols, rcon, be_done
);
signal state : state_type;
signal next_state : state_type;
signal cur_key : key_type;
signal next_cur_key : key_type;
signal new_key : key_type;
signal next_new_key : key_type;
signal c : index;
signal next_c : index;
signal c_clr : std_logic;
signal c_up : std_logic;
signal r : index;
signal next_r : index;
signal r_clr : std_logic;
signal sbox_return_reged : byte;
signal sbox_lookup, sbox_return : byte;
begin
sbox_b : entity work.sbox(dataflow) port map (
clk => clk, a => sbox_lookup, b => sbox_return
);
-- leda C_1406 off
state_reg : process(clk, nrst)
begin
if (nrst = '0') then
state <= idle;
elsif rising_edge(clk) then
state <= next_state;
cur_key <= next_cur_key;
new_key <= next_new_key;
end if;
end process state_reg;
-- leda C_1406 on
state_nsl : process(state, go, r, c, round)
begin
next_state <= idle;
case state is
when idle =>
if (go = '1' and round = 0) then
next_state <= load_key;
elsif (go = '1') then
next_state <= rotate;
else
next_state <= idle;
end if;
when load_key =>
next_state <= be_done;
when rotate =>
next_state <= sub_bytes;
when sub_bytes =>
if (r /= 3) then
next_state <= sub_bytes;
else
next_state <= rcon;
end if;
when rcon =>
next_state <= add_cols;
when add_cols =>
if (r = 3 and c = 3) then
next_state <= be_done;
else
next_state <= add_cols;
end if;
when be_done =>
next_state <= idle;
end case;
end process state_nsl;
state_out : process(state, cur_key, new_key, key_data,
key_index, key_load,
sbox_return_reged, c, r, round)
variable temp_index : index;
begin
next_cur_key <= cur_key;
next_new_key <= new_key;
c_up <= '0';
c_clr <= '0';
r_clr <= '0';
done <= '0';
sbox_lookup <= (others => '-');
case state is
when idle =>
if (key_load = '1') then
next_new_key(key_index mod 4, key_index / 4) <= key_data;
end if;
when load_key =>
-- nothing
when rotate =>
r_clr <= '1';
c_clr <= '1';
sbox_lookup <= cur_key(1, 3);
for i in index loop
next_new_key(i, 0) <= cur_key(to_integer(to_unsigned(i, 2) + 1), 3);
end loop;
when sub_bytes =>
sbox_lookup <= new_key(to_integer(to_unsigned(r, 2) + 1), 0);
next_new_key(r, c) <= sbox_return_reged;
when rcon =>
-- leda DFT_021 off
next_new_key(0, 0) <= new_key(0, 0) xor rcon_tbl(round);
-- leda DFT_021 on
c_clr <= '1';
r_clr <= '1';
when add_cols =>
if (c = 0) then
temp_index := 0;
else
temp_index := c - 1;
end if;
next_new_key(r, c) <= new_key(r, temp_index) xor cur_key(r, c);
if (r = 3) then
c_up <= '1';
end if;
when be_done =>
next_cur_key <= new_key;
done <= '1';
end case;
end process state_out;
-- leda C_1406 off
c_counter_reg : process(clk)
begin
if rising_edge(clk) then
c <= next_c;
end if;
end process c_counter_reg;
-- leda C_1406 on
c_counter_nsl : process(c, c_up, c_clr)
begin
if (c_clr = '1') then
next_c <= 0;
elsif (c_up = '1') then
next_c <= to_integer(to_unsigned(c, 2) + 1);
else
next_c <= c;
end if;
end process c_counter_nsl;
-- leda C_1406 off
r_counter_reg : process(clk)
begin
if rising_edge(clk) then
r <= next_r;
end if;
end process r_counter_reg;
-- leda C_1406 on
-- leda C_1406 off
sbox_return_reg : process(clk)
begin
if rising_edge(clk) then
sbox_return_reged <= sbox_return;
end if;
end process sbox_return_reg;
-- leda C_1406 on
r_counter_nsl : process(r, r_clr)
begin
if (r_clr = '1') then
next_r <= 0;
else
next_r <= to_integer(to_unsigned(r, 2) + 1);
end if;
end process r_counter_nsl;
round_key <= cur_key;
end behavioral;
architecture behavioral_p of key_scheduler is
type state_type is (
idle, load_key, rot_sub_rcon, add_cols, be_done
);
signal state : state_type;
signal next_state : state_type;
signal cur_key : key_type;
signal next_cur_key : key_type;
signal new_key : key_type;
signal next_new_key : key_type;
signal c : index;
signal next_c : index;
signal c_clr : std_logic;
signal c_up : std_logic;
signal sbox_lookup, sbox_return : col;
begin
gen_sbox : for i in index generate
sbox_b : entity work.sbox(dataflow) port map (
clk => clk, a => sbox_lookup(i), b => sbox_return(i)
);
end generate gen_sbox;
process(cur_key)
begin
for i in index loop
sbox_lookup(i) <= cur_key(to_integer(to_unsigned(i, 2) + 1), 3);
end loop;
end process;
-- leda C_1406 off
state_reg : process(clk, nrst)
begin
if (nrst = '0') then
state <= idle;
elsif rising_edge(clk) then
state <= next_state;
cur_key <= next_cur_key;
new_key <= next_new_key;
end if;
end process state_reg;
-- leda C_1406 on
state_nsl : process(state, go, c, round)
begin
next_state <= idle;
case state is
when idle =>
if (go = '1' and round = 0) then
next_state <= load_key;
elsif (go = '1') then
next_state <= rot_sub_rcon;
else
next_state <= idle;
end if;
when load_key =>
next_state <= be_done;
when rot_sub_rcon =>
next_state <= add_cols;
when add_cols =>
if (c = 3) then
next_state <= be_done;
else
next_state <= add_cols;
end if;
when be_done =>
next_state <= idle;
end case;
end process state_nsl;
state_out : process(state, cur_key, new_key, key_data,
key_index, key_load,
sbox_return, c, round)
variable temp_index : index;
begin
next_cur_key <= cur_key;
next_new_key <= new_key;
c_up <= '0';
c_clr <= '0';
done <= '0';
case state is
when idle =>
if (key_load = '1') then
next_new_key(key_index mod 4, key_index / 4) <= key_data;
end if;
when load_key =>
-- nothing
when rot_sub_rcon =>
for i in index loop
if (i = 0) then
next_new_key(i, 0) <= sbox_return(i) xor rcon_tbl(round);
else
next_new_key(i, 0) <= sbox_return(i);
end if;
end loop;
c_clr <= '1';
when add_cols =>
if (c = 0) then
temp_index := 0;
else
temp_index := c - 1;
end if;
for r in index loop
next_new_key(r, c) <= new_key(r, temp_index) xor cur_key(r, c);
end loop;
c_up <= '1';
when be_done =>
next_cur_key <= new_key;
done <= '1';
end case;
end process state_out;
-- leda C_1406 off
c_counter_reg : process(clk)
begin
if rising_edge(clk) then
c <= next_c;
end if;
end process c_counter_reg;
-- leda C_1406 on
c_counter_nsl : process(c, c_up, c_clr)
begin
if (c_clr = '1') then
next_c <= 0;
elsif (c_up = '1') then
next_c <= to_integer(to_unsigned(c, 2) + 1);
else
next_c <= c;
end if;
end process c_counter_nsl;
round_key <= cur_key;
end behavioral_p;
|
------------------------------------------------------------------------------
-- Title : Wishbone Position Calculation Core
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-07-02
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Core Module for position calculation with de-cross, amplitude compensation
-- and delay tuning.
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-07-02 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- DSP Cores
use work.dsp_cores_pkg.all;
-- Position Calc
use work.position_calc_core_pkg.all;
-- WB registers
use work.pos_calc_wbgen2_pkg.all;
entity wb_position_calc_core is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_rffe_version : string := "V2";
g_with_switching : natural := 0
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic; -- Wishbone clock
fs_rst_n_i : in std_logic; -- FS reset
fs_rst2x_n_i : in std_logic; -- FS 2x reset
fs_clk_i : in std_logic; -- clock period = 8.8823218389287 ns (112.583175675676 Mhz)
fs_clk2x_i : in std_logic; -- clock period = 4.4411609194644 ns (225.166351351351 Mhz)
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- Raw ADC signals
-----------------------------
adc_ch0_i : in std_logic_vector(15 downto 0);
adc_ch1_i : in std_logic_vector(15 downto 0);
adc_ch2_i : in std_logic_vector(15 downto 0);
adc_ch3_i : in std_logic_vector(15 downto 0);
-----------------------------
-- Position calculation at various rates
-----------------------------
adc_ch0_dbg_data_o : out std_logic_vector(15 downto 0);
adc_ch1_dbg_data_o : out std_logic_vector(15 downto 0);
adc_ch2_dbg_data_o : out std_logic_vector(15 downto 0);
adc_ch3_dbg_data_o : out std_logic_vector(15 downto 0);
-----------------------------
-- BPF Data
-----------------------------
bpf_ch0_o : out std_logic_vector(23 downto 0);
bpf_ch1_o : out std_logic_vector(23 downto 0);
bpf_ch2_o : out std_logic_vector(23 downto 0);
bpf_ch3_o : out std_logic_vector(23 downto 0);
bpf_valid_o : out std_logic;
-----------------------------
-- MIX Data
-----------------------------
mix_ch0_i_o : out std_logic_vector(23 downto 0);
mix_ch0_q_o : out std_logic_vector(23 downto 0);
mix_ch1_i_o : out std_logic_vector(23 downto 0);
mix_ch1_q_o : out std_logic_vector(23 downto 0);
mix_ch2_i_o : out std_logic_vector(23 downto 0);
mix_ch2_q_o : out std_logic_vector(23 downto 0);
mix_ch3_i_o : out std_logic_vector(23 downto 0);
mix_ch3_q_o : out std_logic_vector(23 downto 0);
mix_valid_o : out std_logic;
-----------------------------
-- TBT Data
-----------------------------
tbt_decim_ch0_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch0_q_o : out std_logic_vector(23 downto 0);
tbt_decim_ch1_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch1_q_o : out std_logic_vector(23 downto 0);
tbt_decim_ch2_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch2_q_o : out std_logic_vector(23 downto 0);
tbt_decim_ch3_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch3_q_o : out std_logic_vector(23 downto 0);
tbt_decim_valid_o : out std_logic;
tbt_amp_ch0_o : out std_logic_vector(23 downto 0);
tbt_amp_ch1_o : out std_logic_vector(23 downto 0);
tbt_amp_ch2_o : out std_logic_vector(23 downto 0);
tbt_amp_ch3_o : out std_logic_vector(23 downto 0);
tbt_amp_valid_o : out std_logic;
tbt_pha_ch0_o : out std_logic_vector(23 downto 0);
tbt_pha_ch1_o : out std_logic_vector(23 downto 0);
tbt_pha_ch2_o : out std_logic_vector(23 downto 0);
tbt_pha_ch3_o : out std_logic_vector(23 downto 0);
tbt_pha_valid_o : out std_logic;
-----------------------------
-- FOFB Data
-----------------------------
fofb_decim_ch0_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch0_q_o : out std_logic_vector(23 downto 0);
fofb_decim_ch1_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch1_q_o : out std_logic_vector(23 downto 0);
fofb_decim_ch2_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch2_q_o : out std_logic_vector(23 downto 0);
fofb_decim_ch3_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch3_q_o : out std_logic_vector(23 downto 0);
fofb_decim_valid_o : out std_logic;
fofb_amp_ch0_o : out std_logic_vector(23 downto 0);
fofb_amp_ch1_o : out std_logic_vector(23 downto 0);
fofb_amp_ch2_o : out std_logic_vector(23 downto 0);
fofb_amp_ch3_o : out std_logic_vector(23 downto 0);
fofb_amp_valid_o : out std_logic;
fofb_pha_ch0_o : out std_logic_vector(23 downto 0);
fofb_pha_ch1_o : out std_logic_vector(23 downto 0);
fofb_pha_ch2_o : out std_logic_vector(23 downto 0);
fofb_pha_ch3_o : out std_logic_vector(23 downto 0);
fofb_pha_valid_o : out std_logic;
-----------------------------
-- Monit. Data
-----------------------------
monit_amp_ch0_o : out std_logic_vector(23 downto 0);
monit_amp_ch1_o : out std_logic_vector(23 downto 0);
monit_amp_ch2_o : out std_logic_vector(23 downto 0);
monit_amp_ch3_o : out std_logic_vector(23 downto 0);
monit_amp_valid_o : out std_logic;
-----------------------------
-- Position Data
-----------------------------
pos_x_tbt_o : out std_logic_vector(25 downto 0);
pos_y_tbt_o : out std_logic_vector(25 downto 0);
pos_q_tbt_o : out std_logic_vector(25 downto 0);
pos_sum_tbt_o : out std_logic_vector(25 downto 0);
pos_tbt_valid_o : out std_logic;
pos_x_fofb_o : out std_logic_vector(25 downto 0);
pos_y_fofb_o : out std_logic_vector(25 downto 0);
pos_q_fofb_o : out std_logic_vector(25 downto 0);
pos_sum_fofb_o : out std_logic_vector(25 downto 0);
pos_fofb_valid_o : out std_logic;
pos_x_monit_o : out std_logic_vector(25 downto 0);
pos_y_monit_o : out std_logic_vector(25 downto 0);
pos_q_monit_o : out std_logic_vector(25 downto 0);
pos_sum_monit_o : out std_logic_vector(25 downto 0);
pos_monit_valid_o : out std_logic;
pos_x_monit_1_o : out std_logic_vector(25 downto 0);
pos_y_monit_1_o : out std_logic_vector(25 downto 0);
pos_q_monit_1_o : out std_logic_vector(25 downto 0);
pos_sum_monit_1_o : out std_logic_vector(25 downto 0);
pos_monit_1_valid_o : out std_logic;
-----------------------------
-- Output to RFFE board
-----------------------------
clk_swap_o : out std_logic;
flag1_o : out std_logic;
flag2_o : out std_logic;
ctrl1_o : out std_logic_vector(7 downto 0);
ctrl2_o : out std_logic_vector(7 downto 0);
-----------------------------
-- Clock drivers for various rates
-----------------------------
clk_ce_1_o : out std_logic;
clk_ce_1112_o : out std_logic;
clk_ce_11120000_o : out std_logic;
clk_ce_111200000_o : out std_logic;
clk_ce_1390000_o : out std_logic;
clk_ce_2_o : out std_logic;
clk_ce_2224_o : out std_logic;
clk_ce_22240000_o : out std_logic;
clk_ce_222400000_o : out std_logic;
clk_ce_2780000_o : out std_logic;
clk_ce_35_o : out std_logic;
clk_ce_5000_o : out std_logic;
clk_ce_556_o : out std_logic;
clk_ce_5560000_o : out std_logic;
clk_ce_70_o : out std_logic;
dbg_cur_address_o : out std_logic_vector(31 downto 0);
dbg_adc_ch0_cond_o : out std_logic_vector(15 downto 0);
dbg_adc_ch1_cond_o : out std_logic_vector(15 downto 0);
dbg_adc_ch2_cond_o : out std_logic_vector(15 downto 0);
dbg_adc_ch3_cond_o : out std_logic_vector(15 downto 0)
);
end wb_position_calc_core;
architecture rtl of wb_position_calc_core is
---------------------------------------------------------
-- Constants --
---------------------------------------------------------
constant c_periph_addr_size : natural := 5+2;
constant c_cdc_data_ref_width : natural := 4*c_dsp_ref_num_bits; -- c_num_adc_channels ?
constant c_cdc_data_ref_iq_width : natural := 8*c_dsp_ref_num_bits; -- c_num_adc_channels*2 ?
constant c_cdc_data_pos_width : natural := 4*c_dsp_pos_num_bits; -- c_num_adc_channels ?
constant c_cdc_ref_size : natural := 16;
-- Crossbar component constants
-- Number of slaves
constant c_slaves : natural := 2;
-- Number of masters
constant c_masters : natural := 1; -- Top master.
constant c_num_pipeline_regs : integer := 8;
-- WB SDB (Self describing bus) layout
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
( 0 => f_sdb_embed_device(c_xwb_pos_calc_core_regs_sdb,
x"00000000"), -- Register interface
1 => f_sdb_embed_device(c_xwb_bpm_swap_sdb, x"00000100") -- WB swap
);
-- Self Describing Bus ROM Address. It will be an addressed slave as well.
constant c_sdb_address : t_wishbone_address := x"00000600";
---------------------------------------------------------
-- General Signals --
---------------------------------------------------------
signal sys_clr : std_logic;
signal sys_clr2x : std_logic;
-- Try to reduce fanout of clear signal
attribute MAX_FANOUT: string;
attribute MAX_FANOUT of sys_clr: signal is "REDUCE";
attribute MAX_FANOUT of sys_clr2x: signal is "REDUCE";
-----------------------------
-- Wishbone slave adapter signals/structures
-----------------------------
signal wb_slv_adp_out : t_wishbone_master_out;
signal wb_slv_adp_in : t_wishbone_master_in;
signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0);
-- Register interface signals
signal regs_out : t_pos_calc_out_registers;
signal regs_in : t_pos_calc_in_registers;
-----------------------------
-- Wishbone crossbar signals
-----------------------------
-- Crossbar master/slave arrays
signal cbar_slave_in : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_out : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_in : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_out : t_wishbone_master_out_array(c_slaves-1 downto 0);
---------------------------------------------------------
-- ADC, MIX and BPF data --
---------------------------------------------------------
signal adc_ch0_sp : std_logic_vector(15 downto 0);
signal adc_ch1_sp : std_logic_vector(15 downto 0);
signal adc_ch2_sp : std_logic_vector(15 downto 0);
signal adc_ch3_sp : std_logic_vector(15 downto 0);
signal adc_ch0_cond : std_logic_vector(15 downto 0);
signal adc_ch1_cond : std_logic_vector(15 downto 0);
signal adc_ch2_cond : std_logic_vector(15 downto 0);
signal adc_ch3_cond : std_logic_vector(15 downto 0);
-- Input conditioner signals
signal adc_ch0_pos_calc : std_logic_vector(15 downto 0);
signal adc_ch1_pos_calc : std_logic_vector(15 downto 0);
signal adc_ch2_pos_calc : std_logic_vector(15 downto 0);
signal adc_ch3_pos_calc : std_logic_vector(15 downto 0);
-- BPM Swap signals
signal sw_mode1 : std_logic_vector(1 downto 0);
signal sw_mode2 : std_logic_vector(1 downto 0);
signal clk_swap_en : std_logic;
signal wdw_rst : std_logic;
signal wdw_rst_n : std_logic;
signal wdw_input_cond_rst_n : std_logic;
signal wdw_sw_clk_in : std_logic;
signal wdw_sw_clk : std_logic;
signal wdw_use_en : std_logic;
signal wdw_dly : std_logic_vector(15 downto 0);
signal bpf_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal bpf_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal bpf_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal bpf_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal bpf_valid : std_logic := '1';
signal mix_ch0_i : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal mix_ch0_q : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal mix_ch1_i : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal mix_ch1_q : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal mix_ch2_i : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal mix_ch2_q : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal mix_ch3_i : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal mix_ch3_q : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal mix_valid : std_logic := '1';
---------------------------------------------------------
-- TBT data --
---------------------------------------------------------
signal tbt_decim_ch0_i : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_decim_ch0_q : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_decim_ch1_i : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_decim_ch1_q : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_decim_ch2_i : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_decim_ch2_q : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_decim_ch3_i : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_decim_ch3_q : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_decim_valid : std_logic := '1';
signal tbt_decim_q_ch01_incorrect_int : std_logic;
signal tbt_decim_q_ch23_incorrect_int : std_logic;
signal tbt_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_amp_valid : std_logic := '1';
signal tbt_pha_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_pha_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_pha_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_pha_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_pha_valid : std_logic := '1';
---------------------------------------------------------
-- FOFB data --
---------------------------------------------------------
signal fofb_decim_ch0_i : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_decim_ch0_q : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_decim_ch1_i : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_decim_ch1_q : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_decim_ch2_i : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_decim_ch2_q : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_decim_ch3_i : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_decim_ch3_q : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_decim_valid : std_logic := '1';
signal fofb_decim_q_ch01_missing_int : std_logic;
signal fofb_decim_q_ch23_missing_int : std_logic;
signal fofb_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_amp_valid : std_logic := '1';
signal fofb_pha_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_pha_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_pha_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_pha_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_pha_valid : std_logic := '1';
---------------------------------------------------------
-- Monitoring data --
---------------------------------------------------------
signal monit_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal monit_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal monit_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal monit_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal monit_amp_valid : std_logic := '1';
signal monit_amp_ch0_fs_sync : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal monit_amp_ch1_fs_sync : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal monit_amp_ch2_fs_sync : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal monit_amp_ch3_fs_sync : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal monit_amp_valid_fs_sync : std_logic := '1';
signal monit_cic_unexpected_int : std_logic;
signal monit_cfir_incorrect_int : std_logic;
signal monit_pfir_incorrect_int : std_logic;
signal monit_pos_1_incorrect_int : std_logic;
---------------------------------------------------------
-- Position data --
---------------------------------------------------------
signal x_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal x_tbt_valid : std_logic := '1';
signal y_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal y_tbt_valid : std_logic := '1';
signal q_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal q_tbt_valid : std_logic := '1';
signal sum_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal sum_tbt_valid : std_logic := '1';
signal x_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal x_fofb_valid : std_logic := '1';
signal y_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal y_fofb_valid : std_logic := '1';
signal q_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal q_fofb_valid : std_logic := '1';
signal sum_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal sum_fofb_valid : std_logic := '1';
signal x_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal x_monit_valid : std_logic := '1';
signal y_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal y_monit_valid : std_logic := '1';
signal q_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal q_monit_valid : std_logic := '1';
signal sum_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal sum_monit_valid : std_logic := '1';
signal x_monit_fs_sync : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal y_monit_fs_sync : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal q_monit_fs_sync : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal sum_monit_fs_sync : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal pos_monit_valid_fs_sync : std_logic := '1';
signal x_monit_1 : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal x_monit_1_valid : std_logic := '1';
signal y_monit_1 : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal y_monit_1_valid : std_logic := '1';
signal q_monit_1 : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal q_monit_1_valid : std_logic := '1';
signal sum_monit_1 : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal sum_monit_1_valid : std_logic := '1';
signal x_monit_1_fs_sync : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal y_monit_1_fs_sync : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal q_monit_1_fs_sync : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal sum_monit_1_fs_sync : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal pos_monit_1_valid_fs_sync : std_logic := '1';
---------------------------------------------------------
-- FIFO CDC signals
---------------------------------------------------------
signal fifo_bpf_in : std_logic_vector(c_cdc_data_ref_width-1 downto 0);
signal fifo_bpf_out : std_logic_vector(c_cdc_data_ref_width-1 downto 0);
signal fifo_bpf_valid_in : std_logic;
signal fifo_bpf_valid_out : std_logic;
signal fifo_mix_in : std_logic_vector(c_cdc_data_ref_iq_width-1 downto 0);
signal fifo_mix_out : std_logic_vector(c_cdc_data_ref_iq_width-1 downto 0);
signal fifo_mix_valid_in : std_logic;
signal fifo_mix_valid_out : std_logic;
signal fifo_tbt_decim_in : std_logic_vector(c_cdc_data_ref_iq_width-1 downto 0);
signal fifo_tbt_decim_out : std_logic_vector(c_cdc_data_ref_iq_width-1 downto 0);
signal fifo_tbt_decim_valid_in : std_logic;
signal fifo_tbt_decim_valid_out : std_logic;
signal fifo_tbt_amp_in : std_logic_vector(c_cdc_data_ref_width-1 downto 0);
signal fifo_tbt_amp_out : std_logic_vector(c_cdc_data_ref_width-1 downto 0);
signal fifo_tbt_amp_valid_in : std_logic;
signal fifo_tbt_amp_valid_out : std_logic;
signal fifo_tbt_pha_in : std_logic_vector(c_cdc_data_ref_width-1 downto 0);
signal fifo_tbt_pha_out : std_logic_vector(c_cdc_data_ref_width-1 downto 0);
signal fifo_tbt_pha_valid_in : std_logic;
signal fifo_tbt_pha_valid_out : std_logic;
signal fifo_tbt_pos_in : std_logic_vector(c_cdc_data_pos_width-1 downto 0);
signal fifo_tbt_pos_out : std_logic_vector(c_cdc_data_pos_width-1 downto 0);
signal fifo_tbt_pos_valid_in : std_logic;
signal fifo_tbt_pos_valid_out : std_logic;
signal fifo_fofb_decim_in : std_logic_vector(c_cdc_data_ref_iq_width-1 downto 0);
signal fifo_fofb_decim_out : std_logic_vector(c_cdc_data_ref_iq_width-1 downto 0);
signal fifo_fofb_decim_valid_in : std_logic;
signal fifo_fofb_decim_valid_out : std_logic;
signal fifo_fofb_amp_in : std_logic_vector(c_cdc_data_ref_width-1 downto 0);
signal fifo_fofb_amp_out : std_logic_vector(c_cdc_data_ref_width-1 downto 0);
signal fifo_fofb_amp_valid_in : std_logic;
signal fifo_fofb_amp_valid_out : std_logic;
signal fifo_fofb_pha_in : std_logic_vector(c_cdc_data_ref_width-1 downto 0);
signal fifo_fofb_pha_out : std_logic_vector(c_cdc_data_ref_width-1 downto 0);
signal fifo_fofb_pha_valid_in : std_logic;
signal fifo_fofb_pha_valid_out : std_logic;
signal fifo_fofb_pos_in : std_logic_vector(c_cdc_data_pos_width-1 downto 0);
signal fifo_fofb_pos_out : std_logic_vector(c_cdc_data_pos_width-1 downto 0);
signal fifo_fofb_pos_valid_in : std_logic;
signal fifo_fofb_pos_valid_out : std_logic;
signal fifo_monit_amp_in : std_logic_vector(c_cdc_data_ref_width-1 downto 0);
signal fifo_monit_amp_out : std_logic_vector(c_cdc_data_ref_width-1 downto 0);
signal fifo_monit_amp_valid_in : std_logic;
signal fifo_monit_amp_valid_out : std_logic;
signal fifo_monit_pos_in : std_logic_vector(c_cdc_data_pos_width-1 downto 0);
signal fifo_monit_pos_out : std_logic_vector(c_cdc_data_pos_width-1 downto 0);
signal fifo_monit_pos_valid_in : std_logic;
signal fifo_monit_pos_valid_out : std_logic;
signal fifo_monit_1_pos_in : std_logic_vector(c_cdc_data_pos_width-1 downto 0);
signal fifo_monit_1_pos_out : std_logic_vector(c_cdc_data_pos_width-1 downto 0);
signal fifo_monit_1_pos_valid_in : std_logic;
signal fifo_monit_1_pos_valid_out : std_logic;
---------------------------------------------------------
-- Clock Enable signals --
---------------------------------------------------------
signal clk_ce_1 : std_logic;
signal clk_ce_1112 : std_logic;
signal clk_ce_1390000 : std_logic;
signal clk_ce_2 : std_logic;
signal clk_ce_2224 : std_logic;
signal clk_ce_22240000 : std_logic;
signal clk_ce_222400000 : std_logic;
signal clk_ce_2780000 : std_logic;
signal clk_ce_35 : std_logic;
signal clk_ce_5000 : std_logic;
signal clk_ce_556 : std_logic;
signal clk_ce_5560000 : std_logic;
signal clk_ce_70 : std_logic;
signal clk_ce_11120000_int : std_logic;
signal clk_ce_111200000_int : std_logic;
-- Components instatiation
component wb_pos_calc_regs
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
fs_clk_i : in std_logic;
fs_clk2x_i : in std_logic;
regs_i : in t_pos_calc_in_registers;
regs_o : out t_pos_calc_out_registers
);
end component;
begin
-- fs_rst_n_i => fs_rst_n_i,
--sys_clr <= not fs_rst_n_i;
--sys_clr2x <= not fs_rst2x_n_i;
sys_clr <= '0';
sys_clr2x <= '0';
-----------------------------
-- WB Position Calc Core Address decoder
-----------------------------
-- We need 2 outputs, as in the same wishbone addressing range, 2
-- other wishbone peripherals must be driven:
--
-- 0 -> WB Position Calc Core Register Wishbone Interface
-- 1 -> WB Uncross module.
-- The Internal Wishbone B.4 crossbar
cmp_interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => true, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_in,
slave_o => cbar_slave_out,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_in,
master_o => cbar_master_out
);
-- External master connection
cbar_slave_in(0).adr <= wb_adr_i;
cbar_slave_in(0).dat <= wb_dat_i;
cbar_slave_in(0).sel <= wb_sel_i;
cbar_slave_in(0).we <= wb_we_i;
cbar_slave_in(0).cyc <= wb_cyc_i;
cbar_slave_in(0).stb <= wb_stb_i;
wb_dat_o <= cbar_slave_out(0).dat;
wb_ack_o <= cbar_slave_out(0).ack;
wb_stall_o <= cbar_slave_out(0).stall;
-----------------------------
-- Slave adapter for Wishbone Register Interface
-----------------------------
cmp_slave_adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => PIPELINED,
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity
)
port map (
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
master_i => wb_slv_adp_in,
master_o => wb_slv_adp_out,
sl_adr_i => resized_addr,
sl_dat_i => cbar_master_out(0).dat,
sl_sel_i => cbar_master_out(0).sel,
sl_cyc_i => cbar_master_out(0).cyc,
sl_stb_i => cbar_master_out(0).stb,
sl_we_i => cbar_master_out(0).we,
sl_dat_o => cbar_master_in(0).dat,
sl_ack_o => cbar_master_in(0).ack,
sl_rty_o => cbar_master_in(0).rty,
sl_err_o => cbar_master_in(0).err,
sl_int_o => cbar_master_in(0).int,
sl_stall_o => cbar_master_in(0).stall
);
resized_addr(c_periph_addr_size-1 downto 0)
<= cbar_master_out(0).adr(c_periph_addr_size-1 downto 0);
resized_addr(c_wishbone_address_width-1 downto c_periph_addr_size)
<= (others => '0');
-----------------------------
-- Position Calc Core Register Wishbone Interface. Word addressed!
-----------------------------
--Position Calc Core register interface is the slave number 0, word addressed
cmp_wb_pos_calc_regs : wb_pos_calc_regs
port map(
rst_n_i => rst_n_i,
clk_sys_i => clk_i,
wb_adr_i => wb_slv_adp_out.adr(4 downto 0),
wb_dat_i => wb_slv_adp_out.dat,
wb_dat_o => wb_slv_adp_in.dat,
wb_cyc_i => wb_slv_adp_out.cyc,
wb_sel_i => wb_slv_adp_out.sel,
wb_stb_i => wb_slv_adp_out.stb,
wb_we_i => wb_slv_adp_out.we,
wb_ack_o => wb_slv_adp_in.ack,
wb_stall_o => wb_slv_adp_in.stall,
fs_clk_i => fs_clk_i,
fs_clk2x_i => fs_clk2x_i,
regs_i => regs_in,
regs_o => regs_out
);
-- Unused wishbone signals
wb_slv_adp_in.int <= '0';
wb_slv_adp_in.err <= '0';
wb_slv_adp_in.rty <= '0';
-- Registers fixed assignments
regs_in.ds_tbt_thres_reserved_i <= (others => '0');
regs_in.ds_fofb_thres_reserved_i <= (others => '0');
regs_in.ds_monit_thres_reserved_i <= (others => '0');
regs_in.kx_reserved_i <= (others => '0');
regs_in.ky_reserved_i <= (others => '0');
regs_in.ksum_reserved_i <= (others => '0');
regs_in.dds_cfg_reserved_ch0_i <= (others => '0');
regs_in.dds_cfg_reserved_ch1_i <= (others => '0');
regs_in.dds_cfg_reserved_ch2_i <= (others => '0');
regs_in.dds_cfg_reserved_ch3_i <= (others => '0');
regs_in.dds_pinc_ch0_reserved_i <= (others => '0');
regs_in.dds_pinc_ch1_reserved_i <= (others => '0');
regs_in.dds_pinc_ch2_reserved_i <= (others => '0');
regs_in.dds_pinc_ch3_reserved_i <= (others => '0');
regs_in.dds_poff_ch0_reserved_i <= (others => '0');
regs_in.dds_poff_ch1_reserved_i <= (others => '0');
regs_in.dds_poff_ch2_reserved_i <= (others => '0');
regs_in.dds_poff_ch3_reserved_i <= (others => '0');
-- Sync with fs_clk
regs_in.dsp_monit_amp_ch0_i <=
std_logic_vector(resize(signed(monit_amp_ch0_fs_sync), regs_in.dsp_monit_amp_ch0_i'length));
regs_in.dsp_monit_amp_ch1_i <=
std_logic_vector(resize(signed(monit_amp_ch1_fs_sync), regs_in.dsp_monit_amp_ch1_i'length));
regs_in.dsp_monit_amp_ch2_i <=
std_logic_vector(resize(signed(monit_amp_ch2_fs_sync), regs_in.dsp_monit_amp_ch2_i'length));
regs_in.dsp_monit_amp_ch3_i <=
std_logic_vector(resize(signed(monit_amp_ch3_fs_sync), regs_in.dsp_monit_amp_ch3_i'length));
-- Sync with fs_clk
regs_in.dsp_monit_pos_x_i <=
std_logic_vector(resize(signed(x_monit_fs_sync), regs_in.dsp_monit_pos_x_i'length));
regs_in.dsp_monit_pos_y_i <=
std_logic_vector(resize(signed(y_monit_fs_sync), regs_in.dsp_monit_pos_y_i'length));
regs_in.dsp_monit_pos_q_i <=
std_logic_vector(resize(signed(q_monit_fs_sync), regs_in.dsp_monit_pos_q_i'length));
regs_in.dsp_monit_pos_sum_i <=
std_logic_vector(resize(signed(sum_monit_fs_sync), regs_in.dsp_monit_pos_sum_i'length));
-----------------------------
-- BPM Swap Module.
-----------------------------
-- BPM Swap Module interface is the slave number 1
cmp_wb_bpm_swap : wb_bpm_swap
generic map
(
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity
)
port map
(
rst_n_i => rst_n_i,
clk_sys_i => clk_i,
fs_clk_i => fs_clk_i,
fs_rst_n_i => fs_rst_n_i,
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i => cbar_master_out(1).adr,
wb_dat_i => cbar_master_out(1).dat,
wb_dat_o => cbar_master_in(1).dat,
wb_sel_i => cbar_master_out(1).sel,
wb_we_i => cbar_master_out(1).we,
wb_cyc_i => cbar_master_out(1).cyc,
wb_stb_i => cbar_master_out(1).stb,
wb_ack_o => cbar_master_in(1).ack,
wb_stall_o => cbar_master_in(1).stall,
-----------------------------
-- External ports
-----------------------------
-- Input from ADC FMC board
cha_i => adc_ch0_i,
chb_i => adc_ch1_i,
chc_i => adc_ch2_i,
chd_i => adc_ch3_i,
-- Output to data processing level
cha_o => adc_ch0_sp,
chb_o => adc_ch1_sp,
chc_o => adc_ch2_sp,
chd_o => adc_ch3_sp,
mode1_o => sw_mode1,
mode2_o => sw_mode2,
wdw_rst_o => wdw_rst,
wdw_sw_clk_i => wdw_sw_clk_in,
wdw_use_o => wdw_use_en,
wdw_dly_o => wdw_dly,
-- Output to RFFE board
clk_swap_o => clk_swap_o,
clk_swap_en_o => clk_swap_en,
flag1_o => flag1_o,
flag2_o => flag2_o,
ctrl1_o => ctrl1_o,
ctrl2_o => ctrl2_o
);
wdw_sw_clk_in <= wdw_sw_clk;
wdw_rst_n <= not wdw_rst;
adc_ch0_dbg_data_o <= adc_ch0_sp;
adc_ch1_dbg_data_o <= adc_ch1_sp;
adc_ch2_dbg_data_o <= adc_ch2_sp;
adc_ch3_dbg_data_o <= adc_ch3_sp;
cmp_input_conditioner : input_conditioner
generic map
(
g_sw_interval => 1000/2, -- We need to generate 2x the FOFB decimation rate
g_input_width => 16, -- FIXME: use ADC constant
g_output_width => 16, -- FIXME: use ADC constant
g_window_width => 24, -- This must match the MATLAB script
g_input_delay => 2+3, -- wb_bpm_swap fixed latency + multiplier pipeline latency
g_window_coef_file => f_window_file(g_rffe_version)
)
port map
(
reset_n_i => wdw_input_cond_rst_n,
clk_i => fs_clk_i,
adc_a_i => adc_ch0_sp,
adc_b_i => adc_ch1_sp,
adc_c_i => adc_ch2_sp,
adc_d_i => adc_ch3_sp,
switch_o => wdw_sw_clk,
switch_en_i => clk_swap_en,
switch_delay_i => wdw_dly,
a_o => adc_ch0_cond,
b_o => adc_ch1_cond,
c_o => adc_ch2_cond,
d_o => adc_ch3_cond,
dbg_cur_address_o => dbg_cur_address_o
);
wdw_input_cond_rst_n <= fs_rst_n_i or wdw_rst_n;
dbg_adc_ch0_cond_o <= adc_ch0_cond;
dbg_adc_ch1_cond_o <= adc_ch1_cond;
dbg_adc_ch2_cond_o <= adc_ch2_cond;
dbg_adc_ch3_cond_o <= adc_ch3_cond;
-- Bypass windowing conditioning if switching is disabled
--
-- sw_mode1 controls channels 0 and 2 : "00" is matched,
-- "01" is direct, "10" is inverted, "11" is switching
--
-- sw_mode2 controls channels 1 and 3 : "00" is matched,
-- "01" is direct, "10" is inverted, "11" is switching
--adc_ch0_pos_calc <= adc_ch0_cond when sw_mode1 = "11" else adc_ch0_sp;
--adc_ch1_pos_calc <= adc_ch1_cond when sw_mode2 = "11" else adc_ch1_sp;
--adc_ch2_pos_calc <= adc_ch2_cond when sw_mode1 = "11" else adc_ch2_sp;
--adc_ch3_pos_calc <= adc_ch3_cond when sw_mode2 = "11" else adc_ch3_sp;
adc_ch0_pos_calc <= adc_ch0_cond when wdw_use_en = '1' else adc_ch0_sp;
adc_ch1_pos_calc <= adc_ch1_cond when wdw_use_en = '1' else adc_ch1_sp;
adc_ch2_pos_calc <= adc_ch2_cond when wdw_use_en = '1' else adc_ch2_sp;
adc_ch3_pos_calc <= adc_ch3_cond when wdw_use_en = '1' else adc_ch3_sp;
cmp_position_calc: position_calc
generic map
(
g_pipeline_regs => c_num_pipeline_regs
)
port map
(
adc_ch0_i => adc_ch0_pos_calc,
adc_ch1_i => adc_ch1_pos_calc,
adc_ch2_i => adc_ch2_pos_calc,
adc_ch3_i => adc_ch3_pos_calc,
clk => fs_clk2x_i,
clr => sys_clr2x,
del_sig_div_fofb_thres_i => regs_out.ds_tbt_thres_val_o,
del_sig_div_monit_thres_i => regs_out.ds_fofb_thres_val_o,
del_sig_div_tbt_thres_i => regs_out.ds_monit_thres_val_o,
ksum_i => regs_out.ksum_val_o,
kx_i => regs_out.kx_val_o,
ky_i => regs_out.ky_val_o,
dds_config_valid_ch0_i => regs_out.dds_cfg_valid_ch0_o,
dds_config_valid_ch1_i => regs_out.dds_cfg_valid_ch1_o,
dds_config_valid_ch2_i => regs_out.dds_cfg_valid_ch2_o,
dds_config_valid_ch3_i => regs_out.dds_cfg_valid_ch3_o,
dds_pinc_ch0_i => regs_out.dds_pinc_ch0_val_o,
dds_pinc_ch1_i => regs_out.dds_pinc_ch1_val_o,
dds_pinc_ch2_i => regs_out.dds_pinc_ch2_val_o,
dds_pinc_ch3_i => regs_out.dds_pinc_ch3_val_o,
dds_poff_ch0_i => regs_out.dds_poff_ch0_val_o,
dds_poff_ch1_i => regs_out.dds_poff_ch1_val_o,
dds_poff_ch2_i => regs_out.dds_poff_ch2_val_o,
dds_poff_ch3_i => regs_out.dds_poff_ch3_val_o,
--adc_ch0_dbg_data_o => adc_ch0_dbg_data_o,
--adc_ch1_dbg_data_o => adc_ch1_dbg_data_o,
--adc_ch2_dbg_data_o => adc_ch2_dbg_data_o,
--adc_ch3_dbg_data_o => adc_ch3_dbg_data_o,
adc_ch0_dbg_data_o => open,
adc_ch1_dbg_data_o => open,
adc_ch2_dbg_data_o => open,
adc_ch3_dbg_data_o => open,
bpf_ch0_o => bpf_ch0,
bpf_ch1_o => bpf_ch1,
bpf_ch2_o => bpf_ch2,
bpf_ch3_o => bpf_ch3,
mix_ch0_i_o => mix_ch0_i,
mix_ch0_q_o => mix_ch0_q,
mix_ch1_i_o => mix_ch1_i,
mix_ch1_q_o => mix_ch1_q,
mix_ch2_i_o => mix_ch2_i,
mix_ch2_q_o => mix_ch2_q,
mix_ch3_i_o => mix_ch3_i,
mix_ch3_q_o => mix_ch3_q,
tbt_decim_ch0_i_o => tbt_decim_ch0_i,
tbt_decim_ch0_q_o => tbt_decim_ch0_q,
tbt_decim_ch1_i_o => tbt_decim_ch1_i,
tbt_decim_ch1_q_o => tbt_decim_ch1_q,
tbt_decim_ch2_i_o => tbt_decim_ch2_i,
tbt_decim_ch2_q_o => tbt_decim_ch2_q,
tbt_decim_ch3_i_o => tbt_decim_ch3_i,
tbt_decim_ch3_q_o => tbt_decim_ch3_q,
tbt_decim_q_ch01_incorrect_o => tbt_decim_q_ch01_incorrect_int,
tbt_decim_q_ch23_incorrect_o => tbt_decim_q_ch23_incorrect_int,
tbt_amp_ch0_o => tbt_amp_ch0,
tbt_amp_ch1_o => tbt_amp_ch1,
tbt_amp_ch2_o => tbt_amp_ch2,
tbt_amp_ch3_o => tbt_amp_ch3,
tbt_pha_ch0_o => tbt_pha_ch0,
tbt_pha_ch1_o => tbt_pha_ch1,
tbt_pha_ch2_o => tbt_pha_ch2,
tbt_pha_ch3_o => tbt_pha_ch3,
fofb_decim_ch0_i_o => fofb_decim_ch0_i,
fofb_decim_ch0_q_o => fofb_decim_ch0_q,
fofb_decim_ch1_i_o => fofb_decim_ch1_i,
fofb_decim_ch1_q_o => fofb_decim_ch1_q,
fofb_decim_ch2_i_o => fofb_decim_ch2_i,
fofb_decim_ch2_q_o => fofb_decim_ch2_q,
fofb_decim_ch3_i_o => fofb_decim_ch3_i,
fofb_decim_ch3_q_o => fofb_decim_ch3_q,
fofb_decim_q_01_missing_o => fofb_decim_q_ch01_missing_int,
fofb_decim_q_23_missing_o => fofb_decim_q_ch23_missing_int,
fofb_amp_ch0_o => fofb_amp_ch0,
fofb_amp_ch1_o => fofb_amp_ch1,
fofb_amp_ch2_o => fofb_amp_ch2,
fofb_amp_ch3_o => fofb_amp_ch3,
fofb_pha_ch0_o => fofb_pha_ch0,
fofb_pha_ch1_o => fofb_pha_ch1,
fofb_pha_ch2_o => fofb_pha_ch2,
fofb_pha_ch3_o => fofb_pha_ch3,
monit_amp_ch0_o => monit_amp_ch0,
monit_amp_ch1_o => monit_amp_ch1,
monit_amp_ch2_o => monit_amp_ch2,
monit_amp_ch3_o => monit_amp_ch3,
monit_cic_unexpected_o => monit_cic_unexpected_int,
monit_cfir_incorrect_o => monit_cfir_incorrect_int,
monit_pfir_incorrect_o => monit_pfir_incorrect_int,
x_tbt_o => x_tbt,
x_tbt_valid_o => x_tbt_valid,
y_tbt_o => y_tbt,
y_tbt_valid_o => y_tbt_valid, -- will be removed soon
q_tbt_o => q_tbt,
q_tbt_valid_o => q_tbt_valid, -- will be removed soon
sum_tbt_o => sum_tbt,
sum_tbt_valid_o => sum_tbt_valid, -- will be removed soon
x_fofb_o => x_fofb,
x_fofb_valid_o => x_fofb_valid,
y_fofb_o => y_fofb,
y_fofb_valid_o => y_fofb_valid, -- will be removed soon
q_fofb_o => q_fofb,
q_fofb_valid_o => q_fofb_valid, -- will be removed soon
sum_fofb_o => sum_fofb,
sum_fofb_valid_o => sum_fofb_valid,-- will be removed soon
x_monit_o => x_monit,
x_monit_valid_o => x_monit_valid,
y_monit_o => y_monit,
y_monit_valid_o => y_monit_valid, -- will be removed soon
q_monit_o => q_monit,
q_monit_valid_o => q_monit_valid, -- will be removed soon
sum_monit_o => sum_monit,
sum_monit_valid_o => sum_monit_valid, -- will be removed soon
x_monit_1_o => x_monit_1,
x_monit_1_valid_o => x_monit_1_valid,
y_monit_1_o => y_monit_1,
y_monit_1_valid_o => y_monit_1_valid, -- will be removed soon
q_monit_1_o => q_monit_1,
q_monit_1_valid_o => q_monit_1_valid, -- will be removed soon
sum_monit_1_o => sum_monit_1,
sum_monit_1_valid_o => sum_monit_1_valid,-- will be removed soon
monit_pos_1_incorrect_o => monit_pos_1_incorrect_int,
-- Clock drivers for various rates
clk_ce_1_o => clk_ce_1,
clk_ce_1112_o => clk_ce_1112,
clk_ce_1390000_o => clk_ce_1390000,
clk_ce_2_o => clk_ce_2,
clk_ce_2224_o => clk_ce_2224,
clk_ce_22240000_o => clk_ce_22240000,
clk_ce_222400000_o => clk_ce_222400000,
clk_ce_2780000_o => clk_ce_2780000,
clk_ce_35_o => clk_ce_35,
clk_ce_5000_o => clk_ce_5000,
clk_ce_556_o => clk_ce_556,
clk_ce_5560000_o => clk_ce_5560000,
clk_ce_70_o => clk_ce_70
);
--------------------------------------------------------------------------
-- Missing CE --
--------------------------------------------------------------------------
-- Generate missing clk_ce_11120000
cmp_xlclockdriver_clk_ce_11120000 : xlclockdriver
generic map (
log_2_period => 24,
period => 11200000, -- FIXME: Change CE net name to the correct ones! This is just to avoid changing the interface
pipeline_regs => c_num_pipeline_regs,
use_bufg => 0
)
port map (
sysce => '1',
sysclk => fs_clk2x_i,
sysclr => sys_clr2x,
ce => clk_ce_11120000_int,
clk => open
);
clk_ce_11120000_o <= clk_ce_11120000_int;
-- Generate missing clk_ce_111200000
cmp_xlclockdriver_clk_ce_111200000 : xlclockdriver
generic map (
log_2_period => 27,
period => 112000000, -- FIXME: Change CE net name to the correct ones! This is just to avoid changing the interface
pipeline_regs => c_num_pipeline_regs,
use_bufg => 0
)
port map (
sysce => '1',
sysclk => fs_clk2x_i,
sysclr => sys_clr2x,
ce => clk_ce_111200000_int,
clk => open
);
clk_ce_111200000_o <= clk_ce_111200000_int;
-- Output CE
clk_ce_1_o <= clk_ce_1;
clk_ce_1112_o <= clk_ce_1112;
clk_ce_1390000_o <= clk_ce_1390000;
clk_ce_2_o <= clk_ce_2;
clk_ce_2224_o <= clk_ce_2224;
clk_ce_22240000_o <= clk_ce_22240000;
clk_ce_222400000_o <= clk_ce_222400000;
clk_ce_2780000_o <= clk_ce_2780000;
clk_ce_35_o <= clk_ce_35;
clk_ce_5000_o <= clk_ce_5000;
clk_ce_556_o <= clk_ce_556;
clk_ce_5560000_o <= clk_ce_5560000;
clk_ce_70_o <= clk_ce_70;
--------------------------------------------------------------------------
-- Position Calc Counters
--------------------------------------------------------------------------
cmp_position_calc_counters : position_calc_counters
port map
(
fs_clk2x_i => fs_clk2x_i,-- clock period = 4.44116091946435 ns (225.16635135135124 Mhz)
fs_rst2x_n_i => fs_rst2x_n_i,
-- Clock enables for various rates
tbt_ce_i => clk_ce_70,
fofb_ce_i => clk_ce_2224,
monit_cic_ce_i => clk_ce_5560000,
monit_cfir_ce_i => clk_ce_11120000_int, -- check this rate!
monit_pfir_ce_i => clk_ce_22240000,
monit_01_ce_i => clk_ce_222400000,
tbt_decim_q_ch01_incorrect_i => tbt_decim_q_ch01_incorrect_int,
tbt_decim_q_ch23_incorrect_i => tbt_decim_q_ch23_incorrect_int,
tbt_decim_err_clr_i => regs_out.dsp_err_clr_tbt_o,
fofb_decim_q_ch01_missing_i => fofb_decim_q_ch01_missing_int,
fofb_decim_q_ch23_missing_i => fofb_decim_q_ch23_missing_int,
fofb_decim_err_clr_i => regs_out.dsp_err_clr_fofb_o,
monit_cic_unexpected_i => monit_cic_unexpected_int,
monit_cfir_incorrect_i => monit_cfir_incorrect_int,
monit_part1_err_clr_i => regs_out.dsp_err_clr_monit_part1_o,
monit_pfir_incorrect_i => monit_pfir_incorrect_int,
monit_pos_1_incorrect_i => monit_pos_1_incorrect_int,
monit_part2_err_clr_i => regs_out.dsp_err_clr_monit_part2_o,
tbt_incorrect_ctnr_ch01_o => regs_in.dsp_ctnr_tbt_ch01_i,
tbt_incorrect_ctnr_ch23_o => regs_in.dsp_ctnr_tbt_ch23_i,
fofb_incorrect_ctnr_ch01_o => regs_in.dsp_ctnr_fofb_ch01_i,
fofb_incorrect_ctnr_ch23_o => regs_in.dsp_ctnr_fofb_ch23_i,
monit_cic_incorrect_ctnr_o => regs_in.dsp_ctnr1_monit_cic_i,
monit_cfir_incorrect_ctnr_o => regs_in.dsp_ctnr1_monit_cfir_i,
monit_pfir_incorrect_ctnr_o => regs_in.dsp_ctnr2_monit_pfir_i,
monit_01_incorrect_ctnr_o => regs_in.dsp_ctnr2_monit_fir_01_i
);
--------------------------------------------------------------------------
-- CDC position data (Amplitudes and Position) to fs_clk domain --
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- MIX and BPF data --
--------------------------------------------------------------------------
-- BPF data
cmp_position_calc_cdc_fifo_bpf : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_ref_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_bpf_in,
valid_i => fifo_bpf_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_bpf_out,
valid_o => fifo_bpf_valid_out
);
p_reg_cdc_fifo_bpf_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_bpf_in <= (others => '0');
fifo_bpf_valid_in <= '0';
elsif clk_ce_2 = '1' then
fifo_bpf_in <= bpf_ch3 & -- 4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits
bpf_ch2 & -- 3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits
bpf_ch1 & -- 2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits
bpf_ch0; -- c_dsp_ref_num_bits-1 downto 0
fifo_bpf_valid_in <= bpf_valid;
else
fifo_bpf_valid_in <= '0';
end if;
end if;
end process;
bpf_ch3_o <= fifo_bpf_out(4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits);
bpf_ch2_o <= fifo_bpf_out(3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits);
bpf_ch1_o <= fifo_bpf_out(2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits);
bpf_ch0_o <= fifo_bpf_out(c_dsp_ref_num_bits-1 downto 0);
bpf_valid_o <= fifo_bpf_valid_out;
-- MIX data
cmp_position_calc_cdc_fifo_mix : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_ref_iq_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_mix_in,
valid_i => fifo_mix_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_mix_out,
valid_o => fifo_mix_valid_out
);
p_reg_cdc_fifo_mix_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_mix_in <= (others => '0');
fifo_mix_valid_in <= '0';
elsif clk_ce_2 = '1' then
fifo_mix_in <= mix_ch3_q & -- 8*c_dsp_ref_num_bits-1 downto 7*c_dsp_ref_num_bits
mix_ch3_i & -- 7*c_dsp_ref_num_bits-1 downto 6*c_dsp_ref_num_bits
mix_ch2_q & -- 6*c_dsp_ref_num_bits-1 downto 5*c_dsp_ref_num_bits
mix_ch2_i & -- 5*c_dsp_ref_num_bits-1 downto 4*c_dsp_ref_num_bits
mix_ch1_q & -- 4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits
mix_ch1_i & -- 3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits
mix_ch0_q & -- 2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits
mix_ch0_i; -- c_dsp_ref_num_bits-1 downto 0
fifo_mix_valid_in <= mix_valid;
else
fifo_mix_valid_in <= '0';
end if;
end if;
end process;
mix_ch3_q_o <= fifo_mix_out(8*c_dsp_ref_num_bits-1 downto 7*c_dsp_ref_num_bits);
mix_ch3_i_o <= fifo_mix_out(7*c_dsp_ref_num_bits-1 downto 6*c_dsp_ref_num_bits);
mix_ch2_q_o <= fifo_mix_out(6*c_dsp_ref_num_bits-1 downto 5*c_dsp_ref_num_bits);
mix_ch2_i_o <= fifo_mix_out(5*c_dsp_ref_num_bits-1 downto 4*c_dsp_ref_num_bits);
mix_ch1_q_o <= fifo_mix_out(4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits);
mix_ch1_i_o <= fifo_mix_out(3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits);
mix_ch0_q_o <= fifo_mix_out(2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits);
mix_ch0_i_o <= fifo_mix_out(c_dsp_ref_num_bits-1 downto 0);
mix_valid_o <= fifo_mix_valid_out;
--------------------------------------------------------------------------
-- TBT data --
--------------------------------------------------------------------------
-- TBT Decim data
cmp_position_calc_cdc_fifo_tbt_decim : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_ref_iq_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_tbt_decim_in,
valid_i => fifo_tbt_decim_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_tbt_decim_out,
valid_o => fifo_tbt_decim_valid_out
);
p_reg_cdc_fifo_tbt_decim_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_tbt_decim_in <= (others => '0');
fifo_tbt_decim_valid_in <= '0';
elsif clk_ce_70 = '1' then
fifo_tbt_decim_in <= tbt_decim_ch3_q & -- 8*c_dsp_ref_num_bits-1 downto 7*c_dsp_ref_num_bits
tbt_decim_ch3_i & -- 7*c_dsp_ref_num_bits-1 downto 6*c_dsp_ref_num_bits
tbt_decim_ch2_q & -- 6*c_dsp_ref_num_bits-1 downto 5*c_dsp_ref_num_bits
tbt_decim_ch2_i & -- 5*c_dsp_ref_num_bits-1 downto 4*c_dsp_ref_num_bits
tbt_decim_ch1_q & -- 4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits
tbt_decim_ch1_i & -- 3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits
tbt_decim_ch0_q & -- 2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits
tbt_decim_ch0_i; -- c_dsp_ref_num_bits-1 downto 0
fifo_tbt_decim_valid_in <= tbt_decim_valid;
else
fifo_tbt_decim_valid_in <= '0';
end if;
end if;
end process;
tbt_decim_ch3_q_o <= fifo_tbt_decim_out(8*c_dsp_ref_num_bits-1 downto 7*c_dsp_ref_num_bits);
tbt_decim_ch3_i_o <= fifo_tbt_decim_out(7*c_dsp_ref_num_bits-1 downto 6*c_dsp_ref_num_bits);
tbt_decim_ch2_q_o <= fifo_tbt_decim_out(6*c_dsp_ref_num_bits-1 downto 5*c_dsp_ref_num_bits);
tbt_decim_ch2_i_o <= fifo_tbt_decim_out(5*c_dsp_ref_num_bits-1 downto 4*c_dsp_ref_num_bits);
tbt_decim_ch1_q_o <= fifo_tbt_decim_out(4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits);
tbt_decim_ch1_i_o <= fifo_tbt_decim_out(3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits);
tbt_decim_ch0_q_o <= fifo_tbt_decim_out(2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits);
tbt_decim_ch0_i_o <= fifo_tbt_decim_out(c_dsp_ref_num_bits-1 downto 0);
tbt_decim_valid_o <= fifo_tbt_decim_valid_out;
--TBT amplitudes data
cmp_position_calc_cdc_fifo_tbt_amp : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_ref_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_tbt_amp_in,
valid_i => fifo_tbt_amp_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_tbt_amp_out,
valid_o => fifo_tbt_amp_valid_out
);
p_reg_cdc_fifo_tbt_amp_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_tbt_amp_in <= (others => '0');
fifo_tbt_amp_valid_in <= '0';
elsif clk_ce_70 = '1' then
fifo_tbt_amp_in <= tbt_amp_ch3 & -- 4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits
tbt_amp_ch2 & -- 3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits
tbt_amp_ch1 & -- 2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits
tbt_amp_ch0; -- c_dsp_ref_num_bits-1 downto 0
fifo_tbt_amp_valid_in <= tbt_amp_valid;
else
fifo_tbt_amp_valid_in <= '0';
end if;
end if;
end process;
tbt_amp_ch3_o <= fifo_tbt_amp_out(4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits);
tbt_amp_ch2_o <= fifo_tbt_amp_out(3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits);
tbt_amp_ch1_o <= fifo_tbt_amp_out(2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits);
tbt_amp_ch0_o <= fifo_tbt_amp_out(c_dsp_ref_num_bits-1 downto 0);
tbt_amp_valid_o <= fifo_tbt_amp_valid_out;
--TBT phase data
cmp_position_calc_cdc_fifo_tbt_phase : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_ref_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_tbt_pha_in,
valid_i => fifo_tbt_pha_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_tbt_pha_out,
valid_o => fifo_tbt_pha_valid_out
);
p_reg_cdc_fifo_tbt_pha_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_tbt_pha_in <= (others => '0');
fifo_tbt_pha_valid_in <= '0';
elsif clk_ce_70 = '1' then
fifo_tbt_pha_in <= tbt_pha_ch3 & -- 4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits
tbt_pha_ch2 & -- 3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits
tbt_pha_ch1 & -- 2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits
tbt_pha_ch0; -- c_dsp_ref_num_bits-1 downto 0
fifo_tbt_pha_valid_in <= tbt_pha_valid;
else
fifo_tbt_pha_valid_in <= '0';
end if;
end if;
end process;
tbt_pha_ch3_o <= fifo_tbt_pha_out(4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits);
tbt_pha_ch2_o <= fifo_tbt_pha_out(3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits);
tbt_pha_ch1_o <= fifo_tbt_pha_out(2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits);
tbt_pha_ch0_o <= fifo_tbt_pha_out(c_dsp_ref_num_bits-1 downto 0);
tbt_pha_valid_o <= fifo_tbt_pha_valid_out;
-- TBT position data
cmp_position_calc_cdc_fifo_tbt_pos : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_pos_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_tbt_pos_in,
valid_i => fifo_tbt_pos_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_tbt_pos_out,
valid_o => fifo_tbt_pos_valid_out
);
p_reg_cdc_fifo_tbt_pos_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_tbt_pos_in <= (others => '0');
fifo_tbt_pos_valid_in <= '0';
elsif clk_ce_70 = '1' then
fifo_tbt_pos_in <= sum_tbt & -- 4*c_dsp_pos_num_bits-1 downto 3*c_dsp_pos_num_bits
q_tbt & -- 3*c_dsp_pos_num_bits-1 downto 2*c_dsp_pos_num_bits
y_tbt & -- 2*c_dsp_pos_num_bits-1 downto c_dsp_pos_num_bits
x_tbt; -- c_dsp_pos_num_bits-1 downto 0
fifo_tbt_pos_valid_in <= x_tbt_valid;
else
fifo_tbt_pos_valid_in <= '0';
end if;
end if;
end process;
pos_sum_tbt_o <= fifo_tbt_pos_out(4*c_dsp_pos_num_bits-1 downto 3*c_dsp_pos_num_bits);
pos_q_tbt_o <= fifo_tbt_pos_out(3*c_dsp_pos_num_bits-1 downto 2*c_dsp_pos_num_bits);
pos_y_tbt_o <= fifo_tbt_pos_out(2*c_dsp_pos_num_bits-1 downto c_dsp_pos_num_bits);
pos_x_tbt_o <= fifo_tbt_pos_out(c_dsp_pos_num_bits-1 downto 0);
pos_tbt_valid_o <= fifo_tbt_pos_valid_out;
--------------------------------------------------------------------------
-- FOFB data --
--------------------------------------------------------------------------
-- FOFB Decim data
cmp_position_calc_cdc_fifo_fofb_decim : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_ref_iq_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_fofb_decim_in,
valid_i => fifo_fofb_decim_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_fofb_decim_out,
valid_o => fifo_fofb_decim_valid_out
);
p_reg_cdc_fifo_fofb_decim_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_fofb_decim_in <= (others => '0');
fifo_fofb_decim_valid_in <= '0';
elsif clk_ce_2224 = '1' then
fifo_fofb_decim_in <= fofb_decim_ch3_q & -- 8*c_dsp_ref_num_bits-1 downto 7*c_dsp_ref_num_bits
fofb_decim_ch3_i & -- 7*c_dsp_ref_num_bits-1 downto 6*c_dsp_ref_num_bits
fofb_decim_ch2_q & -- 6*c_dsp_ref_num_bits-1 downto 5*c_dsp_ref_num_bits
fofb_decim_ch2_i & -- 5*c_dsp_ref_num_bits-1 downto 4*c_dsp_ref_num_bits
fofb_decim_ch1_q & -- 4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits
fofb_decim_ch1_i & -- 3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits
fofb_decim_ch0_q & -- 2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits
fofb_decim_ch0_i; -- c_dsp_ref_num_bits-1 downto 0
fifo_fofb_decim_valid_in <= fofb_decim_valid;
else
fifo_fofb_decim_valid_in <= '0';
end if;
end if;
end process;
fofb_decim_ch3_q_o <= fifo_fofb_decim_out(8*c_dsp_ref_num_bits-1 downto 7*c_dsp_ref_num_bits);
fofb_decim_ch3_i_o <= fifo_fofb_decim_out(7*c_dsp_ref_num_bits-1 downto 6*c_dsp_ref_num_bits);
fofb_decim_ch2_q_o <= fifo_fofb_decim_out(6*c_dsp_ref_num_bits-1 downto 5*c_dsp_ref_num_bits);
fofb_decim_ch2_i_o <= fifo_fofb_decim_out(5*c_dsp_ref_num_bits-1 downto 4*c_dsp_ref_num_bits);
fofb_decim_ch1_q_o <= fifo_fofb_decim_out(4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits);
fofb_decim_ch1_i_o <= fifo_fofb_decim_out(3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits);
fofb_decim_ch0_q_o <= fifo_fofb_decim_out(2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits);
fofb_decim_ch0_i_o <= fifo_fofb_decim_out(c_dsp_ref_num_bits-1 downto 0);
fofb_decim_valid_o <= fifo_fofb_decim_valid_out;
--FOFB amplitudes data
cmp_position_calc_cdc_fifo_fofb_amp : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_ref_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_fofb_amp_in,
valid_i => fifo_fofb_amp_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_fofb_amp_out,
valid_o => fifo_fofb_amp_valid_out
);
p_reg_cdc_fifo_fofb_amp_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_fofb_amp_in <= (others => '0');
fifo_fofb_amp_valid_in <= '0';
elsif clk_ce_2224 = '1' then
fifo_fofb_amp_in <= fofb_amp_ch3 & -- 4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits
fofb_amp_ch2 & -- 3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits
fofb_amp_ch1 & -- 2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits
fofb_amp_ch0; -- c_dsp_ref_num_bits-1 downto 0
fifo_fofb_amp_valid_in <= fofb_amp_valid;
else
fifo_fofb_amp_valid_in <= '0';
end if;
end if;
end process;
fofb_amp_ch3_o <= fifo_fofb_amp_out(4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits);
fofb_amp_ch2_o <= fifo_fofb_amp_out(3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits);
fofb_amp_ch1_o <= fifo_fofb_amp_out(2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits);
fofb_amp_ch0_o <= fifo_fofb_amp_out(c_dsp_ref_num_bits-1 downto 0);
fofb_amp_valid_o <= fifo_fofb_amp_valid_out;
-- FOFB phase data
cmp_position_calc_cdc_fifo_fofb_phase : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_ref_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_fofb_pha_in,
valid_i => fifo_fofb_pha_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_fofb_pha_out,
valid_o => fifo_fofb_pha_valid_out
);
p_reg_cdc_fifo_fofb_pha_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_fofb_pha_in <= (others => '0');
fifo_fofb_pha_valid_in <= '0';
elsif clk_ce_2224 = '1' then
fifo_fofb_pha_in <= fofb_pha_ch3 & -- 4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits
fofb_pha_ch2 & -- 3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits
fofb_pha_ch1 & -- 2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits
fofb_pha_ch0; -- c_dsp_ref_num_bits-1 downto 0
fifo_fofb_pha_valid_in <= fofb_pha_valid;
else
fifo_fofb_pha_valid_in <= '0';
end if;
end if;
end process;
fofb_pha_ch3_o <= fifo_fofb_pha_out(4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits);
fofb_pha_ch2_o <= fifo_fofb_pha_out(3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits);
fofb_pha_ch1_o <= fifo_fofb_pha_out(2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits);
fofb_pha_ch0_o <= fifo_fofb_pha_out(c_dsp_ref_num_bits-1 downto 0);
fofb_pha_valid_o <= fifo_fofb_pha_valid_out;
-- FOFB position data
cmp_position_calc_cdc_fifo_fofb_pos : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_pos_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_fofb_pos_in,
valid_i => fifo_fofb_pos_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_fofb_pos_out,
valid_o => fifo_fofb_pos_valid_out
);
p_reg_cdc_fifo_fofb_pos_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_fofb_pos_in <= (others => '0');
fifo_fofb_pos_valid_in <= '0';
elsif clk_ce_2224 = '1' then
fifo_fofb_pos_in <= sum_fofb & -- 4*c_dsp_pos_num_bits-1 downto 3*c_dsp_pos_num_bits
q_fofb & -- 3*c_dsp_pos_num_bits-1 downto 2*c_dsp_pos_num_bits
y_fofb & -- 2*c_dsp_pos_num_bits-1 downto c_dsp_pos_num_bits
x_fofb; -- c_dsp_pos_num_bits-1 downto 0
fifo_fofb_pos_valid_in <= x_fofb_valid;
else
fifo_fofb_pos_valid_in <= '0';
end if;
end if;
end process;
pos_sum_fofb_o <= fifo_fofb_pos_out(4*c_dsp_pos_num_bits-1 downto 3*c_dsp_pos_num_bits);
pos_q_fofb_o <= fifo_fofb_pos_out(3*c_dsp_pos_num_bits-1 downto 2*c_dsp_pos_num_bits);
pos_y_fofb_o <= fifo_fofb_pos_out(2*c_dsp_pos_num_bits-1 downto c_dsp_pos_num_bits);
pos_x_fofb_o <= fifo_fofb_pos_out(c_dsp_pos_num_bits-1 downto 0);
pos_fofb_valid_o <= fifo_fofb_pos_valid_out;
--------------------------------------------------------------------------
-- Monitoring data --
--------------------------------------------------------------------------
-- Monitoring amplitudes data
cmp_position_calc_cdc_fifo_monit_amp : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_ref_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_monit_amp_in,
valid_i => fifo_monit_amp_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_monit_amp_out,
valid_o => fifo_monit_amp_valid_out
);
p_reg_cdc_fifo_monit_amp_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_monit_amp_in <= (others => '0');
fifo_monit_amp_valid_in <= '0';
elsif clk_ce_22240000 = '1' then
fifo_monit_amp_in <= monit_amp_ch3 & -- 4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits
monit_amp_ch2 & -- 3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits
monit_amp_ch1 & -- 2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits
monit_amp_ch0; -- c_dsp_ref_num_bits-1 downto 0
fifo_monit_amp_valid_in <= monit_amp_valid;
else
fifo_monit_amp_valid_in <= '0';
end if;
end if;
end process;
monit_amp_ch3_fs_sync <= fifo_monit_amp_out(4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits);
monit_amp_ch2_fs_sync <= fifo_monit_amp_out(3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits);
monit_amp_ch1_fs_sync <= fifo_monit_amp_out(2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits);
monit_amp_ch0_fs_sync <= fifo_monit_amp_out(c_dsp_ref_num_bits-1 downto 0);
monit_amp_valid_fs_sync <= fifo_monit_amp_valid_out;
monit_amp_ch3_o <= monit_amp_ch3_fs_sync;
monit_amp_ch2_o <= monit_amp_ch2_fs_sync;
monit_amp_ch1_o <= monit_amp_ch1_fs_sync;
monit_amp_ch0_o <= monit_amp_ch0_fs_sync;
monit_amp_valid_o <= monit_amp_valid_fs_sync;
-- Monitoring position data
cmp_position_calc_cdc_fifo_monit_pos : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_pos_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_monit_pos_in,
valid_i => fifo_monit_pos_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_monit_pos_out,
valid_o => fifo_monit_pos_valid_out
);
p_reg_cdc_fifo_monit_pos_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_monit_pos_in <= (others => '0');
fifo_monit_pos_valid_in <= '0';
elsif clk_ce_22240000 = '1' then
fifo_monit_pos_in <= sum_monit & -- 4*c_dsp_pos_num_bits-1 downto 3*c_dsp_pos_num_bits
q_monit & -- 3*c_dsp_pos_num_bits-1 downto 2*c_dsp_pos_num_bits
y_monit & -- 2*c_dsp_pos_num_bits-1 downto c_dsp_pos_num_bits
x_monit; -- c_dsp_pos_num_bits-1 downto 0
fifo_monit_pos_valid_in <= x_monit_valid;
else
fifo_monit_pos_valid_in <= '0';
end if;
end if;
end process;
sum_monit_fs_sync <= fifo_monit_pos_out(4*c_dsp_pos_num_bits-1 downto 3*c_dsp_pos_num_bits);
q_monit_fs_sync <= fifo_monit_pos_out(3*c_dsp_pos_num_bits-1 downto 2*c_dsp_pos_num_bits);
y_monit_fs_sync <= fifo_monit_pos_out(2*c_dsp_pos_num_bits-1 downto c_dsp_pos_num_bits);
x_monit_fs_sync <= fifo_monit_pos_out(c_dsp_pos_num_bits-1 downto 0);
pos_monit_valid_fs_sync <= fifo_monit_pos_valid_out;
pos_sum_monit_o <= sum_monit_fs_sync;
pos_q_monit_o <= q_monit_fs_sync;
pos_y_monit_o <= y_monit_fs_sync;
pos_x_monit_o <= x_monit_fs_sync;
pos_monit_valid_o <= pos_monit_valid_fs_sync;
--------------------------------------------------------------------------
-- Monitoring 1 Hz data --
--------------------------------------------------------------------------
-- Monitoring 1 Hz position data
cmp_position_calc_cdc_fifo_monit_1_pos : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_pos_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_monit_1_pos_in,
valid_i => fifo_monit_1_pos_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_monit_1_pos_out,
valid_o => fifo_monit_1_pos_valid_out
);
p_reg_cdc_fifo_monit_1_pos_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_monit_1_pos_in <= (others => '0');
fifo_monit_1_pos_valid_in <= '0';
elsif clk_ce_222400000 = '1' then
fifo_monit_1_pos_in <= sum_monit_1 & -- 4*c_dsp_pos_num_bits-1 downto 3*c_dsp_pos_num_bits
q_monit_1 & -- 3*c_dsp_pos_num_bits-1 downto 2*c_dsp_pos_num_bits
y_monit_1 & -- 2*c_dsp_pos_num_bits-1 downto c_dsp_pos_num_bits
x_monit_1; -- c_dsp_pos_num_bits-1 downto 0
fifo_monit_1_pos_valid_in <= x_monit_1_valid;
else
fifo_monit_1_pos_valid_in <= '0';
end if;
end if;
end process;
sum_monit_1_fs_sync <= fifo_monit_1_pos_out(4*c_dsp_pos_num_bits-1 downto 3*c_dsp_pos_num_bits);
q_monit_1_fs_sync <= fifo_monit_1_pos_out(3*c_dsp_pos_num_bits-1 downto 2*c_dsp_pos_num_bits);
y_monit_1_fs_sync <= fifo_monit_1_pos_out(2*c_dsp_pos_num_bits-1 downto c_dsp_pos_num_bits);
x_monit_1_fs_sync <= fifo_monit_1_pos_out(c_dsp_pos_num_bits-1 downto 0);
pos_monit_1_valid_fs_sync <= fifo_monit_1_pos_valid_out;
pos_sum_monit_1_o <= sum_monit_1_fs_sync;
pos_q_monit_1_o <= q_monit_1_fs_sync;
pos_y_monit_1_o <= y_monit_1_fs_sync;
pos_x_monit_1_o <= x_monit_1_fs_sync;
pos_monit_1_valid_o <= pos_monit_1_valid_fs_sync;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_183 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_183;
architecture augh of add_183 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_183 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_183;
architecture augh of add_183 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
-- NEED RESULT: ARCH00153.P1: Multi inertial transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00153.P2: Multi inertial transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00153.P3: Multi inertial transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00153: One inertial transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00153: One inertial transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00153: One inertial transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00153
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00153(ARCH00153)
-- ENT00153_Test_Bench(ARCH00153_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00153 is
port (
s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
end ENT00153 ;
--
architecture ARCH00153 of ENT00153 is
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns,
c_st_rec1_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00153.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1.f2 <= c_st_rec1_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00153" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <= transport
c_st_rec1_1.f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00153" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00153" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <= -- Last transaction above is marked
c_st_rec1_1.f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00153" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00153" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_rec1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns,
c_st_rec2_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00153.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2.f2 <= c_st_rec2_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00153" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <= transport
c_st_rec2_1.f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00153" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00153" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <= -- Last transaction above is marked
c_st_rec2_1.f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00153" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00153" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_rec2'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns,
c_st_rec3_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00153.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f2 <= c_st_rec3_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00153" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <= transport
c_st_rec3_1.f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00153" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00153" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <= -- Last transaction above is marked
c_st_rec3_1.f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00153" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00153" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
wait until (not s_st_rec3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
--
end ARCH00153 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00153_Test_Bench is
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00153_Test_Bench ;
--
architecture ARCH00153_Test_Bench of ENT00153_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec1 : inout st_rec1
; s_st_rec2 : inout st_rec2
; s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00153 ( ARCH00153 ) ;
begin
CIS1 : UUT
port map (
s_st_rec1
, s_st_rec2
, s_st_rec3
) ;
end block L1 ;
end ARCH00153_Test_Bench ;
|
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Simple Wishbone UART
---------------------------------------------------------------------------------------
-- File : simple_uart_pkg.vhd
-- Author : auto-generated by wbgen2 from simple_uart_wb.wb
-- Created : Thu Feb 14 10:36:11 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package uart_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_uart_in_registers is record
sr_tx_busy_i : std_logic;
sr_rx_rdy_i : std_logic;
rdr_rx_data_i : std_logic_vector(7 downto 0);
host_tdr_rdy_i : std_logic;
host_rdr_data_i : std_logic_vector(7 downto 0);
host_rdr_rdy_i : std_logic;
host_rdr_count_i : std_logic_vector(15 downto 0);
end record;
constant c_uart_in_registers_init_value: t_uart_in_registers := (
sr_tx_busy_i => '0',
sr_rx_rdy_i => '0',
rdr_rx_data_i => (others => '0'),
host_tdr_rdy_i => '0',
host_rdr_data_i => (others => '0'),
host_rdr_rdy_i => '0',
host_rdr_count_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_uart_out_registers is record
bcr_o : std_logic_vector(31 downto 0);
bcr_wr_o : std_logic;
tdr_tx_data_o : std_logic_vector(7 downto 0);
tdr_tx_data_wr_o : std_logic;
host_tdr_data_o : std_logic_vector(7 downto 0);
host_tdr_data_wr_o : std_logic;
end record;
constant c_uart_out_registers_init_value: t_uart_out_registers := (
bcr_o => (others => '0'),
bcr_wr_o => '0',
tdr_tx_data_o => (others => '0'),
tdr_tx_data_wr_o => '0',
host_tdr_data_o => (others => '0'),
host_tdr_data_wr_o => '0'
);
function "or" (left, right: t_uart_in_registers) return t_uart_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body uart_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
else
return x;
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_uart_in_registers) return t_uart_in_registers is
variable tmp: t_uart_in_registers;
begin
tmp.sr_tx_busy_i := f_x_to_zero(left.sr_tx_busy_i) or f_x_to_zero(right.sr_tx_busy_i);
tmp.sr_rx_rdy_i := f_x_to_zero(left.sr_rx_rdy_i) or f_x_to_zero(right.sr_rx_rdy_i);
tmp.rdr_rx_data_i := f_x_to_zero(left.rdr_rx_data_i) or f_x_to_zero(right.rdr_rx_data_i);
tmp.host_tdr_rdy_i := f_x_to_zero(left.host_tdr_rdy_i) or f_x_to_zero(right.host_tdr_rdy_i);
tmp.host_rdr_data_i := f_x_to_zero(left.host_rdr_data_i) or f_x_to_zero(right.host_rdr_data_i);
tmp.host_rdr_rdy_i := f_x_to_zero(left.host_rdr_rdy_i) or f_x_to_zero(right.host_rdr_rdy_i);
tmp.host_rdr_count_i := f_x_to_zero(left.host_rdr_count_i) or f_x_to_zero(right.host_rdr_count_i);
return tmp;
end function;
end package body;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: can_oc
-- File: can_oc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB interface for the OpenCores CAN MAC
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.can.all;
entity can_rd is
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
syncrst : integer := 0;
dmap : integer := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(1 downto 0);
can_txo : out std_logic_vector(1 downto 0)
);
end;
architecture rtl of can_rd is
constant ncores : integer := 1;
constant sepirq : integer := 0;
constant REVISION : amba_version_type := ncores-1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_CANAHB, 0, REVISION, irq),
4 => ahb_iobar(ioaddr, iomask), others => zero32);
type ahbregs is record
hsel : std_ulogic;
hwrite : std_ulogic;
hwrite2 : std_ulogic;
htrans : std_logic_vector(1 downto 0);
haddr : std_logic_vector(10 downto 0);
hwdata : std_logic_vector(7 downto 0);
herr : std_ulogic;
hready : std_ulogic;
ws : std_logic_vector(1 downto 0);
irqi : std_logic_vector(ncores-1 downto 0);
irqo : std_logic_vector(ncores-1 downto 0);
muxsel : std_logic;
writemux : std_logic;
end record;
subtype cdata is std_logic_vector(7 downto 0);
type cdataarr is array (0 to 7) of cdata;
signal data_out : cdataarr;
signal reset : std_logic;
signal irqo : std_logic_vector(ncores-1 downto 0);
signal addr : std_logic_vector(7 downto 0);
signal vcc, gnd : std_ulogic;
signal r, rin : ahbregs;
signal can_lrxi, can_ltxo : std_logic;
begin
gnd <= '0'; vcc <= '1'; reset <= not resetn;
comb : process(ahbsi, r, resetn, data_out, irqo)
variable v : ahbregs;
variable hresp : std_logic_vector(1 downto 0);
variable dataout : std_logic_vector(7 downto 0);
variable irqvec : std_logic_vector(NAHBIRQ-1 downto 0);
variable vmuxreg : std_logic;
variable hwdata : std_logic_vector(31 downto 0);
begin
v := r;
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
if (r.hsel = '1' ) and (r.ws /= "11") then v.ws := r.ws + 1; end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(slvndx);
v.haddr := ahbsi.haddr(10 downto 0);
v.htrans := ahbsi.htrans;
v.hwrite := ahbsi.hwrite;
v.herr := orv(ahbsi.hsize) and ahbsi.hwrite;
v.ws := "00";
end if;
v.hready := (r.hsel and r.ws(1) and not r.ws(0)) or not resetn
or (ahbsi.hready and not ahbsi.htrans(1));
vmuxreg := not r.haddr(7) and r.haddr(6);
--v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
-- and not r.ws(0) and not r.herr;
v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and not r.herr and not vmuxreg;
v.writemux := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and vmuxreg;
if (r.herr and r.ws(1)) = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
case r.haddr(1 downto 0) is
when "00" => v.hwdata := hwdata(31 downto 24);
when "01" => v.hwdata := hwdata(23 downto 16);
when "10" => v.hwdata := hwdata(15 downto 8);
when others => v.hwdata := hwdata(7 downto 0);
end case;
--dataout := data_out(0);
if r.haddr(7 downto 6) = "01" then
dataout := (others => r.muxsel);
if r.writemux = '1' then
v.muxsel := r.hwdata(0);
end if;
else
dataout := data_out(0);
end if;
-- Interrupt goes to low when appeard and is normal high
-- but the irq controller from leon is active high and the interrupt should appear only
-- for 1 Clk cycle,
v.irqi := irqo; v.irqo:= (r.irqi and not irqo);
irqvec := (others => '0');
if sepirq = 1 then irqvec(ncores-1+irq downto irq) := r.irqo;
else irqvec(irq) := orv(r.irqo); end if;
ahbso.hirq <= irqvec;
ahbso.hrdata <= ahbdrivedata(dataout);
ahbso.hresp <= hresp; rin <= v;
end process;
-- Double mapping of registers [byte (offset 0), word (offset 0x80)]
dmap0 : if dmap = 0 generate
addr <= r.haddr(7 downto 0);
end generate;
dmap1 : if dmap = 1 generate
addr <= "000"&r.haddr(6 downto 2) when r.haddr(7) = '1' else
r.haddr(7 downto 0);
end generate;
reg : process(clk)
begin if clk'event and clk = '1' then r <= rin; end if; end process;
cmod : can_mod generic map (memtech, syncrst)
--port map (reset, clk, r.hsel, r.hwrite2, r.haddr(7 downto 0), r.hwdata,
port map (reset, clk, r.hsel, r.hwrite2, addr, r.hwdata,
data_out(0), irqo(0), can_lrxi, can_ltxo, ahbsi.testen);
cmux : canmux port map (r.muxsel, can_lrxi, can_ltxo, can_rxi, can_txo);
ahbso.hconfig <= hconfig;
ahbso.hindex <= slvndx;
ahbso.hsplit <= (others => '0');
ahbso.hready <= r.hready;
-- pragma translate_off
bootmsg : report_version
generic map (
"can_oc" & tost(slvndx) &
": SJA1000 Compatible CAN MAC, revision " & tost(REVISION) &
", irq " & tost(irq));
-- pragma translate_on
end;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_ethernetlite:3.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_ethernetlite_v3_0;
USE axi_ethernetlite_v3_0.axi_ethernetlite;
ENTITY design_1_axi_ethernetlite_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
phy_tx_clk : IN STD_LOGIC;
phy_rx_clk : IN STD_LOGIC;
phy_crs : IN STD_LOGIC;
phy_dv : IN STD_LOGIC;
phy_rx_data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_col : IN STD_LOGIC;
phy_rx_er : IN STD_LOGIC;
phy_rst_n : OUT STD_LOGIC;
phy_tx_en : OUT STD_LOGIC;
phy_tx_data : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_mdio_i : IN STD_LOGIC;
phy_mdio_o : OUT STD_LOGIC;
phy_mdio_t : OUT STD_LOGIC;
phy_mdc : OUT STD_LOGIC
);
END design_1_axi_ethernetlite_0_0;
ARCHITECTURE design_1_axi_ethernetlite_0_0_arch OF design_1_axi_ethernetlite_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_ethernetlite_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_ethernetlite IS
GENERIC (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_ACLK_PERIOD_PS : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_INCLUDE_MDIO : INTEGER;
C_INCLUDE_INTERNAL_LOOPBACK : INTEGER;
C_INCLUDE_GLOBAL_BUFFERS : INTEGER;
C_DUPLEX : INTEGER;
C_TX_PING_PONG : INTEGER;
C_RX_PING_PONG : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
phy_tx_clk : IN STD_LOGIC;
phy_rx_clk : IN STD_LOGIC;
phy_crs : IN STD_LOGIC;
phy_dv : IN STD_LOGIC;
phy_rx_data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_col : IN STD_LOGIC;
phy_rx_er : IN STD_LOGIC;
phy_rst_n : OUT STD_LOGIC;
phy_tx_en : OUT STD_LOGIC;
phy_tx_data : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_mdio_i : IN STD_LOGIC;
phy_mdio_o : OUT STD_LOGIC;
phy_mdio_t : OUT STD_LOGIC;
phy_mdc : OUT STD_LOGIC
);
END COMPONENT axi_ethernetlite;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_ethernetlite_0_0_arch: ARCHITECTURE IS "axi_ethernetlite,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_ethernetlite_0_0_arch : ARCHITECTURE IS "design_1_axi_ethernetlite_0_0,axi_ethernetlite,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_ethernetlite_0_0_arch: ARCHITECTURE IS "design_1_axi_ethernetlite_0_0,axi_ethernetlite,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_ethernetlite,x_ipVersion=3.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_INSTANCE=axi_ethernetlite_inst,C_S_AXI_ACLK_PERIOD_PS=10000,C_S_AXI_ADDR_WIDTH=13,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=1,C_S_AXI_PROTOCOL=AXI4LITE,C_INCLUDE_MDIO=1,C_INCLUDE_INTERNAL_LOOPBACK=0,C_INCLUDE_GLOBAL_BUFFERS=1,C_DUPLEX=1,C_TX_PING_PONG=1,C_RX_PING_PONG=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF phy_tx_clk: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TX_CLK";
ATTRIBUTE X_INTERFACE_INFO OF phy_rx_clk: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_CLK";
ATTRIBUTE X_INTERFACE_INFO OF phy_crs: SIGNAL IS "xilinx.com:interface:mii:1.0 MII CRS";
ATTRIBUTE X_INTERFACE_INFO OF phy_dv: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_DV";
ATTRIBUTE X_INTERFACE_INFO OF phy_rx_data: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RXD";
ATTRIBUTE X_INTERFACE_INFO OF phy_col: SIGNAL IS "xilinx.com:interface:mii:1.0 MII COL";
ATTRIBUTE X_INTERFACE_INFO OF phy_rx_er: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_ER";
ATTRIBUTE X_INTERFACE_INFO OF phy_rst_n: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RST_N";
ATTRIBUTE X_INTERFACE_INFO OF phy_tx_en: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TX_EN";
ATTRIBUTE X_INTERFACE_INFO OF phy_tx_data: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TXD";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdio_i: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDIO_I";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdio_o: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDIO_O";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdio_t: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDIO_T";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdc: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDC";
BEGIN
U0 : axi_ethernetlite
GENERIC MAP (
C_FAMILY => "artix7",
C_INSTANCE => "axi_ethernetlite_inst",
C_S_AXI_ACLK_PERIOD_PS => 10000,
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 1,
C_S_AXI_PROTOCOL => "AXI4LITE",
C_INCLUDE_MDIO => 1,
C_INCLUDE_INTERNAL_LOOPBACK => 0,
C_INCLUDE_GLOBAL_BUFFERS => 1,
C_DUPLEX => 1,
C_TX_PING_PONG => 1,
C_RX_PING_PONG => 1
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
ip2intc_irpt => ip2intc_irpt,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => '1',
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => s_axi_araddr,
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
phy_tx_clk => phy_tx_clk,
phy_rx_clk => phy_rx_clk,
phy_crs => phy_crs,
phy_dv => phy_dv,
phy_rx_data => phy_rx_data,
phy_col => phy_col,
phy_rx_er => phy_rx_er,
phy_rst_n => phy_rst_n,
phy_tx_en => phy_tx_en,
phy_tx_data => phy_tx_data,
phy_mdio_i => phy_mdio_i,
phy_mdio_o => phy_mdio_o,
phy_mdio_t => phy_mdio_t,
phy_mdc => phy_mdc
);
END design_1_axi_ethernetlite_0_0_arch;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_ethernetlite:3.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_ethernetlite_v3_0;
USE axi_ethernetlite_v3_0.axi_ethernetlite;
ENTITY design_1_axi_ethernetlite_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
phy_tx_clk : IN STD_LOGIC;
phy_rx_clk : IN STD_LOGIC;
phy_crs : IN STD_LOGIC;
phy_dv : IN STD_LOGIC;
phy_rx_data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_col : IN STD_LOGIC;
phy_rx_er : IN STD_LOGIC;
phy_rst_n : OUT STD_LOGIC;
phy_tx_en : OUT STD_LOGIC;
phy_tx_data : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_mdio_i : IN STD_LOGIC;
phy_mdio_o : OUT STD_LOGIC;
phy_mdio_t : OUT STD_LOGIC;
phy_mdc : OUT STD_LOGIC
);
END design_1_axi_ethernetlite_0_0;
ARCHITECTURE design_1_axi_ethernetlite_0_0_arch OF design_1_axi_ethernetlite_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_ethernetlite_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_ethernetlite IS
GENERIC (
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_ACLK_PERIOD_PS : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_INCLUDE_MDIO : INTEGER;
C_INCLUDE_INTERNAL_LOOPBACK : INTEGER;
C_INCLUDE_GLOBAL_BUFFERS : INTEGER;
C_DUPLEX : INTEGER;
C_TX_PING_PONG : INTEGER;
C_RX_PING_PONG : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
phy_tx_clk : IN STD_LOGIC;
phy_rx_clk : IN STD_LOGIC;
phy_crs : IN STD_LOGIC;
phy_dv : IN STD_LOGIC;
phy_rx_data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_col : IN STD_LOGIC;
phy_rx_er : IN STD_LOGIC;
phy_rst_n : OUT STD_LOGIC;
phy_tx_en : OUT STD_LOGIC;
phy_tx_data : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phy_mdio_i : IN STD_LOGIC;
phy_mdio_o : OUT STD_LOGIC;
phy_mdio_t : OUT STD_LOGIC;
phy_mdc : OUT STD_LOGIC
);
END COMPONENT axi_ethernetlite;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_ethernetlite_0_0_arch: ARCHITECTURE IS "axi_ethernetlite,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_ethernetlite_0_0_arch : ARCHITECTURE IS "design_1_axi_ethernetlite_0_0,axi_ethernetlite,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_ethernetlite_0_0_arch: ARCHITECTURE IS "design_1_axi_ethernetlite_0_0,axi_ethernetlite,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_ethernetlite,x_ipVersion=3.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_INSTANCE=axi_ethernetlite_inst,C_S_AXI_ACLK_PERIOD_PS=10000,C_S_AXI_ADDR_WIDTH=13,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=1,C_S_AXI_PROTOCOL=AXI4LITE,C_INCLUDE_MDIO=1,C_INCLUDE_INTERNAL_LOOPBACK=0,C_INCLUDE_GLOBAL_BUFFERS=1,C_DUPLEX=1,C_TX_PING_PONG=1,C_RX_PING_PONG=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF phy_tx_clk: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TX_CLK";
ATTRIBUTE X_INTERFACE_INFO OF phy_rx_clk: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_CLK";
ATTRIBUTE X_INTERFACE_INFO OF phy_crs: SIGNAL IS "xilinx.com:interface:mii:1.0 MII CRS";
ATTRIBUTE X_INTERFACE_INFO OF phy_dv: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_DV";
ATTRIBUTE X_INTERFACE_INFO OF phy_rx_data: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RXD";
ATTRIBUTE X_INTERFACE_INFO OF phy_col: SIGNAL IS "xilinx.com:interface:mii:1.0 MII COL";
ATTRIBUTE X_INTERFACE_INFO OF phy_rx_er: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RX_ER";
ATTRIBUTE X_INTERFACE_INFO OF phy_rst_n: SIGNAL IS "xilinx.com:interface:mii:1.0 MII RST_N";
ATTRIBUTE X_INTERFACE_INFO OF phy_tx_en: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TX_EN";
ATTRIBUTE X_INTERFACE_INFO OF phy_tx_data: SIGNAL IS "xilinx.com:interface:mii:1.0 MII TXD";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdio_i: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDIO_I";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdio_o: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDIO_O";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdio_t: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDIO_T";
ATTRIBUTE X_INTERFACE_INFO OF phy_mdc: SIGNAL IS "xilinx.com:interface:mdio:1.0 MDIO MDC";
BEGIN
U0 : axi_ethernetlite
GENERIC MAP (
C_FAMILY => "artix7",
C_INSTANCE => "axi_ethernetlite_inst",
C_S_AXI_ACLK_PERIOD_PS => 10000,
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 1,
C_S_AXI_PROTOCOL => "AXI4LITE",
C_INCLUDE_MDIO => 1,
C_INCLUDE_INTERNAL_LOOPBACK => 0,
C_INCLUDE_GLOBAL_BUFFERS => 1,
C_DUPLEX => 1,
C_TX_PING_PONG => 1,
C_RX_PING_PONG => 1
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
ip2intc_irpt => ip2intc_irpt,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => '1',
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => s_axi_araddr,
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
phy_tx_clk => phy_tx_clk,
phy_rx_clk => phy_rx_clk,
phy_crs => phy_crs,
phy_dv => phy_dv,
phy_rx_data => phy_rx_data,
phy_col => phy_col,
phy_rx_er => phy_rx_er,
phy_rst_n => phy_rst_n,
phy_tx_en => phy_tx_en,
phy_tx_data => phy_tx_data,
phy_mdio_i => phy_mdio_i,
phy_mdio_o => phy_mdio_o,
phy_mdio_t => phy_mdio_t,
phy_mdc => phy_mdc
);
END design_1_axi_ethernetlite_0_0_arch;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY spi_async IS
PORT ( SCLK : IN std_logic;
RESET : IN std_logic;
SDATA : IN std_logic;
CS : IN std_logic;
BYTE0, BYTE1 : OUT std_logic_vector(7 downto 0);
dig0, dig1, dig2, dig3 : OUT std_logic_vector(6 DOWNTO 0) -- show key pressed on display dig2 en dig3 (resp high & low).
);
END spi_async;
ARCHITECTURE behav of spi_async is
FUNCTION hex2display (n:std_logic_vector(3 DOWNTO 0)) RETURN std_logic_vector IS
VARIABLE res : std_logic_vector(6 DOWNTO 0);
BEGIN
CASE n IS -- gfedcba; low active
WHEN "0000" => RETURN NOT "0111111";
WHEN "0001" => RETURN NOT "0000110";
WHEN "0010" => RETURN NOT "1011011";
WHEN "0011" => RETURN NOT "1001111";
WHEN "0100" => RETURN NOT "1100110";
WHEN "0101" => RETURN NOT "1101101";
WHEN "0110" => RETURN NOT "1111101";
WHEN "0111" => RETURN NOT "0000111";
WHEN "1000" => RETURN NOT "1111111";
WHEN "1001" => RETURN NOT "1101111";
WHEN "1010" => RETURN NOT "1110111";
WHEN "1011" => RETURN NOT "1111100";
WHEN "1100" => RETURN NOT "0111001";
WHEN "1101" => RETURN NOT "1011110";
WHEN "1110" => RETURN NOT "1111001";
WHEN OTHERS => RETURN NOT "1110001";
END CASE;
END hex2display;
signal SDATA_register : std_logic_vector(15 downto 0);
BEGIN
PROCESS(RESET, SCLK, CS)
variable byte0_reg, byte1_reg : std_logic_vector(7 downto 0);
BEGIN
if reset = '0' then
SDATA_register <= (others => '0');
BYTE0 <= (others => '0');
BYTE1 <= (others => '0');
byte0_reg := (others => '0');
byte1_reg := (others => '0');
dig0 <= hex2display("0000");
dig1 <= hex2display("0000");
dig2 <= hex2display("0000");
dig3 <= hex2display("0000");
elsif CS = '1' then
byte0_reg := SDATA_register(15 downto 8);
dig0 <= hex2display(byte0_reg(3 downto 0));
dig1 <= hex2display(byte0_reg(7 downto 4));
BYTE0 <= byte0_reg;
byte1_reg := SDATA_register(7 downto 0);
dig2 <= hex2display(byte1_reg(3 downto 0));
dig3 <= hex2display(byte1_reg(7 downto 4));
BYTE1 <= byte1_reg;
elsif rising_edge(SCLK) then
if CS = '0' then --Only get SDATA when slave is selected (Active low)
SDATA_register <= SDATA_register(14 downto 0) & SDATA; --Shift register 16 bytes
end if;
end if;
END PROCESS;
END behav; |
-------------------------------------------------------------------------------
-- Entity : plb_powerlink
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This is the toplevel file for using the POWERLINK IP-Core
-- with Xilinx PLB V4.6.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
use work.global.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
-- standard libraries declarations
library UNISIM;
use UNISIM.vcomponents.all;
-- pragma synthesis_off
library IEEE;
use IEEE.vital_timing.all;
-- pragma synthesis_on
-- other libraries declarations
library PLBV46_MASTER_BURST_V1_01_A;
library PLBV46_SLAVE_SINGLE_V1_01_A;
entity plb_powerlink is
generic(
C_FAMILY : string := "spartan6";
-- general
C_GEN_PDI : boolean := false;
C_GEN_PAR_IF : boolean := false;
C_GEN_SPI_IF : boolean := false;
C_GEN_PLB_BUS_IF : boolean := false;
C_GEN_SIMPLE_IO : boolean := false;
-- openMAC
C_MAC_PKT_SIZE : integer := 1024;
C_MAC_PKT_SIZE_LOG2 : integer := 10;
C_MAC_RX_BUFFERS : integer := 16;
C_USE_RMII : boolean := false;
C_TX_INT_PKT : boolean := false;
C_RX_INT_PKT : boolean := false;
C_USE_2ND_PHY : boolean := true;
C_NUM_SMI : integer range 1 to 2 := 2;
C_MAC_GEN_SECOND_TIMER : boolean := false;
--pdi
C_PDI_REV : integer := 0;
C_PCP_SYS_ID : integer := 0;
C_PDI_GEN_ASYNC_BUF_0 : boolean := true;
C_PDI_ASYNC_BUF_0 : integer := 50;
C_PDI_GEN_ASYNC_BUF_1 : boolean := true;
C_PDI_ASYNC_BUF_1 : integer := 50;
C_PDI_GEN_LED : boolean := false;
C_PDI_GEN_TIME_SYNC : boolean := true;
C_PDI_GEN_EVENT : boolean := true;
--global pdi and mac
C_NUM_RPDO : integer := 3;
C_RPDO_0_BUF_SIZE : integer := 100;
C_RPDO_1_BUF_SIZE : integer := 100;
C_RPDO_2_BUF_SIZE : integer := 100;
C_NUM_TPDO : integer := 1;
C_TPDO_BUF_SIZE : integer := 100;
-- pap
C_PAP_DATA_WIDTH : integer := 16;
--C_PAP_BIG_END : boolean := false;
C_PAP_LOW_ACT : boolean := false;
-- spi
C_SPI_CPOL : boolean := false;
C_SPI_CPHA : boolean := false;
--C_SPI_BIG_END : boolean := false;
-- simpleIO
C_PIO_VAL_LENGTH : integer := 50;
-- debug
C_OBSERVER_ENABLE : boolean := false;
-- clock stabiliser
C_INSTANCE_ODDR2 : boolean := false;
-- sync IRQ pulse width
C_USE_PULSE_2nd_CMP_TIMER : boolean := true;
C_PULSE_WIDTH_2nd_CMP_TIMER : integer := 9;
-- PDI AP PLB Slave
C_PDI_AP_BASEADDR : std_logic_vector := X"00000000";
C_PDI_AP_HIGHADDR : std_logic_vector := X"000FFFFF";
C_PDI_AP_NUM_MASTERS : INTEGER := 1;
C_PDI_AP_PLB_AWIDTH : INTEGER := 32;
C_PDI_AP_PLB_DWIDTH : INTEGER := 32;
C_PDI_AP_PLB_MID_WIDTH : INTEGER := 1;
C_PDI_AP_PLB_P2P : INTEGER := 0;
C_PDI_AP_PLB_NUM_MASTERS : INTEGER := 1;
C_PDI_AP_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_PDI_AP_PLB_SUPPORT_BURSTS : INTEGER := 0;
-- PDI AP PLB Slave
C_SMP_PCP_BASEADDR : std_logic_vector := X"00000000";
C_SMP_PCP_HIGHADDR : std_logic_vector := X"000FFFFF";
C_SMP_PCP_NUM_MASTERS : INTEGER := 1;
C_SMP_PCP_PLB_AWIDTH : INTEGER := 32;
C_SMP_PCP_PLB_DWIDTH : INTEGER := 32;
C_SMP_PCP_PLB_MID_WIDTH : INTEGER := 1;
C_SMP_PCP_PLB_P2P : INTEGER := 0;
C_SMP_PCP_PLB_NUM_MASTERS : INTEGER := 1;
C_SMP_PCP_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_SMP_PCP_PLB_SUPPORT_BURSTS : INTEGER := 0;
-- PDI PCP PLB Slave
C_PDI_PCP_BASEADDR : std_logic_vector := X"00000000";
C_PDI_PCP_HIGHADDR : std_logic_vector := X"000FFFFF";
C_PDI_PCP_NUM_MASTERS : INTEGER := 1;
C_PDI_PCP_PLB_AWIDTH : INTEGER := 32;
C_PDI_PCP_PLB_DWIDTH : INTEGER := 32;
C_PDI_PCP_PLB_MID_WIDTH : INTEGER := 1;
C_PDI_PCP_PLB_P2P : INTEGER := 0;
C_PDI_PCP_PLB_NUM_MASTERS : INTEGER := 1;
C_PDI_PCP_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_PDI_PCP_PLB_SUPPORT_BURSTS : INTEGER := 0;
-- openMAC CMP PLB Slave
C_MAC_PKT_BASEADDR : std_logic_vector := X"00000000";
C_MAC_PKT_HIGHADDR : std_logic_vector := X"000FFFFF";
C_MAC_PKT_NUM_MASTERS : INTEGER := 1;
C_MAC_PKT_PLB_AWIDTH : INTEGER := 32;
C_MAC_PKT_PLB_DWIDTH : INTEGER := 32;
C_MAC_PKT_PLB_MID_WIDTH : INTEGER := 1;
C_MAC_PKT_PLB_P2P : INTEGER := 0;
C_MAC_PKT_PLB_NUM_MASTERS : INTEGER := 1;
C_MAC_PKT_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_MAC_PKT_PLB_SUPPORT_BURSTS : INTEGER := 0;
-- openMAC DMA PLB Master
C_MAC_DMA_PLB_AWIDTH : INTEGER := 32;
C_MAC_DMA_PLB_DWIDTH : INTEGER := 32;
C_MAC_DMA_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_MAC_DMA_BURST_SIZE_RX : INTEGER := 8; --in bytes
C_MAC_DMA_BURST_SIZE_TX : INTEGER := 8; --in bytes
C_MAC_DMA_FIFO_SIZE_RX : INTEGER := 32; --in bytes
C_MAC_DMA_FIFO_SIZE_TX : INTEGER := 32; --in bytes
-- openMAC REG PLB Slave
C_MAC_REG_BASEADDR : std_logic_vector := X"00000000";
C_MAC_REG_HIGHADDR : std_logic_vector := X"0000FFFF";
C_MAC_CMP_BASEADDR : std_logic_vector := X"00000000";
C_MAC_CMP_HIGHADDR : std_logic_vector := X"0000FFFF";
C_MAC_REG_BUS2CORE_CLK_RATIO : integer := 2;
C_MAC_REG_NUM_MASTERS : INTEGER := 1;
C_MAC_REG_PLB_AWIDTH : INTEGER := 32;
C_MAC_REG_PLB_DWIDTH : INTEGER := 32;
C_MAC_REG_PLB_MID_WIDTH : INTEGER := 1;
C_MAC_REG_PLB_P2P : INTEGER := 0;
C_MAC_REG_PLB_NUM_MASTERS : INTEGER := 1;
C_MAC_REG_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_MAC_REG_PLB_SUPPORT_BURSTS : INTEGER := 0
);
port(
MAC_DMA_Clk : in std_logic;
MAC_DMA_MAddrAck : in std_logic;
MAC_DMA_MBusy : in std_logic;
MAC_DMA_MIRQ : in std_logic;
MAC_DMA_MRdBTerm : in std_logic;
MAC_DMA_MRdDAck : in std_logic;
MAC_DMA_MRdErr : in std_logic;
MAC_DMA_MRearbitrate : in std_logic;
MAC_DMA_MTimeout : in std_logic;
MAC_DMA_MWrBTerm : in std_logic;
MAC_DMA_MWrDAck : in std_logic;
MAC_DMA_MWrErr : in std_logic;
MAC_DMA_Rst : in std_logic;
MAC_PKT_Clk : in std_logic;
MAC_PKT_PAValid : in std_logic;
MAC_PKT_RNW : in std_logic;
MAC_PKT_Rst : in std_logic;
MAC_PKT_SAValid : in std_logic;
MAC_PKT_abort : in std_logic;
MAC_PKT_busLock : in std_logic;
MAC_PKT_lockErr : in std_logic;
MAC_PKT_rdBurst : in std_logic;
MAC_PKT_rdPendReq : in std_logic;
MAC_PKT_rdPrim : in std_logic;
MAC_PKT_wrBurst : in std_logic;
MAC_PKT_wrPendReq : in std_logic;
MAC_PKT_wrPrim : in std_logic;
MAC_REG_Clk : in std_logic;
MAC_REG_PAValid : in std_logic;
MAC_REG_RNW : in std_logic;
MAC_REG_Rst : in std_logic;
MAC_REG_SAValid : in std_logic;
MAC_REG_abort : in std_logic;
MAC_REG_busLock : in std_logic;
MAC_REG_lockErr : in std_logic;
MAC_REG_rdBurst : in std_logic;
MAC_REG_rdPendReq : in std_logic;
MAC_REG_rdPrim : in std_logic;
MAC_REG_wrBurst : in std_logic;
MAC_REG_wrPendReq : in std_logic;
MAC_REG_wrPrim : in std_logic;
PDI_AP_Clk : in std_logic;
PDI_AP_PAValid : in std_logic;
PDI_AP_RNW : in std_logic;
PDI_AP_Rst : in std_logic;
PDI_AP_SAValid : in std_logic;
PDI_AP_abort : in std_logic;
PDI_AP_busLock : in std_logic;
PDI_AP_lockErr : in std_logic;
PDI_AP_rdBurst : in std_logic;
PDI_AP_rdPendReq : in std_logic;
PDI_AP_rdPrim : in std_logic;
PDI_AP_wrBurst : in std_logic;
PDI_AP_wrPendReq : in std_logic;
PDI_AP_wrPrim : in std_logic;
PDI_PCP_Clk : in std_logic;
PDI_PCP_PAValid : in std_logic;
PDI_PCP_RNW : in std_logic;
PDI_PCP_Rst : in std_logic;
PDI_PCP_SAValid : in std_logic;
PDI_PCP_abort : in std_logic;
PDI_PCP_busLock : in std_logic;
PDI_PCP_lockErr : in std_logic;
PDI_PCP_rdBurst : in std_logic;
PDI_PCP_rdPendReq : in std_logic;
PDI_PCP_rdPrim : in std_logic;
PDI_PCP_wrBurst : in std_logic;
PDI_PCP_wrPendReq : in std_logic;
PDI_PCP_wrPrim : in std_logic;
SMP_PCP_Clk : in std_logic;
SMP_PCP_PAValid : in std_logic;
SMP_PCP_RNW : in std_logic;
SMP_PCP_Rst : in std_logic;
SMP_PCP_SAValid : in std_logic;
SMP_PCP_abort : in std_logic;
SMP_PCP_busLock : in std_logic;
SMP_PCP_lockErr : in std_logic;
SMP_PCP_rdBurst : in std_logic;
SMP_PCP_rdPendReq : in std_logic;
SMP_PCP_rdPrim : in std_logic;
SMP_PCP_wrBurst : in std_logic;
SMP_PCP_wrPendReq : in std_logic;
SMP_PCP_wrPrim : in std_logic;
clk100 : in std_logic;
clk50 : in std_logic;
pap_cs : in std_logic;
pap_cs_n : in std_logic;
pap_rd : in std_logic;
pap_rd_n : in std_logic;
pap_wr : in std_logic;
pap_wr_n : in std_logic;
phy0_RxDv : in std_logic;
phy0_RxErr : in std_logic;
phy0_SMIDat_I : in std_logic;
phy0_link : in std_logic;
phy1_RxDv : in std_logic;
phy1_RxErr : in std_logic;
phy1_SMIDat_I : in std_logic;
phy1_link : in std_logic;
phyMii0_RxClk : in std_logic;
phyMii0_RxDv : in std_logic;
phyMii0_RxEr : in std_logic;
phyMii0_TxClk : in std_logic;
phyMii1_RxClk : in std_logic;
phyMii1_RxDv : in std_logic;
phyMii1_RxEr : in std_logic;
phyMii1_TxClk : in std_logic;
phy_SMIDat_I : in std_logic;
spi_clk : in std_logic;
spi_mosi : in std_logic;
spi_sel_n : in std_logic;
MAC_DMA_MRdDBus : in std_logic_vector(0 to C_MAC_DMA_PLB_DWIDTH-1);
MAC_DMA_MRdWdAddr : in std_logic_vector(0 to 3);
MAC_DMA_MSSize : in std_logic_vector(0 to 1);
MAC_PKT_ABus : in std_logic_vector(0 to 31);
MAC_PKT_BE : in std_logic_vector(0 to (C_MAC_PKT_PLB_DWIDTH/8)-1);
MAC_PKT_MSize : in std_logic_vector(0 to 1);
MAC_PKT_TAttribute : in std_logic_vector(0 to 15);
MAC_PKT_UABus : in std_logic_vector(0 to 31);
MAC_PKT_masterID : in std_logic_vector(0 to C_MAC_PKT_PLB_MID_WIDTH-1);
MAC_PKT_rdPendPri : in std_logic_vector(0 to 1);
MAC_PKT_reqPri : in std_logic_vector(0 to 1);
MAC_PKT_size : in std_logic_vector(0 to 3);
MAC_PKT_type : in std_logic_vector(0 to 2);
MAC_PKT_wrDBus : in std_logic_vector(0 to C_MAC_PKT_PLB_DWIDTH-1);
MAC_PKT_wrPendPri : in std_logic_vector(0 to 1);
MAC_REG_ABus : in std_logic_vector(0 to 31);
MAC_REG_BE : in std_logic_vector(0 to (C_MAC_REG_PLB_DWIDTH / 8) - 1);
MAC_REG_MSize : in std_logic_vector(0 to 1);
MAC_REG_TAttribute : in std_logic_vector(0 to 15);
MAC_REG_UABus : in std_logic_vector(0 to 31);
MAC_REG_masterID : in std_logic_vector(0 to C_MAC_REG_PLB_MID_WIDTH - 1);
MAC_REG_rdPendPri : in std_logic_vector(0 to 1);
MAC_REG_reqPri : in std_logic_vector(0 to 1);
MAC_REG_size : in std_logic_vector(0 to 3);
MAC_REG_type : in std_logic_vector(0 to 2);
MAC_REG_wrDBus : in std_logic_vector(0 to C_MAC_REG_PLB_DWIDTH - 1);
MAC_REG_wrPendPri : in std_logic_vector(0 to 1);
PDI_AP_ABus : in std_logic_vector(0 to 31);
PDI_AP_BE : in std_logic_vector(0 to (C_PDI_AP_PLB_DWIDTH/8)-1);
PDI_AP_MSize : in std_logic_vector(0 to 1);
PDI_AP_TAttribute : in std_logic_vector(0 to 15);
PDI_AP_UABus : in std_logic_vector(0 to 31);
PDI_AP_masterID : in std_logic_vector(0 to C_PDI_AP_PLB_MID_WIDTH-1);
PDI_AP_rdPendPri : in std_logic_vector(0 to 1);
PDI_AP_reqPri : in std_logic_vector(0 to 1);
PDI_AP_size : in std_logic_vector(0 to 3);
PDI_AP_type : in std_logic_vector(0 to 2);
PDI_AP_wrDBus : in std_logic_vector(0 to C_PDI_AP_PLB_DWIDTH-1);
PDI_AP_wrPendPri : in std_logic_vector(0 to 1);
PDI_PCP_ABus : in std_logic_vector(0 to 31);
PDI_PCP_BE : in std_logic_vector(0 to (C_PDI_PCP_PLB_DWIDTH/8)-1);
PDI_PCP_MSize : in std_logic_vector(0 to 1);
PDI_PCP_TAttribute : in std_logic_vector(0 to 15);
PDI_PCP_UABus : in std_logic_vector(0 to 31);
PDI_PCP_masterID : in std_logic_vector(0 to C_PDI_PCP_PLB_MID_WIDTH-1);
PDI_PCP_rdPendPri : in std_logic_vector(0 to 1);
PDI_PCP_reqPri : in std_logic_vector(0 to 1);
PDI_PCP_size : in std_logic_vector(0 to 3);
PDI_PCP_type : in std_logic_vector(0 to 2);
PDI_PCP_wrDBus : in std_logic_vector(0 to C_PDI_PCP_PLB_DWIDTH-1);
PDI_PCP_wrPendPri : in std_logic_vector(0 to 1);
SMP_PCP_ABus : in std_logic_vector(0 to 31);
SMP_PCP_BE : in std_logic_vector(0 to (C_SMP_PCP_PLB_DWIDTH/8)-1);
SMP_PCP_MSize : in std_logic_vector(0 to 1);
SMP_PCP_TAttribute : in std_logic_vector(0 to 15);
SMP_PCP_UABus : in std_logic_vector(0 to 31);
SMP_PCP_masterID : in std_logic_vector(0 to C_SMP_PCP_PLB_MID_WIDTH-1);
SMP_PCP_rdPendPri : in std_logic_vector(0 to 1);
SMP_PCP_reqPri : in std_logic_vector(0 to 1);
SMP_PCP_size : in std_logic_vector(0 to 3);
SMP_PCP_type : in std_logic_vector(0 to 2);
SMP_PCP_wrDBus : in std_logic_vector(0 to C_SMP_PCP_PLB_DWIDTH-1);
SMP_PCP_wrPendPri : in std_logic_vector(0 to 1);
pap_addr : in std_logic_vector(15 downto 0);
pap_be : in std_logic_vector(C_PAP_DATA_WIDTH/8-1 downto 0);
pap_be_n : in std_logic_vector(C_PAP_DATA_WIDTH/8-1 downto 0);
pap_data_I : in std_logic_vector(C_PAP_DATA_WIDTH-1 downto 0);
pap_gpio_I : in std_logic_vector(1 downto 0);
phy0_RxDat : in std_logic_vector(1 downto 0);
phy1_RxDat : in std_logic_vector(1 downto 0);
phyMii0_RxDat : in std_logic_vector(3 downto 0);
phyMii1_RxDat : in std_logic_vector(3 downto 0);
pio_pconfig : in std_logic_vector(3 downto 0);
pio_portInLatch : in std_logic_vector(3 downto 0);
pio_portio_I : in std_logic_vector(31 downto 0);
MAC_DMA_RNW : out std_logic;
MAC_DMA_abort : out std_logic;
MAC_DMA_busLock : out std_logic;
MAC_DMA_error : out std_logic;
MAC_DMA_lockErr : out std_logic;
MAC_DMA_rdBurst : out std_logic;
MAC_DMA_request : out std_logic;
MAC_DMA_wrBurst : out std_logic;
MAC_PKT_addrAck : out std_logic;
MAC_PKT_rdBTerm : out std_logic;
MAC_PKT_rdComp : out std_logic;
MAC_PKT_rdDAck : out std_logic;
MAC_PKT_rearbitrate : out std_logic;
MAC_PKT_wait : out std_logic;
MAC_PKT_wrBTerm : out std_logic;
MAC_PKT_wrComp : out std_logic;
MAC_PKT_wrDAck : out std_logic;
MAC_REG_addrAck : out std_logic;
MAC_REG_rdBTerm : out std_logic;
MAC_REG_rdComp : out std_logic;
MAC_REG_rdDAck : out std_logic;
MAC_REG_rearbitrate : out std_logic;
MAC_REG_wait : out std_logic;
MAC_REG_wrBTerm : out std_logic;
MAC_REG_wrComp : out std_logic;
MAC_REG_wrDAck : out std_logic;
PDI_AP_addrAck : out std_logic;
PDI_AP_rdBTerm : out std_logic;
PDI_AP_rdComp : out std_logic;
PDI_AP_rdDAck : out std_logic;
PDI_AP_rearbitrate : out std_logic;
PDI_AP_wait : out std_logic;
PDI_AP_wrBTerm : out std_logic;
PDI_AP_wrComp : out std_logic;
PDI_AP_wrDAck : out std_logic;
PDI_PCP_addrAck : out std_logic;
PDI_PCP_rdBTerm : out std_logic;
PDI_PCP_rdComp : out std_logic;
PDI_PCP_rdDAck : out std_logic;
PDI_PCP_rearbitrate : out std_logic;
PDI_PCP_wait : out std_logic;
PDI_PCP_wrBTerm : out std_logic;
PDI_PCP_wrComp : out std_logic;
PDI_PCP_wrDAck : out std_logic;
SMP_PCP_addrAck : out std_logic;
SMP_PCP_rdBTerm : out std_logic;
SMP_PCP_rdComp : out std_logic;
SMP_PCP_rdDAck : out std_logic;
SMP_PCP_rearbitrate : out std_logic;
SMP_PCP_wait : out std_logic;
SMP_PCP_wrBTerm : out std_logic;
SMP_PCP_wrComp : out std_logic;
SMP_PCP_wrDAck : out std_logic;
ap_asyncIrq : out std_logic;
ap_asyncIrq_n : out std_logic;
ap_syncIrq : out std_logic;
ap_syncIrq_n : out std_logic;
led_error : out std_logic;
led_status : out std_logic;
mac_irq : out std_logic;
pap_ack : out std_logic;
pap_ack_n : out std_logic;
pap_data_T : out std_logic;
phy0_Rst_n : out std_logic;
phy0_SMIClk : out std_logic;
phy0_SMIDat_O : out std_logic;
phy0_SMIDat_T : out std_logic;
phy0_TxEn : out std_logic;
phy0_clk : out std_logic;
phy1_Rst_n : out std_logic;
phy1_SMIClk : out std_logic;
phy1_SMIDat_O : out std_logic;
phy1_SMIDat_T : out std_logic;
phy1_TxEn : out std_logic;
phy1_clk : out std_logic;
phyMii0_TxEn : out std_logic;
phyMii0_TxEr : out std_logic;
phyMii1_TxEn : out std_logic;
phyMii1_TxEr : out std_logic;
phy_Rst_n : out std_logic;
phy_SMIClk : out std_logic;
phy_SMIDat_O : out std_logic;
phy_SMIDat_T : out std_logic;
pio_operational : out std_logic;
spi_miso : out std_logic;
tcp_irq : out std_logic;
MAC_DMA_ABus : out std_logic_vector(0 to 31);
MAC_DMA_BE : out std_logic_vector(0 to (C_MAC_DMA_PLB_DWIDTH/8)-1);
MAC_DMA_MSize : out std_logic_vector(0 to 1);
MAC_DMA_TAttribute : out std_logic_vector(0 to 15);
MAC_DMA_UABus : out std_logic_vector(0 to 31);
MAC_DMA_priority : out std_logic_vector(0 to 1);
MAC_DMA_size : out std_logic_vector(0 to 3);
MAC_DMA_type : out std_logic_vector(0 to 2);
MAC_DMA_wrDBus : out std_logic_vector(0 to C_MAC_DMA_PLB_DWIDTH-1);
MAC_PKT_MBusy : out std_logic_vector(0 to C_MAC_PKT_NUM_MASTERS-1);
MAC_PKT_MIRQ : out std_logic_vector(0 to C_MAC_PKT_NUM_MASTERS-1);
MAC_PKT_MRdErr : out std_logic_vector(0 to C_MAC_PKT_NUM_MASTERS-1);
MAC_PKT_MWrErr : out std_logic_vector(0 to C_MAC_PKT_NUM_MASTERS-1);
MAC_PKT_SSize : out std_logic_vector(0 to 1);
MAC_PKT_rdDBus : out std_logic_vector(0 to C_MAC_PKT_PLB_DWIDTH-1);
MAC_PKT_rdWdAddr : out std_logic_vector(0 to 3);
MAC_REG_MBusy : out std_logic_vector(0 to C_MAC_REG_NUM_MASTERS-1);
MAC_REG_MIRQ : out std_logic_vector(0 to C_MAC_REG_NUM_MASTERS-1);
MAC_REG_MRdErr : out std_logic_vector(0 to C_MAC_REG_NUM_MASTERS-1);
MAC_REG_MWrErr : out std_logic_vector(0 to C_MAC_REG_NUM_MASTERS-1);
MAC_REG_SSize : out std_logic_vector(0 to 1);
MAC_REG_rdDBus : out std_logic_vector(0 to C_MAC_REG_PLB_DWIDTH-1);
MAC_REG_rdWdAddr : out std_logic_vector(0 to 3);
PDI_AP_MBusy : out std_logic_vector(0 to C_PDI_AP_PLB_NUM_MASTERS-1);
PDI_AP_MIRQ : out std_logic_vector(0 to C_PDI_AP_PLB_NUM_MASTERS-1);
PDI_AP_MRdErr : out std_logic_vector(0 to C_PDI_AP_PLB_NUM_MASTERS-1);
PDI_AP_MWrErr : out std_logic_vector(0 to C_PDI_AP_PLB_NUM_MASTERS-1);
PDI_AP_SSize : out std_logic_vector(0 to 1);
PDI_AP_rdDBus : out std_logic_vector(0 to C_PDI_AP_PLB_DWIDTH-1);
PDI_AP_rdWdAddr : out std_logic_vector(0 to 3);
PDI_PCP_MBusy : out std_logic_vector(0 to C_PDI_PCP_NUM_MASTERS-1);
PDI_PCP_MIRQ : out std_logic_vector(0 to C_PDI_PCP_NUM_MASTERS-1);
PDI_PCP_MRdErr : out std_logic_vector(0 to C_PDI_PCP_NUM_MASTERS-1);
PDI_PCP_MWrErr : out std_logic_vector(0 to C_PDI_PCP_NUM_MASTERS-1);
PDI_PCP_SSize : out std_logic_vector(0 to 1);
PDI_PCP_rdDBus : out std_logic_vector(0 to C_PDI_PCP_PLB_DWIDTH-1);
PDI_PCP_rdWdAddr : out std_logic_vector(0 to 3);
SMP_PCP_MBusy : out std_logic_vector(0 to C_SMP_PCP_PLB_NUM_MASTERS-1);
SMP_PCP_MIRQ : out std_logic_vector(0 to C_SMP_PCP_PLB_NUM_MASTERS-1);
SMP_PCP_MRdErr : out std_logic_vector(0 to C_SMP_PCP_PLB_NUM_MASTERS-1);
SMP_PCP_MWrErr : out std_logic_vector(0 to C_SMP_PCP_PLB_NUM_MASTERS-1);
SMP_PCP_SSize : out std_logic_vector(0 to 1);
SMP_PCP_rdDBus : out std_logic_vector(0 to C_SMP_PCP_PLB_DWIDTH-1);
SMP_PCP_rdWdAddr : out std_logic_vector(0 to 3);
led_gpo : out std_logic_vector(7 downto 0);
led_opt : out std_logic_vector(1 downto 0);
led_phyAct : out std_logic_vector(1 downto 0);
led_phyLink : out std_logic_vector(1 downto 0);
pap_data_O : out std_logic_vector(C_PAP_DATA_WIDTH-1 downto 0);
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0);
phy0_TxDat : out std_logic_vector(1 downto 0);
phy1_TxDat : out std_logic_vector(1 downto 0);
phyMii0_TxDat : out std_logic_vector(3 downto 0);
phyMii1_TxDat : out std_logic_vector(3 downto 0);
pio_portOutValid : out std_logic_vector(3 downto 0);
pio_portio_O : out std_logic_vector(31 downto 0);
pio_portio_T : out std_logic_vector(31 downto 0);
test_port : out std_logic_vector(255 downto 0) := (others => '0')
);
-- Entity declarations --
-- Click here to add additional declarations --
attribute SIGIS : string;
-- Entity attributes --
attribute SIGIS of MAC_DMA_Clk : signal is "Clk";
attribute SIGIS of MAC_DMA_Rst : signal is "Rst";
attribute SIGIS of MAC_PKT_Clk : signal is "Clk";
attribute SIGIS of MAC_PKT_Rst : signal is "Rst";
attribute SIGIS of MAC_REG_Clk : signal is "Clk";
attribute SIGIS of MAC_REG_Rst : signal is "Rst";
attribute SIGIS of PDI_AP_Clk : signal is "Clk";
attribute SIGIS of PDI_AP_Rst : signal is "Rst";
attribute SIGIS of PDI_PCP_Clk : signal is "Clk";
attribute SIGIS of PDI_PCP_Rst : signal is "Rst";
attribute SIGIS of SMP_PCP_Clk : signal is "Clk";
attribute SIGIS of SMP_PCP_Rst : signal is "Rst";
attribute SIGIS of clk100 : signal is "Clk";
attribute SIGIS of clk50 : signal is "Clk";
attribute SIGIS of phy0_clk : signal is "Clk";
attribute SIGIS of phy1_clk : signal is "Clk";
end plb_powerlink;
architecture struct of plb_powerlink is
---- Architecture declarations -----
function get_max( a, b : integer) return integer is
begin
if a < b then
return b;
else
return a;
end if;
end get_max;
---- Component declarations -----
component ipif_master_handler
generic(
C_MAC_DMA_IPIF_AWIDTH : integer := 32;
C_MAC_DMA_IPIF_NATIVE_DWIDTH : integer := 32;
dma_highadr_g : integer := 31;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burstcount_width_g : integer := 4
);
port (
Bus2MAC_DMA_MstRd_d : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0);
Bus2MAC_DMA_MstRd_eof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_rem : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
Bus2MAC_DMA_MstRd_sof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_dsc_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_rdy_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_dsc_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_rdy_n : in std_logic := '1';
Bus2MAC_DMA_Mst_CmdAck : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmd_Timeout : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmplt : in std_logic := '0';
Bus2MAC_DMA_Mst_Error : in std_logic := '0';
Bus2MAC_DMA_Mst_Rearbitrate : in std_logic := '0';
MAC_DMA_CLK : in std_logic;
MAC_DMA_Rst : in std_logic;
m_address : in std_logic_vector(dma_highadr_g downto 0);
m_burstcount : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : in std_logic_vector(3 downto 0);
m_read : in std_logic := '0';
m_write : in std_logic := '0';
m_writedata : in std_logic_vector(31 downto 0);
MAC_DMA2Bus_MstRd_Req : out std_logic := '0';
MAC_DMA2Bus_MstRd_dst_dsc_n : out std_logic := '1';
MAC_DMA2Bus_MstRd_dst_rdy_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_Req : out std_logic := '0';
MAC_DMA2Bus_MstWr_d : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0);
MAC_DMA2Bus_MstWr_eof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_rem : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_MstWr_sof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_dsc_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_rdy_n : out std_logic := '1';
MAC_DMA2Bus_Mst_Addr : out std_logic_vector(C_MAC_DMA_IPIF_AWIDTH-1 downto 0);
MAC_DMA2Bus_Mst_BE : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_Mst_Length : out std_logic_vector(11 downto 0);
MAC_DMA2Bus_Mst_Lock : out std_logic := '0';
MAC_DMA2Bus_Mst_Reset : out std_logic := '0';
MAC_DMA2Bus_Mst_Type : out std_logic := '0';
m_clk : out std_logic;
m_readdata : out std_logic_vector(31 downto 0);
m_readdatavalid : out std_logic := '0';
m_waitrequest : out std_logic := '1'
);
end component;
component openMAC_16to32conv
generic(
bus_address_width : integer := 10;
gEndian : string := "little"
);
port (
bus_address : in std_logic_vector(bus_address_width-1 downto 0);
bus_byteenable : in std_logic_vector(3 downto 0);
bus_read : in std_logic;
bus_select : in std_logic;
bus_write : in std_logic;
bus_writedata : in std_logic_vector(31 downto 0);
clk : in std_logic;
rst : in std_logic;
s_readdata : in std_logic_vector(15 downto 0);
s_waitrequest : in std_logic;
bus_ack_rd : out std_logic;
bus_ack_wr : out std_logic;
bus_readdata : out std_logic_vector(31 downto 0);
s_address : out std_logic_vector(bus_address_width-1 downto 0);
s_byteenable : out std_logic_vector(1 downto 0);
s_chipselect : out std_logic;
s_read : out std_logic;
s_write : out std_logic;
s_writedata : out std_logic_vector(15 downto 0)
);
end component;
component powerlink
generic(
Simulate : integer := 0;
endian_g : string := "little";
gNumSmi : integer range 1 to 2 := 2;
genABuf1_g : integer := 1;
genABuf2_g : integer := 1;
genEvent_g : integer := 0;
genInternalAp_g : integer := 1;
genIoBuf_g : integer := 1;
genLedGadget_g : integer := 0;
genOnePdiClkDomain_g : integer := 0;
genPdi_g : integer := 1;
genSimpleIO_g : integer := 0;
genSmiIO : integer := 1;
genSpiAp_g : integer := 0;
genTimeSync_g : integer := 0;
gen_dma_observer_g : integer := 1;
iAsyBuf1Size_g : integer := 100;
iAsyBuf2Size_g : integer := 100;
iBufSizeLOG2_g : integer := 10;
iBufSize_g : integer := 1024;
iPdiRev_g : integer := 21930;
iRpdo0BufSize_g : integer := 100;
iRpdo1BufSize_g : integer := 100;
iRpdo2BufSize_g : integer := 100;
iRpdos_g : integer := 3;
iTpdoBufSize_g : integer := 100;
iTpdos_g : integer := 1;
m_burstcount_const_g : integer := 1;
m_burstcount_width_g : integer := 4;
m_data_width_g : integer := 16;
m_rx_burst_size_g : integer := 16;
m_rx_fifo_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_tx_fifo_size_g : integer := 16;
papBigEnd_g : integer := 0;
papDataWidth_g : integer := 8;
papLowAct_g : integer := 0;
pcpSysId : integer := 1;
pioValLen_g : integer := 50;
spiBigEnd_g : integer := 0;
spiCPHA_g : integer := 0;
spiCPOL_g : integer := 0;
use2ndCmpTimer_g : integer := 1;
usePulse2ndCmpTimer_g : integer := 1;
pulseWidth2ndCmpTimer_g : integer := 9;
use2ndPhy_g : integer := 1;
useIntPacketBuf_g : integer := 1;
useRmii_g : integer := 1;
useRxIntPacketBuf_g : integer := 1
);
port (
ap_address : in std_logic_vector(12 downto 0);
ap_byteenable : in std_logic_vector(3 downto 0);
ap_chipselect : in std_logic;
ap_read : in std_logic;
ap_write : in std_logic;
ap_writedata : in std_logic_vector(31 downto 0);
clk50 : in std_logic;
clkAp : in std_logic;
clkEth : in std_logic;
clkPcp : in std_logic;
m_clk : in std_logic;
m_readdata : in std_logic_vector(m_data_width_g-1 downto 0) := (others => '0');
m_readdatavalid : in std_logic := '0';
m_waitrequest : in std_logic;
mac_address : in std_logic_vector(11 downto 0);
mac_byteenable : in std_logic_vector(1 downto 0);
mac_chipselect : in std_logic;
mac_read : in std_logic;
mac_write : in std_logic;
mac_writedata : in std_logic_vector(15 downto 0);
mbf_address : in std_logic_vector(ibufsizelog2_g-3 downto 0);
mbf_byteenable : in std_logic_vector(3 downto 0);
mbf_chipselect : in std_logic;
mbf_read : in std_logic;
mbf_write : in std_logic;
mbf_writedata : in std_logic_vector(31 downto 0);
pap_addr : in std_logic_vector(15 downto 0);
pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_be_n : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_cs : in std_logic;
pap_cs_n : in std_logic;
pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0');
pap_rd : in std_logic;
pap_rd_n : in std_logic;
pap_wr : in std_logic;
pap_wr_n : in std_logic;
pcp_address : in std_logic_vector(12 downto 0);
pcp_byteenable : in std_logic_vector(3 downto 0);
pcp_chipselect : in std_logic;
pcp_read : in std_logic;
pcp_write : in std_logic;
pcp_writedata : in std_logic_vector(31 downto 0);
phy0_RxDat : in std_logic_vector(1 downto 0);
phy0_RxDv : in std_logic;
phy0_RxErr : in std_logic;
phy0_SMIDat_I : in std_logic := '1';
phy0_link : in std_logic := '0';
phy1_RxDat : in std_logic_vector(1 downto 0) := (others => '0');
phy1_RxDv : in std_logic;
phy1_RxErr : in std_logic;
phy1_SMIDat_I : in std_logic := '1';
phy1_link : in std_logic := '0';
phyMii0_RxClk : in std_logic;
phyMii0_RxDat : in std_logic_vector(3 downto 0) := (others => '0');
phyMii0_RxDv : in std_logic;
phyMii0_RxEr : in std_logic;
phyMii0_TxClk : in std_logic;
phyMii1_RxClk : in std_logic;
phyMii1_RxDat : in std_logic_vector(3 downto 0) := (others => '0');
phyMii1_RxDv : in std_logic;
phyMii1_RxEr : in std_logic;
phyMii1_TxClk : in std_logic;
phy_SMIDat_I : in std_logic := '1';
pio_pconfig : in std_logic_vector(3 downto 0);
pio_portInLatch : in std_logic_vector(3 downto 0);
pio_portio_I : in std_logic_vector(31 downto 0) := (others => '0');
pkt_clk : in std_logic;
rst : in std_logic;
rstAp : in std_logic;
rstPcp : in std_logic;
smp_address : in std_logic;
smp_byteenable : in std_logic_vector(3 downto 0);
smp_read : in std_logic;
smp_write : in std_logic;
smp_writedata : in std_logic_vector(31 downto 0);
spi_clk : in std_logic;
spi_mosi : in std_logic;
spi_sel_n : in std_logic;
tcp_address : in std_logic_vector(1 downto 0);
tcp_byteenable : in std_logic_vector(3 downto 0);
tcp_chipselect : in std_logic;
tcp_read : in std_logic;
tcp_write : in std_logic;
tcp_writedata : in std_logic_vector(31 downto 0);
ap_asyncIrq : out std_logic := '0';
ap_asyncIrq_n : out std_logic := '1';
ap_irq : out std_logic := '0';
ap_irq_n : out std_logic := '1';
ap_readdata : out std_logic_vector(31 downto 0) := (others => '0');
ap_syncIrq : out std_logic := '0';
ap_syncIrq_n : out std_logic := '1';
ap_waitrequest : out std_logic;
led_error : out std_logic := '0';
led_gpo : out std_logic_vector(7 downto 0) := (others => '0');
led_opt : out std_logic_vector(1 downto 0) := (others => '0');
led_phyAct : out std_logic_vector(1 downto 0) := (others => '0');
led_phyLink : out std_logic_vector(1 downto 0) := (others => '0');
led_status : out std_logic := '0';
m_address : out std_logic_vector(31 downto 0) := (others => '0');
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(m_data_width_g/8-1 downto 0) := (others => '0');
m_read : out std_logic := '0';
m_write : out std_logic := '0';
m_writedata : out std_logic_vector(m_data_width_g-1 downto 0) := (others => '0');
mac_irq : out std_logic := '0';
mac_readdata : out std_logic_vector(15 downto 0) := (others => '0');
mac_waitrequest : out std_logic;
mbf_readdata : out std_logic_vector(31 downto 0) := (others => '0');
mbf_waitrequest : out std_logic;
pap_ack : out std_logic := '0';
pap_ack_n : out std_logic := '1';
pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_T : out std_logic;
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0);
pcp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
pcp_waitrequest : out std_logic;
phy0_Rst_n : out std_logic := '1';
phy0_SMIClk : out std_logic := '0';
phy0_SMIDat_O : out std_logic;
phy0_SMIDat_T : out std_logic;
phy0_TxDat : out std_logic_vector(1 downto 0) := (others => '0');
phy0_TxEn : out std_logic := '0';
phy1_Rst_n : out std_logic := '1';
phy1_SMIClk : out std_logic := '0';
phy1_SMIDat_O : out std_logic;
phy1_SMIDat_T : out std_logic;
phy1_TxDat : out std_logic_vector(1 downto 0) := (others => '0');
phy1_TxEn : out std_logic := '0';
phyMii0_TxDat : out std_logic_vector(3 downto 0) := (others => '0');
phyMii0_TxEn : out std_logic := '0';
phyMii0_TxEr : out std_logic := '0';
phyMii1_TxDat : out std_logic_vector(3 downto 0) := (others => '0');
phyMii1_TxEn : out std_logic := '0';
phyMii1_TxEr : out std_logic := '0';
phy_Rst_n : out std_logic := '1';
phy_SMIClk : out std_logic := '0';
phy_SMIDat_O : out std_logic;
phy_SMIDat_T : out std_logic;
pio_operational : out std_logic := '0';
pio_portOutValid : out std_logic_vector(3 downto 0) := (others => '0');
pio_portio_O : out std_logic_vector(31 downto 0);
pio_portio_T : out std_logic_vector(31 downto 0);
smp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
smp_waitrequest : out std_logic;
spi_miso : out std_logic := '0';
tcp_irq : out std_logic := '0';
tcp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
tcp_waitrequest : out std_logic;
pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_gpio : inout std_logic_vector(1 downto 0) := (others => '0');
phy0_SMIDat : inout std_logic := '1';
phy1_SMIDat : inout std_logic := '1';
phy_SMIDat : inout std_logic := '1';
pio_portio : inout std_logic_vector(31 downto 0) := (others => '0')
);
end component;
component plbv46_master_burst
generic(
C_FAMILY : string := "virtex5";
C_INHIBIT_CC_BLE_INCLUSION : integer range 0 to 1 := 0;
C_MPLB_AWIDTH : integer range 32 to 36 := 32;
C_MPLB_DWIDTH : integer range 32 to 128 := 32;
C_MPLB_NATIVE_DWIDTH : integer range 32 to 128 := 32;
C_MPLB_SMALLEST_SLAVE : integer range 32 to 128 := 32
);
port (
IP2Bus_MstRd_Req : in std_logic;
IP2Bus_MstRd_dst_dsc_n : in std_logic;
IP2Bus_MstRd_dst_rdy_n : in std_logic;
IP2Bus_MstWr_Req : in std_logic;
IP2Bus_MstWr_d : in std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
IP2Bus_MstWr_eof_n : in std_logic;
IP2Bus_MstWr_rem : in std_logic_vector(0 to (C_MPLB_NATIVE_DWIDTH/8)-1);
IP2Bus_MstWr_sof_n : in std_logic;
IP2Bus_MstWr_src_dsc_n : in std_logic;
IP2Bus_MstWr_src_rdy_n : in std_logic;
IP2Bus_Mst_Addr : in std_logic_vector(0 to C_MPLB_AWIDTH-1);
IP2Bus_Mst_BE : in std_logic_vector(0 to (C_MPLB_NATIVE_DWIDTH/8)-1);
IP2Bus_Mst_Length : in std_logic_vector(0 to 11);
IP2Bus_Mst_Lock : in std_logic;
IP2Bus_Mst_Reset : in std_logic;
IP2Bus_Mst_Type : in std_logic;
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MBusy : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to C_MPLB_DWIDTH-1);
PLB_MRdErr : in std_logic;
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MTimeout : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrErr : in std_logic;
Bus2IP_MstRd_d : out std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
Bus2IP_MstRd_eof_n : out std_logic;
Bus2IP_MstRd_rem : out std_logic_vector(0 to (C_MPLB_NATIVE_DWIDTH/8)-1);
Bus2IP_MstRd_sof_n : out std_logic;
Bus2IP_MstRd_src_dsc_n : out std_logic;
Bus2IP_MstRd_src_rdy_n : out std_logic;
Bus2IP_MstWr_dst_dsc_n : out std_logic;
Bus2IP_MstWr_dst_rdy_n : out std_logic;
Bus2IP_Mst_CmdAck : out std_logic;
Bus2IP_Mst_Cmd_Timeout : out std_logic;
Bus2IP_Mst_Cmplt : out std_logic;
Bus2IP_Mst_Error : out std_logic;
Bus2IP_Mst_Rearbitrate : out std_logic;
MD_Error : out std_logic;
M_ABus : out std_logic_vector(0 to 31);
M_BE : out std_logic_vector(0 to (C_MPLB_DWIDTH/8)-1);
M_MSize : out std_logic_vector(0 to 1);
M_RNW : out std_logic;
M_TAttribute : out std_logic_vector(0 to 15);
M_UABus : out std_logic_vector(0 to 31);
M_abort : out std_logic;
M_busLock : out std_logic;
M_lockErr : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1)
);
end component;
component plbv46_slave_single
generic(
C_ARD_ADDR_RANGE_ARRAY : slv64_array_type := (X"0000_0000_7000_0000",X"0000_0000_7000_00FF",X"0000_0000_7000_0100",X"0000_0000_7000_01FF");
C_ARD_NUM_CE_ARRAY : integer_array_type := (1,8);
C_BUS2CORE_CLK_RATIO : integer range 1 to 2 := 1;
C_FAMILY : string := "virtex4";
C_INCLUDE_DPHASE_TIMER : integer range 0 to 1 := 1;
C_SIPIF_DWIDTH : integer range 32 to 32 := 32;
C_SPLB_AWIDTH : integer range 32 to 32 := 32;
C_SPLB_DWIDTH : integer range 32 to 128 := 32;
C_SPLB_MID_WIDTH : integer range 1 to 4 := 2;
C_SPLB_NUM_MASTERS : integer range 1 to 16 := 8;
C_SPLB_P2P : integer range 0 to 1 := 0
);
port (
IP2Bus_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
IP2Bus_Error : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_WrAck : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_BE : in std_logic_vector(0 to (C_SPLB_DWIDTH/8)-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_PAValid : in std_logic;
PLB_RNW : in std_logic;
PLB_SAValid : in std_logic;
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_lockErr : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_rdBurst : in std_logic;
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_rdPendReq : in std_logic;
PLB_rdPrim : in std_logic;
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrBurst : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_wrPendReq : in std_logic;
PLB_wrPrim : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
Bus2IP_Addr : out std_logic_vector(0 to C_SPLB_AWIDTH-1);
Bus2IP_BE : out std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
Bus2IP_CS : out std_logic_vector(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
Bus2IP_Clk : out std_logic;
Bus2IP_Data : out std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_RNW : out std_logic;
Bus2IP_RdCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_Reset : out std_logic;
Bus2IP_WrCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_SSize : out std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdDAck : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rearbitrate : out std_logic;
Sl_wait : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrDAck : out std_logic
);
end component;
---- Architecture declarations -----
constant C_ADDR_PAD_ZERO : std_logic_vector(31 downto 0) := (others => '0');
-- openMAC REG PLB Slave
constant C_MAC_REG_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_REG_BASEADDR;
constant C_MAC_REG_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_REG_HIGHADDR;
-- openMAC CMP PLB Slave
constant C_MAC_CMP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_CMP_BASEADDR;
constant C_MAC_CMP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_CMP_HIGHADDR;
-- openMAC PKT PLB Slave
constant C_MAC_PKT_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_PKT_BASEADDR;
constant C_MAC_PKT_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_PKT_HIGHADDR;
-- SimpleIO Slave
constant C_SMP_PCP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_SMP_PCP_BASEADDR;
constant C_SMP_PCP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_SMP_PCP_HIGHADDR;
-- PDI PCP Slave
constant C_PDI_PCP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_PDI_PCP_BASEADDR;
constant C_PDI_PCP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_PDI_PCP_HIGHADDR;
-- AP PCP Slave
constant C_PDI_AP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_PDI_AP_BASEADDR;
constant C_PDI_AP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_PDI_AP_HIGHADDR;
-- POWERLINK IP-core
constant C_MAC_PKT_EN : boolean := C_TX_INT_PKT or C_RX_INT_PKT;
constant C_MAC_PKT_RX_EN : boolean := C_RX_INT_PKT;
constant C_DMA_EN : boolean := not C_TX_INT_PKT or not C_RX_INT_PKT;
constant C_PKT_BUF_EN : boolean := C_MAC_PKT_EN;
constant C_M_BURSTCOUNT_WIDTH : integer := integer(ceil(log2(real(get_max(C_MAC_DMA_BURST_SIZE_RX,C_MAC_DMA_BURST_SIZE_TX)/4)))) + 1; --in dwords
constant C_M_FIFO_SIZE_RX : integer := C_MAC_DMA_FIFO_SIZE_RX/4; --in dwords
constant C_M_FIFO_SIZE_TX : integer := C_MAC_DMA_FIFO_SIZE_TX/4; --in dwords
---- Constants -----
constant VCC_CONSTANT : std_logic := '1';
constant GND_CONSTANT : std_logic := '0';
---- Signal declarations used on the diagram ----
signal ap_chipselect : std_logic;
signal ap_read : std_logic;
signal ap_waitrequest : std_logic;
signal ap_write : std_logic;
signal Bus2MAC_CMP_Reset : std_logic;
signal Bus2MAC_DMA_MstRd_eof_n : std_logic;
signal Bus2MAC_DMA_MstRd_sof_n : std_logic;
signal Bus2MAC_DMA_MstRd_src_dsc_n : std_logic;
signal Bus2MAC_DMA_MstRd_src_rdy_n : std_logic;
signal Bus2MAC_DMA_MstWr_dst_dsc_n : std_logic;
signal Bus2MAC_DMA_MstWr_dst_rdy_n : std_logic;
signal Bus2MAC_DMA_Mst_CmdAck : std_logic;
signal Bus2MAC_DMA_Mst_Cmd_Timeout : std_logic;
signal Bus2MAC_DMA_Mst_Cmplt : std_logic;
signal Bus2MAC_DMA_Mst_Error : std_logic;
signal Bus2MAC_DMA_Mst_Rearbitrate : std_logic;
signal Bus2MAC_PKT_Clk : std_logic;
signal Bus2MAC_PKT_Reset : std_logic;
signal Bus2MAC_PKT_RNW : std_logic;
signal Bus2MAC_REG_Clk : std_logic;
signal Bus2MAC_REG_Reset : std_logic;
signal Bus2MAC_REG_RNW : std_logic;
signal Bus2MAC_REG_RNW_n : std_logic;
signal Bus2PDI_AP_Clk : std_logic;
signal Bus2PDI_AP_Reset : std_logic;
signal Bus2PDI_AP_RNW : std_logic;
signal Bus2PDI_PCP_Clk : std_logic;
signal Bus2PDI_PCP_Reset : std_logic;
signal Bus2PDI_PCP_RNW : std_logic;
signal Bus2SMP_PCP_Clk : std_logic;
signal Bus2SMP_PCP_Reset : std_logic;
signal Bus2SMP_PCP_RNW : std_logic;
signal clkAp : std_logic;
signal clkPcp : std_logic;
signal GND : std_logic;
signal IP2Bus_Error_s : std_logic;
signal IP2Bus_RdAck_s : std_logic;
signal IP2Bus_WrAck_s : std_logic;
signal mac_chipselect : std_logic;
signal MAC_CMP2Bus_Error : std_logic;
signal MAC_CMP2Bus_RdAck : std_logic;
signal MAC_CMP2Bus_WrAck : std_logic;
signal MAC_DMA2Bus_MstRd_dst_dsc_n : std_logic;
signal MAC_DMA2Bus_MstRd_dst_rdy_n : std_logic;
signal MAC_DMA2Bus_MstRd_Req : std_logic;
signal MAC_DMA2Bus_MstWr_eof_n : std_logic;
signal MAC_DMA2Bus_MstWr_Req : std_logic;
signal MAC_DMA2Bus_MstWr_sof_n : std_logic;
signal MAC_DMA2Bus_MstWr_src_dsc_n : std_logic;
signal MAC_DMA2Bus_MstWr_src_rdy_n : std_logic;
signal MAC_DMA2Bus_Mst_Lock : std_logic;
signal MAC_DMA2Bus_Mst_Reset : std_logic;
signal MAC_DMA2Bus_Mst_Type : std_logic;
signal mac_irq_s : std_logic;
signal MAC_PKT2Bus_Error : std_logic;
signal MAC_PKT2Bus_RdAck : std_logic;
signal MAC_PKT2Bus_WrAck : std_logic;
signal mac_read : std_logic;
signal MAC_REG2Bus_Error : std_logic;
signal MAC_REG2Bus_RdAck : std_logic;
signal MAC_REG2Bus_WrAck : std_logic;
signal mac_waitrequest : std_logic;
signal mac_write : std_logic;
signal mbf_chipselect : std_logic;
signal mbf_read : std_logic;
signal mbf_waitrequest : std_logic;
signal mbf_write : std_logic;
signal m_clk : std_logic;
signal m_read : std_logic;
signal m_readdatavalid : std_logic;
signal m_waitrequest : std_logic;
signal m_write : std_logic;
signal NET118078 : std_ulogic;
signal NET118214 : std_ulogic;
signal pcp_chipselect : std_logic;
signal pcp_read : std_logic;
signal pcp_waitrequest : std_logic;
signal pcp_write : std_logic;
signal PDI_AP2Bus_Error : std_logic;
signal PDI_AP2Bus_RdAck : std_logic;
signal PDI_AP2Bus_WrAck : std_logic;
signal PDI_PCP2Bus_Error : std_logic;
signal PDI_PCP2Bus_RdAck : std_logic;
signal PDI_PCP2Bus_WrAck : std_logic;
signal pkt_clk : std_logic;
signal rst : std_logic;
signal rstAp : std_logic;
signal rstPcp : std_logic;
signal smp_address : std_logic;
signal smp_chipselect : std_logic;
signal SMP_PCP2Bus_Error : std_logic;
signal SMP_PCP2Bus_RdAck : std_logic;
signal SMP_PCP2Bus_WrAck : std_logic;
signal smp_read : std_logic;
signal smp_waitrequest : std_logic;
signal smp_write : std_logic;
signal tcp_chipselect : std_logic;
signal tcp_irq_s : std_logic;
signal tcp_read : std_logic;
signal tcp_waitrequest : std_logic;
signal tcp_write : std_logic;
signal VCC : std_logic;
signal ap_address : std_logic_vector (12 downto 0);
signal ap_byteenable : std_logic_vector (3 downto 0);
signal ap_readdata : std_logic_vector (31 downto 0);
signal ap_writedata : std_logic_vector (31 downto 0);
signal Bus2MAC_DMA_MstRd_d : std_logic_vector (C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0);
signal Bus2MAC_DMA_MstRd_d_s : std_logic_vector (C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0);
signal Bus2MAC_DMA_MstRd_rem : std_logic_vector (0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1);
signal Bus2MAC_PKT_Addr : std_logic_vector (C_MAC_PKT_PLB_AWIDTH-1 downto 0);
signal Bus2MAC_PKT_BE : std_logic_vector ((C_MAC_PKT_PLB_DWIDTH/8)-1 downto 0);
signal Bus2MAC_PKT_CS : std_logic_vector (0 downto 0);
signal Bus2MAC_PKT_Data : std_logic_vector (C_MAC_PKT_PLB_DWIDTH-1 downto 0);
signal Bus2MAC_REG_Addr : std_logic_vector (C_MAC_REG_PLB_AWIDTH-1 downto 0);
signal Bus2MAC_REG_BE : std_logic_vector ((C_MAC_REG_PLB_DWIDTH/8)-1 downto 0);
signal Bus2MAC_REG_BE_s : std_logic_vector ((C_MAC_REG_PLB_DWIDTH/8)-1 downto 0);
signal Bus2MAC_REG_CS : std_logic_vector (1 downto 0);
signal Bus2MAC_REG_Data : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal Bus2MAC_REG_Data_s : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal Bus2PDI_AP_Addr : std_logic_vector (C_PDI_AP_PLB_AWIDTH-1 downto 0);
signal Bus2PDI_AP_BE : std_logic_vector ((C_PDI_AP_PLB_DWIDTH/8)-1 downto 0);
signal Bus2PDI_AP_CS : std_logic_vector (0 downto 0);
signal Bus2PDI_AP_Data : std_logic_vector (C_PDI_AP_PLB_DWIDTH-1 downto 0);
signal Bus2PDI_PCP_Addr : std_logic_vector (C_PDI_PCP_PLB_AWIDTH-1 downto 0);
signal Bus2PDI_PCP_BE : std_logic_vector ((C_PDI_PCP_PLB_DWIDTH/8)-1 downto 0);
signal Bus2PDI_PCP_CS : std_logic_vector (0 downto 0);
signal Bus2PDI_PCP_Data : std_logic_vector (C_PDI_PCP_PLB_DWIDTH-1 downto 0);
signal Bus2SMP_PCP_Addr : std_logic_vector (C_SMP_PCP_PLB_AWIDTH-1 downto 0);
signal Bus2SMP_PCP_BE : std_logic_vector ((C_SMP_PCP_PLB_DWIDTH/8)-1 downto 0);
signal Bus2SMP_PCP_CS : std_logic_vector (0 downto 0);
signal Bus2SMP_PCP_Data : std_logic_vector (C_SMP_PCP_PLB_DWIDTH-1 downto 0);
signal IP2Bus_Data_s : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal mac_address : std_logic_vector (C_MAC_REG_PLB_AWIDTH-1 downto 0);
signal mac_byteenable : std_logic_vector (1 downto 0);
signal MAC_CMP2Bus_Data : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal MAC_DMA2Bus_MstWr_d : std_logic_vector (C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0);
signal MAC_DMA2Bus_MstWr_d_s : std_logic_vector (C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0);
signal MAC_DMA2Bus_MstWr_rem : std_logic_vector (0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1);
signal MAC_DMA2Bus_Mst_Addr : std_logic_vector (0 to C_MAC_DMA_PLB_AWIDTH-1);
signal MAC_DMA2Bus_Mst_BE : std_logic_vector (0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1);
signal MAC_DMA2Bus_Mst_Length : std_logic_vector (0 to 11);
signal MAC_PKT2Bus_Data : std_logic_vector (C_MAC_PKT_PLB_DWIDTH-1 downto 0);
signal mac_readdata : std_logic_vector (15 downto 0);
signal MAC_REG2Bus_Data : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal MAC_REG2Bus_Data_s : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal mac_writedata : std_logic_vector (15 downto 0);
signal mbf_address : std_logic_vector (C_MAC_PKT_SIZE_LOG2-3 downto 0);
signal mbf_byteenable : std_logic_vector (3 downto 0);
signal mbf_readdata : std_logic_vector (31 downto 0);
signal mbf_writedata : std_logic_vector (31 downto 0);
signal m_address : std_logic_vector (31 downto 0);
signal m_burstcount : std_logic_vector (C_M_BURSTCOUNT_WIDTH-1 downto 0);
signal m_burstcounter : std_logic_vector (C_M_BURSTCOUNT_WIDTH-1 downto 0);
signal m_byteenable : std_logic_vector (3 downto 0);
signal m_readdata : std_logic_vector (31 downto 0);
signal m_writedata : std_logic_vector (31 downto 0);
signal pcp_address : std_logic_vector (12 downto 0);
signal pcp_byteenable : std_logic_vector (3 downto 0);
signal pcp_readdata : std_logic_vector (31 downto 0);
signal pcp_writedata : std_logic_vector (31 downto 0);
signal PDI_AP2Bus_Data : std_logic_vector (C_PDI_AP_PLB_DWIDTH-1 downto 0);
signal PDI_PCP2Bus_Data : std_logic_vector (C_PDI_PCP_PLB_DWIDTH-1 downto 0);
signal smp_byteenable : std_logic_vector (3 downto 0);
signal SMP_PCP2Bus_Data : std_logic_vector (C_SMP_PCP_PLB_DWIDTH-1 downto 0);
signal smp_readdata : std_logic_vector (31 downto 0);
signal smp_writedata : std_logic_vector (31 downto 0);
signal tcp_address : std_logic_vector (1 downto 0);
signal tcp_byteenable : std_logic_vector (3 downto 0);
signal tcp_readdata : std_logic_vector (31 downto 0);
signal tcp_writedata : std_logic_vector (31 downto 0);
begin
---- User Signal Assignments ----
-- connect mac reg with mac cmp or reg output signals
with Bus2MAC_REG_CS select
IP2Bus_Data_s(C_MAC_REG_PLB_DWIDTH-1 downto 0) <= MAC_REG2Bus_Data(C_MAC_REG_PLB_DWIDTH-1 downto 0) when "10",
MAC_CMP2Bus_Data(C_MAC_REG_PLB_DWIDTH-1 downto 0) when "01",
(others => '0') when others;
with Bus2MAC_REG_CS select
IP2Bus_WrAck_s <= MAC_REG2Bus_WrAck when "10",
MAC_CMP2Bus_WrAck when "01",
'0' when others;
with Bus2MAC_REG_CS select
IP2Bus_RdAck_s <= MAC_REG2Bus_RdAck when "10",
MAC_CMP2Bus_RdAck when "01",
'0' when others;
with Bus2MAC_REG_CS select
IP2Bus_Error_s <= MAC_REG2Bus_Error when "10",
MAC_CMP2Bus_Error when "01",
'0' when others;
Bus2MAC_REG_BE_s <=
Bus2MAC_REG_BE(0) & Bus2MAC_REG_BE(1) &
Bus2MAC_REG_BE(2) & Bus2MAC_REG_BE(3);
Bus2MAC_REG_Data_s <=
Bus2MAC_REG_Data(7 downto 0) & Bus2MAC_REG_Data(15 downto 8) &
Bus2MAC_REG_Data(23 downto 16) & Bus2MAC_REG_Data(31 downto 24);
MAC_REG2Bus_Data <=
MAC_REG2Bus_Data_s(7 downto 0) & MAC_REG2Bus_Data_s(15 downto 8) &
MAC_REG2Bus_Data_s(23 downto 16) & MAC_REG2Bus_Data_s(31 downto 24);
--test_port
test_port(181 downto 179) <= mac_chipselect & mac_write & mac_read;
test_port(178) <= mac_waitrequest;
test_port(177 downto 176) <= mac_byteenable;
test_port(171 downto 160) <= mac_address(11 downto 0);
test_port(159 downto 144) <= mac_writedata;
test_port(143 downto 128) <= mac_readdata;
test_port(104 downto 102) <= Bus2MAC_REG_CS & Bus2MAC_REG_RNW;
test_port(101 downto 100) <= IP2Bus_WrAck_s & IP2Bus_RdAck_s;
test_port(99 downto 96) <= Bus2MAC_REG_BE;
test_port(95 downto 64) <= Bus2MAC_REG_Addr;
test_port(63 downto 32) <= Bus2MAC_REG_Data;
test_port(31 downto 0) <= IP2Bus_Data_s;
--test_port(255 downto 251) <= m_read & m_write & m_waitrequest & m_readdatavalid & MAC_DMA2Bus_Mst_Type;
--test_port(244 downto 240) <= MAC_DMA2Bus_MstWr_Req & MAC_DMA2Bus_MstWr_sof_n & MAC_DMA2Bus_MstWr_eof_n & MAC_DMA2Bus_MstWr_src_rdy_n & Bus2MAC_DMA_MstWr_dst_rdy_n;
--test_port(234 downto 230) <= MAC_DMA2Bus_MstRd_Req & Bus2MAC_DMA_MstRd_sof_n & Bus2MAC_DMA_MstRd_eof_n & Bus2MAC_DMA_MstRd_src_rdy_n & MAC_DMA2Bus_MstRd_dst_rdy_n;
--test_port(142 downto 140) <= Bus2MAC_DMA_Mst_Cmplt & Bus2MAC_DMA_Mst_Error & Bus2MAC_DMA_Mst_Cmd_Timeout;
--test_port(MAC_DMA2Bus_Mst_Length'length+120-1 downto 120) <= MAC_DMA2Bus_Mst_Length;
--test_port(m_burstcount'length+110-1 downto 110) <= m_burstcount;
--test_port(m_burstcounter'length+96-1 downto 96) <= m_burstcounter;
--test_port(95 downto 64) <= m_address;
--test_port(63 downto 32) <= m_writedata;
--test_port(31 downto 0) <= m_readdata;
--mac_cmp assignments
---cmp_clk <= Bus2MAC_CMP_Clk;
tcp_writedata <=
Bus2MAC_REG_Data(7 downto 0) & Bus2MAC_REG_Data(15 downto 8) &
Bus2MAC_REG_Data(23 downto 16) & Bus2MAC_REG_Data(31 downto 24);
tcp_read <= Bus2MAC_REG_RNW;
tcp_write <= not Bus2MAC_REG_RNW;
tcp_chipselect <= Bus2MAC_REG_CS(0);
tcp_byteenable <=
Bus2MAC_REG_BE(0) & Bus2MAC_REG_BE(1) &
Bus2MAC_REG_BE(2) & Bus2MAC_REG_BE(3);
tcp_address <= Bus2MAC_REG_Addr(3 downto 2);
MAC_CMP2Bus_Data <=
tcp_readdata(7 downto 0) & tcp_readdata(15 downto 8) &
tcp_readdata(23 downto 16) & tcp_readdata(31 downto 24);
MAC_CMP2Bus_RdAck <= tcp_chipselect and tcp_read and not tcp_waitrequest;
MAC_CMP2Bus_WrAck <= tcp_chipselect and tcp_write and not tcp_waitrequest;
MAC_CMP2Bus_Error <= '0';
--mac_pkt assignments
pkt_clk <= Bus2MAC_PKT_Clk;
mbf_writedata <=
Bus2MAC_PKT_Data(7 downto 0) & Bus2MAC_PKT_Data(15 downto 8) &
Bus2MAC_PKT_Data(23 downto 16) & Bus2MAC_PKT_Data(31 downto 24);
mbf_read <= Bus2MAC_PKT_RNW;
mbf_write <= not Bus2MAC_PKT_RNW;
mbf_chipselect <= Bus2MAC_PKT_CS(0);
mbf_byteenable <=
Bus2MAC_PKT_BE(0) & Bus2MAC_PKT_BE(1) &
Bus2MAC_PKT_BE(2) & Bus2MAC_PKT_BE(3);
mbf_address <= Bus2MAC_PKT_Addr(C_MAC_PKT_SIZE_LOG2-1 downto 2);
MAC_PKT2Bus_Data <=
mbf_readdata(7 downto 0) & mbf_readdata(15 downto 8) &
mbf_readdata(23 downto 16) & mbf_readdata(31 downto 24);
MAC_PKT2Bus_RdAck <= mbf_chipselect and mbf_read and not mbf_waitrequest;
MAC_PKT2Bus_WrAck <= mbf_chipselect and mbf_write and not mbf_waitrequest;
MAC_PKT2Bus_Error <= '0';
---- Component instantiations ----
MAC_REG_16to32 : openMAC_16to32conv
generic map (
bus_address_width => C_MAC_REG_PLB_AWIDTH,
gEndian => "big"
)
port map(
bus_ack_rd => MAC_REG2Bus_RdAck,
bus_ack_wr => MAC_REG2Bus_WrAck,
bus_address => Bus2MAC_REG_Addr( C_MAC_REG_PLB_AWIDTH-1 downto 0 ),
bus_byteenable => Bus2MAC_REG_BE_s( (C_MAC_REG_PLB_DWIDTH/8)-1 downto 0 ),
bus_read => Bus2MAC_REG_RNW,
bus_readdata => MAC_REG2Bus_Data_s( C_MAC_REG_PLB_DWIDTH-1 downto 0 ),
bus_select => Bus2MAC_REG_CS(1),
bus_write => Bus2MAC_REG_RNW_n,
bus_writedata => Bus2MAC_REG_Data_s( C_MAC_REG_PLB_DWIDTH-1 downto 0 ),
clk => clk50,
rst => rst,
s_address => mac_address( C_MAC_REG_PLB_AWIDTH-1 downto 0 ),
s_byteenable => mac_byteenable,
s_chipselect => mac_chipselect,
s_read => mac_read,
s_readdata => mac_readdata,
s_waitrequest => mac_waitrequest,
s_write => mac_write,
s_writedata => mac_writedata
);
MAC_REG_PLB_SINGLE_SLAVE : plbv46_slave_single
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_MAC_REG_BASE,C_MAC_REG_HIGH,C_MAC_CMP_BASE,C_MAC_CMP_HIGH),
C_ARD_NUM_CE_ARRAY => (1, 1),
C_BUS2CORE_CLK_RATIO => C_MAC_REG_BUS2CORE_CLK_RATIO,
C_FAMILY => C_FAMILY,
C_INCLUDE_DPHASE_TIMER => 0,
C_SIPIF_DWIDTH => C_MAC_REG_PLB_DWIDTH,
C_SPLB_AWIDTH => C_MAC_REG_PLB_AWIDTH,
C_SPLB_DWIDTH => C_MAC_REG_PLB_DWIDTH,
C_SPLB_MID_WIDTH => C_MAC_REG_PLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_MAC_REG_PLB_NUM_MASTERS,
C_SPLB_P2P => C_MAC_REG_PLB_P2P
)
port map(
Bus2IP_Addr => Bus2MAC_REG_Addr( C_MAC_REG_PLB_AWIDTH-1 downto 0 ),
Bus2IP_BE => Bus2MAC_REG_BE( (C_MAC_REG_PLB_DWIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2MAC_REG_CS( 1 downto 0 ),
Bus2IP_Clk => Bus2MAC_REG_Clk,
Bus2IP_Data => Bus2MAC_REG_Data( C_MAC_REG_PLB_DWIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2MAC_REG_RNW,
Bus2IP_Reset => Bus2MAC_REG_Reset,
IP2Bus_Data => IP2Bus_Data_s( C_MAC_REG_PLB_DWIDTH-1 downto 0 ),
IP2Bus_Error => IP2Bus_Error_s,
IP2Bus_RdAck => IP2Bus_RdAck_s,
IP2Bus_WrAck => IP2Bus_WrAck_s,
PLB_ABus => MAC_REG_ABus,
PLB_BE => MAC_REG_BE( 0 to (C_MAC_REG_PLB_DWIDTH / 8) - 1 ),
PLB_MSize => MAC_REG_MSize,
PLB_PAValid => MAC_REG_PAValid,
PLB_RNW => MAC_REG_RNW,
PLB_SAValid => MAC_REG_SAValid,
PLB_TAttribute => MAC_REG_TAttribute,
PLB_UABus => MAC_REG_UABus,
PLB_abort => MAC_REG_abort,
PLB_busLock => MAC_REG_busLock,
PLB_lockErr => MAC_REG_lockErr,
PLB_masterID => MAC_REG_masterID( 0 to C_MAC_REG_PLB_MID_WIDTH - 1 ),
PLB_rdBurst => MAC_REG_rdBurst,
PLB_rdPendPri => MAC_REG_rdPendPri,
PLB_rdPendReq => MAC_REG_rdPendReq,
PLB_rdPrim => MAC_REG_rdPrim,
PLB_reqPri => MAC_REG_reqPri,
PLB_size => MAC_REG_size,
PLB_type => MAC_REG_type,
PLB_wrBurst => MAC_REG_wrBurst,
PLB_wrDBus => MAC_REG_wrDBus( 0 to C_MAC_REG_PLB_DWIDTH - 1 ),
PLB_wrPendPri => MAC_REG_wrPendPri,
PLB_wrPendReq => MAC_REG_wrPendReq,
PLB_wrPrim => MAC_REG_wrPrim,
SPLB_Clk => MAC_REG_Clk,
SPLB_Rst => MAC_REG_Rst,
Sl_MBusy => MAC_REG_MBusy( 0 to C_MAC_REG_NUM_MASTERS-1 ),
Sl_MIRQ => MAC_REG_MIRQ( 0 to C_MAC_REG_NUM_MASTERS-1 ),
Sl_MRdErr => MAC_REG_MRdErr( 0 to C_MAC_REG_NUM_MASTERS-1 ),
Sl_MWrErr => MAC_REG_MWrErr( 0 to C_MAC_REG_NUM_MASTERS-1 ),
Sl_SSize => MAC_REG_SSize,
Sl_addrAck => MAC_REG_addrAck,
Sl_rdBTerm => MAC_REG_rdBTerm,
Sl_rdComp => MAC_REG_rdComp,
Sl_rdDAck => MAC_REG_rdDAck,
Sl_rdDBus => MAC_REG_rdDBus( 0 to C_MAC_REG_PLB_DWIDTH-1 ),
Sl_rdWdAddr => MAC_REG_rdWdAddr,
Sl_rearbitrate => MAC_REG_rearbitrate,
Sl_wait => MAC_REG_wait,
Sl_wrBTerm => MAC_REG_wrBTerm,
Sl_wrComp => MAC_REG_wrComp,
Sl_wrDAck => MAC_REG_wrDAck
);
THE_POWERLINK_IP_CORE : powerlink
generic map (
Simulate => booleanToInteger(false),
endian_g => "big",
gNumSmi => C_NUM_SMI,
genABuf1_g => booleanToInteger(C_PDI_GEN_ASYNC_BUF_0),
genABuf2_g => booleanToInteger(C_PDI_GEN_ASYNC_BUF_1),
genEvent_g => booleanToInteger(C_PDI_GEN_EVENT),
genInternalAp_g => booleanToInteger(C_GEN_PLB_BUS_IF),
genIoBuf_g => booleanToInteger(false),
genLedGadget_g => booleanToInteger(C_PDI_GEN_LED),
genOnePdiClkDomain_g => booleanToInteger(false),
genPdi_g => booleanToInteger(C_GEN_PDI),
genSimpleIO_g => booleanToInteger(C_GEN_SIMPLE_IO),
genSmiIO => booleanToInteger(false),
genSpiAp_g => booleanToInteger(C_GEN_SPI_IF),
genTimeSync_g => booleanToInteger(C_PDI_GEN_TIME_SYNC),
gen_dma_observer_g => booleanToInteger(C_OBSERVER_ENABLE),
iAsyBuf1Size_g => C_PDI_ASYNC_BUF_0,
iAsyBuf2Size_g => C_PDI_ASYNC_BUF_1,
iBufSizeLOG2_g => C_MAC_PKT_SIZE_LOG2,
iBufSize_g => C_MAC_PKT_SIZE,
iPdiRev_g => C_PDI_REV,
iRpdo0BufSize_g => C_RPDO_0_BUF_SIZE,
iRpdo1BufSize_g => C_RPDO_1_BUF_SIZE,
iRpdo2BufSize_g => C_RPDO_2_BUF_SIZE,
iRpdos_g => C_NUM_RPDO,
iTpdoBufSize_g => C_TPDO_BUF_SIZE,
iTpdos_g => C_NUM_TPDO,
m_burstcount_const_g => booleanToInteger(true),
m_burstcount_width_g => C_M_BURSTCOUNT_WIDTH,
m_data_width_g => 32,
m_rx_burst_size_g => C_MAC_DMA_BURST_SIZE_RX/4,
m_rx_fifo_size_g => C_M_FIFO_SIZE_RX,
m_tx_burst_size_g => C_MAC_DMA_BURST_SIZE_TX/4,
m_tx_fifo_size_g => C_M_FIFO_SIZE_TX,
papBigEnd_g => booleanToInteger(false),
papDataWidth_g => C_PAP_DATA_WIDTH,
papLowAct_g => booleanToInteger(C_PAP_LOW_ACT),
pcpSysId => C_PCP_SYS_ID,
pioValLen_g => C_PIO_VAL_LENGTH,
pulseWidth2ndCmpTimer_g => C_PULSE_WIDTH_2nd_CMP_TIMER,
spiBigEnd_g => booleanToInteger(false),
spiCPHA_g => booleanToInteger(C_SPI_CPHA),
spiCPOL_g => booleanToInteger(C_SPI_CPOL),
use2ndCmpTimer_g => booleanToInteger(C_MAC_GEN_SECOND_TIMER),
use2ndPhy_g => booleanToInteger(C_USE_2ND_PHY),
useIntPacketBuf_g => booleanToInteger(C_MAC_PKT_EN),
usePulse2ndCmpTimer_g => booleanToInteger(C_USE_PULSE_2nd_CMP_TIMER),
useRmii_g => booleanToInteger(C_USE_RMII),
useRxIntPacketBuf_g => booleanToInteger(C_MAC_PKT_RX_EN)
)
port map(
mac_address(0) => mac_address(0),
mac_address(1) => mac_address(1),
mac_address(2) => mac_address(2),
mac_address(3) => mac_address(3),
mac_address(4) => mac_address(4),
mac_address(5) => mac_address(5),
mac_address(6) => mac_address(6),
mac_address(7) => mac_address(7),
mac_address(8) => mac_address(8),
mac_address(9) => mac_address(9),
mac_address(10) => mac_address(10),
mac_address(11) => mac_address(11),
ap_address => ap_address,
ap_asyncIrq => ap_asyncIrq,
ap_asyncIrq_n => ap_asyncIrq_n,
ap_byteenable => ap_byteenable,
ap_chipselect => ap_chipselect,
ap_read => ap_read,
ap_readdata => ap_readdata,
ap_syncIrq => ap_syncIrq,
ap_syncIrq_n => ap_syncIrq_n,
ap_waitrequest => ap_waitrequest,
ap_write => ap_write,
ap_writedata => ap_writedata,
clk50 => clk50,
clkAp => clkAp,
clkEth => clk100,
clkPcp => clkPcp,
led_error => led_error,
led_gpo => led_gpo,
led_opt => led_opt,
led_phyAct => led_phyAct,
led_phyLink => led_phyLink,
led_status => led_status,
m_address => m_address,
m_burstcount => m_burstcount( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_burstcounter => m_burstcounter( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_byteenable => m_byteenable( 3 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdata => m_readdata( 31 downto 0 ),
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
m_writedata => m_writedata( 31 downto 0 ),
mac_byteenable => mac_byteenable,
mac_chipselect => mac_chipselect,
mac_irq => mac_irq_s,
mac_read => mac_read,
mac_readdata => mac_readdata,
mac_waitrequest => mac_waitrequest,
mac_write => mac_write,
mac_writedata => mac_writedata,
mbf_address => mbf_address( C_MAC_PKT_SIZE_LOG2-3 downto 0 ),
mbf_byteenable => mbf_byteenable,
mbf_chipselect => mbf_chipselect,
mbf_read => mbf_read,
mbf_readdata => mbf_readdata,
mbf_waitrequest => mbf_waitrequest,
mbf_write => mbf_write,
mbf_writedata => mbf_writedata,
pap_ack => pap_ack,
pap_ack_n => pap_ack_n,
pap_addr => pap_addr,
pap_be => pap_be( C_PAP_DATA_WIDTH/8-1 downto 0 ),
pap_be_n => pap_be_n( C_PAP_DATA_WIDTH/8-1 downto 0 ),
pap_cs => pap_cs,
pap_cs_n => pap_cs_n,
pap_data_I => pap_data_I( C_PAP_DATA_WIDTH-1 downto 0 ),
pap_data_O => pap_data_O( C_PAP_DATA_WIDTH-1 downto 0 ),
pap_data_T => pap_data_T,
pap_gpio_I => pap_gpio_I,
pap_gpio_O => pap_gpio_O,
pap_gpio_T => pap_gpio_T,
pap_rd => pap_rd,
pap_rd_n => pap_rd_n,
pap_wr => pap_wr,
pap_wr_n => pap_wr_n,
pcp_address => pcp_address,
pcp_byteenable => pcp_byteenable,
pcp_chipselect => pcp_chipselect,
pcp_read => pcp_read,
pcp_readdata => pcp_readdata,
pcp_waitrequest => pcp_waitrequest,
pcp_write => pcp_write,
pcp_writedata => pcp_writedata,
phy0_Rst_n => phy0_Rst_n,
phy0_RxDat => phy0_RxDat,
phy0_RxDv => phy0_RxDv,
phy0_RxErr => phy0_RxErr,
phy0_SMIClk => phy0_SMIClk,
phy0_SMIDat_I => phy0_SMIDat_I,
phy0_SMIDat_O => phy0_SMIDat_O,
phy0_SMIDat_T => phy0_SMIDat_T,
phy0_TxDat => phy0_TxDat,
phy0_TxEn => phy0_TxEn,
phy0_link => phy0_link,
phy1_Rst_n => phy1_Rst_n,
phy1_RxDat => phy1_RxDat,
phy1_RxDv => phy1_RxDv,
phy1_RxErr => phy1_RxErr,
phy1_SMIClk => phy1_SMIClk,
phy1_SMIDat_I => phy1_SMIDat_I,
phy1_SMIDat_O => phy1_SMIDat_O,
phy1_SMIDat_T => phy1_SMIDat_T,
phy1_TxDat => phy1_TxDat,
phy1_TxEn => phy1_TxEn,
phy1_link => phy1_link,
phyMii0_RxClk => phyMii0_RxClk,
phyMii0_RxDat => phyMii0_RxDat,
phyMii0_RxDv => phyMii0_RxDv,
phyMii0_RxEr => phyMii0_RxEr,
phyMii0_TxClk => phyMii0_TxClk,
phyMii0_TxDat => phyMii0_TxDat,
phyMii0_TxEn => phyMii0_TxEn,
phyMii0_TxEr => phyMii0_TxEr,
phyMii1_RxClk => phyMii1_RxClk,
phyMii1_RxDat => phyMii1_RxDat,
phyMii1_RxDv => phyMii1_RxDv,
phyMii1_RxEr => phyMii1_RxEr,
phyMii1_TxClk => phyMii1_TxClk,
phyMii1_TxDat => phyMii1_TxDat,
phyMii1_TxEn => phyMii1_TxEn,
phyMii1_TxEr => phyMii1_TxEr,
phy_Rst_n => phy_Rst_n,
phy_SMIClk => phy_SMIClk,
phy_SMIDat_I => phy_SMIDat_I,
phy_SMIDat_O => phy_SMIDat_O,
phy_SMIDat_T => phy_SMIDat_T,
pio_operational => pio_operational,
pio_pconfig => pio_pconfig,
pio_portInLatch => pio_portInLatch,
pio_portOutValid => pio_portOutValid,
pio_portio_I => pio_portio_I,
pio_portio_O => pio_portio_O,
pio_portio_T => pio_portio_T,
pkt_clk => pkt_clk,
rst => rst,
rstAp => rstAp,
rstPcp => rstPcp,
smp_address => smp_address,
smp_byteenable => smp_byteenable,
smp_read => smp_read,
smp_readdata => smp_readdata,
smp_waitrequest => smp_waitrequest,
smp_write => smp_write,
smp_writedata => smp_writedata,
spi_clk => spi_clk,
spi_miso => spi_miso,
spi_mosi => spi_mosi,
spi_sel_n => spi_sel_n,
tcp_address => tcp_address,
tcp_byteenable => tcp_byteenable,
tcp_chipselect => tcp_chipselect,
tcp_irq => tcp_irq_s,
tcp_read => tcp_read,
tcp_readdata => tcp_readdata,
tcp_waitrequest => tcp_waitrequest,
tcp_write => tcp_write,
tcp_writedata => tcp_writedata
);
rst <= Bus2MAC_REG_Reset or Bus2MAC_CMP_Reset or MAC_DMA_RST or Bus2MAC_PKT_Reset;
Bus2MAC_REG_RNW_n <= not(Bus2MAC_REG_RNW);
---- Power , ground assignment ----
VCC <= VCC_CONSTANT;
GND <= GND_CONSTANT;
MAC_REG2Bus_Error <= GND;
---- Terminal assignment ----
-- Output\buffer terminals
mac_irq <= mac_irq_s;
tcp_irq <= tcp_irq_s;
---- Generate statements ----
genMacDmaPlbBurst : if C_DMA_EN = TRUE generate
begin
MAC_DMA_PLB_BURST_MASTER : plbv46_master_burst
generic map (
C_FAMILY => C_FAMILY,
C_INHIBIT_CC_BLE_INCLUSION => 1,
C_MPLB_AWIDTH => C_MAC_DMA_PLB_AWIDTH,
C_MPLB_DWIDTH => C_MAC_DMA_PLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH => C_MAC_DMA_PLB_NATIVE_DWIDTH,
C_MPLB_SMALLEST_SLAVE => 32
)
port map(
Bus2IP_MstRd_d => Bus2MAC_DMA_MstRd_d( C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0 ),
Bus2IP_MstRd_eof_n => Bus2MAC_DMA_MstRd_eof_n,
Bus2IP_MstRd_rem => Bus2MAC_DMA_MstRd_rem( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
Bus2IP_MstRd_sof_n => Bus2MAC_DMA_MstRd_sof_n,
Bus2IP_MstRd_src_dsc_n => Bus2MAC_DMA_MstRd_src_dsc_n,
Bus2IP_MstRd_src_rdy_n => Bus2MAC_DMA_MstRd_src_rdy_n,
Bus2IP_MstWr_dst_dsc_n => Bus2MAC_DMA_MstWr_dst_dsc_n,
Bus2IP_MstWr_dst_rdy_n => Bus2MAC_DMA_MstWr_dst_rdy_n,
Bus2IP_Mst_CmdAck => Bus2MAC_DMA_Mst_CmdAck,
Bus2IP_Mst_Cmd_Timeout => Bus2MAC_DMA_Mst_Cmd_Timeout,
Bus2IP_Mst_Cmplt => Bus2MAC_DMA_Mst_Cmplt,
Bus2IP_Mst_Error => Bus2MAC_DMA_Mst_Error,
Bus2IP_Mst_Rearbitrate => Bus2MAC_DMA_Mst_Rearbitrate,
IP2Bus_MstRd_Req => MAC_DMA2Bus_MstRd_Req,
IP2Bus_MstRd_dst_dsc_n => MAC_DMA2Bus_MstRd_dst_dsc_n,
IP2Bus_MstRd_dst_rdy_n => MAC_DMA2Bus_MstRd_dst_rdy_n,
IP2Bus_MstWr_Req => MAC_DMA2Bus_MstWr_Req,
IP2Bus_MstWr_d => MAC_DMA2Bus_MstWr_d( C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0 ),
IP2Bus_MstWr_eof_n => MAC_DMA2Bus_MstWr_eof_n,
IP2Bus_MstWr_rem => MAC_DMA2Bus_MstWr_rem( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
IP2Bus_MstWr_sof_n => MAC_DMA2Bus_MstWr_sof_n,
IP2Bus_MstWr_src_dsc_n => MAC_DMA2Bus_MstWr_src_dsc_n,
IP2Bus_MstWr_src_rdy_n => MAC_DMA2Bus_MstWr_src_rdy_n,
IP2Bus_Mst_Addr => MAC_DMA2Bus_Mst_Addr( 0 to C_MAC_DMA_PLB_AWIDTH-1 ),
IP2Bus_Mst_BE => MAC_DMA2Bus_Mst_BE( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
IP2Bus_Mst_Length => MAC_DMA2Bus_Mst_Length,
IP2Bus_Mst_Lock => MAC_DMA2Bus_Mst_Lock,
IP2Bus_Mst_Reset => MAC_DMA2Bus_Mst_Reset,
IP2Bus_Mst_Type => MAC_DMA2Bus_Mst_Type,
MD_Error => MAC_DMA_error,
MPLB_Clk => MAC_DMA_Clk,
MPLB_Rst => MAC_DMA_Rst,
M_ABus => MAC_DMA_ABus,
M_BE => MAC_DMA_BE( 0 to (C_MAC_DMA_PLB_DWIDTH/8)-1 ),
M_MSize => MAC_DMA_MSize,
M_RNW => MAC_DMA_RNW,
M_TAttribute => MAC_DMA_TAttribute,
M_UABus => MAC_DMA_UABus,
M_abort => MAC_DMA_abort,
M_busLock => MAC_DMA_busLock,
M_lockErr => MAC_DMA_lockErr,
M_priority => MAC_DMA_priority,
M_rdBurst => MAC_DMA_rdBurst,
M_request => MAC_DMA_request,
M_size => MAC_DMA_size,
M_type => MAC_DMA_type,
M_wrBurst => MAC_DMA_wrBurst,
M_wrDBus => MAC_DMA_wrDBus( 0 to C_MAC_DMA_PLB_DWIDTH-1 ),
PLB_MAddrAck => MAC_DMA_MAddrAck,
PLB_MBusy => MAC_DMA_MBusy,
PLB_MIRQ => MAC_DMA_MIRQ,
PLB_MRdBTerm => MAC_DMA_MRdBTerm,
PLB_MRdDAck => MAC_DMA_MRdDAck,
PLB_MRdDBus => MAC_DMA_MRdDBus( 0 to C_MAC_DMA_PLB_DWIDTH-1 ),
PLB_MRdErr => MAC_DMA_MRdErr,
PLB_MRdWdAddr => MAC_DMA_MRdWdAddr,
PLB_MRearbitrate => MAC_DMA_MRearbitrate,
PLB_MSSize => MAC_DMA_MSSize,
PLB_MTimeout => MAC_DMA_MTimeout,
PLB_MWrBTerm => MAC_DMA_MWrBTerm,
PLB_MWrDAck => MAC_DMA_MWrDAck,
PLB_MWrErr => MAC_DMA_MWrErr
);
end generate genMacDmaPlbBurst;
oddr2_0 : if not C_INSTANCE_ODDR2 generate
begin
phy0_clk <= clk50;
phy1_clk <= clk50;
end generate oddr2_0;
oddr2_1 : if C_INSTANCE_ODDR2 generate
begin
U4 : ODDR2
port map(
C0 => clk50,
C1 => NET118078,
CE => VCC,
D0 => VCC,
D1 => GND,
Q => phy0_clk,
R => GND,
S => GND
);
NET118078 <= not(clk50);
U6 : ODDR2
port map(
C0 => clk50,
C1 => NET118214,
CE => VCC,
D0 => VCC,
D1 => GND,
Q => phy1_clk,
R => GND,
S => GND
);
NET118214 <= not(clk50);
end generate oddr2_1;
genThePlbMaster : if C_DMA_EN = TRUE generate
begin
THE_IPIF_MASTER_HANDLER : ipif_master_handler
generic map (
dma_highadr_g => m_address'high,
gen_rx_fifo_g => not C_RX_INT_PKT,
gen_tx_fifo_g => not C_TX_INT_PKT,
m_burstcount_width_g => C_M_BURSTCOUNT_WIDTH
)
port map(
Bus2MAC_DMA_MstRd_d => Bus2MAC_DMA_MstRd_d_s( C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0 ),
Bus2MAC_DMA_MstRd_eof_n => Bus2MAC_DMA_MstRd_eof_n,
Bus2MAC_DMA_MstRd_rem => Bus2MAC_DMA_MstRd_rem( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
Bus2MAC_DMA_MstRd_sof_n => Bus2MAC_DMA_MstRd_sof_n,
Bus2MAC_DMA_MstRd_src_dsc_n => Bus2MAC_DMA_MstRd_src_dsc_n,
Bus2MAC_DMA_MstRd_src_rdy_n => Bus2MAC_DMA_MstRd_src_rdy_n,
Bus2MAC_DMA_MstWr_dst_dsc_n => Bus2MAC_DMA_MstWr_dst_dsc_n,
Bus2MAC_DMA_MstWr_dst_rdy_n => Bus2MAC_DMA_MstWr_dst_rdy_n,
Bus2MAC_DMA_Mst_CmdAck => Bus2MAC_DMA_Mst_CmdAck,
Bus2MAC_DMA_Mst_Cmd_Timeout => Bus2MAC_DMA_Mst_Cmd_Timeout,
Bus2MAC_DMA_Mst_Cmplt => Bus2MAC_DMA_Mst_Cmplt,
Bus2MAC_DMA_Mst_Error => Bus2MAC_DMA_Mst_Error,
Bus2MAC_DMA_Mst_Rearbitrate => Bus2MAC_DMA_Mst_Rearbitrate,
MAC_DMA2Bus_MstRd_Req => MAC_DMA2Bus_MstRd_Req,
MAC_DMA2Bus_MstRd_dst_dsc_n => MAC_DMA2Bus_MstRd_dst_dsc_n,
MAC_DMA2Bus_MstRd_dst_rdy_n => MAC_DMA2Bus_MstRd_dst_rdy_n,
MAC_DMA2Bus_MstWr_Req => MAC_DMA2Bus_MstWr_Req,
MAC_DMA2Bus_MstWr_d => MAC_DMA2Bus_MstWr_d_s( C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0 ),
MAC_DMA2Bus_MstWr_eof_n => MAC_DMA2Bus_MstWr_eof_n,
MAC_DMA2Bus_MstWr_rem => MAC_DMA2Bus_MstWr_rem( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
MAC_DMA2Bus_MstWr_sof_n => MAC_DMA2Bus_MstWr_sof_n,
MAC_DMA2Bus_MstWr_src_dsc_n => MAC_DMA2Bus_MstWr_src_dsc_n,
MAC_DMA2Bus_MstWr_src_rdy_n => MAC_DMA2Bus_MstWr_src_rdy_n,
MAC_DMA2Bus_Mst_Addr => MAC_DMA2Bus_Mst_Addr( 0 to C_MAC_DMA_PLB_AWIDTH-1 ),
MAC_DMA2Bus_Mst_BE => MAC_DMA2Bus_Mst_BE( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
MAC_DMA2Bus_Mst_Length => MAC_DMA2Bus_Mst_Length,
MAC_DMA2Bus_Mst_Lock => MAC_DMA2Bus_Mst_Lock,
MAC_DMA2Bus_Mst_Reset => MAC_DMA2Bus_Mst_Reset,
MAC_DMA2Bus_Mst_Type => MAC_DMA2Bus_Mst_Type,
MAC_DMA_CLK => MAC_DMA_CLK,
MAC_DMA_Rst => MAC_DMA_Rst,
m_address => m_address( 31 downto 0 ),
m_burstcount => m_burstcount( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_burstcounter => m_burstcounter( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_byteenable => m_byteenable,
m_clk => m_clk,
m_read => m_read,
m_readdata => m_readdata,
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
m_writedata => m_writedata
);
Bus2MAC_DMA_MstRd_d_s <= Bus2MAC_DMA_MstRd_d(7 downto 0) & Bus2MAC_DMA_MstRd_d(15 downto 8) &
Bus2MAC_DMA_MstRd_d(23 downto 16) & Bus2MAC_DMA_MstRd_d(31 downto 24);
MAC_DMA2Bus_MstWr_d <= MAC_DMA2Bus_MstWr_d_s(7 downto 0) & MAC_DMA2Bus_MstWr_d_s(15 downto 8) &
MAC_DMA2Bus_MstWr_d_s(23 downto 16) & MAC_DMA2Bus_MstWr_d_s(31 downto 24);
end generate genThePlbMaster;
genMacPktPLbSingleSlave : if C_PKT_BUF_EN generate
begin
MAC_PKT_PLB_SINGLE_SLAVE : plbv46_slave_single
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_MAC_PKT_BASE,C_MAC_PKT_HIGH),
C_ARD_NUM_CE_ARRAY => (0 => 1),
C_BUS2CORE_CLK_RATIO => 1,
C_FAMILY => C_FAMILY,
C_INCLUDE_DPHASE_TIMER => 0,
C_SIPIF_DWIDTH => C_MAC_PKT_PLB_DWIDTH,
C_SPLB_AWIDTH => C_MAC_PKT_PLB_AWIDTH,
C_SPLB_DWIDTH => C_MAC_PKT_PLB_DWIDTH,
C_SPLB_MID_WIDTH => C_MAC_PKT_PLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_MAC_PKT_PLB_NUM_MASTERS,
C_SPLB_P2P => C_MAC_PKT_PLB_P2P
)
port map(
Bus2IP_Addr => Bus2MAC_PKT_Addr( C_MAC_PKT_PLB_AWIDTH-1 downto 0 ),
Bus2IP_BE => Bus2MAC_PKT_BE( (C_MAC_PKT_PLB_DWIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2MAC_PKT_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2MAC_PKT_Clk,
Bus2IP_Data => Bus2MAC_PKT_Data( C_MAC_PKT_PLB_DWIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2MAC_PKT_RNW,
Bus2IP_Reset => Bus2MAC_PKT_Reset,
IP2Bus_Data => MAC_PKT2Bus_Data( C_MAC_PKT_PLB_DWIDTH-1 downto 0 ),
IP2Bus_Error => MAC_PKT2Bus_Error,
IP2Bus_RdAck => MAC_PKT2Bus_RdAck,
IP2Bus_WrAck => MAC_PKT2Bus_WrAck,
PLB_ABus => MAC_PKT_ABus,
PLB_BE => MAC_PKT_BE( 0 to (C_MAC_PKT_PLB_DWIDTH/8)-1 ),
PLB_MSize => MAC_PKT_MSize,
PLB_PAValid => MAC_PKT_PAValid,
PLB_RNW => MAC_PKT_RNW,
PLB_SAValid => MAC_PKT_SAValid,
PLB_TAttribute => MAC_PKT_TAttribute,
PLB_UABus => MAC_PKT_UABus,
PLB_abort => MAC_PKT_abort,
PLB_busLock => MAC_PKT_busLock,
PLB_lockErr => MAC_PKT_lockErr,
PLB_masterID => MAC_PKT_masterID( 0 to C_MAC_PKT_PLB_MID_WIDTH-1 ),
PLB_rdBurst => MAC_PKT_rdBurst,
PLB_rdPendPri => MAC_PKT_rdPendPri,
PLB_rdPendReq => MAC_PKT_rdPendReq,
PLB_rdPrim => MAC_PKT_rdPrim,
PLB_reqPri => MAC_PKT_reqPri,
PLB_size => MAC_PKT_size,
PLB_type => MAC_PKT_type,
PLB_wrBurst => MAC_PKT_wrBurst,
PLB_wrDBus => MAC_PKT_wrDBus( 0 to C_MAC_PKT_PLB_DWIDTH-1 ),
PLB_wrPendPri => MAC_PKT_wrPendPri,
PLB_wrPendReq => MAC_PKT_wrPendReq,
PLB_wrPrim => MAC_PKT_wrPrim,
SPLB_Clk => MAC_PKT_Clk,
SPLB_Rst => MAC_PKT_Rst,
Sl_MBusy => MAC_PKT_MBusy( 0 to C_MAC_PKT_NUM_MASTERS-1 ),
Sl_MIRQ => MAC_PKT_MIRQ( 0 to C_MAC_PKT_NUM_MASTERS-1 ),
Sl_MRdErr => MAC_PKT_MRdErr( 0 to C_MAC_PKT_NUM_MASTERS-1 ),
Sl_MWrErr => MAC_PKT_MWrErr( 0 to C_MAC_PKT_NUM_MASTERS-1 ),
Sl_SSize => MAC_PKT_SSize,
Sl_addrAck => MAC_PKT_addrAck,
Sl_rdBTerm => MAC_PKT_rdBTerm,
Sl_rdComp => MAC_PKT_rdComp,
Sl_rdDAck => MAC_PKT_rdDAck,
Sl_rdDBus => MAC_PKT_rdDBus( 0 to C_MAC_PKT_PLB_DWIDTH-1 ),
Sl_rdWdAddr => MAC_PKT_rdWdAddr,
Sl_rearbitrate => MAC_PKT_rearbitrate,
Sl_wait => MAC_PKT_wait,
Sl_wrBTerm => MAC_PKT_wrBTerm,
Sl_wrComp => MAC_PKT_wrComp,
Sl_wrDAck => MAC_PKT_wrDAck
);
end generate genMacPktPLbSingleSlave;
genPdiPcp : if (C_GEN_PDI) generate
begin
PDI_PCP_PLB_SINGLE_SLAVE : plbv46_slave_single
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_PDI_PCP_BASE,C_PDI_PCP_HIGH),
C_ARD_NUM_CE_ARRAY => (0 => 1),
C_BUS2CORE_CLK_RATIO => 1,
C_FAMILY => C_FAMILY,
C_INCLUDE_DPHASE_TIMER => 0,
C_SIPIF_DWIDTH => C_PDI_PCP_PLB_DWIDTH,
C_SPLB_AWIDTH => C_PDI_PCP_PLB_AWIDTH,
C_SPLB_DWIDTH => C_PDI_PCP_PLB_DWIDTH,
C_SPLB_MID_WIDTH => C_PDI_PCP_PLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_PDI_PCP_PLB_NUM_MASTERS,
C_SPLB_P2P => C_PDI_PCP_PLB_P2P
)
port map(
Bus2IP_Addr => Bus2PDI_PCP_Addr( C_PDI_PCP_PLB_AWIDTH-1 downto 0 ),
Bus2IP_BE => Bus2PDI_PCP_BE( (C_PDI_PCP_PLB_DWIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2PDI_PCP_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2PDI_PCP_Clk,
Bus2IP_Data => Bus2PDI_PCP_Data( C_PDI_PCP_PLB_DWIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2PDI_PCP_RNW,
Bus2IP_Reset => Bus2PDI_PCP_Reset,
IP2Bus_Data => PDI_PCP2Bus_Data( C_PDI_PCP_PLB_DWIDTH-1 downto 0 ),
IP2Bus_Error => PDI_PCP2Bus_Error,
IP2Bus_RdAck => PDI_PCP2Bus_RdAck,
IP2Bus_WrAck => PDI_PCP2Bus_WrAck,
PLB_ABus => PDI_PCP_ABus,
PLB_BE => PDI_PCP_BE( 0 to (C_PDI_PCP_PLB_DWIDTH/8)-1 ),
PLB_MSize => PDI_PCP_MSize,
PLB_PAValid => PDI_PCP_PAValid,
PLB_RNW => PDI_PCP_RNW,
PLB_SAValid => PDI_PCP_SAValid,
PLB_TAttribute => PDI_PCP_TAttribute,
PLB_UABus => PDI_PCP_UABus,
PLB_abort => PDI_PCP_abort,
PLB_busLock => PDI_PCP_busLock,
PLB_lockErr => PDI_PCP_lockErr,
PLB_masterID => PDI_PCP_masterID( 0 to C_PDI_PCP_PLB_MID_WIDTH-1 ),
PLB_rdBurst => PDI_PCP_rdBurst,
PLB_rdPendPri => PDI_PCP_rdPendPri,
PLB_rdPendReq => PDI_PCP_rdPendReq,
PLB_rdPrim => PDI_PCP_rdPrim,
PLB_reqPri => PDI_PCP_reqPri,
PLB_size => PDI_PCP_size,
PLB_type => PDI_PCP_type,
PLB_wrBurst => PDI_PCP_wrBurst,
PLB_wrDBus => PDI_PCP_wrDBus( 0 to C_PDI_PCP_PLB_DWIDTH-1 ),
PLB_wrPendPri => PDI_PCP_wrPendPri,
PLB_wrPendReq => PDI_PCP_wrPendReq,
PLB_wrPrim => PDI_PCP_wrPrim,
SPLB_Clk => PDI_PCP_Clk,
SPLB_Rst => PDI_PCP_Rst,
Sl_MBusy => PDI_PCP_MBusy( 0 to C_PDI_PCP_NUM_MASTERS-1 ),
Sl_MIRQ => PDI_PCP_MIRQ( 0 to C_PDI_PCP_NUM_MASTERS-1 ),
Sl_MRdErr => PDI_PCP_MRdErr( 0 to C_PDI_PCP_NUM_MASTERS-1 ),
Sl_MWrErr => PDI_PCP_MWrErr( 0 to C_PDI_PCP_NUM_MASTERS-1 ),
Sl_SSize => PDI_PCP_SSize,
Sl_addrAck => PDI_PCP_addrAck,
Sl_rdBTerm => PDI_PCP_rdBTerm,
Sl_rdComp => PDI_PCP_rdComp,
Sl_rdDAck => PDI_PCP_rdDAck,
Sl_rdDBus => PDI_PCP_rdDBus( 0 to C_PDI_PCP_PLB_DWIDTH-1 ),
Sl_rdWdAddr => PDI_PCP_rdWdAddr,
Sl_rearbitrate => PDI_PCP_rearbitrate,
Sl_wait => PDI_PCP_wait,
Sl_wrBTerm => PDI_PCP_wrBTerm,
Sl_wrComp => PDI_PCP_wrComp,
Sl_wrDAck => PDI_PCP_wrDAck
);
end generate genPdiPcp;
genPcpPdiLink : if C_GEN_PDI generate
begin
--pdi_pcp assignments
clkPcp <= Bus2PDI_PCP_Clk;
rstPcp <= Bus2PDI_PCP_Reset;
--pcp_writedata <= Bus2PDI_PCP_Data;
pcp_writedata <= Bus2PDI_PCP_Data(7 downto 0) & Bus2PDI_PCP_Data(15 downto 8) & Bus2PDI_PCP_Data(23 downto 16) & Bus2PDI_PCP_Data(31 downto 24);
--pcp_writedata <= Bus2PDI_PCP_Data(15 downto 0) & Bus2PDI_PCP_Data(31 downto 16) when Bus2PDI_PCP_BE = "1100" or Bus2PDI_PCP_BE = "0011" else
-- Bus2PDI_PCP_Data(15 downto 8) & Bus2PDI_PCP_Data(7 downto 0) & Bus2PDI_PCP_Data(31 downto 24) & Bus2PDI_PCP_Data(23 downto 16) when Bus2PDI_PCP_BE = "1000" or Bus2PDI_PCP_BE = "0100" or Bus2PDI_PCP_BE = "0010" or Bus2PDI_PCP_BE = "0001" else
-- Bus2PDI_PCP_Data;
pcp_read <= Bus2PDI_PCP_RNW;
pcp_write <= not Bus2PDI_PCP_RNW;
pcp_chipselect <= Bus2PDI_PCP_CS(0);
--pcp_byteenable <= Bus2PDI_PCP_BE;
pcp_byteenable <= Bus2PDI_PCP_BE(0) & Bus2PDI_PCP_BE(1) & Bus2PDI_PCP_BE(2) & Bus2PDI_PCP_BE(3);
pcp_address <= Bus2PDI_PCP_Addr(14 downto 2);
--PDI_PCP2Bus_Data <= pcp_readdata;
PDI_PCP2Bus_Data <= pcp_readdata(7 downto 0) & pcp_readdata(15 downto 8) & pcp_readdata(23 downto 16) & pcp_readdata(31 downto 24);
PDI_PCP2Bus_RdAck <= pcp_chipselect and pcp_read and not pcp_waitrequest;
PDI_PCP2Bus_WrAck <= pcp_chipselect and pcp_write and not pcp_waitrequest;
PDI_PCP2Bus_Error <= '0';
end generate genPcpPdiLink;
genPdiAp : if (C_GEN_PLB_BUS_IF) generate
begin
PDI_AP_PLB_SINGLE_SLAVE : plbv46_slave_single
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_PDI_AP_BASE,C_PDI_AP_HIGH),
C_ARD_NUM_CE_ARRAY => (0 => 1),
C_BUS2CORE_CLK_RATIO => 1,
C_FAMILY => C_FAMILY,
C_INCLUDE_DPHASE_TIMER => 0,
C_SIPIF_DWIDTH => C_PDI_AP_PLB_DWIDTH,
C_SPLB_AWIDTH => C_PDI_AP_PLB_AWIDTH,
C_SPLB_DWIDTH => C_PDI_AP_PLB_DWIDTH,
C_SPLB_MID_WIDTH => C_PDI_AP_PLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_PDI_AP_PLB_NUM_MASTERS,
C_SPLB_P2P => C_PDI_AP_PLB_P2P
)
port map(
Bus2IP_Addr => Bus2PDI_AP_Addr( C_PDI_AP_PLB_AWIDTH-1 downto 0 ),
Bus2IP_BE => Bus2PDI_AP_BE( (C_PDI_AP_PLB_DWIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2PDI_AP_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2PDI_AP_Clk,
Bus2IP_Data => Bus2PDI_AP_Data( C_PDI_AP_PLB_DWIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2PDI_AP_RNW,
Bus2IP_Reset => Bus2PDI_AP_Reset,
IP2Bus_Data => PDI_AP2Bus_Data( C_PDI_AP_PLB_DWIDTH-1 downto 0 ),
IP2Bus_Error => PDI_AP2Bus_Error,
IP2Bus_RdAck => PDI_AP2Bus_RdAck,
IP2Bus_WrAck => PDI_AP2Bus_WrAck,
PLB_ABus => PDI_AP_ABus,
PLB_BE => PDI_AP_BE( 0 to (C_PDI_AP_PLB_DWIDTH/8)-1 ),
PLB_MSize => PDI_AP_MSize,
PLB_PAValid => PDI_AP_PAValid,
PLB_RNW => PDI_AP_RNW,
PLB_SAValid => PDI_AP_SAValid,
PLB_TAttribute => PDI_AP_TAttribute,
PLB_UABus => PDI_AP_UABus,
PLB_abort => PDI_AP_abort,
PLB_busLock => PDI_AP_busLock,
PLB_lockErr => PDI_AP_lockErr,
PLB_masterID => PDI_AP_masterID( 0 to C_PDI_AP_PLB_MID_WIDTH-1 ),
PLB_rdBurst => PDI_AP_rdBurst,
PLB_rdPendPri => PDI_AP_rdPendPri,
PLB_rdPendReq => PDI_AP_rdPendReq,
PLB_rdPrim => PDI_AP_rdPrim,
PLB_reqPri => PDI_AP_reqPri,
PLB_size => PDI_AP_size,
PLB_type => PDI_AP_type,
PLB_wrBurst => PDI_AP_wrBurst,
PLB_wrDBus => PDI_AP_wrDBus( 0 to C_PDI_AP_PLB_DWIDTH-1 ),
PLB_wrPendPri => PDI_AP_wrPendPri,
PLB_wrPendReq => PDI_AP_wrPendReq,
PLB_wrPrim => PDI_AP_wrPrim,
SPLB_Clk => PDI_AP_Clk,
SPLB_Rst => PDI_AP_Rst,
Sl_MBusy => PDI_AP_MBusy( 0 to C_PDI_AP_PLB_NUM_MASTERS-1 ),
Sl_MIRQ => PDI_AP_MIRQ( 0 to C_PDI_AP_PLB_NUM_MASTERS-1 ),
Sl_MRdErr => PDI_AP_MRdErr( 0 to C_PDI_AP_PLB_NUM_MASTERS-1 ),
Sl_MWrErr => PDI_AP_MWrErr( 0 to C_PDI_AP_PLB_NUM_MASTERS-1 ),
Sl_SSize => PDI_AP_SSize,
Sl_addrAck => PDI_AP_addrAck,
Sl_rdBTerm => PDI_AP_rdBTerm,
Sl_rdComp => PDI_AP_rdComp,
Sl_rdDAck => PDI_AP_rdDAck,
Sl_rdDBus => PDI_AP_rdDBus( 0 to C_PDI_AP_PLB_DWIDTH-1 ),
Sl_rdWdAddr => PDI_AP_rdWdAddr,
Sl_rearbitrate => PDI_AP_rearbitrate,
Sl_wait => PDI_AP_wait,
Sl_wrBTerm => PDI_AP_wrBTerm,
Sl_wrComp => PDI_AP_wrComp,
Sl_wrDAck => PDI_AP_wrDAck
);
end generate genPdiAp;
genApPdiLink : if C_GEN_PDI generate
begin
--ap_pcp assignments
clkAp <= Bus2PDI_AP_Clk;
rstAp <= Bus2PDI_AP_Reset;
--ap_writedata <= Bus2PDI_AP_Data;
ap_writedata <= Bus2PDI_AP_Data(7 downto 0) & Bus2PDI_AP_Data(15 downto 8) & Bus2PDI_AP_Data(23 downto 16) & Bus2PDI_AP_Data(31 downto 24);
ap_read <= Bus2PDI_AP_RNW;
ap_write <= not Bus2PDI_AP_RNW;
ap_chipselect <= Bus2PDI_AP_CS(0);
--ap_byteenable <= Bus2PDI_AP_BE;
ap_byteenable <= Bus2PDI_AP_BE(0) & Bus2PDI_AP_BE(1) & Bus2PDI_AP_BE(2) & Bus2PDI_AP_BE(3);
ap_address <= Bus2PDI_AP_Addr(14 downto 2);
--PDI_AP2Bus_Data <= ap_readdata;
PDI_AP2Bus_Data <= ap_readdata(7 downto 0) & ap_readdata(15 downto 8) & ap_readdata(23 downto 16) & ap_readdata(31 downto 24);
PDI_AP2Bus_RdAck <= ap_chipselect and ap_read and not ap_waitrequest;
PDI_AP2Bus_WrAck <= ap_chipselect and ap_write and not ap_waitrequest;
PDI_AP2Bus_Error <= '0';
end generate genApPdiLink;
genSimpleIoSignals : if C_GEN_SIMPLE_IO generate
begin
--SMP_PCP assignments
clkPcp <= Bus2SMP_PCP_Clk;
rstPcp <= Bus2SMP_PCP_Reset;
--smp_writedata <= Bus2SMP_PCP_Data;
smp_writedata <= Bus2SMP_PCP_Data(7 downto 0) & Bus2SMP_PCP_Data(15 downto 8) & Bus2SMP_PCP_Data(23 downto 16) & Bus2SMP_PCP_Data(31 downto 24);
smp_read <= Bus2SMP_PCP_RNW and Bus2SMP_PCP_CS(0);
smp_write <= not Bus2SMP_PCP_RNW and Bus2SMP_PCP_CS(0);
smp_chipselect <= Bus2SMP_PCP_CS(0);
--smp_byteenable <= Bus2SMP_PCP_BE;
smp_byteenable <= Bus2SMP_PCP_BE(0) & Bus2SMP_PCP_BE(1) & Bus2SMP_PCP_BE(2) & Bus2SMP_PCP_BE(3);
smp_address <= Bus2SMP_PCP_Addr(2);
--SMP_PCP2Bus_Data <= smp_readdata;
SMP_PCP2Bus_Data <= smp_readdata(7 downto 0) & smp_readdata(15 downto 8) & smp_readdata(23 downto 16) & smp_readdata(31 downto 24);
SMP_PCP2Bus_RdAck <= smp_chipselect and smp_read and not smp_waitrequest;
SMP_PCP2Bus_WrAck <= smp_chipselect and smp_write and not smp_waitrequest;
SMP_PCP2Bus_Error <= '0';
end generate genSimpleIoSignals;
genSmpIo : if (C_GEN_SIMPLE_IO) generate
begin
SMP_IO_PLB_SINGLE_SLAVE : plbv46_slave_single
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_SMP_PCP_BASE,C_SMP_PCP_HIGH),
C_ARD_NUM_CE_ARRAY => (0 => 1),
C_BUS2CORE_CLK_RATIO => 1,
C_FAMILY => C_FAMILY,
C_INCLUDE_DPHASE_TIMER => 0,
C_SIPIF_DWIDTH => C_SMP_PCP_PLB_DWIDTH,
C_SPLB_AWIDTH => C_SMP_PCP_PLB_AWIDTH,
C_SPLB_DWIDTH => C_SMP_PCP_PLB_DWIDTH,
C_SPLB_MID_WIDTH => C_SMP_PCP_PLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SMP_PCP_PLB_NUM_MASTERS,
C_SPLB_P2P => C_SMP_PCP_PLB_P2P
)
port map(
Bus2IP_Addr => Bus2SMP_PCP_Addr( C_SMP_PCP_PLB_AWIDTH-1 downto 0 ),
Bus2IP_BE => Bus2SMP_PCP_BE( (C_SMP_PCP_PLB_DWIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2SMP_PCP_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2SMP_PCP_Clk,
Bus2IP_Data => Bus2SMP_PCP_Data( C_SMP_PCP_PLB_DWIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2SMP_PCP_RNW,
Bus2IP_Reset => Bus2SMP_PCP_Reset,
IP2Bus_Data => SMP_PCP2Bus_Data( C_SMP_PCP_PLB_DWIDTH-1 downto 0 ),
IP2Bus_Error => SMP_PCP2Bus_Error,
IP2Bus_RdAck => SMP_PCP2Bus_RdAck,
IP2Bus_WrAck => SMP_PCP2Bus_WrAck,
PLB_ABus => SMP_PCP_ABus,
PLB_BE => SMP_PCP_BE( 0 to (C_SMP_PCP_PLB_DWIDTH/8)-1 ),
PLB_MSize => SMP_PCP_MSize,
PLB_PAValid => SMP_PCP_PAValid,
PLB_RNW => SMP_PCP_RNW,
PLB_SAValid => SMP_PCP_SAValid,
PLB_TAttribute => SMP_PCP_TAttribute,
PLB_UABus => SMP_PCP_UABus,
PLB_abort => SMP_PCP_abort,
PLB_busLock => SMP_PCP_busLock,
PLB_lockErr => SMP_PCP_lockErr,
PLB_masterID => SMP_PCP_masterID( 0 to C_SMP_PCP_PLB_MID_WIDTH-1 ),
PLB_rdBurst => SMP_PCP_rdBurst,
PLB_rdPendPri => SMP_PCP_rdPendPri,
PLB_rdPendReq => SMP_PCP_rdPendReq,
PLB_rdPrim => SMP_PCP_rdPrim,
PLB_reqPri => SMP_PCP_reqPri,
PLB_size => SMP_PCP_size,
PLB_type => SMP_PCP_type,
PLB_wrBurst => SMP_PCP_wrBurst,
PLB_wrDBus => SMP_PCP_wrDBus( 0 to C_SMP_PCP_PLB_DWIDTH-1 ),
PLB_wrPendPri => SMP_PCP_wrPendPri,
PLB_wrPendReq => SMP_PCP_wrPendReq,
PLB_wrPrim => SMP_PCP_wrPrim,
SPLB_Clk => SMP_PCP_Clk,
SPLB_Rst => SMP_PCP_Rst,
Sl_MBusy => SMP_PCP_MBusy( 0 to C_SMP_PCP_PLB_NUM_MASTERS-1 ),
Sl_MIRQ => SMP_PCP_MIRQ( 0 to C_SMP_PCP_PLB_NUM_MASTERS-1 ),
Sl_MRdErr => SMP_PCP_MRdErr( 0 to C_SMP_PCP_PLB_NUM_MASTERS-1 ),
Sl_MWrErr => SMP_PCP_MWrErr( 0 to C_SMP_PCP_PLB_NUM_MASTERS-1 ),
Sl_SSize => SMP_PCP_SSize,
Sl_addrAck => SMP_PCP_addrAck,
Sl_rdBTerm => SMP_PCP_rdBTerm,
Sl_rdComp => SMP_PCP_rdComp,
Sl_rdDAck => SMP_PCP_rdDAck,
Sl_rdDBus => SMP_PCP_rdDBus( 0 to C_SMP_PCP_PLB_DWIDTH-1 ),
Sl_rdWdAddr => SMP_PCP_rdWdAddr,
Sl_rearbitrate => SMP_PCP_rearbitrate,
Sl_wait => SMP_PCP_wait,
Sl_wrBTerm => SMP_PCP_wrBTerm,
Sl_wrComp => SMP_PCP_wrComp,
Sl_wrDAck => SMP_PCP_wrDAck
);
end generate genSmpIo;
end struct;
|
-------------------------------------------------------------------------------
-- Entity : plb_powerlink
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This is the toplevel file for using the POWERLINK IP-Core
-- with Xilinx PLB V4.6.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
use work.global.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
-- standard libraries declarations
library UNISIM;
use UNISIM.vcomponents.all;
-- pragma synthesis_off
library IEEE;
use IEEE.vital_timing.all;
-- pragma synthesis_on
-- other libraries declarations
library PLBV46_MASTER_BURST_V1_01_A;
library PLBV46_SLAVE_SINGLE_V1_01_A;
entity plb_powerlink is
generic(
C_FAMILY : string := "spartan6";
-- general
C_GEN_PDI : boolean := false;
C_GEN_PAR_IF : boolean := false;
C_GEN_SPI_IF : boolean := false;
C_GEN_PLB_BUS_IF : boolean := false;
C_GEN_SIMPLE_IO : boolean := false;
-- openMAC
C_MAC_PKT_SIZE : integer := 1024;
C_MAC_PKT_SIZE_LOG2 : integer := 10;
C_MAC_RX_BUFFERS : integer := 16;
C_USE_RMII : boolean := false;
C_TX_INT_PKT : boolean := false;
C_RX_INT_PKT : boolean := false;
C_USE_2ND_PHY : boolean := true;
C_NUM_SMI : integer range 1 to 2 := 2;
C_MAC_GEN_SECOND_TIMER : boolean := false;
--pdi
C_PDI_REV : integer := 0;
C_PCP_SYS_ID : integer := 0;
C_PDI_GEN_ASYNC_BUF_0 : boolean := true;
C_PDI_ASYNC_BUF_0 : integer := 50;
C_PDI_GEN_ASYNC_BUF_1 : boolean := true;
C_PDI_ASYNC_BUF_1 : integer := 50;
C_PDI_GEN_LED : boolean := false;
C_PDI_GEN_TIME_SYNC : boolean := true;
C_PDI_GEN_EVENT : boolean := true;
--global pdi and mac
C_NUM_RPDO : integer := 3;
C_RPDO_0_BUF_SIZE : integer := 100;
C_RPDO_1_BUF_SIZE : integer := 100;
C_RPDO_2_BUF_SIZE : integer := 100;
C_NUM_TPDO : integer := 1;
C_TPDO_BUF_SIZE : integer := 100;
-- pap
C_PAP_DATA_WIDTH : integer := 16;
--C_PAP_BIG_END : boolean := false;
C_PAP_LOW_ACT : boolean := false;
-- spi
C_SPI_CPOL : boolean := false;
C_SPI_CPHA : boolean := false;
--C_SPI_BIG_END : boolean := false;
-- simpleIO
C_PIO_VAL_LENGTH : integer := 50;
-- debug
C_OBSERVER_ENABLE : boolean := false;
-- clock stabiliser
C_INSTANCE_ODDR2 : boolean := false;
-- sync IRQ pulse width
C_USE_PULSE_2nd_CMP_TIMER : boolean := true;
C_PULSE_WIDTH_2nd_CMP_TIMER : integer := 9;
-- PDI AP PLB Slave
C_PDI_AP_BASEADDR : std_logic_vector := X"00000000";
C_PDI_AP_HIGHADDR : std_logic_vector := X"000FFFFF";
C_PDI_AP_NUM_MASTERS : INTEGER := 1;
C_PDI_AP_PLB_AWIDTH : INTEGER := 32;
C_PDI_AP_PLB_DWIDTH : INTEGER := 32;
C_PDI_AP_PLB_MID_WIDTH : INTEGER := 1;
C_PDI_AP_PLB_P2P : INTEGER := 0;
C_PDI_AP_PLB_NUM_MASTERS : INTEGER := 1;
C_PDI_AP_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_PDI_AP_PLB_SUPPORT_BURSTS : INTEGER := 0;
-- PDI AP PLB Slave
C_SMP_PCP_BASEADDR : std_logic_vector := X"00000000";
C_SMP_PCP_HIGHADDR : std_logic_vector := X"000FFFFF";
C_SMP_PCP_NUM_MASTERS : INTEGER := 1;
C_SMP_PCP_PLB_AWIDTH : INTEGER := 32;
C_SMP_PCP_PLB_DWIDTH : INTEGER := 32;
C_SMP_PCP_PLB_MID_WIDTH : INTEGER := 1;
C_SMP_PCP_PLB_P2P : INTEGER := 0;
C_SMP_PCP_PLB_NUM_MASTERS : INTEGER := 1;
C_SMP_PCP_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_SMP_PCP_PLB_SUPPORT_BURSTS : INTEGER := 0;
-- PDI PCP PLB Slave
C_PDI_PCP_BASEADDR : std_logic_vector := X"00000000";
C_PDI_PCP_HIGHADDR : std_logic_vector := X"000FFFFF";
C_PDI_PCP_NUM_MASTERS : INTEGER := 1;
C_PDI_PCP_PLB_AWIDTH : INTEGER := 32;
C_PDI_PCP_PLB_DWIDTH : INTEGER := 32;
C_PDI_PCP_PLB_MID_WIDTH : INTEGER := 1;
C_PDI_PCP_PLB_P2P : INTEGER := 0;
C_PDI_PCP_PLB_NUM_MASTERS : INTEGER := 1;
C_PDI_PCP_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_PDI_PCP_PLB_SUPPORT_BURSTS : INTEGER := 0;
-- openMAC CMP PLB Slave
C_MAC_PKT_BASEADDR : std_logic_vector := X"00000000";
C_MAC_PKT_HIGHADDR : std_logic_vector := X"000FFFFF";
C_MAC_PKT_NUM_MASTERS : INTEGER := 1;
C_MAC_PKT_PLB_AWIDTH : INTEGER := 32;
C_MAC_PKT_PLB_DWIDTH : INTEGER := 32;
C_MAC_PKT_PLB_MID_WIDTH : INTEGER := 1;
C_MAC_PKT_PLB_P2P : INTEGER := 0;
C_MAC_PKT_PLB_NUM_MASTERS : INTEGER := 1;
C_MAC_PKT_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_MAC_PKT_PLB_SUPPORT_BURSTS : INTEGER := 0;
-- openMAC DMA PLB Master
C_MAC_DMA_PLB_AWIDTH : INTEGER := 32;
C_MAC_DMA_PLB_DWIDTH : INTEGER := 32;
C_MAC_DMA_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_MAC_DMA_BURST_SIZE_RX : INTEGER := 8; --in bytes
C_MAC_DMA_BURST_SIZE_TX : INTEGER := 8; --in bytes
C_MAC_DMA_FIFO_SIZE_RX : INTEGER := 32; --in bytes
C_MAC_DMA_FIFO_SIZE_TX : INTEGER := 32; --in bytes
-- openMAC REG PLB Slave
C_MAC_REG_BASEADDR : std_logic_vector := X"00000000";
C_MAC_REG_HIGHADDR : std_logic_vector := X"0000FFFF";
C_MAC_CMP_BASEADDR : std_logic_vector := X"00000000";
C_MAC_CMP_HIGHADDR : std_logic_vector := X"0000FFFF";
C_MAC_REG_BUS2CORE_CLK_RATIO : integer := 2;
C_MAC_REG_NUM_MASTERS : INTEGER := 1;
C_MAC_REG_PLB_AWIDTH : INTEGER := 32;
C_MAC_REG_PLB_DWIDTH : INTEGER := 32;
C_MAC_REG_PLB_MID_WIDTH : INTEGER := 1;
C_MAC_REG_PLB_P2P : INTEGER := 0;
C_MAC_REG_PLB_NUM_MASTERS : INTEGER := 1;
C_MAC_REG_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_MAC_REG_PLB_SUPPORT_BURSTS : INTEGER := 0
);
port(
MAC_DMA_Clk : in std_logic;
MAC_DMA_MAddrAck : in std_logic;
MAC_DMA_MBusy : in std_logic;
MAC_DMA_MIRQ : in std_logic;
MAC_DMA_MRdBTerm : in std_logic;
MAC_DMA_MRdDAck : in std_logic;
MAC_DMA_MRdErr : in std_logic;
MAC_DMA_MRearbitrate : in std_logic;
MAC_DMA_MTimeout : in std_logic;
MAC_DMA_MWrBTerm : in std_logic;
MAC_DMA_MWrDAck : in std_logic;
MAC_DMA_MWrErr : in std_logic;
MAC_DMA_Rst : in std_logic;
MAC_PKT_Clk : in std_logic;
MAC_PKT_PAValid : in std_logic;
MAC_PKT_RNW : in std_logic;
MAC_PKT_Rst : in std_logic;
MAC_PKT_SAValid : in std_logic;
MAC_PKT_abort : in std_logic;
MAC_PKT_busLock : in std_logic;
MAC_PKT_lockErr : in std_logic;
MAC_PKT_rdBurst : in std_logic;
MAC_PKT_rdPendReq : in std_logic;
MAC_PKT_rdPrim : in std_logic;
MAC_PKT_wrBurst : in std_logic;
MAC_PKT_wrPendReq : in std_logic;
MAC_PKT_wrPrim : in std_logic;
MAC_REG_Clk : in std_logic;
MAC_REG_PAValid : in std_logic;
MAC_REG_RNW : in std_logic;
MAC_REG_Rst : in std_logic;
MAC_REG_SAValid : in std_logic;
MAC_REG_abort : in std_logic;
MAC_REG_busLock : in std_logic;
MAC_REG_lockErr : in std_logic;
MAC_REG_rdBurst : in std_logic;
MAC_REG_rdPendReq : in std_logic;
MAC_REG_rdPrim : in std_logic;
MAC_REG_wrBurst : in std_logic;
MAC_REG_wrPendReq : in std_logic;
MAC_REG_wrPrim : in std_logic;
PDI_AP_Clk : in std_logic;
PDI_AP_PAValid : in std_logic;
PDI_AP_RNW : in std_logic;
PDI_AP_Rst : in std_logic;
PDI_AP_SAValid : in std_logic;
PDI_AP_abort : in std_logic;
PDI_AP_busLock : in std_logic;
PDI_AP_lockErr : in std_logic;
PDI_AP_rdBurst : in std_logic;
PDI_AP_rdPendReq : in std_logic;
PDI_AP_rdPrim : in std_logic;
PDI_AP_wrBurst : in std_logic;
PDI_AP_wrPendReq : in std_logic;
PDI_AP_wrPrim : in std_logic;
PDI_PCP_Clk : in std_logic;
PDI_PCP_PAValid : in std_logic;
PDI_PCP_RNW : in std_logic;
PDI_PCP_Rst : in std_logic;
PDI_PCP_SAValid : in std_logic;
PDI_PCP_abort : in std_logic;
PDI_PCP_busLock : in std_logic;
PDI_PCP_lockErr : in std_logic;
PDI_PCP_rdBurst : in std_logic;
PDI_PCP_rdPendReq : in std_logic;
PDI_PCP_rdPrim : in std_logic;
PDI_PCP_wrBurst : in std_logic;
PDI_PCP_wrPendReq : in std_logic;
PDI_PCP_wrPrim : in std_logic;
SMP_PCP_Clk : in std_logic;
SMP_PCP_PAValid : in std_logic;
SMP_PCP_RNW : in std_logic;
SMP_PCP_Rst : in std_logic;
SMP_PCP_SAValid : in std_logic;
SMP_PCP_abort : in std_logic;
SMP_PCP_busLock : in std_logic;
SMP_PCP_lockErr : in std_logic;
SMP_PCP_rdBurst : in std_logic;
SMP_PCP_rdPendReq : in std_logic;
SMP_PCP_rdPrim : in std_logic;
SMP_PCP_wrBurst : in std_logic;
SMP_PCP_wrPendReq : in std_logic;
SMP_PCP_wrPrim : in std_logic;
clk100 : in std_logic;
clk50 : in std_logic;
pap_cs : in std_logic;
pap_cs_n : in std_logic;
pap_rd : in std_logic;
pap_rd_n : in std_logic;
pap_wr : in std_logic;
pap_wr_n : in std_logic;
phy0_RxDv : in std_logic;
phy0_RxErr : in std_logic;
phy0_SMIDat_I : in std_logic;
phy0_link : in std_logic;
phy1_RxDv : in std_logic;
phy1_RxErr : in std_logic;
phy1_SMIDat_I : in std_logic;
phy1_link : in std_logic;
phyMii0_RxClk : in std_logic;
phyMii0_RxDv : in std_logic;
phyMii0_RxEr : in std_logic;
phyMii0_TxClk : in std_logic;
phyMii1_RxClk : in std_logic;
phyMii1_RxDv : in std_logic;
phyMii1_RxEr : in std_logic;
phyMii1_TxClk : in std_logic;
phy_SMIDat_I : in std_logic;
spi_clk : in std_logic;
spi_mosi : in std_logic;
spi_sel_n : in std_logic;
MAC_DMA_MRdDBus : in std_logic_vector(0 to C_MAC_DMA_PLB_DWIDTH-1);
MAC_DMA_MRdWdAddr : in std_logic_vector(0 to 3);
MAC_DMA_MSSize : in std_logic_vector(0 to 1);
MAC_PKT_ABus : in std_logic_vector(0 to 31);
MAC_PKT_BE : in std_logic_vector(0 to (C_MAC_PKT_PLB_DWIDTH/8)-1);
MAC_PKT_MSize : in std_logic_vector(0 to 1);
MAC_PKT_TAttribute : in std_logic_vector(0 to 15);
MAC_PKT_UABus : in std_logic_vector(0 to 31);
MAC_PKT_masterID : in std_logic_vector(0 to C_MAC_PKT_PLB_MID_WIDTH-1);
MAC_PKT_rdPendPri : in std_logic_vector(0 to 1);
MAC_PKT_reqPri : in std_logic_vector(0 to 1);
MAC_PKT_size : in std_logic_vector(0 to 3);
MAC_PKT_type : in std_logic_vector(0 to 2);
MAC_PKT_wrDBus : in std_logic_vector(0 to C_MAC_PKT_PLB_DWIDTH-1);
MAC_PKT_wrPendPri : in std_logic_vector(0 to 1);
MAC_REG_ABus : in std_logic_vector(0 to 31);
MAC_REG_BE : in std_logic_vector(0 to (C_MAC_REG_PLB_DWIDTH / 8) - 1);
MAC_REG_MSize : in std_logic_vector(0 to 1);
MAC_REG_TAttribute : in std_logic_vector(0 to 15);
MAC_REG_UABus : in std_logic_vector(0 to 31);
MAC_REG_masterID : in std_logic_vector(0 to C_MAC_REG_PLB_MID_WIDTH - 1);
MAC_REG_rdPendPri : in std_logic_vector(0 to 1);
MAC_REG_reqPri : in std_logic_vector(0 to 1);
MAC_REG_size : in std_logic_vector(0 to 3);
MAC_REG_type : in std_logic_vector(0 to 2);
MAC_REG_wrDBus : in std_logic_vector(0 to C_MAC_REG_PLB_DWIDTH - 1);
MAC_REG_wrPendPri : in std_logic_vector(0 to 1);
PDI_AP_ABus : in std_logic_vector(0 to 31);
PDI_AP_BE : in std_logic_vector(0 to (C_PDI_AP_PLB_DWIDTH/8)-1);
PDI_AP_MSize : in std_logic_vector(0 to 1);
PDI_AP_TAttribute : in std_logic_vector(0 to 15);
PDI_AP_UABus : in std_logic_vector(0 to 31);
PDI_AP_masterID : in std_logic_vector(0 to C_PDI_AP_PLB_MID_WIDTH-1);
PDI_AP_rdPendPri : in std_logic_vector(0 to 1);
PDI_AP_reqPri : in std_logic_vector(0 to 1);
PDI_AP_size : in std_logic_vector(0 to 3);
PDI_AP_type : in std_logic_vector(0 to 2);
PDI_AP_wrDBus : in std_logic_vector(0 to C_PDI_AP_PLB_DWIDTH-1);
PDI_AP_wrPendPri : in std_logic_vector(0 to 1);
PDI_PCP_ABus : in std_logic_vector(0 to 31);
PDI_PCP_BE : in std_logic_vector(0 to (C_PDI_PCP_PLB_DWIDTH/8)-1);
PDI_PCP_MSize : in std_logic_vector(0 to 1);
PDI_PCP_TAttribute : in std_logic_vector(0 to 15);
PDI_PCP_UABus : in std_logic_vector(0 to 31);
PDI_PCP_masterID : in std_logic_vector(0 to C_PDI_PCP_PLB_MID_WIDTH-1);
PDI_PCP_rdPendPri : in std_logic_vector(0 to 1);
PDI_PCP_reqPri : in std_logic_vector(0 to 1);
PDI_PCP_size : in std_logic_vector(0 to 3);
PDI_PCP_type : in std_logic_vector(0 to 2);
PDI_PCP_wrDBus : in std_logic_vector(0 to C_PDI_PCP_PLB_DWIDTH-1);
PDI_PCP_wrPendPri : in std_logic_vector(0 to 1);
SMP_PCP_ABus : in std_logic_vector(0 to 31);
SMP_PCP_BE : in std_logic_vector(0 to (C_SMP_PCP_PLB_DWIDTH/8)-1);
SMP_PCP_MSize : in std_logic_vector(0 to 1);
SMP_PCP_TAttribute : in std_logic_vector(0 to 15);
SMP_PCP_UABus : in std_logic_vector(0 to 31);
SMP_PCP_masterID : in std_logic_vector(0 to C_SMP_PCP_PLB_MID_WIDTH-1);
SMP_PCP_rdPendPri : in std_logic_vector(0 to 1);
SMP_PCP_reqPri : in std_logic_vector(0 to 1);
SMP_PCP_size : in std_logic_vector(0 to 3);
SMP_PCP_type : in std_logic_vector(0 to 2);
SMP_PCP_wrDBus : in std_logic_vector(0 to C_SMP_PCP_PLB_DWIDTH-1);
SMP_PCP_wrPendPri : in std_logic_vector(0 to 1);
pap_addr : in std_logic_vector(15 downto 0);
pap_be : in std_logic_vector(C_PAP_DATA_WIDTH/8-1 downto 0);
pap_be_n : in std_logic_vector(C_PAP_DATA_WIDTH/8-1 downto 0);
pap_data_I : in std_logic_vector(C_PAP_DATA_WIDTH-1 downto 0);
pap_gpio_I : in std_logic_vector(1 downto 0);
phy0_RxDat : in std_logic_vector(1 downto 0);
phy1_RxDat : in std_logic_vector(1 downto 0);
phyMii0_RxDat : in std_logic_vector(3 downto 0);
phyMii1_RxDat : in std_logic_vector(3 downto 0);
pio_pconfig : in std_logic_vector(3 downto 0);
pio_portInLatch : in std_logic_vector(3 downto 0);
pio_portio_I : in std_logic_vector(31 downto 0);
MAC_DMA_RNW : out std_logic;
MAC_DMA_abort : out std_logic;
MAC_DMA_busLock : out std_logic;
MAC_DMA_error : out std_logic;
MAC_DMA_lockErr : out std_logic;
MAC_DMA_rdBurst : out std_logic;
MAC_DMA_request : out std_logic;
MAC_DMA_wrBurst : out std_logic;
MAC_PKT_addrAck : out std_logic;
MAC_PKT_rdBTerm : out std_logic;
MAC_PKT_rdComp : out std_logic;
MAC_PKT_rdDAck : out std_logic;
MAC_PKT_rearbitrate : out std_logic;
MAC_PKT_wait : out std_logic;
MAC_PKT_wrBTerm : out std_logic;
MAC_PKT_wrComp : out std_logic;
MAC_PKT_wrDAck : out std_logic;
MAC_REG_addrAck : out std_logic;
MAC_REG_rdBTerm : out std_logic;
MAC_REG_rdComp : out std_logic;
MAC_REG_rdDAck : out std_logic;
MAC_REG_rearbitrate : out std_logic;
MAC_REG_wait : out std_logic;
MAC_REG_wrBTerm : out std_logic;
MAC_REG_wrComp : out std_logic;
MAC_REG_wrDAck : out std_logic;
PDI_AP_addrAck : out std_logic;
PDI_AP_rdBTerm : out std_logic;
PDI_AP_rdComp : out std_logic;
PDI_AP_rdDAck : out std_logic;
PDI_AP_rearbitrate : out std_logic;
PDI_AP_wait : out std_logic;
PDI_AP_wrBTerm : out std_logic;
PDI_AP_wrComp : out std_logic;
PDI_AP_wrDAck : out std_logic;
PDI_PCP_addrAck : out std_logic;
PDI_PCP_rdBTerm : out std_logic;
PDI_PCP_rdComp : out std_logic;
PDI_PCP_rdDAck : out std_logic;
PDI_PCP_rearbitrate : out std_logic;
PDI_PCP_wait : out std_logic;
PDI_PCP_wrBTerm : out std_logic;
PDI_PCP_wrComp : out std_logic;
PDI_PCP_wrDAck : out std_logic;
SMP_PCP_addrAck : out std_logic;
SMP_PCP_rdBTerm : out std_logic;
SMP_PCP_rdComp : out std_logic;
SMP_PCP_rdDAck : out std_logic;
SMP_PCP_rearbitrate : out std_logic;
SMP_PCP_wait : out std_logic;
SMP_PCP_wrBTerm : out std_logic;
SMP_PCP_wrComp : out std_logic;
SMP_PCP_wrDAck : out std_logic;
ap_asyncIrq : out std_logic;
ap_asyncIrq_n : out std_logic;
ap_syncIrq : out std_logic;
ap_syncIrq_n : out std_logic;
led_error : out std_logic;
led_status : out std_logic;
mac_irq : out std_logic;
pap_ack : out std_logic;
pap_ack_n : out std_logic;
pap_data_T : out std_logic;
phy0_Rst_n : out std_logic;
phy0_SMIClk : out std_logic;
phy0_SMIDat_O : out std_logic;
phy0_SMIDat_T : out std_logic;
phy0_TxEn : out std_logic;
phy0_clk : out std_logic;
phy1_Rst_n : out std_logic;
phy1_SMIClk : out std_logic;
phy1_SMIDat_O : out std_logic;
phy1_SMIDat_T : out std_logic;
phy1_TxEn : out std_logic;
phy1_clk : out std_logic;
phyMii0_TxEn : out std_logic;
phyMii0_TxEr : out std_logic;
phyMii1_TxEn : out std_logic;
phyMii1_TxEr : out std_logic;
phy_Rst_n : out std_logic;
phy_SMIClk : out std_logic;
phy_SMIDat_O : out std_logic;
phy_SMIDat_T : out std_logic;
pio_operational : out std_logic;
spi_miso : out std_logic;
tcp_irq : out std_logic;
MAC_DMA_ABus : out std_logic_vector(0 to 31);
MAC_DMA_BE : out std_logic_vector(0 to (C_MAC_DMA_PLB_DWIDTH/8)-1);
MAC_DMA_MSize : out std_logic_vector(0 to 1);
MAC_DMA_TAttribute : out std_logic_vector(0 to 15);
MAC_DMA_UABus : out std_logic_vector(0 to 31);
MAC_DMA_priority : out std_logic_vector(0 to 1);
MAC_DMA_size : out std_logic_vector(0 to 3);
MAC_DMA_type : out std_logic_vector(0 to 2);
MAC_DMA_wrDBus : out std_logic_vector(0 to C_MAC_DMA_PLB_DWIDTH-1);
MAC_PKT_MBusy : out std_logic_vector(0 to C_MAC_PKT_NUM_MASTERS-1);
MAC_PKT_MIRQ : out std_logic_vector(0 to C_MAC_PKT_NUM_MASTERS-1);
MAC_PKT_MRdErr : out std_logic_vector(0 to C_MAC_PKT_NUM_MASTERS-1);
MAC_PKT_MWrErr : out std_logic_vector(0 to C_MAC_PKT_NUM_MASTERS-1);
MAC_PKT_SSize : out std_logic_vector(0 to 1);
MAC_PKT_rdDBus : out std_logic_vector(0 to C_MAC_PKT_PLB_DWIDTH-1);
MAC_PKT_rdWdAddr : out std_logic_vector(0 to 3);
MAC_REG_MBusy : out std_logic_vector(0 to C_MAC_REG_NUM_MASTERS-1);
MAC_REG_MIRQ : out std_logic_vector(0 to C_MAC_REG_NUM_MASTERS-1);
MAC_REG_MRdErr : out std_logic_vector(0 to C_MAC_REG_NUM_MASTERS-1);
MAC_REG_MWrErr : out std_logic_vector(0 to C_MAC_REG_NUM_MASTERS-1);
MAC_REG_SSize : out std_logic_vector(0 to 1);
MAC_REG_rdDBus : out std_logic_vector(0 to C_MAC_REG_PLB_DWIDTH-1);
MAC_REG_rdWdAddr : out std_logic_vector(0 to 3);
PDI_AP_MBusy : out std_logic_vector(0 to C_PDI_AP_PLB_NUM_MASTERS-1);
PDI_AP_MIRQ : out std_logic_vector(0 to C_PDI_AP_PLB_NUM_MASTERS-1);
PDI_AP_MRdErr : out std_logic_vector(0 to C_PDI_AP_PLB_NUM_MASTERS-1);
PDI_AP_MWrErr : out std_logic_vector(0 to C_PDI_AP_PLB_NUM_MASTERS-1);
PDI_AP_SSize : out std_logic_vector(0 to 1);
PDI_AP_rdDBus : out std_logic_vector(0 to C_PDI_AP_PLB_DWIDTH-1);
PDI_AP_rdWdAddr : out std_logic_vector(0 to 3);
PDI_PCP_MBusy : out std_logic_vector(0 to C_PDI_PCP_NUM_MASTERS-1);
PDI_PCP_MIRQ : out std_logic_vector(0 to C_PDI_PCP_NUM_MASTERS-1);
PDI_PCP_MRdErr : out std_logic_vector(0 to C_PDI_PCP_NUM_MASTERS-1);
PDI_PCP_MWrErr : out std_logic_vector(0 to C_PDI_PCP_NUM_MASTERS-1);
PDI_PCP_SSize : out std_logic_vector(0 to 1);
PDI_PCP_rdDBus : out std_logic_vector(0 to C_PDI_PCP_PLB_DWIDTH-1);
PDI_PCP_rdWdAddr : out std_logic_vector(0 to 3);
SMP_PCP_MBusy : out std_logic_vector(0 to C_SMP_PCP_PLB_NUM_MASTERS-1);
SMP_PCP_MIRQ : out std_logic_vector(0 to C_SMP_PCP_PLB_NUM_MASTERS-1);
SMP_PCP_MRdErr : out std_logic_vector(0 to C_SMP_PCP_PLB_NUM_MASTERS-1);
SMP_PCP_MWrErr : out std_logic_vector(0 to C_SMP_PCP_PLB_NUM_MASTERS-1);
SMP_PCP_SSize : out std_logic_vector(0 to 1);
SMP_PCP_rdDBus : out std_logic_vector(0 to C_SMP_PCP_PLB_DWIDTH-1);
SMP_PCP_rdWdAddr : out std_logic_vector(0 to 3);
led_gpo : out std_logic_vector(7 downto 0);
led_opt : out std_logic_vector(1 downto 0);
led_phyAct : out std_logic_vector(1 downto 0);
led_phyLink : out std_logic_vector(1 downto 0);
pap_data_O : out std_logic_vector(C_PAP_DATA_WIDTH-1 downto 0);
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0);
phy0_TxDat : out std_logic_vector(1 downto 0);
phy1_TxDat : out std_logic_vector(1 downto 0);
phyMii0_TxDat : out std_logic_vector(3 downto 0);
phyMii1_TxDat : out std_logic_vector(3 downto 0);
pio_portOutValid : out std_logic_vector(3 downto 0);
pio_portio_O : out std_logic_vector(31 downto 0);
pio_portio_T : out std_logic_vector(31 downto 0);
test_port : out std_logic_vector(255 downto 0) := (others => '0')
);
-- Entity declarations --
-- Click here to add additional declarations --
attribute SIGIS : string;
-- Entity attributes --
attribute SIGIS of MAC_DMA_Clk : signal is "Clk";
attribute SIGIS of MAC_DMA_Rst : signal is "Rst";
attribute SIGIS of MAC_PKT_Clk : signal is "Clk";
attribute SIGIS of MAC_PKT_Rst : signal is "Rst";
attribute SIGIS of MAC_REG_Clk : signal is "Clk";
attribute SIGIS of MAC_REG_Rst : signal is "Rst";
attribute SIGIS of PDI_AP_Clk : signal is "Clk";
attribute SIGIS of PDI_AP_Rst : signal is "Rst";
attribute SIGIS of PDI_PCP_Clk : signal is "Clk";
attribute SIGIS of PDI_PCP_Rst : signal is "Rst";
attribute SIGIS of SMP_PCP_Clk : signal is "Clk";
attribute SIGIS of SMP_PCP_Rst : signal is "Rst";
attribute SIGIS of clk100 : signal is "Clk";
attribute SIGIS of clk50 : signal is "Clk";
attribute SIGIS of phy0_clk : signal is "Clk";
attribute SIGIS of phy1_clk : signal is "Clk";
end plb_powerlink;
architecture struct of plb_powerlink is
---- Architecture declarations -----
function get_max( a, b : integer) return integer is
begin
if a < b then
return b;
else
return a;
end if;
end get_max;
---- Component declarations -----
component ipif_master_handler
generic(
C_MAC_DMA_IPIF_AWIDTH : integer := 32;
C_MAC_DMA_IPIF_NATIVE_DWIDTH : integer := 32;
dma_highadr_g : integer := 31;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burstcount_width_g : integer := 4
);
port (
Bus2MAC_DMA_MstRd_d : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0);
Bus2MAC_DMA_MstRd_eof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_rem : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
Bus2MAC_DMA_MstRd_sof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_dsc_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_rdy_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_dsc_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_rdy_n : in std_logic := '1';
Bus2MAC_DMA_Mst_CmdAck : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmd_Timeout : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmplt : in std_logic := '0';
Bus2MAC_DMA_Mst_Error : in std_logic := '0';
Bus2MAC_DMA_Mst_Rearbitrate : in std_logic := '0';
MAC_DMA_CLK : in std_logic;
MAC_DMA_Rst : in std_logic;
m_address : in std_logic_vector(dma_highadr_g downto 0);
m_burstcount : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : in std_logic_vector(3 downto 0);
m_read : in std_logic := '0';
m_write : in std_logic := '0';
m_writedata : in std_logic_vector(31 downto 0);
MAC_DMA2Bus_MstRd_Req : out std_logic := '0';
MAC_DMA2Bus_MstRd_dst_dsc_n : out std_logic := '1';
MAC_DMA2Bus_MstRd_dst_rdy_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_Req : out std_logic := '0';
MAC_DMA2Bus_MstWr_d : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0);
MAC_DMA2Bus_MstWr_eof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_rem : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_MstWr_sof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_dsc_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_rdy_n : out std_logic := '1';
MAC_DMA2Bus_Mst_Addr : out std_logic_vector(C_MAC_DMA_IPIF_AWIDTH-1 downto 0);
MAC_DMA2Bus_Mst_BE : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_Mst_Length : out std_logic_vector(11 downto 0);
MAC_DMA2Bus_Mst_Lock : out std_logic := '0';
MAC_DMA2Bus_Mst_Reset : out std_logic := '0';
MAC_DMA2Bus_Mst_Type : out std_logic := '0';
m_clk : out std_logic;
m_readdata : out std_logic_vector(31 downto 0);
m_readdatavalid : out std_logic := '0';
m_waitrequest : out std_logic := '1'
);
end component;
component openMAC_16to32conv
generic(
bus_address_width : integer := 10;
gEndian : string := "little"
);
port (
bus_address : in std_logic_vector(bus_address_width-1 downto 0);
bus_byteenable : in std_logic_vector(3 downto 0);
bus_read : in std_logic;
bus_select : in std_logic;
bus_write : in std_logic;
bus_writedata : in std_logic_vector(31 downto 0);
clk : in std_logic;
rst : in std_logic;
s_readdata : in std_logic_vector(15 downto 0);
s_waitrequest : in std_logic;
bus_ack_rd : out std_logic;
bus_ack_wr : out std_logic;
bus_readdata : out std_logic_vector(31 downto 0);
s_address : out std_logic_vector(bus_address_width-1 downto 0);
s_byteenable : out std_logic_vector(1 downto 0);
s_chipselect : out std_logic;
s_read : out std_logic;
s_write : out std_logic;
s_writedata : out std_logic_vector(15 downto 0)
);
end component;
component powerlink
generic(
Simulate : integer := 0;
endian_g : string := "little";
gNumSmi : integer range 1 to 2 := 2;
genABuf1_g : integer := 1;
genABuf2_g : integer := 1;
genEvent_g : integer := 0;
genInternalAp_g : integer := 1;
genIoBuf_g : integer := 1;
genLedGadget_g : integer := 0;
genOnePdiClkDomain_g : integer := 0;
genPdi_g : integer := 1;
genSimpleIO_g : integer := 0;
genSmiIO : integer := 1;
genSpiAp_g : integer := 0;
genTimeSync_g : integer := 0;
gen_dma_observer_g : integer := 1;
iAsyBuf1Size_g : integer := 100;
iAsyBuf2Size_g : integer := 100;
iBufSizeLOG2_g : integer := 10;
iBufSize_g : integer := 1024;
iPdiRev_g : integer := 21930;
iRpdo0BufSize_g : integer := 100;
iRpdo1BufSize_g : integer := 100;
iRpdo2BufSize_g : integer := 100;
iRpdos_g : integer := 3;
iTpdoBufSize_g : integer := 100;
iTpdos_g : integer := 1;
m_burstcount_const_g : integer := 1;
m_burstcount_width_g : integer := 4;
m_data_width_g : integer := 16;
m_rx_burst_size_g : integer := 16;
m_rx_fifo_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_tx_fifo_size_g : integer := 16;
papBigEnd_g : integer := 0;
papDataWidth_g : integer := 8;
papLowAct_g : integer := 0;
pcpSysId : integer := 1;
pioValLen_g : integer := 50;
spiBigEnd_g : integer := 0;
spiCPHA_g : integer := 0;
spiCPOL_g : integer := 0;
use2ndCmpTimer_g : integer := 1;
usePulse2ndCmpTimer_g : integer := 1;
pulseWidth2ndCmpTimer_g : integer := 9;
use2ndPhy_g : integer := 1;
useIntPacketBuf_g : integer := 1;
useRmii_g : integer := 1;
useRxIntPacketBuf_g : integer := 1
);
port (
ap_address : in std_logic_vector(12 downto 0);
ap_byteenable : in std_logic_vector(3 downto 0);
ap_chipselect : in std_logic;
ap_read : in std_logic;
ap_write : in std_logic;
ap_writedata : in std_logic_vector(31 downto 0);
clk50 : in std_logic;
clkAp : in std_logic;
clkEth : in std_logic;
clkPcp : in std_logic;
m_clk : in std_logic;
m_readdata : in std_logic_vector(m_data_width_g-1 downto 0) := (others => '0');
m_readdatavalid : in std_logic := '0';
m_waitrequest : in std_logic;
mac_address : in std_logic_vector(11 downto 0);
mac_byteenable : in std_logic_vector(1 downto 0);
mac_chipselect : in std_logic;
mac_read : in std_logic;
mac_write : in std_logic;
mac_writedata : in std_logic_vector(15 downto 0);
mbf_address : in std_logic_vector(ibufsizelog2_g-3 downto 0);
mbf_byteenable : in std_logic_vector(3 downto 0);
mbf_chipselect : in std_logic;
mbf_read : in std_logic;
mbf_write : in std_logic;
mbf_writedata : in std_logic_vector(31 downto 0);
pap_addr : in std_logic_vector(15 downto 0);
pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_be_n : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_cs : in std_logic;
pap_cs_n : in std_logic;
pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0');
pap_rd : in std_logic;
pap_rd_n : in std_logic;
pap_wr : in std_logic;
pap_wr_n : in std_logic;
pcp_address : in std_logic_vector(12 downto 0);
pcp_byteenable : in std_logic_vector(3 downto 0);
pcp_chipselect : in std_logic;
pcp_read : in std_logic;
pcp_write : in std_logic;
pcp_writedata : in std_logic_vector(31 downto 0);
phy0_RxDat : in std_logic_vector(1 downto 0);
phy0_RxDv : in std_logic;
phy0_RxErr : in std_logic;
phy0_SMIDat_I : in std_logic := '1';
phy0_link : in std_logic := '0';
phy1_RxDat : in std_logic_vector(1 downto 0) := (others => '0');
phy1_RxDv : in std_logic;
phy1_RxErr : in std_logic;
phy1_SMIDat_I : in std_logic := '1';
phy1_link : in std_logic := '0';
phyMii0_RxClk : in std_logic;
phyMii0_RxDat : in std_logic_vector(3 downto 0) := (others => '0');
phyMii0_RxDv : in std_logic;
phyMii0_RxEr : in std_logic;
phyMii0_TxClk : in std_logic;
phyMii1_RxClk : in std_logic;
phyMii1_RxDat : in std_logic_vector(3 downto 0) := (others => '0');
phyMii1_RxDv : in std_logic;
phyMii1_RxEr : in std_logic;
phyMii1_TxClk : in std_logic;
phy_SMIDat_I : in std_logic := '1';
pio_pconfig : in std_logic_vector(3 downto 0);
pio_portInLatch : in std_logic_vector(3 downto 0);
pio_portio_I : in std_logic_vector(31 downto 0) := (others => '0');
pkt_clk : in std_logic;
rst : in std_logic;
rstAp : in std_logic;
rstPcp : in std_logic;
smp_address : in std_logic;
smp_byteenable : in std_logic_vector(3 downto 0);
smp_read : in std_logic;
smp_write : in std_logic;
smp_writedata : in std_logic_vector(31 downto 0);
spi_clk : in std_logic;
spi_mosi : in std_logic;
spi_sel_n : in std_logic;
tcp_address : in std_logic_vector(1 downto 0);
tcp_byteenable : in std_logic_vector(3 downto 0);
tcp_chipselect : in std_logic;
tcp_read : in std_logic;
tcp_write : in std_logic;
tcp_writedata : in std_logic_vector(31 downto 0);
ap_asyncIrq : out std_logic := '0';
ap_asyncIrq_n : out std_logic := '1';
ap_irq : out std_logic := '0';
ap_irq_n : out std_logic := '1';
ap_readdata : out std_logic_vector(31 downto 0) := (others => '0');
ap_syncIrq : out std_logic := '0';
ap_syncIrq_n : out std_logic := '1';
ap_waitrequest : out std_logic;
led_error : out std_logic := '0';
led_gpo : out std_logic_vector(7 downto 0) := (others => '0');
led_opt : out std_logic_vector(1 downto 0) := (others => '0');
led_phyAct : out std_logic_vector(1 downto 0) := (others => '0');
led_phyLink : out std_logic_vector(1 downto 0) := (others => '0');
led_status : out std_logic := '0';
m_address : out std_logic_vector(31 downto 0) := (others => '0');
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(m_data_width_g/8-1 downto 0) := (others => '0');
m_read : out std_logic := '0';
m_write : out std_logic := '0';
m_writedata : out std_logic_vector(m_data_width_g-1 downto 0) := (others => '0');
mac_irq : out std_logic := '0';
mac_readdata : out std_logic_vector(15 downto 0) := (others => '0');
mac_waitrequest : out std_logic;
mbf_readdata : out std_logic_vector(31 downto 0) := (others => '0');
mbf_waitrequest : out std_logic;
pap_ack : out std_logic := '0';
pap_ack_n : out std_logic := '1';
pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_T : out std_logic;
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0);
pcp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
pcp_waitrequest : out std_logic;
phy0_Rst_n : out std_logic := '1';
phy0_SMIClk : out std_logic := '0';
phy0_SMIDat_O : out std_logic;
phy0_SMIDat_T : out std_logic;
phy0_TxDat : out std_logic_vector(1 downto 0) := (others => '0');
phy0_TxEn : out std_logic := '0';
phy1_Rst_n : out std_logic := '1';
phy1_SMIClk : out std_logic := '0';
phy1_SMIDat_O : out std_logic;
phy1_SMIDat_T : out std_logic;
phy1_TxDat : out std_logic_vector(1 downto 0) := (others => '0');
phy1_TxEn : out std_logic := '0';
phyMii0_TxDat : out std_logic_vector(3 downto 0) := (others => '0');
phyMii0_TxEn : out std_logic := '0';
phyMii0_TxEr : out std_logic := '0';
phyMii1_TxDat : out std_logic_vector(3 downto 0) := (others => '0');
phyMii1_TxEn : out std_logic := '0';
phyMii1_TxEr : out std_logic := '0';
phy_Rst_n : out std_logic := '1';
phy_SMIClk : out std_logic := '0';
phy_SMIDat_O : out std_logic;
phy_SMIDat_T : out std_logic;
pio_operational : out std_logic := '0';
pio_portOutValid : out std_logic_vector(3 downto 0) := (others => '0');
pio_portio_O : out std_logic_vector(31 downto 0);
pio_portio_T : out std_logic_vector(31 downto 0);
smp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
smp_waitrequest : out std_logic;
spi_miso : out std_logic := '0';
tcp_irq : out std_logic := '0';
tcp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
tcp_waitrequest : out std_logic;
pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_gpio : inout std_logic_vector(1 downto 0) := (others => '0');
phy0_SMIDat : inout std_logic := '1';
phy1_SMIDat : inout std_logic := '1';
phy_SMIDat : inout std_logic := '1';
pio_portio : inout std_logic_vector(31 downto 0) := (others => '0')
);
end component;
component plbv46_master_burst
generic(
C_FAMILY : string := "virtex5";
C_INHIBIT_CC_BLE_INCLUSION : integer range 0 to 1 := 0;
C_MPLB_AWIDTH : integer range 32 to 36 := 32;
C_MPLB_DWIDTH : integer range 32 to 128 := 32;
C_MPLB_NATIVE_DWIDTH : integer range 32 to 128 := 32;
C_MPLB_SMALLEST_SLAVE : integer range 32 to 128 := 32
);
port (
IP2Bus_MstRd_Req : in std_logic;
IP2Bus_MstRd_dst_dsc_n : in std_logic;
IP2Bus_MstRd_dst_rdy_n : in std_logic;
IP2Bus_MstWr_Req : in std_logic;
IP2Bus_MstWr_d : in std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
IP2Bus_MstWr_eof_n : in std_logic;
IP2Bus_MstWr_rem : in std_logic_vector(0 to (C_MPLB_NATIVE_DWIDTH/8)-1);
IP2Bus_MstWr_sof_n : in std_logic;
IP2Bus_MstWr_src_dsc_n : in std_logic;
IP2Bus_MstWr_src_rdy_n : in std_logic;
IP2Bus_Mst_Addr : in std_logic_vector(0 to C_MPLB_AWIDTH-1);
IP2Bus_Mst_BE : in std_logic_vector(0 to (C_MPLB_NATIVE_DWIDTH/8)-1);
IP2Bus_Mst_Length : in std_logic_vector(0 to 11);
IP2Bus_Mst_Lock : in std_logic;
IP2Bus_Mst_Reset : in std_logic;
IP2Bus_Mst_Type : in std_logic;
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MBusy : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to C_MPLB_DWIDTH-1);
PLB_MRdErr : in std_logic;
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MTimeout : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrErr : in std_logic;
Bus2IP_MstRd_d : out std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
Bus2IP_MstRd_eof_n : out std_logic;
Bus2IP_MstRd_rem : out std_logic_vector(0 to (C_MPLB_NATIVE_DWIDTH/8)-1);
Bus2IP_MstRd_sof_n : out std_logic;
Bus2IP_MstRd_src_dsc_n : out std_logic;
Bus2IP_MstRd_src_rdy_n : out std_logic;
Bus2IP_MstWr_dst_dsc_n : out std_logic;
Bus2IP_MstWr_dst_rdy_n : out std_logic;
Bus2IP_Mst_CmdAck : out std_logic;
Bus2IP_Mst_Cmd_Timeout : out std_logic;
Bus2IP_Mst_Cmplt : out std_logic;
Bus2IP_Mst_Error : out std_logic;
Bus2IP_Mst_Rearbitrate : out std_logic;
MD_Error : out std_logic;
M_ABus : out std_logic_vector(0 to 31);
M_BE : out std_logic_vector(0 to (C_MPLB_DWIDTH/8)-1);
M_MSize : out std_logic_vector(0 to 1);
M_RNW : out std_logic;
M_TAttribute : out std_logic_vector(0 to 15);
M_UABus : out std_logic_vector(0 to 31);
M_abort : out std_logic;
M_busLock : out std_logic;
M_lockErr : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1)
);
end component;
component plbv46_slave_single
generic(
C_ARD_ADDR_RANGE_ARRAY : slv64_array_type := (X"0000_0000_7000_0000",X"0000_0000_7000_00FF",X"0000_0000_7000_0100",X"0000_0000_7000_01FF");
C_ARD_NUM_CE_ARRAY : integer_array_type := (1,8);
C_BUS2CORE_CLK_RATIO : integer range 1 to 2 := 1;
C_FAMILY : string := "virtex4";
C_INCLUDE_DPHASE_TIMER : integer range 0 to 1 := 1;
C_SIPIF_DWIDTH : integer range 32 to 32 := 32;
C_SPLB_AWIDTH : integer range 32 to 32 := 32;
C_SPLB_DWIDTH : integer range 32 to 128 := 32;
C_SPLB_MID_WIDTH : integer range 1 to 4 := 2;
C_SPLB_NUM_MASTERS : integer range 1 to 16 := 8;
C_SPLB_P2P : integer range 0 to 1 := 0
);
port (
IP2Bus_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
IP2Bus_Error : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_WrAck : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_BE : in std_logic_vector(0 to (C_SPLB_DWIDTH/8)-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_PAValid : in std_logic;
PLB_RNW : in std_logic;
PLB_SAValid : in std_logic;
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_lockErr : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_rdBurst : in std_logic;
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_rdPendReq : in std_logic;
PLB_rdPrim : in std_logic;
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrBurst : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_wrPendReq : in std_logic;
PLB_wrPrim : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
Bus2IP_Addr : out std_logic_vector(0 to C_SPLB_AWIDTH-1);
Bus2IP_BE : out std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
Bus2IP_CS : out std_logic_vector(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
Bus2IP_Clk : out std_logic;
Bus2IP_Data : out std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_RNW : out std_logic;
Bus2IP_RdCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_Reset : out std_logic;
Bus2IP_WrCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_SSize : out std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdDAck : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rearbitrate : out std_logic;
Sl_wait : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrDAck : out std_logic
);
end component;
---- Architecture declarations -----
constant C_ADDR_PAD_ZERO : std_logic_vector(31 downto 0) := (others => '0');
-- openMAC REG PLB Slave
constant C_MAC_REG_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_REG_BASEADDR;
constant C_MAC_REG_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_REG_HIGHADDR;
-- openMAC CMP PLB Slave
constant C_MAC_CMP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_CMP_BASEADDR;
constant C_MAC_CMP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_CMP_HIGHADDR;
-- openMAC PKT PLB Slave
constant C_MAC_PKT_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_PKT_BASEADDR;
constant C_MAC_PKT_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_PKT_HIGHADDR;
-- SimpleIO Slave
constant C_SMP_PCP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_SMP_PCP_BASEADDR;
constant C_SMP_PCP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_SMP_PCP_HIGHADDR;
-- PDI PCP Slave
constant C_PDI_PCP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_PDI_PCP_BASEADDR;
constant C_PDI_PCP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_PDI_PCP_HIGHADDR;
-- AP PCP Slave
constant C_PDI_AP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_PDI_AP_BASEADDR;
constant C_PDI_AP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_PDI_AP_HIGHADDR;
-- POWERLINK IP-core
constant C_MAC_PKT_EN : boolean := C_TX_INT_PKT or C_RX_INT_PKT;
constant C_MAC_PKT_RX_EN : boolean := C_RX_INT_PKT;
constant C_DMA_EN : boolean := not C_TX_INT_PKT or not C_RX_INT_PKT;
constant C_PKT_BUF_EN : boolean := C_MAC_PKT_EN;
constant C_M_BURSTCOUNT_WIDTH : integer := integer(ceil(log2(real(get_max(C_MAC_DMA_BURST_SIZE_RX,C_MAC_DMA_BURST_SIZE_TX)/4)))) + 1; --in dwords
constant C_M_FIFO_SIZE_RX : integer := C_MAC_DMA_FIFO_SIZE_RX/4; --in dwords
constant C_M_FIFO_SIZE_TX : integer := C_MAC_DMA_FIFO_SIZE_TX/4; --in dwords
---- Constants -----
constant VCC_CONSTANT : std_logic := '1';
constant GND_CONSTANT : std_logic := '0';
---- Signal declarations used on the diagram ----
signal ap_chipselect : std_logic;
signal ap_read : std_logic;
signal ap_waitrequest : std_logic;
signal ap_write : std_logic;
signal Bus2MAC_CMP_Reset : std_logic;
signal Bus2MAC_DMA_MstRd_eof_n : std_logic;
signal Bus2MAC_DMA_MstRd_sof_n : std_logic;
signal Bus2MAC_DMA_MstRd_src_dsc_n : std_logic;
signal Bus2MAC_DMA_MstRd_src_rdy_n : std_logic;
signal Bus2MAC_DMA_MstWr_dst_dsc_n : std_logic;
signal Bus2MAC_DMA_MstWr_dst_rdy_n : std_logic;
signal Bus2MAC_DMA_Mst_CmdAck : std_logic;
signal Bus2MAC_DMA_Mst_Cmd_Timeout : std_logic;
signal Bus2MAC_DMA_Mst_Cmplt : std_logic;
signal Bus2MAC_DMA_Mst_Error : std_logic;
signal Bus2MAC_DMA_Mst_Rearbitrate : std_logic;
signal Bus2MAC_PKT_Clk : std_logic;
signal Bus2MAC_PKT_Reset : std_logic;
signal Bus2MAC_PKT_RNW : std_logic;
signal Bus2MAC_REG_Clk : std_logic;
signal Bus2MAC_REG_Reset : std_logic;
signal Bus2MAC_REG_RNW : std_logic;
signal Bus2MAC_REG_RNW_n : std_logic;
signal Bus2PDI_AP_Clk : std_logic;
signal Bus2PDI_AP_Reset : std_logic;
signal Bus2PDI_AP_RNW : std_logic;
signal Bus2PDI_PCP_Clk : std_logic;
signal Bus2PDI_PCP_Reset : std_logic;
signal Bus2PDI_PCP_RNW : std_logic;
signal Bus2SMP_PCP_Clk : std_logic;
signal Bus2SMP_PCP_Reset : std_logic;
signal Bus2SMP_PCP_RNW : std_logic;
signal clkAp : std_logic;
signal clkPcp : std_logic;
signal GND : std_logic;
signal IP2Bus_Error_s : std_logic;
signal IP2Bus_RdAck_s : std_logic;
signal IP2Bus_WrAck_s : std_logic;
signal mac_chipselect : std_logic;
signal MAC_CMP2Bus_Error : std_logic;
signal MAC_CMP2Bus_RdAck : std_logic;
signal MAC_CMP2Bus_WrAck : std_logic;
signal MAC_DMA2Bus_MstRd_dst_dsc_n : std_logic;
signal MAC_DMA2Bus_MstRd_dst_rdy_n : std_logic;
signal MAC_DMA2Bus_MstRd_Req : std_logic;
signal MAC_DMA2Bus_MstWr_eof_n : std_logic;
signal MAC_DMA2Bus_MstWr_Req : std_logic;
signal MAC_DMA2Bus_MstWr_sof_n : std_logic;
signal MAC_DMA2Bus_MstWr_src_dsc_n : std_logic;
signal MAC_DMA2Bus_MstWr_src_rdy_n : std_logic;
signal MAC_DMA2Bus_Mst_Lock : std_logic;
signal MAC_DMA2Bus_Mst_Reset : std_logic;
signal MAC_DMA2Bus_Mst_Type : std_logic;
signal mac_irq_s : std_logic;
signal MAC_PKT2Bus_Error : std_logic;
signal MAC_PKT2Bus_RdAck : std_logic;
signal MAC_PKT2Bus_WrAck : std_logic;
signal mac_read : std_logic;
signal MAC_REG2Bus_Error : std_logic;
signal MAC_REG2Bus_RdAck : std_logic;
signal MAC_REG2Bus_WrAck : std_logic;
signal mac_waitrequest : std_logic;
signal mac_write : std_logic;
signal mbf_chipselect : std_logic;
signal mbf_read : std_logic;
signal mbf_waitrequest : std_logic;
signal mbf_write : std_logic;
signal m_clk : std_logic;
signal m_read : std_logic;
signal m_readdatavalid : std_logic;
signal m_waitrequest : std_logic;
signal m_write : std_logic;
signal NET118078 : std_ulogic;
signal NET118214 : std_ulogic;
signal pcp_chipselect : std_logic;
signal pcp_read : std_logic;
signal pcp_waitrequest : std_logic;
signal pcp_write : std_logic;
signal PDI_AP2Bus_Error : std_logic;
signal PDI_AP2Bus_RdAck : std_logic;
signal PDI_AP2Bus_WrAck : std_logic;
signal PDI_PCP2Bus_Error : std_logic;
signal PDI_PCP2Bus_RdAck : std_logic;
signal PDI_PCP2Bus_WrAck : std_logic;
signal pkt_clk : std_logic;
signal rst : std_logic;
signal rstAp : std_logic;
signal rstPcp : std_logic;
signal smp_address : std_logic;
signal smp_chipselect : std_logic;
signal SMP_PCP2Bus_Error : std_logic;
signal SMP_PCP2Bus_RdAck : std_logic;
signal SMP_PCP2Bus_WrAck : std_logic;
signal smp_read : std_logic;
signal smp_waitrequest : std_logic;
signal smp_write : std_logic;
signal tcp_chipselect : std_logic;
signal tcp_irq_s : std_logic;
signal tcp_read : std_logic;
signal tcp_waitrequest : std_logic;
signal tcp_write : std_logic;
signal VCC : std_logic;
signal ap_address : std_logic_vector (12 downto 0);
signal ap_byteenable : std_logic_vector (3 downto 0);
signal ap_readdata : std_logic_vector (31 downto 0);
signal ap_writedata : std_logic_vector (31 downto 0);
signal Bus2MAC_DMA_MstRd_d : std_logic_vector (C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0);
signal Bus2MAC_DMA_MstRd_d_s : std_logic_vector (C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0);
signal Bus2MAC_DMA_MstRd_rem : std_logic_vector (0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1);
signal Bus2MAC_PKT_Addr : std_logic_vector (C_MAC_PKT_PLB_AWIDTH-1 downto 0);
signal Bus2MAC_PKT_BE : std_logic_vector ((C_MAC_PKT_PLB_DWIDTH/8)-1 downto 0);
signal Bus2MAC_PKT_CS : std_logic_vector (0 downto 0);
signal Bus2MAC_PKT_Data : std_logic_vector (C_MAC_PKT_PLB_DWIDTH-1 downto 0);
signal Bus2MAC_REG_Addr : std_logic_vector (C_MAC_REG_PLB_AWIDTH-1 downto 0);
signal Bus2MAC_REG_BE : std_logic_vector ((C_MAC_REG_PLB_DWIDTH/8)-1 downto 0);
signal Bus2MAC_REG_BE_s : std_logic_vector ((C_MAC_REG_PLB_DWIDTH/8)-1 downto 0);
signal Bus2MAC_REG_CS : std_logic_vector (1 downto 0);
signal Bus2MAC_REG_Data : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal Bus2MAC_REG_Data_s : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal Bus2PDI_AP_Addr : std_logic_vector (C_PDI_AP_PLB_AWIDTH-1 downto 0);
signal Bus2PDI_AP_BE : std_logic_vector ((C_PDI_AP_PLB_DWIDTH/8)-1 downto 0);
signal Bus2PDI_AP_CS : std_logic_vector (0 downto 0);
signal Bus2PDI_AP_Data : std_logic_vector (C_PDI_AP_PLB_DWIDTH-1 downto 0);
signal Bus2PDI_PCP_Addr : std_logic_vector (C_PDI_PCP_PLB_AWIDTH-1 downto 0);
signal Bus2PDI_PCP_BE : std_logic_vector ((C_PDI_PCP_PLB_DWIDTH/8)-1 downto 0);
signal Bus2PDI_PCP_CS : std_logic_vector (0 downto 0);
signal Bus2PDI_PCP_Data : std_logic_vector (C_PDI_PCP_PLB_DWIDTH-1 downto 0);
signal Bus2SMP_PCP_Addr : std_logic_vector (C_SMP_PCP_PLB_AWIDTH-1 downto 0);
signal Bus2SMP_PCP_BE : std_logic_vector ((C_SMP_PCP_PLB_DWIDTH/8)-1 downto 0);
signal Bus2SMP_PCP_CS : std_logic_vector (0 downto 0);
signal Bus2SMP_PCP_Data : std_logic_vector (C_SMP_PCP_PLB_DWIDTH-1 downto 0);
signal IP2Bus_Data_s : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal mac_address : std_logic_vector (C_MAC_REG_PLB_AWIDTH-1 downto 0);
signal mac_byteenable : std_logic_vector (1 downto 0);
signal MAC_CMP2Bus_Data : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal MAC_DMA2Bus_MstWr_d : std_logic_vector (C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0);
signal MAC_DMA2Bus_MstWr_d_s : std_logic_vector (C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0);
signal MAC_DMA2Bus_MstWr_rem : std_logic_vector (0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1);
signal MAC_DMA2Bus_Mst_Addr : std_logic_vector (0 to C_MAC_DMA_PLB_AWIDTH-1);
signal MAC_DMA2Bus_Mst_BE : std_logic_vector (0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1);
signal MAC_DMA2Bus_Mst_Length : std_logic_vector (0 to 11);
signal MAC_PKT2Bus_Data : std_logic_vector (C_MAC_PKT_PLB_DWIDTH-1 downto 0);
signal mac_readdata : std_logic_vector (15 downto 0);
signal MAC_REG2Bus_Data : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal MAC_REG2Bus_Data_s : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal mac_writedata : std_logic_vector (15 downto 0);
signal mbf_address : std_logic_vector (C_MAC_PKT_SIZE_LOG2-3 downto 0);
signal mbf_byteenable : std_logic_vector (3 downto 0);
signal mbf_readdata : std_logic_vector (31 downto 0);
signal mbf_writedata : std_logic_vector (31 downto 0);
signal m_address : std_logic_vector (31 downto 0);
signal m_burstcount : std_logic_vector (C_M_BURSTCOUNT_WIDTH-1 downto 0);
signal m_burstcounter : std_logic_vector (C_M_BURSTCOUNT_WIDTH-1 downto 0);
signal m_byteenable : std_logic_vector (3 downto 0);
signal m_readdata : std_logic_vector (31 downto 0);
signal m_writedata : std_logic_vector (31 downto 0);
signal pcp_address : std_logic_vector (12 downto 0);
signal pcp_byteenable : std_logic_vector (3 downto 0);
signal pcp_readdata : std_logic_vector (31 downto 0);
signal pcp_writedata : std_logic_vector (31 downto 0);
signal PDI_AP2Bus_Data : std_logic_vector (C_PDI_AP_PLB_DWIDTH-1 downto 0);
signal PDI_PCP2Bus_Data : std_logic_vector (C_PDI_PCP_PLB_DWIDTH-1 downto 0);
signal smp_byteenable : std_logic_vector (3 downto 0);
signal SMP_PCP2Bus_Data : std_logic_vector (C_SMP_PCP_PLB_DWIDTH-1 downto 0);
signal smp_readdata : std_logic_vector (31 downto 0);
signal smp_writedata : std_logic_vector (31 downto 0);
signal tcp_address : std_logic_vector (1 downto 0);
signal tcp_byteenable : std_logic_vector (3 downto 0);
signal tcp_readdata : std_logic_vector (31 downto 0);
signal tcp_writedata : std_logic_vector (31 downto 0);
begin
---- User Signal Assignments ----
-- connect mac reg with mac cmp or reg output signals
with Bus2MAC_REG_CS select
IP2Bus_Data_s(C_MAC_REG_PLB_DWIDTH-1 downto 0) <= MAC_REG2Bus_Data(C_MAC_REG_PLB_DWIDTH-1 downto 0) when "10",
MAC_CMP2Bus_Data(C_MAC_REG_PLB_DWIDTH-1 downto 0) when "01",
(others => '0') when others;
with Bus2MAC_REG_CS select
IP2Bus_WrAck_s <= MAC_REG2Bus_WrAck when "10",
MAC_CMP2Bus_WrAck when "01",
'0' when others;
with Bus2MAC_REG_CS select
IP2Bus_RdAck_s <= MAC_REG2Bus_RdAck when "10",
MAC_CMP2Bus_RdAck when "01",
'0' when others;
with Bus2MAC_REG_CS select
IP2Bus_Error_s <= MAC_REG2Bus_Error when "10",
MAC_CMP2Bus_Error when "01",
'0' when others;
Bus2MAC_REG_BE_s <=
Bus2MAC_REG_BE(0) & Bus2MAC_REG_BE(1) &
Bus2MAC_REG_BE(2) & Bus2MAC_REG_BE(3);
Bus2MAC_REG_Data_s <=
Bus2MAC_REG_Data(7 downto 0) & Bus2MAC_REG_Data(15 downto 8) &
Bus2MAC_REG_Data(23 downto 16) & Bus2MAC_REG_Data(31 downto 24);
MAC_REG2Bus_Data <=
MAC_REG2Bus_Data_s(7 downto 0) & MAC_REG2Bus_Data_s(15 downto 8) &
MAC_REG2Bus_Data_s(23 downto 16) & MAC_REG2Bus_Data_s(31 downto 24);
--test_port
test_port(181 downto 179) <= mac_chipselect & mac_write & mac_read;
test_port(178) <= mac_waitrequest;
test_port(177 downto 176) <= mac_byteenable;
test_port(171 downto 160) <= mac_address(11 downto 0);
test_port(159 downto 144) <= mac_writedata;
test_port(143 downto 128) <= mac_readdata;
test_port(104 downto 102) <= Bus2MAC_REG_CS & Bus2MAC_REG_RNW;
test_port(101 downto 100) <= IP2Bus_WrAck_s & IP2Bus_RdAck_s;
test_port(99 downto 96) <= Bus2MAC_REG_BE;
test_port(95 downto 64) <= Bus2MAC_REG_Addr;
test_port(63 downto 32) <= Bus2MAC_REG_Data;
test_port(31 downto 0) <= IP2Bus_Data_s;
--test_port(255 downto 251) <= m_read & m_write & m_waitrequest & m_readdatavalid & MAC_DMA2Bus_Mst_Type;
--test_port(244 downto 240) <= MAC_DMA2Bus_MstWr_Req & MAC_DMA2Bus_MstWr_sof_n & MAC_DMA2Bus_MstWr_eof_n & MAC_DMA2Bus_MstWr_src_rdy_n & Bus2MAC_DMA_MstWr_dst_rdy_n;
--test_port(234 downto 230) <= MAC_DMA2Bus_MstRd_Req & Bus2MAC_DMA_MstRd_sof_n & Bus2MAC_DMA_MstRd_eof_n & Bus2MAC_DMA_MstRd_src_rdy_n & MAC_DMA2Bus_MstRd_dst_rdy_n;
--test_port(142 downto 140) <= Bus2MAC_DMA_Mst_Cmplt & Bus2MAC_DMA_Mst_Error & Bus2MAC_DMA_Mst_Cmd_Timeout;
--test_port(MAC_DMA2Bus_Mst_Length'length+120-1 downto 120) <= MAC_DMA2Bus_Mst_Length;
--test_port(m_burstcount'length+110-1 downto 110) <= m_burstcount;
--test_port(m_burstcounter'length+96-1 downto 96) <= m_burstcounter;
--test_port(95 downto 64) <= m_address;
--test_port(63 downto 32) <= m_writedata;
--test_port(31 downto 0) <= m_readdata;
--mac_cmp assignments
---cmp_clk <= Bus2MAC_CMP_Clk;
tcp_writedata <=
Bus2MAC_REG_Data(7 downto 0) & Bus2MAC_REG_Data(15 downto 8) &
Bus2MAC_REG_Data(23 downto 16) & Bus2MAC_REG_Data(31 downto 24);
tcp_read <= Bus2MAC_REG_RNW;
tcp_write <= not Bus2MAC_REG_RNW;
tcp_chipselect <= Bus2MAC_REG_CS(0);
tcp_byteenable <=
Bus2MAC_REG_BE(0) & Bus2MAC_REG_BE(1) &
Bus2MAC_REG_BE(2) & Bus2MAC_REG_BE(3);
tcp_address <= Bus2MAC_REG_Addr(3 downto 2);
MAC_CMP2Bus_Data <=
tcp_readdata(7 downto 0) & tcp_readdata(15 downto 8) &
tcp_readdata(23 downto 16) & tcp_readdata(31 downto 24);
MAC_CMP2Bus_RdAck <= tcp_chipselect and tcp_read and not tcp_waitrequest;
MAC_CMP2Bus_WrAck <= tcp_chipselect and tcp_write and not tcp_waitrequest;
MAC_CMP2Bus_Error <= '0';
--mac_pkt assignments
pkt_clk <= Bus2MAC_PKT_Clk;
mbf_writedata <=
Bus2MAC_PKT_Data(7 downto 0) & Bus2MAC_PKT_Data(15 downto 8) &
Bus2MAC_PKT_Data(23 downto 16) & Bus2MAC_PKT_Data(31 downto 24);
mbf_read <= Bus2MAC_PKT_RNW;
mbf_write <= not Bus2MAC_PKT_RNW;
mbf_chipselect <= Bus2MAC_PKT_CS(0);
mbf_byteenable <=
Bus2MAC_PKT_BE(0) & Bus2MAC_PKT_BE(1) &
Bus2MAC_PKT_BE(2) & Bus2MAC_PKT_BE(3);
mbf_address <= Bus2MAC_PKT_Addr(C_MAC_PKT_SIZE_LOG2-1 downto 2);
MAC_PKT2Bus_Data <=
mbf_readdata(7 downto 0) & mbf_readdata(15 downto 8) &
mbf_readdata(23 downto 16) & mbf_readdata(31 downto 24);
MAC_PKT2Bus_RdAck <= mbf_chipselect and mbf_read and not mbf_waitrequest;
MAC_PKT2Bus_WrAck <= mbf_chipselect and mbf_write and not mbf_waitrequest;
MAC_PKT2Bus_Error <= '0';
---- Component instantiations ----
MAC_REG_16to32 : openMAC_16to32conv
generic map (
bus_address_width => C_MAC_REG_PLB_AWIDTH,
gEndian => "big"
)
port map(
bus_ack_rd => MAC_REG2Bus_RdAck,
bus_ack_wr => MAC_REG2Bus_WrAck,
bus_address => Bus2MAC_REG_Addr( C_MAC_REG_PLB_AWIDTH-1 downto 0 ),
bus_byteenable => Bus2MAC_REG_BE_s( (C_MAC_REG_PLB_DWIDTH/8)-1 downto 0 ),
bus_read => Bus2MAC_REG_RNW,
bus_readdata => MAC_REG2Bus_Data_s( C_MAC_REG_PLB_DWIDTH-1 downto 0 ),
bus_select => Bus2MAC_REG_CS(1),
bus_write => Bus2MAC_REG_RNW_n,
bus_writedata => Bus2MAC_REG_Data_s( C_MAC_REG_PLB_DWIDTH-1 downto 0 ),
clk => clk50,
rst => rst,
s_address => mac_address( C_MAC_REG_PLB_AWIDTH-1 downto 0 ),
s_byteenable => mac_byteenable,
s_chipselect => mac_chipselect,
s_read => mac_read,
s_readdata => mac_readdata,
s_waitrequest => mac_waitrequest,
s_write => mac_write,
s_writedata => mac_writedata
);
MAC_REG_PLB_SINGLE_SLAVE : plbv46_slave_single
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_MAC_REG_BASE,C_MAC_REG_HIGH,C_MAC_CMP_BASE,C_MAC_CMP_HIGH),
C_ARD_NUM_CE_ARRAY => (1, 1),
C_BUS2CORE_CLK_RATIO => C_MAC_REG_BUS2CORE_CLK_RATIO,
C_FAMILY => C_FAMILY,
C_INCLUDE_DPHASE_TIMER => 0,
C_SIPIF_DWIDTH => C_MAC_REG_PLB_DWIDTH,
C_SPLB_AWIDTH => C_MAC_REG_PLB_AWIDTH,
C_SPLB_DWIDTH => C_MAC_REG_PLB_DWIDTH,
C_SPLB_MID_WIDTH => C_MAC_REG_PLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_MAC_REG_PLB_NUM_MASTERS,
C_SPLB_P2P => C_MAC_REG_PLB_P2P
)
port map(
Bus2IP_Addr => Bus2MAC_REG_Addr( C_MAC_REG_PLB_AWIDTH-1 downto 0 ),
Bus2IP_BE => Bus2MAC_REG_BE( (C_MAC_REG_PLB_DWIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2MAC_REG_CS( 1 downto 0 ),
Bus2IP_Clk => Bus2MAC_REG_Clk,
Bus2IP_Data => Bus2MAC_REG_Data( C_MAC_REG_PLB_DWIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2MAC_REG_RNW,
Bus2IP_Reset => Bus2MAC_REG_Reset,
IP2Bus_Data => IP2Bus_Data_s( C_MAC_REG_PLB_DWIDTH-1 downto 0 ),
IP2Bus_Error => IP2Bus_Error_s,
IP2Bus_RdAck => IP2Bus_RdAck_s,
IP2Bus_WrAck => IP2Bus_WrAck_s,
PLB_ABus => MAC_REG_ABus,
PLB_BE => MAC_REG_BE( 0 to (C_MAC_REG_PLB_DWIDTH / 8) - 1 ),
PLB_MSize => MAC_REG_MSize,
PLB_PAValid => MAC_REG_PAValid,
PLB_RNW => MAC_REG_RNW,
PLB_SAValid => MAC_REG_SAValid,
PLB_TAttribute => MAC_REG_TAttribute,
PLB_UABus => MAC_REG_UABus,
PLB_abort => MAC_REG_abort,
PLB_busLock => MAC_REG_busLock,
PLB_lockErr => MAC_REG_lockErr,
PLB_masterID => MAC_REG_masterID( 0 to C_MAC_REG_PLB_MID_WIDTH - 1 ),
PLB_rdBurst => MAC_REG_rdBurst,
PLB_rdPendPri => MAC_REG_rdPendPri,
PLB_rdPendReq => MAC_REG_rdPendReq,
PLB_rdPrim => MAC_REG_rdPrim,
PLB_reqPri => MAC_REG_reqPri,
PLB_size => MAC_REG_size,
PLB_type => MAC_REG_type,
PLB_wrBurst => MAC_REG_wrBurst,
PLB_wrDBus => MAC_REG_wrDBus( 0 to C_MAC_REG_PLB_DWIDTH - 1 ),
PLB_wrPendPri => MAC_REG_wrPendPri,
PLB_wrPendReq => MAC_REG_wrPendReq,
PLB_wrPrim => MAC_REG_wrPrim,
SPLB_Clk => MAC_REG_Clk,
SPLB_Rst => MAC_REG_Rst,
Sl_MBusy => MAC_REG_MBusy( 0 to C_MAC_REG_NUM_MASTERS-1 ),
Sl_MIRQ => MAC_REG_MIRQ( 0 to C_MAC_REG_NUM_MASTERS-1 ),
Sl_MRdErr => MAC_REG_MRdErr( 0 to C_MAC_REG_NUM_MASTERS-1 ),
Sl_MWrErr => MAC_REG_MWrErr( 0 to C_MAC_REG_NUM_MASTERS-1 ),
Sl_SSize => MAC_REG_SSize,
Sl_addrAck => MAC_REG_addrAck,
Sl_rdBTerm => MAC_REG_rdBTerm,
Sl_rdComp => MAC_REG_rdComp,
Sl_rdDAck => MAC_REG_rdDAck,
Sl_rdDBus => MAC_REG_rdDBus( 0 to C_MAC_REG_PLB_DWIDTH-1 ),
Sl_rdWdAddr => MAC_REG_rdWdAddr,
Sl_rearbitrate => MAC_REG_rearbitrate,
Sl_wait => MAC_REG_wait,
Sl_wrBTerm => MAC_REG_wrBTerm,
Sl_wrComp => MAC_REG_wrComp,
Sl_wrDAck => MAC_REG_wrDAck
);
THE_POWERLINK_IP_CORE : powerlink
generic map (
Simulate => booleanToInteger(false),
endian_g => "big",
gNumSmi => C_NUM_SMI,
genABuf1_g => booleanToInteger(C_PDI_GEN_ASYNC_BUF_0),
genABuf2_g => booleanToInteger(C_PDI_GEN_ASYNC_BUF_1),
genEvent_g => booleanToInteger(C_PDI_GEN_EVENT),
genInternalAp_g => booleanToInteger(C_GEN_PLB_BUS_IF),
genIoBuf_g => booleanToInteger(false),
genLedGadget_g => booleanToInteger(C_PDI_GEN_LED),
genOnePdiClkDomain_g => booleanToInteger(false),
genPdi_g => booleanToInteger(C_GEN_PDI),
genSimpleIO_g => booleanToInteger(C_GEN_SIMPLE_IO),
genSmiIO => booleanToInteger(false),
genSpiAp_g => booleanToInteger(C_GEN_SPI_IF),
genTimeSync_g => booleanToInteger(C_PDI_GEN_TIME_SYNC),
gen_dma_observer_g => booleanToInteger(C_OBSERVER_ENABLE),
iAsyBuf1Size_g => C_PDI_ASYNC_BUF_0,
iAsyBuf2Size_g => C_PDI_ASYNC_BUF_1,
iBufSizeLOG2_g => C_MAC_PKT_SIZE_LOG2,
iBufSize_g => C_MAC_PKT_SIZE,
iPdiRev_g => C_PDI_REV,
iRpdo0BufSize_g => C_RPDO_0_BUF_SIZE,
iRpdo1BufSize_g => C_RPDO_1_BUF_SIZE,
iRpdo2BufSize_g => C_RPDO_2_BUF_SIZE,
iRpdos_g => C_NUM_RPDO,
iTpdoBufSize_g => C_TPDO_BUF_SIZE,
iTpdos_g => C_NUM_TPDO,
m_burstcount_const_g => booleanToInteger(true),
m_burstcount_width_g => C_M_BURSTCOUNT_WIDTH,
m_data_width_g => 32,
m_rx_burst_size_g => C_MAC_DMA_BURST_SIZE_RX/4,
m_rx_fifo_size_g => C_M_FIFO_SIZE_RX,
m_tx_burst_size_g => C_MAC_DMA_BURST_SIZE_TX/4,
m_tx_fifo_size_g => C_M_FIFO_SIZE_TX,
papBigEnd_g => booleanToInteger(false),
papDataWidth_g => C_PAP_DATA_WIDTH,
papLowAct_g => booleanToInteger(C_PAP_LOW_ACT),
pcpSysId => C_PCP_SYS_ID,
pioValLen_g => C_PIO_VAL_LENGTH,
pulseWidth2ndCmpTimer_g => C_PULSE_WIDTH_2nd_CMP_TIMER,
spiBigEnd_g => booleanToInteger(false),
spiCPHA_g => booleanToInteger(C_SPI_CPHA),
spiCPOL_g => booleanToInteger(C_SPI_CPOL),
use2ndCmpTimer_g => booleanToInteger(C_MAC_GEN_SECOND_TIMER),
use2ndPhy_g => booleanToInteger(C_USE_2ND_PHY),
useIntPacketBuf_g => booleanToInteger(C_MAC_PKT_EN),
usePulse2ndCmpTimer_g => booleanToInteger(C_USE_PULSE_2nd_CMP_TIMER),
useRmii_g => booleanToInteger(C_USE_RMII),
useRxIntPacketBuf_g => booleanToInteger(C_MAC_PKT_RX_EN)
)
port map(
mac_address(0) => mac_address(0),
mac_address(1) => mac_address(1),
mac_address(2) => mac_address(2),
mac_address(3) => mac_address(3),
mac_address(4) => mac_address(4),
mac_address(5) => mac_address(5),
mac_address(6) => mac_address(6),
mac_address(7) => mac_address(7),
mac_address(8) => mac_address(8),
mac_address(9) => mac_address(9),
mac_address(10) => mac_address(10),
mac_address(11) => mac_address(11),
ap_address => ap_address,
ap_asyncIrq => ap_asyncIrq,
ap_asyncIrq_n => ap_asyncIrq_n,
ap_byteenable => ap_byteenable,
ap_chipselect => ap_chipselect,
ap_read => ap_read,
ap_readdata => ap_readdata,
ap_syncIrq => ap_syncIrq,
ap_syncIrq_n => ap_syncIrq_n,
ap_waitrequest => ap_waitrequest,
ap_write => ap_write,
ap_writedata => ap_writedata,
clk50 => clk50,
clkAp => clkAp,
clkEth => clk100,
clkPcp => clkPcp,
led_error => led_error,
led_gpo => led_gpo,
led_opt => led_opt,
led_phyAct => led_phyAct,
led_phyLink => led_phyLink,
led_status => led_status,
m_address => m_address,
m_burstcount => m_burstcount( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_burstcounter => m_burstcounter( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_byteenable => m_byteenable( 3 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdata => m_readdata( 31 downto 0 ),
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
m_writedata => m_writedata( 31 downto 0 ),
mac_byteenable => mac_byteenable,
mac_chipselect => mac_chipselect,
mac_irq => mac_irq_s,
mac_read => mac_read,
mac_readdata => mac_readdata,
mac_waitrequest => mac_waitrequest,
mac_write => mac_write,
mac_writedata => mac_writedata,
mbf_address => mbf_address( C_MAC_PKT_SIZE_LOG2-3 downto 0 ),
mbf_byteenable => mbf_byteenable,
mbf_chipselect => mbf_chipselect,
mbf_read => mbf_read,
mbf_readdata => mbf_readdata,
mbf_waitrequest => mbf_waitrequest,
mbf_write => mbf_write,
mbf_writedata => mbf_writedata,
pap_ack => pap_ack,
pap_ack_n => pap_ack_n,
pap_addr => pap_addr,
pap_be => pap_be( C_PAP_DATA_WIDTH/8-1 downto 0 ),
pap_be_n => pap_be_n( C_PAP_DATA_WIDTH/8-1 downto 0 ),
pap_cs => pap_cs,
pap_cs_n => pap_cs_n,
pap_data_I => pap_data_I( C_PAP_DATA_WIDTH-1 downto 0 ),
pap_data_O => pap_data_O( C_PAP_DATA_WIDTH-1 downto 0 ),
pap_data_T => pap_data_T,
pap_gpio_I => pap_gpio_I,
pap_gpio_O => pap_gpio_O,
pap_gpio_T => pap_gpio_T,
pap_rd => pap_rd,
pap_rd_n => pap_rd_n,
pap_wr => pap_wr,
pap_wr_n => pap_wr_n,
pcp_address => pcp_address,
pcp_byteenable => pcp_byteenable,
pcp_chipselect => pcp_chipselect,
pcp_read => pcp_read,
pcp_readdata => pcp_readdata,
pcp_waitrequest => pcp_waitrequest,
pcp_write => pcp_write,
pcp_writedata => pcp_writedata,
phy0_Rst_n => phy0_Rst_n,
phy0_RxDat => phy0_RxDat,
phy0_RxDv => phy0_RxDv,
phy0_RxErr => phy0_RxErr,
phy0_SMIClk => phy0_SMIClk,
phy0_SMIDat_I => phy0_SMIDat_I,
phy0_SMIDat_O => phy0_SMIDat_O,
phy0_SMIDat_T => phy0_SMIDat_T,
phy0_TxDat => phy0_TxDat,
phy0_TxEn => phy0_TxEn,
phy0_link => phy0_link,
phy1_Rst_n => phy1_Rst_n,
phy1_RxDat => phy1_RxDat,
phy1_RxDv => phy1_RxDv,
phy1_RxErr => phy1_RxErr,
phy1_SMIClk => phy1_SMIClk,
phy1_SMIDat_I => phy1_SMIDat_I,
phy1_SMIDat_O => phy1_SMIDat_O,
phy1_SMIDat_T => phy1_SMIDat_T,
phy1_TxDat => phy1_TxDat,
phy1_TxEn => phy1_TxEn,
phy1_link => phy1_link,
phyMii0_RxClk => phyMii0_RxClk,
phyMii0_RxDat => phyMii0_RxDat,
phyMii0_RxDv => phyMii0_RxDv,
phyMii0_RxEr => phyMii0_RxEr,
phyMii0_TxClk => phyMii0_TxClk,
phyMii0_TxDat => phyMii0_TxDat,
phyMii0_TxEn => phyMii0_TxEn,
phyMii0_TxEr => phyMii0_TxEr,
phyMii1_RxClk => phyMii1_RxClk,
phyMii1_RxDat => phyMii1_RxDat,
phyMii1_RxDv => phyMii1_RxDv,
phyMii1_RxEr => phyMii1_RxEr,
phyMii1_TxClk => phyMii1_TxClk,
phyMii1_TxDat => phyMii1_TxDat,
phyMii1_TxEn => phyMii1_TxEn,
phyMii1_TxEr => phyMii1_TxEr,
phy_Rst_n => phy_Rst_n,
phy_SMIClk => phy_SMIClk,
phy_SMIDat_I => phy_SMIDat_I,
phy_SMIDat_O => phy_SMIDat_O,
phy_SMIDat_T => phy_SMIDat_T,
pio_operational => pio_operational,
pio_pconfig => pio_pconfig,
pio_portInLatch => pio_portInLatch,
pio_portOutValid => pio_portOutValid,
pio_portio_I => pio_portio_I,
pio_portio_O => pio_portio_O,
pio_portio_T => pio_portio_T,
pkt_clk => pkt_clk,
rst => rst,
rstAp => rstAp,
rstPcp => rstPcp,
smp_address => smp_address,
smp_byteenable => smp_byteenable,
smp_read => smp_read,
smp_readdata => smp_readdata,
smp_waitrequest => smp_waitrequest,
smp_write => smp_write,
smp_writedata => smp_writedata,
spi_clk => spi_clk,
spi_miso => spi_miso,
spi_mosi => spi_mosi,
spi_sel_n => spi_sel_n,
tcp_address => tcp_address,
tcp_byteenable => tcp_byteenable,
tcp_chipselect => tcp_chipselect,
tcp_irq => tcp_irq_s,
tcp_read => tcp_read,
tcp_readdata => tcp_readdata,
tcp_waitrequest => tcp_waitrequest,
tcp_write => tcp_write,
tcp_writedata => tcp_writedata
);
rst <= Bus2MAC_REG_Reset or Bus2MAC_CMP_Reset or MAC_DMA_RST or Bus2MAC_PKT_Reset;
Bus2MAC_REG_RNW_n <= not(Bus2MAC_REG_RNW);
---- Power , ground assignment ----
VCC <= VCC_CONSTANT;
GND <= GND_CONSTANT;
MAC_REG2Bus_Error <= GND;
---- Terminal assignment ----
-- Output\buffer terminals
mac_irq <= mac_irq_s;
tcp_irq <= tcp_irq_s;
---- Generate statements ----
genMacDmaPlbBurst : if C_DMA_EN = TRUE generate
begin
MAC_DMA_PLB_BURST_MASTER : plbv46_master_burst
generic map (
C_FAMILY => C_FAMILY,
C_INHIBIT_CC_BLE_INCLUSION => 1,
C_MPLB_AWIDTH => C_MAC_DMA_PLB_AWIDTH,
C_MPLB_DWIDTH => C_MAC_DMA_PLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH => C_MAC_DMA_PLB_NATIVE_DWIDTH,
C_MPLB_SMALLEST_SLAVE => 32
)
port map(
Bus2IP_MstRd_d => Bus2MAC_DMA_MstRd_d( C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0 ),
Bus2IP_MstRd_eof_n => Bus2MAC_DMA_MstRd_eof_n,
Bus2IP_MstRd_rem => Bus2MAC_DMA_MstRd_rem( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
Bus2IP_MstRd_sof_n => Bus2MAC_DMA_MstRd_sof_n,
Bus2IP_MstRd_src_dsc_n => Bus2MAC_DMA_MstRd_src_dsc_n,
Bus2IP_MstRd_src_rdy_n => Bus2MAC_DMA_MstRd_src_rdy_n,
Bus2IP_MstWr_dst_dsc_n => Bus2MAC_DMA_MstWr_dst_dsc_n,
Bus2IP_MstWr_dst_rdy_n => Bus2MAC_DMA_MstWr_dst_rdy_n,
Bus2IP_Mst_CmdAck => Bus2MAC_DMA_Mst_CmdAck,
Bus2IP_Mst_Cmd_Timeout => Bus2MAC_DMA_Mst_Cmd_Timeout,
Bus2IP_Mst_Cmplt => Bus2MAC_DMA_Mst_Cmplt,
Bus2IP_Mst_Error => Bus2MAC_DMA_Mst_Error,
Bus2IP_Mst_Rearbitrate => Bus2MAC_DMA_Mst_Rearbitrate,
IP2Bus_MstRd_Req => MAC_DMA2Bus_MstRd_Req,
IP2Bus_MstRd_dst_dsc_n => MAC_DMA2Bus_MstRd_dst_dsc_n,
IP2Bus_MstRd_dst_rdy_n => MAC_DMA2Bus_MstRd_dst_rdy_n,
IP2Bus_MstWr_Req => MAC_DMA2Bus_MstWr_Req,
IP2Bus_MstWr_d => MAC_DMA2Bus_MstWr_d( C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0 ),
IP2Bus_MstWr_eof_n => MAC_DMA2Bus_MstWr_eof_n,
IP2Bus_MstWr_rem => MAC_DMA2Bus_MstWr_rem( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
IP2Bus_MstWr_sof_n => MAC_DMA2Bus_MstWr_sof_n,
IP2Bus_MstWr_src_dsc_n => MAC_DMA2Bus_MstWr_src_dsc_n,
IP2Bus_MstWr_src_rdy_n => MAC_DMA2Bus_MstWr_src_rdy_n,
IP2Bus_Mst_Addr => MAC_DMA2Bus_Mst_Addr( 0 to C_MAC_DMA_PLB_AWIDTH-1 ),
IP2Bus_Mst_BE => MAC_DMA2Bus_Mst_BE( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
IP2Bus_Mst_Length => MAC_DMA2Bus_Mst_Length,
IP2Bus_Mst_Lock => MAC_DMA2Bus_Mst_Lock,
IP2Bus_Mst_Reset => MAC_DMA2Bus_Mst_Reset,
IP2Bus_Mst_Type => MAC_DMA2Bus_Mst_Type,
MD_Error => MAC_DMA_error,
MPLB_Clk => MAC_DMA_Clk,
MPLB_Rst => MAC_DMA_Rst,
M_ABus => MAC_DMA_ABus,
M_BE => MAC_DMA_BE( 0 to (C_MAC_DMA_PLB_DWIDTH/8)-1 ),
M_MSize => MAC_DMA_MSize,
M_RNW => MAC_DMA_RNW,
M_TAttribute => MAC_DMA_TAttribute,
M_UABus => MAC_DMA_UABus,
M_abort => MAC_DMA_abort,
M_busLock => MAC_DMA_busLock,
M_lockErr => MAC_DMA_lockErr,
M_priority => MAC_DMA_priority,
M_rdBurst => MAC_DMA_rdBurst,
M_request => MAC_DMA_request,
M_size => MAC_DMA_size,
M_type => MAC_DMA_type,
M_wrBurst => MAC_DMA_wrBurst,
M_wrDBus => MAC_DMA_wrDBus( 0 to C_MAC_DMA_PLB_DWIDTH-1 ),
PLB_MAddrAck => MAC_DMA_MAddrAck,
PLB_MBusy => MAC_DMA_MBusy,
PLB_MIRQ => MAC_DMA_MIRQ,
PLB_MRdBTerm => MAC_DMA_MRdBTerm,
PLB_MRdDAck => MAC_DMA_MRdDAck,
PLB_MRdDBus => MAC_DMA_MRdDBus( 0 to C_MAC_DMA_PLB_DWIDTH-1 ),
PLB_MRdErr => MAC_DMA_MRdErr,
PLB_MRdWdAddr => MAC_DMA_MRdWdAddr,
PLB_MRearbitrate => MAC_DMA_MRearbitrate,
PLB_MSSize => MAC_DMA_MSSize,
PLB_MTimeout => MAC_DMA_MTimeout,
PLB_MWrBTerm => MAC_DMA_MWrBTerm,
PLB_MWrDAck => MAC_DMA_MWrDAck,
PLB_MWrErr => MAC_DMA_MWrErr
);
end generate genMacDmaPlbBurst;
oddr2_0 : if not C_INSTANCE_ODDR2 generate
begin
phy0_clk <= clk50;
phy1_clk <= clk50;
end generate oddr2_0;
oddr2_1 : if C_INSTANCE_ODDR2 generate
begin
U4 : ODDR2
port map(
C0 => clk50,
C1 => NET118078,
CE => VCC,
D0 => VCC,
D1 => GND,
Q => phy0_clk,
R => GND,
S => GND
);
NET118078 <= not(clk50);
U6 : ODDR2
port map(
C0 => clk50,
C1 => NET118214,
CE => VCC,
D0 => VCC,
D1 => GND,
Q => phy1_clk,
R => GND,
S => GND
);
NET118214 <= not(clk50);
end generate oddr2_1;
genThePlbMaster : if C_DMA_EN = TRUE generate
begin
THE_IPIF_MASTER_HANDLER : ipif_master_handler
generic map (
dma_highadr_g => m_address'high,
gen_rx_fifo_g => not C_RX_INT_PKT,
gen_tx_fifo_g => not C_TX_INT_PKT,
m_burstcount_width_g => C_M_BURSTCOUNT_WIDTH
)
port map(
Bus2MAC_DMA_MstRd_d => Bus2MAC_DMA_MstRd_d_s( C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0 ),
Bus2MAC_DMA_MstRd_eof_n => Bus2MAC_DMA_MstRd_eof_n,
Bus2MAC_DMA_MstRd_rem => Bus2MAC_DMA_MstRd_rem( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
Bus2MAC_DMA_MstRd_sof_n => Bus2MAC_DMA_MstRd_sof_n,
Bus2MAC_DMA_MstRd_src_dsc_n => Bus2MAC_DMA_MstRd_src_dsc_n,
Bus2MAC_DMA_MstRd_src_rdy_n => Bus2MAC_DMA_MstRd_src_rdy_n,
Bus2MAC_DMA_MstWr_dst_dsc_n => Bus2MAC_DMA_MstWr_dst_dsc_n,
Bus2MAC_DMA_MstWr_dst_rdy_n => Bus2MAC_DMA_MstWr_dst_rdy_n,
Bus2MAC_DMA_Mst_CmdAck => Bus2MAC_DMA_Mst_CmdAck,
Bus2MAC_DMA_Mst_Cmd_Timeout => Bus2MAC_DMA_Mst_Cmd_Timeout,
Bus2MAC_DMA_Mst_Cmplt => Bus2MAC_DMA_Mst_Cmplt,
Bus2MAC_DMA_Mst_Error => Bus2MAC_DMA_Mst_Error,
Bus2MAC_DMA_Mst_Rearbitrate => Bus2MAC_DMA_Mst_Rearbitrate,
MAC_DMA2Bus_MstRd_Req => MAC_DMA2Bus_MstRd_Req,
MAC_DMA2Bus_MstRd_dst_dsc_n => MAC_DMA2Bus_MstRd_dst_dsc_n,
MAC_DMA2Bus_MstRd_dst_rdy_n => MAC_DMA2Bus_MstRd_dst_rdy_n,
MAC_DMA2Bus_MstWr_Req => MAC_DMA2Bus_MstWr_Req,
MAC_DMA2Bus_MstWr_d => MAC_DMA2Bus_MstWr_d_s( C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0 ),
MAC_DMA2Bus_MstWr_eof_n => MAC_DMA2Bus_MstWr_eof_n,
MAC_DMA2Bus_MstWr_rem => MAC_DMA2Bus_MstWr_rem( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
MAC_DMA2Bus_MstWr_sof_n => MAC_DMA2Bus_MstWr_sof_n,
MAC_DMA2Bus_MstWr_src_dsc_n => MAC_DMA2Bus_MstWr_src_dsc_n,
MAC_DMA2Bus_MstWr_src_rdy_n => MAC_DMA2Bus_MstWr_src_rdy_n,
MAC_DMA2Bus_Mst_Addr => MAC_DMA2Bus_Mst_Addr( 0 to C_MAC_DMA_PLB_AWIDTH-1 ),
MAC_DMA2Bus_Mst_BE => MAC_DMA2Bus_Mst_BE( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
MAC_DMA2Bus_Mst_Length => MAC_DMA2Bus_Mst_Length,
MAC_DMA2Bus_Mst_Lock => MAC_DMA2Bus_Mst_Lock,
MAC_DMA2Bus_Mst_Reset => MAC_DMA2Bus_Mst_Reset,
MAC_DMA2Bus_Mst_Type => MAC_DMA2Bus_Mst_Type,
MAC_DMA_CLK => MAC_DMA_CLK,
MAC_DMA_Rst => MAC_DMA_Rst,
m_address => m_address( 31 downto 0 ),
m_burstcount => m_burstcount( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_burstcounter => m_burstcounter( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_byteenable => m_byteenable,
m_clk => m_clk,
m_read => m_read,
m_readdata => m_readdata,
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
m_writedata => m_writedata
);
Bus2MAC_DMA_MstRd_d_s <= Bus2MAC_DMA_MstRd_d(7 downto 0) & Bus2MAC_DMA_MstRd_d(15 downto 8) &
Bus2MAC_DMA_MstRd_d(23 downto 16) & Bus2MAC_DMA_MstRd_d(31 downto 24);
MAC_DMA2Bus_MstWr_d <= MAC_DMA2Bus_MstWr_d_s(7 downto 0) & MAC_DMA2Bus_MstWr_d_s(15 downto 8) &
MAC_DMA2Bus_MstWr_d_s(23 downto 16) & MAC_DMA2Bus_MstWr_d_s(31 downto 24);
end generate genThePlbMaster;
genMacPktPLbSingleSlave : if C_PKT_BUF_EN generate
begin
MAC_PKT_PLB_SINGLE_SLAVE : plbv46_slave_single
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_MAC_PKT_BASE,C_MAC_PKT_HIGH),
C_ARD_NUM_CE_ARRAY => (0 => 1),
C_BUS2CORE_CLK_RATIO => 1,
C_FAMILY => C_FAMILY,
C_INCLUDE_DPHASE_TIMER => 0,
C_SIPIF_DWIDTH => C_MAC_PKT_PLB_DWIDTH,
C_SPLB_AWIDTH => C_MAC_PKT_PLB_AWIDTH,
C_SPLB_DWIDTH => C_MAC_PKT_PLB_DWIDTH,
C_SPLB_MID_WIDTH => C_MAC_PKT_PLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_MAC_PKT_PLB_NUM_MASTERS,
C_SPLB_P2P => C_MAC_PKT_PLB_P2P
)
port map(
Bus2IP_Addr => Bus2MAC_PKT_Addr( C_MAC_PKT_PLB_AWIDTH-1 downto 0 ),
Bus2IP_BE => Bus2MAC_PKT_BE( (C_MAC_PKT_PLB_DWIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2MAC_PKT_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2MAC_PKT_Clk,
Bus2IP_Data => Bus2MAC_PKT_Data( C_MAC_PKT_PLB_DWIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2MAC_PKT_RNW,
Bus2IP_Reset => Bus2MAC_PKT_Reset,
IP2Bus_Data => MAC_PKT2Bus_Data( C_MAC_PKT_PLB_DWIDTH-1 downto 0 ),
IP2Bus_Error => MAC_PKT2Bus_Error,
IP2Bus_RdAck => MAC_PKT2Bus_RdAck,
IP2Bus_WrAck => MAC_PKT2Bus_WrAck,
PLB_ABus => MAC_PKT_ABus,
PLB_BE => MAC_PKT_BE( 0 to (C_MAC_PKT_PLB_DWIDTH/8)-1 ),
PLB_MSize => MAC_PKT_MSize,
PLB_PAValid => MAC_PKT_PAValid,
PLB_RNW => MAC_PKT_RNW,
PLB_SAValid => MAC_PKT_SAValid,
PLB_TAttribute => MAC_PKT_TAttribute,
PLB_UABus => MAC_PKT_UABus,
PLB_abort => MAC_PKT_abort,
PLB_busLock => MAC_PKT_busLock,
PLB_lockErr => MAC_PKT_lockErr,
PLB_masterID => MAC_PKT_masterID( 0 to C_MAC_PKT_PLB_MID_WIDTH-1 ),
PLB_rdBurst => MAC_PKT_rdBurst,
PLB_rdPendPri => MAC_PKT_rdPendPri,
PLB_rdPendReq => MAC_PKT_rdPendReq,
PLB_rdPrim => MAC_PKT_rdPrim,
PLB_reqPri => MAC_PKT_reqPri,
PLB_size => MAC_PKT_size,
PLB_type => MAC_PKT_type,
PLB_wrBurst => MAC_PKT_wrBurst,
PLB_wrDBus => MAC_PKT_wrDBus( 0 to C_MAC_PKT_PLB_DWIDTH-1 ),
PLB_wrPendPri => MAC_PKT_wrPendPri,
PLB_wrPendReq => MAC_PKT_wrPendReq,
PLB_wrPrim => MAC_PKT_wrPrim,
SPLB_Clk => MAC_PKT_Clk,
SPLB_Rst => MAC_PKT_Rst,
Sl_MBusy => MAC_PKT_MBusy( 0 to C_MAC_PKT_NUM_MASTERS-1 ),
Sl_MIRQ => MAC_PKT_MIRQ( 0 to C_MAC_PKT_NUM_MASTERS-1 ),
Sl_MRdErr => MAC_PKT_MRdErr( 0 to C_MAC_PKT_NUM_MASTERS-1 ),
Sl_MWrErr => MAC_PKT_MWrErr( 0 to C_MAC_PKT_NUM_MASTERS-1 ),
Sl_SSize => MAC_PKT_SSize,
Sl_addrAck => MAC_PKT_addrAck,
Sl_rdBTerm => MAC_PKT_rdBTerm,
Sl_rdComp => MAC_PKT_rdComp,
Sl_rdDAck => MAC_PKT_rdDAck,
Sl_rdDBus => MAC_PKT_rdDBus( 0 to C_MAC_PKT_PLB_DWIDTH-1 ),
Sl_rdWdAddr => MAC_PKT_rdWdAddr,
Sl_rearbitrate => MAC_PKT_rearbitrate,
Sl_wait => MAC_PKT_wait,
Sl_wrBTerm => MAC_PKT_wrBTerm,
Sl_wrComp => MAC_PKT_wrComp,
Sl_wrDAck => MAC_PKT_wrDAck
);
end generate genMacPktPLbSingleSlave;
genPdiPcp : if (C_GEN_PDI) generate
begin
PDI_PCP_PLB_SINGLE_SLAVE : plbv46_slave_single
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_PDI_PCP_BASE,C_PDI_PCP_HIGH),
C_ARD_NUM_CE_ARRAY => (0 => 1),
C_BUS2CORE_CLK_RATIO => 1,
C_FAMILY => C_FAMILY,
C_INCLUDE_DPHASE_TIMER => 0,
C_SIPIF_DWIDTH => C_PDI_PCP_PLB_DWIDTH,
C_SPLB_AWIDTH => C_PDI_PCP_PLB_AWIDTH,
C_SPLB_DWIDTH => C_PDI_PCP_PLB_DWIDTH,
C_SPLB_MID_WIDTH => C_PDI_PCP_PLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_PDI_PCP_PLB_NUM_MASTERS,
C_SPLB_P2P => C_PDI_PCP_PLB_P2P
)
port map(
Bus2IP_Addr => Bus2PDI_PCP_Addr( C_PDI_PCP_PLB_AWIDTH-1 downto 0 ),
Bus2IP_BE => Bus2PDI_PCP_BE( (C_PDI_PCP_PLB_DWIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2PDI_PCP_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2PDI_PCP_Clk,
Bus2IP_Data => Bus2PDI_PCP_Data( C_PDI_PCP_PLB_DWIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2PDI_PCP_RNW,
Bus2IP_Reset => Bus2PDI_PCP_Reset,
IP2Bus_Data => PDI_PCP2Bus_Data( C_PDI_PCP_PLB_DWIDTH-1 downto 0 ),
IP2Bus_Error => PDI_PCP2Bus_Error,
IP2Bus_RdAck => PDI_PCP2Bus_RdAck,
IP2Bus_WrAck => PDI_PCP2Bus_WrAck,
PLB_ABus => PDI_PCP_ABus,
PLB_BE => PDI_PCP_BE( 0 to (C_PDI_PCP_PLB_DWIDTH/8)-1 ),
PLB_MSize => PDI_PCP_MSize,
PLB_PAValid => PDI_PCP_PAValid,
PLB_RNW => PDI_PCP_RNW,
PLB_SAValid => PDI_PCP_SAValid,
PLB_TAttribute => PDI_PCP_TAttribute,
PLB_UABus => PDI_PCP_UABus,
PLB_abort => PDI_PCP_abort,
PLB_busLock => PDI_PCP_busLock,
PLB_lockErr => PDI_PCP_lockErr,
PLB_masterID => PDI_PCP_masterID( 0 to C_PDI_PCP_PLB_MID_WIDTH-1 ),
PLB_rdBurst => PDI_PCP_rdBurst,
PLB_rdPendPri => PDI_PCP_rdPendPri,
PLB_rdPendReq => PDI_PCP_rdPendReq,
PLB_rdPrim => PDI_PCP_rdPrim,
PLB_reqPri => PDI_PCP_reqPri,
PLB_size => PDI_PCP_size,
PLB_type => PDI_PCP_type,
PLB_wrBurst => PDI_PCP_wrBurst,
PLB_wrDBus => PDI_PCP_wrDBus( 0 to C_PDI_PCP_PLB_DWIDTH-1 ),
PLB_wrPendPri => PDI_PCP_wrPendPri,
PLB_wrPendReq => PDI_PCP_wrPendReq,
PLB_wrPrim => PDI_PCP_wrPrim,
SPLB_Clk => PDI_PCP_Clk,
SPLB_Rst => PDI_PCP_Rst,
Sl_MBusy => PDI_PCP_MBusy( 0 to C_PDI_PCP_NUM_MASTERS-1 ),
Sl_MIRQ => PDI_PCP_MIRQ( 0 to C_PDI_PCP_NUM_MASTERS-1 ),
Sl_MRdErr => PDI_PCP_MRdErr( 0 to C_PDI_PCP_NUM_MASTERS-1 ),
Sl_MWrErr => PDI_PCP_MWrErr( 0 to C_PDI_PCP_NUM_MASTERS-1 ),
Sl_SSize => PDI_PCP_SSize,
Sl_addrAck => PDI_PCP_addrAck,
Sl_rdBTerm => PDI_PCP_rdBTerm,
Sl_rdComp => PDI_PCP_rdComp,
Sl_rdDAck => PDI_PCP_rdDAck,
Sl_rdDBus => PDI_PCP_rdDBus( 0 to C_PDI_PCP_PLB_DWIDTH-1 ),
Sl_rdWdAddr => PDI_PCP_rdWdAddr,
Sl_rearbitrate => PDI_PCP_rearbitrate,
Sl_wait => PDI_PCP_wait,
Sl_wrBTerm => PDI_PCP_wrBTerm,
Sl_wrComp => PDI_PCP_wrComp,
Sl_wrDAck => PDI_PCP_wrDAck
);
end generate genPdiPcp;
genPcpPdiLink : if C_GEN_PDI generate
begin
--pdi_pcp assignments
clkPcp <= Bus2PDI_PCP_Clk;
rstPcp <= Bus2PDI_PCP_Reset;
--pcp_writedata <= Bus2PDI_PCP_Data;
pcp_writedata <= Bus2PDI_PCP_Data(7 downto 0) & Bus2PDI_PCP_Data(15 downto 8) & Bus2PDI_PCP_Data(23 downto 16) & Bus2PDI_PCP_Data(31 downto 24);
--pcp_writedata <= Bus2PDI_PCP_Data(15 downto 0) & Bus2PDI_PCP_Data(31 downto 16) when Bus2PDI_PCP_BE = "1100" or Bus2PDI_PCP_BE = "0011" else
-- Bus2PDI_PCP_Data(15 downto 8) & Bus2PDI_PCP_Data(7 downto 0) & Bus2PDI_PCP_Data(31 downto 24) & Bus2PDI_PCP_Data(23 downto 16) when Bus2PDI_PCP_BE = "1000" or Bus2PDI_PCP_BE = "0100" or Bus2PDI_PCP_BE = "0010" or Bus2PDI_PCP_BE = "0001" else
-- Bus2PDI_PCP_Data;
pcp_read <= Bus2PDI_PCP_RNW;
pcp_write <= not Bus2PDI_PCP_RNW;
pcp_chipselect <= Bus2PDI_PCP_CS(0);
--pcp_byteenable <= Bus2PDI_PCP_BE;
pcp_byteenable <= Bus2PDI_PCP_BE(0) & Bus2PDI_PCP_BE(1) & Bus2PDI_PCP_BE(2) & Bus2PDI_PCP_BE(3);
pcp_address <= Bus2PDI_PCP_Addr(14 downto 2);
--PDI_PCP2Bus_Data <= pcp_readdata;
PDI_PCP2Bus_Data <= pcp_readdata(7 downto 0) & pcp_readdata(15 downto 8) & pcp_readdata(23 downto 16) & pcp_readdata(31 downto 24);
PDI_PCP2Bus_RdAck <= pcp_chipselect and pcp_read and not pcp_waitrequest;
PDI_PCP2Bus_WrAck <= pcp_chipselect and pcp_write and not pcp_waitrequest;
PDI_PCP2Bus_Error <= '0';
end generate genPcpPdiLink;
genPdiAp : if (C_GEN_PLB_BUS_IF) generate
begin
PDI_AP_PLB_SINGLE_SLAVE : plbv46_slave_single
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_PDI_AP_BASE,C_PDI_AP_HIGH),
C_ARD_NUM_CE_ARRAY => (0 => 1),
C_BUS2CORE_CLK_RATIO => 1,
C_FAMILY => C_FAMILY,
C_INCLUDE_DPHASE_TIMER => 0,
C_SIPIF_DWIDTH => C_PDI_AP_PLB_DWIDTH,
C_SPLB_AWIDTH => C_PDI_AP_PLB_AWIDTH,
C_SPLB_DWIDTH => C_PDI_AP_PLB_DWIDTH,
C_SPLB_MID_WIDTH => C_PDI_AP_PLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_PDI_AP_PLB_NUM_MASTERS,
C_SPLB_P2P => C_PDI_AP_PLB_P2P
)
port map(
Bus2IP_Addr => Bus2PDI_AP_Addr( C_PDI_AP_PLB_AWIDTH-1 downto 0 ),
Bus2IP_BE => Bus2PDI_AP_BE( (C_PDI_AP_PLB_DWIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2PDI_AP_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2PDI_AP_Clk,
Bus2IP_Data => Bus2PDI_AP_Data( C_PDI_AP_PLB_DWIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2PDI_AP_RNW,
Bus2IP_Reset => Bus2PDI_AP_Reset,
IP2Bus_Data => PDI_AP2Bus_Data( C_PDI_AP_PLB_DWIDTH-1 downto 0 ),
IP2Bus_Error => PDI_AP2Bus_Error,
IP2Bus_RdAck => PDI_AP2Bus_RdAck,
IP2Bus_WrAck => PDI_AP2Bus_WrAck,
PLB_ABus => PDI_AP_ABus,
PLB_BE => PDI_AP_BE( 0 to (C_PDI_AP_PLB_DWIDTH/8)-1 ),
PLB_MSize => PDI_AP_MSize,
PLB_PAValid => PDI_AP_PAValid,
PLB_RNW => PDI_AP_RNW,
PLB_SAValid => PDI_AP_SAValid,
PLB_TAttribute => PDI_AP_TAttribute,
PLB_UABus => PDI_AP_UABus,
PLB_abort => PDI_AP_abort,
PLB_busLock => PDI_AP_busLock,
PLB_lockErr => PDI_AP_lockErr,
PLB_masterID => PDI_AP_masterID( 0 to C_PDI_AP_PLB_MID_WIDTH-1 ),
PLB_rdBurst => PDI_AP_rdBurst,
PLB_rdPendPri => PDI_AP_rdPendPri,
PLB_rdPendReq => PDI_AP_rdPendReq,
PLB_rdPrim => PDI_AP_rdPrim,
PLB_reqPri => PDI_AP_reqPri,
PLB_size => PDI_AP_size,
PLB_type => PDI_AP_type,
PLB_wrBurst => PDI_AP_wrBurst,
PLB_wrDBus => PDI_AP_wrDBus( 0 to C_PDI_AP_PLB_DWIDTH-1 ),
PLB_wrPendPri => PDI_AP_wrPendPri,
PLB_wrPendReq => PDI_AP_wrPendReq,
PLB_wrPrim => PDI_AP_wrPrim,
SPLB_Clk => PDI_AP_Clk,
SPLB_Rst => PDI_AP_Rst,
Sl_MBusy => PDI_AP_MBusy( 0 to C_PDI_AP_PLB_NUM_MASTERS-1 ),
Sl_MIRQ => PDI_AP_MIRQ( 0 to C_PDI_AP_PLB_NUM_MASTERS-1 ),
Sl_MRdErr => PDI_AP_MRdErr( 0 to C_PDI_AP_PLB_NUM_MASTERS-1 ),
Sl_MWrErr => PDI_AP_MWrErr( 0 to C_PDI_AP_PLB_NUM_MASTERS-1 ),
Sl_SSize => PDI_AP_SSize,
Sl_addrAck => PDI_AP_addrAck,
Sl_rdBTerm => PDI_AP_rdBTerm,
Sl_rdComp => PDI_AP_rdComp,
Sl_rdDAck => PDI_AP_rdDAck,
Sl_rdDBus => PDI_AP_rdDBus( 0 to C_PDI_AP_PLB_DWIDTH-1 ),
Sl_rdWdAddr => PDI_AP_rdWdAddr,
Sl_rearbitrate => PDI_AP_rearbitrate,
Sl_wait => PDI_AP_wait,
Sl_wrBTerm => PDI_AP_wrBTerm,
Sl_wrComp => PDI_AP_wrComp,
Sl_wrDAck => PDI_AP_wrDAck
);
end generate genPdiAp;
genApPdiLink : if C_GEN_PDI generate
begin
--ap_pcp assignments
clkAp <= Bus2PDI_AP_Clk;
rstAp <= Bus2PDI_AP_Reset;
--ap_writedata <= Bus2PDI_AP_Data;
ap_writedata <= Bus2PDI_AP_Data(7 downto 0) & Bus2PDI_AP_Data(15 downto 8) & Bus2PDI_AP_Data(23 downto 16) & Bus2PDI_AP_Data(31 downto 24);
ap_read <= Bus2PDI_AP_RNW;
ap_write <= not Bus2PDI_AP_RNW;
ap_chipselect <= Bus2PDI_AP_CS(0);
--ap_byteenable <= Bus2PDI_AP_BE;
ap_byteenable <= Bus2PDI_AP_BE(0) & Bus2PDI_AP_BE(1) & Bus2PDI_AP_BE(2) & Bus2PDI_AP_BE(3);
ap_address <= Bus2PDI_AP_Addr(14 downto 2);
--PDI_AP2Bus_Data <= ap_readdata;
PDI_AP2Bus_Data <= ap_readdata(7 downto 0) & ap_readdata(15 downto 8) & ap_readdata(23 downto 16) & ap_readdata(31 downto 24);
PDI_AP2Bus_RdAck <= ap_chipselect and ap_read and not ap_waitrequest;
PDI_AP2Bus_WrAck <= ap_chipselect and ap_write and not ap_waitrequest;
PDI_AP2Bus_Error <= '0';
end generate genApPdiLink;
genSimpleIoSignals : if C_GEN_SIMPLE_IO generate
begin
--SMP_PCP assignments
clkPcp <= Bus2SMP_PCP_Clk;
rstPcp <= Bus2SMP_PCP_Reset;
--smp_writedata <= Bus2SMP_PCP_Data;
smp_writedata <= Bus2SMP_PCP_Data(7 downto 0) & Bus2SMP_PCP_Data(15 downto 8) & Bus2SMP_PCP_Data(23 downto 16) & Bus2SMP_PCP_Data(31 downto 24);
smp_read <= Bus2SMP_PCP_RNW and Bus2SMP_PCP_CS(0);
smp_write <= not Bus2SMP_PCP_RNW and Bus2SMP_PCP_CS(0);
smp_chipselect <= Bus2SMP_PCP_CS(0);
--smp_byteenable <= Bus2SMP_PCP_BE;
smp_byteenable <= Bus2SMP_PCP_BE(0) & Bus2SMP_PCP_BE(1) & Bus2SMP_PCP_BE(2) & Bus2SMP_PCP_BE(3);
smp_address <= Bus2SMP_PCP_Addr(2);
--SMP_PCP2Bus_Data <= smp_readdata;
SMP_PCP2Bus_Data <= smp_readdata(7 downto 0) & smp_readdata(15 downto 8) & smp_readdata(23 downto 16) & smp_readdata(31 downto 24);
SMP_PCP2Bus_RdAck <= smp_chipselect and smp_read and not smp_waitrequest;
SMP_PCP2Bus_WrAck <= smp_chipselect and smp_write and not smp_waitrequest;
SMP_PCP2Bus_Error <= '0';
end generate genSimpleIoSignals;
genSmpIo : if (C_GEN_SIMPLE_IO) generate
begin
SMP_IO_PLB_SINGLE_SLAVE : plbv46_slave_single
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_SMP_PCP_BASE,C_SMP_PCP_HIGH),
C_ARD_NUM_CE_ARRAY => (0 => 1),
C_BUS2CORE_CLK_RATIO => 1,
C_FAMILY => C_FAMILY,
C_INCLUDE_DPHASE_TIMER => 0,
C_SIPIF_DWIDTH => C_SMP_PCP_PLB_DWIDTH,
C_SPLB_AWIDTH => C_SMP_PCP_PLB_AWIDTH,
C_SPLB_DWIDTH => C_SMP_PCP_PLB_DWIDTH,
C_SPLB_MID_WIDTH => C_SMP_PCP_PLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SMP_PCP_PLB_NUM_MASTERS,
C_SPLB_P2P => C_SMP_PCP_PLB_P2P
)
port map(
Bus2IP_Addr => Bus2SMP_PCP_Addr( C_SMP_PCP_PLB_AWIDTH-1 downto 0 ),
Bus2IP_BE => Bus2SMP_PCP_BE( (C_SMP_PCP_PLB_DWIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2SMP_PCP_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2SMP_PCP_Clk,
Bus2IP_Data => Bus2SMP_PCP_Data( C_SMP_PCP_PLB_DWIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2SMP_PCP_RNW,
Bus2IP_Reset => Bus2SMP_PCP_Reset,
IP2Bus_Data => SMP_PCP2Bus_Data( C_SMP_PCP_PLB_DWIDTH-1 downto 0 ),
IP2Bus_Error => SMP_PCP2Bus_Error,
IP2Bus_RdAck => SMP_PCP2Bus_RdAck,
IP2Bus_WrAck => SMP_PCP2Bus_WrAck,
PLB_ABus => SMP_PCP_ABus,
PLB_BE => SMP_PCP_BE( 0 to (C_SMP_PCP_PLB_DWIDTH/8)-1 ),
PLB_MSize => SMP_PCP_MSize,
PLB_PAValid => SMP_PCP_PAValid,
PLB_RNW => SMP_PCP_RNW,
PLB_SAValid => SMP_PCP_SAValid,
PLB_TAttribute => SMP_PCP_TAttribute,
PLB_UABus => SMP_PCP_UABus,
PLB_abort => SMP_PCP_abort,
PLB_busLock => SMP_PCP_busLock,
PLB_lockErr => SMP_PCP_lockErr,
PLB_masterID => SMP_PCP_masterID( 0 to C_SMP_PCP_PLB_MID_WIDTH-1 ),
PLB_rdBurst => SMP_PCP_rdBurst,
PLB_rdPendPri => SMP_PCP_rdPendPri,
PLB_rdPendReq => SMP_PCP_rdPendReq,
PLB_rdPrim => SMP_PCP_rdPrim,
PLB_reqPri => SMP_PCP_reqPri,
PLB_size => SMP_PCP_size,
PLB_type => SMP_PCP_type,
PLB_wrBurst => SMP_PCP_wrBurst,
PLB_wrDBus => SMP_PCP_wrDBus( 0 to C_SMP_PCP_PLB_DWIDTH-1 ),
PLB_wrPendPri => SMP_PCP_wrPendPri,
PLB_wrPendReq => SMP_PCP_wrPendReq,
PLB_wrPrim => SMP_PCP_wrPrim,
SPLB_Clk => SMP_PCP_Clk,
SPLB_Rst => SMP_PCP_Rst,
Sl_MBusy => SMP_PCP_MBusy( 0 to C_SMP_PCP_PLB_NUM_MASTERS-1 ),
Sl_MIRQ => SMP_PCP_MIRQ( 0 to C_SMP_PCP_PLB_NUM_MASTERS-1 ),
Sl_MRdErr => SMP_PCP_MRdErr( 0 to C_SMP_PCP_PLB_NUM_MASTERS-1 ),
Sl_MWrErr => SMP_PCP_MWrErr( 0 to C_SMP_PCP_PLB_NUM_MASTERS-1 ),
Sl_SSize => SMP_PCP_SSize,
Sl_addrAck => SMP_PCP_addrAck,
Sl_rdBTerm => SMP_PCP_rdBTerm,
Sl_rdComp => SMP_PCP_rdComp,
Sl_rdDAck => SMP_PCP_rdDAck,
Sl_rdDBus => SMP_PCP_rdDBus( 0 to C_SMP_PCP_PLB_DWIDTH-1 ),
Sl_rdWdAddr => SMP_PCP_rdWdAddr,
Sl_rearbitrate => SMP_PCP_rearbitrate,
Sl_wait => SMP_PCP_wait,
Sl_wrBTerm => SMP_PCP_wrBTerm,
Sl_wrComp => SMP_PCP_wrComp,
Sl_wrDAck => SMP_PCP_wrDAck
);
end generate genSmpIo;
end struct;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:27:29 11/20/2013
-- Design Name:
-- Module Name: Selector - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.MyTypes.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Selector is
generic (
num_sum: integer := 0;
num_buffer: integer := 0
);
Port ( cIn : in PairT;
cSel : in PairT;
cOut : out PairT;
sumIn : in PairArr(num_sum downto 0);
sumOut : out PairArr(num_sum downto 0);
bufferIn: in PairArr(num_buffer downto 0);
bufferOut:out PairArr(num_buffer downto 0));
end Selector;
architecture Behavioral of Selector is
begin
process (cIn, cSel, sumIn)
begin
if (cSel(0) = cSel(1)) then
if (cSel(0) = '0') then
for index in 0 to num_sum loop
sumOut(index) <= (1 downto 0 => sumIn(index)(0));
end loop;
cOut <= (1 downto 0 => cIn(0));
else
for index in 0 to num_sum loop
sumOut(index) <= (1 downto 0 => sumIn(index)(1));
end loop;
cOut <= (1 downto 0 => cIn(1));
end if;
else
for index in 0 to num_sum loop
sumOut <= sumIn;
end loop;
cOut <= cIn;
end if;
end process;
bufferOut <= bufferIn;
end Behavioral; |
library verilog;
use verilog.vl_types.all;
entity MEM_WR is
port(
clk : in vl_logic;
stall : in vl_logic;
flush : in vl_logic;
MemData_Mem : in vl_logic_vector(31 downto 0);
Rd_write_byte_en_Mem: in vl_logic_vector(3 downto 0);
WBData_Mem : in vl_logic_vector(31 downto 0);
MemRead_Mem : in vl_logic;
RegWrite_Mem : in vl_logic;
Rd_Mem : in vl_logic_vector(4 downto 0);
MemData_Wr : out vl_logic_vector(31 downto 0);
Rd_write_byte_en_Wr: out vl_logic_vector(3 downto 0);
WBData_Wr : out vl_logic_vector(31 downto 0);
MemRead_Wr : out vl_logic;
RegWrite_Wr : out vl_logic;
Rd_Wr : out vl_logic_vector(4 downto 0)
);
end MEM_WR;
|
-- megafunction wizard: %LPM_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_add_sub
-- ============================================================
-- File Name: add.vhd
-- Megafunction Name(s):
-- lpm_add_sub
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY add IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END add;
ARCHITECTURE SYN OF add IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(7 DOWNTO 0);
lpm_add_sub_component : lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_ADD_SUB",
lpm_width => 8
)
PORT MAP (
dataa => dataa,
datab => datab,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: ConstantA NUMERIC "0"
-- Retrieval info: PRIVATE: ConstantB NUMERIC "0"
-- Retrieval info: PRIVATE: Function NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: Overflow NUMERIC "0"
-- Retrieval info: PRIVATE: RadixA NUMERIC "10"
-- Retrieval info: PRIVATE: RadixB NUMERIC "10"
-- Retrieval info: PRIVATE: Representation NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
-- Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
-- Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL dataa[7..0]
-- Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL datab[7..0]
-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0]
-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
-- Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
-- Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL add.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL add.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL add.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL add.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL add_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL add_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL add_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
--------------------------------------------------------------
------------------------------------------------------------
-- adder.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(addend1,addend2:in std_logic_vector(3 downto 0);
sum:out std_logic_vector(3 downto 0));
end adder;
architecture add of adder is
begin
sum<=addend1+addend2;
end add;
--------------------------------------------------------------
------------------------------------------------------------
-- comparator.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity comparator is
port(point:in std_logic_vector(3 downto 0);
sum:in std_logic_vector(3 downto 0);
eq:out bit);
end comparator;
architecture compare of comparator is
begin
--could be alternatived by MUX statements...3 lines...--
process(point,sum)
begin
if point=sum then
eq<='1';
else eq<='0';
end if;
end process;
end compare;
--------------------------------------------------------------
------------------------------------------------------------
-- control.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity control is
port(reset,rb,eq,d7,d711,d2312:in bit;
roll,win,lose,sp:out bit);
end control;
architecture con of control is
signal count:std_logic_vector(3 downto 0):="0000";
signal w,l:bit;
begin
process(reset,rb)
begin
if reset='0' then
sp<='1';
count<="0000";
elsif rb'event and rb='1' then
count<=count+1;
elsif rb'event and rb='0' and count="0001" then
sp<='0';
end if;
roll<=not rb;
end process;
process(count,eq,d7,d711,d2312)
begin
--if w='0' and l='0' then
if count="0000" then
w <='0';l <='0';
elsif count="0001" then
w <=d711;l <=d2312;
else
w <=eq;l <=d7;
end if;
--end if;
end process;
win<=w;
lose<=l;
end con;
--------------------------------------------------------------
------------------------------------------------------------
-- counter_1_6.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter_1_6 is
port(clk_50m,roll:in bit;
out_count:inout std_logic_vector(3 downto 0));
end counter_1_6;
architecture count of counter_1_6 is
signal count:std_logic_vector(3 downto 0):="0000";
begin
process(clk_50m,roll,count)
begin
if roll='1' then
if clk_50m'event and clk_50m='0' then
if count>"0100" then
count<="0001";
else count<=count+1;
end if;
end if;
else out_count<=count;
end if;
end process;
end count;
--------------------------------------------------------------
------------------------------------------------------------
-- decoder_1_6.vhd
------------------------------------------------------------
--------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY decoder_1_6 IS
PORT(
m:IN STD_LOGIC_vector(3 downto 0);
led_vector:out bit_vector(7 DOWNTO 0));
END decoder_1_6;
ARCHITECTURE decoder_architecture OF decoder_1_6 IS
BEGIN
PROCESS(m)
BEGIN
CASE m IS
WHEN "0001" => led_vector<="11111001";--F9=>1
WHEN "0010" => led_vector<="10100100";--A4=>2
WHEN "0011" => led_vector<="10110000";--B0=>3
WHEN "0100" => led_vector<="10011001";--99=>4
WHEN "0101" => led_vector<="10010010";--92=>5
WHEN "0110" => led_vector<="10000010";--82=>6
WHEN others => led_vector<="11111111";--FF=>²»ÁÁ
END CASE;
END PROCESS;
END decoder_architecture;
--------------------------------------------------------------
------------------------------------------------------------
-- lab50.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lab50 is
port(reset,rb,clk_50m,clk_28m:in bit;
win,lose:out bit;
led1,led2:out bit_vector(7 downto 0));
end lab50;
architecture allmap of lab50 is
component counter_1_6 is
port(clk_50m,roll:in bit;
out_count:inout std_logic_vector(3 downto 0));
end component;
component decoder_1_6 IS
PORT(m:IN STD_LOGIC_vector(3 downto 0);
led_vector:out bit_vector(7 DOWNTO 0));
end component;
component adder is
port(addend1,addend2:in std_logic_vector(3 downto 0);
sum:out std_logic_vector(3 downto 0));
end component;
component point_register is
port(sp:in bit;
point:out std_logic_vector(3 downto 0);
sum:in std_logic_vector(3 downto 0));
end component;
component comparator is
port(point:in std_logic_vector(3 downto 0);
sum:in std_logic_vector(3 downto 0);
eq:out bit);
end component;
component test_logic is
port(sum:in std_logic_vector(3 downto 0);
d7,d711,d2312:out bit);
end component;
component control is
port(reset,rb,eq,d7,d711,d2312:in bit;
roll,win,lose,sp:out bit);
end component;
signal roll,eq,d7,d711,d2312,sp:bit;
signal count1,count2,sum,point:std_logic_vector(3 downto 0);
begin
decoder1:decoder_1_6 port map(m=>count1,led_vector=>led1);
decoder2:decoder_1_6 port map(m=>count2,led_vector=>led2);
counter1:counter_1_6 port map(clk_50m=>clk_50m,roll=>roll,out_count=>count1);
counter2:counter_1_6 port map(clk_50m=>clk_28m,roll=>roll,out_count=>count2);
add:adder port map(addend1=>count1,addend2=>count2,sum=>sum);
pr:point_register port map(sp=>sp,point=>point,sum=>sum);
compare:comparator port map(point=>point,sum=>sum,eq=>eq);
test:test_logic port map(sum=>sum,d7=>d7,d711=>d711,d2312=>d2312);
con:control port map(reset=>reset,rb=>rb,
eq=>eq,d7=>d7,d711=>d711,d2312=>d2312,
roll=>roll,win=>win,lose=>lose,sp=>sp);
end allmap;
--------------------------------------------------------------
------------------------------------------------------------
-- point_register.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity point_register is
--latch the last value--
port(sp:in bit;
point:out std_logic_vector(3 downto 0):="0000";
sum:in std_logic_vector(3 downto 0));
end point_register;
architecture point of point_register is
--signal count:bit;
begin
process(sp,sum)
begin
if sp='0' then
--count<='0';
elsif sp='1' then
--count<='1';
point<=sum;
end if;
end process;
end point;
--------------------------------------------------------------
------------------------------------------------------------
-- test_logic.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity test_logic is
port(sum:in std_logic_vector(3 downto 0);
d7,d711,d2312:out bit);
end test_logic;
architecture test of test_logic is
begin
process(sum)
begin
if sum="0111" then
d7<='1';
else d7<='0';
end if;
if sum="0111" or sum="1011" then
d711<='1';
else d711<='0';
end if;
if sum="0010" or sum="0011" or sum="1100" then
d2312<='1';
else d2312<='0';
end if;
end process;
end test;
|
entity test is
end test;
architecture only of test is
signal s : bit := '0';
begin
p : process
begin
s <= '1';
wait for 0 fs;
assert s'last_value = '0' report "TEST FAILED" severity failure;
report "TEST PASSED";
wait;
end process;
end only;
|
entity test is
end test;
architecture only of test is
signal s : bit := '0';
begin
p : process
begin
s <= '1';
wait for 0 fs;
assert s'last_value = '0' report "TEST FAILED" severity failure;
report "TEST PASSED";
wait;
end process;
end only;
|
entity test is
end test;
architecture only of test is
signal s : bit := '0';
begin
p : process
begin
s <= '1';
wait for 0 fs;
assert s'last_value = '0' report "TEST FAILED" severity failure;
report "TEST PASSED";
wait;
end process;
end only;
|
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: RX channel
-- # FE-I4 Style Rx Channel; Sync, Align & Decode
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library decode_8b10b;
entity fei4_rx_channel is
port (
-- Sys connect
rst_n_i : in std_logic;
clk_160_i : in std_logic;
clk_640_i : in std_logic;
enable_i : in std_logic;
-- Input
rx_data_i : in std_logic;
trig_tag_i : in std_logic_vector(31 downto 0);
-- Output
rx_data_o : out std_logic_vector(25 downto 0);
rx_valid_o : out std_logic;
rx_stat_o : out std_logic_vector(7 downto 0);
rx_data_raw_o : out std_logic_vector(7 downto 0)
);
end fei4_rx_channel;
architecture behavioral of fei4_rx_channel is
component cdr_serdes
port (
-- clocks
clk160 : in std_logic;
clk640 : in std_logic;
-- reset
reset : in std_logic;
-- data input
din : in std_logic;
slip : in std_logic;
-- data output
data_value : out std_logic_vector(1 downto 0);
data_valid : out std_logic_vector(1 downto 0);
data_lock : out std_logic
);
end component;
component data_alignment
port
(
clk : in std_logic;
reset : in std_logic;
din : in std_logic_vector(1 downto 0);
din_valid : in std_logic_vector(1 downto 0);
dout : out std_logic_vector(9 downto 0);
dout_valid : out std_logic;
dout_sync : out std_logic
);
end component;
component decode_8b10b_wrapper
port(
CLK : IN std_logic;
DIN : IN std_logic_vector(9 downto 0);
CE : IN std_logic;
SINIT : IN std_logic;
DOUT : OUT std_logic_vector(7 downto 0);
KOUT : OUT std_logic;
CODE_ERR : OUT std_logic;
DISP_ERR : OUT std_logic;
ND : OUT std_logic
);
end component;
constant c_SOF : std_logic_vector(7 downto 0) := x"fc";
constant c_EOF : std_logic_vector(7 downto 0) := x"bc";
constant c_IDLE : std_logic_vector(7 downto 0) := x"3c";
signal data_raw_value : std_logic_vector(1 downto 0);
signal data_raw_valid : std_logic_vector(1 downto 0);
signal data_raw_lock : std_logic;
signal data_enc_value : std_logic_vector(9 downto 0);
signal data_enc_valid : std_logic;
signal data_enc_sync : std_logic;
signal data_enc_value_rev : std_logic_vector(9 downto 0);
signal data_enc_valid_rev : std_logic;
signal data_enc_valid_rev_d : std_logic;
signal data_dec_value : std_logic_vector(7 downto 0);
signal data_dec_valid : std_logic;
signal data_dec_kchar : std_logic;
signal data_dec_decerr : std_logic;
signal data_dec_disperr : std_logic;
signal data_fram_cnt : unsigned(1 downto 0);
signal data_frame_flag : std_logic;
signal data_frame_value : std_logic_vector(25 downto 0);
signal data_frame_valid : std_logic;
signal status : std_logic_vector(7 downto 0);
begin
-- Status Output
rx_stat_o <= status;
status(0) <= data_raw_lock;
status(1) <= data_enc_sync;
status(2) <= data_dec_decerr;
status(3) <= data_dec_disperr;
status(5 downto 4) <= data_raw_value;
status(7 downto 6) <= data_raw_valid;
rx_data_raw_o <= data_dec_value;
-- Frame collector
rx_data_o <= data_frame_value;
rx_valid_o <= data_frame_valid and data_raw_lock and data_enc_sync and enable_i;
framing_proc : process(clk_160_i, rst_n_i)
begin
if (rst_n_i = '0') then
data_fram_cnt <= (others => '0');
data_frame_flag <= '0';
data_frame_value <= (others => '0');
data_frame_valid <= '0';
elsif rising_edge(clk_160_i) then
-- Count bytes
if (data_frame_flag = '1' and data_dec_valid = '1' and data_fram_cnt = 2) then
data_fram_cnt <= (others => '0');
data_frame_valid <= '1';
elsif (data_frame_flag = '1' and data_dec_valid = '1' and data_fram_cnt < 2) then
data_fram_cnt <= data_fram_cnt + 1;
data_frame_valid <= '0';
elsif (data_frame_flag = '0') then
data_fram_cnt <= (others => '0');
data_frame_valid <= '0';
else
data_frame_valid <= '0';
end if;
-- Mark Start and End of Frame
if (data_dec_valid = '1' and data_dec_kchar = '1' and data_dec_value = c_SOF and data_enc_sync = '1') then
data_frame_flag <= '1';
data_frame_value(25 downto 24) <= "01"; -- tag code
data_frame_value(23 downto 0) <= trig_tag_i(23 downto 0);
data_frame_valid <= '1';
elsif (data_dec_valid = '1' and data_dec_kchar = '1' and (data_dec_value = c_EOF or data_dec_value = c_IDLE)) then
data_frame_flag <= '0';
end if;
-- Build Frame
if (data_frame_flag = '1' and data_dec_valid = '1' and data_dec_kchar = '0' ) then
data_frame_value(25 downto 24) <= "00"; -- no special code
data_frame_value(23 downto 16) <= data_frame_value(15 downto 8);
data_frame_value(15 downto 8) <= data_frame_value(7 downto 0);
data_frame_value(7 downto 0) <= data_dec_value;
end if;
end if;
end process framing_proc;
-- Reverse bit order to make it standard
reverse_proc : process (clk_160_i, rst_n_i)
begin
if (rst_n_i = '0') then
data_enc_value_rev <= (others => '0');
data_enc_valid_rev <= '0';
data_enc_valid_rev_d <= '0';
data_dec_valid <= '0';
elsif rising_edge(clk_160_i) then
for I in 0 to 9 loop
data_enc_value_rev(I) <= data_enc_value(9-I);
end loop;
data_enc_valid_rev <= data_enc_valid;
data_enc_valid_rev_d <= data_enc_valid_rev;
data_dec_valid <= data_enc_valid_rev_d;
end if;
end process reverse_proc;
cmp_cdr_serdes : cdr_serdes port map (
clk160 => clk_160_i,
clk640 => clk_640_i,
reset => not rst_n_i,
din => rx_data_i,
slip => '0',
data_value => data_raw_value,
data_valid => data_raw_valid,
data_lock => data_raw_lock
);
cmp_data_align : data_alignment port map (
clk => clk_160_i,
reset => not rst_n_i,
din => data_raw_value,
din_valid => data_raw_valid,
dout => data_enc_value,
dout_valid => data_enc_valid,
dout_sync => data_enc_sync
);
cmp_decoder: decode_8b10b_wrapper PORT MAP(
CLK => clk_160_i,
DIN => data_enc_value_rev,
CE => data_enc_valid_rev,
SINIT => '0',
DOUT => data_dec_value,
KOUT => data_dec_kchar,
CODE_ERR => data_dec_decErr,
DISP_ERR => data_dec_dispErr,
ND => open
);
end behavioral;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.10:15:30)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesahb_alap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 30);
output1, output2: OUT unsigned(0 TO 31));
END mesahb_alap_entity;
ARCHITECTURE mesahb_alap_description OF mesahb_alap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "0000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
WHEN "00000010" =>
register1 := register1 + 3;
register2 := input2 * 4;
WHEN "00000011" =>
register1 := register1 * 6;
register3 := input3 * 7;
register2 := register2 + 9;
WHEN "00000100" =>
register1 := register1 + 11;
register3 := register3 + 13;
register2 := ((NOT register2) + 1) XOR register2;
register4 := input4 * 16;
WHEN "00000101" =>
register1 := ((NOT register1) + 1) XOR register1;
register3 := register3 * 20;
register2 := register4 * register2;
WHEN "00000110" =>
register1 := register1 * 22;
register3 := register3 + 24;
WHEN "00000111" =>
register1 := register1 + register2;
output1 <= input5 + 25;
WHEN "00001000" =>
output2 <= register1(0 TO 14) & register3(0 TO 15);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesahb_alap_description; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2655.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02655ent IS
END c13s03b01x00p02n01i02655ent;
ARCHITECTURE c13s03b01x00p02n01i02655arch OF c13s03b01x00p02n01i02655ent IS
BEGIN
TESTING: PROCESS
variable :k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02655d - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02655arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2655.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02655ent IS
END c13s03b01x00p02n01i02655ent;
ARCHITECTURE c13s03b01x00p02n01i02655arch OF c13s03b01x00p02n01i02655ent IS
BEGIN
TESTING: PROCESS
variable :k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02655d - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02655arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2655.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02655ent IS
END c13s03b01x00p02n01i02655ent;
ARCHITECTURE c13s03b01x00p02n01i02655arch OF c13s03b01x00p02n01i02655ent IS
BEGIN
TESTING: PROCESS
variable :k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02655d - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02655arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2082.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02082ent IS
END c07s02b04x00p20n01i02082ent;
ARCHITECTURE c07s02b04x00p20n01i02082arch OF c07s02b04x00p20n01i02082ent IS
TYPE real_vector is array (INTEGER range <>) of REAL;
BEGIN
TESTING: PROCESS
VARIABLE target : real_vector (1 to 7) ;
VARIABLE slice_1 : real_vector (1 to 4) := (1.0,2.0,3.0,4.0);
VARIABLE slice_2 : real_vector (-2 to 4) :=
(5.0,6.0,7.0,8.0,9.0,10.0,11.0);
BEGIN
target := slice_1 ( 1 to 3 ) & slice_2 ( -1 to 2 );
assert NOT(target=(1.0,2.0,3.0,6.0,7.0,8.0,9.0))
report "***PASSED TEST: c07s02b04x00p20n01i02082"
severity NOTE;
assert (target=(1.0,2.0,3.0,6.0,7.0,8.0,9.0))
report "***FAILED TEST: c07s02b04x00p20n01i02082 - One dimensional array of REAL type concatenation into a larger ARRAY failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02082arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2082.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02082ent IS
END c07s02b04x00p20n01i02082ent;
ARCHITECTURE c07s02b04x00p20n01i02082arch OF c07s02b04x00p20n01i02082ent IS
TYPE real_vector is array (INTEGER range <>) of REAL;
BEGIN
TESTING: PROCESS
VARIABLE target : real_vector (1 to 7) ;
VARIABLE slice_1 : real_vector (1 to 4) := (1.0,2.0,3.0,4.0);
VARIABLE slice_2 : real_vector (-2 to 4) :=
(5.0,6.0,7.0,8.0,9.0,10.0,11.0);
BEGIN
target := slice_1 ( 1 to 3 ) & slice_2 ( -1 to 2 );
assert NOT(target=(1.0,2.0,3.0,6.0,7.0,8.0,9.0))
report "***PASSED TEST: c07s02b04x00p20n01i02082"
severity NOTE;
assert (target=(1.0,2.0,3.0,6.0,7.0,8.0,9.0))
report "***FAILED TEST: c07s02b04x00p20n01i02082 - One dimensional array of REAL type concatenation into a larger ARRAY failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02082arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2082.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02082ent IS
END c07s02b04x00p20n01i02082ent;
ARCHITECTURE c07s02b04x00p20n01i02082arch OF c07s02b04x00p20n01i02082ent IS
TYPE real_vector is array (INTEGER range <>) of REAL;
BEGIN
TESTING: PROCESS
VARIABLE target : real_vector (1 to 7) ;
VARIABLE slice_1 : real_vector (1 to 4) := (1.0,2.0,3.0,4.0);
VARIABLE slice_2 : real_vector (-2 to 4) :=
(5.0,6.0,7.0,8.0,9.0,10.0,11.0);
BEGIN
target := slice_1 ( 1 to 3 ) & slice_2 ( -1 to 2 );
assert NOT(target=(1.0,2.0,3.0,6.0,7.0,8.0,9.0))
report "***PASSED TEST: c07s02b04x00p20n01i02082"
severity NOTE;
assert (target=(1.0,2.0,3.0,6.0,7.0,8.0,9.0))
report "***FAILED TEST: c07s02b04x00p20n01i02082 - One dimensional array of REAL type concatenation into a larger ARRAY failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02082arch;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal clkout, pllref : std_ulogic;
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(23 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_ulogic;
signal ramoen : std_ulogic;
signal rwen : std_ulogic;
signal mben : std_logic_vector(3 downto 0);
--signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
--signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_ulogic; -- clk en
signal sdcsn : std_ulogic; -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector (3 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal sdba : std_logic_vector(1 downto 0);
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
--signal txd2, rxd2 : std_ulogic;
-- for smc lan chip
signal eth_aen : std_ulogic; -- for smsc eth
signal eth_readn : std_ulogic; -- for smsc eth
signal eth_writen : std_ulogic; -- for smsc eth
signal eth_nbe : std_logic_vector(3 downto 0); -- for smsc eth
signal eth_datacsn : std_ulogic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(31 downto 0);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
d3 : entity work.leon3mp generic map (fabtech, memtech, padtech, clktech,
ncpu, disas, dbguart, pclow )
port map (rst, clk, error, address, data, ramsn, ramoen, rwen, mben, iosn,
romsn, oen, writen, open, open, sa(11 downto 0), sd, sdclk, sdcke,
sdcsn, sdwen, sdrasn, sdcasn, sddqm, sdba, dsutx, dsurx, dsubren,
dsuact, rxd1, txd1, eth_aen, eth_readn,
eth_writen, eth_nbe);
sd1 : if (CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 1) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sdba, Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sdba, Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
-- 8 bit prom
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24),
romsn, rwen, oen);
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn,
rwen, ramoen);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
--------------------------------------------------------------------------------
-- Company: KTH
--
-- File: WOLF_CONTROLLER.vhd
-- File history:
-- v0.1: 2017-04-15: Initial verision for drop test only
--
-- Description:
-- Controller for the REXUS - WOLF exeriment. Handles the statemachine and status communication.
--
-- Backup version:
-- 2017-05-28: D.R: Initial version, light led at 5 sec, turn off led at 10 sec.
-- 2017-06-14: D.R: Droptest version
--
-- Targeted device: <Family::ProASIC3> <Die::A3P250> <Package::100 VQFP>
-- Author: David Rozenbeek
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity WOLF_CONTROLLER is
port (
---------------------------------------------------
-- Inputs --
---------------------------------------------------
mclk : IN std_logic; -- Main clock
clk_1hz : IN std_logic; -- 1 Hz clock
reset : IN std_logic; -- Reset (when 1)
--UART
uart_data_in : IN std_logic_vector(7 downto 0);
uart_txrdy : IN std_logic;
uart_rxrdy : IN std_logic;
---------------------------------------------------
-- Outputs --
---------------------------------------------------
--Cutter
cutter_en : OUT std_logic; -- Cutter Enable (0=Off, 1=On)
cutter_pwm_duty : OUT std_logic_vector(7 downto 0); -- Cutter PWM duty cycle (100% = 255, 0% = 0)
--UART
uart_data_out : OUT std_logic_vector(7 downto 0);
uart_wen : OUT std_logic;
uart_oen : OUT std_logic;
uart_baud_val : OUT std_logic_vector(12 downto 0);
uart_baud_val_frac: OUT std_logic_vector(2 downto 0) := "000";
--LED
led1 : OUT std_logic;
led2 : OUT std_logic
);
end WOLF_CONTROLLER;
architecture architecture_WOLF_CONTROLLER of WOLF_CONTROLLER is
--####################### Constants #####################################
--Cutter
constant sec_cutter_enable : integer := 2; -- Seconds cutter should be enabled
constant sec_to_cutter_enable : integer := 2; -- Seconds from ejection to enable cutter.
constant cutter_duty : integer := 50; -- Cutter PWM duty cycle, controls current through heating filament(255 => More current, 0 => Less current)
--Uart
constant uart_baud_val_int : integer := 212; -- baudval = (mclk / (16 * baudrate)) - 1; set for 9600 baud
--####################### Signals #####################################
----------------------------------------------------------------------------------------------------------------------
-- Control signals |Comments --
----------------------------------------------------------------------------------------------------------------------
--uart
signal uart_data_buffer_in : std_logic_vector(7 downto 0) :=(others => '0');
signal uart_ready : std_logic := '0';
signal main_uart_transmit_flag : std_logic := '0';
signal main_uart_data_out : std_logic_vector(7 downto 0) :=(others => '0');
--Misson counter
signal sec_since_res : unsigned(12 downto 0) := (others => '0'); -- Variable to keep track of seconds since reset
-----------------------------------------------------------------------------------------------------------------------
-- State Machine Signals |Comments --
-----------------------------------------------------------------------------------------------------------------------
type main_state is (START, IDLE, CUTTER_ENABLE, CUTTER_DISABLE, SLEEP);
signal main_current_state : main_state;
signal main_next_state : main_state := START;
type uart_state is (START, IDLE, RECEIVE, RESPONSE, TRANSMIT);
signal uart_current_state : uart_state;
signal uart_next_state : uart_state := START;
--################# Architecture Body ###########################
begin
-----------------------------------------------------------------
-- Signal/Port mapping --
-----------------------------------------------------------------
cutter_pwm_duty <= std_logic_vector(to_unsigned(cutter_duty, cutter_pwm_duty'length));
uart_baud_val <= std_logic_vector(to_unsigned(uart_baud_val_int, uart_baud_val'length));
-----------------------------------------------------------------
-- Mission counter --
-- Description: --
-- Keeps track of seconds since reset, counts up to --
-- 2^12 = 4096 seconds (68,3 min) and then overflows back to 0.--
-----------------------------------------------------------------
mission_counter: process(clk_1hz, reset)
begin
if ( reset = '1' ) then
sec_since_res <= (others => '0');
else
if ( rising_edge(clk_1hz) ) then
sec_since_res <= sec_since_res + 1;
end if;
end if;
end process;
-----------------------------------------------------------------
-- Uart State Machine --
-- Description: --
-- Uart state machine --
-----------------------------------------------------------------
uart_state_machine : process(mclk, reset)
begin
if(reset = '1') then
uart_next_state <= START;
uart_data_out <= (others => '0');
uart_wen <= '1';
uart_oen <= '1';
uart_ready <= '0';
else
if(rising_edge(mclk)) then
uart_current_state <= uart_next_state;
case uart_current_state is
when START =>
uart_data_out <= (others => '0');
uart_wen <= '1';
uart_oen <= '1';
uart_ready <= '0';
uart_next_state <= IDLE;
when IDLE => -- Wait for receving command
uart_ready <= '1';
if(uart_rxrdy = '1') then
uart_ready <= '0';
uart_next_state <= RECEIVE;
elsif(main_uart_transmit_flag='1') then
uart_ready <= '0';
uart_data_out <= main_uart_data_out;
uart_next_state <= TRANSMIT;
else
uart_next_state <= uart_current_state;
end if;
when RECEIVE => -- Recevie the byte
uart_data_buffer_in <= uart_data_in;
uart_oen <= '0';
uart_next_state <= RESPONSE;
when RESPONSE =>
uart_data_out <= uart_data_buffer_in;
uart_next_state <= TRANSMIT;
when TRANSMIT =>
if(uart_txrdy = '1') then
uart_wen <= '0';
uart_next_state <= START;
else
uart_next_state <= uart_current_state;
end if;
end case;
end if;
end if;
end process uart_state_machine;
-----------------------------------------------------------------
-- Main State Machine --
-- Description: --
-- Main state machine of the WOLF mission controller --
-----------------------------------------------------------------
main_state_machine : process(mclk, reset)
begin
if(reset = '1') then
cutter_en <= '0';
main_uart_transmit_flag <= '0';
main_uart_data_out <= x"00";
main_next_state <= START;
elsif(rising_edge(mclk)) then
main_current_state <= main_next_state;
case main_current_state is
-- Starting state
when START =>
cutter_en <= '0';
main_uart_transmit_flag <= '0';
if(uart_ready = '1') then
main_next_state <= IDLE;
main_uart_data_out <= x"01";
main_uart_transmit_flag <= '1';
end if;
-- IDLE state
when IDLE =>
main_uart_transmit_flag <= '0';
-- Enable cutter after "sec_to_cutter_enable" from reset
if (sec_since_res >= To_unsigned(sec_to_cutter_enable, sec_since_res'length)) then
if(uart_ready = '1') then
main_next_state <= CUTTER_ENABLE;
main_uart_data_out <= x"02";
main_uart_transmit_flag <= '1';
end if;
else
main_next_state <= main_current_state;
end if;
-- Enable cutter
when CUTTER_ENABLE =>
main_uart_transmit_flag <= '0';
if(uart_ready = '1') then
cutter_en <= '1';
main_uart_data_out <= x"03";
main_uart_transmit_flag <= '1';
main_next_state <= CUTTER_DISABLE;
end if;
--Disable cutter
when CUTTER_DISABLE =>
-- Disable cutter after "sec_cutter_enable"
main_uart_transmit_flag <= '0';
if (sec_since_res >= To_unsigned((sec_to_cutter_enable + sec_cutter_enable), sec_since_res'length)) then
if(uart_ready = '1') then
cutter_en <= '0';
main_uart_data_out <= x"04";
main_uart_transmit_flag <= '1';
main_next_state <= SLEEP;
end if;
else
main_next_state <= main_current_state;
end if;
-- SLEEP state, do nothing
when SLEEP =>
main_uart_transmit_flag <= '0';
end case;
end if;
end process main_state_machine;
end architecture_WOLF_CONTROLLER;
|
-------------------------------------------------------------------------------
--
-- T420/421 controller toplevel without tri-states.
--
-- $Id: t420_notri-c.vhd,v 1.2 2006-06-05 20:03:11 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t420_notri_struct_c0 of t420_notri is
for struct
for core_b: t400_core
use configuration work.t400_core_struct_c0;
end for;
for pmem_b: t420_rom
use configuration work.t420_rom_struct_c0;
end for;
for dmem_b: generic_ram_ena
use configuration work.generic_ram_ena_rtl_c0;
end for;
for por_b: t400_por
use configuration work.t400_por_rtl_c0;
end for;
end for;
end t420_notri_struct_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.1 2006/05/14 22:29:01 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
entity test is
end entity test;
architecture atest of test is
-- signal s : bit;
signal t : bit;
begin
main1: process
begin
t <= '1';
t <= '0';
end process;
-- main2: process(s)
-- begin
-- t <= '0';
-- end process;
-- main2: process(s)
-- begin
-- end process;
-- s <= '1';
end;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY DataMemory_tb IS
END DataMemory_tb;
ARCHITECTURE behavior OF DataMemory_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT DataMemory
PORT(
Crd : IN std_logic_vector(31 downto 0);
Address : IN std_logic_vector(31 downto 0);
WRENMEM : IN std_logic;
DATATOMEM : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Crd : std_logic_vector(31 downto 0) := (others => '0');
signal Address : std_logic_vector(31 downto 0) := (others => '0');
signal WRENMEM : std_logic := '0';
--Outputs
signal DATATOMEM : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: DataMemory PORT MAP (
Crd => Crd,
Address => Address,
WRENMEM => WRENMEM,
DATATOMEM => DATATOMEM
);
-- Stimulus process
stim_proc: process
begin
Crd<="00000000000000000000001000001011";
Address<="00000000000000000000000000001110";
wait for 20 ns;
Crd<="00000000000000000000001000101011";
Address<="00000000000000000000000000001111";
WRENMEM<='1';
wait for 20 ns;
Crd<="00000000000000000000000000001011";
Address<="00000000000000000000000000001111";
WRENMEM<='0';
wait for 20 ns;
Crd<="00000000000000000001001000001011";
Address<="00000000000000000000000000001111";
WRENMEM<='1';
wait for 20 ns;
Crd<="00000000000000000000000000001011";
Address<="00000000000000000000000000010000";
wait for 20 ns;
Crd<="00000000000000000000000000000011";
Address<="00000000000000000000000000010000";
WRENMEM<='0';
wait;
end process;
END;
|
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
COMPONENT <component name>
PORT(
<port1> : IN std_logic;
<port2> : IN std_logic_vector(3 downto 0);
<port3> : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
SIGNAL <signal1> : std_logic;
SIGNAL <signal2> : std_logic_vector(3 downto 0);
BEGIN
-- Component Instantiation
uut: <component name> PORT MAP(
<port1> => <signal1>,
<port3> => <signal2>
);
-- Test Bench Statements
tb : PROCESS
BEGIN
wait; -- will wait forever
END PROCESS tb;
-- End Test Bench
END;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: proc3
-- File: proc3.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: LEON3 processor core with pipeline, mul/div & cache control
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.arith.all;
use gaisler.libleon3.all;
use gaisler.libfpu.all;
entity proc3 is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := 0;
memtech : integer range 0 to NTECH := 0;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 0;
svt : integer range 0 to 1 := 0;
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : out std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
crami : out cram_in_type;
cramo : in cram_out_type;
tbi : out tracebuf_in_type;
tbo : in tracebuf_out_type;
fpi : out fpc_in_type;
fpo : in fpc_out_type;
cpi : out fpc_in_type;
cpo : in fpc_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic
);
end;
architecture rtl of proc3 is
constant IRFWT : integer := 1; --regfile_3p_write_through(memtech);
signal ici : icache_in_type;
signal ico : icache_out_type;
signal dci : dcache_in_type;
signal dco : dcache_out_type;
signal holdnx, pholdn : std_logic;
signal muli : mul32_in_type;
signal mulo : mul32_out_type;
signal divi : div32_in_type;
signal divo : div32_out_type;
begin
holdnx <= ico.hold and dco.hold and fpo.holdn; holdn <= holdnx;
pholdn <= fpo.holdn;
-- integer unit
iu : iu3
generic map (nwindows, isets, dsets, fpu, v8, cp, mac, dsu, nwp, pclow,
notag, hindex, lddel, IRFWT, disas, tbuf, pwd, svt, rstaddr, smp, fabtech,
clk2x, bp)
port map (clk, rstn, holdnx, ici, ico, dci, dco, rfi, rfo, irqi, irqo,
dbgi, dbgo, muli, mulo, divi, divo, fpo, fpi, cpo, cpi, tbo, tbi, sclk);
-- multiply and divide units
mgen : if v8 /= 0 generate
mul0 : mul32 generic map (fabtech, v8/16, (v8 mod 4)/2, mac, (v8 mod 16)/4)
port map (rstn, clk, holdnx, muli, mulo);
div0 : div32 port map (rstn, clk, holdnx, divi, divo);
end generate;
nomgen : if v8 = 0 generate
divo <= ('0', '0', "0000", zero32);
mulo <= ('0', '0', "0000", zero32&zero32);
end generate;
-- cache controller
c0mmu : mmu_cache
generic map (
hindex, memtech, dsu, icen, irepl, isets, ilinesize, isetsize,
isetlock, dcen, drepl, dsets, dlinesize, dsetsize, dsetlock,
dsnoop, ilram, ilramsize, ilramstart, dlram, dlramsize, dlramstart,
itlbnum, dtlbnum, tlb_type, tlb_rep, cached,
clk2x, scantest, mmupgsz, smp, mmuen)
port map (rstn, clk, ici, ico, dci, dco, ahbi, ahbo, ahbsi, ahbso,
crami, cramo, pholdn, hclk, sclk, hclken);
end;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:alu:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_alu_0_0 IS
PORT (
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
C_IN : IN STD_LOGIC;
Sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SUM : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
C_FLAG : OUT STD_LOGIC;
Z_FLAG : OUT STD_LOGIC
);
END RAT_alu_0_0;
ARCHITECTURE RAT_alu_0_0_arch OF RAT_alu_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_alu_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT alu IS
GENERIC (
data_width : INTEGER;
sel_width : INTEGER
);
PORT (
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
C_IN : IN STD_LOGIC;
Sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SUM : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
C_FLAG : OUT STD_LOGIC;
Z_FLAG : OUT STD_LOGIC
);
END COMPONENT alu;
BEGIN
U0 : alu
GENERIC MAP (
data_width => 8,
sel_width => 4
)
PORT MAP (
A => A,
B => B,
C_IN => C_IN,
Sel => Sel,
SUM => SUM,
C_FLAG => C_FLAG,
Z_FLAG => Z_FLAG
);
END RAT_alu_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:alu:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_alu_0_0 IS
PORT (
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
C_IN : IN STD_LOGIC;
Sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SUM : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
C_FLAG : OUT STD_LOGIC;
Z_FLAG : OUT STD_LOGIC
);
END RAT_alu_0_0;
ARCHITECTURE RAT_alu_0_0_arch OF RAT_alu_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_alu_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT alu IS
GENERIC (
data_width : INTEGER;
sel_width : INTEGER
);
PORT (
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
C_IN : IN STD_LOGIC;
Sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SUM : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
C_FLAG : OUT STD_LOGIC;
Z_FLAG : OUT STD_LOGIC
);
END COMPONENT alu;
BEGIN
U0 : alu
GENERIC MAP (
data_width => 8,
sel_width => 4
)
PORT MAP (
A => A,
B => B,
C_IN => C_IN,
Sel => Sel,
SUM => SUM,
C_FLAG => C_FLAG,
Z_FLAG => Z_FLAG
);
END RAT_alu_0_0_arch;
|
-- Gaisler Ethernet core
constant CFG_GRETH2 : integer := CONFIG_GRETH2_ENABLE;
constant CFG_GRETH21G : integer := CONFIG_GRETH2_GIGA;
constant CFG_ETH2_FIFO : integer := CFG_GRETH2_FIFO;
|
-- Gaisler Ethernet core
constant CFG_GRETH2 : integer := CONFIG_GRETH2_ENABLE;
constant CFG_GRETH21G : integer := CONFIG_GRETH2_GIGA;
constant CFG_ETH2_FIFO : integer := CFG_GRETH2_FIFO;
|
-- Gaisler Ethernet core
constant CFG_GRETH2 : integer := CONFIG_GRETH2_ENABLE;
constant CFG_GRETH21G : integer := CONFIG_GRETH2_GIGA;
constant CFG_ETH2_FIFO : integer := CFG_GRETH2_FIFO;
|
-- Gaisler Ethernet core
constant CFG_GRETH2 : integer := CONFIG_GRETH2_ENABLE;
constant CFG_GRETH21G : integer := CONFIG_GRETH2_GIGA;
constant CFG_ETH2_FIFO : integer := CFG_GRETH2_FIFO;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY MUX_RFSOURCE_tb IS
END MUX_RFSOURCE_tb;
ARCHITECTURE behavior OF MUX_RFSOURCE_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MUX_RFSOURCE
PORT(
RFSOURCE : IN std_logic_vector(1 downto 0);
DATATOMEM : IN std_logic_vector(31 downto 0);
ALURESULT : IN std_logic_vector(31 downto 0);
PC : IN std_logic_vector(31 downto 0);
DATATOREG : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal RFSOURCE : std_logic_vector(1 downto 0) := (others => '0');
signal DATATOMEM : std_logic_vector(31 downto 0) := (others => '0');
signal ALURESULT : std_logic_vector(31 downto 0) := (others => '0');
signal PC : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal DATATOREG : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MUX_RFSOURCE PORT MAP (
RFSOURCE => RFSOURCE,
DATATOMEM => DATATOMEM,
ALURESULT => ALURESULT,
PC => PC,
DATATOREG => DATATOREG
);
-- Stimulus process
stim_proc: process
begin
RFSOURCE<="00";
DATATOMEM<="00000000000000000011010000111111";
ALURESULT<="00000000000000000000000000010111";
PC<="00000000000000000000000000000011";
wait for 20 ns;
RFSOURCE<="01";
DATATOMEM<="00000000000000000010000000100001";
ALURESULT<="00000000000000000000000100010000";
PC<="00000000000000000000000000000111";
wait for 20 ns;
RFSOURCE<="10";
DATATOMEM<="00000000000000000000001100000000";
ALURESULT<="00000000000000000000000111110000";
PC<="00000000000000000000000000001011";
wait for 20 ns;
RFSOURCE<="11";
DATATOMEM<="00000000000000000000000000101000";
ALURESULT<="00000000000000000000000000000101";
PC<="00000000000000000000000000001111";
wait;
end process;
END;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
-- pragma translate_off
use altera_mf.altpll;
-- pragma translate_on
entity clkgen_de2 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of clkgen_de2 is
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "CLK0" ;
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkout : std_logic_vector (5 downto 0);
signal inclk : std_logic_vector (1 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(1);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone II",
operation_mode => "ZERO_DELAY_BUFFER",
compensate_clock => "CLK2",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => 5, clk1_divide_by => 10,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= clkout(2);
end generate;
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone II",
operation_mode => "NORMAL",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => 5, clk1_divide_by => 10)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= '0';
end generate;
end;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_k1_k2_e
--
-- Generated
-- by: wig
-- on: Wed Nov 30 09:22:45 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_k1_k2_e-e.vhd,v 1.3 2005/11/30 14:04:02 wig Exp $
-- $Date: 2005/11/30 14:04:02 $
-- $Log: inst_k1_k2_e-e.vhd,v $
-- Revision 1.3 2005/11/30 14:04:02 wig
-- Updated testcase references
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.42 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_k1_k2_e
--
entity inst_k1_k2_e is
-- Generics:
-- No Generated Generics for Entity inst_k1_k2_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_k1_k2_e
port1 : in std_ulogic_vector(3 downto 0); -- Macro test 0 k1_k2
port2 : in std_ulogic_vector(3 downto 0); -- Macro test 0 k1_k2
port3 : in std_ulogic_vector(3 downto 0); -- Macro test 0 k1_k2
port_mac : out std_ulogic; -- Macro test 0 k1_k2 __I_AUTO_REDUCED_BUS2SIGNAL
port_mac_c : out std_ulogic_vector(6 downto 0) -- Macro test 0 k1_k2
-- End of Generated Port for Entity inst_k1_k2_e
);
end inst_k1_k2_e;
--
-- End of Generated Entity inst_k1_k2_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- Title : Hall Sensor Encoder Module
-- Project : Loa
-------------------------------------------------------------------------------
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- Description: Connectes a hall sensor encoder with a 16-bit counter to
-- the internal bus system.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.encoder_module_pkg.all;
use work.motor_control_pkg.all;
use work.hall_sensor_decoder_pkg.all;
use work.up_down_counter_pkg.all;
-------------------------------------------------------------------------------
entity encoder_hall_sensor_module is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#
);
port (
hall_sensor_p : in hall_sensor_type;
-- counter, set to '0' if not used
load_p : in std_logic; -- Save the current encoder value in a
-- buffer register
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic
);
end encoder_hall_sensor_module;
-------------------------------------------------------------------------------
architecture behavioral of encoder_hall_sensor_module is
type encoder_hall_sensor_module_type is record
counter : std_logic_vector(15 downto 0);
data_out : std_logic_vector(15 downto 0);
end record;
signal r, rin : encoder_hall_sensor_module_type :=
(data_out => (others => '0'),
counter => (others => '0'));
signal step : std_logic := '0';
signal up_down : std_logic := '0'; -- Direction for the counter ('1' = up, '0' = down)
signal decode_error : std_logic; -- Decoding Error, currently not used
signal counter : std_logic_vector(15 downto 0);
begin
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process(bus_i, counter, load_p, r)
variable v : encoder_hall_sensor_module_type;
begin
v := r;
v.data_out := (others => '0');
-- Load counter into own buffer
if load_p = '1' then
v.counter := counter;
end if;
-- Check Bus Address
if bus_i.addr = std_logic_vector(to_unsigned(BASE_ADDRESS, 15)) then
if bus_i.we = '1' then
-- TODO
elsif bus_i.re = '1' then
v.data_out := r.counter;
end if;
end if;
rin <= v;
end process comb_proc;
bus_o.data <= r.data_out;
decoder : hall_sensor_decoder
port map (
hall_sensor_p => hall_sensor_p,
step_p => step,
dir_p => up_down,
error_p => decode_error,
clk => clk);
up_down_counter_1 : up_down_counter
generic map (
WIDTH => 16)
port map (
clk_en_p => step,
up_down_p => up_down,
value_p => counter,
reset => '0',
clk => clk);
end behavioral;
|
-------------------------------------------------------------------------------
-- Title : Hall Sensor Encoder Module
-- Project : Loa
-------------------------------------------------------------------------------
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- Description: Connectes a hall sensor encoder with a 16-bit counter to
-- the internal bus system.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.encoder_module_pkg.all;
use work.motor_control_pkg.all;
use work.hall_sensor_decoder_pkg.all;
use work.up_down_counter_pkg.all;
-------------------------------------------------------------------------------
entity encoder_hall_sensor_module is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#
);
port (
hall_sensor_p : in hall_sensor_type;
-- counter, set to '0' if not used
load_p : in std_logic; -- Save the current encoder value in a
-- buffer register
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic
);
end encoder_hall_sensor_module;
-------------------------------------------------------------------------------
architecture behavioral of encoder_hall_sensor_module is
type encoder_hall_sensor_module_type is record
counter : std_logic_vector(15 downto 0);
data_out : std_logic_vector(15 downto 0);
end record;
signal r, rin : encoder_hall_sensor_module_type :=
(data_out => (others => '0'),
counter => (others => '0'));
signal step : std_logic := '0';
signal up_down : std_logic := '0'; -- Direction for the counter ('1' = up, '0' = down)
signal decode_error : std_logic; -- Decoding Error, currently not used
signal counter : std_logic_vector(15 downto 0);
begin
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process(bus_i, counter, load_p, r)
variable v : encoder_hall_sensor_module_type;
begin
v := r;
v.data_out := (others => '0');
-- Load counter into own buffer
if load_p = '1' then
v.counter := counter;
end if;
-- Check Bus Address
if bus_i.addr = std_logic_vector(to_unsigned(BASE_ADDRESS, 15)) then
if bus_i.we = '1' then
-- TODO
elsif bus_i.re = '1' then
v.data_out := r.counter;
end if;
end if;
rin <= v;
end process comb_proc;
bus_o.data <= r.data_out;
decoder : hall_sensor_decoder
port map (
hall_sensor_p => hall_sensor_p,
step_p => step,
dir_p => up_down,
error_p => decode_error,
clk => clk);
up_down_counter_1 : up_down_counter
generic map (
WIDTH => 16)
port map (
clk_en_p => step,
up_down_p => up_down,
value_p => counter,
reset => '0',
clk => clk);
end behavioral;
|
-- Btrace 448
-- Ray Generator - Test Bench
--
-- Bradley Boccuzzi
-- 2016
-- !Remove from project
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity raygen_TB is
end raygen_TB;
architecture arch of raygen_TB is
constant clkPd: time := 20 ns;
constant int, fraction: integer := 16;
signal clk, rst: std_logic := '0';
signal set_cam: std_logic := '0';
signal inc_x, inc_y: std_logic := '0';
signal clr_x, clr_y: std_logic := '0';
signal mv_x, mv_y, mv_z: std_logic_vector((int+fraction)-1 downto 0);
begin
uut: entity work.raygen generic map(int, fraction) port map(clk, rst, set_cam, inc_x, inc_y, clr_x, clr_y, mv_x, mv_y, mv_z);
clkProc: process
begin
wait for clkPd/2;
clk <= '1';
wait for clkPd/2;
clk <= '0';
end process clkProc;
mainTB: process
begin
wait for clkPd/3;
rst <= '1';
wait for clkPd/2;
rst <= '0';
wait for clkPd/2;
rst <= '0';
set_cam <= '1';
wait for clkPd;
set_cam <= '0';
for i in 0 to 3 loop
inc_x <= '1';
wait for clkPd;
inc_x <= '0';
wait for clkPd;
end loop;
inc_y <= '1';
clr_x <= '1';
wait for clkPd;
inc_y <= '0';
clr_x <= '0';
wait;
end process mainTB;
end arch;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: tcp_engine_tx_fifo - Behavioral
--
-- Description: A FIFO for the packet headers, before they have data added
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <hamster@snap.net.nz>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tcp_engine_tx_fifo is
Port ( clk : in STD_LOGIC;
write_en : in std_logic := '0';
full : out std_logic := '0';
in_src_port : in std_logic_vector(15 downto 0) := (others => '0');
in_dst_ip : in std_logic_vector(31 downto 0) := (others => '0');
in_dst_port : in std_logic_vector(15 downto 0) := (others => '0');
in_seq_num : in std_logic_vector(31 downto 0) := (others => '0');
in_ack_num : in std_logic_vector(31 downto 0) := (others => '0');
in_window : in std_logic_vector(15 downto 0) := (others => '0');
in_flag_urg : in std_logic := '0';
in_flag_ack : in std_logic := '0';
in_flag_psh : in std_logic := '0';
in_flag_rst : in std_logic := '0';
in_flag_syn : in std_logic := '0';
in_flag_fin : in std_logic := '0';
in_urgent_ptr : in std_logic_vector(15 downto 0) := (others => '0');
in_data_addr : in std_logic_vector(15 downto 0) := (others => '0');
in_data_len : in std_logic_vector(10 downto 0) := (others => '0');
read_en : in std_logic := '0';
empty : out std_logic := '0';
out_src_port : out std_logic_vector(15 downto 0) := (others => '0');
out_dst_ip : out std_logic_vector(31 downto 0) := (others => '0');
out_dst_port : out std_logic_vector(15 downto 0) := (others => '0');
out_seq_num : out std_logic_vector(31 downto 0) := (others => '0');
out_ack_num : out std_logic_vector(31 downto 0) := (others => '0');
out_window : out std_logic_vector(15 downto 0) := (others => '0');
out_flag_urg : out std_logic := '0';
out_flag_ack : out std_logic := '0';
out_flag_psh : out std_logic := '0';
out_flag_rst : out std_logic := '0';
out_flag_syn : out std_logic := '0';
out_flag_fin : out std_logic := '0';
out_urgent_ptr : out std_logic_vector(15 downto 0) := (others => '0');
out_data_addr : out std_logic_vector(15 downto 0) := (others => '0');
out_data_len : out std_logic_vector(10 downto 0) := (others => '0'));
end tcp_engine_tx_fifo;
architecture Behavioral of tcp_engine_tx_fifo is
component fifo_32 is
port (
clk : in std_logic;
full : out std_logic := '0';
write_en : in std_logic;
data_in : in std_logic_vector;
empty : out std_logic := '0';
read_en : in std_logic;
data_out : out std_logic_vector := (others => '0'));
end component;
signal data_in : std_logic_vector(192 downto 0) := (others => '0');
signal data_out : std_logic_vector(192 downto 0) := (others => '0');
begin
out_data_addr <= data_out(192 downto 177);
out_data_len <= data_out(176 downto 166);
out_src_port <= data_out(165 downto 150);
out_dst_ip <= data_out(149 downto 118);
out_dst_port <= data_out(117 downto 102);
out_seq_num <= data_out(101 downto 70);
out_ack_num <= data_out(69 downto 38);
out_window <= data_out(37 downto 22);
out_flag_urg <= data_out(21);
out_flag_ack <= data_out(20);
out_flag_psh <= data_out(19);
out_flag_rst <= data_out(18);
out_flag_syn <= data_out(17);
out_flag_fin <= data_out(16);
out_urgent_ptr <= data_out(15 downto 0);
data_in <= in_data_addr
& in_data_len
& in_src_port
& in_dst_ip
& in_dst_port
& in_seq_num
& in_ack_num
& in_window
& in_flag_urg
& in_flag_ack
& in_flag_psh
& in_flag_rst
& in_flag_syn
& in_flag_fin
& in_urgent_ptr;
i_generic_fifo: fifo_32
port map (
clk => clk,
full => full,
write_en => write_en,
data_in => data_in,
empty => empty,
read_en => read_en,
data_out => data_out);
end Behavioral;
|
-------------------------------------------------------------------------------------
-- FILE NAME : fmc176_ctrl.vhd
--
-- AUTHOR : Peter Kortekaas
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - fmc176_ctrl
-- architecture - fmc176_ctrl_syn
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
-- fmc176_ctrl
-- Notes: fmc176_ctrl
-------------------------------------------------------------------------------------
-- Disclaimer: LIMITED WARRANTY AND DISCLAIMER. These designs are
-- provided to you as is. 4DSP specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4DSP does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the Designs
-- will be corrected. Furthermore, 4DSP does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- LIMITATION OF LIABILITY. In no event will 4DSP or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. This limitation will apply even if 4DSP
-- has been advised of the possibility of such damage. This
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
----------------------------------------------
-------------------------------------------------------------------------------------
-- Specified libraries
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------------
-- Entity declaration
-------------------------------------------------------------------------------------
entity stellarip_registers is
generic
(
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port (
rst : in std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
cmd_busy : out std_logic;
reg0 : out std_logic_vector(31 downto 0);
reg1 : out std_logic_vector(31 downto 0);
reg2 : in std_logic_vector(31 downto 0);
reg3 : in std_logic_vector(31 downto 0);
reg4 : in std_logic_vector(31 downto 0);
reg5 : in std_logic_vector(31 downto 0);
reg6 : in std_logic_vector(31 downto 0);
mbx_in_reg : in std_logic_vector(31 downto 0);--value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end stellarip_registers;
-------------------------------------------------------------------------------------
-- Architecture declaration
-------------------------------------------------------------------------------------
architecture fmc_ctrl_syn of stellarip_registers is
----------------------------------------------------------------------------------------------------
-- Constants
----------------------------------------------------------------------------------------------------
constant ADDR_REG0 : std_logic_vector(31 downto 0) := x"00000000";
constant ADDR_REG1 : std_logic_vector(31 downto 0) := x"00000001";
constant ADDR_REG2 : std_logic_vector(31 downto 0) := x"00000002";
constant ADDR_REG3 : std_logic_vector(31 downto 0) := x"00000003";
constant ADDR_REG4 : std_logic_vector(31 downto 0) := x"00000004";
constant ADDR_REG5 : std_logic_vector(31 downto 0) := x"00000005";
constant ADDR_REG6 : std_logic_vector(31 downto 0) := x"00000006";
constant ADDR_REG7 : std_logic_vector(31 downto 0) := x"00000007";
constant ADDR_REG8 : std_logic_vector(31 downto 0) := x"00000008";
constant ADDR_REG9 : std_logic_vector(31 downto 0) := x"00000009";
constant ADDR_REGA : std_logic_vector(31 downto 0) := x"0000000A";
constant ADDR_REGB : std_logic_vector(31 downto 0) := x"0000000B";
constant ADDR_REGC : std_logic_vector(31 downto 0) := x"0000000C";
constant ADDR_REGD : std_logic_vector(31 downto 0) := x"0000000D";
constant ADDR_REGE : std_logic_vector(31 downto 0) := x"0000000E";
constant ADDR_REGF : std_logic_vector(31 downto 0) := x"0000000F";
----------------------------------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------------------------------
signal out_reg_val : std_logic;
signal out_reg_addr : std_logic_vector(27 downto 0);
signal out_reg : std_logic_vector(31 downto 0);
signal in_reg_req : std_logic;
signal in_reg_addr : std_logic_vector(27 downto 0);
signal in_reg_val : std_logic;
signal in_reg : std_logic_vector(31 downto 0);
signal out_reg_val_ack : std_logic;
signal wr_ack : std_logic;
signal register0 : std_logic_vector(31 downto 0);
signal register1 : std_logic_vector(31 downto 0);
signal register2 : std_logic_vector(31 downto 0);
signal register3 : std_logic_vector(31 downto 0);
signal register4 : std_logic_vector(31 downto 0);
signal register5 : std_logic_vector(31 downto 0);
signal register6 : std_logic_vector(31 downto 0);
signal register7 : std_logic_vector(31 downto 0);
signal register8 : std_logic_vector(31 downto 0);
signal register9 : std_logic_vector(31 downto 0);
signal registerA : std_logic_vector(31 downto 0);
--*************************************************************************************************
begin
--*************************************************************************************************
reg0 <= register0;
reg1 <= register1;
----------------------------------------------------------------------------------------------------
-- Stellar Command Interface
----------------------------------------------------------------------------------------------------
stellar_cmd_inst:
entity work.gbl_generic_cmd
generic map (
START_ADDR => START_ADDR,
STOP_ADDR => STOP_ADDR
)
port map (
reset => rst,
clk_cmd => clk_cmd,
in_cmd_val => in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => out_cmd_val,
out_cmd => out_cmd,
clk_reg => clk_cmd,
out_reg_val => out_reg_val,
out_reg_addr => out_reg_addr,
out_reg => out_reg,
out_reg_val_ack => out_reg_val_ack,
in_reg_req => in_reg_req,
in_reg_addr => in_reg_addr,
in_reg_val => in_reg_val,
in_reg => in_reg,
wr_ack => wr_ack,
mbx_in_val => mbx_in_val,
mbx_in_reg => mbx_in_reg
);
cmd_busy <= '0';
----------------------------------------------------------------------------------------------------
-- Registers
----------------------------------------------------------------------------------------------------
process (rst, clk_cmd)
begin
if (rst = '1') then
-- cmd_reg <= (others => '0');
in_reg_val <= '0';
in_reg <= (others => '0');
wr_ack <= '0';
register0 <= (others=>'0');
register1 <= (others=>'0');
elsif (rising_edge(clk_cmd)) then
------------------------------------------------------------
-- Write
------------------------------------------------------------
if ((out_reg_val = '1' or out_reg_val_ack = '1') and out_reg_addr = ADDR_REG0) then
register0 <= out_reg;
else
register0 <= (others=>'0');
end if;
if ((out_reg_val = '1' or out_reg_val_ack = '1') and out_reg_addr = ADDR_REG1) then
register1 <= out_reg;
end if;
-- Write acknowledge
if (out_reg_val_ack = '1') then
wr_ack <= '1';
else
wr_ack <= '0';
end if;
------------------------------------------------------------
-- Read
if (in_reg_req = '1' and in_reg_addr = ADDR_REG0) then
in_reg_val <= '1';
in_reg <= register0;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG1) then
in_reg_val <= '1';
in_reg <= register1;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG2) then
in_reg_val <= '1';
in_reg <= reg2;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG3) then
in_reg_val <= '1';
in_reg <= reg3;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG4) then
in_reg_val <= '1';
in_reg <= reg4;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG5) then
in_reg_val <= '1';
in_reg <= reg5;
elsif (in_reg_req = '1' and in_reg_addr = ADDR_REG6) then
in_reg_val <= '1';
in_reg <= reg6;
else
in_reg_val <= '0';
in_reg <= in_reg;
end if;
end if;
end process;
--*************************************************************************************************
end fmc_ctrl_syn;
--*************************************************************************************************
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1340.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p04n01i01340ent IS
END c08s04b01x00p04n01i01340ent;
ARCHITECTURE c08s04b01x00p04n01i01340arch OF c08s04b01x00p04n01i01340ent IS
signal X : integer := 0;
BEGIN
TESTING: PROCESS
BEGIN
X <= 15 after 10 ms;
wait for 10 ms;
assert NOT( X=15 )
report "***PASSED TEST: c08s04b01x00p04n01i01340"
severity NOTE;
assert ( X=15 )
report "***FAILED TEST: c08s04b01x00p04n01i01340 - Predefined TIME unit ms as the base type of the time expression test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p04n01i01340arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1340.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p04n01i01340ent IS
END c08s04b01x00p04n01i01340ent;
ARCHITECTURE c08s04b01x00p04n01i01340arch OF c08s04b01x00p04n01i01340ent IS
signal X : integer := 0;
BEGIN
TESTING: PROCESS
BEGIN
X <= 15 after 10 ms;
wait for 10 ms;
assert NOT( X=15 )
report "***PASSED TEST: c08s04b01x00p04n01i01340"
severity NOTE;
assert ( X=15 )
report "***FAILED TEST: c08s04b01x00p04n01i01340 - Predefined TIME unit ms as the base type of the time expression test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p04n01i01340arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1340.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p04n01i01340ent IS
END c08s04b01x00p04n01i01340ent;
ARCHITECTURE c08s04b01x00p04n01i01340arch OF c08s04b01x00p04n01i01340ent IS
signal X : integer := 0;
BEGIN
TESTING: PROCESS
BEGIN
X <= 15 after 10 ms;
wait for 10 ms;
assert NOT( X=15 )
report "***PASSED TEST: c08s04b01x00p04n01i01340"
severity NOTE;
assert ( X=15 )
report "***FAILED TEST: c08s04b01x00p04n01i01340 - Predefined TIME unit ms as the base type of the time expression test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p04n01i01340arch;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg.vhd
-- Description: This entity is the top level entity for the AXI Scatter Gather
-- Engine.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream out for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_INCLUDE_DESC_UPDATE : integer range 0 to 1 := 1;
-- Include or Exclude Scatter Gather Descriptor Update
-- 0 = Exclude Descriptor Update
-- 1 = Include Descriptor Update
C_INCLUDE_INTRPT : integer range 0 to 1 := 1;
-- Include/Exclude interrupt logic coalescing
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in usec
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1;
C_NUM_MM2S_CHANNELS : integer range 1 to 16 := 1;
C_ACTUAL_ADDR : integer range 32 to 64 := 32;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
--
dm_resetn : in std_logic ; --
sg_ctl : in std_logic_vector (7 downto 0) ;
--
-- Scatter Gather Write Address Channel --
m_axi_sg_awaddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awuser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awvalid : out std_logic ; --
m_axi_sg_awready : in std_logic ; --
--
-- Scatter Gather Write Data Channel --
m_axi_sg_wdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_wstrb : out std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
m_axi_sg_wlast : out std_logic ; --
m_axi_sg_wvalid : out std_logic ; --
m_axi_sg_wready : in std_logic ; --
--
-- Scatter Gather Write Response Channel --
m_axi_sg_bresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_bvalid : in std_logic ; --
m_axi_sg_bready : out std_logic ; --
--
-- Scatter Gather Read Address Channel --
m_axi_sg_araddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_aruser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arvalid : out std_logic ; --
m_axi_sg_arready : in std_logic ; --
--
-- Memory Map to Stream Scatter Gather Read Data Channel --
m_axi_sg_rdata : in std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rlast : in std_logic ; --
m_axi_sg_rvalid : in std_logic ; --
m_axi_sg_rready : out std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_cyclic : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
--
--
-- Channel 1 Interrupt Coalescing Signals --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ch1_ftch_aclk : in std_logic ; --
m_axis_ch1_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch1_ftch_tvalid : out std_logic ; --
m_axis_ch1_ftch_tready : in std_logic ; --
m_axis_ch1_ftch_tlast : out std_logic ; --
m_axis_ch1_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch1_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch1_ftch_tvalid_new : out std_logic ; --
m_axis_ftch1_desc_available : out std_logic;
--
--
-- Channel 1 AXI Update Stream In --
s_axis_ch1_updt_aclk : in std_logic ; --
s_axis_ch1_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_ch1_updtptr_tvalid : in std_logic ; --
s_axis_ch1_updtptr_tready : out std_logic ; --
s_axis_ch1_updtptr_tlast : in std_logic ; --
--
s_axis_ch1_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtsts_tvalid : in std_logic ; --
s_axis_ch1_updtsts_tready : out std_logic ; --
s_axis_ch1_updtsts_tlast : in std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_cyclic : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
--
-- Channel 2 Interrupt Coalescing Signals --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) ; --
ch2_update_active : out std_logic ;
--
-- Channel 2 AXI Fetch Stream Out --
m_axis_ch2_ftch_aclk : in std_logic ; --
m_axis_ch2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid : out std_logic ; --
m_axis_ch2_ftch_tready : in std_logic ; --
m_axis_ch2_ftch_tlast : out std_logic ; --
--
m_axis_ch2_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch2_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch2_ftch_tdata_mcdma_nxt : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid_new : out std_logic ; --
m_axis_ftch2_desc_available : out std_logic;
-- Channel 2 AXI Update Stream In --
s_axis_ch2_updt_aclk : in std_logic ; --
s_axis_ch2_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_ch2_updtptr_tvalid : in std_logic ; --
s_axis_ch2_updtptr_tready : out std_logic ; --
s_axis_ch2_updtptr_tlast : in std_logic ; --
--
--
s_axis_ch2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtsts_tvalid : in std_logic ; --
s_axis_ch2_updtsts_tready : out std_logic ; --
s_axis_ch2_updtsts_tlast : in std_logic ; --
--
--
-- Error addresses --
ftch_error : out std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_error : out std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic ;
bd_eq : out std_logic
);
end axi_sg;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant AXI_LITE_MODE : integer := 2; -- DataMover Lite Mode
constant EXCLUDE : integer := 0; -- Define Exclude as 0
constant NEVER_HALT : std_logic := '0'; -- Never halt sg datamover
-- Always include descriptor fetch (use lite datamover)
constant INCLUDE_DESC_FETCH : integer := AXI_LITE_MODE;
-- Selectable include descriptor update (use lite datamover)
constant INCLUDE_DESC_UPDATE : integer := AXI_LITE_MODE * C_INCLUDE_DESC_UPDATE;
-- Always allow address requests
constant ALWAYS_ALLOW : std_logic := '1';
-- If async mode and number of descriptors to fetch is zero then set number
-- of descriptors to fetch as 1.
constant SG_FTCH_DESC2QUEUE : integer := max2(C_SG_FTCH_DESC2QUEUE,C_AXIS_IS_ASYNC);
constant SG_UPDT_DESC2QUEUE : integer := max2(C_SG_UPDT_DESC2QUEUE,C_AXIS_IS_ASYNC);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- DataMover MM2S Fetch Command Stream Signals
signal s_axis_ftch_cmd_tvalid : std_logic := '0';
signal s_axis_ftch_cmd_tready : std_logic := '0';
signal s_axis_ftch_cmd_tdata : std_logic_vector
(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover MM2S Fetch Status Stream Signals
signal m_axis_ftch_sts_tvalid : std_logic := '0';
signal m_axis_ftch_sts_tready : std_logic := '0';
signal m_axis_ftch_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_ftch_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal mm2s_err : std_logic := '0';
-- DataMover MM2S Fetch Stream Signals
signal m_axis_mm2s_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_mm2s_tkeep : std_logic_vector
((C_M_AXIS_SG_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_mm2s_tlast : std_logic := '0';
signal m_axis_mm2s_tvalid : std_logic := '0';
signal m_axis_mm2s_tready : std_logic := '0';
-- DataMover S2MM Update Command Stream Signals
signal s_axis_updt_cmd_tvalid : std_logic := '0';
signal s_axis_updt_cmd_tready : std_logic := '0';
signal s_axis_updt_cmd_tdata : std_logic_vector
(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover S2MM Update Status Stream Signals
signal m_axis_updt_sts_tvalid : std_logic := '0';
signal m_axis_updt_sts_tready : std_logic := '0';
signal m_axis_updt_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_updt_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal s2mm_err : std_logic := '0';
-- DataMover S2MM Update Stream Signals
signal s_axis_s2mm_tdata : std_logic_vector
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_tkeep : std_logic_vector
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0) := (others => '1');
signal s_axis_s2mm_tlast : std_logic := '0';
signal s_axis_s2mm_tvalid : std_logic := '0';
signal s_axis_s2mm_tready : std_logic := '0';
-- Channel 1 internals
signal ch1_ftch_active : std_logic := '0';
signal ch1_ftch_queue_empty : std_logic := '0';
signal ch1_ftch_queue_full : std_logic := '0';
signal ch1_nxtdesc_wren : std_logic := '0';
signal ch1_updt_active : std_logic := '0';
signal ch1_updt_queue_empty : std_logic := '0';
signal ch1_updt_curdesc_wren : std_logic := '0';
signal ch1_updt_curdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch1_updt_ioc : std_logic := '0';
signal ch1_updt_ioc_irq_set_i : std_logic := '0';
signal ch1_dma_interr : std_logic := '0';
signal ch1_dma_slverr : std_logic := '0';
signal ch1_dma_decerr : std_logic := '0';
signal ch1_dma_interr_set_i : std_logic := '0';
signal ch1_dma_slverr_set_i : std_logic := '0';
signal ch1_dma_decerr_set_i : std_logic := '0';
signal ch1_updt_done : std_logic := '0';
signal ch1_ftch_pause : std_logic := '0';
-- Channel 2 internals
signal ch2_ftch_active : std_logic := '0';
signal ch2_ftch_queue_empty : std_logic := '0';
signal ch2_ftch_queue_full : std_logic := '0';
signal ch2_nxtdesc_wren : std_logic := '0';
signal ch2_updt_active : std_logic := '0';
signal ch2_updt_queue_empty : std_logic := '0';
signal ch2_updt_curdesc_wren : std_logic := '0';
signal ch2_updt_curdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch2_updt_ioc : std_logic := '0';
signal ch2_updt_ioc_irq_set_i : std_logic := '0';
signal ch2_dma_interr : std_logic := '0';
signal ch2_dma_slverr : std_logic := '0';
signal ch2_dma_decerr : std_logic := '0';
signal ch2_dma_interr_set_i : std_logic := '0';
signal ch2_dma_slverr_set_i : std_logic := '0';
signal ch2_dma_decerr_set_i : std_logic := '0';
signal ch2_updt_done : std_logic := '0';
signal ch2_ftch_pause : std_logic := '0';
signal nxtdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ftch_cmnd_wr : std_logic := '0';
signal ftch_cmnd_data : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
signal ftch_stale_desc : std_logic := '0';
signal ftch_error_i : std_logic := '0';
signal updt_error_i : std_logic := '0';
signal ch1_irqthresh_decr : std_logic := '0'; --CR567661
signal ch2_irqthresh_decr : std_logic := '0'; --CR567661
signal m_axi_sg_awaddr_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal m_axi_sg_awlen_int : std_logic_vector(7 downto 0) ; --
signal m_axi_sg_awsize_int : std_logic_vector(2 downto 0) ; --
signal m_axi_sg_awburst_int : std_logic_vector(1 downto 0) ; --
signal m_axi_sg_awprot_int : std_logic_vector(2 downto 0) ; --
signal m_axi_sg_awcache_int : std_logic_vector(3 downto 0) ; --
signal m_axi_sg_awuser_int : std_logic_vector(3 downto 0) ; --
signal m_axi_sg_awvalid_int : std_logic ; --
signal m_axi_sg_awready_int : std_logic ; --
--
-- Scatter Gather Write Data Channel --
signal m_axi_sg_wdata_int : std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
signal m_axi_sg_wstrb_int : std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
signal m_axi_sg_wlast_int : std_logic ; --
signal m_axi_sg_wvalid_int : std_logic ; --
signal m_axi_sg_wready_int : std_logic ; --
signal m_axi_sg_bresp_int : std_logic_vector (1 downto 0);
signal m_axi_sg_bvalid_int : std_logic;
signal m_axi_sg_bready_int : std_logic;
signal m_axi_sg_bvalid_int_del : std_logic;
signal ch2_eof_detected : std_logic;
signal s_axis_ch2_updtsts_tready_i : std_logic;
signal ch2_sg_idle, tail_updt_latch : std_logic;
signal tail_updt : std_logic;
signal ch2_taildesc_wren_int : std_logic;
signal ch2_sg_idle_int : std_logic;
signal ftch_error_addr_1 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
signal updt_error_addr_1 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
signal ch1_ftch_interr_set_i : std_logic := '0';
signal ch1_ftch_slverr_set_i : std_logic := '0';
signal ch1_ftch_decerr_set_i : std_logic := '0';
signal ch2_ftch_interr_set_i : std_logic := '0';
signal ch2_ftch_slverr_set_i : std_logic := '0';
signal ch2_ftch_decerr_set_i : std_logic := '0';
signal ch1_updt_interr_set_i : std_logic := '0';
signal ch1_updt_slverr_set_i : std_logic := '0';
signal ch1_updt_decerr_set_i : std_logic := '0';
signal ch2_updt_interr_set_i : std_logic := '0';
signal ch2_updt_slverr_set_i : std_logic := '0';
signal ch2_updt_decerr_set_i : std_logic := '0';
signal ftch_error_capture : std_logic := '0';
signal updt_error_capture : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_error <= updt_error_i;
ftch_error <= ftch_error_i;
ftch_error_capture <= ch1_ftch_interr_set_i or
ch1_ftch_slverr_set_i or
ch1_ftch_decerr_set_i or
ch2_ftch_interr_set_i or
ch2_ftch_slverr_set_i or
ch2_ftch_decerr_set_i;
ch1_ftch_interr_set <= ch1_ftch_interr_set_i;
ch1_ftch_slverr_set <= ch1_ftch_slverr_set_i;
ch1_ftch_decerr_set <= ch1_ftch_decerr_set_i;
ch2_ftch_interr_set <= ch2_ftch_interr_set_i;
ch2_ftch_slverr_set <= ch2_ftch_slverr_set_i;
ch2_ftch_decerr_set <= ch2_ftch_decerr_set_i;
updt_error_capture <= ch1_updt_interr_set_i or
ch1_updt_slverr_set_i or
ch1_updt_decerr_set_i or
ch2_updt_interr_set_i or
ch2_updt_slverr_set_i or
ch2_updt_decerr_set_i or
ch2_dma_interr_set_i or
ch2_dma_slverr_set_i or
ch2_dma_decerr_set_i or
ch1_dma_interr_set_i or
ch1_dma_slverr_set_i or
ch1_dma_decerr_set_i;
ch1_updt_interr_set <= ch1_updt_interr_set_i;
ch1_updt_slverr_set <= ch1_updt_slverr_set_i;
ch1_updt_decerr_set <= ch1_updt_decerr_set_i;
ch2_updt_interr_set <= ch2_updt_interr_set_i;
ch2_updt_slverr_set <= ch2_updt_slverr_set_i;
ch2_updt_decerr_set <= ch2_updt_decerr_set_i;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
ftch_error_addr (31 downto 6) <= (others => '0');
elsif (ftch_error_capture = '1') then -- or updt_error_i = '1') then
ftch_error_addr (31 downto 6)<= ftch_error_addr_1(31 downto 6);
elsif (updt_error_capture = '1') then
ftch_error_addr (31 downto 6)<= updt_error_addr_1(31 downto 6);
end if;
end if;
end process;
ADDR_64 : if (C_M_AXI_SG_ADDR_WIDTH > 32) generate
begin
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
ftch_error_addr (63 downto 32) <= (others => '0');
elsif (ftch_error_capture = '1') then -- or updt_error_i = '1') then
ftch_error_addr (63 downto 32)<= ftch_error_addr_1(63 downto 32);
elsif (updt_error_capture = '1') then
ftch_error_addr (63 downto 32)<= updt_error_addr_1(63 downto 32);
end if;
end if;
end process;
end generate ADDR_64;
updt_error_addr <= (others => '0');
ftch_error_addr (5 downto 0) <= (others => '0');
-- Always valid therefore fix to '1'
s_axis_s2mm_tkeep <= (others => '1');
-- Drive interrupt on complete set out
--ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i; -- CR567661
--ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i; -- CR567661
ch1_dma_interr_set <= ch1_dma_interr_set_i;
ch1_dma_slverr_set <= ch1_dma_slverr_set_i;
ch1_dma_decerr_set <= ch1_dma_decerr_set_i;
ch2_dma_interr_set <= ch2_dma_interr_set_i;
ch2_dma_slverr_set <= ch2_dma_slverr_set_i;
ch2_dma_decerr_set <= ch2_dma_decerr_set_i;
s_axis_ch2_updtsts_tready <= s_axis_ch2_updtsts_tready_i;
EOF_DET : if (C_ENABLE_MULTI_CHANNEL = 1) generate
ch2_eof_detected <= s_axis_ch2_updtsts_tdata (26)
and s_axis_ch2_updtsts_tready_i
and s_axis_ch2_updtsts_tvalid
and s_axis_ch2_updtsts_tlast;
-- ch2_eof_detected <= '0';
ch2_sg_idle_int <= ch2_sg_idle;
-- ch2_sg_idle_int <= '0'; --ch2_sg_idle;
TAILUPDT_LATCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or tail_updt = '1' ) then -- nned to have some reset condition here
tail_updt <= '0';
elsif(ch2_sg_idle = '1' and tail_updt_latch = '1' and tail_updt = '0')then
tail_updt <= '1';
end if;
end if;
end process TAILUPDT_LATCH;
ch2_taildesc_wren_int <= ch2_taildesc_wren or tail_updt;
--ch2_taildesc_wren_int <= ch2_taildesc_wren;
end generate EOF_DET;
NOEOF_DET : if (C_ENABLE_MULTI_CHANNEL = 0) generate
tail_updt <= '0';
ch2_eof_detected <= '0';
ch2_taildesc_wren_int <= ch2_taildesc_wren;
ch2_sg_idle_int <= '0'; --ch2_sg_idle;
end generate NOEOF_DET;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Manager
-------------------------------------------------------------------------------
I_SG_FETCH_MNGR : entity axi_sg_v4_1_3.axi_sg_ftch_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
ch1_run_stop => ch1_run_stop ,
ch1_desc_flush => ch1_desc_flush ,
ch1_updt_done => ch1_updt_done ,
ch1_ftch_idle => ch1_ftch_idle ,
ch1_ftch_active => ch1_ftch_active ,
ch1_ftch_interr_set => ch1_ftch_interr_set_i ,
ch1_ftch_slverr_set => ch1_ftch_slverr_set_i ,
ch1_ftch_decerr_set => ch1_ftch_decerr_set_i ,
ch1_ftch_err_early => ch1_ftch_err_early ,
ch1_ftch_stale_desc => ch1_ftch_stale_desc ,
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_taildesc_wren => ch1_taildesc_wren ,
ch1_taildesc => ch1_taildesc ,
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
ch1_curdesc => ch1_curdesc ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control and Status
ch2_run_stop => ch2_run_stop ,
ch2_desc_flush => ch2_desc_flush ,
ch2_updt_done => ch2_updt_done ,
ch2_ftch_idle => ch2_ftch_idle ,
ch2_ftch_active => ch2_ftch_active ,
ch2_ftch_interr_set => ch2_ftch_interr_set_i ,
ch2_ftch_slverr_set => ch2_ftch_slverr_set_i ,
ch2_ftch_decerr_set => ch2_ftch_decerr_set_i ,
ch2_ftch_err_early => ch2_ftch_err_early ,
ch2_ftch_stale_desc => ch2_ftch_stale_desc ,
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_taildesc_wren => ch2_taildesc_wren_int ,
ch2_taildesc => ch2_taildesc ,
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
ch2_curdesc => ch2_curdesc ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_ftch_pause => ch2_ftch_pause ,
ch2_eof_detected => ch2_eof_detected ,
tail_updt => tail_updt ,
tail_updt_latch => tail_updt_latch ,
ch2_sg_idle => ch2_sg_idle ,
nxtdesc => nxtdesc ,
-- Read response for detecting slverr, decerr early
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
-- User Command Interface Ports (AXI Stream)
s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_ftch_sts_tready => m_axis_ftch_sts_tready ,
m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep ,
mm2s_err => mm2s_err ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
ftch_stale_desc => ftch_stale_desc ,
updt_error => updt_error_i ,
ftch_error => ftch_error_i ,
ftch_error_addr => ftch_error_addr_1 ,
bd_eq => bd_eq
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Queue
-------------------------------------------------------------------------------
I_SG_FETCH_QUEUE : entity axi_sg_v4_1_3.axi_sg_ftch_q_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_ASYNC => C_ASYNC ,
C_ENABLE_CDMA => C_ENABLE_CDMA,
C_ACTUAL_ADDR => C_ACTUAL_ADDR,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
p_reset_n => p_reset_n ,
ch2_sg_idle => ch2_sg_idle_int ,
-- Channel 1 Control
ch1_desc_flush => ch1_desc_flush ,
ch1_cyclic => ch1_cyclic ,
ch1_cntrl_strm_stop => ch1_cntrl_strm_stop ,
ch1_ftch_active => ch1_ftch_active ,
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control
ch2_ftch_active => ch2_ftch_active ,
ch2_cyclic => ch2_cyclic ,
ch2_desc_flush => ch2_desc_flush ,
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_ftch_pause => ch2_ftch_pause ,
nxtdesc => nxtdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
ftch_stale_desc => ftch_stale_desc ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ch1_ftch_aclk => m_axis_ch1_ftch_aclk ,
m_axis_ch1_ftch_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ch1_ftch_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ch1_ftch_tready => m_axis_ch1_ftch_tready ,
m_axis_ch1_ftch_tlast => m_axis_ch1_ftch_tlast ,
m_axis_ch1_ftch_tdata_new => m_axis_ch1_ftch_tdata_new ,
m_axis_ch1_ftch_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new ,
m_axis_ch1_ftch_tvalid_new => m_axis_ch1_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available,
m_axis_ch2_ftch_tdata_new => m_axis_ch2_ftch_tdata_new ,
m_axis_ch2_ftch_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new ,
m_axis_ch2_ftch_tdata_mcdma_nxt => m_axis_ch2_ftch_tdata_mcdma_nxt ,
m_axis_ch2_ftch_tvalid_new => m_axis_ch2_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available,
-- Channel 2 AXI Fetch Stream Out
m_axis_ch2_ftch_aclk => m_axis_ch2_ftch_aclk ,
m_axis_ch2_ftch_tdata => m_axis_ch2_ftch_tdata ,
m_axis_ch2_ftch_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis_ch2_ftch_tready => m_axis_ch2_ftch_tready ,
m_axis_ch2_ftch_tlast => m_axis_ch2_ftch_tlast ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
-- Include Scatter Gather Descriptor Update logic
GEN_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 1 generate
begin
-- CR567661
-- Route update version of IOC set to threshold
-- counter decrement control
ch1_irqthresh_decr <= ch1_updt_ioc_irq_set_i;
ch2_irqthresh_decr <= ch2_updt_ioc_irq_set_i;
-- Drive interrupt on complete set out
ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i;
ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i;
-------------------------------------------------------------------------------
-- Scatter Gather Update Manager
-------------------------------------------------------------------------------
I_SG_UPDATE_MNGR : entity axi_sg_v4_1_3.axi_sg_updt_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => C_SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH2_FIRST_UPDATE_WORD => C_SG_CH2_FIRST_UPDATE_WORD
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
ch1_updt_idle => ch1_updt_idle ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i ,
-- Update Descriptor Status
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set_i ,
ch1_dma_slverr_set => ch1_dma_slverr_set_i ,
ch1_dma_decerr_set => ch1_dma_decerr_set_i ,
ch1_updt_interr_set => ch1_updt_interr_set_i ,
ch1_updt_slverr_set => ch1_updt_slverr_set_i ,
ch1_updt_decerr_set => ch1_updt_decerr_set_i ,
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_done => ch1_updt_done ,
-- Channel 2 Control and Status
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_updt_idle => ch2_updt_idle ,
ch2_updt_active => ch2_updt_active ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i ,
ch2_dma_interr_set => ch2_dma_interr_set_i ,
ch2_dma_slverr_set => ch2_dma_slverr_set_i ,
ch2_dma_decerr_set => ch2_dma_decerr_set_i ,
ch2_updt_interr_set => ch2_updt_interr_set_i ,
ch2_updt_slverr_set => ch2_updt_slverr_set_i ,
ch2_updt_decerr_set => ch2_updt_decerr_set_i ,
ch2_updt_queue_empty => ch2_updt_queue_empty ,
-- ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
-- ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_done => ch2_updt_done ,
-- User Command Interface Ports (AXI Stream)
s_axis_updt_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_updt_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_updt_cmd_tdata => s_axis_updt_cmd_tdata ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_updt_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_updt_sts_tready => m_axis_updt_sts_tready ,
m_axis_updt_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_updt_sts_tkeep => m_axis_updt_sts_tkeep ,
s2mm_err => s2mm_err ,
ftch_error => ftch_error_i ,
updt_error => updt_error_i ,
updt_error_addr => updt_error_addr_1
);
-------------------------------------------------------------------------------
-- Scatter Gather Update Queue
-------------------------------------------------------------------------------
I_SG_UPDATE_QUEUE : entity axi_sg_v4_1_3.axi_sg_updt_q_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i ,
-- Channel 1 Update Descriptor Status
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set_i ,
ch1_dma_slverr_set => ch1_dma_slverr_set_i ,
ch1_dma_decerr_set => ch1_dma_decerr_set_i ,
-- Channel 2 Control
ch2_updt_active => ch2_updt_active ,
-- ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
-- ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_queue_empty => ch2_updt_queue_empty ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i ,
-- Channel 2 Update Descriptor Status
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_dma_interr_set => ch2_dma_interr_set_i ,
ch2_dma_slverr_set => ch2_dma_slverr_set_i ,
ch2_dma_decerr_set => ch2_dma_decerr_set_i ,
-- S2MM Stream Out To DataMover
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready ,
-- Channel 1 AXI Update Stream In
s_axis_ch1_updt_aclk => s_axis_ch1_updt_aclk ,
s_axis_ch1_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_ch1_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_ch1_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_ch1_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
s_axis_ch1_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_ch1_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_ch1_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_ch1_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
-- Channel 2 AXI Update Stream In
s_axis_ch2_updt_aclk => s_axis_ch2_updt_aclk ,
s_axis_ch2_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis_ch2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis_ch2_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis_ch2_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
s_axis_ch2_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis_ch2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis_ch2_updtsts_tready => s_axis_ch2_updtsts_tready_i ,
s_axis_ch2_updtsts_tlast => s_axis_ch2_updtsts_tlast
);
end generate GEN_DESC_UPDATE;
-- Exclude Scatter Gather Descriptor Update logic
GEN_NO_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 0 generate
begin
ch1_updt_idle <= '1';
ch1_updt_active <= '0';
-- ch1_updt_ioc_irq_set <= '0';--CR#569609
ch1_updt_interr_set <= '0';
ch1_updt_slverr_set <= '0';
ch1_updt_decerr_set <= '0';
ch1_dma_interr_set_i <= '0';
ch1_dma_slverr_set_i <= '0';
ch1_dma_decerr_set_i <= '0';
ch1_updt_done <= '1'; -- Always done
ch2_updt_idle <= '1';
ch2_updt_active <= '0';
-- ch2_updt_ioc_irq_set <= '0'; --CR#569609
ch2_updt_interr_set <= '0';
ch2_updt_slverr_set <= '0';
ch2_updt_decerr_set <= '0';
ch2_dma_interr_set_i <= '0';
ch2_dma_slverr_set_i <= '0';
ch2_dma_decerr_set_i <= '0';
ch2_updt_done <= '1'; -- Always done
s_axis_updt_cmd_tvalid <= '0';
s_axis_updt_cmd_tdata <= (others => '0');
m_axis_updt_sts_tready <= '0';
updt_error_i <= '0';
updt_error_addr <= (others => '0');
ch1_updt_curdesc_wren <= '0';
ch1_updt_curdesc <= (others => '0');
ch1_updt_queue_empty <= '0';
ch1_updt_ioc <= '0';
ch1_dma_interr <= '0';
ch1_dma_slverr <= '0';
ch1_dma_decerr <= '0';
ch2_updt_curdesc_wren <= '0';
ch2_updt_curdesc <= (others => '0');
ch2_updt_queue_empty <= '0';
ch2_updt_ioc <= '0';
ch2_dma_interr <= '0';
ch2_dma_slverr <= '0';
ch2_dma_decerr <= '0';
s_axis_s2mm_tdata <= (others => '0');
s_axis_s2mm_tlast <= '0';
s_axis_s2mm_tvalid <= '0';
s_axis_ch1_updtptr_tready <= '0';
s_axis_ch2_updtptr_tready <= '0';
s_axis_ch1_updtsts_tready <= '0';
s_axis_ch2_updtsts_tready <= '0';
-- CR567661
-- Route packet eof to threshold counter decrement control
ch1_irqthresh_decr <= ch1_packet_eof;
ch2_irqthresh_decr <= ch2_packet_eof;
-- Drive interrupt on complete set out
ch1_updt_ioc_irq_set <= ch1_packet_eof;
ch2_updt_ioc_irq_set <= ch2_packet_eof;
end generate GEN_NO_DESC_UPDATE;
-------------------------------------------------------------------------------
-- Scatter Gather Interrupt Coalescing
-------------------------------------------------------------------------------
GEN_INTERRUPT_LOGIC : if C_INCLUDE_INTRPT = 1 generate
begin
I_AXI_SG_INTRPT : entity axi_sg_v4_1_3.axi_sg_intrpt
generic map(
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_INCLUDE_DLYTMR => C_INCLUDE_DLYTMR ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
ch1_irqthresh_decr => ch1_irqthresh_decr , -- CR567661
ch1_irqthresh_rstdsbl => ch1_irqthresh_rstdsbl , -- CR572013
ch1_dlyirq_dsble => ch1_dlyirq_dsble ,
ch1_irqdelay_wren => ch1_irqdelay_wren ,
ch1_irqdelay => ch1_irqdelay ,
ch1_irqthresh_wren => ch1_irqthresh_wren ,
ch1_irqthresh => ch1_irqthresh ,
ch1_packet_sof => ch1_packet_sof ,
ch1_packet_eof => ch1_packet_eof ,
ch1_ioc_irq_set => ch1_ioc_irq_set ,
ch1_dly_irq_set => ch1_dly_irq_set ,
ch1_irqdelay_status => ch1_irqdelay_status ,
ch1_irqthresh_status => ch1_irqthresh_status ,
ch2_irqthresh_decr => ch2_irqthresh_decr , -- CR567661
ch2_irqthresh_rstdsbl => ch2_irqthresh_rstdsbl , -- CR572013
ch2_dlyirq_dsble => ch2_dlyirq_dsble ,
ch2_irqdelay_wren => ch2_irqdelay_wren ,
ch2_irqdelay => ch2_irqdelay ,
ch2_irqthresh_wren => ch2_irqthresh_wren ,
ch2_irqthresh => ch2_irqthresh ,
ch2_packet_sof => ch2_packet_sof ,
ch2_packet_eof => ch2_packet_eof ,
ch2_ioc_irq_set => ch2_ioc_irq_set ,
ch2_dly_irq_set => ch2_dly_irq_set ,
ch2_irqdelay_status => ch2_irqdelay_status ,
ch2_irqthresh_status => ch2_irqthresh_status
);
end generate GEN_INTERRUPT_LOGIC;
GEN_NO_INTRPT_LOGIC : if C_INCLUDE_INTRPT = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_NO_INTRPT_LOGIC;
-------------------------------------------------------------------------------
-- Scatter Gather DataMover Lite
-------------------------------------------------------------------------------
I_SG_AXI_DATAMOVER : entity axi_sg_v4_1_3.axi_sg_datamover
generic map(
C_INCLUDE_MM2S => 2, --INCLUDE_DESC_FETCH, -- Lite
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_INCLUDE_MM2S_STSFIFO => 0, -- Exclude
C_MM2S_STSCMD_FIFO_DEPTH => 1, -- Set to Min
C_MM2S_STSCMD_IS_ASYNC => 0, -- Synchronous
C_INCLUDE_MM2S_DRE => 0, -- No DRE
C_MM2S_BURST_SIZE => 16, -- Set to Min
C_MM2S_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request
C_MM2S_INCLUDE_SF => 0, -- Exclude Store-and-Forward
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL, --
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD,
C_INCLUDE_S2MM => 2, --INCLUDE_DESC_UPDATE, -- Lite
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_S_AXIS_S2MM_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_INCLUDE_S2MM_STSFIFO => 0, -- Exclude
C_S2MM_STSCMD_FIFO_DEPTH => 1, -- Set to Min
C_S2MM_STSCMD_IS_ASYNC => 0, -- Synchronous
C_INCLUDE_S2MM_DRE => 0, -- No DRE
C_S2MM_BURST_SIZE => 16, -- Set to Min;
C_S2MM_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request
C_S2MM_INCLUDE_SF => 0, -- Exclude Store-and-Forward
C_FAMILY => C_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => m_axi_sg_aclk ,
m_axi_mm2s_aresetn => dm_resetn ,
mm2s_halt => NEVER_HALT ,
mm2s_halt_cmplt => open ,
mm2s_err => mm2s_err ,
mm2s_allow_addr_req => ALWAYS_ALLOW ,
mm2s_addr_req_posted => open ,
mm2s_rd_xfer_cmplt => open ,
sg_ctl => sg_ctl ,
-- Memory Map to Stream Command FIFO and Status FIFO I/O --------------
m_axis_mm2s_cmdsts_aclk => m_axi_sg_aclk ,
m_axis_mm2s_cmdsts_aresetn => dm_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_ftch_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_ftch_sts_tkeep ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_sg_araddr ,
m_axi_mm2s_arlen => m_axi_sg_arlen ,
m_axi_mm2s_arsize => m_axi_sg_arsize ,
m_axi_mm2s_arburst => m_axi_sg_arburst ,
m_axi_mm2s_arprot => m_axi_sg_arprot ,
m_axi_mm2s_arcache => m_axi_sg_arcache ,
m_axi_mm2s_aruser => m_axi_sg_aruser ,
m_axi_mm2s_arvalid => m_axi_sg_arvalid ,
m_axi_mm2s_arready => m_axi_sg_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_sg_rdata ,
m_axi_mm2s_rresp => m_axi_sg_rresp ,
m_axi_mm2s_rlast => m_axi_sg_rlast ,
m_axi_mm2s_rvalid => m_axi_sg_rvalid ,
m_axi_mm2s_rready => m_axi_sg_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => m_axi_sg_aclk ,
m_axi_s2mm_aresetn => dm_resetn ,
s2mm_halt => NEVER_HALT ,
s2mm_halt_cmplt => open ,
s2mm_err => s2mm_err ,
s2mm_allow_addr_req => ALWAYS_ALLOW ,
s2mm_addr_req_posted => open ,
s2mm_wr_xfer_cmplt => open ,
s2mm_ld_nxt_len => open ,
s2mm_wr_len => open ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => m_axi_sg_aclk ,
m_axis_s2mm_cmdsts_aresetn => dm_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_updt_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_updt_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_updt_sts_tkeep ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_sg_awaddr_int ,
m_axi_s2mm_awlen => m_axi_sg_awlen_int ,
m_axi_s2mm_awsize => m_axi_sg_awsize_int ,
m_axi_s2mm_awburst => m_axi_sg_awburst_int ,
m_axi_s2mm_awprot => m_axi_sg_awprot_int ,
m_axi_s2mm_awcache => m_axi_sg_awcache_int ,
m_axi_s2mm_awuser => m_axi_sg_awuser_int ,
m_axi_s2mm_awvalid => m_axi_sg_awvalid_int ,
m_axi_s2mm_awready => m_axi_sg_awready_int ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_sg_wdata ,
m_axi_s2mm_wstrb => m_axi_sg_wstrb ,
m_axi_s2mm_wlast => m_axi_sg_wlast ,
m_axi_s2mm_wvalid => m_axi_sg_wvalid_int ,
m_axi_s2mm_wready => m_axi_sg_wready_int ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_sg_bresp_int ,
m_axi_s2mm_bvalid => m_axi_sg_bvalid_int ,
m_axi_s2mm_bready => m_axi_sg_bready_int ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
--ENABLE_MM2S_STATUS: if (C_NUM_MM2S_CHANNELS = 1) generate
-- begin
m_axi_sg_awaddr <= m_axi_sg_awaddr_int ;
m_axi_sg_awlen <= m_axi_sg_awlen_int ;
m_axi_sg_awsize <= m_axi_sg_awsize_int ;
m_axi_sg_awburst <= m_axi_sg_awburst_int;
m_axi_sg_awprot <= m_axi_sg_awprot_int ;
m_axi_sg_awcache <= m_axi_sg_awcache_int;
m_axi_sg_awuser <= m_axi_sg_awuser_int ;
m_axi_sg_awvalid <= m_axi_sg_awvalid_int;
m_axi_sg_awready_int <= m_axi_sg_awready;
m_axi_sg_wvalid <= m_axi_sg_wvalid_int;
m_axi_sg_wready_int <= m_axi_sg_wready;
m_axi_sg_bresp_int <= m_axi_sg_bresp;
m_axi_sg_bvalid_int <= m_axi_sg_bvalid;
m_axi_sg_bready <= m_axi_sg_bready_int;
-- end generate ENABLE_MM2S_STATUS;
--DISABLE_MM2S_STATUS: if (C_NUM_MM2S_CHANNELS > 1) generate
--
-- m_axi_sg_awaddr <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awaddr_int;
-- m_axi_sg_awlen <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awlen_int;
-- m_axi_sg_awsize <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awsize_int;
-- m_axi_sg_awburst <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awburst_int;
-- m_axi_sg_awprot <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awprot_int;
-- m_axi_sg_awcache <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awcache_int;
-- m_axi_sg_awuser <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awuser_int;
-- m_axi_sg_awvalid <= '0' when ch1_updt_active = '1' else m_axi_sg_awvalid_int;
-- m_axi_sg_awready_int <= m_axi_sg_awvalid_int when ch1_updt_active = '1' else m_axi_sg_awready; -- to make sure that AXI logic is fine.
--
-- m_axi_sg_wvalid <= '0' when ch1_updt_active = '1' else m_axi_sg_wvalid_int;
-- m_axi_sg_wready_int <= m_axi_sg_wvalid_int when ch1_updt_active = '1' else m_axi_sg_wready; -- to make sure that AXI logic is fine
--
-- m_axi_sg_bresp_int <= m_axi_sg_bresp;
-- m_axi_sg_bvalid_int <= m_axi_sg_bvalid_int_del when ch1_updt_active = '1' else m_axi_sg_bvalid;
-- m_axi_sg_bready <= m_axi_sg_bready_int;
--
ch2_update_active <= ch2_updt_active;
--
---- A dummy response is needed to keep things running on DMA side
-- PROC_DUMMY_RESP : process (m_axi_sg_aclk)
-- begin
-- if (dm_resetn = '0') then
-- m_axi_sg_bvalid_int_del <= '0';
-- elsif (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- m_axi_sg_bvalid_int_del <= m_axi_sg_wvalid_int;
-- end if;
-- end process PROC_DUMMY_RESP;
--
-- end generate DISABLE_MM2S_STATUS;
end implementation;
|
entity test is
type t is range 0 to 16#f.f2;
end;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_ab
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:27 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_MIXED -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ab-rtl-conf-c.vhd,v 1.4 2005/07/19 07:13:20 wig Exp $
-- $Date: 2005/07/19 07:13:20 $
-- $Log: ent_ab-rtl-conf-c.vhd,v $
-- Revision 1.4 2005/07/19 07:13:20 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_ab_rtl_conf / ent_ab
--
configuration ent_ab_rtl_conf of ent_ab is
for rtl
-- Generated Configuration
end for;
end ent_ab_rtl_conf;
--
-- End of Generated Configuration ent_ab_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
----------------------------------------------------------------------------------
-- Company: ESA
-- Engineer: Felix Winterstein
--
-- Create Date: 06.04.2013 21:02:35
-- Design Name:
-- Module Name: dsp_round - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity dsp_round is
generic (
BITWIDTH_IN : integer := 32;
BITWIDTH_OUT : integer := 32
);
port (
sclr : in std_logic;
nd : in std_logic;
AB_IN : in std_logic_vector (BITWIDTH_IN-1 downto 0);
CARRYIN_IN : in std_logic;
CLK_IN : in std_logic;
C_IN : in std_logic_vector (BITWIDTH_IN-1 downto 0);
P_OUT : out std_logic_vector (BITWIDTH_OUT-1 downto 0);
rdy : out std_logic
);
end dsp_round;
architecture BEHAVIORAL of dsp_round is
constant LAT : integer := 2;
signal GND_ALUMODE : std_logic;
signal GND_BUS_3 : std_logic_vector (2 downto 0);
signal GND_BUS_18 : std_logic_vector (17 downto 0);
signal GND_BUS_30 : std_logic_vector (29 downto 0);
signal GND_BUS_48 : std_logic_vector (47 downto 0);
signal GND_OPMODE : std_logic;
signal VCC_OPMODE : std_logic;
signal ab_in_ext : std_logic_vector(47 downto 0);
signal c_in_ext : std_logic_vector(47 downto 0);
signal p_out_ext : std_logic_vector(47 downto 0);
signal delay_line : std_logic_vector(0 to LAT-1);
begin
GND_ALUMODE <= '0';
GND_BUS_3(2 downto 0) <= "000";
GND_BUS_18(17 downto 0) <= "000000000000000000";
GND_BUS_30(29 downto 0) <= "000000000000000000000000000000";
GND_BUS_48(47 downto 0) <=
"000000000000000000000000000000000000000000000000";
GND_OPMODE <= '0';
VCC_OPMODE <= '1';
ab_in_ext(47 downto BITWIDTH_IN) <= (others => AB_IN(BITWIDTH_IN-1));
ab_in_ext(BITWIDTH_IN-1 downto 0) <= AB_IN;
c_in_ext(47 downto BITWIDTH_IN) <= (others => C_IN(BITWIDTH_IN-1));
c_in_ext(BITWIDTH_IN-1 downto 0) <= C_IN;
DSP48E_INST : DSP48E
generic map( ACASCREG => 1,
ALUMODEREG => 0,
AREG => 1,
AUTORESET_PATTERN_DETECT => FALSE,
AUTORESET_PATTERN_DETECT_OPTINV => "MATCH",
A_INPUT => "DIRECT",
BCASCREG => 1,
BREG => 1,
B_INPUT => "DIRECT",
CARRYINREG => 1,
CARRYINSELREG => 0,
CREG => 1,
MASK => x"3FFFFFFFFFFF",
MREG => 1,
MULTCARRYINREG => 1,
OPMODEREG => 0,
PATTERN => x"000000000000",
PREG => 1,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
SEL_ROUNDING_MASK => "SEL_MASK",
USE_MULT => "NONE",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48")
port map (A(29 downto 0)=>ab_in_ext(47 downto 18),
ACIN(29 downto 0)=>GND_BUS_30(29 downto 0),
ALUMODE(3)=>GND_ALUMODE,
ALUMODE(2)=>GND_ALUMODE,
ALUMODE(1)=>GND_ALUMODE,
ALUMODE(0)=>GND_ALUMODE,
B(17 downto 0)=>ab_in_ext(17 downto 0),
BCIN(17 downto 0)=>GND_BUS_18(17 downto 0),
C(47 downto 0)=>c_in_ext(47 downto 0),
CARRYCASCIN=>GND_ALUMODE,
CARRYIN=>CARRYIN_IN,
CARRYINSEL(2 downto 0)=>GND_BUS_3(2 downto 0),
CEALUMODE=>VCC_OPMODE,
CEA1=>VCC_OPMODE,
CEA2=>VCC_OPMODE,
CEB1=>VCC_OPMODE,
CEB2=>VCC_OPMODE,
CEC=>VCC_OPMODE,
CECARRYIN=>VCC_OPMODE,
CECTRL=>VCC_OPMODE,
CEM=>VCC_OPMODE,
CEMULTCARRYIN=>VCC_OPMODE,
CEP=>VCC_OPMODE,
CLK=>CLK_IN,
MULTSIGNIN=>GND_ALUMODE,
OPMODE(6)=>GND_OPMODE,
OPMODE(5)=>VCC_OPMODE,
OPMODE(4)=>VCC_OPMODE,
OPMODE(3)=>GND_OPMODE,
OPMODE(2)=>GND_OPMODE,
OPMODE(1)=>VCC_OPMODE,
OPMODE(0)=>VCC_OPMODE,
PCIN(47 downto 0)=>GND_BUS_48(47 downto 0),
RSTA=>GND_ALUMODE,
RSTALLCARRYIN=>GND_ALUMODE,
RSTALUMODE=>GND_ALUMODE,
RSTB=>GND_ALUMODE,
RSTC=>GND_ALUMODE,
RSTCTRL=>GND_ALUMODE,
RSTM=>GND_ALUMODE,
RSTP=>GND_ALUMODE,
ACOUT=>open,
BCOUT=>open,
CARRYCASCOUT=>open,
CARRYOUT=>open,
MULTSIGNOUT=>open,
OVERFLOW=>open,
P(47 downto 0)=>p_out_ext(47 downto 0),
PATTERNBDETECT=>open,
PATTERNDETECT=>open,
PCOUT=>open,
UNDERFLOW=>open);
P_OUT <= p_out_ext(BITWIDTH_IN-1 downto BITWIDTH_IN-BITWIDTH_OUT);
delay_line_proc : process(CLK_IN)
begin
if rising_edge(CLK_IN) then
if sclr = '1' then
delay_line <= (others => '0');
else
delay_line(0) <= nd;
delay_line(1 to LAT-1) <= delay_line(0 to LAT-2);
end if;
end if;
end process delay_line_proc;
rdy <= delay_line(LAT-1);
end BEHAVIORAL;
|
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter2.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter2 IS
PORT
(
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END lpm_counter2;
ARCHITECTURE SYN OF lpm_counter2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(0 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 1
)
PORT MAP (
clock => clock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "1"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 1 0 @q 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter2.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1159.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s06b00x00p02n01i01159ent IS
END c06s06b00x00p02n01i01159ent;
ARCHITECTURE c06s06b00x00p02n01i01159arch OF c06s06b00x00p02n01i01159ent IS
BEGIN
TESTING: PROCESS
type arr is array(0 to 50) of boolean;
function ret_arr(I : integer) return arr is
variable RA : arr ;
begin
return RA;
end ret_arr;
variable k : integer := 0;
BEGIN
k := arr'low;
assert NOT( k=0 )
report "***PASSED TEST: c06s06b00x00p02n01i01159"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c06s06b00x00p02n01i01159 - The prefix of an attribute name may be a selected name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p02n01i01159arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1159.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s06b00x00p02n01i01159ent IS
END c06s06b00x00p02n01i01159ent;
ARCHITECTURE c06s06b00x00p02n01i01159arch OF c06s06b00x00p02n01i01159ent IS
BEGIN
TESTING: PROCESS
type arr is array(0 to 50) of boolean;
function ret_arr(I : integer) return arr is
variable RA : arr ;
begin
return RA;
end ret_arr;
variable k : integer := 0;
BEGIN
k := arr'low;
assert NOT( k=0 )
report "***PASSED TEST: c06s06b00x00p02n01i01159"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c06s06b00x00p02n01i01159 - The prefix of an attribute name may be a selected name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p02n01i01159arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1159.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s06b00x00p02n01i01159ent IS
END c06s06b00x00p02n01i01159ent;
ARCHITECTURE c06s06b00x00p02n01i01159arch OF c06s06b00x00p02n01i01159ent IS
BEGIN
TESTING: PROCESS
type arr is array(0 to 50) of boolean;
function ret_arr(I : integer) return arr is
variable RA : arr ;
begin
return RA;
end ret_arr;
variable k : integer := 0;
BEGIN
k := arr'low;
assert NOT( k=0 )
report "***PASSED TEST: c06s06b00x00p02n01i01159"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c06s06b00x00p02n01i01159 - The prefix of an attribute name may be a selected name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p02n01i01159arch;
|
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