content stringlengths 1 1.04M ⌀ |
|---|
library verilog;
use verilog.vl_types.all;
entity acb_96_bit is
generic(
ANALOG_QUAD_NUM : integer := 6;
ACB_BYTES_NUM_PER_QUAD: integer := 12;
WARNING_MSGS_ON : integer := 1
);
port(
ACB_RST : in vl_logic;
ACB_WEN : in vl_logic;
ACB_AD... |
library verilog;
use verilog.vl_types.all;
entity acb_96_bit is
generic(
ANALOG_QUAD_NUM : integer := 6;
ACB_BYTES_NUM_PER_QUAD: integer := 12;
WARNING_MSGS_ON : integer := 1
);
port(
ACB_RST : in vl_logic;
ACB_WEN : in vl_logic;
ACB_AD... |
library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
i : in bit;
o : out bit
);
end;
architecture a of ent is
signal test : std_logic_vector(7 downto 0);
alias a : std_logic_vector(7 downto 0) is test;
begin
process(i)
begin
if a = x"00" then
end if;
... |
entity test is
end test;
architecture only of test is
procedure proc (
constant a : in bit_vector;
constant l : in integer ) is
type dyn is range a'left downto 0;
begin
assert dyn'left = l report "TEST FAILED" severity FAILURE;
end proc;
begin -- only
doit: process
begin -- process doit
... |
entity test is
end test;
architecture only of test is
procedure proc (
constant a : in bit_vector;
constant l : in integer ) is
type dyn is range a'left downto 0;
begin
assert dyn'left = l report "TEST FAILED" severity FAILURE;
end proc;
begin -- only
doit: process
begin -- process doit
... |
entity test is
end test;
architecture only of test is
procedure proc (
constant a : in bit_vector;
constant l : in integer ) is
type dyn is range a'left downto 0;
begin
assert dyn'left = l report "TEST FAILED" severity FAILURE;
end proc;
begin -- only
doit: process
begin -- process doit
... |
----------------------------------------------------------------------------------
-- Company: Open Source
-- Engineer: Steven T. Seppala ( rad- )
--
-- Create Date: 01/26/2016 03:26:56 PM
-- Design Name:
-- Module Name: 65C816 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- ... |
----------------------------------------------------------------------------------
-- Company: Open Source
-- Engineer: Steven T. Seppala ( rad- )
--
-- Create Date: 01/26/2016 03:26:56 PM
-- Design Name:
-- Module Name: 65C816 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- ... |
----------------------------------------------------------------------------------
-- Company: Open Source
-- Engineer: Steven T. Seppala ( rad- )
--
-- Create Date: 01/26/2016 03:26:56 PM
-- Design Name:
-- Module Name: 65C816 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- ... |
-- rc filter test bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity rc_filt_tb is
end rc_filt_tb;
architecture behav of rc_filt_tb is
component rc_filt
generic (
time_const : positive;
iowidth : positive;
procwidth : positive;
pd_min : std_logic;
pd_m... |
entity Or2 is
port (x, y: in BIT; z: out BIT);
end entity Or2;
architecture gate1 of Or2 is
begin
z <= x or y;
end architecture gate1;
|
architecture RTL of FIFO is
begin
process
begin
for x in (0 to 30) loop
end loop;
loop
end loop;
-- Violations below
for x in (0 to 30)loop
end loop;
for x in (0 to 30) loop
end loop;
end process;
end;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
----------------------------------------------------------------------------------
-- Engineer: Noxet
--
-- Module Name: string_generator - Behavioral
-- Description:
-- A state machine to generate potential passwords
----------------------------------------------------------------------------------
library I... |
entity sub_ent is
end entity;
architecture a of sub_ent is
begin
end architecture a;
entity test is
end entity;
architecture test1 of test is
begin
entity work.sub_ent; -- unlabeled entity instantiation
end architecture;
architecture test2 of test is
begin
fg1: for ii in 0 to 0 generate
begin
end generate;
bloc... |
entity sub_ent is
end entity;
architecture a of sub_ent is
begin
end architecture a;
entity test is
end entity;
architecture test1 of test is
begin
entity work.sub_ent; -- unlabeled entity instantiation
end architecture;
architecture test2 of test is
begin
fg1: for ii in 0 to 0 generate
begin
end generate;
bloc... |
entity sub_ent is
end entity;
architecture a of sub_ent is
begin
end architecture a;
entity test is
end entity;
architecture test1 of test is
begin
entity work.sub_ent; -- unlabeled entity instantiation
end architecture;
architecture test2 of test is
begin
fg1: for ii in 0 to 0 generate
begin
end generate;
bloc... |
entity sub_ent is
end entity;
architecture a of sub_ent is
begin
end architecture a;
entity test is
end entity;
architecture test1 of test is
begin
entity work.sub_ent; -- unlabeled entity instantiation
end architecture;
architecture test2 of test is
begin
fg1: for ii in 0 to 0 generate
begin
end generate;
bloc... |
entity sub_ent is
end entity;
architecture a of sub_ent is
begin
end architecture a;
entity test is
end entity;
architecture test1 of test is
begin
entity work.sub_ent; -- unlabeled entity instantiation
end architecture;
architecture test2 of test is
begin
fg1: for ii in 0 to 0 generate
begin
end generate;
bloc... |
entity tb is
end tb;
architecture behav of tb is
signal s : bit;
begin
postponed assert s = '0' severity failure;
process
begin
s <= '1';
wait for 0 ns;
s <= '0';
wait;
end process;
end behav;
|
entity tb is
end tb;
architecture behav of tb is
signal s : bit;
begin
postponed assert s = '0' severity failure;
process
begin
s <= '1';
wait for 0 ns;
s <= '0';
wait;
end process;
end behav;
|
architecture RTL of FIFO is
begin
block_label : block is begin end block block_label;
BLOCK_LABEL : BLOCK is BEGIN END BLOCK BLOCK_LABEL;
end architecture RTL;
|
-- File name: key_scheduler.vhd
-- Created: 2009-03-30
-- Author: Matt Swanson
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: Rijndael KeyScheduler
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity key_scheduler is
... |
------------------------------------------------------------------------------
-- Title : Wishbone Position Calculation Core
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-07-02
-- Platform : F... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_183 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_183;
architecture augh of add_183 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_183 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_183;
architecture augh of add_183 is
signal carry_inA : std_l... |
-- NEED RESULT: ARCH00153.P1: Multi inertial transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00153.P2: Multi inertial transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00153.P3: Multi inertial transactions occurred on signal asg with sele... |
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Simple Wishbone UART
---------------------------------------------------------------------------------------
-- File : simple_uart_pkg.vhd
-- Author : auto-generated by w... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY spi_async IS
PORT ( SCLK : IN std_logic;
RESET : IN std_logic;
SDATA : IN std_logic;
CS : IN std_logic;
BYTE0, BYTE1 : OUT std_logic_vector(7 downto 0);
dig0, dig1, dig2, dig3 : OUT std_logic_vector(6 DOWNTO 0) -- show key p... |
-------------------------------------------------------------------------------
-- Entity : plb_powerlink
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted p... |
-------------------------------------------------------------------------------
-- Entity : plb_powerlink
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted p... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:27:29 11/20/2013
-- Design Name:
-- Module Name: Selector - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
library verilog;
use verilog.vl_types.all;
entity MEM_WR is
port(
clk : in vl_logic;
stall : in vl_logic;
flush : in vl_logic;
MemData_Mem : in vl_logic_vector(31 downto 0);
Rd_write_byte_en_Mem: in vl_logic_vector(3 dow... |
-- megafunction wizard: %LPM_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_add_sub
-- ============================================================
-- File Name: add.vhd
-- Megafunction Name(s):
-- lpm_add_sub
--
-- Simulation Library Files(s):
-- lpm
-- ======================================... |
--------------------------------------------------------------
------------------------------------------------------------
-- adder.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.... |
entity test is
end test;
architecture only of test is
signal s : bit := '0';
begin
p : process
begin
s <= '1';
wait for 0 fs;
assert s'last_value = '0' report "TEST FAILED" severity failure;
report "TEST PASSED";
wait;
end process;
end only;
|
entity test is
end test;
architecture only of test is
signal s : bit := '0';
begin
p : process
begin
s <= '1';
wait for 0 fs;
assert s'last_value = '0' report "TEST FAILED" severity failure;
report "TEST PASSED";
wait;
end process;
end only;
|
entity test is
end test;
architecture only of test is
signal s : bit := '0';
begin
p : process
begin
s <= '1';
wait for 0 fs;
assert s'last_value = '0' report "TEST FAILED" severity failure;
report "TEST PASSED";
wait;
end process;
end only;
|
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: RX channel
-- # FE-I4 Style Rx Channel; Sync, Align & Decode
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library decode... |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.10:15:30)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesahb_alap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 30);
output1, output2: OUT unsigned(0 TO 31));
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright... |
--------------------------------------------------------------------------------
-- Company: KTH
--
-- File: WOLF_CONTROLLER.vhd
-- File history:
-- v0.1: 2017-04-15: Initial verision for drop test only
--
-- Description:
-- Controller for the REXUS - WOLF exeriment. Handles the statemachine and status communica... |
-------------------------------------------------------------------------------
--
-- T420/421 controller toplevel without tri-states.
--
-- $Id: t420_notri-c.vhd,v 1.2 2006-06-05 20:03:11 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
--------------------------... |
library ieee;
use ieee.std_logic_1164.all;
entity test is
end entity test;
architecture atest of test is
-- signal s : bit;
signal t : bit;
begin
main1: process
begin
t <= '1';
t <= '0';
end process;
-- main2: process(s)
-- begin
-- t <= '0';
-- end process;
-- main2: process(s)
-- ... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY DataMemory_tb IS
END DataMemory_tb;
ARCHITECTURE behavior OF DataMemory_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT DataMemory
PORT(
Crd : IN std_logic_vector(31 downto 0);
Address : IN std... |
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Component Declaration
COMPONENT <component name>
PORT(
<port1> : IN std_logic;
... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Gaisler Ethernet core
constant CFG_GRETH2 : integer := CONFIG_GRETH2_ENABLE;
constant CFG_GRETH21G : integer := CONFIG_GRETH2_GIGA;
constant CFG_ETH2_FIFO : integer := CFG_GRETH2_FIFO;
|
-- Gaisler Ethernet core
constant CFG_GRETH2 : integer := CONFIG_GRETH2_ENABLE;
constant CFG_GRETH21G : integer := CONFIG_GRETH2_GIGA;
constant CFG_ETH2_FIFO : integer := CFG_GRETH2_FIFO;
|
-- Gaisler Ethernet core
constant CFG_GRETH2 : integer := CONFIG_GRETH2_ENABLE;
constant CFG_GRETH21G : integer := CONFIG_GRETH2_GIGA;
constant CFG_ETH2_FIFO : integer := CFG_GRETH2_FIFO;
|
-- Gaisler Ethernet core
constant CFG_GRETH2 : integer := CONFIG_GRETH2_ENABLE;
constant CFG_GRETH21G : integer := CONFIG_GRETH2_GIGA;
constant CFG_ETH2_FIFO : integer := CFG_GRETH2_FIFO;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY MUX_RFSOURCE_tb IS
END MUX_RFSOURCE_tb;
ARCHITECTURE behavior OF MUX_RFSOURCE_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MUX_RFSOURCE
PORT(
RFSOURCE : IN std_logic_vector(1 downto 0);
DATAT... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_k1_k2_e
--
-- Generated
-- by: wig
-- on: Wed Nov 30 09:22:45 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_... |
-------------------------------------------------------------------------------
-- Title : Hall Sensor Encoder Module
-- Project : Loa
-------------------------------------------------------------------------------
-- Platform : Spartan 3
-----------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- Title : Hall Sensor Encoder Module
-- Project : Loa
-------------------------------------------------------------------------------
-- Platform : Spartan 3
-----------------------------------------------------------------------... |
-- Btrace 448
-- Ray Generator - Test Bench
--
-- Bradley Boccuzzi
-- 2016
-- !Remove from project
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity raygen_TB is
end raygen_TB;
architecture arch of raygen_TB is
constant clkPd: time := 20 ns;
constant int, fraction: integer := 16;
... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: tcp_engine_tx_fifo - Behavioral
--
-- Description: A FIFO for the packet headers, before they have data added
--
---------------------------------------------------------... |
-------------------------------------------------------------------------------------
-- FILE NAME : fmc176_ctrl.vhd
--
-- AUTHOR : Peter Kortekaas
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - fmc176_ctrl
-- architecture - fmc176_ctrl_syn
--
-- LANGUAGE : VHDL
--
---------... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property... |
entity test is
type t is range 0 to 16#f.f2;
end;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_ab
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:27 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_MIXED -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!... |
----------------------------------------------------------------------------------
-- Company: ESA
-- Engineer: Felix Winterstein
--
-- Create Date: 06.04.2013 21:02:35
-- Design Name:
-- Module Name: dsp_round - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:... |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter2.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- =============================... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
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