content stringlengths 1 1.04M ⌀ |
|---|
---------------------------------------------------------------------
-- TITLE: Plasma CPU core
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_cpu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without w... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 00:41:34 2017
-- Host : GILAMONSTER running 64-bit major rel... |
library verilog;
use verilog.vl_types.all;
entity FSM_core is
port(
X : in vl_logic;
CLK : in vl_logic;
reset : in vl_logic;
stateout : out vl_logic_vector(3 downto 0);
Z : out vl_logic
);
end FSM_... |
library verilog;
use verilog.vl_types.all;
entity FSM_core is
port(
X : in vl_logic;
CLK : in vl_logic;
reset : in vl_logic;
stateout : out vl_logic_vector(3 downto 0);
Z : out vl_logic
);
end FSM_... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity projeto2 is
port (
a : in std_logic := '0';
b : in std_logic := '1';
c : in std_logic := '0';
s : out std_logic
);
end projeto2;
architecture Behavioral of projeto2 is
signal multiplex : std_logic;
signal out_multiplex : std_logic;
signal demultiplex : ... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity v_split3 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end v... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity v_split3 is
port (
clk : in std_logic;
ra0_data : out std_logic_vector(7 downto 0);
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic;
wa0_en : in std_logic;
ra0_addr : in std_logic
);
end v... |
library IEEE;
use IEEE.std_logic_1164.all;
package pkg2_lib1 is
component com1_pkg2_lib1 is
generic (
WITH_GENERIC: boolean:=TRUE
);
port (
data_i : in std_logic;
data_o : out std_logic
);
end component com1_pkg2_lib1;
end package pkg2_lib1;
|
-- Company: Team 5
-- Engineer:
-- -Timothy Doucette Jr
-- -Robert Mushrall III
-- -Christopher Parks
--
-- Create Date: 14:26:47 03/31/2016
-- Design Name:
-- Module Name: Instruction_Memory_TL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_t_e
--
-- Generated
-- by: wig
-- on: Thu Jan 19 07:52:39 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: ... |
-------------------------------------------------------------------------------
-- Title : A sample GPIO port with asynchronous clock (wbgen2 example)
-- Project :
-------------------------------------------------------------------------------
-- File : gpio_port_async.vhdl
-- Author : T.W.
-- Compan... |
entity sig2var is
end entity;
architecture test of sig2var is
function foo(signal x : bit_vector) return bit_vector is
variable v : bit_vector(1 to 8) := x;
begin
return v;
end function;
function bar(signal x : bit) return bit is
variable v : bit := x;
begin
return... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
use work.prio_pkg.all;
entity cocotb_prio2 is
port (
clk : in std_logic;
reset_n : in std_logic;
clk2 : in std_logic;
reset_n2 : in std_logic... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
use work.prio_pkg.all;
entity cocotb_prio2 is
port (
clk : in std_logic;
reset_n : in std_logic;
clk2 : in std_logic;
reset_n2 : in std_logic... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.component_pack.all;
entity allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.component_pack.all;
entity allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.component_pack.all;
entity allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:01:01 07/07/2015
-- Design Name:
-- Module Name: /home/pmorales/VHDL/OFDM/src/FULL_tb.vhd
-- Project Name: OFDM
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL ... |
-- Vhdl test bench created from schematic F:\Datos\workspace\Prueba\Esquematico.sch - Sun Aug 21 10:12:22 2011
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types alway... |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity RF is
Port ( rs1 : in STD_LOGIC_VECTOR... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_865 is
port (
ne : out std_logic;
in1 : in std_logic_vector(2 downto 0);
in0 : in std_logic_vector(2 downto 0)
);
end cmp_865;
architecture augh of cmp_865 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'... |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_865 is
port (
ne : out std_logic;
in1 : in std_logic_vector(2 downto 0);
in0 : in std_logic_vector(2 downto 0)
);
end cmp_865;
architecture augh of cmp_865 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity harris_slave is
port (
clk_proc : in std_logic;
reset_n : in std_logic;
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Fu Zuoyou.
--
-- Create Date: 20:30:32 11/30/2013
-- Design Name:
-- Module Name: flashio - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- -------------------------------------------------------------
--
-- Entity Declaration for vgca_mm
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id:... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY add_3bit_add_3bit_sch_tb IS
END add_3bit_add_3bit_sch_tb;
ARCHITECTURE behavioral OF add_3bit_add_3bit_sch_tb IS
COMPONENT add_3bit
PORT( A : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:54:00 10/26/2015
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
--------------------------------------------------------------------------
-- This file is part of Oggonachip project
-- http://oggonachip.sourceforge.net
---------------------------------------------------------------------------
-- Entities: mdct, mdctctrl
-- File: mdct.vhd
-- Author: Luis L. Azuara
--... |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-... |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-... |
entity counter_bot is
port (
clk : in bit;
count : out integer );
end entity;
architecture behav of counter_bot is
begin
process (clk) is
variable count_var : integer := 0;
begin
if clk'event and clk = '1' then
count_var := count_var + 1;
count <= ... |
entity counter_bot is
port (
clk : in bit;
count : out integer );
end entity;
architecture behav of counter_bot is
begin
process (clk) is
variable count_var : integer := 0;
begin
if clk'event and clk = '1' then
count_var := count_var + 1;
count <= ... |
entity counter_bot is
port (
clk : in bit;
count : out integer );
end entity;
architecture behav of counter_bot is
begin
process (clk) is
variable count_var : integer := 0;
begin
if clk'event and clk = '1' then
count_var := count_var + 1;
count <= ... |
entity counter_bot is
port (
clk : in bit;
count : out integer );
end entity;
architecture behav of counter_bot is
begin
process (clk) is
variable count_var : integer := 0;
begin
if clk'event and clk = '1' then
count_var := count_var + 1;
count <= ... |
entity counter_bot is
port (
clk : in bit;
count : out integer );
end entity;
architecture behav of counter_bot is
begin
process (clk) is
variable count_var : integer := 0;
begin
if clk'event and clk = '1' then
count_var := count_var + 1;
count <= ... |
-- niosii_system_jtag_uart_0_avalon_jtag_slave_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_jtag_uart_0_avalon_jtag_slave_translator is
generic (
AV_ADDRESS_W : integer ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.packetprocessordf_types.all;
entity packetprocessordf_cnt_j is
port(pts : in packetprocessordf_types.array_of_tup3(0 to 3);
pts_0 : in ... |
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.packetprocessordf_types.all;
entity packetprocessordf_cnt_j is
port(pts : in packetprocessordf_types.array_of_tup3(0 to 3);
pts_0 : in ... |
-------------------------------------------------------------------------------
-- Title : Captain Drive
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian.greif@rwth-aachen.de>
-- Company : Roboterclub Aachen e.V.
-- Platform : Spartan 3-400
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: clock3hz.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- =================================... |
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_sg_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ********************... |
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_sg_afifo_autord.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ********************... |
-- Gray_Binarization_GN.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.12.15:50:58
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Gray_Binarization_GN is
port (
Avalon_ST_Source_valid : out std_logic; -- Avalon_ST_Source_... |
-- Gray_Binarization_GN.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.12.15:50:58
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Gray_Binarization_GN is
port (
Avalon_ST_Source_valid : out std_logic; -- Avalon_ST_Source_... |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 ... |
architecture RTL of FIFO is
begin
PROCESS
begin
end process;
-- Violations below
PROCESS
begin
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
package fmc150_pkg is
--------------------------------------------------------------------
-- Type definition
--------------------------------------------------------------------
type cntvalueout_array is array(13 downto 0) of std_logic_vector(4 downto ... |
-- This unit is a DAemulator
-- The outout will be writen to a file
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use std.textio.all;
library simio;
use simio.SIMIO_PACKAGE.all;
entity DAemulator is
generic ( DA_FILE : string := "UNUSED";
DATA_WIDTH : integer := 6 );
po... |
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the ... |
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos (rodrigo4zevedo@gmail.com)
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity ErrorGuessing is
Port ( ... |
package ENV is
procedure STOP (STATUS : INTEGER);
procedure FINISH (STATUS : INTEGER);
function RESOLUTION_LIMIT return DELAY_LENGTH;
end package ENV;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
package body ENV is
procedure STOP (STATUS : INTEGER) is
begin
repor... |
package ENV is
procedure STOP (STATUS : INTEGER);
procedure FINISH (STATUS : INTEGER);
function RESOLUTION_LIMIT return DELAY_LENGTH;
end package ENV;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
package body ENV is
procedure STOP (STATUS : INTEGER) is
begin
repor... |
package ENV is
procedure STOP (STATUS : INTEGER);
procedure FINISH (STATUS : INTEGER);
function RESOLUTION_LIMIT return DELAY_LENGTH;
end package ENV;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
package body ENV is
procedure STOP (STATUS : INTEGER) is
begin
repor... |
entity VelikiDek2 is port (
a: in std_logic_vector(1 downto 0);
e: in std_logic;
i: out std_logic_vector(0 to 3));
end VelikiDek2;
architecture strukturna of VelikiDek2 is
signal ez1, ez2: std_logic;
begin
d0: entity work.MaliDek2 port map (a(1), e, ez1, ez2);
d1: entity work.MaliDek2 port map (a(0)... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Feb 08 00:47:16 2017
-- Host : GILAMONSTER running 64-bit major rel... |
ARCHITECTURE voltage_dependend OF current_source IS
QUANTITY v ACROSS i THROUGH lt TO rt;
BEGIN
i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE voltage_dependend;
|
ARCHITECTURE voltage_dependend OF current_source IS
QUANTITY v ACROSS i THROUGH lt TO rt;
BEGIN
i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE voltage_dependend;
|
ARCHITECTURE voltage_dependend OF current_source IS
QUANTITY v ACROSS i THROUGH lt TO rt;
BEGIN
i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE voltage_dependend;
|
ARCHITECTURE voltage_dependend OF current_source IS
QUANTITY v ACROSS i THROUGH lt TO rt;
BEGIN
i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE voltage_dependend;
|
ARCHITECTURE voltage_dependend OF current_source IS
QUANTITY v ACROSS i THROUGH lt TO rt;
BEGIN
i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE voltage_dependend;
|
ARCHITECTURE voltage_dependend OF current_source IS
QUANTITY v ACROSS i THROUGH lt TO rt;
BEGIN
i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE voltage_dependend;
|
ARCHITECTURE voltage_dependend OF current_source IS
QUANTITY v ACROSS i THROUGH lt TO rt;
BEGIN
i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE voltage_dependend;
|
ARCHITECTURE voltage_dependend OF current_source IS
QUANTITY v ACROSS i THROUGH lt TO rt;
BEGIN
i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE voltage_dependend;
|
ARCHITECTURE voltage_dependend OF current_source IS
QUANTITY v ACROSS i THROUGH lt TO rt;
BEGIN
i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE voltage_dependend;
|
ARCHITECTURE voltage_dependend OF current_source IS
QUANTITY v ACROSS i THROUGH lt TO rt;
BEGIN
i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE voltage_dependend;
|
ARCHITECTURE voltage_dependend OF current_source IS
QUANTITY v ACROSS i THROUGH lt TO rt;
BEGIN
i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE voltage_dependend;
|
ARCHITECTURE voltage_dependend OF current_source IS
QUANTITY v ACROSS i THROUGH lt TO rt;
BEGIN
i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE voltage_dependend;
|
ARCHITECTURE voltage_dependend OF current_source IS
QUANTITY v ACROSS i THROUGH lt TO rt;
BEGIN
i == ISS * (exp(v/(N * VT)) - 1.0);
END ARCHITECTURE voltage_dependend;
|
-------------------------------------------------------------------------------
-- filter.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
-------------------------------------------------------------------------------
-- filter.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY ... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
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