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-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:fifo_generator:12.0 -- IP Revision: 3 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY fifo_generator_v12_0; USE fifo_generator_v12_0.fifo_generator_v12_0; ENTITY DPBSCFIFO40x64WC IS PORT ( clk : IN STD_LOGIC; srst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(39 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(39 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) ); END DPBSCFIFO40x64WC; ARCHITECTURE DPBSCFIFO40x64WC_arch OF DPBSCFIFO40x64WC IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBSCFIFO40x64WC_arch: ARCHITECTURE IS "yes"; COMPONENT fifo_generator_v12_0 IS GENERIC ( C_COMMON_CLOCK : INTEGER; C_COUNT_TYPE : INTEGER; C_DATA_COUNT_WIDTH : INTEGER; C_DEFAULT_VALUE : STRING; C_DIN_WIDTH : INTEGER; C_DOUT_RST_VAL : STRING; C_DOUT_WIDTH : INTEGER; C_ENABLE_RLOCS : INTEGER; C_FAMILY : STRING; C_FULL_FLAGS_RST_VAL : INTEGER; C_HAS_ALMOST_EMPTY : INTEGER; C_HAS_ALMOST_FULL : INTEGER; C_HAS_BACKUP : INTEGER; C_HAS_DATA_COUNT : INTEGER; C_HAS_INT_CLK : INTEGER; C_HAS_MEMINIT_FILE : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_RD_DATA_COUNT : INTEGER; C_HAS_RD_RST : INTEGER; C_HAS_RST : INTEGER; C_HAS_SRST : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_VALID : INTEGER; C_HAS_WR_ACK : INTEGER; C_HAS_WR_DATA_COUNT : INTEGER; C_HAS_WR_RST : INTEGER; C_IMPLEMENTATION_TYPE : INTEGER; C_INIT_WR_PNTR_VAL : INTEGER; C_MEMORY_TYPE : INTEGER; C_MIF_FILE_NAME : STRING; C_OPTIMIZATION_MODE : INTEGER; C_OVERFLOW_LOW : INTEGER; C_PRELOAD_LATENCY : INTEGER; C_PRELOAD_REGS : INTEGER; C_PRIM_FIFO_TYPE : STRING; C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER; C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER; C_PROG_EMPTY_TYPE : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER; C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER; C_PROG_FULL_TYPE : INTEGER; C_RD_DATA_COUNT_WIDTH : INTEGER; C_RD_DEPTH : INTEGER; C_RD_FREQ : INTEGER; C_RD_PNTR_WIDTH : INTEGER; C_UNDERFLOW_LOW : INTEGER; C_USE_DOUT_RST : INTEGER; C_USE_ECC : INTEGER; C_USE_EMBEDDED_REG : INTEGER; C_USE_PIPELINE_REG : INTEGER; C_POWER_SAVING_MODE : INTEGER; C_USE_FIFO16_FLAGS : INTEGER; C_USE_FWFT_DATA_COUNT : INTEGER; C_VALID_LOW : INTEGER; C_WR_ACK_LOW : INTEGER; C_WR_DATA_COUNT_WIDTH : INTEGER; C_WR_DEPTH : INTEGER; C_WR_FREQ : INTEGER; C_WR_PNTR_WIDTH : INTEGER; C_WR_RESPONSE_LATENCY : INTEGER; C_MSGON_VAL : INTEGER; C_ENABLE_RST_SYNC : INTEGER; C_ERROR_INJECTION_TYPE : INTEGER; C_SYNCHRONIZER_STAGE : INTEGER; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_HAS_AXI_WR_CHANNEL : INTEGER; C_HAS_AXI_RD_CHANNEL : INTEGER; C_HAS_SLAVE_CE : INTEGER; C_HAS_MASTER_CE : INTEGER; C_ADD_NGC_CONSTRAINT : INTEGER; C_USE_COMMON_OVERFLOW : INTEGER; C_USE_COMMON_UNDERFLOW : INTEGER; C_USE_DEFAULT_SETTINGS : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_AXI_ADDR_WIDTH : INTEGER; C_AXI_DATA_WIDTH : INTEGER; C_AXI_LEN_WIDTH : INTEGER; C_AXI_LOCK_WIDTH : INTEGER; C_HAS_AXI_ID : INTEGER; C_HAS_AXI_AWUSER : INTEGER; C_HAS_AXI_WUSER : INTEGER; C_HAS_AXI_BUSER : INTEGER; C_HAS_AXI_ARUSER : INTEGER; C_HAS_AXI_RUSER : INTEGER; C_AXI_ARUSER_WIDTH : INTEGER; C_AXI_AWUSER_WIDTH : INTEGER; C_AXI_WUSER_WIDTH : INTEGER; C_AXI_BUSER_WIDTH : INTEGER; C_AXI_RUSER_WIDTH : INTEGER; C_HAS_AXIS_TDATA : INTEGER; C_HAS_AXIS_TID : INTEGER; C_HAS_AXIS_TDEST : INTEGER; C_HAS_AXIS_TUSER : INTEGER; C_HAS_AXIS_TREADY : INTEGER; C_HAS_AXIS_TLAST : INTEGER; C_HAS_AXIS_TSTRB : INTEGER; C_HAS_AXIS_TKEEP : INTEGER; C_AXIS_TDATA_WIDTH : INTEGER; C_AXIS_TID_WIDTH : INTEGER; C_AXIS_TDEST_WIDTH : INTEGER; C_AXIS_TUSER_WIDTH : INTEGER; C_AXIS_TSTRB_WIDTH : INTEGER; C_AXIS_TKEEP_WIDTH : INTEGER; C_WACH_TYPE : INTEGER; C_WDCH_TYPE : INTEGER; C_WRCH_TYPE : INTEGER; C_RACH_TYPE : INTEGER; C_RDCH_TYPE : INTEGER; C_AXIS_TYPE : INTEGER; C_IMPLEMENTATION_TYPE_WACH : INTEGER; C_IMPLEMENTATION_TYPE_WDCH : INTEGER; C_IMPLEMENTATION_TYPE_WRCH : INTEGER; C_IMPLEMENTATION_TYPE_RACH : INTEGER; C_IMPLEMENTATION_TYPE_RDCH : INTEGER; C_IMPLEMENTATION_TYPE_AXIS : INTEGER; C_APPLICATION_TYPE_WACH : INTEGER; C_APPLICATION_TYPE_WDCH : INTEGER; C_APPLICATION_TYPE_WRCH : INTEGER; C_APPLICATION_TYPE_RACH : INTEGER; C_APPLICATION_TYPE_RDCH : INTEGER; C_APPLICATION_TYPE_AXIS : INTEGER; C_PRIM_FIFO_TYPE_WACH : STRING; C_PRIM_FIFO_TYPE_WDCH : STRING; C_PRIM_FIFO_TYPE_WRCH : STRING; C_PRIM_FIFO_TYPE_RACH : STRING; C_PRIM_FIFO_TYPE_RDCH : STRING; C_PRIM_FIFO_TYPE_AXIS : STRING; C_USE_ECC_WACH : INTEGER; C_USE_ECC_WDCH : INTEGER; C_USE_ECC_WRCH : INTEGER; C_USE_ECC_RACH : INTEGER; C_USE_ECC_RDCH : INTEGER; C_USE_ECC_AXIS : INTEGER; C_ERROR_INJECTION_TYPE_WACH : INTEGER; C_ERROR_INJECTION_TYPE_WDCH : INTEGER; C_ERROR_INJECTION_TYPE_WRCH : INTEGER; C_ERROR_INJECTION_TYPE_RACH : INTEGER; C_ERROR_INJECTION_TYPE_RDCH : INTEGER; C_ERROR_INJECTION_TYPE_AXIS : INTEGER; C_DIN_WIDTH_WACH : INTEGER; C_DIN_WIDTH_WDCH : INTEGER; C_DIN_WIDTH_WRCH : INTEGER; C_DIN_WIDTH_RACH : INTEGER; C_DIN_WIDTH_RDCH : INTEGER; C_DIN_WIDTH_AXIS : INTEGER; C_WR_DEPTH_WACH : INTEGER; C_WR_DEPTH_WDCH : INTEGER; C_WR_DEPTH_WRCH : INTEGER; C_WR_DEPTH_RACH : INTEGER; C_WR_DEPTH_RDCH : INTEGER; C_WR_DEPTH_AXIS : INTEGER; C_WR_PNTR_WIDTH_WACH : INTEGER; C_WR_PNTR_WIDTH_WDCH : INTEGER; C_WR_PNTR_WIDTH_WRCH : INTEGER; C_WR_PNTR_WIDTH_RACH : INTEGER; C_WR_PNTR_WIDTH_RDCH : INTEGER; C_WR_PNTR_WIDTH_AXIS : INTEGER; C_HAS_DATA_COUNTS_WACH : INTEGER; C_HAS_DATA_COUNTS_WDCH : INTEGER; C_HAS_DATA_COUNTS_WRCH : INTEGER; C_HAS_DATA_COUNTS_RACH : INTEGER; C_HAS_DATA_COUNTS_RDCH : INTEGER; C_HAS_DATA_COUNTS_AXIS : INTEGER; C_HAS_PROG_FLAGS_WACH : INTEGER; C_HAS_PROG_FLAGS_WDCH : INTEGER; C_HAS_PROG_FLAGS_WRCH : INTEGER; C_HAS_PROG_FLAGS_RACH : INTEGER; C_HAS_PROG_FLAGS_RDCH : INTEGER; C_HAS_PROG_FLAGS_AXIS : INTEGER; C_PROG_FULL_TYPE_WACH : INTEGER; C_PROG_FULL_TYPE_WDCH : INTEGER; C_PROG_FULL_TYPE_WRCH : INTEGER; C_PROG_FULL_TYPE_RACH : INTEGER; C_PROG_FULL_TYPE_RDCH : INTEGER; C_PROG_FULL_TYPE_AXIS : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER; C_PROG_EMPTY_TYPE_WACH : INTEGER; C_PROG_EMPTY_TYPE_WDCH : INTEGER; C_PROG_EMPTY_TYPE_WRCH : INTEGER; C_PROG_EMPTY_TYPE_RACH : INTEGER; C_PROG_EMPTY_TYPE_RDCH : INTEGER; C_PROG_EMPTY_TYPE_AXIS : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER; C_REG_SLICE_MODE_WACH : INTEGER; C_REG_SLICE_MODE_WDCH : INTEGER; C_REG_SLICE_MODE_WRCH : INTEGER; C_REG_SLICE_MODE_RACH : INTEGER; C_REG_SLICE_MODE_RDCH : INTEGER; C_REG_SLICE_MODE_AXIS : INTEGER ); PORT ( backup : IN STD_LOGIC; backup_marker : IN STD_LOGIC; clk : IN STD_LOGIC; rst : IN STD_LOGIC; srst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; wr_rst : IN STD_LOGIC; rd_clk : IN STD_LOGIC; rd_rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(39 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); int_clk : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; injectsbiterr : IN STD_LOGIC; sleep : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(39 DOWNTO 0); full : OUT STD_LOGIC; almost_full : OUT STD_LOGIC; wr_ack : OUT STD_LOGIC; overflow : OUT STD_LOGIC; empty : OUT STD_LOGIC; almost_empty : OUT STD_LOGIC; valid : OUT STD_LOGIC; underflow : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; wr_rst_busy : OUT STD_LOGIC; rd_rst_busy : OUT STD_LOGIC; m_aclk : IN STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; m_aclk_en : IN STD_LOGIC; s_aclk_en : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awvalid : OUT STD_LOGIC; m_axi_awready : IN STD_LOGIC; m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_wlast : OUT STD_LOGIC; m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wvalid : OUT STD_LOGIC; m_axi_wready : IN STD_LOGIC; m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bvalid : IN STD_LOGIC; m_axi_bready : OUT STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arvalid : OUT STD_LOGIC; m_axi_arready : IN STD_LOGIC; m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_rlast : IN STD_LOGIC; m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rvalid : IN STD_LOGIC; m_axi_rready : OUT STD_LOGIC; s_axis_tvalid : IN STD_LOGIC; s_axis_tready : OUT STD_LOGIC; s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tlast : IN STD_LOGIC; s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_tvalid : OUT STD_LOGIC; m_axis_tready : IN STD_LOGIC; m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tlast : OUT STD_LOGIC; m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_injectsbiterr : IN STD_LOGIC; axi_aw_injectdbiterr : IN STD_LOGIC; axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_sbiterr : OUT STD_LOGIC; axi_aw_dbiterr : OUT STD_LOGIC; axi_aw_overflow : OUT STD_LOGIC; axi_aw_underflow : OUT STD_LOGIC; axi_aw_prog_full : OUT STD_LOGIC; axi_aw_prog_empty : OUT STD_LOGIC; axi_w_injectsbiterr : IN STD_LOGIC; axi_w_injectdbiterr : IN STD_LOGIC; axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_sbiterr : OUT STD_LOGIC; axi_w_dbiterr : OUT STD_LOGIC; axi_w_overflow : OUT STD_LOGIC; axi_w_underflow : OUT STD_LOGIC; axi_w_prog_full : OUT STD_LOGIC; axi_w_prog_empty : OUT STD_LOGIC; axi_b_injectsbiterr : IN STD_LOGIC; axi_b_injectdbiterr : IN STD_LOGIC; axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_sbiterr : OUT STD_LOGIC; axi_b_dbiterr : OUT STD_LOGIC; axi_b_overflow : OUT STD_LOGIC; axi_b_underflow : OUT STD_LOGIC; axi_b_prog_full : OUT STD_LOGIC; axi_b_prog_empty : OUT STD_LOGIC; axi_ar_injectsbiterr : IN STD_LOGIC; axi_ar_injectdbiterr : IN STD_LOGIC; axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_sbiterr : OUT STD_LOGIC; axi_ar_dbiterr : OUT STD_LOGIC; axi_ar_overflow : OUT STD_LOGIC; axi_ar_underflow : OUT STD_LOGIC; axi_ar_prog_full : OUT STD_LOGIC; axi_ar_prog_empty : OUT STD_LOGIC; axi_r_injectsbiterr : IN STD_LOGIC; axi_r_injectdbiterr : IN STD_LOGIC; axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_sbiterr : OUT STD_LOGIC; axi_r_dbiterr : OUT STD_LOGIC; axi_r_overflow : OUT STD_LOGIC; axi_r_underflow : OUT STD_LOGIC; axi_r_prog_full : OUT STD_LOGIC; axi_r_prog_empty : OUT STD_LOGIC; axis_injectsbiterr : IN STD_LOGIC; axis_injectdbiterr : IN STD_LOGIC; axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_sbiterr : OUT STD_LOGIC; axis_dbiterr : OUT STD_LOGIC; axis_overflow : OUT STD_LOGIC; axis_underflow : OUT STD_LOGIC; axis_prog_full : OUT STD_LOGIC; axis_prog_empty : OUT STD_LOGIC ); END COMPONENT fifo_generator_v12_0; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF DPBSCFIFO40x64WC_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.4.1"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF DPBSCFIFO40x64WC_arch : ARCHITECTURE IS "DPBSCFIFO40x64WC,fifo_generator_v12_0,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF DPBSCFIFO40x64WC_arch: ARCHITECTURE IS "DPBSCFIFO40x64WC,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=40,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=40,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=1,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=62,C_PROG_FULL_THRESH_NEGATE_VAL=61,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=64,C_RD_FREQ=1,C_RD_PNTR_WIDTH=6,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=64,C_WR_FREQ=1,C_WR_PNTR_WIDTH=6,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA"; ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN"; ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN"; ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA"; ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL"; ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY"; BEGIN U0 : fifo_generator_v12_0 GENERIC MAP ( C_COMMON_CLOCK => 1, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => 6, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => 40, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => 40, C_ENABLE_RLOCS => 0, C_FAMILY => "zynq", C_FULL_FLAGS_RST_VAL => 0, C_HAS_ALMOST_EMPTY => 0, C_HAS_ALMOST_FULL => 0, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => 1, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => 0, C_HAS_RD_DATA_COUNT => 0, C_HAS_RD_RST => 0, C_HAS_RST => 0, C_HAS_SRST => 1, C_HAS_UNDERFLOW => 0, C_HAS_VALID => 0, C_HAS_WR_ACK => 0, C_HAS_WR_DATA_COUNT => 0, C_HAS_WR_RST => 0, C_IMPLEMENTATION_TYPE => 0, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => 1, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => 0, C_PRELOAD_LATENCY => 1, C_PRELOAD_REGS => 0, C_PRIM_FIFO_TYPE => "512x72", C_PROG_EMPTY_THRESH_ASSERT_VAL => 2, C_PROG_EMPTY_THRESH_NEGATE_VAL => 3, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => 62, C_PROG_FULL_THRESH_NEGATE_VAL => 61, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => 6, C_RD_DEPTH => 64, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => 6, C_UNDERFLOW_LOW => 0, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => 0, C_USE_PIPELINE_REG => 0, C_POWER_SAVING_MODE => 0, C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => 0, C_WR_DATA_COUNT_WIDTH => 6, C_WR_DEPTH => 64, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => 6, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => 2, C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_HAS_AXI_WR_CHANNEL => 1, C_HAS_AXI_RD_CHANNEL => 1, C_HAS_SLAVE_CE => 0, C_HAS_MASTER_CE => 0, C_ADD_NGC_CONSTRAINT => 0, C_USE_COMMON_OVERFLOW => 0, C_USE_COMMON_UNDERFLOW => 0, C_USE_DEFAULT_SETTINGS => 0, C_AXI_ID_WIDTH => 1, C_AXI_ADDR_WIDTH => 32, C_AXI_DATA_WIDTH => 64, C_AXI_LEN_WIDTH => 8, C_AXI_LOCK_WIDTH => 1, C_HAS_AXI_ID => 0, C_HAS_AXI_AWUSER => 0, C_HAS_AXI_WUSER => 0, C_HAS_AXI_BUSER => 0, C_HAS_AXI_ARUSER => 0, C_HAS_AXI_RUSER => 0, C_AXI_ARUSER_WIDTH => 1, C_AXI_AWUSER_WIDTH => 1, C_AXI_WUSER_WIDTH => 1, C_AXI_BUSER_WIDTH => 1, C_AXI_RUSER_WIDTH => 1, C_HAS_AXIS_TDATA => 1, C_HAS_AXIS_TID => 0, C_HAS_AXIS_TDEST => 0, C_HAS_AXIS_TUSER => 1, C_HAS_AXIS_TREADY => 1, C_HAS_AXIS_TLAST => 0, C_HAS_AXIS_TSTRB => 0, C_HAS_AXIS_TKEEP => 0, C_AXIS_TDATA_WIDTH => 8, C_AXIS_TID_WIDTH => 1, C_AXIS_TDEST_WIDTH => 1, C_AXIS_TUSER_WIDTH => 4, C_AXIS_TSTRB_WIDTH => 1, C_AXIS_TKEEP_WIDTH => 1, C_WACH_TYPE => 0, C_WDCH_TYPE => 0, C_WRCH_TYPE => 0, C_RACH_TYPE => 0, C_RDCH_TYPE => 0, C_AXIS_TYPE => 0, C_IMPLEMENTATION_TYPE_WACH => 1, C_IMPLEMENTATION_TYPE_WDCH => 1, C_IMPLEMENTATION_TYPE_WRCH => 1, C_IMPLEMENTATION_TYPE_RACH => 1, C_IMPLEMENTATION_TYPE_RDCH => 1, C_IMPLEMENTATION_TYPE_AXIS => 1, C_APPLICATION_TYPE_WACH => 0, C_APPLICATION_TYPE_WDCH => 0, C_APPLICATION_TYPE_WRCH => 0, C_APPLICATION_TYPE_RACH => 0, C_APPLICATION_TYPE_RDCH => 0, C_APPLICATION_TYPE_AXIS => 0, C_PRIM_FIFO_TYPE_WACH => "512x36", C_PRIM_FIFO_TYPE_WDCH => "1kx36", C_PRIM_FIFO_TYPE_WRCH => "512x36", C_PRIM_FIFO_TYPE_RACH => "512x36", C_PRIM_FIFO_TYPE_RDCH => "1kx36", C_PRIM_FIFO_TYPE_AXIS => "1kx18", C_USE_ECC_WACH => 0, C_USE_ECC_WDCH => 0, C_USE_ECC_WRCH => 0, C_USE_ECC_RACH => 0, C_USE_ECC_RDCH => 0, C_USE_ECC_AXIS => 0, C_ERROR_INJECTION_TYPE_WACH => 0, C_ERROR_INJECTION_TYPE_WDCH => 0, C_ERROR_INJECTION_TYPE_WRCH => 0, C_ERROR_INJECTION_TYPE_RACH => 0, C_ERROR_INJECTION_TYPE_RDCH => 0, C_ERROR_INJECTION_TYPE_AXIS => 0, C_DIN_WIDTH_WACH => 32, C_DIN_WIDTH_WDCH => 64, C_DIN_WIDTH_WRCH => 2, C_DIN_WIDTH_RACH => 32, C_DIN_WIDTH_RDCH => 64, C_DIN_WIDTH_AXIS => 1, C_WR_DEPTH_WACH => 16, C_WR_DEPTH_WDCH => 1024, C_WR_DEPTH_WRCH => 16, C_WR_DEPTH_RACH => 16, C_WR_DEPTH_RDCH => 1024, C_WR_DEPTH_AXIS => 1024, C_WR_PNTR_WIDTH_WACH => 4, C_WR_PNTR_WIDTH_WDCH => 10, C_WR_PNTR_WIDTH_WRCH => 4, C_WR_PNTR_WIDTH_RACH => 4, C_WR_PNTR_WIDTH_RDCH => 10, C_WR_PNTR_WIDTH_AXIS => 10, C_HAS_DATA_COUNTS_WACH => 0, C_HAS_DATA_COUNTS_WDCH => 0, C_HAS_DATA_COUNTS_WRCH => 0, C_HAS_DATA_COUNTS_RACH => 0, C_HAS_DATA_COUNTS_RDCH => 0, C_HAS_DATA_COUNTS_AXIS => 0, C_HAS_PROG_FLAGS_WACH => 0, C_HAS_PROG_FLAGS_WDCH => 0, C_HAS_PROG_FLAGS_WRCH => 0, C_HAS_PROG_FLAGS_RACH => 0, C_HAS_PROG_FLAGS_RDCH => 0, C_HAS_PROG_FLAGS_AXIS => 0, C_PROG_FULL_TYPE_WACH => 0, C_PROG_FULL_TYPE_WDCH => 0, C_PROG_FULL_TYPE_WRCH => 0, C_PROG_FULL_TYPE_RACH => 0, C_PROG_FULL_TYPE_RDCH => 0, C_PROG_FULL_TYPE_AXIS => 0, C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, C_PROG_EMPTY_TYPE_WACH => 0, C_PROG_EMPTY_TYPE_WDCH => 0, C_PROG_EMPTY_TYPE_WRCH => 0, C_PROG_EMPTY_TYPE_RACH => 0, C_PROG_EMPTY_TYPE_RDCH => 0, C_PROG_EMPTY_TYPE_AXIS => 0, C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, C_REG_SLICE_MODE_WACH => 0, C_REG_SLICE_MODE_WDCH => 0, C_REG_SLICE_MODE_WRCH => 0, C_REG_SLICE_MODE_RACH => 0, C_REG_SLICE_MODE_RDCH => 0, C_REG_SLICE_MODE_AXIS => 0 ) PORT MAP ( backup => '0', backup_marker => '0', clk => clk, rst => '0', srst => srst, wr_clk => '0', wr_rst => '0', rd_clk => '0', rd_rst => '0', din => din, wr_en => wr_en, rd_en => rd_en, prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), int_clk => '0', injectdbiterr => '0', injectsbiterr => '0', sleep => '0', dout => dout, full => full, empty => empty, data_count => data_count, m_aclk => '0', s_aclk => '0', s_aresetn => '0', m_aclk_en => '0', s_aclk_en => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awvalid => '0', s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wlast => '0', s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wvalid => '0', s_axi_bready => '0', m_axi_awready => '0', m_axi_wready => '0', m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bvalid => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arvalid => '0', s_axi_rready => '0', m_axi_arready => '0', m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_rlast => '0', m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rvalid => '0', s_axis_tvalid => '0', s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tlast => '0', s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), m_axis_tready => '0', axi_aw_injectsbiterr => '0', axi_aw_injectdbiterr => '0', axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_w_injectsbiterr => '0', axi_w_injectdbiterr => '0', axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_b_injectsbiterr => '0', axi_b_injectdbiterr => '0', axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_injectsbiterr => '0', axi_ar_injectdbiterr => '0', axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_r_injectsbiterr => '0', axi_r_injectdbiterr => '0', axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_injectsbiterr => '0', axis_injectdbiterr => '0', axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)) ); END DPBSCFIFO40x64WC_arch;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:fifo_generator:12.0 -- IP Revision: 3 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY fifo_generator_v12_0; USE fifo_generator_v12_0.fifo_generator_v12_0; ENTITY DPBSCFIFO40x64WC IS PORT ( clk : IN STD_LOGIC; srst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(39 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(39 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) ); END DPBSCFIFO40x64WC; ARCHITECTURE DPBSCFIFO40x64WC_arch OF DPBSCFIFO40x64WC IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBSCFIFO40x64WC_arch: ARCHITECTURE IS "yes"; COMPONENT fifo_generator_v12_0 IS GENERIC ( C_COMMON_CLOCK : INTEGER; C_COUNT_TYPE : INTEGER; C_DATA_COUNT_WIDTH : INTEGER; C_DEFAULT_VALUE : STRING; C_DIN_WIDTH : INTEGER; C_DOUT_RST_VAL : STRING; C_DOUT_WIDTH : INTEGER; C_ENABLE_RLOCS : INTEGER; C_FAMILY : STRING; C_FULL_FLAGS_RST_VAL : INTEGER; C_HAS_ALMOST_EMPTY : INTEGER; C_HAS_ALMOST_FULL : INTEGER; C_HAS_BACKUP : INTEGER; C_HAS_DATA_COUNT : INTEGER; C_HAS_INT_CLK : INTEGER; C_HAS_MEMINIT_FILE : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_RD_DATA_COUNT : INTEGER; C_HAS_RD_RST : INTEGER; C_HAS_RST : INTEGER; C_HAS_SRST : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_VALID : INTEGER; C_HAS_WR_ACK : INTEGER; C_HAS_WR_DATA_COUNT : INTEGER; C_HAS_WR_RST : INTEGER; C_IMPLEMENTATION_TYPE : INTEGER; C_INIT_WR_PNTR_VAL : INTEGER; C_MEMORY_TYPE : INTEGER; C_MIF_FILE_NAME : STRING; C_OPTIMIZATION_MODE : INTEGER; C_OVERFLOW_LOW : INTEGER; C_PRELOAD_LATENCY : INTEGER; C_PRELOAD_REGS : INTEGER; C_PRIM_FIFO_TYPE : STRING; C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER; C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER; C_PROG_EMPTY_TYPE : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER; C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER; C_PROG_FULL_TYPE : INTEGER; C_RD_DATA_COUNT_WIDTH : INTEGER; C_RD_DEPTH : INTEGER; C_RD_FREQ : INTEGER; C_RD_PNTR_WIDTH : INTEGER; C_UNDERFLOW_LOW : INTEGER; C_USE_DOUT_RST : INTEGER; C_USE_ECC : INTEGER; C_USE_EMBEDDED_REG : INTEGER; C_USE_PIPELINE_REG : INTEGER; C_POWER_SAVING_MODE : INTEGER; C_USE_FIFO16_FLAGS : INTEGER; C_USE_FWFT_DATA_COUNT : INTEGER; C_VALID_LOW : INTEGER; C_WR_ACK_LOW : INTEGER; C_WR_DATA_COUNT_WIDTH : INTEGER; C_WR_DEPTH : INTEGER; C_WR_FREQ : INTEGER; C_WR_PNTR_WIDTH : INTEGER; C_WR_RESPONSE_LATENCY : INTEGER; C_MSGON_VAL : INTEGER; C_ENABLE_RST_SYNC : INTEGER; C_ERROR_INJECTION_TYPE : INTEGER; C_SYNCHRONIZER_STAGE : INTEGER; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_HAS_AXI_WR_CHANNEL : INTEGER; C_HAS_AXI_RD_CHANNEL : INTEGER; C_HAS_SLAVE_CE : INTEGER; C_HAS_MASTER_CE : INTEGER; C_ADD_NGC_CONSTRAINT : INTEGER; C_USE_COMMON_OVERFLOW : INTEGER; C_USE_COMMON_UNDERFLOW : INTEGER; C_USE_DEFAULT_SETTINGS : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_AXI_ADDR_WIDTH : INTEGER; C_AXI_DATA_WIDTH : INTEGER; C_AXI_LEN_WIDTH : INTEGER; C_AXI_LOCK_WIDTH : INTEGER; C_HAS_AXI_ID : INTEGER; C_HAS_AXI_AWUSER : INTEGER; C_HAS_AXI_WUSER : INTEGER; C_HAS_AXI_BUSER : INTEGER; C_HAS_AXI_ARUSER : INTEGER; C_HAS_AXI_RUSER : INTEGER; C_AXI_ARUSER_WIDTH : INTEGER; C_AXI_AWUSER_WIDTH : INTEGER; C_AXI_WUSER_WIDTH : INTEGER; C_AXI_BUSER_WIDTH : INTEGER; C_AXI_RUSER_WIDTH : INTEGER; C_HAS_AXIS_TDATA : INTEGER; C_HAS_AXIS_TID : INTEGER; C_HAS_AXIS_TDEST : INTEGER; C_HAS_AXIS_TUSER : INTEGER; C_HAS_AXIS_TREADY : INTEGER; C_HAS_AXIS_TLAST : INTEGER; C_HAS_AXIS_TSTRB : INTEGER; C_HAS_AXIS_TKEEP : INTEGER; C_AXIS_TDATA_WIDTH : INTEGER; C_AXIS_TID_WIDTH : INTEGER; C_AXIS_TDEST_WIDTH : INTEGER; C_AXIS_TUSER_WIDTH : INTEGER; C_AXIS_TSTRB_WIDTH : INTEGER; C_AXIS_TKEEP_WIDTH : INTEGER; C_WACH_TYPE : INTEGER; C_WDCH_TYPE : INTEGER; C_WRCH_TYPE : INTEGER; C_RACH_TYPE : INTEGER; C_RDCH_TYPE : INTEGER; C_AXIS_TYPE : INTEGER; C_IMPLEMENTATION_TYPE_WACH : INTEGER; C_IMPLEMENTATION_TYPE_WDCH : INTEGER; C_IMPLEMENTATION_TYPE_WRCH : INTEGER; C_IMPLEMENTATION_TYPE_RACH : INTEGER; C_IMPLEMENTATION_TYPE_RDCH : INTEGER; C_IMPLEMENTATION_TYPE_AXIS : INTEGER; C_APPLICATION_TYPE_WACH : INTEGER; C_APPLICATION_TYPE_WDCH : INTEGER; C_APPLICATION_TYPE_WRCH : INTEGER; C_APPLICATION_TYPE_RACH : INTEGER; C_APPLICATION_TYPE_RDCH : INTEGER; C_APPLICATION_TYPE_AXIS : INTEGER; C_PRIM_FIFO_TYPE_WACH : STRING; C_PRIM_FIFO_TYPE_WDCH : STRING; C_PRIM_FIFO_TYPE_WRCH : STRING; C_PRIM_FIFO_TYPE_RACH : STRING; C_PRIM_FIFO_TYPE_RDCH : STRING; C_PRIM_FIFO_TYPE_AXIS : STRING; C_USE_ECC_WACH : INTEGER; C_USE_ECC_WDCH : INTEGER; C_USE_ECC_WRCH : INTEGER; C_USE_ECC_RACH : INTEGER; C_USE_ECC_RDCH : INTEGER; C_USE_ECC_AXIS : INTEGER; C_ERROR_INJECTION_TYPE_WACH : INTEGER; C_ERROR_INJECTION_TYPE_WDCH : INTEGER; C_ERROR_INJECTION_TYPE_WRCH : INTEGER; C_ERROR_INJECTION_TYPE_RACH : INTEGER; C_ERROR_INJECTION_TYPE_RDCH : INTEGER; C_ERROR_INJECTION_TYPE_AXIS : INTEGER; C_DIN_WIDTH_WACH : INTEGER; C_DIN_WIDTH_WDCH : INTEGER; C_DIN_WIDTH_WRCH : INTEGER; C_DIN_WIDTH_RACH : INTEGER; C_DIN_WIDTH_RDCH : INTEGER; C_DIN_WIDTH_AXIS : INTEGER; C_WR_DEPTH_WACH : INTEGER; C_WR_DEPTH_WDCH : INTEGER; C_WR_DEPTH_WRCH : INTEGER; C_WR_DEPTH_RACH : INTEGER; C_WR_DEPTH_RDCH : INTEGER; C_WR_DEPTH_AXIS : INTEGER; C_WR_PNTR_WIDTH_WACH : INTEGER; C_WR_PNTR_WIDTH_WDCH : INTEGER; C_WR_PNTR_WIDTH_WRCH : INTEGER; C_WR_PNTR_WIDTH_RACH : INTEGER; C_WR_PNTR_WIDTH_RDCH : INTEGER; C_WR_PNTR_WIDTH_AXIS : INTEGER; C_HAS_DATA_COUNTS_WACH : INTEGER; C_HAS_DATA_COUNTS_WDCH : INTEGER; C_HAS_DATA_COUNTS_WRCH : INTEGER; C_HAS_DATA_COUNTS_RACH : INTEGER; C_HAS_DATA_COUNTS_RDCH : INTEGER; C_HAS_DATA_COUNTS_AXIS : INTEGER; C_HAS_PROG_FLAGS_WACH : INTEGER; C_HAS_PROG_FLAGS_WDCH : INTEGER; C_HAS_PROG_FLAGS_WRCH : INTEGER; C_HAS_PROG_FLAGS_RACH : INTEGER; C_HAS_PROG_FLAGS_RDCH : INTEGER; C_HAS_PROG_FLAGS_AXIS : INTEGER; C_PROG_FULL_TYPE_WACH : INTEGER; C_PROG_FULL_TYPE_WDCH : INTEGER; C_PROG_FULL_TYPE_WRCH : INTEGER; C_PROG_FULL_TYPE_RACH : INTEGER; C_PROG_FULL_TYPE_RDCH : INTEGER; C_PROG_FULL_TYPE_AXIS : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER; C_PROG_EMPTY_TYPE_WACH : INTEGER; C_PROG_EMPTY_TYPE_WDCH : INTEGER; C_PROG_EMPTY_TYPE_WRCH : INTEGER; C_PROG_EMPTY_TYPE_RACH : INTEGER; C_PROG_EMPTY_TYPE_RDCH : INTEGER; C_PROG_EMPTY_TYPE_AXIS : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER; C_REG_SLICE_MODE_WACH : INTEGER; C_REG_SLICE_MODE_WDCH : INTEGER; C_REG_SLICE_MODE_WRCH : INTEGER; C_REG_SLICE_MODE_RACH : INTEGER; C_REG_SLICE_MODE_RDCH : INTEGER; C_REG_SLICE_MODE_AXIS : INTEGER ); PORT ( backup : IN STD_LOGIC; backup_marker : IN STD_LOGIC; clk : IN STD_LOGIC; rst : IN STD_LOGIC; srst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; wr_rst : IN STD_LOGIC; rd_clk : IN STD_LOGIC; rd_rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(39 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); int_clk : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; injectsbiterr : IN STD_LOGIC; sleep : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(39 DOWNTO 0); full : OUT STD_LOGIC; almost_full : OUT STD_LOGIC; wr_ack : OUT STD_LOGIC; overflow : OUT STD_LOGIC; empty : OUT STD_LOGIC; almost_empty : OUT STD_LOGIC; valid : OUT STD_LOGIC; underflow : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; wr_rst_busy : OUT STD_LOGIC; rd_rst_busy : OUT STD_LOGIC; m_aclk : IN STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; m_aclk_en : IN STD_LOGIC; s_aclk_en : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awvalid : OUT STD_LOGIC; m_axi_awready : IN STD_LOGIC; m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_wlast : OUT STD_LOGIC; m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wvalid : OUT STD_LOGIC; m_axi_wready : IN STD_LOGIC; m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bvalid : IN STD_LOGIC; m_axi_bready : OUT STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arvalid : OUT STD_LOGIC; m_axi_arready : IN STD_LOGIC; m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_rlast : IN STD_LOGIC; m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rvalid : IN STD_LOGIC; m_axi_rready : OUT STD_LOGIC; s_axis_tvalid : IN STD_LOGIC; s_axis_tready : OUT STD_LOGIC; s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tlast : IN STD_LOGIC; s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_tvalid : OUT STD_LOGIC; m_axis_tready : IN STD_LOGIC; m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tlast : OUT STD_LOGIC; m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_injectsbiterr : IN STD_LOGIC; axi_aw_injectdbiterr : IN STD_LOGIC; axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_sbiterr : OUT STD_LOGIC; axi_aw_dbiterr : OUT STD_LOGIC; axi_aw_overflow : OUT STD_LOGIC; axi_aw_underflow : OUT STD_LOGIC; axi_aw_prog_full : OUT STD_LOGIC; axi_aw_prog_empty : OUT STD_LOGIC; axi_w_injectsbiterr : IN STD_LOGIC; axi_w_injectdbiterr : IN STD_LOGIC; axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_sbiterr : OUT STD_LOGIC; axi_w_dbiterr : OUT STD_LOGIC; axi_w_overflow : OUT STD_LOGIC; axi_w_underflow : OUT STD_LOGIC; axi_w_prog_full : OUT STD_LOGIC; axi_w_prog_empty : OUT STD_LOGIC; axi_b_injectsbiterr : IN STD_LOGIC; axi_b_injectdbiterr : IN STD_LOGIC; axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_sbiterr : OUT STD_LOGIC; axi_b_dbiterr : OUT STD_LOGIC; axi_b_overflow : OUT STD_LOGIC; axi_b_underflow : OUT STD_LOGIC; axi_b_prog_full : OUT STD_LOGIC; axi_b_prog_empty : OUT STD_LOGIC; axi_ar_injectsbiterr : IN STD_LOGIC; axi_ar_injectdbiterr : IN STD_LOGIC; axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_sbiterr : OUT STD_LOGIC; axi_ar_dbiterr : OUT STD_LOGIC; axi_ar_overflow : OUT STD_LOGIC; axi_ar_underflow : OUT STD_LOGIC; axi_ar_prog_full : OUT STD_LOGIC; axi_ar_prog_empty : OUT STD_LOGIC; axi_r_injectsbiterr : IN STD_LOGIC; axi_r_injectdbiterr : IN STD_LOGIC; axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_sbiterr : OUT STD_LOGIC; axi_r_dbiterr : OUT STD_LOGIC; axi_r_overflow : OUT STD_LOGIC; axi_r_underflow : OUT STD_LOGIC; axi_r_prog_full : OUT STD_LOGIC; axi_r_prog_empty : OUT STD_LOGIC; axis_injectsbiterr : IN STD_LOGIC; axis_injectdbiterr : IN STD_LOGIC; axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_sbiterr : OUT STD_LOGIC; axis_dbiterr : OUT STD_LOGIC; axis_overflow : OUT STD_LOGIC; axis_underflow : OUT STD_LOGIC; axis_prog_full : OUT STD_LOGIC; axis_prog_empty : OUT STD_LOGIC ); END COMPONENT fifo_generator_v12_0; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF DPBSCFIFO40x64WC_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.4.1"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF DPBSCFIFO40x64WC_arch : ARCHITECTURE IS "DPBSCFIFO40x64WC,fifo_generator_v12_0,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF DPBSCFIFO40x64WC_arch: ARCHITECTURE IS "DPBSCFIFO40x64WC,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=40,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=40,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=1,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=62,C_PROG_FULL_THRESH_NEGATE_VAL=61,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=64,C_RD_FREQ=1,C_RD_PNTR_WIDTH=6,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=64,C_WR_FREQ=1,C_WR_PNTR_WIDTH=6,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA"; ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN"; ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN"; ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA"; ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL"; ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY"; BEGIN U0 : fifo_generator_v12_0 GENERIC MAP ( C_COMMON_CLOCK => 1, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => 6, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => 40, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => 40, C_ENABLE_RLOCS => 0, C_FAMILY => "zynq", C_FULL_FLAGS_RST_VAL => 0, C_HAS_ALMOST_EMPTY => 0, C_HAS_ALMOST_FULL => 0, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => 1, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => 0, C_HAS_RD_DATA_COUNT => 0, C_HAS_RD_RST => 0, C_HAS_RST => 0, C_HAS_SRST => 1, C_HAS_UNDERFLOW => 0, C_HAS_VALID => 0, C_HAS_WR_ACK => 0, C_HAS_WR_DATA_COUNT => 0, C_HAS_WR_RST => 0, C_IMPLEMENTATION_TYPE => 0, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => 1, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => 0, C_PRELOAD_LATENCY => 1, C_PRELOAD_REGS => 0, C_PRIM_FIFO_TYPE => "512x72", C_PROG_EMPTY_THRESH_ASSERT_VAL => 2, C_PROG_EMPTY_THRESH_NEGATE_VAL => 3, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => 62, C_PROG_FULL_THRESH_NEGATE_VAL => 61, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => 6, C_RD_DEPTH => 64, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => 6, C_UNDERFLOW_LOW => 0, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => 0, C_USE_PIPELINE_REG => 0, C_POWER_SAVING_MODE => 0, C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => 0, C_WR_DATA_COUNT_WIDTH => 6, C_WR_DEPTH => 64, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => 6, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => 2, C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_HAS_AXI_WR_CHANNEL => 1, C_HAS_AXI_RD_CHANNEL => 1, C_HAS_SLAVE_CE => 0, C_HAS_MASTER_CE => 0, C_ADD_NGC_CONSTRAINT => 0, C_USE_COMMON_OVERFLOW => 0, C_USE_COMMON_UNDERFLOW => 0, C_USE_DEFAULT_SETTINGS => 0, C_AXI_ID_WIDTH => 1, C_AXI_ADDR_WIDTH => 32, C_AXI_DATA_WIDTH => 64, C_AXI_LEN_WIDTH => 8, C_AXI_LOCK_WIDTH => 1, C_HAS_AXI_ID => 0, C_HAS_AXI_AWUSER => 0, C_HAS_AXI_WUSER => 0, C_HAS_AXI_BUSER => 0, C_HAS_AXI_ARUSER => 0, C_HAS_AXI_RUSER => 0, C_AXI_ARUSER_WIDTH => 1, C_AXI_AWUSER_WIDTH => 1, C_AXI_WUSER_WIDTH => 1, C_AXI_BUSER_WIDTH => 1, C_AXI_RUSER_WIDTH => 1, C_HAS_AXIS_TDATA => 1, C_HAS_AXIS_TID => 0, C_HAS_AXIS_TDEST => 0, C_HAS_AXIS_TUSER => 1, C_HAS_AXIS_TREADY => 1, C_HAS_AXIS_TLAST => 0, C_HAS_AXIS_TSTRB => 0, C_HAS_AXIS_TKEEP => 0, C_AXIS_TDATA_WIDTH => 8, C_AXIS_TID_WIDTH => 1, C_AXIS_TDEST_WIDTH => 1, C_AXIS_TUSER_WIDTH => 4, C_AXIS_TSTRB_WIDTH => 1, C_AXIS_TKEEP_WIDTH => 1, C_WACH_TYPE => 0, C_WDCH_TYPE => 0, C_WRCH_TYPE => 0, C_RACH_TYPE => 0, C_RDCH_TYPE => 0, C_AXIS_TYPE => 0, C_IMPLEMENTATION_TYPE_WACH => 1, C_IMPLEMENTATION_TYPE_WDCH => 1, C_IMPLEMENTATION_TYPE_WRCH => 1, C_IMPLEMENTATION_TYPE_RACH => 1, C_IMPLEMENTATION_TYPE_RDCH => 1, C_IMPLEMENTATION_TYPE_AXIS => 1, C_APPLICATION_TYPE_WACH => 0, C_APPLICATION_TYPE_WDCH => 0, C_APPLICATION_TYPE_WRCH => 0, C_APPLICATION_TYPE_RACH => 0, C_APPLICATION_TYPE_RDCH => 0, C_APPLICATION_TYPE_AXIS => 0, C_PRIM_FIFO_TYPE_WACH => "512x36", C_PRIM_FIFO_TYPE_WDCH => "1kx36", C_PRIM_FIFO_TYPE_WRCH => "512x36", C_PRIM_FIFO_TYPE_RACH => "512x36", C_PRIM_FIFO_TYPE_RDCH => "1kx36", C_PRIM_FIFO_TYPE_AXIS => "1kx18", C_USE_ECC_WACH => 0, C_USE_ECC_WDCH => 0, C_USE_ECC_WRCH => 0, C_USE_ECC_RACH => 0, C_USE_ECC_RDCH => 0, C_USE_ECC_AXIS => 0, C_ERROR_INJECTION_TYPE_WACH => 0, C_ERROR_INJECTION_TYPE_WDCH => 0, C_ERROR_INJECTION_TYPE_WRCH => 0, C_ERROR_INJECTION_TYPE_RACH => 0, C_ERROR_INJECTION_TYPE_RDCH => 0, C_ERROR_INJECTION_TYPE_AXIS => 0, C_DIN_WIDTH_WACH => 32, C_DIN_WIDTH_WDCH => 64, C_DIN_WIDTH_WRCH => 2, C_DIN_WIDTH_RACH => 32, C_DIN_WIDTH_RDCH => 64, C_DIN_WIDTH_AXIS => 1, C_WR_DEPTH_WACH => 16, C_WR_DEPTH_WDCH => 1024, C_WR_DEPTH_WRCH => 16, C_WR_DEPTH_RACH => 16, C_WR_DEPTH_RDCH => 1024, C_WR_DEPTH_AXIS => 1024, C_WR_PNTR_WIDTH_WACH => 4, C_WR_PNTR_WIDTH_WDCH => 10, C_WR_PNTR_WIDTH_WRCH => 4, C_WR_PNTR_WIDTH_RACH => 4, C_WR_PNTR_WIDTH_RDCH => 10, C_WR_PNTR_WIDTH_AXIS => 10, C_HAS_DATA_COUNTS_WACH => 0, C_HAS_DATA_COUNTS_WDCH => 0, C_HAS_DATA_COUNTS_WRCH => 0, C_HAS_DATA_COUNTS_RACH => 0, C_HAS_DATA_COUNTS_RDCH => 0, C_HAS_DATA_COUNTS_AXIS => 0, C_HAS_PROG_FLAGS_WACH => 0, C_HAS_PROG_FLAGS_WDCH => 0, C_HAS_PROG_FLAGS_WRCH => 0, C_HAS_PROG_FLAGS_RACH => 0, C_HAS_PROG_FLAGS_RDCH => 0, C_HAS_PROG_FLAGS_AXIS => 0, C_PROG_FULL_TYPE_WACH => 0, C_PROG_FULL_TYPE_WDCH => 0, C_PROG_FULL_TYPE_WRCH => 0, C_PROG_FULL_TYPE_RACH => 0, C_PROG_FULL_TYPE_RDCH => 0, C_PROG_FULL_TYPE_AXIS => 0, C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, C_PROG_EMPTY_TYPE_WACH => 0, C_PROG_EMPTY_TYPE_WDCH => 0, C_PROG_EMPTY_TYPE_WRCH => 0, C_PROG_EMPTY_TYPE_RACH => 0, C_PROG_EMPTY_TYPE_RDCH => 0, C_PROG_EMPTY_TYPE_AXIS => 0, C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, C_REG_SLICE_MODE_WACH => 0, C_REG_SLICE_MODE_WDCH => 0, C_REG_SLICE_MODE_WRCH => 0, C_REG_SLICE_MODE_RACH => 0, C_REG_SLICE_MODE_RDCH => 0, C_REG_SLICE_MODE_AXIS => 0 ) PORT MAP ( backup => '0', backup_marker => '0', clk => clk, rst => '0', srst => srst, wr_clk => '0', wr_rst => '0', rd_clk => '0', rd_rst => '0', din => din, wr_en => wr_en, rd_en => rd_en, prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), int_clk => '0', injectdbiterr => '0', injectsbiterr => '0', sleep => '0', dout => dout, full => full, empty => empty, data_count => data_count, m_aclk => '0', s_aclk => '0', s_aresetn => '0', m_aclk_en => '0', s_aclk_en => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awvalid => '0', s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wlast => '0', s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wvalid => '0', s_axi_bready => '0', m_axi_awready => '0', m_axi_wready => '0', m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bvalid => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arvalid => '0', s_axi_rready => '0', m_axi_arready => '0', m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_rlast => '0', m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rvalid => '0', s_axis_tvalid => '0', s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tlast => '0', s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), m_axis_tready => '0', axi_aw_injectsbiterr => '0', axi_aw_injectdbiterr => '0', axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_w_injectsbiterr => '0', axi_w_injectdbiterr => '0', axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_b_injectsbiterr => '0', axi_b_injectdbiterr => '0', axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_injectsbiterr => '0', axi_ar_injectdbiterr => '0', axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_r_injectsbiterr => '0', axi_r_injectdbiterr => '0', axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_injectsbiterr => '0', axis_injectdbiterr => '0', axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)) ); END DPBSCFIFO40x64WC_arch;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:fifo_generator:12.0 -- IP Revision: 3 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY fifo_generator_v12_0; USE fifo_generator_v12_0.fifo_generator_v12_0; ENTITY DPBSCFIFO40x64WC IS PORT ( clk : IN STD_LOGIC; srst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(39 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(39 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) ); END DPBSCFIFO40x64WC; ARCHITECTURE DPBSCFIFO40x64WC_arch OF DPBSCFIFO40x64WC IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBSCFIFO40x64WC_arch: ARCHITECTURE IS "yes"; COMPONENT fifo_generator_v12_0 IS GENERIC ( C_COMMON_CLOCK : INTEGER; C_COUNT_TYPE : INTEGER; C_DATA_COUNT_WIDTH : INTEGER; C_DEFAULT_VALUE : STRING; C_DIN_WIDTH : INTEGER; C_DOUT_RST_VAL : STRING; C_DOUT_WIDTH : INTEGER; C_ENABLE_RLOCS : INTEGER; C_FAMILY : STRING; C_FULL_FLAGS_RST_VAL : INTEGER; C_HAS_ALMOST_EMPTY : INTEGER; C_HAS_ALMOST_FULL : INTEGER; C_HAS_BACKUP : INTEGER; C_HAS_DATA_COUNT : INTEGER; C_HAS_INT_CLK : INTEGER; C_HAS_MEMINIT_FILE : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_RD_DATA_COUNT : INTEGER; C_HAS_RD_RST : INTEGER; C_HAS_RST : INTEGER; C_HAS_SRST : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_VALID : INTEGER; C_HAS_WR_ACK : INTEGER; C_HAS_WR_DATA_COUNT : INTEGER; C_HAS_WR_RST : INTEGER; C_IMPLEMENTATION_TYPE : INTEGER; C_INIT_WR_PNTR_VAL : INTEGER; C_MEMORY_TYPE : INTEGER; C_MIF_FILE_NAME : STRING; C_OPTIMIZATION_MODE : INTEGER; C_OVERFLOW_LOW : INTEGER; C_PRELOAD_LATENCY : INTEGER; C_PRELOAD_REGS : INTEGER; C_PRIM_FIFO_TYPE : STRING; C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER; C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER; C_PROG_EMPTY_TYPE : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER; C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER; C_PROG_FULL_TYPE : INTEGER; C_RD_DATA_COUNT_WIDTH : INTEGER; C_RD_DEPTH : INTEGER; C_RD_FREQ : INTEGER; C_RD_PNTR_WIDTH : INTEGER; C_UNDERFLOW_LOW : INTEGER; C_USE_DOUT_RST : INTEGER; C_USE_ECC : INTEGER; C_USE_EMBEDDED_REG : INTEGER; C_USE_PIPELINE_REG : INTEGER; C_POWER_SAVING_MODE : INTEGER; C_USE_FIFO16_FLAGS : INTEGER; C_USE_FWFT_DATA_COUNT : INTEGER; C_VALID_LOW : INTEGER; C_WR_ACK_LOW : INTEGER; C_WR_DATA_COUNT_WIDTH : INTEGER; C_WR_DEPTH : INTEGER; C_WR_FREQ : INTEGER; C_WR_PNTR_WIDTH : INTEGER; C_WR_RESPONSE_LATENCY : INTEGER; C_MSGON_VAL : INTEGER; C_ENABLE_RST_SYNC : INTEGER; C_ERROR_INJECTION_TYPE : INTEGER; C_SYNCHRONIZER_STAGE : INTEGER; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_HAS_AXI_WR_CHANNEL : INTEGER; C_HAS_AXI_RD_CHANNEL : INTEGER; C_HAS_SLAVE_CE : INTEGER; C_HAS_MASTER_CE : INTEGER; C_ADD_NGC_CONSTRAINT : INTEGER; C_USE_COMMON_OVERFLOW : INTEGER; C_USE_COMMON_UNDERFLOW : INTEGER; C_USE_DEFAULT_SETTINGS : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_AXI_ADDR_WIDTH : INTEGER; C_AXI_DATA_WIDTH : INTEGER; C_AXI_LEN_WIDTH : INTEGER; C_AXI_LOCK_WIDTH : INTEGER; C_HAS_AXI_ID : INTEGER; C_HAS_AXI_AWUSER : INTEGER; C_HAS_AXI_WUSER : INTEGER; C_HAS_AXI_BUSER : INTEGER; C_HAS_AXI_ARUSER : INTEGER; C_HAS_AXI_RUSER : INTEGER; C_AXI_ARUSER_WIDTH : INTEGER; C_AXI_AWUSER_WIDTH : INTEGER; C_AXI_WUSER_WIDTH : INTEGER; C_AXI_BUSER_WIDTH : INTEGER; C_AXI_RUSER_WIDTH : INTEGER; C_HAS_AXIS_TDATA : INTEGER; C_HAS_AXIS_TID : INTEGER; C_HAS_AXIS_TDEST : INTEGER; C_HAS_AXIS_TUSER : INTEGER; C_HAS_AXIS_TREADY : INTEGER; C_HAS_AXIS_TLAST : INTEGER; C_HAS_AXIS_TSTRB : INTEGER; C_HAS_AXIS_TKEEP : INTEGER; C_AXIS_TDATA_WIDTH : INTEGER; C_AXIS_TID_WIDTH : INTEGER; C_AXIS_TDEST_WIDTH : INTEGER; C_AXIS_TUSER_WIDTH : INTEGER; C_AXIS_TSTRB_WIDTH : INTEGER; C_AXIS_TKEEP_WIDTH : INTEGER; C_WACH_TYPE : INTEGER; C_WDCH_TYPE : INTEGER; C_WRCH_TYPE : INTEGER; C_RACH_TYPE : INTEGER; C_RDCH_TYPE : INTEGER; C_AXIS_TYPE : INTEGER; C_IMPLEMENTATION_TYPE_WACH : INTEGER; C_IMPLEMENTATION_TYPE_WDCH : INTEGER; C_IMPLEMENTATION_TYPE_WRCH : INTEGER; C_IMPLEMENTATION_TYPE_RACH : INTEGER; C_IMPLEMENTATION_TYPE_RDCH : INTEGER; C_IMPLEMENTATION_TYPE_AXIS : INTEGER; C_APPLICATION_TYPE_WACH : INTEGER; C_APPLICATION_TYPE_WDCH : INTEGER; C_APPLICATION_TYPE_WRCH : INTEGER; C_APPLICATION_TYPE_RACH : INTEGER; C_APPLICATION_TYPE_RDCH : INTEGER; C_APPLICATION_TYPE_AXIS : INTEGER; C_PRIM_FIFO_TYPE_WACH : STRING; C_PRIM_FIFO_TYPE_WDCH : STRING; C_PRIM_FIFO_TYPE_WRCH : STRING; C_PRIM_FIFO_TYPE_RACH : STRING; C_PRIM_FIFO_TYPE_RDCH : STRING; C_PRIM_FIFO_TYPE_AXIS : STRING; C_USE_ECC_WACH : INTEGER; C_USE_ECC_WDCH : INTEGER; C_USE_ECC_WRCH : INTEGER; C_USE_ECC_RACH : INTEGER; C_USE_ECC_RDCH : INTEGER; C_USE_ECC_AXIS : INTEGER; C_ERROR_INJECTION_TYPE_WACH : INTEGER; C_ERROR_INJECTION_TYPE_WDCH : INTEGER; C_ERROR_INJECTION_TYPE_WRCH : INTEGER; C_ERROR_INJECTION_TYPE_RACH : INTEGER; C_ERROR_INJECTION_TYPE_RDCH : INTEGER; C_ERROR_INJECTION_TYPE_AXIS : INTEGER; C_DIN_WIDTH_WACH : INTEGER; C_DIN_WIDTH_WDCH : INTEGER; C_DIN_WIDTH_WRCH : INTEGER; C_DIN_WIDTH_RACH : INTEGER; C_DIN_WIDTH_RDCH : INTEGER; C_DIN_WIDTH_AXIS : INTEGER; C_WR_DEPTH_WACH : INTEGER; C_WR_DEPTH_WDCH : INTEGER; C_WR_DEPTH_WRCH : INTEGER; C_WR_DEPTH_RACH : INTEGER; C_WR_DEPTH_RDCH : INTEGER; C_WR_DEPTH_AXIS : INTEGER; C_WR_PNTR_WIDTH_WACH : INTEGER; C_WR_PNTR_WIDTH_WDCH : INTEGER; C_WR_PNTR_WIDTH_WRCH : INTEGER; C_WR_PNTR_WIDTH_RACH : INTEGER; C_WR_PNTR_WIDTH_RDCH : INTEGER; C_WR_PNTR_WIDTH_AXIS : INTEGER; C_HAS_DATA_COUNTS_WACH : INTEGER; C_HAS_DATA_COUNTS_WDCH : INTEGER; C_HAS_DATA_COUNTS_WRCH : INTEGER; C_HAS_DATA_COUNTS_RACH : INTEGER; C_HAS_DATA_COUNTS_RDCH : INTEGER; C_HAS_DATA_COUNTS_AXIS : INTEGER; C_HAS_PROG_FLAGS_WACH : INTEGER; C_HAS_PROG_FLAGS_WDCH : INTEGER; C_HAS_PROG_FLAGS_WRCH : INTEGER; C_HAS_PROG_FLAGS_RACH : INTEGER; C_HAS_PROG_FLAGS_RDCH : INTEGER; C_HAS_PROG_FLAGS_AXIS : INTEGER; C_PROG_FULL_TYPE_WACH : INTEGER; C_PROG_FULL_TYPE_WDCH : INTEGER; C_PROG_FULL_TYPE_WRCH : INTEGER; C_PROG_FULL_TYPE_RACH : INTEGER; C_PROG_FULL_TYPE_RDCH : INTEGER; C_PROG_FULL_TYPE_AXIS : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER; C_PROG_EMPTY_TYPE_WACH : INTEGER; C_PROG_EMPTY_TYPE_WDCH : INTEGER; C_PROG_EMPTY_TYPE_WRCH : INTEGER; C_PROG_EMPTY_TYPE_RACH : INTEGER; C_PROG_EMPTY_TYPE_RDCH : INTEGER; C_PROG_EMPTY_TYPE_AXIS : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER; C_REG_SLICE_MODE_WACH : INTEGER; C_REG_SLICE_MODE_WDCH : INTEGER; C_REG_SLICE_MODE_WRCH : INTEGER; C_REG_SLICE_MODE_RACH : INTEGER; C_REG_SLICE_MODE_RDCH : INTEGER; C_REG_SLICE_MODE_AXIS : INTEGER ); PORT ( backup : IN STD_LOGIC; backup_marker : IN STD_LOGIC; clk : IN STD_LOGIC; rst : IN STD_LOGIC; srst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; wr_rst : IN STD_LOGIC; rd_clk : IN STD_LOGIC; rd_rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(39 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); int_clk : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; injectsbiterr : IN STD_LOGIC; sleep : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(39 DOWNTO 0); full : OUT STD_LOGIC; almost_full : OUT STD_LOGIC; wr_ack : OUT STD_LOGIC; overflow : OUT STD_LOGIC; empty : OUT STD_LOGIC; almost_empty : OUT STD_LOGIC; valid : OUT STD_LOGIC; underflow : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; wr_rst_busy : OUT STD_LOGIC; rd_rst_busy : OUT STD_LOGIC; m_aclk : IN STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; m_aclk_en : IN STD_LOGIC; s_aclk_en : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awvalid : OUT STD_LOGIC; m_axi_awready : IN STD_LOGIC; m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_wlast : OUT STD_LOGIC; m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wvalid : OUT STD_LOGIC; m_axi_wready : IN STD_LOGIC; m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bvalid : IN STD_LOGIC; m_axi_bready : OUT STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arvalid : OUT STD_LOGIC; m_axi_arready : IN STD_LOGIC; m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_rlast : IN STD_LOGIC; m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rvalid : IN STD_LOGIC; m_axi_rready : OUT STD_LOGIC; s_axis_tvalid : IN STD_LOGIC; s_axis_tready : OUT STD_LOGIC; s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tlast : IN STD_LOGIC; s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_tvalid : OUT STD_LOGIC; m_axis_tready : IN STD_LOGIC; m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tlast : OUT STD_LOGIC; m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_injectsbiterr : IN STD_LOGIC; axi_aw_injectdbiterr : IN STD_LOGIC; axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_sbiterr : OUT STD_LOGIC; axi_aw_dbiterr : OUT STD_LOGIC; axi_aw_overflow : OUT STD_LOGIC; axi_aw_underflow : OUT STD_LOGIC; axi_aw_prog_full : OUT STD_LOGIC; axi_aw_prog_empty : OUT STD_LOGIC; axi_w_injectsbiterr : IN STD_LOGIC; axi_w_injectdbiterr : IN STD_LOGIC; axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_sbiterr : OUT STD_LOGIC; axi_w_dbiterr : OUT STD_LOGIC; axi_w_overflow : OUT STD_LOGIC; axi_w_underflow : OUT STD_LOGIC; axi_w_prog_full : OUT STD_LOGIC; axi_w_prog_empty : OUT STD_LOGIC; axi_b_injectsbiterr : IN STD_LOGIC; axi_b_injectdbiterr : IN STD_LOGIC; axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_sbiterr : OUT STD_LOGIC; axi_b_dbiterr : OUT STD_LOGIC; axi_b_overflow : OUT STD_LOGIC; axi_b_underflow : OUT STD_LOGIC; axi_b_prog_full : OUT STD_LOGIC; axi_b_prog_empty : OUT STD_LOGIC; axi_ar_injectsbiterr : IN STD_LOGIC; axi_ar_injectdbiterr : IN STD_LOGIC; axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_sbiterr : OUT STD_LOGIC; axi_ar_dbiterr : OUT STD_LOGIC; axi_ar_overflow : OUT STD_LOGIC; axi_ar_underflow : OUT STD_LOGIC; axi_ar_prog_full : OUT STD_LOGIC; axi_ar_prog_empty : OUT STD_LOGIC; axi_r_injectsbiterr : IN STD_LOGIC; axi_r_injectdbiterr : IN STD_LOGIC; axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_sbiterr : OUT STD_LOGIC; axi_r_dbiterr : OUT STD_LOGIC; axi_r_overflow : OUT STD_LOGIC; axi_r_underflow : OUT STD_LOGIC; axi_r_prog_full : OUT STD_LOGIC; axi_r_prog_empty : OUT STD_LOGIC; axis_injectsbiterr : IN STD_LOGIC; axis_injectdbiterr : IN STD_LOGIC; axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_sbiterr : OUT STD_LOGIC; axis_dbiterr : OUT STD_LOGIC; axis_overflow : OUT STD_LOGIC; axis_underflow : OUT STD_LOGIC; axis_prog_full : OUT STD_LOGIC; axis_prog_empty : OUT STD_LOGIC ); END COMPONENT fifo_generator_v12_0; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF DPBSCFIFO40x64WC_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.4.1"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF DPBSCFIFO40x64WC_arch : ARCHITECTURE IS "DPBSCFIFO40x64WC,fifo_generator_v12_0,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF DPBSCFIFO40x64WC_arch: ARCHITECTURE IS "DPBSCFIFO40x64WC,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=40,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=40,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=1,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=62,C_PROG_FULL_THRESH_NEGATE_VAL=61,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=64,C_RD_FREQ=1,C_RD_PNTR_WIDTH=6,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=64,C_WR_FREQ=1,C_WR_PNTR_WIDTH=6,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA"; ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN"; ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN"; ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA"; ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL"; ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY"; BEGIN U0 : fifo_generator_v12_0 GENERIC MAP ( C_COMMON_CLOCK => 1, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => 6, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => 40, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => 40, C_ENABLE_RLOCS => 0, C_FAMILY => "zynq", C_FULL_FLAGS_RST_VAL => 0, C_HAS_ALMOST_EMPTY => 0, C_HAS_ALMOST_FULL => 0, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => 1, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => 0, C_HAS_RD_DATA_COUNT => 0, C_HAS_RD_RST => 0, C_HAS_RST => 0, C_HAS_SRST => 1, C_HAS_UNDERFLOW => 0, C_HAS_VALID => 0, C_HAS_WR_ACK => 0, C_HAS_WR_DATA_COUNT => 0, C_HAS_WR_RST => 0, C_IMPLEMENTATION_TYPE => 0, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => 1, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => 0, C_PRELOAD_LATENCY => 1, C_PRELOAD_REGS => 0, C_PRIM_FIFO_TYPE => "512x72", C_PROG_EMPTY_THRESH_ASSERT_VAL => 2, C_PROG_EMPTY_THRESH_NEGATE_VAL => 3, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => 62, C_PROG_FULL_THRESH_NEGATE_VAL => 61, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => 6, C_RD_DEPTH => 64, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => 6, C_UNDERFLOW_LOW => 0, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => 0, C_USE_PIPELINE_REG => 0, C_POWER_SAVING_MODE => 0, C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => 0, C_WR_DATA_COUNT_WIDTH => 6, C_WR_DEPTH => 64, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => 6, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => 2, C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_HAS_AXI_WR_CHANNEL => 1, C_HAS_AXI_RD_CHANNEL => 1, C_HAS_SLAVE_CE => 0, C_HAS_MASTER_CE => 0, C_ADD_NGC_CONSTRAINT => 0, C_USE_COMMON_OVERFLOW => 0, C_USE_COMMON_UNDERFLOW => 0, C_USE_DEFAULT_SETTINGS => 0, C_AXI_ID_WIDTH => 1, C_AXI_ADDR_WIDTH => 32, C_AXI_DATA_WIDTH => 64, C_AXI_LEN_WIDTH => 8, C_AXI_LOCK_WIDTH => 1, C_HAS_AXI_ID => 0, C_HAS_AXI_AWUSER => 0, C_HAS_AXI_WUSER => 0, C_HAS_AXI_BUSER => 0, C_HAS_AXI_ARUSER => 0, C_HAS_AXI_RUSER => 0, C_AXI_ARUSER_WIDTH => 1, C_AXI_AWUSER_WIDTH => 1, C_AXI_WUSER_WIDTH => 1, C_AXI_BUSER_WIDTH => 1, C_AXI_RUSER_WIDTH => 1, C_HAS_AXIS_TDATA => 1, C_HAS_AXIS_TID => 0, C_HAS_AXIS_TDEST => 0, C_HAS_AXIS_TUSER => 1, C_HAS_AXIS_TREADY => 1, C_HAS_AXIS_TLAST => 0, C_HAS_AXIS_TSTRB => 0, C_HAS_AXIS_TKEEP => 0, C_AXIS_TDATA_WIDTH => 8, C_AXIS_TID_WIDTH => 1, C_AXIS_TDEST_WIDTH => 1, C_AXIS_TUSER_WIDTH => 4, C_AXIS_TSTRB_WIDTH => 1, C_AXIS_TKEEP_WIDTH => 1, C_WACH_TYPE => 0, C_WDCH_TYPE => 0, C_WRCH_TYPE => 0, C_RACH_TYPE => 0, C_RDCH_TYPE => 0, C_AXIS_TYPE => 0, C_IMPLEMENTATION_TYPE_WACH => 1, C_IMPLEMENTATION_TYPE_WDCH => 1, C_IMPLEMENTATION_TYPE_WRCH => 1, C_IMPLEMENTATION_TYPE_RACH => 1, C_IMPLEMENTATION_TYPE_RDCH => 1, C_IMPLEMENTATION_TYPE_AXIS => 1, C_APPLICATION_TYPE_WACH => 0, C_APPLICATION_TYPE_WDCH => 0, C_APPLICATION_TYPE_WRCH => 0, C_APPLICATION_TYPE_RACH => 0, C_APPLICATION_TYPE_RDCH => 0, C_APPLICATION_TYPE_AXIS => 0, C_PRIM_FIFO_TYPE_WACH => "512x36", C_PRIM_FIFO_TYPE_WDCH => "1kx36", C_PRIM_FIFO_TYPE_WRCH => "512x36", C_PRIM_FIFO_TYPE_RACH => "512x36", C_PRIM_FIFO_TYPE_RDCH => "1kx36", C_PRIM_FIFO_TYPE_AXIS => "1kx18", C_USE_ECC_WACH => 0, C_USE_ECC_WDCH => 0, C_USE_ECC_WRCH => 0, C_USE_ECC_RACH => 0, C_USE_ECC_RDCH => 0, C_USE_ECC_AXIS => 0, C_ERROR_INJECTION_TYPE_WACH => 0, C_ERROR_INJECTION_TYPE_WDCH => 0, C_ERROR_INJECTION_TYPE_WRCH => 0, C_ERROR_INJECTION_TYPE_RACH => 0, C_ERROR_INJECTION_TYPE_RDCH => 0, C_ERROR_INJECTION_TYPE_AXIS => 0, C_DIN_WIDTH_WACH => 32, C_DIN_WIDTH_WDCH => 64, C_DIN_WIDTH_WRCH => 2, C_DIN_WIDTH_RACH => 32, C_DIN_WIDTH_RDCH => 64, C_DIN_WIDTH_AXIS => 1, C_WR_DEPTH_WACH => 16, C_WR_DEPTH_WDCH => 1024, C_WR_DEPTH_WRCH => 16, C_WR_DEPTH_RACH => 16, C_WR_DEPTH_RDCH => 1024, C_WR_DEPTH_AXIS => 1024, C_WR_PNTR_WIDTH_WACH => 4, C_WR_PNTR_WIDTH_WDCH => 10, C_WR_PNTR_WIDTH_WRCH => 4, C_WR_PNTR_WIDTH_RACH => 4, C_WR_PNTR_WIDTH_RDCH => 10, C_WR_PNTR_WIDTH_AXIS => 10, C_HAS_DATA_COUNTS_WACH => 0, C_HAS_DATA_COUNTS_WDCH => 0, C_HAS_DATA_COUNTS_WRCH => 0, C_HAS_DATA_COUNTS_RACH => 0, C_HAS_DATA_COUNTS_RDCH => 0, C_HAS_DATA_COUNTS_AXIS => 0, C_HAS_PROG_FLAGS_WACH => 0, C_HAS_PROG_FLAGS_WDCH => 0, C_HAS_PROG_FLAGS_WRCH => 0, C_HAS_PROG_FLAGS_RACH => 0, C_HAS_PROG_FLAGS_RDCH => 0, C_HAS_PROG_FLAGS_AXIS => 0, C_PROG_FULL_TYPE_WACH => 0, C_PROG_FULL_TYPE_WDCH => 0, C_PROG_FULL_TYPE_WRCH => 0, C_PROG_FULL_TYPE_RACH => 0, C_PROG_FULL_TYPE_RDCH => 0, C_PROG_FULL_TYPE_AXIS => 0, C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, C_PROG_EMPTY_TYPE_WACH => 0, C_PROG_EMPTY_TYPE_WDCH => 0, C_PROG_EMPTY_TYPE_WRCH => 0, C_PROG_EMPTY_TYPE_RACH => 0, C_PROG_EMPTY_TYPE_RDCH => 0, C_PROG_EMPTY_TYPE_AXIS => 0, C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, C_REG_SLICE_MODE_WACH => 0, C_REG_SLICE_MODE_WDCH => 0, C_REG_SLICE_MODE_WRCH => 0, C_REG_SLICE_MODE_RACH => 0, C_REG_SLICE_MODE_RDCH => 0, C_REG_SLICE_MODE_AXIS => 0 ) PORT MAP ( backup => '0', backup_marker => '0', clk => clk, rst => '0', srst => srst, wr_clk => '0', wr_rst => '0', rd_clk => '0', rd_rst => '0', din => din, wr_en => wr_en, rd_en => rd_en, prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), int_clk => '0', injectdbiterr => '0', injectsbiterr => '0', sleep => '0', dout => dout, full => full, empty => empty, data_count => data_count, m_aclk => '0', s_aclk => '0', s_aresetn => '0', m_aclk_en => '0', s_aclk_en => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awvalid => '0', s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wlast => '0', s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wvalid => '0', s_axi_bready => '0', m_axi_awready => '0', m_axi_wready => '0', m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bvalid => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arvalid => '0', s_axi_rready => '0', m_axi_arready => '0', m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_rlast => '0', m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rvalid => '0', s_axis_tvalid => '0', s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tlast => '0', s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), m_axis_tready => '0', axi_aw_injectsbiterr => '0', axi_aw_injectdbiterr => '0', axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_w_injectsbiterr => '0', axi_w_injectdbiterr => '0', axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_b_injectsbiterr => '0', axi_b_injectdbiterr => '0', axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_injectsbiterr => '0', axi_ar_injectdbiterr => '0', axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_r_injectsbiterr => '0', axi_r_injectdbiterr => '0', axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_injectsbiterr => '0', axis_injectdbiterr => '0', axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)) ); END DPBSCFIFO40x64WC_arch;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 21:00:50 11/11/2017 -- Design Name: -- Module Name: Execute - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Execute is Port ( callin : in STD_LOGIC_VECTOR (31 downto 0); ifin : in STD_LOGIC_VECTOR (31 downto 0); pcsourcein : in STD_LOGIC_VECTOR (1 downto 0); aluopin : in STD_LOGIC_VECTOR (5 downto 0); op1in : in STD_LOGIC_VECTOR (31 downto 0); op2in : in STD_LOGIC_VECTOR (31 downto 0); cwp : out STD_LOGIC; ncwp : in STD_LOGIC; icc : out STD_LOGIC_VECTOR (3 downto 0); nextpc : out STD_LOGIC_VECTOR (31 downto 0); aluresult : out STD_LOGIC_VECTOR (31 downto 0); Clkinext : in STD_LOGIC; Resetext : in STD_LOGIC); end Execute; architecture Behavioral of Execute is COMPONENT ALU PORT( OPER1 : in STD_LOGIC_VECTOR (31 downto 0); OPER2 : in STD_LOGIC_VECTOR (31 downto 0); c :in STD_LOGIC; ALURESULT : out STD_LOGIC_VECTOR (31 downto 0); ALUOP : in STD_LOGIC_VECTOR (5 downto 0) ); END COMPONENT; COMPONENT PSR PORT( nzvc : in STD_LOGIC_VECTOR (3 downto 0); clk : in STD_LOGIC ; cwp : out STD_LOGIC; ncwp : in STD_LOGIC; icc : out STD_LOGIC_VECTOR (3 downto 0); rest : in STD_LOGIC; c : out STD_LOGIC ); END COMPONENT; COMPONENT PSR_Modifier PORT( oper1 : in STD_LOGIC_VECTOR (31 downto 0); oper2 : in STD_LOGIC_VECTOR (31 downto 0); aluop : in STD_LOGIC_VECTOR (5 downto 0); aluResult : in STD_LOGIC_VECTOR (31 downto 0); conditionalCodes : out STD_LOGIC_VECTOR (3 downto 0) ); END COMPONENT; COMPONENT MuxPC PORT( Disp30 : in STD_LOGIC_VECTOR (31 downto 0); Disp22 : in STD_LOGIC_VECTOR (31 downto 0); PC1 : in STD_LOGIC_VECTOR (31 downto 0); Direccion : in STD_LOGIC_VECTOR (31 downto 0); Selector : in STD_LOGIC_VECTOR (1 downto 0); Direccion_Out : out STD_LOGIC_VECTOR (31 downto 0) ); END COMPONENT; signal a23: std_logic_vector(31 downto 0); signal a29: STD_LOGIC; signal a28: std_logic_vector(3 downto 0); begin ints_alu: ALU PORT MAP( OPER1 => op1in, OPER2 => op2in, c =>a29, ALURESULT => a23, ALUOP => aluopin ); aluresult<= a23; ints_psr: PSR PORT MAP( nzvc => a28, clk => Clkinext, cwp => cwp, rest => Resetext, ncwp => ncwp, icc => icc, c => a29 ); ints_psrmodifier: PSR_Modifier PORT MAP( oper1 => op1in, oper2 => op2in, aluop => aluopin, aluResult => a23, conditionalCodes => a28 ); ints_muxPC: MuxPC PORT MAP( Disp30 => callin, Disp22 => ifin, PC1 => "00000000000000000000000000000000", Direccion => a23, Selector => pcsourcein, Direccion_Out => nextpc ); end Behavioral;
entity assign4 is end entity; architecture test of assign4 is type int_vec is array (natural range <>) of integer; begin check: process is variable v : int_vec(1 to 2); variable a, b : integer; begin v := (1, 2); wait for 1 ns; (a, b) := v; wait for 1 ns; assert a = 1; assert b = 2; (a, b) := int_vec'(5, 7); assert a = 5; assert b = 7; wait; end process; end architecture;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.common.all; use work.decode_pkg.all; package encode_pkg is subtype register_t is integer range 0 to 31; -- functions to encode the different types of instructions, organized by format function encode_r_type (insn_type : r_insn_t; rs1, rs2, rd : register_t) return word; function encode_i_type (insn_type : i_insn_t; imm : std_logic_vector(11 downto 0); rs1, rd : register_t) return word; function encode_s_type (insn_type : s_insn_t; imm : std_logic_vector(11 downto 0); rs1, rs2 : register_t) return word; function encode_sb_type (insn_type : sb_insn_t; imm : std_logic_vector(12 downto 1); rs1, rs2 : register_t) return word; function encode_u_type (insn_type : u_insn_t; imm_31_12 : std_logic_vector(31 downto 12); rd : register_t) return word; function encode_uj_type (insn_type : uj_insn_t; imm : std_logic_vector(20 downto 1); rd : register_t) return word; function encode_i_shift (i_insn : i_insn_t; shamt : std_logic_vector(4 downto 0); rs1, rd : register_t) return word; end package encode_pkg; package body encode_pkg is -- purpose: encode a U-type instruction function encode_u_type (insn_type : u_insn_t; imm_31_12 : std_logic_vector(31 downto 12); rd : register_t) return word is variable result : word; begin -- function encode_lui result(31 downto 12) := imm_31_12; result(11 downto 7) := std_logic_vector(to_unsigned(rd, 5)); case insn_type is when U_LUI => result(6 downto 0) := c_op_lui; when U_AUIPC => result(6 downto 0) := c_op_auipc; end case; return result; end function encode_u_type; -- purpose: encode an R-type instruction function encode_r_type (insn_type : r_insn_t; rs1, rs2, rd : register_t) return word is variable result : word; begin -- function encode_r_type result(24 downto 20) := std_logic_vector(to_unsigned(rs2, 5)); result(19 downto 15) := std_logic_vector(to_unsigned(rs1, 5)); result(11 downto 7) := std_logic_vector(to_unsigned(rd, 5)); result(6 downto 0) := c_op_reg; case insn_type is when R_ADD => result(31 downto 25) := "0000000"; result(14 downto 12) := "000"; when R_SUB => result(31 downto 25) := "0100000"; result(14 downto 12) := "000"; when R_SLL => result(31 downto 25) := "0000000"; result(14 downto 12) := "001"; when R_SLT => result(31 downto 25) := "0000000"; result(14 downto 12) := "010"; when R_SLTU => result(31 downto 25) := "0000000"; result(14 downto 12) := "011"; when R_XOR => result(31 downto 25) := "0000000"; result(14 downto 12) := "100"; when R_SRL => result(31 downto 25) := "0000000"; result(14 downto 12) := "101"; when R_SRA => result(31 downto 25) := "0100000"; result(14 downto 12) := "101"; when R_OR => result(31 downto 25) := "0000000"; result(14 downto 12) := "110"; when R_AND => result(31 downto 25) := "0000000"; result(14 downto 12) := "111"; end case; return result; end function encode_r_type; -- purpose: encode a UJ-type instruction function encode_uj_type ( insn_type : uj_insn_t; imm : std_logic_vector(20 downto 1); rd : register_t) return word is variable result : word; begin -- function encode_uj_type result(31) := imm(20); result(30 downto 21) := imm(10 downto 1); result(20) := imm(11); result(19 downto 12) := imm(19 downto 12); result(11 downto 7) := std_logic_vector(to_unsigned(rd, 5)); case insn_type is when UJ_JAL => result(6 downto 0) := c_op_jal; end case; return result; end function encode_uj_type; -- purpose: encode an I-type instruction (for shifts only) function encode_i_shift ( i_insn : i_insn_t; shamt : std_logic_vector(4 downto 0); rs1, rd : register_t) return word is variable result : word; begin -- function encode_i_shift result(24 downto 20) := shamt; result(19 downto 15) := std_logic_vector(to_unsigned(rs1, 5)); result(11 downto 7) := std_logic_vector(to_unsigned(rd, 5)); result(6 downto 0) := c_op_imm; case (i_insn) is when I_SLLI => result(31 downto 25) := "0000000"; result(14 downto 12) := "001"; when I_SRLI => result(31 downto 25) := "0000000"; result(14 downto 12) := "101"; when I_SRAI => result(31 downto 25) := "0100000"; result(14 downto 12) := "101"; when others => assert false report "Not an immediate shift instruction" severity error; end case; return result; end function encode_i_shift; -- purpose: encode an I-type instruction function encode_i_type (insn_type : i_insn_t; imm : std_logic_vector(11 downto 0); rs1, rd : register_t) return word is variable result : word; begin result(31 downto 20) := imm; result(19 downto 15) := std_logic_vector(to_unsigned(rs1, 5)); result(11 downto 7) := std_logic_vector(to_unsigned(rd, 5)); case insn_type is when I_JALR => result(14 downto 12) := "000"; result(6 downto 0) := c_op_jalr; when I_LB => result(14 downto 12) := "000"; result(6 downto 0) := c_op_load; when I_LH => result(14 downto 12) := "001"; result(6 downto 0) := c_op_load; when I_LW => result(14 downto 12) := "010"; result(6 downto 0) := c_op_load; when I_LBU => result(14 downto 12) := "100"; result(6 downto 0) := c_op_load; when I_LHU => result(14 downto 12) := "101"; result(6 downto 0) := c_op_load; when I_ADDI => result(14 downto 12) := "000"; result(6 downto 0) := c_op_imm; when I_SLTI => result(14 downto 12) := "010"; result(6 downto 0) := c_op_imm; when I_SLTIU => result(14 downto 12) := "011"; result(6 downto 0) := c_op_imm; when I_XORI => result(14 downto 12) := "100"; result(6 downto 0) := c_op_imm; when I_ORI => result(14 downto 12) := "110"; result(6 downto 0) := c_op_imm; when I_ANDI => result(14 downto 12) := "111"; result(6 downto 0) := c_op_imm; when others => assert false report "Use encode_i_shift" severity error; end case; return result; end function encode_i_type; -- purpose: encode an S-type instruction function encode_s_type (insn_type : s_insn_t; imm : std_logic_vector(11 downto 0); rs1, rs2 : register_t) return word is variable result : word; begin -- function encode_s_type result(31 downto 25) := imm(11 downto 5); result(24 downto 20) := std_logic_vector(to_unsigned(rs2, 5)); result(19 downto 15) := std_logic_vector(to_unsigned(rs1, 5)); result(11 downto 7) := imm(4 downto 0); result(6 downto 0) := c_op_store; case insn_type is when S_SB => result(14 downto 12) := "000"; when S_SH => result(14 downto 12) := "001"; when S_SW => result(14 downto 12) := "010"; end case; return result; end function encode_s_type; -- encode an SB-type instruction function encode_sb_type (insn_type : sb_insn_t; imm : std_logic_vector(12 downto 1); rs1, rs2 : register_t) return word is variable result : word; begin result(31) := imm(12); result(30 downto 25) := imm(10 downto 5); result(24 downto 20) := std_logic_vector(to_unsigned(rs2, 5)); result(19 downto 15) := std_logic_vector(to_unsigned(rs1, 5)); result(11 downto 8) := imm(4 downto 1); result(7) := imm(11); result(6 downto 0) := c_op_branch; case insn_type is when SB_BEQ => result(14 downto 12) := "000"; when SB_BNE => result(14 downto 12) := "001"; when SB_BLT => result(14 downto 12) := "100"; when SB_BGE => result(14 downto 12) := "101"; when SB_BLTU => result(14 downto 12) := "110"; when SB_BGEU => result(14 downto 12) := "111"; end case; return result; end function encode_sb_type; end package body encode_pkg;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.common.all; use work.decode_pkg.all; package encode_pkg is subtype register_t is integer range 0 to 31; -- functions to encode the different types of instructions, organized by format function encode_r_type (insn_type : r_insn_t; rs1, rs2, rd : register_t) return word; function encode_i_type (insn_type : i_insn_t; imm : std_logic_vector(11 downto 0); rs1, rd : register_t) return word; function encode_s_type (insn_type : s_insn_t; imm : std_logic_vector(11 downto 0); rs1, rs2 : register_t) return word; function encode_sb_type (insn_type : sb_insn_t; imm : std_logic_vector(12 downto 1); rs1, rs2 : register_t) return word; function encode_u_type (insn_type : u_insn_t; imm_31_12 : std_logic_vector(31 downto 12); rd : register_t) return word; function encode_uj_type (insn_type : uj_insn_t; imm : std_logic_vector(20 downto 1); rd : register_t) return word; function encode_i_shift (i_insn : i_insn_t; shamt : std_logic_vector(4 downto 0); rs1, rd : register_t) return word; end package encode_pkg; package body encode_pkg is -- purpose: encode a U-type instruction function encode_u_type (insn_type : u_insn_t; imm_31_12 : std_logic_vector(31 downto 12); rd : register_t) return word is variable result : word; begin -- function encode_lui result(31 downto 12) := imm_31_12; result(11 downto 7) := std_logic_vector(to_unsigned(rd, 5)); case insn_type is when U_LUI => result(6 downto 0) := c_op_lui; when U_AUIPC => result(6 downto 0) := c_op_auipc; end case; return result; end function encode_u_type; -- purpose: encode an R-type instruction function encode_r_type (insn_type : r_insn_t; rs1, rs2, rd : register_t) return word is variable result : word; begin -- function encode_r_type result(24 downto 20) := std_logic_vector(to_unsigned(rs2, 5)); result(19 downto 15) := std_logic_vector(to_unsigned(rs1, 5)); result(11 downto 7) := std_logic_vector(to_unsigned(rd, 5)); result(6 downto 0) := c_op_reg; case insn_type is when R_ADD => result(31 downto 25) := "0000000"; result(14 downto 12) := "000"; when R_SUB => result(31 downto 25) := "0100000"; result(14 downto 12) := "000"; when R_SLL => result(31 downto 25) := "0000000"; result(14 downto 12) := "001"; when R_SLT => result(31 downto 25) := "0000000"; result(14 downto 12) := "010"; when R_SLTU => result(31 downto 25) := "0000000"; result(14 downto 12) := "011"; when R_XOR => result(31 downto 25) := "0000000"; result(14 downto 12) := "100"; when R_SRL => result(31 downto 25) := "0000000"; result(14 downto 12) := "101"; when R_SRA => result(31 downto 25) := "0100000"; result(14 downto 12) := "101"; when R_OR => result(31 downto 25) := "0000000"; result(14 downto 12) := "110"; when R_AND => result(31 downto 25) := "0000000"; result(14 downto 12) := "111"; end case; return result; end function encode_r_type; -- purpose: encode a UJ-type instruction function encode_uj_type ( insn_type : uj_insn_t; imm : std_logic_vector(20 downto 1); rd : register_t) return word is variable result : word; begin -- function encode_uj_type result(31) := imm(20); result(30 downto 21) := imm(10 downto 1); result(20) := imm(11); result(19 downto 12) := imm(19 downto 12); result(11 downto 7) := std_logic_vector(to_unsigned(rd, 5)); case insn_type is when UJ_JAL => result(6 downto 0) := c_op_jal; end case; return result; end function encode_uj_type; -- purpose: encode an I-type instruction (for shifts only) function encode_i_shift ( i_insn : i_insn_t; shamt : std_logic_vector(4 downto 0); rs1, rd : register_t) return word is variable result : word; begin -- function encode_i_shift result(24 downto 20) := shamt; result(19 downto 15) := std_logic_vector(to_unsigned(rs1, 5)); result(11 downto 7) := std_logic_vector(to_unsigned(rd, 5)); result(6 downto 0) := c_op_imm; case (i_insn) is when I_SLLI => result(31 downto 25) := "0000000"; result(14 downto 12) := "001"; when I_SRLI => result(31 downto 25) := "0000000"; result(14 downto 12) := "101"; when I_SRAI => result(31 downto 25) := "0100000"; result(14 downto 12) := "101"; when others => assert false report "Not an immediate shift instruction" severity error; end case; return result; end function encode_i_shift; -- purpose: encode an I-type instruction function encode_i_type (insn_type : i_insn_t; imm : std_logic_vector(11 downto 0); rs1, rd : register_t) return word is variable result : word; begin result(31 downto 20) := imm; result(19 downto 15) := std_logic_vector(to_unsigned(rs1, 5)); result(11 downto 7) := std_logic_vector(to_unsigned(rd, 5)); case insn_type is when I_JALR => result(14 downto 12) := "000"; result(6 downto 0) := c_op_jalr; when I_LB => result(14 downto 12) := "000"; result(6 downto 0) := c_op_load; when I_LH => result(14 downto 12) := "001"; result(6 downto 0) := c_op_load; when I_LW => result(14 downto 12) := "010"; result(6 downto 0) := c_op_load; when I_LBU => result(14 downto 12) := "100"; result(6 downto 0) := c_op_load; when I_LHU => result(14 downto 12) := "101"; result(6 downto 0) := c_op_load; when I_ADDI => result(14 downto 12) := "000"; result(6 downto 0) := c_op_imm; when I_SLTI => result(14 downto 12) := "010"; result(6 downto 0) := c_op_imm; when I_SLTIU => result(14 downto 12) := "011"; result(6 downto 0) := c_op_imm; when I_XORI => result(14 downto 12) := "100"; result(6 downto 0) := c_op_imm; when I_ORI => result(14 downto 12) := "110"; result(6 downto 0) := c_op_imm; when I_ANDI => result(14 downto 12) := "111"; result(6 downto 0) := c_op_imm; when others => assert false report "Use encode_i_shift" severity error; end case; return result; end function encode_i_type; -- purpose: encode an S-type instruction function encode_s_type (insn_type : s_insn_t; imm : std_logic_vector(11 downto 0); rs1, rs2 : register_t) return word is variable result : word; begin -- function encode_s_type result(31 downto 25) := imm(11 downto 5); result(24 downto 20) := std_logic_vector(to_unsigned(rs2, 5)); result(19 downto 15) := std_logic_vector(to_unsigned(rs1, 5)); result(11 downto 7) := imm(4 downto 0); result(6 downto 0) := c_op_store; case insn_type is when S_SB => result(14 downto 12) := "000"; when S_SH => result(14 downto 12) := "001"; when S_SW => result(14 downto 12) := "010"; end case; return result; end function encode_s_type; -- encode an SB-type instruction function encode_sb_type (insn_type : sb_insn_t; imm : std_logic_vector(12 downto 1); rs1, rs2 : register_t) return word is variable result : word; begin result(31) := imm(12); result(30 downto 25) := imm(10 downto 5); result(24 downto 20) := std_logic_vector(to_unsigned(rs2, 5)); result(19 downto 15) := std_logic_vector(to_unsigned(rs1, 5)); result(11 downto 8) := imm(4 downto 1); result(7) := imm(11); result(6 downto 0) := c_op_branch; case insn_type is when SB_BEQ => result(14 downto 12) := "000"; when SB_BNE => result(14 downto 12) := "001"; when SB_BLT => result(14 downto 12) := "100"; when SB_BGE => result(14 downto 12) := "101"; when SB_BLTU => result(14 downto 12) := "110"; when SB_BGEU => result(14 downto 12) := "111"; end case; return result; end function encode_sb_type; end package body encode_pkg;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_08_fg_08_08.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- package bit_vector_signed_arithmetic is function "+" ( bv1, bv2 : bit_vector ) return bit_vector; function "-" ( bv : bit_vector ) return bit_vector; function "*" ( bv1, bv2 : bit_vector ) return bit_vector; -- . . . end package bit_vector_signed_arithmetic; -- not in book library bv_utilities; use bv_utilities.bv_arithmetic; -- end not in book package body bit_vector_signed_arithmetic is function "+" ( bv1, bv2 : bit_vector ) return bit_vector is -- . . . -- not in book begin return bv_arithmetic."+"(bv1, bv2); end function "+"; -- end not in book function "-" ( bv : bit_vector ) return bit_vector is -- . . . -- not in book begin return bv_arithmetic."-"(bv); end function "-"; -- end not in book function mult_unsigned ( bv1, bv2 : bit_vector ) return bit_vector is -- . . . begin -- not in book -- . . . return bv_arithmetic.bv_multu(bv1, bv2); -- end not in book end function mult_unsigned; function "*" ( bv1, bv2 : bit_vector ) return bit_vector is begin if bv1(bv1'left) = '0' and bv2(bv2'left) = '0' then return mult_unsigned(bv1, bv2); elsif bv1(bv1'left) = '0' and bv2(bv2'left) = '1' then return -mult_unsigned(bv1, -bv2); elsif bv1(bv1'left) = '1' and bv2(bv2'left) = '0' then return -mult_unsigned(-bv1, bv2); else return mult_unsigned(-bv1, -bv2); end if; end function "*"; -- . . . end package body bit_vector_signed_arithmetic; -- not in book entity fg_08_08 is end entity fg_08_08; library bv_utilities; use bv_utilities.bit_vector_signed_arithmetic.all; use std.textio.all; architecture test of fg_08_08 is begin stimulus : process is variable L : line; begin write(L, X"0002" + X"0005"); writeline(output, L); write(L, X"0002" + X"FFFE"); writeline(output, L); write(L, - X"0005"); writeline(output, L); write(L, - X"FFFE"); writeline(output, L); write(L, X"0002" * X"0005"); writeline(output, L); write(L, X"0002" * X"FFFD"); writeline(output, L); wait; end process stimulus; end architecture test; -- end not in book
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_08_fg_08_08.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- package bit_vector_signed_arithmetic is function "+" ( bv1, bv2 : bit_vector ) return bit_vector; function "-" ( bv : bit_vector ) return bit_vector; function "*" ( bv1, bv2 : bit_vector ) return bit_vector; -- . . . end package bit_vector_signed_arithmetic; -- not in book library bv_utilities; use bv_utilities.bv_arithmetic; -- end not in book package body bit_vector_signed_arithmetic is function "+" ( bv1, bv2 : bit_vector ) return bit_vector is -- . . . -- not in book begin return bv_arithmetic."+"(bv1, bv2); end function "+"; -- end not in book function "-" ( bv : bit_vector ) return bit_vector is -- . . . -- not in book begin return bv_arithmetic."-"(bv); end function "-"; -- end not in book function mult_unsigned ( bv1, bv2 : bit_vector ) return bit_vector is -- . . . begin -- not in book -- . . . return bv_arithmetic.bv_multu(bv1, bv2); -- end not in book end function mult_unsigned; function "*" ( bv1, bv2 : bit_vector ) return bit_vector is begin if bv1(bv1'left) = '0' and bv2(bv2'left) = '0' then return mult_unsigned(bv1, bv2); elsif bv1(bv1'left) = '0' and bv2(bv2'left) = '1' then return -mult_unsigned(bv1, -bv2); elsif bv1(bv1'left) = '1' and bv2(bv2'left) = '0' then return -mult_unsigned(-bv1, bv2); else return mult_unsigned(-bv1, -bv2); end if; end function "*"; -- . . . end package body bit_vector_signed_arithmetic; -- not in book entity fg_08_08 is end entity fg_08_08; library bv_utilities; use bv_utilities.bit_vector_signed_arithmetic.all; use std.textio.all; architecture test of fg_08_08 is begin stimulus : process is variable L : line; begin write(L, X"0002" + X"0005"); writeline(output, L); write(L, X"0002" + X"FFFE"); writeline(output, L); write(L, - X"0005"); writeline(output, L); write(L, - X"FFFE"); writeline(output, L); write(L, X"0002" * X"0005"); writeline(output, L); write(L, X"0002" * X"FFFD"); writeline(output, L); wait; end process stimulus; end architecture test; -- end not in book
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_08_fg_08_08.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- package bit_vector_signed_arithmetic is function "+" ( bv1, bv2 : bit_vector ) return bit_vector; function "-" ( bv : bit_vector ) return bit_vector; function "*" ( bv1, bv2 : bit_vector ) return bit_vector; -- . . . end package bit_vector_signed_arithmetic; -- not in book library bv_utilities; use bv_utilities.bv_arithmetic; -- end not in book package body bit_vector_signed_arithmetic is function "+" ( bv1, bv2 : bit_vector ) return bit_vector is -- . . . -- not in book begin return bv_arithmetic."+"(bv1, bv2); end function "+"; -- end not in book function "-" ( bv : bit_vector ) return bit_vector is -- . . . -- not in book begin return bv_arithmetic."-"(bv); end function "-"; -- end not in book function mult_unsigned ( bv1, bv2 : bit_vector ) return bit_vector is -- . . . begin -- not in book -- . . . return bv_arithmetic.bv_multu(bv1, bv2); -- end not in book end function mult_unsigned; function "*" ( bv1, bv2 : bit_vector ) return bit_vector is begin if bv1(bv1'left) = '0' and bv2(bv2'left) = '0' then return mult_unsigned(bv1, bv2); elsif bv1(bv1'left) = '0' and bv2(bv2'left) = '1' then return -mult_unsigned(bv1, -bv2); elsif bv1(bv1'left) = '1' and bv2(bv2'left) = '0' then return -mult_unsigned(-bv1, bv2); else return mult_unsigned(-bv1, -bv2); end if; end function "*"; -- . . . end package body bit_vector_signed_arithmetic; -- not in book entity fg_08_08 is end entity fg_08_08; library bv_utilities; use bv_utilities.bit_vector_signed_arithmetic.all; use std.textio.all; architecture test of fg_08_08 is begin stimulus : process is variable L : line; begin write(L, X"0002" + X"0005"); writeline(output, L); write(L, X"0002" + X"FFFE"); writeline(output, L); write(L, - X"0005"); writeline(output, L); write(L, - X"FFFE"); writeline(output, L); write(L, X"0002" * X"0005"); writeline(output, L); write(L, X"0002" * X"FFFD"); writeline(output, L); wait; end process stimulus; end architecture test; -- end not in book
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.all; entity immediate_memory is port(immediate_addr : in std_logic_vector(5 downto 0); immediate_out : out std_logic_vector(31 downto 0)); end immediate_memory; architecture Behavioral of immediate_memory is type immediate_data_type is array (63 downto 0) of std_logic_vector(31 downto 0); signal immediate_data : immediate_data_type; begin immediate_out <= immediate_data(conv_integer(unsigned(immediate_addr))); immediate_data(0) <= x"00000000"; immediate_data(1) <= x"00000001"; immediate_data(2) <= x"00000002"; immediate_data(3) <= x"00000003"; immediate_data(4) <= x"00000004"; immediate_data(5) <= x"00000010"; immediate_data(6) <= x"00000010"; immediate_data(7) <= x"00000013"; immediate_data(8) <= x"00000025"; immediate_data(9) <= x"0000000b"; immediate_data(10) <= x"0000003b"; immediate_data(11) <= x"00000053"; immediate_data(12) <= x"0000005b"; end Behavioral;
entity repro is end repro; architecture behav of repro is constant c1 : character := character'value("ack"); constant c2 : character := character'value("'Z'"); constant c3 : character := character'value("'a'"); constant c4 : boolean := boolean'value("TruE"); constant c5 : boolean := boolean'value("TruE "); constant c6 : boolean := boolean'value(" TruE "); begin assert c1 = ack report "value incorrect for ack" severity failure; assert c2 = 'Z' report "value incorrect for 'Z'" severity failure; assert c3 = 'a' report "value incorrect for 'a'" severity failure; assert c4 and c5 and c6 severity failure; end behav;
entity repro is end repro; architecture behav of repro is constant c1 : character := character'value("ack"); constant c2 : character := character'value("'Z'"); constant c3 : character := character'value("'a'"); constant c4 : boolean := boolean'value("TruE"); constant c5 : boolean := boolean'value("TruE "); constant c6 : boolean := boolean'value(" TruE "); begin assert c1 = ack report "value incorrect for ack" severity failure; assert c2 = 'Z' report "value incorrect for 'Z'" severity failure; assert c3 = 'a' report "value incorrect for 'a'" severity failure; assert c4 and c5 and c6 severity failure; end behav;
library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; entity mc_rnd is port( clock: in std_logic; input: in std_logic_vector(2 downto 0); output: out std_logic_vector(4 downto 0) ); end mc_rnd; architecture behaviour of mc_rnd is constant HG: std_logic_vector(1 downto 0) := "01"; constant HY: std_logic_vector(1 downto 0) := "10"; constant FG: std_logic_vector(1 downto 0) := "11"; constant FY: std_logic_vector(1 downto 0) := "00"; signal current_state, next_state: std_logic_vector(1 downto 0); begin process(clock) begin if rising_edge(clock) then current_state <= next_state; end if; end process; process(input, current_state) begin next_state <= "--"; output <= "-----"; case current_state is when HG => if std_match(input, "0--") then next_state <= HG; output <= "00010"; elsif std_match(input, "-0-") then next_state <= HG; output <= "00010"; elsif std_match(input, "11-") then next_state <= HY; output <= "10010"; end if; when HY => if std_match(input, "--0") then next_state <= HY; output <= "00110"; elsif std_match(input, "--1") then next_state <= FG; output <= "10110"; end if; when FG => if std_match(input, "10-") then next_state <= FG; output <= "01000"; elsif std_match(input, "0--") then next_state <= FY; output <= "11000"; elsif std_match(input, "-1-") then next_state <= FY; output <= "11000"; end if; when FY => if std_match(input, "--0") then next_state <= FY; output <= "01001"; elsif std_match(input, "--1") then next_state <= HG; output <= "11001"; end if; when others => next_state <= "--"; output <= "-----"; end case; end process; end behaviour;
-- ========== Copyright Header Begin ============================================= -- AmgPacman File: contMod8_comb.vhd -- Copyright (c) 2015 Alberto Miedes Garcés -- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. -- -- The above named program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- The above named program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with Foobar. If not, see <http://www.gnu.org/licenses/>. -- ========== Copyright Header End =============================================== ---------------------------------------------------------------------------------- -- Engineer: Alberto Miedes Garcés -- Correo: albertomg994@gmail.com -- Create Date: January 2015 -- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent) ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- ================================================================================= -- ENTITY -- ================================================================================= entity incrementadorCuenta8bits is Port ( num_in : in STD_LOGIC_VECTOR (7 downto 0); num_out : out STD_LOGIC_VECTOR (7 downto 0) ); end incrementadorCuenta8bits; -- ================================================================================= -- ARCHITECTURE -- ================================================================================= architecture rtl of incrementadorCuenta8bits is ----------------------------------------------------------------------------- -- Declaracion de senales ----------------------------------------------------------------------------- signal aux: std_logic_vector(6 downto 0); ----------------------------------------------------------------------------- -- Componentes ----------------------------------------------------------------------------- COMPONENT adder1bit_comb PORT( A : IN std_logic; B : IN std_logic; Cin : IN std_logic; Z : OUT std_logic; Cout : OUT std_logic ); END COMPONENT; COMPONENT adder1bit_noCout PORT( A : IN std_logic; B : IN std_logic; Cin : IN std_logic; Z : OUT std_logic ); END COMPONENT; begin ----------------------------------------------------------------------------- -- Conexion de componentes ----------------------------------------------------------------------------- adder_0: adder1bit_comb port map( A => num_in(0), B => '1', Cin => '0', Z => num_out(0), Cout => aux(0) ); adder_1: adder1bit_comb port map( A => num_in(1), B => aux(0), Cin => '0', Z => num_out(1), Cout => aux(1) ); adder_2: adder1bit_comb port map( A => num_in(2), B => aux(1), Cin => '0', Z => num_out(2), Cout => aux(2) ); adder_3: adder1bit_comb port map( A => num_in(3), B => aux(2), Cin => '0', Z => num_out(3), Cout => aux(3) ); adder_4: adder1bit_comb port map( A => num_in(4), B => aux(3), Cin => '0', Z => num_out(4), Cout => aux(4) ); adder_5: adder1bit_comb port map( A => num_in(5), B => aux(4), Cin => '0', Z => num_out(5), Cout => aux(5) ); adder_6: adder1bit_comb port map( A => num_in(6), B => aux(5), Cin => '0', Z => num_out(6), Cout => aux(6) ); adder_7: adder1bit_noCout PORT MAP( A => num_in(7), B => aux(6), Cin => '0', Z => num_out(7) ); end rtl;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 21:44:52 11/11/2017 -- Design Name: -- Module Name: Union - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Union is Port ( Clk : in STD_LOGIC; reset : in STD_LOGIC; Salidaunion :out STD_LOGIC_VECTOR(31 downto 0) ); end Union; architecture Behavioral of Union is COMPONENT fetch PORT( Clk : in STD_LOGIC; Reset : in STD_LOGIC; CUentrada : in STD_LOGIC_VECTOR(1 downto 0); Entradain : in STD_LOGIC_VECTOR (31 downto 0); Instruccionout : out STD_LOGIC_VECTOR (31 downto 0); PCout : out STD_LOGIC_VECTOR (31 downto 0) ); END COMPONENT; COMPONENT Barra1 PORT( Clk : in STD_LOGIC; Reset : in STD_LOGIC; instrutin : in STD_LOGIC_VECTOR (31 downto 0); PCin : in STD_LOGIC_VECTOR (31 downto 0); instrutout : out STD_LOGIC_VECTOR (31 downto 0); PCout : out STD_LOGIC_VECTOR (31 downto 0) ); END COMPONENT; COMPONENT Decode PORT( Instruction : in STD_LOGIC_VECTOR (31 downto 0); posicionin : in STD_LOGIC_VECTOR (31 downto 0); Regtomemin : in STD_LOGIC_VECTOR (31 downto 0); cwpin : in STD_LOGIC; iccin : in STD_LOGIC_VECTOR (3 downto 0); Resetext : in STD_LOGIC; ncwpout : out STD_LOGIC; callout : out STD_LOGIC_VECTOR (31 downto 0); ifout : out STD_LOGIC_VECTOR (31 downto 0); rfsourceout : out STD_LOGIC_VECTOR (1 downto 0); wrenmen : out STD_LOGIC; pcsource : out STD_LOGIC_VECTOR (1 downto 0); Cuentrada : out STD_LOGIC_VECTOR (1 downto 0); aluop : out STD_LOGIC_VECTOR (5 downto 0); a18 : out STD_LOGIC_VECTOR (31 downto 0); crs1out : out STD_LOGIC_VECTOR (31 downto 0); RD : in STD_LOGIC_VECTOR (5 downto 0); RDout : out STD_LOGIC_VECTOR (5 downto 0); op2out : out STD_LOGIC_VECTOR (31 downto 0) ); END COMPONENT; COMPONENT Barra2 PORT( Clk : in STD_LOGIC; Reset : in STD_LOGIC; ncwpin : in STD_LOGIC; callin : in STD_LOGIC_VECTOR (31 downto 0); ifin : in STD_LOGIC_VECTOR (31 downto 0); rfsourcein : in STD_LOGIC_VECTOR (1 downto 0); wrenmenin : in STD_LOGIC; pcsourcein : in STD_LOGIC_VECTOR (1 downto 0); aluopin : in STD_LOGIC_VECTOR (5 downto 0); a18in : in STD_LOGIC_VECTOR (31 downto 0); crs1outin : in STD_LOGIC_VECTOR (31 downto 0); op2outin : in STD_LOGIC_VECTOR (31 downto 0); PCC : in STD_LOGIC_VECTOR (31 downto 0); PCCout : out STD_LOGIC_VECTOR (31 downto 0); RD : in STD_LOGIC_VECTOR (5 downto 0); RDout : out STD_LOGIC_VECTOR (5 downto 0); Cuentradain : in STD_LOGIC_VECTOR (1 downto 0); Cuentradaout : out STD_LOGIC_VECTOR (1 downto 0); ncwpout : out STD_LOGIC; callout : out STD_LOGIC_VECTOR (31 downto 0); ifout : out STD_LOGIC_VECTOR (31 downto 0); rfsourceout : out STD_LOGIC_VECTOR (1 downto 0); wrenmen : out STD_LOGIC; pcsource : out STD_LOGIC_VECTOR (1 downto 0); aluop : out STD_LOGIC_VECTOR (5 downto 0); a18 : out STD_LOGIC_VECTOR (31 downto 0); crs1out : out STD_LOGIC_VECTOR (31 downto 0); op2out : out STD_LOGIC_VECTOR (31 downto 0) ); END COMPONENT; COMPONENT Execute PORT( callin : in STD_LOGIC_VECTOR (31 downto 0); ifin : in STD_LOGIC_VECTOR (31 downto 0); pcsourcein : in STD_LOGIC_VECTOR (1 downto 0); aluopin : in STD_LOGIC_VECTOR (5 downto 0); op1in : in STD_LOGIC_VECTOR (31 downto 0); op2in : in STD_LOGIC_VECTOR (31 downto 0); cwp : out STD_LOGIC; ncwp : in STD_LOGIC; icc : out STD_LOGIC_VECTOR (3 downto 0); nextpc : out STD_LOGIC_VECTOR (31 downto 0); aluresult : out STD_LOGIC_VECTOR (31 downto 0); Clkinext : in STD_LOGIC; Resetext : in STD_LOGIC ); END COMPONENT; COMPONENT Barra3 PORT( Clk : in STD_LOGIC; Reset : in STD_LOGIC; a18in : in STD_LOGIC_VECTOR (31 downto 0); aluresultin : in STD_LOGIC_VECTOR (31 downto 0); wrenmenin : in STD_LOGIC; PCCin : in STD_LOGIC_VECTOR (31 downto 0); PCCout : out STD_LOGIC_VECTOR (31 downto 0); RD : in STD_LOGIC_VECTOR (5 downto 0); RDout : out STD_LOGIC_VECTOR (5 downto 0); rfsource : in STD_LOGIC_VECTOR (1 downto 0); a18inout : out STD_LOGIC_VECTOR (31 downto 0); aluresultout : out STD_LOGIC_VECTOR (31 downto 0); wrenmeninout : out STD_LOGIC; rfsourceout : out STD_LOGIC_VECTOR (1 downto 0) ); END COMPONENT; COMPONENT Memory PORT( a18in : in STD_LOGIC_VECTOR (31 downto 0); aluresultin : in STD_LOGIC_VECTOR (31 downto 0); datatomenout : out STD_LOGIC_VECTOR (31 downto 0); wrenmenin : in STD_LOGIC; Resetext : in STD_LOGIC; aluresultout : out STD_LOGIC_VECTOR (31 downto 0) ); END COMPONENT; COMPONENT Barra4 PORT( Clk : in STD_LOGIC; Reset : in STD_LOGIC; datatomenin : in STD_LOGIC_VECTOR (31 downto 0); aluresultin : in STD_LOGIC_VECTOR (31 downto 0); pcin : in STD_LOGIC_VECTOR (31 downto 0); RD : in STD_LOGIC_VECTOR (5 downto 0); RDout : out STD_LOGIC_VECTOR (5 downto 0); rfsourcein : in STD_LOGIC_VECTOR (1 downto 0); rfsource : out STD_LOGIC_VECTOR (1 downto 0); datatomenout : out STD_LOGIC_VECTOR (31 downto 0); aluresultout : out STD_LOGIC_VECTOR (31 downto 0); pcout : out STD_LOGIC_VECTOR (31 downto 0) ); END COMPONENT; COMPONENT Writeback PORT( datatomenin : in STD_LOGIC_VECTOR (31 downto 0); aluresultin : in STD_LOGIC_VECTOR (31 downto 0); pc : in STD_LOGIC_VECTOR (31 downto 0); rfsourcein : in STD_LOGIC_VECTOR (1 downto 0); datatoreg : out STD_LOGIC_VECTOR (31 downto 0) ); END COMPONENT; signal a1,a2,a5,a9,a10,a18n,a16,a17,a20,a21,a22,a23,a60: std_logic_vector(31 downto 0); signal a4,a13,a15, a117,a118,a130,a139,a140a,a555: std_logic_vector(1 downto 0); signal a8: std_logic_vector(3 downto 0); signal a11,a126,a183,a184,a185,a186: std_logic_vector(5 downto 0); signal a6,a7,a14,a115,a116,a129: std_logic; signal a111,a112,a120,a121,a122,a123,a124,a125,a127,a128: std_logic_vector(31 downto 0); signal a131,a132,a133,a138,a160,a180,a181,a182,a191,a668: std_logic_vector(31 downto 0); begin ints_fetch: fetch PORT MAP( Clk =>Clk, Reset =>reset, CUentrada =>a555, Entradain =>a60, Instruccionout =>a2, PCout =>a1 ); ints_barra1: Barra1 PORT MAP( Clk =>Clk, Reset =>reset, instrutin =>a2, PCin =>a1, instrutout =>a112, PCout =>a111 ); ints_decode: Decode PORT MAP( Instruction =>a112, posicionin =>a111, Regtomemin =>a23, cwpin =>a6, iccin =>a8, Resetext =>reset, ncwpout =>a7, callout =>a17, ifout =>a16, rfsourceout =>a15, wrenmen =>a14, pcsource =>a13, Cuentrada =>a4, aluop =>a11, a18 =>a18n, crs1out =>a10, RD =>a186, RDout =>a183, op2out =>a9 ); ints_barra2: Barra2 PORT MAP( Clk =>Clk, Reset =>reset, ncwpin =>a7, callin =>a17, ifin =>a16, rfsourcein =>a15, wrenmenin =>a14, pcsourcein =>a13, aluopin =>a11, a18in =>a18n, crs1outin =>a10, op2outin =>a9, PCC =>a111, PCCout =>a180, RD =>a183, RDout =>a184, Cuentradain =>a13, Cuentradaout =>a555, ncwpout =>a115, callout =>a120, ifout =>a121, rfsourceout =>a117, wrenmen =>a116, pcsource =>a118, aluop =>a126, a18 =>a122, crs1out =>a123, op2out =>a124 ); ints_execute: Execute PORT MAP( callin =>a120, ifin =>a121, pcsourcein =>a118, aluopin =>a126, op1in =>a123, op2in =>a124, cwp =>a6, ncwp =>a7, icc =>a8, nextpc =>a60, aluresult =>a20, Clkinext =>Clk, Resetext =>reset ); ints_Barra3: Barra3 PORT MAP( Clk =>Clk, Reset =>reset, a18in=> a122, aluresultin =>a20, wrenmenin =>a116, rfsource =>a117, PCCin =>a180, PCCout =>a181, RD =>a184, RDout =>a185, a18inout =>a127, aluresultout =>a668, wrenmeninout =>a129, rfsourceout =>a130 ); ints_memory: Memory PORT MAP( Resetext =>reset, a18in=>a127, aluresultin =>a668, wrenmenin =>a129, datatomenout =>a21, aluresultout =>a128 ); ints_Barra4: Barra4 PORT MAP( Clk =>Clk, Reset =>reset, datatomenin =>a21, aluresultin =>a128, pcin =>a181, rfsourcein =>a130, RD =>a185, RDout =>a186, datatomenout =>a191, aluresultout =>a133, pcout=>a132, rfsource =>a139 ); ints_writeback: Writeback PORT MAP( pc =>a132, datatomenin =>a191, aluresultin =>a133, rfsourcein =>a139, datatoreg =>a23 ); Salidaunion<=a23; end Behavioral;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1575.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s10b00x00p04n01i01575ent IS END c08s10b00x00p04n01i01575ent; ARCHITECTURE c08s10b00x00p04n01i01575arch OF c08s10b00x00p04n01i01575ent IS BEGIN TESTING: PROCESS BEGIN L : for i in 1 to 10 loop next L when 5; end loop; assert FALSE report "***FAILED TEST: c08s10b00x00p04n01i01575 - The condition in a next statement has to be of type boolean" severity ERROR; wait; END PROCESS TESTING; END c08s10b00x00p04n01i01575arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1575.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s10b00x00p04n01i01575ent IS END c08s10b00x00p04n01i01575ent; ARCHITECTURE c08s10b00x00p04n01i01575arch OF c08s10b00x00p04n01i01575ent IS BEGIN TESTING: PROCESS BEGIN L : for i in 1 to 10 loop next L when 5; end loop; assert FALSE report "***FAILED TEST: c08s10b00x00p04n01i01575 - The condition in a next statement has to be of type boolean" severity ERROR; wait; END PROCESS TESTING; END c08s10b00x00p04n01i01575arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1575.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s10b00x00p04n01i01575ent IS END c08s10b00x00p04n01i01575ent; ARCHITECTURE c08s10b00x00p04n01i01575arch OF c08s10b00x00p04n01i01575ent IS BEGIN TESTING: PROCESS BEGIN L : for i in 1 to 10 loop next L when 5; end loop; assert FALSE report "***FAILED TEST: c08s10b00x00p04n01i01575 - The condition in a next statement has to be of type boolean" severity ERROR; wait; END PROCESS TESTING; END c08s10b00x00p04n01i01575arch;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity alu is Port ( clk : in STD_LOGIC; operandA : in STD_LOGIC_VECTOR (7 downto 0); operandB : in STD_LOGIC_VECTOR (7 downto 0); operatorSelect : in STD_LOGIC_VECTOR (2 downto 0); carryIn : in STD_LOGIC; carryOut : out STD_LOGIC; zeroOut : out STD_LOGIC; signOut : out STD_LOGIC; parityOut : out STD_LOGIC; auxCarryOut : out STD_LOGIC; result : out STD_LOGIC_VECTOR (7 downto 0) ); end alu; architecture Behavioral of alu is begin procloop: process (clk) variable tempResult : std_logic_vector(8 downto 0); begin --if (rising_edge(clk)) then -- not sure this needs to be clocked really if (falling_edge(clk)) then -- not sure this needs to be clocked really auxCarryOut <= '0'; carryOut <= '0'; if (operatorSelect(2 downto 1) = "00") then -- add / add with carry tempResult := std_logic_vector(signed(operandA(7) & operandA) + signed(operandB(7) & operandB)); --auxCarryOut <= (((operandA(3 downto 0) + operandB(3 downto 0)) >> 4 and 1 if ((operatorSelect(0) and carryIn) = '1') then tempResult := std_logic_vector(signed(tempResult) + 1); end if; carryOut <= tempResult(8); result <= tempResult(7 downto 0); -- auxcar = (((opra[3:0]+oprb[3:0]) >> 4) & 1'b1) ? 1'b1 : 1'b0 ; -- auxcar = (((opra[3:0]+oprb[3:0]+cin) >> 4) & 1'b1) ? 1'b1 : 1'b0; auxCarryOut <= '0'; elsif (operatorSelect(2 downto 1) = "01") then -- sub / sub with borrow tempResult := std_logic_vector(signed(operandA(7) & operandA) - signed(operandB(7) & operandB)); if ((operatorSelect(0) and carryIn) = '1') then tempResult := std_logic_vector(signed(tempResult) - 1); end if; carryOut <= tempResult(8); result <= tempResult(7 downto 0); auxCarryOut <= '0'; elsif (operatorSelect = "100") then -- and tempResult := "0" & (operandA and operandB); result <= operandA and operandB; elsif (operatorSelect = "101") then -- xor tempResult := "0" & (operandA xor operandB); result <= operandA xor operandB; elsif (operatorSelect = "110") then -- or tempResult := "0" & (operandA or operandB); result <= operandA or operandB; else -- "111" -- compare tempResult := std_logic_vector(signed(operandA(7) & operandA) - signed(operandB(7) & operandB)); carryOut <= tempResult(8); result <= operandA; --tempResult(7 downto 0); auxCarryOut <= '0'; end if; if (signed(tempResult) = 0) then zeroOut <= '1'; else zeroOut <= '0'; end if; signOut <= tempResult(7); parityOut <= not (tempResult(7) xor tempResult(6) xor tempResult(5) xor tempResult(4) xor tempResult(3) xor tempResult(2) xor tempResult(1) xor tempResult(0)); end if; end process; end Behavioral;
-- ------------------------------------------------------------- -- -- Entity Declaration for inst_t_e -- -- Generated -- by: wig -- on: Fri Jul 15 13:54:30 2005 -- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_t_e-e.vhd,v 1.2 2005/07/15 16:20:01 wig Exp $ -- $Date: 2005/07/15 16:20:01 $ -- $Log: inst_t_e-e.vhd,v $ -- Revision 1.2 2005/07/15 16:20:01 wig -- Update all testcases; still problems though -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com -- (C) 2003 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/enty -- -- -- Start of Generated Entity inst_t_e -- entity inst_t_e is -- Generics: -- No Generated Generics for Entity inst_t_e -- Generated Port Declaration: port( -- Generated Port for Entity inst_t_e macro_sig1_k1_k2 : in std_ulogic_vector(3 downto 0); macro_sig1_k1_k4 : in std_ulogic_vector(3 downto 0); macro_sig1_k3_k2 : in std_ulogic_vector(3 downto 0); macro_sig1_k3_k4 : in std_ulogic_vector(3 downto 0); macro_sig2_k1_k2 : in std_ulogic_vector(3 downto 0); macro_sig2_k1_k4 : in std_ulogic_vector(3 downto 0); macro_sig2_k3_k2 : in std_ulogic_vector(3 downto 0); macro_sig2_k3_k4 : in std_ulogic_vector(3 downto 0); macro_sig4_k1_k2 : out std_ulogic_vector(6 downto 0); macro_sig4_k1_k4 : out std_ulogic_vector(6 downto 0); macro_sig4_k3_k2 : out std_ulogic_vector(6 downto 0); macro_sig4_k3_k4 : out std_ulogic_vector(6 downto 0); macro_sign_0 : in std_ulogic_vector(3 downto 0); macro_sign_1 : in std_ulogic_vector(3 downto 0); macro_sign_2 : in std_ulogic_vector(3 downto 0); macro_sign_3 : in std_ulogic_vector(3 downto 0) -- End of Generated Port for Entity inst_t_e ); end inst_t_e; -- -- End of Generated Entity inst_t_e -- -- --!End of Entity/ies -- --------------------------------------------------------------
-- $Id: sys_tst_snhumanio_atlys.vhd 439 2011-12-16 21:56:04Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free -- Software Foundation, either version 2, or at your option any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY -- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for complete details. -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_snhumanio_atlys - syn -- Description: snhumanio tester design for atlys -- -- Dependencies: vlib/genlib/clkdivce -- bplib/bpgen/sn_humanio_demu -- tst_snhumanio -- -- Test bench: - -- -- Target Devices: generic -- Tool versions: xst 13.1; ghdl 0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri -- 2011-10-11 414 13.1 O40d xc6slx45 166 196 - 60 t 4.9 -- -- Revision History: -- Date Rev Version Comment -- 2011-10-11 414 1.0 Initial version ------------------------------------------------------------------------------ -- Usage of Atlys Switches, Buttons, LEDs: -- library ieee; use ieee.std_logic_1164.all; use work.slvtypes.all; use work.genlib.all; use work.bpgenlib.all; use work.sys_conf.all; -- ---------------------------------------------------------------------------- entity sys_tst_snhumanio_atlys is -- top level -- implements atlys_aif port ( I_CLK100 : in slbit; -- 100 MHz clock -- O_CLKSYS : out slbit; -- DCM derived system clock I_USB_RXD : in slbit; -- USB UART receive data (board view) O_USB_TXD : out slbit; -- USB UART transmit data (board view) I_HIO_SWI : in slv8; -- atlys hio switches I_HIO_BTN : in slv6; -- atlys hio buttons O_HIO_LED: out slv8; -- atlys hio leds O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n I_FUSP_RXD : in slbit; -- fusp: rs232 rx O_FUSP_TXD : out slbit -- fusp: rs232 tx ); end sys_tst_snhumanio_atlys; architecture syn of sys_tst_snhumanio_atlys is signal CLK : slbit := '0'; signal SWI : slv8 := (others=>'0'); signal BTN : slv4 := (others=>'0'); signal LED : slv8 := (others=>'0'); signal DSP_DAT : slv16 := (others=>'0'); signal DSP_DP : slv4 := (others=>'0'); signal RESET : slbit := '0'; signal CE_MSEC : slbit := '0'; begin RESET <= '0'; -- so far not used CLK <= I_CLK100; CLKDIV : clkdivce generic map ( CDUWIDTH => 7, USECDIV => 100, MSECDIV => 1000) port map ( CLK => CLK, CE_USEC => open, CE_MSEC => CE_MSEC ); HIO : sn_humanio_demu generic map ( DEBOUNCE => sys_conf_hio_debounce) port map ( CLK => CLK, RESET => RESET, CE_MSEC => CE_MSEC, SWI => SWI, BTN => BTN, LED => LED, DSP_DAT => DSP_DAT, DSP_DP => DSP_DP, I_SWI => I_HIO_SWI, I_BTN => I_HIO_BTN, O_LED => O_HIO_LED ); HIOTEST : entity work.tst_snhumanio generic map ( BWIDTH => 4) port map ( CLK => CLK, RESET => RESET, CE_MSEC => CE_MSEC, SWI => SWI, BTN => BTN, LED => LED, DSP_DAT => DSP_DAT, DSP_DP => DSP_DP ); O_USB_TXD <= I_USB_RXD; O_FUSP_TXD <= I_FUSP_RXD; O_FUSP_RTS_N <= I_FUSP_CTS_N; end syn;
-- $Id: sys_tst_snhumanio_atlys.vhd 439 2011-12-16 21:56:04Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free -- Software Foundation, either version 2, or at your option any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY -- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for complete details. -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_snhumanio_atlys - syn -- Description: snhumanio tester design for atlys -- -- Dependencies: vlib/genlib/clkdivce -- bplib/bpgen/sn_humanio_demu -- tst_snhumanio -- -- Test bench: - -- -- Target Devices: generic -- Tool versions: xst 13.1; ghdl 0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri -- 2011-10-11 414 13.1 O40d xc6slx45 166 196 - 60 t 4.9 -- -- Revision History: -- Date Rev Version Comment -- 2011-10-11 414 1.0 Initial version ------------------------------------------------------------------------------ -- Usage of Atlys Switches, Buttons, LEDs: -- library ieee; use ieee.std_logic_1164.all; use work.slvtypes.all; use work.genlib.all; use work.bpgenlib.all; use work.sys_conf.all; -- ---------------------------------------------------------------------------- entity sys_tst_snhumanio_atlys is -- top level -- implements atlys_aif port ( I_CLK100 : in slbit; -- 100 MHz clock -- O_CLKSYS : out slbit; -- DCM derived system clock I_USB_RXD : in slbit; -- USB UART receive data (board view) O_USB_TXD : out slbit; -- USB UART transmit data (board view) I_HIO_SWI : in slv8; -- atlys hio switches I_HIO_BTN : in slv6; -- atlys hio buttons O_HIO_LED: out slv8; -- atlys hio leds O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n I_FUSP_RXD : in slbit; -- fusp: rs232 rx O_FUSP_TXD : out slbit -- fusp: rs232 tx ); end sys_tst_snhumanio_atlys; architecture syn of sys_tst_snhumanio_atlys is signal CLK : slbit := '0'; signal SWI : slv8 := (others=>'0'); signal BTN : slv4 := (others=>'0'); signal LED : slv8 := (others=>'0'); signal DSP_DAT : slv16 := (others=>'0'); signal DSP_DP : slv4 := (others=>'0'); signal RESET : slbit := '0'; signal CE_MSEC : slbit := '0'; begin RESET <= '0'; -- so far not used CLK <= I_CLK100; CLKDIV : clkdivce generic map ( CDUWIDTH => 7, USECDIV => 100, MSECDIV => 1000) port map ( CLK => CLK, CE_USEC => open, CE_MSEC => CE_MSEC ); HIO : sn_humanio_demu generic map ( DEBOUNCE => sys_conf_hio_debounce) port map ( CLK => CLK, RESET => RESET, CE_MSEC => CE_MSEC, SWI => SWI, BTN => BTN, LED => LED, DSP_DAT => DSP_DAT, DSP_DP => DSP_DP, I_SWI => I_HIO_SWI, I_BTN => I_HIO_BTN, O_LED => O_HIO_LED ); HIOTEST : entity work.tst_snhumanio generic map ( BWIDTH => 4) port map ( CLK => CLK, RESET => RESET, CE_MSEC => CE_MSEC, SWI => SWI, BTN => BTN, LED => LED, DSP_DAT => DSP_DAT, DSP_DP => DSP_DP ); O_USB_TXD <= I_USB_RXD; O_FUSP_TXD <= I_FUSP_RXD; O_FUSP_RTS_N <= I_FUSP_CTS_N; end syn;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.mem_bus_pkg.all; entity cpu_part_1541 is generic ( g_tag : std_logic_vector(7 downto 0) := X"02"; g_ram_base : unsigned(27 downto 0) := X"0060000" ); port ( clock : in std_logic; falling : in std_logic; rising : in std_logic; reset : in std_logic; -- serial bus pins atn_o : out std_logic; -- open drain atn_i : in std_logic; clk_o : out std_logic; -- open drain clk_i : in std_logic; data_o : out std_logic; -- open drain data_i : in std_logic; -- memory interface mem_req : out t_mem_req; mem_resp : in t_mem_resp; mem_busy : out std_logic; -- Debug port debug_data : out std_logic_vector(31 downto 0); debug_valid : out std_logic; -- configuration bank_is_ram : in std_logic_vector(7 downto 1); -- Parallel cable pins via1_port_a_o : out std_logic_vector(7 downto 0); via1_port_a_i : in std_logic_vector(7 downto 0); via1_port_a_t : out std_logic_vector(7 downto 0); via1_ca2_o : out std_logic; via1_ca2_i : in std_logic; via1_ca2_t : out std_logic; via1_cb1_o : out std_logic; via1_cb1_i : in std_logic; via1_cb1_t : out std_logic; -- drive pins power : in std_logic; drive_address : in std_logic_vector(1 downto 0); motor_on : out std_logic; mode : out std_logic; write_prot_n : in std_logic; step : out std_logic_vector(1 downto 0); rate_ctrl : out std_logic_vector(1 downto 0); byte_ready : in std_logic; sync : in std_logic; drv_rdata : in std_logic_vector(7 downto 0); drv_wdata : out std_logic_vector(7 downto 0); act_led : out std_logic ); end cpu_part_1541; architecture structural of cpu_part_1541 is signal soe : std_logic; signal so_n : std_logic; signal bank_is_ram_i : std_logic_vector(7 downto 0); signal cpu_write : std_logic; signal cpu_wdata : std_logic_vector(7 downto 0); signal cpu_rdata : std_logic_vector(7 downto 0); signal cpu_addr : std_logic_vector(16 downto 0); signal cpu_irqn : std_logic; signal ext_rdata : std_logic_vector(7 downto 0) := X"00"; signal io_rdata : std_logic_vector(7 downto 0); signal via1_data : std_logic_vector(7 downto 0); signal via2_data : std_logic_vector(7 downto 0); signal via1_wen : std_logic; signal via1_ren : std_logic; signal via2_wen : std_logic; signal via2_ren : std_logic; signal via1_port_b_o : std_logic_vector(7 downto 0); signal via1_port_b_t : std_logic_vector(7 downto 0); signal via1_port_b_i : std_logic_vector(7 downto 0); signal via1_ca1 : std_logic; signal via1_cb2_o : std_logic; signal via1_cb2_i : std_logic; signal via1_cb2_t : std_logic; signal via1_irq : std_logic; signal via2_port_b_o : std_logic_vector(7 downto 0); signal via2_port_b_t : std_logic_vector(7 downto 0); signal via2_port_b_i : std_logic_vector(7 downto 0); signal via2_ca2_o : std_logic; signal via2_ca2_i : std_logic; signal via2_ca2_t : std_logic; signal via2_cb1_o : std_logic; signal via2_cb1_i : std_logic; signal via2_cb1_t : std_logic; signal via2_cb2_o : std_logic; signal via2_cb2_i : std_logic; signal via2_cb2_t : std_logic; signal via2_irq : std_logic; signal io_select : std_logic; signal cpu_clk_en : std_logic; signal cpu_rising : std_logic; type t_mem_state is (idle, newcycle, extcycle); signal mem_state : t_mem_state; -- "old" style signals signal mem_request : std_logic; signal mem_addr : unsigned(25 downto 0); signal mem_rwn : std_logic; signal mem_rack : std_logic; signal mem_dack : std_logic; signal mem_wdata : std_logic_vector(7 downto 0); begin mem_req.request <= mem_request; mem_req.address <= mem_addr; mem_req.read_writen <= mem_rwn; mem_req.data <= mem_wdata; mem_req.tag <= g_tag; mem_req.size <= "00"; -- 1 byte at a time mem_rack <= '1' when mem_resp.rack_tag = g_tag else '0'; mem_dack <= '1' when mem_resp.dack_tag = g_tag else '0'; cpu: entity work.cpu6502(cycle_exact) port map ( cpu_clk => clock, cpu_clk_en => cpu_clk_en, cpu_reset => reset, cpu_write => cpu_write, cpu_wdata => cpu_wdata, cpu_rdata => cpu_rdata, cpu_addr => cpu_addr, --cpu_pc => cpu_pc, IRQn => cpu_irqn, -- IRQ interrupt (level sensitive) NMIn => '1', SOn => so_n ); -- Generate an output stream to debug internal operation of 1541 CPU process(clock) begin if rising_edge(clock) then debug_valid <= '0'; if cpu_clk_en = '1' then debug_data <= '0' & atn_i & data_i & clk_i & sync & so_n & cpu_irqn & not cpu_write & cpu_rdata & cpu_addr(15 downto 0); debug_valid <= '1'; if cpu_write = '1' then debug_data(23 downto 16) <= cpu_wdata; end if; end if; end if; end process; via1: entity work.via6522 port map ( clock => clock, falling => cpu_clk_en, rising => cpu_rising, reset => reset, addr => cpu_addr(3 downto 0), wen => via1_wen, ren => via1_ren, data_in => cpu_wdata, data_out => via1_data, -- pio -- port_a_o => via1_port_a_o, port_a_t => via1_port_a_t, port_a_i => via1_port_a_i, port_b_o => via1_port_b_o, port_b_t => via1_port_b_t, port_b_i => via1_port_b_i, -- handshake pins ca1_i => via1_ca1, ca2_o => via1_ca2_o, ca2_i => via1_ca2_i, ca2_t => via1_ca2_t, cb1_o => via1_cb1_o, cb1_i => via1_cb1_i, cb1_t => via1_cb1_t, cb2_o => via1_cb2_o, cb2_i => via1_cb2_i, cb2_t => via1_cb2_t, irq => via1_irq ); via2: entity work.via6522 port map ( clock => clock, falling => cpu_clk_en, rising => cpu_rising, reset => reset, addr => cpu_addr(3 downto 0), wen => via2_wen, ren => via2_ren, data_in => cpu_wdata, data_out => via2_data, -- pio -- port_a_o => drv_wdata, port_a_t => open, port_a_i => drv_rdata, port_b_o => via2_port_b_o, port_b_t => via2_port_b_t, port_b_i => via2_port_b_i, -- handshake pins ca1_i => so_n, ca2_o => via2_ca2_o, ca2_i => via2_ca2_i, ca2_t => via2_ca2_t, cb1_o => via2_cb1_o, cb1_i => via2_cb1_i, cb1_t => via2_cb1_t, cb2_o => via2_cb2_o, cb2_i => via2_cb2_i, cb2_t => via2_cb2_t, irq => via2_irq ); cpu_irqn <= not(via1_irq or via2_irq); cpu_clk_en <= falling; cpu_rising <= rising; mem_busy <= '0' when mem_state = idle else '1'; bank_is_ram_i <= bank_is_ram & '0'; -- Fetch ROM byte process(clock) begin if rising_edge(clock) then mem_addr(25 downto 16) <= g_ram_base(25 downto 16); case mem_state is when idle => if cpu_clk_en = '1' then mem_state <= newcycle; end if; when newcycle => -- we have a new address now mem_addr(15 downto 0) <= unsigned(cpu_addr(15 downto 0)); io_select <= '0'; -- not active -- Start by checking whether it is an extended RAM block if bank_is_ram_i(to_integer(unsigned(cpu_addr(15 downto 13))))='1' then mem_request <= '1'; mem_state <= extcycle; elsif cpu_addr(15) = '1' then -- ROM Area, which is not overridden as RAM if cpu_write = '0' then mem_request <= '1'; mem_state <= extcycle; else -- writing to rom -> ignore mem_state <= idle; end if; -- It's not extended RAM, not ROM, so it must be internal RAM or I/O. elsif cpu_addr(12 downto 11) = "00" then -- Internal RAM mem_addr(14 downto 13) <= "00"; -- force mirroring for 2000-27FF, 4000-47FF and 6000-67FF. mem_request <= '1'; mem_state <= extcycle; else io_select <= '1'; mem_state <= idle; end if; when extcycle => if mem_rack='1' then mem_request <= '0'; if cpu_write='1' then mem_state <= idle; end if; end if; if mem_dack='1' and cpu_write='0' then -- only for reads ext_rdata <= mem_resp.data; mem_state <= idle; end if; when others => null; end case; if reset='1' then io_select <= '0'; mem_request <= '0'; mem_state <= idle; end if; end if; end process; mem_rwn <= not cpu_write; mem_wdata <= cpu_wdata; -- address decoding and data muxing with cpu_addr(12 downto 10) select io_rdata <= via1_data when "110", via2_data when "111", X"FF" when others; cpu_rdata <= io_rdata when io_select='1' else ext_rdata; via1_wen <= '1' when cpu_write='1' and io_select='1' and cpu_addr(12 downto 10)="110" else '0'; via1_ren <= '1' when cpu_write='0' and io_select='1' and cpu_addr(12 downto 10)="110" else '0'; via2_wen <= '1' when cpu_write='1' and io_select='1' and cpu_addr(12 downto 10)="111" else '0'; via2_ren <= '1' when cpu_write='0' and io_select='1' and cpu_addr(12 downto 10)="111" else '0'; -- correctly attach the VIA pins to the outside world via1_ca1 <= not atn_i; via1_cb2_i <= via1_cb2_o or not via1_cb2_t; -- Because Port B reads its own output when set to output, we do not need to consider the direction here via1_port_b_i(7) <= not atn_i; -- the following bits should read 0 when the jumper is closed (drive select = 0) or when driven low by the VIA itself via1_port_b_i(6) <= drive_address(1); -- drive select via1_port_b_i(5) <= drive_address(0); -- drive select; via1_port_b_i(4) <= '1'; -- atn a - PUP via1_port_b_i(3) <= '1'; -- clock out - PUP via1_port_b_i(2) <= not (clk_i and (not (via1_port_b_o(3) or not via1_port_b_t(3)))); via1_port_b_i(1) <= '1'; -- data out - PUP via1_port_b_i(0) <= not (data_i and (not (via1_port_b_o(1) or not via1_port_b_t(1))) and (not ((via1_port_b_o(4) or not via1_port_b_t(4)) xor (not atn_i)))); --auto_o <= not power or via1_port_b_i(4); data_o <= not power or ((not (via1_port_b_o(1) or not via1_port_b_t(1))) and (not ((via1_port_b_o(4) or not via1_port_b_t(4)) xor (not atn_i)))); clk_o <= not power or (not (via1_port_b_o(3) or not via1_port_b_t(3))); atn_o <= '1'; -- Do the same for VIA 2. Pin levels instead of output register. via2_port_b_i(7) <= sync; via2_port_b_i(6) <= '1'; --Density via2_port_b_i(5) <= '1'; --Density via2_port_b_i(4) <= write_prot_n; via2_port_b_i(3) <= '1'; -- LED via2_port_b_i(2) <= '1'; -- Motor via2_port_b_i(1) <= '1'; -- Step via2_port_b_i(0) <= '1'; -- Step via2_cb1_i <= via2_cb1_o or not via2_cb1_t; via2_cb2_i <= via2_cb2_o or not via2_cb2_t; via2_ca2_i <= via2_ca2_o or not via2_ca2_t; act_led <= not (via2_port_b_o(3) or not via2_port_b_t(3)) or not power; mode <= via2_cb2_i; step(0) <= via2_port_b_o(0) or not via2_port_b_t(0); step(1) <= via2_port_b_o(1) or not via2_port_b_t(1); motor_on <= (via2_port_b_o(2) or not via2_port_b_t(2)) and power; rate_ctrl(0) <= via2_port_b_o(5) or not via2_port_b_t(5); rate_ctrl(1) <= via2_port_b_o(6) or not via2_port_b_t(6); soe <= via2_ca2_i; so_n <= byte_ready or not soe; end structural; -- Original mapping: -- 0000-07FF RAM -- 0800-17FF open -- 1800-1BFF VIA 1 -- 1C00-1FFF VIA 2 -- 2000-27FF RAM -- 2800-37FF open -- 3800-3BFF VIA 1 -- 3C00-3FFF VIA 2 -- 4000-47FF RAM -- 4800-57FF open -- 5800-5BFF VIA 1 -- 5C00-5FFF VIA 2 -- 6000-67FF RAM -- 6800-77FF open -- 7800-7BFF VIA 1 -- 7C00-7FFF VIA 2 -- 8000-BFFF ROM image (mirror) -- C000-FFFF ROM image
--! --! \file dcr_slave_regs.vhd --! --! DCR bus slave logic for ReconOS OSIF (user_logic) --! --! Contains the bus access logic for the two register sets of the OSIF: --! --! bus2osif registers (writeable by the bus, readable by OSIF logic): --! o_bus2osif_command command register C_DCR_BASEADDR + 0x00 --! o_bus2osif_data data register C_DCR_BASEADDR + 0x01 --! o_bus2osif_done s/w-access handshake reg C_DCR_BASEADDR + 0x02 --! UNUSED C_DCR_BASEADDR + 0x03 --! --! osif2bus registers (readable by the bus, writeable by OSIF logic): --! i_osif2bus_command command register C_DCR_BASEADDR + 0x00 --! i_osif2bus_data data register C_DCR_BASEADDR + 0x01 --! i_osif2bus_datax extended data register C_DCR_BASEADDR + 0x02 --! i_osif2bus_signature hardware thread signature C_DCR_BASEADDR + 0x03 --! --! --! The i_post signal is set on a OS request which needs to be handled in --! software. --! --! \author Enno Luebbers <enno.luebbers@upb.de> --! \date 07.08.2006 -- ----------------------------------------------------------------------------- -- %%%RECONOS_COPYRIGHT_BEGIN%%% -- -- This file is part of the ReconOS project <http://www.reconos.de>. -- Copyright (c) 2008, Computer Engineering Group, University of -- Paderborn. -- -- For details regarding licensing and redistribution, see COPYING. If -- you did not receive a COPYING file as part of the distribution package -- containing this file, you can get it at http://www.reconos.de/COPYING. -- -- This software is provided "as is" without express or implied warranty, -- and with no claim as to its suitability for any particular purpose. -- The copyright owner or the contributors shall not be liable for any -- damages arising out of the use of this software. -- -- %%%RECONOS_COPYRIGHT_END%%% ----------------------------------------------------------------------------- -- -- Major changes -- 07.08.2006 Enno Luebbers File created -- 25.09.2007 Enno Luebbers added i_osif2bus_datax -- 23.11.2007 Enno Luebbers moved to DCR interface -- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.numeric_std.all; --use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; library reconos_v2_01_a; use reconos_v2_01_a.reconos_pkg.all; entity dcr_slave_regs is generic ( C_DCR_BASEADDR : std_logic_vector := "1111111111"; C_DCR_HIGHADDR : std_logic_vector := "0000000000"; C_DCR_AWIDTH : integer := 10; C_DCR_DWIDTH : integer := 32; C_NUM_REGS : integer := 8; C_ENABLE_MMU : boolean := true; C_INCLUDE_ILA : integer := 0 -- 0: no ILA, 1: ILA ); port ( clk : in std_logic; reset : in std_logic; -- high active synchronous -- DCR interface o_dcrAck : out std_logic; o_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1); i_dcrABus : in std_logic_vector(0 to C_DCR_AWIDTH-1); i_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH-1); i_dcrRead : in std_logic; i_dcrWrite : in std_logic; i_dcrICON : in std_logic_vector(35 downto 0); -- mmu diagnosis registers i_tlb_miss_count : in std_logic_vector(C_DCR_DWIDTH - 1 downto 0); i_tlb_hit_count : in std_logic_vector(C_DCR_DWIDTH - 1 downto 0); i_page_fault_count : in std_logic_vector(C_DCR_DWIDTH - 1 downto 0); -- user registers i_osif2bus_command : in std_logic_vector(0 to C_OSIF_CMD_WIDTH-1); i_osif2bus_flags : in std_logic_vector(0 to C_OSIF_FLAGS_WIDTH-1); i_osif2bus_saved_state_enc : in std_logic_vector(0 to C_OSIF_STATE_ENC_WIDTH-1); i_osif2bus_saved_step_enc : in std_logic_vector(0 to C_OSIF_STEP_ENC_WIDTH-1); i_osif2bus_data : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1); i_osif2bus_datax : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1); i_osif2bus_signature : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1); o_bus2osif_command : out std_logic_vector(0 to C_OSIF_CMD_WIDTH-1); o_bus2osif_data : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1); o_bus2osif_done : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1); -- additional user interface o_newcmd : out std_logic; i_post : in std_logic; o_busy : out std_logic --o_interrupt : out std_logic ); end dcr_slave_regs; architecture behavioral of dcr_slave_regs is -- chipscope DCR ILA component component dcr_ila port ( control : in std_logic_vector(35 downto 0); clk : in std_logic; data : in std_logic_vector(76 downto 0); trig0 : in std_logic_vector(2 downto 0) ); end component; constant C_OSIF_DCR_AWIDTH : natural := 3; type reg_select_t is ( C_SELECT_NONE, C_SELECT_COMMAND, C_SELECT_DATA, C_SELECT_DONE, C_SELECT_SIGNATURE, C_SELECT_TLB_MISS, C_SELECT_TLB_HIT, C_SELECT_PGFAULT ); -- Bus signalling helper signals signal dcrAddrHit : std_logic; signal dcrAck : std_logic; -- Bus signalling helper signals signal ip2bus_data : std_logic_vector(0 to C_DCR_DWIDTH-1); signal reg_write_select : reg_select_t; signal reg_read_select : reg_select_t; -- Actual bus2osif registers signal bus2osif_command_reg : std_logic_vector(0 to C_DCR_DWIDTH-1) := (others => '0'); signal bus2osif_data_reg : std_logic_vector(0 to C_DCR_DWIDTH-1) := (others => '0'); signal bus2osif_done_reg : std_logic_vector(0 to C_DCR_DWIDTH-1) := (others => '0'); -- new command arrived signal newcmd : std_logic; -- signals indicating unread data in bus-readable registers signal osif2bus_reg_dirty : std_logic_vector(0 to 2) := "000"; -- DCR debug ILA signals signal ila_data : std_logic_vector(76 downto 0); signal ila_trig0 : std_logic_vector(2 downto 0); begin --------------------------------------------------- -- CHIPSCOPE gen_dcr_ila : if C_INCLUDE_ILA = 1 generate dcr_ila_inst : dcr_ila port map ( control => i_dcrICON, clk => clk, data => ila_data, trig0 => ila_trig0 ); -- bits 76 75 74-65 64-33 32 31-0 --ila_data <= i_dcrRead & i_dcrWrite & i_dcrABus & i_dcrDBus & dcrAck & ip2bus_data; ila_data <= i_dcrRead & i_dcrWrite & i_dcrABus & i_dcrDBus & newcmd & ip2bus_data; ila_trig0 <= i_dcrRead & i_dcrWrite & dcrAck; end generate; --------------------------------------------------- ---------------------------------------------------------------------------------------------------------- -- DCR "IPIF" ---------------------------------------------------------------------------------------------------------- -- 4 registers = 2 LSBs FIXME: hardcoded. Use log2 instead! --dcrAddrHit <= '1' when i_dcrABus(0 to C_DCR_AWIDTH-C_OSIF_DCR_AWIDTH) = C_DCR_BASEADDR(0 to C_DCR_AWIDTH-C_OSIF_DCR_AWIDTH) -- else '0'; --regAddr <= i_dcrABus(C_DCR_AWIDTH-C_OSIF_DCR_AWIDTH+1 to C_DCR_AWIDTH-1); -- -- decode read and write accesses into chip enable signals -- ASYNCHRONOUS -- ce_gen : process(dcrAddrHit, i_dcrRead, i_dcrWrite, i_dcrABus) variable tmp : reg_select_t; begin -- decode register address and set -- corresponding chip enable signal dcrAddrHit <= '1'; if i_dcrABus = C_DCR_BASEADDR + 0 then tmp := C_SELECT_COMMAND; elsif i_dcrABus = C_DCR_BASEADDR + 1 then tmp := C_SELECT_DATA; elsif i_dcrABus = C_DCR_BASEADDR + 2 then tmp := C_SELECT_DONE; elsif i_dcrABus = C_DCR_BASEADDR + 3 then tmp := C_SELECT_SIGNATURE; elsif C_ENABLE_MMU and i_dcrABus = C_DCR_BASEADDR + 4 then tmp := C_SELECT_TLB_MISS; elsif C_ENABLE_MMU and i_dcrABus = C_DCR_BASEADDR + 5 then tmp := C_SELECT_TLB_HIT; elsif C_ENABLE_MMU and i_dcrABus = C_DCR_BASEADDR + 6 then tmp := C_SELECT_PGFAULT; else tmp := C_SELECT_NONE; dcrAddrHit <= '0'; end if; if i_dcrRead = '1' then reg_read_select <= tmp; reg_write_select <= C_SELECT_NONE; elsif i_dcrWrite = '1' then reg_read_select <= C_SELECT_NONE; reg_write_select <= tmp; else reg_read_select <= C_SELECT_NONE; reg_write_select <= C_SELECT_NONE; end if; end process; -- -- generate DCR slave acknowledge signal -- SYNCHRONOUS -- gen_ack_proc : process(clk, reset) begin if reset = '1' then dcrAck <= '0'; elsif rising_edge(clk) then dcrAck <= ( i_dcrRead or i_dcrWrite ) and dcrAddrHit; end if; end process; o_dcrAck <= dcrAck; -- connect registers to outputs o_bus2osif_command <= bus2osif_command_reg(0 to C_OSIF_CMD_WIDTH-1); o_bus2osif_data <= bus2osif_data_reg; o_bus2osif_done <= bus2osif_done_reg; -- new command from OS if write_reg2 is all ones. FIXME: 0000_0001 sufficient? -- this is here to prevent incomplete command transmission if CPU uses byte accesses -- will be cleared on cycle after assertion (see slave_reg_write_proc) newcmd <= '1' when bus2osif_done_reg = X"FFFF_FFFF" else '0'; o_newcmd <= newcmd; -- we are busy as long as a pending request has not been retrieved by the CPU o_busy <= osif2bus_reg_dirty(0) or osif2bus_reg_dirty(1) or osif2bus_reg_dirty(2) or i_post; -- posting generates an interrupt -- o_interrupt <= i_post; -- drive IP to DCR Bus signals o_dcrDBus <= ip2bus_data; -- connect bus signalling --reg_write_select <= writeCE; --reg_read_select <= readCE; ------------------------------------------------------------- -- slave_reg_write_proc: implement bus write access to slave -- registers ------------------------------------------------------------- slave_reg_write_proc : process(clk) is begin if clk'event and clk = '1' then if reset = '1' then bus2osif_command_reg <= (others => '0'); bus2osif_data_reg <= (others => '0'); bus2osif_done_reg <= (others => '0'); else if dcrAck = '0' then -- register values only ONCE per write select case reg_write_select is when C_SELECT_COMMAND => bus2osif_command_reg <= i_dcrDBus; when C_SELECT_DATA => bus2osif_data_reg <= i_dcrDBus; when C_SELECT_DONE => bus2osif_done_reg <= i_dcrDBus; --when C_SELECT_SIGNATURE => null; when others => null; end case; end if; if newcmd = '1' then bus2osif_done_reg <= (others => '0'); end if; end if; end if; end process SLAVE_REG_WRITE_PROC; ------------------------------------------------------------- -- slave_reg_read_proc: implement bus read access to slave -- registers ------------------------------------------------------------- slave_reg_read_proc : process(reg_read_select, i_osif2bus_command, i_osif2bus_data, i_osif2bus_datax, i_dcrDBus, i_osif2bus_flags, i_osif2bus_saved_state_enc, i_osif2bus_saved_step_enc, i_osif2bus_signature, i_tlb_miss_count, i_tlb_hit_count, i_page_fault_count) is begin ip2bus_data <= i_dcrDBus; case reg_read_select is when C_SELECT_COMMAND => ip2bus_data <= i_osif2bus_command & i_osif2bus_flags & i_osif2bus_saved_state_enc & i_osif2bus_saved_step_enc & "000000"; when C_SELECT_DATA => ip2bus_data <= i_osif2bus_data; when C_SELECT_DONE => ip2bus_data <= i_osif2bus_datax; when C_SELECT_SIGNATURE => ip2bus_data <= i_osif2bus_signature; when C_SELECT_TLB_MISS => ip2bus_data <= i_tlb_miss_count; when C_SELECT_TLB_HIT => ip2bus_data <= i_tlb_hit_count; when C_SELECT_PGFAULT => ip2bus_data <= i_page_fault_count; when others => null; end case; end process SLAVE_REG_READ_PROC; ----------------------------------------------------------------------- -- dirty_flags: sets and clears osif2bus_reg_dirty bits -- -- This allows to block the user task in a busy state while waiting -- for OS to fetch the new commands. -- The signature register does not need to be read to clear the dirty -- flags. -- The dirty flags are (obviously) only set on software-handled requests. ----------------------------------------------------------------------- dirty_flags : process(reset, clk) --, i_post, reg_read_select) begin if reset = '1' then osif2bus_reg_dirty <= (others => '0'); -- request only pollutes the read registers, if request is to be handled by software elsif rising_edge(clk) then if i_post = '1' then osif2bus_reg_dirty <= (others => '1'); else if reg_read_select = C_SELECT_COMMAND then osif2bus_reg_dirty(0) <= '0'; end if; if reg_read_select = C_SELECT_DATA then osif2bus_reg_dirty(1) <= '0'; end if; if reg_read_select = C_SELECT_DONE then osif2bus_reg_dirty(2) <= '0'; end if; end if; end if; end process; end behavioral;
------------------------------------------------------------------------ -- -- Filename : xlslice.vhd -- -- Date : 06/05/12 -- -- Description : VHDL description of a slice block. This -- block does not use a core. -- ------------------------------------------------------------------------ ------------------------------------------------------------------------ -- -- Entity : xlslice -- -- Architecture : behavior -- -- Description : Top level VHDL description of bus slicer -- ------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity xlslice is generic ( DIN_WIDTH : integer := 32; -- Width of a Din input DIN_FROM : integer := 8; -- Din msb position to slice from DIN_TO : integer := 8); -- Din lsb position to slice to port ( Din : in std_logic_vector (DIN_WIDTH-1 downto 0); Dout : out std_logic_vector ( DIN_FROM - DIN_TO downto 0) ); end xlslice; architecture behavioral of xlslice is begin Dout <= Din(DIN_FROM downto DIN_TO); end behavioral;
------------------------------------------------------------------------ -- -- Filename : xlslice.vhd -- -- Date : 06/05/12 -- -- Description : VHDL description of a slice block. This -- block does not use a core. -- ------------------------------------------------------------------------ ------------------------------------------------------------------------ -- -- Entity : xlslice -- -- Architecture : behavior -- -- Description : Top level VHDL description of bus slicer -- ------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity xlslice is generic ( DIN_WIDTH : integer := 32; -- Width of a Din input DIN_FROM : integer := 8; -- Din msb position to slice from DIN_TO : integer := 8); -- Din lsb position to slice to port ( Din : in std_logic_vector (DIN_WIDTH-1 downto 0); Dout : out std_logic_vector ( DIN_FROM - DIN_TO downto 0) ); end xlslice; architecture behavioral of xlslice is begin Dout <= Din(DIN_FROM downto DIN_TO); end behavioral;
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================= -- ____ _ ____ _ _ _ _ -- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _ -- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | | -- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| | -- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, | -- |___/ -- ============================================================================= -- Authors: Patrick Lehmann -- -- Module: Scaler (8/16/24/32/40 bit) Device for PicoBlaze -- -- Description: -- ------------------------------------ -- TODO -- -- -- License: -- ============================================================================ -- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library PoC; use PoC.utils.all; use PoC.vectors.all; use PoC.strings.all; library L_PicoBlaze; use L_PicoBlaze.pb.all; entity pb_Scaler_Device is generic ( DEVICE_INSTANCE : T_PB_DEVICE_INSTANCE; BITS : POSITIVE ); port ( Clock : in STD_LOGIC; Reset : in STD_LOGIC; -- PicoBlaze interface Address : in T_SLV_8; WriteStrobe : in STD_LOGIC; WriteStrobe_K : in STD_LOGIC; ReadStrobe : in STD_LOGIC; DataIn : in T_SLV_8; DataOut : out T_SLV_8; Interrupt : out STD_LOGIC; Interrupt_Ack : in STD_LOGIC; Message : out T_SLV_8 ); end entity; architecture rtl of pb_Scaler_Device is constant REG_RW_A0 : STD_LOGIC_VECTOR(2 downto 0) := "000"; constant REG_RW_A1 : STD_LOGIC_VECTOR(2 downto 0) := "001"; constant REG_RW_A2 : STD_LOGIC_VECTOR(2 downto 0) := "010"; constant REG_RW_A3 : STD_LOGIC_VECTOR(2 downto 0) := "011"; constant REG_RW_A4 : STD_LOGIC_VECTOR(2 downto 0) := "100"; constant REG_WO_MULT : STD_LOGIC_VECTOR(2 downto 0) := "101"; constant REG_WO_DIV : STD_LOGIC_VECTOR(2 downto 0) := "110"; constant REG_RO_STATUS : STD_LOGIC_VECTOR(2 downto 0) := "111"; signal AdrDec_we : STD_LOGIC; signal AdrDec_re : STD_LOGIC; signal AdrDec_WriteAddress : T_SLV_8; signal AdrDec_ReadAddress : T_SLV_8; signal AdrDec_Data : T_SLV_8; constant BYTES : POSITIVE := div_ceil(BITS, 8); constant BITS_A : NATURAL := log2ceil(BYTES); signal Reg_Scaler : STD_LOGIC_VECTOR(BITS - 1 downto 0) := x"0000000000"; signal Reg_Mult : T_SLV_8 := x"00"; signal Reg_Div : T_SLV_8 := x"00"; function getVALUES return T_POSVEC is variable Result : T_POSVEC(0 to 255); begin Result(0) := 1; for i in 1 to Result'high loop Result(I) := I; end loop; return Result; end function; constant MULTS : T_POSVEC := getVALUES; constant DIVS : T_POSVEC := getVALUES; signal MultDiv_Start : STD_LOGIC; signal MultDiv_Start_d : STD_LOGIC := '0'; signal MultDiv_Done : STD_LOGIC; signal MultDiv_Done_d : STD_LOGIC := '0'; signal MultDiv_Done_re : STD_LOGIC; signal MultDiv_Result : STD_LOGIC_VECTOR(BITS - 1 downto 0); begin assert (BITS = 40) -- assert ((BITS = 8) or (BITS = 16) or (BITS = 24) or (BITS = 32) or (BITS = 40)) report "Multiplier size is not supported. Supported sizes: 8, 16, 24, 32, 40. BITS=" & INTEGER'image(BITS) severity failure; AdrDec : entity L_PicoBlaze.PicoBlaze_AddressDecoder generic map ( DEVICE_NAME => str_trim(DEVICE_INSTANCE.DeviceShort), BUS_NAME => str_trim(DEVICE_INSTANCE.BusShort), READ_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_READ), WRITE_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITE), WRITEK_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITEK) ) port map ( Clock => Clock, Reset => Reset, -- PicoBlaze interface In_WriteStrobe => WriteStrobe, In_WriteStrobe_K => WriteStrobe_K, In_ReadStrobe => ReadStrobe, In_Address => Address, In_Data => DataIn, Out_WriteStrobe => AdrDec_we, Out_ReadStrobe => AdrDec_re, Out_WriteAddress => AdrDec_WriteAddress, Out_ReadAddress => AdrDec_ReadAddress, Out_Data => AdrDec_Data ); process(Clock) begin if rising_edge(Clock) then if (Reset = '1') then Reg_Scaler <= (others => '0'); Reg_Mult <= (others => '0'); Reg_Div <= (others => '0'); else if (AdrDec_we = '1') then case AdrDec_WriteAddress(2 downto 0) IS when REG_WO_MULT => Reg_Mult <= AdrDec_Data; when REG_WO_DIV => Reg_Div <= AdrDec_Data; when REG_RW_A0 => Reg_Scaler(7 downto 0) <= AdrDec_Data; when REG_RW_A1 => Reg_Scaler(15 downto 8) <= AdrDec_Data; when REG_RW_A2 => Reg_Scaler(23 downto 16) <= AdrDec_Data; when REG_RW_A3 => Reg_Scaler(31 downto 24) <= AdrDec_Data; when REG_RW_A4 => Reg_Scaler(39 downto 32) <= AdrDec_Data; when others => null; end case; elsif (MultDiv_Done_re = '1') then Reg_Scaler <= MultDiv_Result; end if; end if; end if; end process; MultDiv_Start <= AdrDec_we and to_sl(AdrDec_WriteAddress(2 downto 0) = REG_WO_DIV); MultDiv_Start_d <= MultDiv_Start when rising_edge(Clock); MultDiv_Done_d <= MultDiv_Done when rising_edge(Clock); MultDiv_Done_re <= not MultDiv_Done_d and MultDiv_Done; MultDiv : entity PoC.arith_scaler generic map ( MULS => MULTS, -- The set of multipliers to choose from in scaling operations. DIVS => DIVS -- The set of divisors to choose from in scaling operations. ) port map ( clk => Clock, rst => Reset, start => MultDiv_Start_d, arg => Reg_Scaler, msel => Reg_Mult, dsel => Reg_Div, done => MultDiv_Done, res => MultDiv_Result ); process(AdrDec_re, AdrDec_ReadAddress, Reg_Scaler, MultDiv_Done_d) variable Reg_Scaler_slvv : T_SLVV_8(4 downto 0); begin Reg_Scaler_slvv := to_slvv_8(Reg_Scaler); DataOut <= Reg_Scaler_slvv(to_index(AdrDec_ReadAddress(2 downto 0), Reg_Scaler_slvv'length - 1)); if (AdrDec_ReadAddress(2 downto 0) = REG_RO_STATUS) then DataOut <= "0000000" & MultDiv_Done_d; end if; end process; Interrupt <= MultDiv_Done_re; Message <= x"00"; end;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA library IEEE; use IEEE.std_logic_1164.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; entity tb_lpf_dot_ltf_ztf is end tb_lpf_dot_ltf_ztf; architecture TB_lpf_dot_ltf_ztf of tb_lpf_dot_ltf_ztf is -- Component declarations -- Signal declarations terminal in_src : electrical; terminal out_dot, out_ltf, out_ztf1, out_ztf4, out_RC : electrical; begin -- Signal assignments -- Component instances vio : entity work.v_sine(ideal) generic map( freq => 100.0, amplitude => 5.0 ) port map( pos => in_src, neg => ELECTRICAL_REF ); RC1 : entity work.lowpass(RC) port map( input => in_src, output => out_RC ); dot1 : entity work.lowpass(dot) port map( input => in_src, output => out_dot ); ltf1 : entity work.lowpass(ltf) port map( input => in_src, output => out_ltf ); ztf1 : entity work.lowpass(ztf) port map( input => in_src, output => out_ztf1 ); ztf4 : entity work.lowpass(z_minus_1) port map( input => in_src, output => out_ztf4 ); end TB_lpf_dot_ltf_ztf;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA library IEEE; use IEEE.std_logic_1164.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; entity tb_lpf_dot_ltf_ztf is end tb_lpf_dot_ltf_ztf; architecture TB_lpf_dot_ltf_ztf of tb_lpf_dot_ltf_ztf is -- Component declarations -- Signal declarations terminal in_src : electrical; terminal out_dot, out_ltf, out_ztf1, out_ztf4, out_RC : electrical; begin -- Signal assignments -- Component instances vio : entity work.v_sine(ideal) generic map( freq => 100.0, amplitude => 5.0 ) port map( pos => in_src, neg => ELECTRICAL_REF ); RC1 : entity work.lowpass(RC) port map( input => in_src, output => out_RC ); dot1 : entity work.lowpass(dot) port map( input => in_src, output => out_dot ); ltf1 : entity work.lowpass(ltf) port map( input => in_src, output => out_ltf ); ztf1 : entity work.lowpass(ztf) port map( input => in_src, output => out_ztf1 ); ztf4 : entity work.lowpass(z_minus_1) port map( input => in_src, output => out_ztf4 ); end TB_lpf_dot_ltf_ztf;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA library IEEE; use IEEE.std_logic_1164.all; library IEEE_proposed; use IEEE_proposed.electrical_systems.all; entity tb_lpf_dot_ltf_ztf is end tb_lpf_dot_ltf_ztf; architecture TB_lpf_dot_ltf_ztf of tb_lpf_dot_ltf_ztf is -- Component declarations -- Signal declarations terminal in_src : electrical; terminal out_dot, out_ltf, out_ztf1, out_ztf4, out_RC : electrical; begin -- Signal assignments -- Component instances vio : entity work.v_sine(ideal) generic map( freq => 100.0, amplitude => 5.0 ) port map( pos => in_src, neg => ELECTRICAL_REF ); RC1 : entity work.lowpass(RC) port map( input => in_src, output => out_RC ); dot1 : entity work.lowpass(dot) port map( input => in_src, output => out_dot ); ltf1 : entity work.lowpass(ltf) port map( input => in_src, output => out_ltf ); ztf1 : entity work.lowpass(ztf) port map( input => in_src, output => out_ztf1 ); ztf4 : entity work.lowpass(z_minus_1) port map( input => in_src, output => out_ztf4 ); end TB_lpf_dot_ltf_ztf;
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_s2mm_sts_strm.vhd.vhd -- Description: This entity is the AXI Status Stream Interface -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1_10; use axi_dma_v7_1_10.axi_dma_pkg.all; library lib_srl_fifo_v1_0_2; library lib_cdc_v1_0_2; library lib_pkg_v1_0_2; use lib_pkg_v1_0_2.lib_pkg.all; ------------------------------------------------------------------------------- entity axi_dma_s2mm_sts_strm is generic ( C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0; -- Primary MM2S/S2MM sync/async mode -- 0 = synchronous mode - all clocks are synchronous -- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM) -- run asynchronous to AXI Lite, DMA Control, -- and SG. ----------------------------------------------------------------------- -- Scatter Gather Parameters ----------------------------------------------------------------------- C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32; -- Slave AXI Status Stream Data Width C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1; -- Enable or Disable use of Status Stream Rx Length. Only valid -- if C_SG_INCLUDE_STSCNTRL_STRM = 1 -- 0 = Don't use Rx Length -- 1 = Use Rx Length C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14; -- Descriptor Buffer Length, Transferred Bytes, and Status Stream -- Rx Length Width. Indicates the least significant valid bits of -- descriptor buffer length, transferred bytes, or Rx Length value -- in the status word coincident with tlast. C_ENABLE_SKID : integer range 0 to 1 := 0; C_FAMILY : string := "virtex5" -- Target FPGA Device Family ); port ( m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- axi_prmry_aclk : in std_logic ; -- p_reset_n : in std_logic ; -- -- s2mm_stop : in std_logic ; -- -- s2mm_rxlength_valid : out std_logic ; -- s2mm_rxlength_clr : in std_logic ; -- s2mm_rxlength : out std_logic_vector -- (C_SG_LENGTH_WIDTH - 1 downto 0) ; -- -- stsstrm_fifo_rden : in std_logic ; -- stsstrm_fifo_empty : out std_logic ; -- stsstrm_fifo_dout : out std_logic_vector -- (C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0); -- -- -- Stream to Memory Map Status Stream Interface -- s_axis_s2mm_sts_tdata : in std_logic_vector -- (C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- s_axis_s2mm_sts_tkeep : in std_logic_vector -- ((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0); -- s_axis_s2mm_sts_tvalid : in std_logic ; -- s_axis_s2mm_sts_tready : out std_logic ; -- s_axis_s2mm_sts_tlast : in std_logic -- ); end axi_dma_s2mm_sts_strm; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_s2mm_sts_strm is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- Status Stream FIFO Depth constant STSSTRM_FIFO_DEPTH : integer := 16; -- Status Stream FIFO Data Count Width (Unsused) constant STSSTRM_FIFO_CNT_WIDTH : integer := clog2(STSSTRM_FIFO_DEPTH+1); constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal fifo_full : std_logic := '0'; signal fifo_din : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0'); signal fifo_wren : std_logic := '0'; signal fifo_sinit : std_logic := '0'; signal rxlength_cdc_from : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal rxlength_valid_cdc_from : std_logic := '0'; signal rxlength_valid_trdy : std_logic := '0'; --signal sts_tvalid_re : std_logic := '0';-- CR565502 --signal sts_tvalid_d1 : std_logic := '0';-- CR565502 signal sts_tvalid : std_logic := '0'; signal sts_tready : std_logic := '0'; signal sts_tdata : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0'); signal sts_tkeep : std_logic_vector((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sts_tlast : std_logic := '0'; signal m_tvalid : std_logic := '0'; signal m_tready : std_logic := '0'; signal m_tdata : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0'); signal m_tkeep : std_logic_vector((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal m_tlast : std_logic := '0'; signal tag_stripped : std_logic := '0'; signal mask_tag_write : std_logic := '0'; --signal mask_tag_hold : std_logic := '0';-- CR565502 signal skid_rst : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin -- Primary Clock is synchronous to Secondary Clock therfore -- instantiate a sync fifo. GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate signal s2mm_stop_d1 : std_logic := '0'; signal s2mm_stop_re : std_logic := '0'; signal sts_rden : std_logic := '0'; signal follower_empty : std_logic := '0'; signal fifo_empty : std_logic := '0'; signal fifo_out : std_logic_vector (C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0'); begin -- Generate Synchronous FIFO -- I_STSSTRM_FIFO : entity lib_srl_fifo_v1_0_2.sync_fifo_fg -- generic map ( -- C_FAMILY => C_FAMILY , -- C_MEMORY_TYPE => USE_LOGIC_FIFOS, -- C_WRITE_DATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1, -- C_WRITE_DEPTH => STSSTRM_FIFO_DEPTH , -- C_READ_DATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1, -- C_READ_DEPTH => STSSTRM_FIFO_DEPTH , -- C_PORTS_DIFFER => 0, -- C_HAS_DCOUNT => 1, --req for proper fifo operation -- C_DCOUNT_WIDTH => STSSTRM_FIFO_CNT_WIDTH, -- C_HAS_ALMOST_FULL => 0, -- C_HAS_RD_ACK => 0, -- C_HAS_RD_ERR => 0, -- C_HAS_WR_ACK => 0, -- C_HAS_WR_ERR => 0, -- C_RD_ACK_LOW => 0, -- C_RD_ERR_LOW => 0, -- C_WR_ACK_LOW => 0, -- C_WR_ERR_LOW => 0, -- C_PRELOAD_REGS => 1,-- 1 = first word fall through -- C_PRELOAD_LATENCY => 0 -- 0 = first word fall through -- -- C_USE_EMBEDDED_REG => 1 -- 0 ; -- ) -- port map ( -- -- Clk => m_axi_sg_aclk , -- Sinit => fifo_sinit , -- Din => fifo_din , -- Wr_en => fifo_wren , -- Rd_en => stsstrm_fifo_rden , -- Dout => stsstrm_fifo_dout , -- Full => fifo_full , -- Empty => stsstrm_fifo_empty , -- Almost_full => open , -- Data_count => open , -- Rd_ack => open , -- Rd_err => open , -- Wr_ack => open , -- Wr_err => open -- -- ); I_UPDT_STS_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f generic map ( C_DWIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1, C_DEPTH => 16 , C_FAMILY => C_FAMILY ) port map ( Clk => m_axi_sg_aclk , Reset => fifo_sinit , FIFO_Write => fifo_wren , Data_In => fifo_din , FIFO_Read => sts_rden, --sts_queue_rden , Data_Out => fifo_out, --sts_queue_dout , FIFO_Empty => fifo_empty, --sts_queue_empty , FIFO_Full => fifo_full , Addr => open ); sts_rden <= (not fifo_empty) and follower_empty; stsstrm_fifo_empty <= follower_empty; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (fifo_sinit = '1' or stsstrm_fifo_rden = '1') then follower_empty <= '1'; elsif (sts_rden = '1') then follower_empty <= '0'; end if; end if; end process; process (m_axi_sg_aclk) begin if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then if (fifo_sinit = '1') then stsstrm_fifo_dout <= (others => '0'); elsif (sts_rden = '1') then stsstrm_fifo_dout <= fifo_out; end if; end if; end process; fifo_sinit <= not m_axi_sg_aresetn; fifo_din <= sts_tlast & sts_tdata; fifo_wren <= sts_tvalid and not fifo_full and not rxlength_valid_cdc_from and not mask_tag_write; sts_tready <= not fifo_sinit and not fifo_full and not rxlength_valid_cdc_from; -- CR565502 - particular throttle condition caused masking of tag write to not occur -- simplified logic will provide more robust handling of tag write mask -- -- Create register delay of status tvalid in order to create a -- -- rising edge pulse. note xx_re signal will hold at 1 if -- -- fifo full on rising edge of tvalid. -- REG_TVALID : process(axi_prmry_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- sts_tvalid_d1 <= '0'; -- elsif(fifo_full = '0')then -- sts_tvalid_d1 <= sts_tvalid; -- end if; -- end if; -- end process REG_TVALID; -- -- -- rising edge on tvalid used to gate off status tag from being -- -- writen into fifo. -- sts_tvalid_re <= sts_tvalid and not sts_tvalid_d1; REG_TAG_STRIPPED : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then tag_stripped <= '0'; -- Reset on write of last word elsif(fifo_wren = '1' and sts_tlast = '1')then tag_stripped <= '0'; -- Set on beginning of new status stream elsif(sts_tready = '1' and sts_tvalid = '1')then tag_stripped <= '1'; end if; end if; end process REG_TAG_STRIPPED; -- CR565502 - particular throttle condition caused masking of tag write to not occur -- simplified logic will provide more robust handling of tag write mask -- REG_MASK_TAG : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- mask_tag_hold <= '0'; -- elsif((sts_tvalid_re = '1' and tag_stripped = '0') -- or (fifo_wren = '1' and sts_tlast = '1'))then -- mask_tag_hold <= '1'; -- elsif(tag_stripped = '1')then -- mask_tag_hold <= '0'; -- end if; -- end if; -- end process; -- -- -- Mask TAG if not already masked and rising edge of tvalid -- mask_tag_write <= not tag_stripped and (sts_tvalid_re or mask_tag_hold); mask_tag_write <= not tag_stripped and sts_tready and sts_tvalid; -- Generate logic to capture receive length when Use Receive Length is -- enabled GEN_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate begin -- Register receive length on assertion of last and valid -- Mark rxlength as valid for higher processes REG_RXLENGTH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_rxlength_clr = '1')then rxlength_cdc_from <= (others => '0'); rxlength_valid_cdc_from <= '0'; elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then rxlength_cdc_from <= sts_tdata(C_SG_LENGTH_WIDTH-1 downto 0); rxlength_valid_cdc_from <= '1'; end if; end if; end process REG_RXLENGTH; s2mm_rxlength_valid <= rxlength_valid_cdc_from; s2mm_rxlength <= rxlength_cdc_from; end generate GEN_STS_APP_LENGTH; -- Do NOT generate logic to capture receive length when option disabled GEN_NO_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate begin s2mm_rxlength_valid <= '0'; s2mm_rxlength <= (others => '0'); end generate GEN_NO_STS_APP_LENGTH; -- register stop to create re pulse REG_STOP : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0')then s2mm_stop_d1 <= '0'; else s2mm_stop_d1 <= s2mm_stop; end if; end if; end process REG_STOP; s2mm_stop_re <= s2mm_stop and not s2mm_stop_d1; skid_rst <= not m_axi_sg_aresetn; ENABLE_SKID : if C_ENABLE_SKID = 1 generate begin --------------------------------------------------------------------------- -- Buffer AXI Signals --------------------------------------------------------------------------- STS_SKID_BUF_I : entity axi_dma_v7_1_10.axi_dma_skid_buf generic map( C_WDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH ) port map( -- System Ports ACLK => m_axi_sg_aclk , ARST => skid_rst , skid_stop => s2mm_stop_re , -- Slave Side (Stream Data Input) S_VALID => s_axis_s2mm_sts_tvalid , S_READY => s_axis_s2mm_sts_tready , S_Data => s_axis_s2mm_sts_tdata , S_STRB => s_axis_s2mm_sts_tkeep , S_Last => s_axis_s2mm_sts_tlast , -- Master Side (Stream Data Output M_VALID => sts_tvalid , M_READY => sts_tready , M_Data => sts_tdata , M_STRB => sts_tkeep , M_Last => sts_tlast ); end generate ENABLE_SKID; DISABLE_SKID : if C_ENABLE_SKID = 0 generate begin sts_tvalid <= s_axis_s2mm_sts_tvalid; s_axis_s2mm_sts_tready <= sts_tready; sts_tdata <= s_axis_s2mm_sts_tdata; sts_tkeep <= s_axis_s2mm_sts_tkeep; sts_tlast <= s_axis_s2mm_sts_tlast; end generate DISABLE_SKID; end generate GEN_SYNC_FIFO; -- Primary Clock is asynchronous to Secondary Clock therfore -- instantiate an async fifo. GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate ATTRIBUTE async_reg : STRING; signal s2mm_stop_reg : std_logic := '0'; -- CR605883 signal p_s2mm_stop_d1_cdc_tig : std_logic := '0'; signal p_s2mm_stop_d2 : std_logic := '0'; signal p_s2mm_stop_d3 : std_logic := '0'; signal p_s2mm_stop_re : std_logic := '0'; --ATTRIBUTE async_reg OF p_s2mm_stop_d1_cdc_tig : SIGNAL IS "true"; --ATTRIBUTE async_reg OF p_s2mm_stop_d2 : SIGNAL IS "true"; begin -- Generate Asynchronous FIFO I_STSSTRM_FIFO : entity axi_dma_v7_1_10.axi_dma_afifo_autord generic map( C_DWIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH + 1 , -- C_DEPTH => STSSTRM_FIFO_DEPTH , -- C_CNT_WIDTH => STSSTRM_FIFO_CNT_WIDTH , C_DEPTH => 15 , C_CNT_WIDTH => 4 , C_USE_BLKMEM => USE_LOGIC_FIFOS , C_FAMILY => C_FAMILY ) port map( -- Inputs AFIFO_Ainit => fifo_sinit , AFIFO_Wr_clk => axi_prmry_aclk , AFIFO_Wr_en => fifo_wren , AFIFO_Din => fifo_din , AFIFO_Rd_clk => m_axi_sg_aclk , AFIFO_Rd_en => stsstrm_fifo_rden , AFIFO_Clr_Rd_Data_Valid => '0' , -- Outputs AFIFO_DValid => open , AFIFO_Dout => stsstrm_fifo_dout , AFIFO_Full => fifo_full , AFIFO_Empty => stsstrm_fifo_empty , AFIFO_Almost_full => open , AFIFO_Almost_empty => open , AFIFO_Wr_count => open , AFIFO_Rd_count => open , AFIFO_Corr_Rd_count => open , AFIFO_Corr_Rd_count_minus1 => open , AFIFO_Rd_ack => open ); fifo_sinit <= not p_reset_n; fifo_din <= sts_tlast & sts_tdata; fifo_wren <= sts_tvalid -- valid data and not fifo_full -- fifo has room and not rxlength_valid_trdy --rxlength_valid_cdc_from -- not holding a valid length and not mask_tag_write; -- not masking off tag word sts_tready <= not fifo_sinit and not fifo_full and not rxlength_valid_trdy; --rxlength_valid_cdc_from; -- CR565502 - particular throttle condition caused masking of tag write to not occur -- simplified logic will provide more robust handling of tag write mask -- -- Create register delay of status tvalid in order to create a -- -- rising edge pulse. note xx_re signal will hold at 1 if -- -- fifo full on rising edge of tvalid. -- REG_TVALID : process(axi_prmry_aclk) -- begin -- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- sts_tvalid_d1 <= '0'; -- elsif(fifo_full = '0')then -- sts_tvalid_d1 <= sts_tvalid; -- end if; -- end if; -- end process REG_TVALID; -- -- rising edge on tvalid used to gate off status tag from being -- -- writen into fifo. -- sts_tvalid_re <= sts_tvalid and not sts_tvalid_d1; REG_TAG_STRIPPED : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0')then tag_stripped <= '0'; -- Reset on write of last word elsif(fifo_wren = '1' and sts_tlast = '1')then tag_stripped <= '0'; -- Set on beginning of new status stream elsif(sts_tready = '1' and sts_tvalid = '1')then tag_stripped <= '1'; end if; end if; end process REG_TAG_STRIPPED; -- CR565502 - particular throttle condition caused masking of tag write to not occur -- simplified logic will provide more robust handling of tag write mask -- REG_MASK_TAG : process(axi_prmry_aclk) -- begin -- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- mask_tag_hold <= '0'; -- elsif(tag_stripped = '1')then -- mask_tag_hold <= '0'; -- -- elsif(sts_tvalid_re = '1' -- or (fifo_wren = '1' and sts_tlast = '1'))then -- mask_tag_hold <= '1'; -- end if; -- end if; -- end process; -- -- -- Mask TAG if not already masked and rising edge of tvalid -- mask_tag_write <= not tag_stripped and (sts_tvalid_re or mask_tag_hold); mask_tag_write <= not tag_stripped and sts_tready and sts_tvalid; -- Generate logic to capture receive length when Use Receive Length is -- enabled GEN_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate signal rxlength_clr_d1_cdc_tig : std_logic := '0'; signal rxlength_clr_d2 : std_logic := '0'; signal rxlength_d1_cdc_to : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal rxlength_d2 : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal rxlength_valid_d1_cdc_to : std_logic := '0'; signal rxlength_valid_d2_cdc_from : std_logic := '0'; signal rxlength_valid_d3 : std_logic := '0'; signal rxlength_valid_d4 : std_logic := '0'; signal rxlength_valid_d1_back_cdc_to, rxlength_valid_d2_back : std_logic := '0'; ATTRIBUTE async_reg : STRING; --ATTRIBUTE async_reg OF rxlength_d1_cdc_to : SIGNAL IS "true"; --ATTRIBUTE async_reg OF rxlength_d2 : SIGNAL IS "true"; --ATTRIBUTE async_reg OF rxlength_valid_d1_cdc_to : SIGNAL IS "true"; --ATTRIBUTE async_reg OF rxlength_valid_d1_back_cdc_to : SIGNAL IS "true"; --ATTRIBUTE async_reg OF rxlength_valid_d2_back : SIGNAL IS "true"; begin -- Double register from secondary clock domain to primary S2P_CLK_CROSS : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => s2mm_rxlength_clr, prmry_vect_in => (others => '0'), scndry_aclk => axi_prmry_aclk, scndry_resetn => '0', scndry_out => rxlength_clr_d2, scndry_vect_out => open ); -- S2P_CLK_CROSS : process(axi_prmry_aclk) -- begin -- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then -- if(p_reset_n = '0')then -- rxlength_clr_d1_cdc_tig <= '0'; -- rxlength_clr_d2 <= '0'; -- else -- rxlength_clr_d1_cdc_tig <= s2mm_rxlength_clr; -- rxlength_clr_d2 <= rxlength_clr_d1_cdc_tig; -- end if; -- end if; -- end process S2P_CLK_CROSS; -- Register receive length on assertion of last and valid -- Mark rxlength as valid for higher processes TRDY_RXLENGTH : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0' or rxlength_clr_d2 = '1')then rxlength_valid_trdy <= '0'; elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then rxlength_valid_trdy <= '1'; end if; end if; end process TRDY_RXLENGTH; REG_RXLENGTH : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0') then -- or rxlength_clr_d2 = '1')then rxlength_cdc_from <= (others => '0'); rxlength_valid_cdc_from <= '0'; elsif(sts_tlast = '1' and sts_tvalid = '1' and sts_tready = '1')then rxlength_cdc_from <= sts_tdata(C_SG_LENGTH_WIDTH-1 downto 0); rxlength_valid_cdc_from <= '1'; elsif (rxlength_valid_d2_back = '1') then rxlength_valid_cdc_from <= '0'; end if; end if; end process REG_RXLENGTH; SYNC_RXLENGTH : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => rxlength_valid_d2_cdc_from, prmry_vect_in => (others => '0'), scndry_aclk => axi_prmry_aclk, scndry_resetn => '0', scndry_out => rxlength_valid_d2_back, scndry_vect_out => open ); -- SYNC_RXLENGTH : process(axi_prmry_aclk) -- begin -- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then -- if(p_reset_n = '0') then -- or rxlength_clr_d2 = '1')then -- -- rxlength_valid_d1_back_cdc_to <= '0'; -- rxlength_valid_d2_back <= '0'; -- else -- rxlength_valid_d1_back_cdc_to <= rxlength_valid_d2_cdc_from; -- rxlength_valid_d2_back <= rxlength_valid_d1_back_cdc_to; -- -- end if; -- end if; -- end process SYNC_RXLENGTH; -- Double register from primary clock domain to secondary P2S_CLK_CROSS : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => rxlength_valid_cdc_from, prmry_vect_in => (others => '0'), scndry_aclk => m_axi_sg_aclk, scndry_resetn => '0', scndry_out => rxlength_valid_d2_cdc_from, scndry_vect_out => open ); P2S_CLK_CROSS2 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 0, C_VECTOR_WIDTH => C_SG_LENGTH_WIDTH, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => '0', prmry_vect_in => rxlength_cdc_from, scndry_aclk => m_axi_sg_aclk, scndry_resetn => '0', scndry_out => open, scndry_vect_out => rxlength_d2 ); P2S_CLK_CROSS1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0') then -- or s2mm_rxlength_clr = '1') then -- rxlength_d1_cdc_to <= (others => '0'); -- rxlength_d2 <= (others => '0'); -- rxlength_valid_d1_cdc_to <= '0'; -- rxlength_valid_d2_cdc_from <= '0'; rxlength_valid_d3 <= '0'; else -- rxlength_d1_cdc_to <= rxlength_cdc_from; -- rxlength_d2 <= rxlength_d1_cdc_to; -- rxlength_valid_d1_cdc_to <= rxlength_valid_cdc_from; -- rxlength_valid_d2_cdc_from <= rxlength_valid_d1_cdc_to; rxlength_valid_d3 <= rxlength_valid_d2_cdc_from; end if; end if; end process P2S_CLK_CROSS1; process (m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_rxlength_clr = '1')then rxlength_valid_d4 <= '0'; elsif (rxlength_valid_d3 = '1' and rxlength_valid_d2_cdc_from = '0') then rxlength_valid_d4 <= '1'; end if; end if; end process; s2mm_rxlength <= rxlength_d2; -- s2mm_rxlength_valid <= rxlength_valid_d2; s2mm_rxlength_valid <= rxlength_valid_d4; end generate GEN_STS_APP_LENGTH; -- Do NOT generate logic to capture receive length when option disabled GEN_NO_STS_APP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate s2mm_rxlength_valid <= '0'; s2mm_rxlength <= (others => '0'); end generate GEN_NO_STS_APP_LENGTH; -- CR605883 -- Register stop to provide pure FF output for synchronizer REG_STOP : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_stop_reg <= '0'; else s2mm_stop_reg <= s2mm_stop; end if; end if; end process REG_STOP; -- double register s2mm error into primary clock domain REG_ERR2PRMRY : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => s2mm_stop_reg, prmry_vect_in => (others => '0'), scndry_aclk => axi_prmry_aclk, scndry_resetn => '0', scndry_out => p_s2mm_stop_d2, scndry_vect_out => open ); REG_ERR2PRMRY1 : process(axi_prmry_aclk) begin if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then if(p_reset_n = '0')then -- p_s2mm_stop_d1_cdc_tig <= '0'; -- p_s2mm_stop_d2 <= '0'; p_s2mm_stop_d3 <= '0'; else --p_s2mm_stop_d1_cdc_tig <= s2mm_stop; -- CR605883 -- p_s2mm_stop_d1_cdc_tig <= s2mm_stop_reg; -- p_s2mm_stop_d2 <= p_s2mm_stop_d1_cdc_tig; p_s2mm_stop_d3 <= p_s2mm_stop_d2; end if; end if; end process REG_ERR2PRMRY1; p_s2mm_stop_re <= p_s2mm_stop_d2 and not p_s2mm_stop_d3; skid_rst <= not p_reset_n; --------------------------------------------------------------------------- -- Buffer AXI Signals --------------------------------------------------------------------------- STS_SKID_BUF_I : entity axi_dma_v7_1_10.axi_dma_skid_buf generic map( C_WDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH ) port map( -- System Ports ACLK => axi_prmry_aclk , ARST => skid_rst , skid_stop => p_s2mm_stop_re , -- Slave Side (Stream Data Input) S_VALID => s_axis_s2mm_sts_tvalid , S_READY => s_axis_s2mm_sts_tready , S_Data => s_axis_s2mm_sts_tdata , S_STRB => s_axis_s2mm_sts_tkeep , S_Last => s_axis_s2mm_sts_tlast , -- Master Side (Stream Data Output M_VALID => sts_tvalid , M_READY => sts_tready , M_Data => sts_tdata , M_STRB => sts_tkeep , M_Last => sts_tlast ); end generate GEN_ASYNC_FIFO; end implementation;
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use ieee.std_logic_unsigned.all; entity keyboard is port ( CLOCK : in std_logic; nRESET : in std_logic; CLKEN_1MHZ : in std_logic; PS2_CLK : in std_logic; PS2_DATA : in std_logic; KEYOUT : out std_logic_vector(5 downto 0); ROW : in std_logic_vector(3 downto 0); ESC_IN : in std_logic; BREAK_IN : in std_logic; SHIFT_OUT : out std_logic; CTRL_OUT : out std_logic; REPEAT_OUT : out std_logic; BREAK_OUT : out std_logic; TURBO : out std_logic_vector(1 downto 0); ESC_OUT : out std_logic); end entity; architecture rtl of keyboard is component ps2_intf is generic (filter_length : positive := 8); port( CLK : in std_logic; nRESET : in std_logic; PS2_CLK : in std_logic; PS2_DATA : in std_logic; DATA : out std_logic_vector(7 downto 0); VALID : out std_logic; error : out std_logic ); end component; signal keyb_data : std_logic_vector(7 downto 0); signal keyb_valid : std_logic; signal keyb_error : std_logic; type key_matrix is array(0 to 15) of std_logic_vector(7 downto 0); signal keys : key_matrix; signal col : unsigned(3 downto 0); signal release : std_logic; signal extended : std_logic; signal key_data : std_logic_vector(7 downto 0); signal ESC_IN1 : std_logic; signal BREAK_IN1 : std_logic; begin ps2 : ps2_intf port map ( CLOCK, nRESET, PS2_CLK, PS2_DATA, keyb_data, keyb_valid, keyb_error); process(keys, ROW) begin key_data <= keys(conv_integer(ROW(3 downto 0))); KEYOUT <= key_data(5 downto 0); end process; process(CLOCK, nRESET) begin if nRESET = '0' then release <= '0'; extended <= '0'; TURBO <= "00"; BREAK_OUT <= '1'; SHIFT_OUT <= '1'; CTRL_OUT <= '1'; REPEAT_OUT <= '1'; ESC_IN1 <= ESC_IN; BREAK_IN1 <= BREAK_IN; keys(0) <= (others => '1'); keys(1) <= (others => '1'); keys(2) <= (others => '1'); keys(3) <= (others => '1'); keys(4) <= (others => '1'); keys(5) <= (others => '1'); keys(6) <= (others => '1'); keys(7) <= (others => '1'); keys(8) <= (others => '1'); keys(9) <= (others => '1'); keys(10) <= (others => '1'); keys(11) <= (others => '1'); keys(12) <= (others => '1'); keys(13) <= (others => '1'); keys(14) <= (others => '1'); keys(15) <= (others => '1'); elsif rising_edge(CLOCK) then -- handle the escape key seperately, as it's value also depends on ESC_IN if keyb_valid = '1' and keyb_data = X"76" then keys(0)(5) <= release; elsif ESC_IN /= ESC_IN1 then keys(0)(5) <= ESC_IN; end if; ESC_IN1 <= ESC_IN; -- handle the break key seperately, as it's value also depends on BREAK_IN if keyb_valid = '1' and keyb_data = X"09" then BREAK_OUT <= release; elsif BREAK_IN /= BREAK_IN1 then BREAK_OUT <= BREAK_IN; end if; BREAK_IN1 <= BREAK_IN; if keyb_valid = '1' then if keyb_data = X"e0" then extended <= '1'; elsif keyb_data = X"f0" then release <= '1'; else release <= '0'; extended <= '0'; case keyb_data is when X"05" => TURBO <= "00"; -- F1 (1MHz) when X"06" => TURBO <= "01"; -- F2 (2MMz) when X"04" => TURBO <= "10"; -- F3 (4MHz) when X"0C" => TURBO <= "11"; -- F4 (8MHz) -- when X"09" => BREAK_OUT <= release; -- F10 (BREAK) when X"11" => REPEAT_OUT <= release; -- LEFT ALT (SHIFT LOCK) when X"12" | X"59" => if (extended = '0') then -- Ignore fake shifts SHIFT_OUT <= release; -- Left SHIFT -- Right SHIFT end if; when X"14" => CTRL_OUT <= release; -- LEFT/RIGHT CTRL (CTRL) ----------------------------------------------------- -- process matrix ----------------------------------------------------- when X"29" => keys(9)(0) <= release; -- SPACE when X"54" => keys(8)(0) <= release; -- [ when X"5D" => keys(7)(0) <= release; -- \ when X"5B" => keys(6)(0) <= release; -- ] when X"0D" => keys(5)(0) <= release; -- UP when X"58" => keys(4)(0) <= release; -- CAPS LOCK when X"74" => keys(3)(0) <= release; -- RIGHT when X"75" => keys(2)(0) <= release; -- UP when X"5A" => keys(6)(1) <= release; -- RETURN when X"69" => keys(5)(1) <= release; -- END (COPY) when X"66" => keys(4)(1) <= release; -- BACKSPACE (DELETE) when X"45" => keys(3)(1) <= release; -- 0 when X"16" => keys(2)(1) <= release; -- 1 when X"1E" => keys(1)(1) <= release; -- 2 when X"26" => keys(0)(1) <= release; -- 3 when X"25" => keys(9)(2) <= release; -- 4 when X"2E" => keys(8)(2) <= release; -- 5 when X"36" => keys(7)(2) <= release; -- 6 when X"3D" => keys(6)(2) <= release; -- 7 when X"3E" => keys(5)(2) <= release; -- 8 when X"46" => keys(4)(2) <= release; -- 9 when X"52" => keys(3)(2) <= release; -- ' full colon substitute when X"4C" => keys(2)(2) <= release; -- ; when X"41" => keys(1)(2) <= release; -- , when X"4E" => keys(0)(2) <= release; -- - when X"49" => keys(9)(3) <= release; -- . when X"4A" => keys(8)(3) <= release; -- / when X"55" => keys(7)(3) <= release; -- @ (TAB) when X"1C" => keys(6)(3) <= release; -- A when X"32" => keys(5)(3) <= release; -- B when X"21" => keys(4)(3) <= release; -- C when X"23" => keys(3)(3) <= release; -- D when X"24" => keys(2)(3) <= release; -- E when X"2B" => keys(1)(3) <= release; -- F when X"34" => keys(0)(3) <= release; -- G when X"33" => keys(9)(4) <= release; -- H when X"43" => keys(8)(4) <= release; -- I when X"3B" => keys(7)(4) <= release; -- J when X"42" => keys(6)(4) <= release; -- K when X"4B" => keys(5)(4) <= release; -- L when X"3A" => keys(4)(4) <= release; -- M when X"31" => keys(3)(4) <= release; -- N when X"44" => keys(2)(4) <= release; -- O when X"4D" => keys(1)(4) <= release; -- P when X"15" => keys(0)(4) <= release; -- Q when X"2D" => keys(9)(5) <= release; -- R when X"1B" => keys(8)(5) <= release; -- S when X"2C" => keys(7)(5) <= release; -- T when X"3C" => keys(6)(5) <= release; -- U when X"2A" => keys(5)(5) <= release; -- V when X"1D" => keys(4)(5) <= release; -- W when X"22" => keys(3)(5) <= release; -- X when X"35" => keys(2)(5) <= release; -- Y when X"1A" => keys(1)(5) <= release; -- Z -- when X"76" => keys(0)(5) <= release; -- ESCAPE when others => null; end case; end if; end if; end if; end process; ESC_OUT <= keys(0)(5); end architecture;
library ieee; use ieee.std_logic_1164.all; package work14_pkg is function f_log2_size ( A : natural) return natural; component work14_comp generic ( max_out_val : natural; sample_parm : string); port ( clk_i : in std_logic; val : out std_logic_vector(f_log2_size(max_out_val)-1 downto 0)); end component; end work14_pkg; package body work14_pkg is function f_log2_size (A : natural) return natural is begin for I in 1 to 64 loop -- Works for up to 64 bits if (2**I >= A) then return(I); end if; end loop; return(63); end function f_log2_size; end work14_pkg;
library ieee; use ieee.std_logic_1164.all; package work14_pkg is function f_log2_size ( A : natural) return natural; component work14_comp generic ( max_out_val : natural; sample_parm : string); port ( clk_i : in std_logic; val : out std_logic_vector(f_log2_size(max_out_val)-1 downto 0)); end component; end work14_pkg; package body work14_pkg is function f_log2_size (A : natural) return natural is begin for I in 1 to 64 loop -- Works for up to 64 bits if (2**I >= A) then return(I); end if; end loop; return(63); end function f_log2_size; end work14_pkg;
library ieee; use ieee.std_logic_1164.all; package work14_pkg is function f_log2_size ( A : natural) return natural; component work14_comp generic ( max_out_val : natural; sample_parm : string); port ( clk_i : in std_logic; val : out std_logic_vector(f_log2_size(max_out_val)-1 downto 0)); end component; end work14_pkg; package body work14_pkg is function f_log2_size (A : natural) return natural is begin for I in 1 to 64 loop -- Works for up to 64 bits if (2**I >= A) then return(I); end if; end loop; return(63); end function f_log2_size; end work14_pkg;
library ieee; use ieee.std_logic_1164.all; package work14_pkg is function f_log2_size ( A : natural) return natural; component work14_comp generic ( max_out_val : natural; sample_parm : string); port ( clk_i : in std_logic; val : out std_logic_vector(f_log2_size(max_out_val)-1 downto 0)); end component; end work14_pkg; package body work14_pkg is function f_log2_size (A : natural) return natural is begin for I in 1 to 64 loop -- Works for up to 64 bits if (2**I >= A) then return(I); end if; end loop; return(63); end function f_log2_size; end work14_pkg;
-- Author: Osama Gamal M. Attia -- email: ogamal [at] iastate dot edu -- Description: -- Process 2: -- Read p1 response, get start, end address -- request neighbors id from graphData library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_misc.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity process2 is port ( -- control signals clk : in std_logic; rst : in std_logic; started : in std_logic; -- Process 2 information p2_done : out std_logic; p2_busy : out std_logic; p2_count_1 : out unsigned(31 downto 0); p2_count_2 : out unsigned(31 downto 0); -- Input Graph Pointers (Represented in Custom CSR) graphData : in std_logic_vector(63 downto 0); -- Process 1 information p1_done : in std_logic; p1_count : in unsigned(31 downto 0); -- Process 1 response queue signals p1_rsp_q_rd_en : in std_logic; p1_rsp_q_rd_enb : out std_logic; p1_rsp_q_dout : in std_logic_vector(63 downto 0); p1_rsp_q_valid : in std_logic; p1_rsp_q_empty : in std_logic; -- Process 2 request queue signals p2_req_q_almost_full : in std_logic; p2_req_q_wr_en : out std_logic; p2_req_q_din : out std_logic_vector(63 downto 0) ); end entity ; -- process2 architecture arch of process2 is type state_type is (s0, s1, s2, s3); signal p2_state : state_type; signal done_out : std_logic; signal count_1 : unsigned(31 downto 0); signal count_2 : unsigned(31 downto 0); signal start_index : unsigned(31 downto 0); signal neigh_count : unsigned(30 downto 0); signal busy : std_logic; signal rd_offset : unsigned(31 downto 0); begin -- assign count signals p2_count_1 <= count_1; p2_count_2 <= count_2; -- assign p2_done signal p2_done <= done_out; --p2_done <= '1' when started = '1' and p1_done = '1' and busy = '0' and p1_count = count_1 else '0'; p2_busy <= busy; p2: process(clk, rst) begin if (rising_edge(clk)) then if (rst = '1') then p2_state <= s0; done_out <= '0'; busy <= '0'; count_1 <= (others => '0'); count_2 <= (others => '0'); start_index <= (others => '0'); neigh_count <= (others => '0'); p1_rsp_q_rd_enb <= '0'; p2_req_q_wr_en <= '0'; p2_req_q_din <= (others => '0'); else p2_req_q_din <= std_logic_vector(resize(unsigned(graphData) + 4 * start_index, 64)); if (started = '1') then case (p2_state) is -- Start: when s0 => -- If p1_rsp_q NOT empty, pop, go to s1 if (p1_rsp_q_empty = '0') then p1_rsp_q_rd_enb <= '1'; count_1 <= count_1 + 1; p2_state <= s1; -- if p1_rsp_q empty, keep waiting else p1_rsp_q_rd_enb <= '0'; p2_state <= s0; end if; -- Reset Signals p2_req_q_wr_en <= '0'; -- Request a neighbor when s1 => -- There at least one neighbor to request if (p1_rsp_q_valid = '1' and or_reduce(p1_rsp_q_dout(31 downto 1)) /= '0') then -- Save start index and neighbors count, go to s2 start_index <= unsigned(p1_rsp_q_dout(63 downto 32)); neigh_count <= unsigned(p1_rsp_q_dout(31 downto 1)); p2_state <= s2; -- Reset Signals p1_rsp_q_rd_enb <= '0'; -- No neighbors to request elsif (p1_rsp_q_valid = '1') then if (p1_rsp_q_empty = '0') then p1_rsp_q_rd_enb <= '1'; count_1 <= count_1 + 1; p2_state <= s1; else p1_rsp_q_rd_enb <= '0'; p2_state <= s0; end if; -- Data isn't ready yet, keep waiting in s1 else p2_state <= s1; -- reset signals p1_rsp_q_rd_enb <= '0'; end if; -- Reset Signals p2_req_q_wr_en <= '0'; -- Request more neighbors when s2 => -- There at least one neighbor to request if (neigh_count /= 0) then -- p2_req_q is ready, request a neighbor if (p2_req_q_almost_full = '0') then p2_req_q_wr_en <= '1'; count_2 <= count_2 + 1; start_index <= start_index + 1; neigh_count <= neigh_count - 1; p2_state <= s2; -- Reset signals p1_rsp_q_rd_enb <= '0'; -- p2_req_q is NOT ready (i.e. full) else -- Go to s2 p2_state <= s2; -- Reset Signals p1_rsp_q_rd_enb <= '0'; p2_req_q_wr_en <= '0'; end if; -- No neighbors to request else if (p1_rsp_q_empty = '0') then p1_rsp_q_rd_enb <= '1'; count_1 <= count_1 + 1; p2_state <= s1; else p1_rsp_q_rd_enb <= '0'; p2_state <= s0; end if; p2_req_q_wr_en <= '0'; end if; -- Uknown state when others => -- Reset Signals p1_rsp_q_rd_enb <= '0'; p2_req_q_wr_en <= '0'; p2_state <= s0; end case; if (p1_done = '1' and count_1 >= p1_count and p2_state = s0 and neigh_count = 0 and p1_rsp_q_valid = '0' and p1_rsp_q_empty = '1') then done_out <= '1'; else done_out <= '0'; end if; else -- reset everything p2_state <= s0; done_out <= '0'; busy <= '0'; count_1 <= (others => '0'); count_2 <= (others => '0'); start_index <= (others => '0'); neigh_count <= (others => '0'); p1_rsp_q_rd_enb <= '0'; p2_req_q_wr_en <= '0'; end if; -- end if started end if; -- end if rst end if; -- end if clk end process; -- p2 end architecture; -- arch
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2228.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b06x00p01n01i02228ent IS END c07s02b06x00p01n01i02228ent; ARCHITECTURE c07s02b06x00p01n01i02228arch OF c07s02b06x00p01n01i02228ent IS BEGIN TESTING: PROCESS variable SEVERV : SEVERITY_LEVEL := NOTE; variable k : integer; BEGIN k := SEVERV mod WARNING; assert FALSE report "***FAILED TEST: c07s02b06x00p01n01i02228 - Operators mod and rem are predefined for any integer type only." severity ERROR; wait; END PROCESS TESTING; END c07s02b06x00p01n01i02228arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2228.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b06x00p01n01i02228ent IS END c07s02b06x00p01n01i02228ent; ARCHITECTURE c07s02b06x00p01n01i02228arch OF c07s02b06x00p01n01i02228ent IS BEGIN TESTING: PROCESS variable SEVERV : SEVERITY_LEVEL := NOTE; variable k : integer; BEGIN k := SEVERV mod WARNING; assert FALSE report "***FAILED TEST: c07s02b06x00p01n01i02228 - Operators mod and rem are predefined for any integer type only." severity ERROR; wait; END PROCESS TESTING; END c07s02b06x00p01n01i02228arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2228.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b06x00p01n01i02228ent IS END c07s02b06x00p01n01i02228ent; ARCHITECTURE c07s02b06x00p01n01i02228arch OF c07s02b06x00p01n01i02228ent IS BEGIN TESTING: PROCESS variable SEVERV : SEVERITY_LEVEL := NOTE; variable k : integer; BEGIN k := SEVERV mod WARNING; assert FALSE report "***FAILED TEST: c07s02b06x00p01n01i02228 - Operators mod and rem are predefined for any integer type only." severity ERROR; wait; END PROCESS TESTING; END c07s02b06x00p01n01i02228arch;
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE IEEE.STD_LOGIC_ARITH.all; USE IEEE.STD_LOGIC_UNSIGNED.all; ENTITY clk_div IS PORT ( clock_48Mhz : IN STD_LOGIC; clock_1MHz : OUT STD_LOGIC; clock_100KHz : OUT STD_LOGIC; clock_10KHz : OUT STD_LOGIC; clock_1KHz : OUT STD_LOGIC; clock_100Hz : OUT STD_LOGIC; clock_10Hz : OUT STD_LOGIC; clock_1Hz : OUT STD_LOGIC); END clk_div; ARCHITECTURE a OF clk_div IS SIGNAL count_1Mhz: STD_LOGIC_VECTOR(6 DOWNTO 0); SIGNAL count_100Khz, count_10Khz, count_1Khz : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL count_100hz, count_10hz, count_1hz : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL clock_1Mhz_int, clock_100Khz_int, clock_10Khz_int, clock_1Khz_int: STD_LOGIC; SIGNAL clock_100hz_int, clock_10Hz_int, clock_1Hz_int : STD_LOGIC; SIGNAL clock_1Mhz_reg, clock_100Khz_reg, clock_10Khz_reg, clock_1Khz_reg: STD_LOGIC; SIGNAL clock_100hz_reg, clock_10Hz_reg, clock_1Hz_reg : STD_LOGIC; BEGIN PROCESS BEGIN clock_1Mhz <= clock_1Mhz_reg; clock_100Khz <= clock_100Khz_reg; clock_10Khz <= clock_10Khz_reg; clock_1Khz <= clock_1Khz_reg; clock_100hz <= clock_100hz_reg; clock_10hz <= clock_10hz_reg; clock_1hz <= clock_1hz_reg; -- Divide by 48 WAIT UNTIL clock_48Mhz'EVENT and clock_48Mhz = '1'; IF count_1Mhz < 47 THEN count_1Mhz <= count_1Mhz + 1; ELSE count_1Mhz <= "0000000"; END IF; IF count_1Mhz < 24 THEN clock_1Mhz_int <= '0'; ELSE clock_1Mhz_int <= '1'; END IF; -- Ripple clocks are used in this code to save prescalar hardware -- Sync all clock prescalar outputs back to master clock signal clock_1Mhz_reg <= clock_1Mhz_int; clock_100Khz_reg <= clock_100Khz_int; clock_10Khz_reg <= clock_10Khz_int; clock_1Khz_reg <= clock_1Khz_int; clock_100hz_reg <= clock_100hz_int; clock_10hz_reg <= clock_10hz_int; clock_1hz_reg <= clock_1hz_int; END PROCESS; -- Divide by 10 PROCESS BEGIN WAIT UNTIL clock_1Mhz_reg'EVENT and clock_1Mhz_reg = '1'; IF count_100Khz /= 4 THEN count_100Khz <= count_100Khz + 1; ELSE count_100khz <= "000"; clock_100Khz_int <= NOT clock_100Khz_int; END IF; END PROCESS; -- Divide by 10 PROCESS BEGIN WAIT UNTIL clock_100Khz_reg'EVENT and clock_100Khz_reg = '1'; IF count_10Khz /= 4 THEN count_10Khz <= count_10Khz + 1; ELSE count_10khz <= "000"; clock_10Khz_int <= NOT clock_10Khz_int; END IF; END PROCESS; -- Divide by 10 PROCESS BEGIN WAIT UNTIL clock_10Khz_reg'EVENT and clock_10Khz_reg = '1'; IF count_1Khz /= 4 THEN count_1Khz <= count_1Khz + 1; ELSE count_1khz <= "000"; clock_1Khz_int <= NOT clock_1Khz_int; END IF; END PROCESS; -- Divide by 10 PROCESS BEGIN WAIT UNTIL clock_1Khz_reg'EVENT and clock_1Khz_reg = '1'; IF count_100hz /= 4 THEN count_100hz <= count_100hz + 1; ELSE count_100hz <= "000"; clock_100hz_int <= NOT clock_100hz_int; END IF; END PROCESS; -- Divide by 10 PROCESS BEGIN WAIT UNTIL clock_100hz_reg'EVENT and clock_100hz_reg = '1'; IF count_10hz /= 4 THEN count_10hz <= count_10hz + 1; ELSE count_10hz <= "000"; clock_10hz_int <= NOT clock_10hz_int; END IF; END PROCESS; -- Divide by 10 PROCESS BEGIN WAIT UNTIL clock_10hz_reg'EVENT and clock_10hz_reg = '1'; IF count_1hz /= 4 THEN count_1hz <= count_1hz + 1; ELSE count_1hz <= "000"; clock_1hz_int <= NOT clock_1hz_int; END IF; END PROCESS; END a;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_15_dlx.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.dlx_types.all; entity dlx is generic ( Tpd_clk_out : delay_length; debug : dlx_debug_control := none ); port ( phi1, phi2 : in std_logic; reset : in std_logic; halt : out std_logic; a : out dlx_address; d : inout dlx_word; width : out dlx_mem_width; write_enable : out std_logic; ifetch : out std_logic; mem_enable : out std_logic; ready : in std_logic ); end entity dlx;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_15_dlx.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.dlx_types.all; entity dlx is generic ( Tpd_clk_out : delay_length; debug : dlx_debug_control := none ); port ( phi1, phi2 : in std_logic; reset : in std_logic; halt : out std_logic; a : out dlx_address; d : inout dlx_word; width : out dlx_mem_width; write_enable : out std_logic; ifetch : out std_logic; mem_enable : out std_logic; ready : in std_logic ); end entity dlx;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_15_dlx.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.dlx_types.all; entity dlx is generic ( Tpd_clk_out : delay_length; debug : dlx_debug_control := none ); port ( phi1, phi2 : in std_logic; reset : in std_logic; halt : out std_logic; a : out dlx_address; d : inout dlx_word; width : out dlx_mem_width; write_enable : out std_logic; ifetch : out std_logic; mem_enable : out std_logic; ready : in std_logic ); end entity dlx;
entity e is end entity; architecture a of e is signal a : bit; constant b : bit := '0'; begin assert FALSE report bit'image(a'subtype'left) severity NOTE; assert FALSE report bit'image(b'subtype'left) severity NOTE; assert FALSE report a'subtype'image(a) severity NOTE; assert FALSE report b'subtype'image(b) severity NOTE; end architecture;
entity e is end entity; architecture a of e is signal a : bit; constant b : bit := '0'; begin assert FALSE report bit'image(a'subtype'left) severity NOTE; assert FALSE report bit'image(b'subtype'left) severity NOTE; assert FALSE report a'subtype'image(a) severity NOTE; assert FALSE report b'subtype'image(b) severity NOTE; end architecture;
/*************************************************************************************************** / / Author: Antonio Pastor González / ¯¯¯¯¯¯ / / Date: / ¯¯¯¯ / / Version: / ¯¯¯¯¯¯¯ / / Notes: / ¯¯¯¯¯ / This design makes use of some features from VHDL-2008, all of which have been implemented by / Altera and Xilinx in their software. / A 3 space tab is used throughout the document / / Description: / ¯¯¯¯¯¯¯¯¯¯¯ / This package contains necessary types, constants, and functions for the parameterized counter / design. / **************************************************************************************************/ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.common_pkg.all; use work.common_data_types_pkg.all; /*================================================================================================*/ /*================================================================================================*/ /*================================================================================================*/ package counter_pkg is /* types and related functions 1 */ /**************************************************************************************************/ type T_count_mode is (t_up, t_down, t_input_signal); type T_overflow_behavior is (t_saturate, t_wrap); type T_target_count_behavior is (t_blocking, t_non_blocking); type T_set_reset_priority is (t_set, t_reset); function ite( cond : boolean; if_true, if_false : T_count_mode) return T_count_mode; function ite( cond : boolean; if_true, if_false : T_overflow_behavior) return T_overflow_behavior; function ite( cond : boolean; if_true, if_false : T_target_count_behavior) return T_target_count_behavior; function ite( cond : boolean; if_true, if_false : T_set_reset_priority) return T_set_reset_priority; /* function to check the consistency and correctness of generics 2 */ /**************************************************************************************************/ function counter_CHECKS ( unsigned_2comp_opt, target_mode, use_set, use_reset, use_load: boolean; target_blocking_opt : boolean_exc; target_dep, set_to_dep: integer_exc; counter_width_dep: positive_exc) return natural; /* functions for corrected generics and internal/external port signals 3 */ /**************************************************************************************************/ function counter_MWCG( unsigned_2comp_opt : boolean; target_dep : integer_exc; use_set : boolean; set_to_dep : integer_exc) return positive; function counter_CIW( unsigned_2comp_opt : boolean; counter_width_dep : positive_exc; target_mode : boolean; target_dep : integer_exc; use_set : boolean; set_to_dep : integer_exc) return positive; function counter_CW( unsigned_2comp_opt : boolean; counter_width_dep : positive_exc; target_mode : boolean; target_dep : integer_exc; target_with_count : boolean; use_set : boolean; set_to_dep : integer_exc) return natural; end package; /*================================================================================================*/ /*================================================================================================*/ /*================================================================================================*/ package body counter_pkg is /********************************************************************************************** 1 */ function ite( cond : boolean; if_true, if_false : T_count_mode) return T_count_mode is begin if cond then return(if_true); else return(if_false); end if; end function ite; function ite( cond : boolean; if_true, if_false : T_overflow_behavior) return T_overflow_behavior is begin if cond then return(if_true); else return(if_false); end if; end function ite; function ite( cond : boolean; if_true, if_false : T_target_count_behavior) return T_target_count_behavior is begin if cond then return(if_true); else return(if_false); end if; end function ite; function ite( cond : boolean; if_true, if_false : T_set_reset_priority) return T_set_reset_priority is begin if cond then return(if_true); else return(if_false); end if; end function ite; /********************************************************************************************** 2 */ function counter_CHECKS ( unsigned_2comp_opt, target_mode, use_set, use_reset, use_load: boolean; target_blocking_opt : boolean_exc; target_dep, set_to_dep: integer_exc; counter_width_dep: positive_exc) return natural is constant target : integer := integer(target_dep); constant set_to : integer := integer(set_to_dep); constant counter_width : integer := integer(counter_width_dep); variable target_min_bits : positive; variable set_to_min_bits : positive; variable counter_w : natural; begin --error: target mode but target not set assert not(target_mode and target=integer'low) report "(1) " & "ILLEGAL PARAMETERS in entity counter: in target mode (target_MODE=true) the parameter " & "target_dep must be assigned a value." severity error; --error: negative target in an unsigned counter assert not (target_mode and unsigned_2comp_opt and target<0) report "(2) " & "ILLEGAL PARAMETERS in entity counter: cannot have a negative number as the target " & "in an unsigned counter. Generic UNSIGNED_2COMP should be false." severity error; --error: negative set_to in an unsigned counter assert not (unsigned_2comp_opt and use_set and set_to<0) report "(3) " & "ILLEGAL PARAMETERS in entity counter: cannot have a negative number as the value" & " to set the counter to when set='1'. Generic UNSIGNED_2COMP should be false." severity error; counter_w := counter_CIW(unsigned_2comp_opt, counter_width_dep, target_mode, target_dep, use_set, set_to_dep); --error: COUNTER_WIDTH is not set when in normal mode assert not(not target_mode and counter_width=0) report "(4) " & "MISSING PARAMETERS in entity counter: when in normal mode (target_MODE = false) " & "the value of the generic COUNTER_WIDTH must be set." severity error; --error: SET_TO_dep is not set when USE_SET is true assert not(use_set and set_to=integer'low) report "(5) " & "MISSING PARAMETERS in entity counter: when using set (USE_SET = true) " & "the value of the generic SET_TO_dep must be set." severity error; if target_mode then target_min_bits:= min_bits(target, not unsigned_2comp_opt); else target_min_bits := 1; end if; --error: the width of the counter is not enough for target assert not(target_mode and counter_w<target_min_bits) report "(6) " & "ILLEGAL PARAMETERS in entity counter: the specified counter width (" & image(counter_w) & ") is not enough for the stated target (" & image(target_dep) & "). At least " & image(target_min_bits) & " bits are necessary." severity error; if use_set then set_to_min_bits := min_bits(set_to, not unsigned_2comp_opt); else set_to_min_bits := 1; end if; --error: the width of the counter is not enough for set_to assert not(use_set and counter_w<set_to_min_bits) report "(7) " & "ILLEGAL PARAMETERS in entity counter: the specified counter width (" & image(counter_w) & ") is not enough for the stated set_to (" & image(set_to) & "). At least " & image(set_to_min_bits) & " bits are necessary." severity error; --warning: target blocking but neither set, reset, nor load (permanent block) assert not(target_mode and target_blocking_opt=t_true and not(use_set or use_reset or use_load)) report "(11) " & "With the specified parameters, the counter module will reach a permanent block "& "once it reaches the target" severity warning; return 0; end function; /********************************************************************************************** 3 */ function counter_MWCG( unsigned_2comp_opt : boolean; target_dep : integer_exc; use_set : boolean; set_to_dep : integer_exc) return positive is begin if use_set then return maximum(min_bits(target_dep, not unsigned_2comp_opt), min_bits(set_to_dep, not unsigned_2comp_opt)); else return min_bits(target_dep, not unsigned_2comp_opt); end if; end function; function counter_CIW( unsigned_2comp_opt : boolean; counter_width_dep : positive_exc; target_mode : boolean; target_dep : integer_exc; use_set : boolean; set_to_dep : integer_exc) return positive is begin if target_mode then if counter_width_dep = 0 then return counter_MWCG(unsigned_2comp_opt, target_dep, use_set, set_to_dep); else return positive(counter_width_dep); end if; else return positive(counter_width_dep); end if; end function; function counter_CW( unsigned_2comp_opt : boolean; counter_width_dep : positive_exc; target_mode : boolean; target_dep : integer_exc; target_with_count : boolean; use_set : boolean; set_to_dep : integer_exc) return natural is begin if target_mode then if target_with_count then if counter_width_dep = 0 then return counter_MWCG(unsigned_2comp_opt, target_dep, use_set, set_to_dep); else return natural(counter_width_dep); end if; else return 0; end if; else return natural(counter_width_dep); end if; end function; end package body;
-- File: dyplo_hdl_node_user_params.vhd -- -- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED. -- -- This file contains confidential and proprietary information of -- Topic Embedded Products B.V. and is protected under Dutch and -- International copyright and other international intellectual property laws. -- -- Disclaimer -- -- This disclaimer is not a license and does not grant any rights to the -- materials distributed herewith. Except as otherwise provided in a valid -- license issued to you by Topic Embedded Products B.V., and to the maximum -- extend permitted by applicable law: -- -- 1. Dyplo is furnished on an �as is�, as available basis. Topic makes no -- warranty, express or implied, with respect to the capability of Dyplo. All -- warranties of any type, express or implied, including the warranties of -- merchantability, fitness for a particular purpose and non-infringement of -- third party rights are expressly disclaimed. -- -- 2. Topic�s maximum total liability shall be limited to general money -- damages in an amount not to exceed the total amount paid for in the year -- in which the damages have occurred. Under no circumstances including -- negligence shall Topic be liable for direct, indirect, incidental, special, -- consequential or punitive damages, or for loss of profits, revenue, or data, -- that are directly or indirectly related to the use of, or the inability to -- access and use Dyplo and related services, whether in an action in contract, -- tort, product liability, strict liability, statute or otherwise even if -- Topic has been advised of the possibility of those damages. -- -- This copyright notice and disclaimer must be retained as part of this file at all times. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package hdl_node_user_params is constant c_vendor_id : integer range 0 to 255 := 1; constant c_product_id : integer range 0 to 255 := 4; constant c_version_id : integer range 0 to 255 := 1; constant c_revision_id : integer range 0 to 255 := 1; constant c_input_streams : integer range 0 to 4 := 4; constant c_hdl_in_fifo_depth : integer range 7 to 12 := 8; -- specify power of 2. FIFO size = 2^x. 7 = 128, 12 = 4096 constant c_hdl_in_fifo_type : string := "DISTRIBUTED"; constant c_output_streams : integer range 0 to 4 := 4; end hdl_node_user_params;
-- File: dyplo_hdl_node_user_params.vhd -- -- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED. -- -- This file contains confidential and proprietary information of -- Topic Embedded Products B.V. and is protected under Dutch and -- International copyright and other international intellectual property laws. -- -- Disclaimer -- -- This disclaimer is not a license and does not grant any rights to the -- materials distributed herewith. Except as otherwise provided in a valid -- license issued to you by Topic Embedded Products B.V., and to the maximum -- extend permitted by applicable law: -- -- 1. Dyplo is furnished on an �as is�, as available basis. Topic makes no -- warranty, express or implied, with respect to the capability of Dyplo. All -- warranties of any type, express or implied, including the warranties of -- merchantability, fitness for a particular purpose and non-infringement of -- third party rights are expressly disclaimed. -- -- 2. Topic�s maximum total liability shall be limited to general money -- damages in an amount not to exceed the total amount paid for in the year -- in which the damages have occurred. Under no circumstances including -- negligence shall Topic be liable for direct, indirect, incidental, special, -- consequential or punitive damages, or for loss of profits, revenue, or data, -- that are directly or indirectly related to the use of, or the inability to -- access and use Dyplo and related services, whether in an action in contract, -- tort, product liability, strict liability, statute or otherwise even if -- Topic has been advised of the possibility of those damages. -- -- This copyright notice and disclaimer must be retained as part of this file at all times. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package hdl_node_user_params is constant c_vendor_id : integer range 0 to 255 := 1; constant c_product_id : integer range 0 to 255 := 4; constant c_version_id : integer range 0 to 255 := 1; constant c_revision_id : integer range 0 to 255 := 1; constant c_input_streams : integer range 0 to 4 := 4; constant c_hdl_in_fifo_depth : integer range 7 to 12 := 8; -- specify power of 2. FIFO size = 2^x. 7 = 128, 12 = 4096 constant c_hdl_in_fifo_type : string := "DISTRIBUTED"; constant c_output_streams : integer range 0 to 4 := 4; end hdl_node_user_params;
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:lmb_bram_if_cntlr:4.0 -- IP Revision: 6 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY lmb_bram_if_cntlr_v4_0; USE lmb_bram_if_cntlr_v4_0.lmb_bram_if_cntlr; ENTITY design_1_ilmb_bram_if_cntlr_0 IS PORT ( LMB_Clk : IN STD_LOGIC; LMB_Rst : IN STD_LOGIC; LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31); LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31); LMB_AddrStrobe : IN STD_LOGIC; LMB_ReadStrobe : IN STD_LOGIC; LMB_WriteStrobe : IN STD_LOGIC; LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3); Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31); Sl_Ready : OUT STD_LOGIC; Sl_Wait : OUT STD_LOGIC; Sl_UE : OUT STD_LOGIC; Sl_CE : OUT STD_LOGIC; BRAM_Rst_A : OUT STD_LOGIC; BRAM_Clk_A : OUT STD_LOGIC; BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31); BRAM_EN_A : OUT STD_LOGIC; BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3); BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31); BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31) ); END design_1_ilmb_bram_if_cntlr_0; ARCHITECTURE design_1_ilmb_bram_if_cntlr_0_arch OF design_1_ilmb_bram_if_cntlr_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "yes"; COMPONENT lmb_bram_if_cntlr IS GENERIC ( C_FAMILY : STRING; C_HIGHADDR : STD_LOGIC_VECTOR(0 TO 31); C_BASEADDR : STD_LOGIC_VECTOR(0 TO 31); C_NUM_LMB : INTEGER; C_MASK : STD_LOGIC_VECTOR(0 TO 31); C_MASK1 : STD_LOGIC_VECTOR(0 TO 31); C_MASK2 : STD_LOGIC_VECTOR(0 TO 31); C_MASK3 : STD_LOGIC_VECTOR(0 TO 31); C_LMB_AWIDTH : INTEGER; C_LMB_DWIDTH : INTEGER; C_ECC : INTEGER; C_INTERCONNECT : INTEGER; C_FAULT_INJECT : INTEGER; C_CE_FAILING_REGISTERS : INTEGER; C_UE_FAILING_REGISTERS : INTEGER; C_ECC_STATUS_REGISTERS : INTEGER; C_ECC_ONOFF_REGISTER : INTEGER; C_ECC_ONOFF_RESET_VALUE : INTEGER; C_CE_COUNTER_WIDTH : INTEGER; C_WRITE_ACCESS : INTEGER; C_S_AXI_CTRL_ADDR_WIDTH : INTEGER; C_S_AXI_CTRL_DATA_WIDTH : INTEGER ); PORT ( LMB_Clk : IN STD_LOGIC; LMB_Rst : IN STD_LOGIC; LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31); LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31); LMB_AddrStrobe : IN STD_LOGIC; LMB_ReadStrobe : IN STD_LOGIC; LMB_WriteStrobe : IN STD_LOGIC; LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3); Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31); Sl_Ready : OUT STD_LOGIC; Sl_Wait : OUT STD_LOGIC; Sl_UE : OUT STD_LOGIC; Sl_CE : OUT STD_LOGIC; LMB1_ABus : IN STD_LOGIC_VECTOR(0 TO 31); LMB1_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31); LMB1_AddrStrobe : IN STD_LOGIC; LMB1_ReadStrobe : IN STD_LOGIC; LMB1_WriteStrobe : IN STD_LOGIC; LMB1_BE : IN STD_LOGIC_VECTOR(0 TO 3); Sl1_DBus : OUT STD_LOGIC_VECTOR(0 TO 31); Sl1_Ready : OUT STD_LOGIC; Sl1_Wait : OUT STD_LOGIC; Sl1_UE : OUT STD_LOGIC; Sl1_CE : OUT STD_LOGIC; LMB2_ABus : IN STD_LOGIC_VECTOR(0 TO 31); LMB2_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31); LMB2_AddrStrobe : IN STD_LOGIC; LMB2_ReadStrobe : IN STD_LOGIC; LMB2_WriteStrobe : IN STD_LOGIC; LMB2_BE : IN STD_LOGIC_VECTOR(0 TO 3); Sl2_DBus : OUT STD_LOGIC_VECTOR(0 TO 31); Sl2_Ready : OUT STD_LOGIC; Sl2_Wait : OUT STD_LOGIC; Sl2_UE : OUT STD_LOGIC; Sl2_CE : OUT STD_LOGIC; LMB3_ABus : IN STD_LOGIC_VECTOR(0 TO 31); LMB3_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31); LMB3_AddrStrobe : IN STD_LOGIC; LMB3_ReadStrobe : IN STD_LOGIC; LMB3_WriteStrobe : IN STD_LOGIC; LMB3_BE : IN STD_LOGIC_VECTOR(0 TO 3); Sl3_DBus : OUT STD_LOGIC_VECTOR(0 TO 31); Sl3_Ready : OUT STD_LOGIC; Sl3_Wait : OUT STD_LOGIC; Sl3_UE : OUT STD_LOGIC; Sl3_CE : OUT STD_LOGIC; BRAM_Rst_A : OUT STD_LOGIC; BRAM_Clk_A : OUT STD_LOGIC; BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31); BRAM_EN_A : OUT STD_LOGIC; BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3); BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31); BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31); S_AXI_CTRL_ACLK : IN STD_LOGIC; S_AXI_CTRL_ARESETN : IN STD_LOGIC; S_AXI_CTRL_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S_AXI_CTRL_AWVALID : IN STD_LOGIC; S_AXI_CTRL_AWREADY : OUT STD_LOGIC; S_AXI_CTRL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S_AXI_CTRL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_AXI_CTRL_WVALID : IN STD_LOGIC; S_AXI_CTRL_WREADY : OUT STD_LOGIC; S_AXI_CTRL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S_AXI_CTRL_BVALID : OUT STD_LOGIC; S_AXI_CTRL_BREADY : IN STD_LOGIC; S_AXI_CTRL_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S_AXI_CTRL_ARVALID : IN STD_LOGIC; S_AXI_CTRL_ARREADY : OUT STD_LOGIC; S_AXI_CTRL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); S_AXI_CTRL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S_AXI_CTRL_RVALID : OUT STD_LOGIC; S_AXI_CTRL_RREADY : IN STD_LOGIC; UE : OUT STD_LOGIC; CE : OUT STD_LOGIC; Interrupt : OUT STD_LOGIC ); END COMPONENT lmb_bram_if_cntlr; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF design_1_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "lmb_bram_if_cntlr,Vivado 2015.2"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_ilmb_bram_if_cntlr_0_arch : ARCHITECTURE IS "design_1_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF design_1_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "design_1_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_bram_if_cntlr,x_ipVersion=4.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_HIGHADDR=0x00007FFF,C_BASEADDR=0x00000000,C_NUM_LMB=1,C_MASK=0x20000000,C_MASK1=0x00800000,C_MASK2=0x00800000,C_MASK3=0x00800000,C_LMB_AWIDTH=32,C_LMB_DWIDTH=32,C_ECC=0,C_INTERCONNECT=0,C_FAULT_INJECT=0,C_CE_FAILING_REGISTERS=0,C_UE_FAILING_REGISTERS=0,C_ECC_STATUS_REGISTERS=0,C_ECC_ONOFF_REGISTER=0,C_ECC_ONOFF_RESET_VALUE=1,C_CE_COUNTER_WIDTH=0,C_WRITE_ACCESS=2,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK"; ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST"; ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ABUS"; ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS"; ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE"; ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READSTROBE"; ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE"; ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB BE"; ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READDBUS"; ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READY"; ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WAIT"; ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB UE"; ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB CE"; ATTRIBUTE X_INTERFACE_INFO OF BRAM_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT RST"; ATTRIBUTE X_INTERFACE_INFO OF BRAM_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT CLK"; ATTRIBUTE X_INTERFACE_INFO OF BRAM_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR"; ATTRIBUTE X_INTERFACE_INFO OF BRAM_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT EN"; ATTRIBUTE X_INTERFACE_INFO OF BRAM_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT WE"; ATTRIBUTE X_INTERFACE_INFO OF BRAM_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DIN"; ATTRIBUTE X_INTERFACE_INFO OF BRAM_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT"; BEGIN U0 : lmb_bram_if_cntlr GENERIC MAP ( C_FAMILY => "artix7", C_HIGHADDR => X"00007FFF", C_BASEADDR => X"00000000", C_NUM_LMB => 1, C_MASK => X"20000000", C_MASK1 => X"00800000", C_MASK2 => X"00800000", C_MASK3 => X"00800000", C_LMB_AWIDTH => 32, C_LMB_DWIDTH => 32, C_ECC => 0, C_INTERCONNECT => 0, C_FAULT_INJECT => 0, C_CE_FAILING_REGISTERS => 0, C_UE_FAILING_REGISTERS => 0, C_ECC_STATUS_REGISTERS => 0, C_ECC_ONOFF_REGISTER => 0, C_ECC_ONOFF_RESET_VALUE => 1, C_CE_COUNTER_WIDTH => 0, C_WRITE_ACCESS => 2, C_S_AXI_CTRL_ADDR_WIDTH => 32, C_S_AXI_CTRL_DATA_WIDTH => 32 ) PORT MAP ( LMB_Clk => LMB_Clk, LMB_Rst => LMB_Rst, LMB_ABus => LMB_ABus, LMB_WriteDBus => LMB_WriteDBus, LMB_AddrStrobe => LMB_AddrStrobe, LMB_ReadStrobe => LMB_ReadStrobe, LMB_WriteStrobe => LMB_WriteStrobe, LMB_BE => LMB_BE, Sl_DBus => Sl_DBus, Sl_Ready => Sl_Ready, Sl_Wait => Sl_Wait, Sl_UE => Sl_UE, Sl_CE => Sl_CE, LMB1_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), LMB1_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), LMB1_AddrStrobe => '0', LMB1_ReadStrobe => '0', LMB1_WriteStrobe => '0', LMB1_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), LMB2_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), LMB2_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), LMB2_AddrStrobe => '0', LMB2_ReadStrobe => '0', LMB2_WriteStrobe => '0', LMB2_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), LMB3_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), LMB3_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), LMB3_AddrStrobe => '0', LMB3_ReadStrobe => '0', LMB3_WriteStrobe => '0', LMB3_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), BRAM_Rst_A => BRAM_Rst_A, BRAM_Clk_A => BRAM_Clk_A, BRAM_Addr_A => BRAM_Addr_A, BRAM_EN_A => BRAM_EN_A, BRAM_WEN_A => BRAM_WEN_A, BRAM_Dout_A => BRAM_Dout_A, BRAM_Din_A => BRAM_Din_A, S_AXI_CTRL_ACLK => '0', S_AXI_CTRL_ARESETN => '0', S_AXI_CTRL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S_AXI_CTRL_AWVALID => '0', S_AXI_CTRL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S_AXI_CTRL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), S_AXI_CTRL_WVALID => '0', S_AXI_CTRL_BREADY => '0', S_AXI_CTRL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S_AXI_CTRL_ARVALID => '0', S_AXI_CTRL_RREADY => '0' ); END design_1_ilmb_bram_if_cntlr_0_arch;
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:lmb_bram_if_cntlr:4.0 -- IP Revision: 6 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY lmb_bram_if_cntlr_v4_0; USE lmb_bram_if_cntlr_v4_0.lmb_bram_if_cntlr; ENTITY design_1_ilmb_bram_if_cntlr_0 IS PORT ( LMB_Clk : IN STD_LOGIC; LMB_Rst : IN STD_LOGIC; LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31); LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31); LMB_AddrStrobe : IN STD_LOGIC; LMB_ReadStrobe : IN STD_LOGIC; LMB_WriteStrobe : IN STD_LOGIC; LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3); Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31); Sl_Ready : OUT STD_LOGIC; Sl_Wait : OUT STD_LOGIC; Sl_UE : OUT STD_LOGIC; Sl_CE : OUT STD_LOGIC; BRAM_Rst_A : OUT STD_LOGIC; BRAM_Clk_A : OUT STD_LOGIC; BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31); BRAM_EN_A : OUT STD_LOGIC; BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3); BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31); BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31) ); END design_1_ilmb_bram_if_cntlr_0; ARCHITECTURE design_1_ilmb_bram_if_cntlr_0_arch OF design_1_ilmb_bram_if_cntlr_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "yes"; COMPONENT lmb_bram_if_cntlr IS GENERIC ( C_FAMILY : STRING; C_HIGHADDR : STD_LOGIC_VECTOR(0 TO 31); C_BASEADDR : STD_LOGIC_VECTOR(0 TO 31); C_NUM_LMB : INTEGER; C_MASK : STD_LOGIC_VECTOR(0 TO 31); C_MASK1 : STD_LOGIC_VECTOR(0 TO 31); C_MASK2 : STD_LOGIC_VECTOR(0 TO 31); C_MASK3 : STD_LOGIC_VECTOR(0 TO 31); C_LMB_AWIDTH : INTEGER; C_LMB_DWIDTH : INTEGER; C_ECC : INTEGER; C_INTERCONNECT : INTEGER; C_FAULT_INJECT : INTEGER; C_CE_FAILING_REGISTERS : INTEGER; C_UE_FAILING_REGISTERS : INTEGER; C_ECC_STATUS_REGISTERS : INTEGER; C_ECC_ONOFF_REGISTER : INTEGER; C_ECC_ONOFF_RESET_VALUE : INTEGER; C_CE_COUNTER_WIDTH : INTEGER; C_WRITE_ACCESS : INTEGER; C_S_AXI_CTRL_ADDR_WIDTH : INTEGER; C_S_AXI_CTRL_DATA_WIDTH : INTEGER ); PORT ( LMB_Clk : IN STD_LOGIC; LMB_Rst : IN STD_LOGIC; LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31); LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31); LMB_AddrStrobe : IN STD_LOGIC; LMB_ReadStrobe : IN STD_LOGIC; LMB_WriteStrobe : IN STD_LOGIC; LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3); Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31); Sl_Ready : OUT STD_LOGIC; Sl_Wait : OUT STD_LOGIC; Sl_UE : OUT STD_LOGIC; Sl_CE : OUT STD_LOGIC; LMB1_ABus : IN STD_LOGIC_VECTOR(0 TO 31); LMB1_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31); LMB1_AddrStrobe : IN STD_LOGIC; LMB1_ReadStrobe : IN STD_LOGIC; LMB1_WriteStrobe : IN STD_LOGIC; LMB1_BE : IN STD_LOGIC_VECTOR(0 TO 3); Sl1_DBus : OUT STD_LOGIC_VECTOR(0 TO 31); Sl1_Ready : OUT STD_LOGIC; Sl1_Wait : OUT STD_LOGIC; Sl1_UE : OUT STD_LOGIC; Sl1_CE : OUT STD_LOGIC; LMB2_ABus : IN STD_LOGIC_VECTOR(0 TO 31); LMB2_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31); LMB2_AddrStrobe : IN STD_LOGIC; LMB2_ReadStrobe : IN STD_LOGIC; LMB2_WriteStrobe : IN STD_LOGIC; LMB2_BE : IN STD_LOGIC_VECTOR(0 TO 3); Sl2_DBus : OUT STD_LOGIC_VECTOR(0 TO 31); Sl2_Ready : OUT STD_LOGIC; Sl2_Wait : OUT STD_LOGIC; Sl2_UE : OUT STD_LOGIC; Sl2_CE : OUT STD_LOGIC; LMB3_ABus : IN STD_LOGIC_VECTOR(0 TO 31); LMB3_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31); LMB3_AddrStrobe : IN STD_LOGIC; LMB3_ReadStrobe : IN STD_LOGIC; LMB3_WriteStrobe : IN STD_LOGIC; LMB3_BE : IN STD_LOGIC_VECTOR(0 TO 3); Sl3_DBus : OUT STD_LOGIC_VECTOR(0 TO 31); Sl3_Ready : OUT STD_LOGIC; Sl3_Wait : OUT STD_LOGIC; Sl3_UE : OUT STD_LOGIC; Sl3_CE : OUT STD_LOGIC; BRAM_Rst_A : OUT STD_LOGIC; BRAM_Clk_A : OUT STD_LOGIC; BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31); BRAM_EN_A : OUT STD_LOGIC; BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3); BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31); BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31); S_AXI_CTRL_ACLK : IN STD_LOGIC; S_AXI_CTRL_ARESETN : IN STD_LOGIC; S_AXI_CTRL_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S_AXI_CTRL_AWVALID : IN STD_LOGIC; S_AXI_CTRL_AWREADY : OUT STD_LOGIC; S_AXI_CTRL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S_AXI_CTRL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); S_AXI_CTRL_WVALID : IN STD_LOGIC; S_AXI_CTRL_WREADY : OUT STD_LOGIC; S_AXI_CTRL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S_AXI_CTRL_BVALID : OUT STD_LOGIC; S_AXI_CTRL_BREADY : IN STD_LOGIC; S_AXI_CTRL_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S_AXI_CTRL_ARVALID : IN STD_LOGIC; S_AXI_CTRL_ARREADY : OUT STD_LOGIC; S_AXI_CTRL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); S_AXI_CTRL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); S_AXI_CTRL_RVALID : OUT STD_LOGIC; S_AXI_CTRL_RREADY : IN STD_LOGIC; UE : OUT STD_LOGIC; CE : OUT STD_LOGIC; Interrupt : OUT STD_LOGIC ); END COMPONENT lmb_bram_if_cntlr; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF design_1_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "lmb_bram_if_cntlr,Vivado 2015.2"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_ilmb_bram_if_cntlr_0_arch : ARCHITECTURE IS "design_1_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF design_1_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "design_1_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_bram_if_cntlr,x_ipVersion=4.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_HIGHADDR=0x00007FFF,C_BASEADDR=0x00000000,C_NUM_LMB=1,C_MASK=0x20000000,C_MASK1=0x00800000,C_MASK2=0x00800000,C_MASK3=0x00800000,C_LMB_AWIDTH=32,C_LMB_DWIDTH=32,C_ECC=0,C_INTERCONNECT=0,C_FAULT_INJECT=0,C_CE_FAILING_REGISTERS=0,C_UE_FAILING_REGISTERS=0,C_ECC_STATUS_REGISTERS=0,C_ECC_ONOFF_REGISTER=0,C_ECC_ONOFF_RESET_VALUE=1,C_CE_COUNTER_WIDTH=0,C_WRITE_ACCESS=2,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK"; ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST"; ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ABUS"; ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS"; ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE"; ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READSTROBE"; ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE"; ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB BE"; ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READDBUS"; ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READY"; ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WAIT"; ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB UE"; ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB CE"; ATTRIBUTE X_INTERFACE_INFO OF BRAM_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT RST"; ATTRIBUTE X_INTERFACE_INFO OF BRAM_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT CLK"; ATTRIBUTE X_INTERFACE_INFO OF BRAM_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR"; ATTRIBUTE X_INTERFACE_INFO OF BRAM_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT EN"; ATTRIBUTE X_INTERFACE_INFO OF BRAM_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT WE"; ATTRIBUTE X_INTERFACE_INFO OF BRAM_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DIN"; ATTRIBUTE X_INTERFACE_INFO OF BRAM_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT"; BEGIN U0 : lmb_bram_if_cntlr GENERIC MAP ( C_FAMILY => "artix7", C_HIGHADDR => X"00007FFF", C_BASEADDR => X"00000000", C_NUM_LMB => 1, C_MASK => X"20000000", C_MASK1 => X"00800000", C_MASK2 => X"00800000", C_MASK3 => X"00800000", C_LMB_AWIDTH => 32, C_LMB_DWIDTH => 32, C_ECC => 0, C_INTERCONNECT => 0, C_FAULT_INJECT => 0, C_CE_FAILING_REGISTERS => 0, C_UE_FAILING_REGISTERS => 0, C_ECC_STATUS_REGISTERS => 0, C_ECC_ONOFF_REGISTER => 0, C_ECC_ONOFF_RESET_VALUE => 1, C_CE_COUNTER_WIDTH => 0, C_WRITE_ACCESS => 2, C_S_AXI_CTRL_ADDR_WIDTH => 32, C_S_AXI_CTRL_DATA_WIDTH => 32 ) PORT MAP ( LMB_Clk => LMB_Clk, LMB_Rst => LMB_Rst, LMB_ABus => LMB_ABus, LMB_WriteDBus => LMB_WriteDBus, LMB_AddrStrobe => LMB_AddrStrobe, LMB_ReadStrobe => LMB_ReadStrobe, LMB_WriteStrobe => LMB_WriteStrobe, LMB_BE => LMB_BE, Sl_DBus => Sl_DBus, Sl_Ready => Sl_Ready, Sl_Wait => Sl_Wait, Sl_UE => Sl_UE, Sl_CE => Sl_CE, LMB1_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), LMB1_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), LMB1_AddrStrobe => '0', LMB1_ReadStrobe => '0', LMB1_WriteStrobe => '0', LMB1_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), LMB2_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), LMB2_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), LMB2_AddrStrobe => '0', LMB2_ReadStrobe => '0', LMB2_WriteStrobe => '0', LMB2_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), LMB3_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), LMB3_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), LMB3_AddrStrobe => '0', LMB3_ReadStrobe => '0', LMB3_WriteStrobe => '0', LMB3_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), BRAM_Rst_A => BRAM_Rst_A, BRAM_Clk_A => BRAM_Clk_A, BRAM_Addr_A => BRAM_Addr_A, BRAM_EN_A => BRAM_EN_A, BRAM_WEN_A => BRAM_WEN_A, BRAM_Dout_A => BRAM_Dout_A, BRAM_Din_A => BRAM_Din_A, S_AXI_CTRL_ACLK => '0', S_AXI_CTRL_ARESETN => '0', S_AXI_CTRL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S_AXI_CTRL_AWVALID => '0', S_AXI_CTRL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S_AXI_CTRL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), S_AXI_CTRL_WVALID => '0', S_AXI_CTRL_BREADY => '0', S_AXI_CTRL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S_AXI_CTRL_ARVALID => '0', S_AXI_CTRL_RREADY => '0' ); END design_1_ilmb_bram_if_cntlr_0_arch;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_CASTYTOF.VHD *** --*** *** --*** Function: Cast Internal Double to *** --*** External Single *** --*** *** --*** 06/03/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_castytof IS GENERIC ( roundconvert : integer := 1; -- global switch - round all conversions when '1' mantissa : positive := 32; normspeed : positive := 2 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); END hcc_castytof; ARCHITECTURE rtl OF hcc_castytof IS signal midnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal satnode, zipnode : STD_LOGIC; component hcc_castytox GENERIC ( roundconvert : integer := 1; -- global switch - round all conversions when '1' mantissa : positive := 32 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); end component; component hcc_castxtof GENERIC ( mantissa : positive := 32; -- 32 or 36 normspeed : positive := 2 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); end component; BEGIN one: hcc_castytox GENERIC MAP (roundconvert=>roundconvert,mantissa=>mantissa) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aa,aasat=>aasat,aazip=>aazip, cc=>midnode,ccsat=>satnode,cczip=>zipnode); two: hcc_castxtof GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>midnode,aasat=>satnode,aazip=>zipnode, cc=>cc); END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_CASTYTOF.VHD *** --*** *** --*** Function: Cast Internal Double to *** --*** External Single *** --*** *** --*** 06/03/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_castytof IS GENERIC ( roundconvert : integer := 1; -- global switch - round all conversions when '1' mantissa : positive := 32; normspeed : positive := 2 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); END hcc_castytof; ARCHITECTURE rtl OF hcc_castytof IS signal midnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal satnode, zipnode : STD_LOGIC; component hcc_castytox GENERIC ( roundconvert : integer := 1; -- global switch - round all conversions when '1' mantissa : positive := 32 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); end component; component hcc_castxtof GENERIC ( mantissa : positive := 32; -- 32 or 36 normspeed : positive := 2 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); end component; BEGIN one: hcc_castytox GENERIC MAP (roundconvert=>roundconvert,mantissa=>mantissa) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aa,aasat=>aasat,aazip=>aazip, cc=>midnode,ccsat=>satnode,cczip=>zipnode); two: hcc_castxtof GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>midnode,aasat=>satnode,aazip=>zipnode, cc=>cc); END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_CASTYTOF.VHD *** --*** *** --*** Function: Cast Internal Double to *** --*** External Single *** --*** *** --*** 06/03/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_castytof IS GENERIC ( roundconvert : integer := 1; -- global switch - round all conversions when '1' mantissa : positive := 32; normspeed : positive := 2 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); END hcc_castytof; ARCHITECTURE rtl OF hcc_castytof IS signal midnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal satnode, zipnode : STD_LOGIC; component hcc_castytox GENERIC ( roundconvert : integer := 1; -- global switch - round all conversions when '1' mantissa : positive := 32 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); end component; component hcc_castxtof GENERIC ( mantissa : positive := 32; -- 32 or 36 normspeed : positive := 2 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); end component; BEGIN one: hcc_castytox GENERIC MAP (roundconvert=>roundconvert,mantissa=>mantissa) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aa,aasat=>aasat,aazip=>aazip, cc=>midnode,ccsat=>satnode,cczip=>zipnode); two: hcc_castxtof GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>midnode,aasat=>satnode,aazip=>zipnode, cc=>cc); END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_CASTYTOF.VHD *** --*** *** --*** Function: Cast Internal Double to *** --*** External Single *** --*** *** --*** 06/03/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_castytof IS GENERIC ( roundconvert : integer := 1; -- global switch - round all conversions when '1' mantissa : positive := 32; normspeed : positive := 2 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); END hcc_castytof; ARCHITECTURE rtl OF hcc_castytof IS signal midnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal satnode, zipnode : STD_LOGIC; component hcc_castytox GENERIC ( roundconvert : integer := 1; -- global switch - round all conversions when '1' mantissa : positive := 32 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); end component; component hcc_castxtof GENERIC ( mantissa : positive := 32; -- 32 or 36 normspeed : positive := 2 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); end component; BEGIN one: hcc_castytox GENERIC MAP (roundconvert=>roundconvert,mantissa=>mantissa) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aa,aasat=>aasat,aazip=>aazip, cc=>midnode,ccsat=>satnode,cczip=>zipnode); two: hcc_castxtof GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>midnode,aasat=>satnode,aazip=>zipnode, cc=>cc); END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_CASTYTOF.VHD *** --*** *** --*** Function: Cast Internal Double to *** --*** External Single *** --*** *** --*** 06/03/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_castytof IS GENERIC ( roundconvert : integer := 1; -- global switch - round all conversions when '1' mantissa : positive := 32; normspeed : positive := 2 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); END hcc_castytof; ARCHITECTURE rtl OF hcc_castytof IS signal midnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal satnode, zipnode : STD_LOGIC; component hcc_castytox GENERIC ( roundconvert : integer := 1; -- global switch - round all conversions when '1' mantissa : positive := 32 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); end component; component hcc_castxtof GENERIC ( mantissa : positive := 32; -- 32 or 36 normspeed : positive := 2 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); end component; BEGIN one: hcc_castytox GENERIC MAP (roundconvert=>roundconvert,mantissa=>mantissa) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aa,aasat=>aasat,aazip=>aazip, cc=>midnode,ccsat=>satnode,cczip=>zipnode); two: hcc_castxtof GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>midnode,aasat=>satnode,aazip=>zipnode, cc=>cc); END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_CASTYTOF.VHD *** --*** *** --*** Function: Cast Internal Double to *** --*** External Single *** --*** *** --*** 06/03/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_castytof IS GENERIC ( roundconvert : integer := 1; -- global switch - round all conversions when '1' mantissa : positive := 32; normspeed : positive := 2 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); END hcc_castytof; ARCHITECTURE rtl OF hcc_castytof IS signal midnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal satnode, zipnode : STD_LOGIC; component hcc_castytox GENERIC ( roundconvert : integer := 1; -- global switch - round all conversions when '1' mantissa : positive := 32 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); end component; component hcc_castxtof GENERIC ( mantissa : positive := 32; -- 32 or 36 normspeed : positive := 2 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); end component; BEGIN one: hcc_castytox GENERIC MAP (roundconvert=>roundconvert,mantissa=>mantissa) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aa,aasat=>aasat,aazip=>aazip, cc=>midnode,ccsat=>satnode,cczip=>zipnode); two: hcc_castxtof GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>midnode,aasat=>satnode,aazip=>zipnode, cc=>cc); END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_CASTYTOF.VHD *** --*** *** --*** Function: Cast Internal Double to *** --*** External Single *** --*** *** --*** 06/03/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_castytof IS GENERIC ( roundconvert : integer := 1; -- global switch - round all conversions when '1' mantissa : positive := 32; normspeed : positive := 2 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); END hcc_castytof; ARCHITECTURE rtl OF hcc_castytof IS signal midnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal satnode, zipnode : STD_LOGIC; component hcc_castytox GENERIC ( roundconvert : integer := 1; -- global switch - round all conversions when '1' mantissa : positive := 32 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); end component; component hcc_castxtof GENERIC ( mantissa : positive := 32; -- 32 or 36 normspeed : positive := 2 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); end component; BEGIN one: hcc_castytox GENERIC MAP (roundconvert=>roundconvert,mantissa=>mantissa) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aa,aasat=>aasat,aazip=>aazip, cc=>midnode,ccsat=>satnode,cczip=>zipnode); two: hcc_castxtof GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>midnode,aasat=>satnode,aazip=>zipnode, cc=>cc); END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_CASTYTOF.VHD *** --*** *** --*** Function: Cast Internal Double to *** --*** External Single *** --*** *** --*** 06/03/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_castytof IS GENERIC ( roundconvert : integer := 1; -- global switch - round all conversions when '1' mantissa : positive := 32; normspeed : positive := 2 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); END hcc_castytof; ARCHITECTURE rtl OF hcc_castytof IS signal midnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal satnode, zipnode : STD_LOGIC; component hcc_castytox GENERIC ( roundconvert : integer := 1; -- global switch - round all conversions when '1' mantissa : positive := 32 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); end component; component hcc_castxtof GENERIC ( mantissa : positive := 32; -- 32 or 36 normspeed : positive := 2 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); end component; BEGIN one: hcc_castytox GENERIC MAP (roundconvert=>roundconvert,mantissa=>mantissa) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aa,aasat=>aasat,aazip=>aazip, cc=>midnode,ccsat=>satnode,cczip=>zipnode); two: hcc_castxtof GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>midnode,aasat=>satnode,aazip=>zipnode, cc=>cc); END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_CASTYTOF.VHD *** --*** *** --*** Function: Cast Internal Double to *** --*** External Single *** --*** *** --*** 06/03/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_castytof IS GENERIC ( roundconvert : integer := 1; -- global switch - round all conversions when '1' mantissa : positive := 32; normspeed : positive := 2 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); END hcc_castytof; ARCHITECTURE rtl OF hcc_castytof IS signal midnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal satnode, zipnode : STD_LOGIC; component hcc_castytox GENERIC ( roundconvert : integer := 1; -- global switch - round all conversions when '1' mantissa : positive := 32 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); end component; component hcc_castxtof GENERIC ( mantissa : positive := 32; -- 32 or 36 normspeed : positive := 2 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); end component; BEGIN one: hcc_castytox GENERIC MAP (roundconvert=>roundconvert,mantissa=>mantissa) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aa,aasat=>aasat,aazip=>aazip, cc=>midnode,ccsat=>satnode,cczip=>zipnode); two: hcc_castxtof GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>midnode,aasat=>satnode,aazip=>zipnode, cc=>cc); END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_CASTYTOF.VHD *** --*** *** --*** Function: Cast Internal Double to *** --*** External Single *** --*** *** --*** 06/03/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_castytof IS GENERIC ( roundconvert : integer := 1; -- global switch - round all conversions when '1' mantissa : positive := 32; normspeed : positive := 2 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); END hcc_castytof; ARCHITECTURE rtl OF hcc_castytof IS signal midnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal satnode, zipnode : STD_LOGIC; component hcc_castytox GENERIC ( roundconvert : integer := 1; -- global switch - round all conversions when '1' mantissa : positive := 32 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); end component; component hcc_castxtof GENERIC ( mantissa : positive := 32; -- 32 or 36 normspeed : positive := 2 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); aasat, aazip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); end component; BEGIN one: hcc_castytox GENERIC MAP (roundconvert=>roundconvert,mantissa=>mantissa) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aa,aasat=>aasat,aazip=>aazip, cc=>midnode,ccsat=>satnode,cczip=>zipnode); two: hcc_castxtof GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>midnode,aasat=>satnode,aazip=>zipnode, cc=>cc); END rtl;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1579.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s10b00x00p04n01i01579ent IS END c08s10b00x00p04n01i01579ent; ARCHITECTURE c08s10b00x00p04n01i01579arch OF c08s10b00x00p04n01i01579ent IS BEGIN TESTING: PROCESS BEGIN L : for i in 1 to 10 loop next when 't'; end loop; assert FALSE report "***FAILED TEST: c08s10b00x00p04n01i01579 - The condition in a next statement has to be of type boolean" severity ERROR; wait; END PROCESS TESTING; END c08s10b00x00p04n01i01579arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1579.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s10b00x00p04n01i01579ent IS END c08s10b00x00p04n01i01579ent; ARCHITECTURE c08s10b00x00p04n01i01579arch OF c08s10b00x00p04n01i01579ent IS BEGIN TESTING: PROCESS BEGIN L : for i in 1 to 10 loop next when 't'; end loop; assert FALSE report "***FAILED TEST: c08s10b00x00p04n01i01579 - The condition in a next statement has to be of type boolean" severity ERROR; wait; END PROCESS TESTING; END c08s10b00x00p04n01i01579arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1579.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s10b00x00p04n01i01579ent IS END c08s10b00x00p04n01i01579ent; ARCHITECTURE c08s10b00x00p04n01i01579arch OF c08s10b00x00p04n01i01579ent IS BEGIN TESTING: PROCESS BEGIN L : for i in 1 to 10 loop next when 't'; end loop; assert FALSE report "***FAILED TEST: c08s10b00x00p04n01i01579 - The condition in a next statement has to be of type boolean" severity ERROR; wait; END PROCESS TESTING; END c08s10b00x00p04n01i01579arch;
architecture rtl of fifo is begin PROCEDURE_CALL_LABEL : postponed wr_en(a, b); PROCEDURE_CALL_LABEL : postponed wr_en(a, b); process_label : process begin PROCEDURE_CALL_LABEL : wr_en(a, b); PROCEDURE_CALL_LABEL : wr_en(a, b); end process; end architecture rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_DELMEM.VHD *** --*** *** --*** Function: Delay an arbitrary width an *** --*** arbitrary number of stages *** --*** *** --*** Note: this code megawizard generated *** --*** *** --*** 12/12/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_delmem IS GENERIC ( width : positive := 79; delay : positive := 7 ); PORT ( sysclk : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END hcc_delmem; ARCHITECTURE SYN OF hcc_delmem IS signal dummy : STD_LOGIC_VECTOR (width DOWNTO 1); COMPONENT altshift_taps GENERIC ( lpm_hint : STRING; lpm_type : STRING; number_of_taps : NATURAL; tap_distance : NATURAL; width : NATURAL ); PORT ( taps : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0); clken : IN STD_LOGIC ; clock : IN STD_LOGIC ; shiftout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0); shiftin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) ); END COMPONENT; BEGIN delcore: altshift_taps GENERIC MAP ( lpm_hint => "RAM_BLOCK_TYPE=M512", lpm_type => "altshift_taps", number_of_taps => 1, tap_distance => delay, width => width ) PORT MAP ( clock => sysclk, clken => enable, shiftin => aa, taps => dummy, shiftout => cc ); END SYN;
LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_DELMEM.VHD *** --*** *** --*** Function: Delay an arbitrary width an *** --*** arbitrary number of stages *** --*** *** --*** Note: this code megawizard generated *** --*** *** --*** 12/12/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_delmem IS GENERIC ( width : positive := 79; delay : positive := 7 ); PORT ( sysclk : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END hcc_delmem; ARCHITECTURE SYN OF hcc_delmem IS signal dummy : STD_LOGIC_VECTOR (width DOWNTO 1); COMPONENT altshift_taps GENERIC ( lpm_hint : STRING; lpm_type : STRING; number_of_taps : NATURAL; tap_distance : NATURAL; width : NATURAL ); PORT ( taps : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0); clken : IN STD_LOGIC ; clock : IN STD_LOGIC ; shiftout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0); shiftin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) ); END COMPONENT; BEGIN delcore: altshift_taps GENERIC MAP ( lpm_hint => "RAM_BLOCK_TYPE=M512", lpm_type => "altshift_taps", number_of_taps => 1, tap_distance => delay, width => width ) PORT MAP ( clock => sysclk, clken => enable, shiftin => aa, taps => dummy, shiftout => cc ); END SYN;
LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_DELMEM.VHD *** --*** *** --*** Function: Delay an arbitrary width an *** --*** arbitrary number of stages *** --*** *** --*** Note: this code megawizard generated *** --*** *** --*** 12/12/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_delmem IS GENERIC ( width : positive := 79; delay : positive := 7 ); PORT ( sysclk : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END hcc_delmem; ARCHITECTURE SYN OF hcc_delmem IS signal dummy : STD_LOGIC_VECTOR (width DOWNTO 1); COMPONENT altshift_taps GENERIC ( lpm_hint : STRING; lpm_type : STRING; number_of_taps : NATURAL; tap_distance : NATURAL; width : NATURAL ); PORT ( taps : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0); clken : IN STD_LOGIC ; clock : IN STD_LOGIC ; shiftout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0); shiftin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) ); END COMPONENT; BEGIN delcore: altshift_taps GENERIC MAP ( lpm_hint => "RAM_BLOCK_TYPE=M512", lpm_type => "altshift_taps", number_of_taps => 1, tap_distance => delay, width => width ) PORT MAP ( clock => sysclk, clken => enable, shiftin => aa, taps => dummy, shiftout => cc ); END SYN;
LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_DELMEM.VHD *** --*** *** --*** Function: Delay an arbitrary width an *** --*** arbitrary number of stages *** --*** *** --*** Note: this code megawizard generated *** --*** *** --*** 12/12/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_delmem IS GENERIC ( width : positive := 79; delay : positive := 7 ); PORT ( sysclk : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END hcc_delmem; ARCHITECTURE SYN OF hcc_delmem IS signal dummy : STD_LOGIC_VECTOR (width DOWNTO 1); COMPONENT altshift_taps GENERIC ( lpm_hint : STRING; lpm_type : STRING; number_of_taps : NATURAL; tap_distance : NATURAL; width : NATURAL ); PORT ( taps : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0); clken : IN STD_LOGIC ; clock : IN STD_LOGIC ; shiftout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0); shiftin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) ); END COMPONENT; BEGIN delcore: altshift_taps GENERIC MAP ( lpm_hint => "RAM_BLOCK_TYPE=M512", lpm_type => "altshift_taps", number_of_taps => 1, tap_distance => delay, width => width ) PORT MAP ( clock => sysclk, clken => enable, shiftin => aa, taps => dummy, shiftout => cc ); END SYN;
LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_DELMEM.VHD *** --*** *** --*** Function: Delay an arbitrary width an *** --*** arbitrary number of stages *** --*** *** --*** Note: this code megawizard generated *** --*** *** --*** 12/12/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_delmem IS GENERIC ( width : positive := 79; delay : positive := 7 ); PORT ( sysclk : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END hcc_delmem; ARCHITECTURE SYN OF hcc_delmem IS signal dummy : STD_LOGIC_VECTOR (width DOWNTO 1); COMPONENT altshift_taps GENERIC ( lpm_hint : STRING; lpm_type : STRING; number_of_taps : NATURAL; tap_distance : NATURAL; width : NATURAL ); PORT ( taps : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0); clken : IN STD_LOGIC ; clock : IN STD_LOGIC ; shiftout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0); shiftin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) ); END COMPONENT; BEGIN delcore: altshift_taps GENERIC MAP ( lpm_hint => "RAM_BLOCK_TYPE=M512", lpm_type => "altshift_taps", number_of_taps => 1, tap_distance => delay, width => width ) PORT MAP ( clock => sysclk, clken => enable, shiftin => aa, taps => dummy, shiftout => cc ); END SYN;
LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_DELMEM.VHD *** --*** *** --*** Function: Delay an arbitrary width an *** --*** arbitrary number of stages *** --*** *** --*** Note: this code megawizard generated *** --*** *** --*** 12/12/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_delmem IS GENERIC ( width : positive := 79; delay : positive := 7 ); PORT ( sysclk : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END hcc_delmem; ARCHITECTURE SYN OF hcc_delmem IS signal dummy : STD_LOGIC_VECTOR (width DOWNTO 1); COMPONENT altshift_taps GENERIC ( lpm_hint : STRING; lpm_type : STRING; number_of_taps : NATURAL; tap_distance : NATURAL; width : NATURAL ); PORT ( taps : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0); clken : IN STD_LOGIC ; clock : IN STD_LOGIC ; shiftout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0); shiftin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) ); END COMPONENT; BEGIN delcore: altshift_taps GENERIC MAP ( lpm_hint => "RAM_BLOCK_TYPE=M512", lpm_type => "altshift_taps", number_of_taps => 1, tap_distance => delay, width => width ) PORT MAP ( clock => sysclk, clken => enable, shiftin => aa, taps => dummy, shiftout => cc ); END SYN;
LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_DELMEM.VHD *** --*** *** --*** Function: Delay an arbitrary width an *** --*** arbitrary number of stages *** --*** *** --*** Note: this code megawizard generated *** --*** *** --*** 12/12/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_delmem IS GENERIC ( width : positive := 79; delay : positive := 7 ); PORT ( sysclk : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END hcc_delmem; ARCHITECTURE SYN OF hcc_delmem IS signal dummy : STD_LOGIC_VECTOR (width DOWNTO 1); COMPONENT altshift_taps GENERIC ( lpm_hint : STRING; lpm_type : STRING; number_of_taps : NATURAL; tap_distance : NATURAL; width : NATURAL ); PORT ( taps : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0); clken : IN STD_LOGIC ; clock : IN STD_LOGIC ; shiftout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0); shiftin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) ); END COMPONENT; BEGIN delcore: altshift_taps GENERIC MAP ( lpm_hint => "RAM_BLOCK_TYPE=M512", lpm_type => "altshift_taps", number_of_taps => 1, tap_distance => delay, width => width ) PORT MAP ( clock => sysclk, clken => enable, shiftin => aa, taps => dummy, shiftout => cc ); END SYN;
LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_DELMEM.VHD *** --*** *** --*** Function: Delay an arbitrary width an *** --*** arbitrary number of stages *** --*** *** --*** Note: this code megawizard generated *** --*** *** --*** 12/12/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_delmem IS GENERIC ( width : positive := 79; delay : positive := 7 ); PORT ( sysclk : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END hcc_delmem; ARCHITECTURE SYN OF hcc_delmem IS signal dummy : STD_LOGIC_VECTOR (width DOWNTO 1); COMPONENT altshift_taps GENERIC ( lpm_hint : STRING; lpm_type : STRING; number_of_taps : NATURAL; tap_distance : NATURAL; width : NATURAL ); PORT ( taps : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0); clken : IN STD_LOGIC ; clock : IN STD_LOGIC ; shiftout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0); shiftin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) ); END COMPONENT; BEGIN delcore: altshift_taps GENERIC MAP ( lpm_hint => "RAM_BLOCK_TYPE=M512", lpm_type => "altshift_taps", number_of_taps => 1, tap_distance => delay, width => width ) PORT MAP ( clock => sysclk, clken => enable, shiftin => aa, taps => dummy, shiftout => cc ); END SYN;
LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_DELMEM.VHD *** --*** *** --*** Function: Delay an arbitrary width an *** --*** arbitrary number of stages *** --*** *** --*** Note: this code megawizard generated *** --*** *** --*** 12/12/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_delmem IS GENERIC ( width : positive := 79; delay : positive := 7 ); PORT ( sysclk : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END hcc_delmem; ARCHITECTURE SYN OF hcc_delmem IS signal dummy : STD_LOGIC_VECTOR (width DOWNTO 1); COMPONENT altshift_taps GENERIC ( lpm_hint : STRING; lpm_type : STRING; number_of_taps : NATURAL; tap_distance : NATURAL; width : NATURAL ); PORT ( taps : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0); clken : IN STD_LOGIC ; clock : IN STD_LOGIC ; shiftout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0); shiftin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) ); END COMPONENT; BEGIN delcore: altshift_taps GENERIC MAP ( lpm_hint => "RAM_BLOCK_TYPE=M512", lpm_type => "altshift_taps", number_of_taps => 1, tap_distance => delay, width => width ) PORT MAP ( clock => sysclk, clken => enable, shiftin => aa, taps => dummy, shiftout => cc ); END SYN;
LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_DELMEM.VHD *** --*** *** --*** Function: Delay an arbitrary width an *** --*** arbitrary number of stages *** --*** *** --*** Note: this code megawizard generated *** --*** *** --*** 12/12/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_delmem IS GENERIC ( width : positive := 79; delay : positive := 7 ); PORT ( sysclk : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END hcc_delmem; ARCHITECTURE SYN OF hcc_delmem IS signal dummy : STD_LOGIC_VECTOR (width DOWNTO 1); COMPONENT altshift_taps GENERIC ( lpm_hint : STRING; lpm_type : STRING; number_of_taps : NATURAL; tap_distance : NATURAL; width : NATURAL ); PORT ( taps : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0); clken : IN STD_LOGIC ; clock : IN STD_LOGIC ; shiftout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0); shiftin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) ); END COMPONENT; BEGIN delcore: altshift_taps GENERIC MAP ( lpm_hint => "RAM_BLOCK_TYPE=M512", lpm_type => "altshift_taps", number_of_taps => 1, tap_distance => delay, width => width ) PORT MAP ( clock => sysclk, clken => enable, shiftin => aa, taps => dummy, shiftout => cc ); END SYN;
Library ieee; use ieee.std_logic_1164.all; entity nbit_basic_alu is generic (bitsPerVector: integer:=4); port( enable : in std_logic; opA : in std_logic_vector(bitsPerVector-1 downto 0); opB : in std_logic_vector(bitsPerVector-1 downto 0); result: out std_logic_vector(bitsPerVector-1 downto 0); selector: in std_logic_vector(1 downto 0); c_out: out std_logic; c_in: in std_logic ); end nbit_basic_alu; architecture primary of nbit_basic_alu is signal temp_res: std_logic_vector(bitsPerVector downto 0); begin process(opA,opB,enable,selector,temp_res) variable opA_int,opB_int,res_int: integer; begin if(enable = '1') then opA_int := to_integer(signed(opA)); opB_int := to_integer(signed(opB)); if(selector = "00") then res_int := opA_int; elsif(selector = "01) then res_int := opA_int+1; elsif(selector = "10") then res_int := opA_int - opB_int -1; elsif(selector = "11") then res_int := opA_int - opB_int; end if res_int := res_int + to_integer(unsigned(c+in)); temp_res <= std_logic_vector(to_signed(res_int,bitsPerVector)); c_out <= temp_res(bitsPerVector); result <= temp_res(bitsPerVector-1 downto 0); else result<= (others => '0'); c_out <= '0'; end if end process; end primary;
component wasca is port ( abus_avalon_sdram_bridge_0_abus_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address abus_avalon_sdram_bridge_0_abus_read : in std_logic := 'X'; -- read abus_avalon_sdram_bridge_0_abus_waitrequest : out std_logic; -- waitrequest abus_avalon_sdram_bridge_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => 'X'); -- addressdata abus_avalon_sdram_bridge_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- chipselect abus_avalon_sdram_bridge_0_abus_direction : out std_logic; -- direction abus_avalon_sdram_bridge_0_abus_disable_out : out std_logic; -- disable_out abus_avalon_sdram_bridge_0_abus_interrupt : out std_logic; -- interrupt abus_avalon_sdram_bridge_0_abus_muxing : out std_logic_vector(1 downto 0); -- muxing abus_avalon_sdram_bridge_0_abus_writebyteenable_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- writebyteenable_n abus_avalon_sdram_bridge_0_abus_reset : in std_logic := 'X'; -- reset abus_avalon_sdram_bridge_0_sdram_addr : out std_logic_vector(12 downto 0); -- addr abus_avalon_sdram_bridge_0_sdram_ba : out std_logic_vector(1 downto 0); -- ba abus_avalon_sdram_bridge_0_sdram_cas_n : out std_logic; -- cas_n abus_avalon_sdram_bridge_0_sdram_cke : out std_logic; -- cke abus_avalon_sdram_bridge_0_sdram_cs_n : out std_logic; -- cs_n abus_avalon_sdram_bridge_0_sdram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq abus_avalon_sdram_bridge_0_sdram_dqm : out std_logic_vector(1 downto 0); -- dqm abus_avalon_sdram_bridge_0_sdram_ras_n : out std_logic; -- ras_n abus_avalon_sdram_bridge_0_sdram_we_n : out std_logic; -- we_n abus_avalon_sdram_bridge_0_sdram_clk : out std_logic; -- clk altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd : inout std_logic := 'X'; -- b_SD_cmd altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat : inout std_logic := 'X'; -- b_SD_dat altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3 : inout std_logic := 'X'; -- b_SD_dat3 altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock : out std_logic; -- o_SD_clock altpll_1_areset_conduit_export : in std_logic := 'X'; -- export altpll_1_locked_conduit_export : out std_logic; -- export altpll_1_phasedone_conduit_export : out std_logic; -- export audio_out_BCLK : in std_logic := 'X'; -- BCLK audio_out_DACDAT : out std_logic; -- DACDAT audio_out_DACLRCK : in std_logic := 'X'; -- DACLRCK buffered_spi_mosi : out std_logic; -- mosi buffered_spi_clk : out std_logic; -- clk buffered_spi_miso : in std_logic := 'X'; -- miso buffered_spi_cs : out std_logic; -- cs clk_clk : in std_logic := 'X'; -- clk clock_116_mhz_clk : out std_logic; -- clk reset_reset_n : in std_logic := 'X'; -- reset_n reset_controller_0_reset_in1_reset : in std_logic := 'X'; -- reset uart_0_external_connection_rxd : in std_logic := 'X'; -- rxd uart_0_external_connection_txd : out std_logic -- txd ); end component wasca; u0 : component wasca port map ( abus_avalon_sdram_bridge_0_abus_address => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_address, -- abus_avalon_sdram_bridge_0_abus.address abus_avalon_sdram_bridge_0_abus_read => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_read, -- .read abus_avalon_sdram_bridge_0_abus_waitrequest => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_waitrequest, -- .waitrequest abus_avalon_sdram_bridge_0_abus_addressdata => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_addressdata, -- .addressdata abus_avalon_sdram_bridge_0_abus_chipselect => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_chipselect, -- .chipselect abus_avalon_sdram_bridge_0_abus_direction => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_direction, -- .direction abus_avalon_sdram_bridge_0_abus_disable_out => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_disable_out, -- .disable_out abus_avalon_sdram_bridge_0_abus_interrupt => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_interrupt, -- .interrupt abus_avalon_sdram_bridge_0_abus_muxing => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_muxing, -- .muxing abus_avalon_sdram_bridge_0_abus_writebyteenable_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_writebyteenable_n, -- .writebyteenable_n abus_avalon_sdram_bridge_0_abus_reset => CONNECTED_TO_abus_avalon_sdram_bridge_0_abus_reset, -- .reset abus_avalon_sdram_bridge_0_sdram_addr => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_addr, -- abus_avalon_sdram_bridge_0_sdram.addr abus_avalon_sdram_bridge_0_sdram_ba => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_ba, -- .ba abus_avalon_sdram_bridge_0_sdram_cas_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_cas_n, -- .cas_n abus_avalon_sdram_bridge_0_sdram_cke => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_cke, -- .cke abus_avalon_sdram_bridge_0_sdram_cs_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_cs_n, -- .cs_n abus_avalon_sdram_bridge_0_sdram_dq => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_dq, -- .dq abus_avalon_sdram_bridge_0_sdram_dqm => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_dqm, -- .dqm abus_avalon_sdram_bridge_0_sdram_ras_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_ras_n, -- .ras_n abus_avalon_sdram_bridge_0_sdram_we_n => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_we_n, -- .we_n abus_avalon_sdram_bridge_0_sdram_clk => CONNECTED_TO_abus_avalon_sdram_bridge_0_sdram_clk, -- .clk altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd => CONNECTED_TO_altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_cmd, -- altera_up_sd_card_avalon_interface_0_conduit_end.b_SD_cmd altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat => CONNECTED_TO_altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat, -- .b_SD_dat altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3 => CONNECTED_TO_altera_up_sd_card_avalon_interface_0_conduit_end_b_SD_dat3, -- .b_SD_dat3 altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock => CONNECTED_TO_altera_up_sd_card_avalon_interface_0_conduit_end_o_SD_clock, -- .o_SD_clock altpll_1_areset_conduit_export => CONNECTED_TO_altpll_1_areset_conduit_export, -- altpll_1_areset_conduit.export altpll_1_locked_conduit_export => CONNECTED_TO_altpll_1_locked_conduit_export, -- altpll_1_locked_conduit.export altpll_1_phasedone_conduit_export => CONNECTED_TO_altpll_1_phasedone_conduit_export, -- altpll_1_phasedone_conduit.export audio_out_BCLK => CONNECTED_TO_audio_out_BCLK, -- audio_out.BCLK audio_out_DACDAT => CONNECTED_TO_audio_out_DACDAT, -- .DACDAT audio_out_DACLRCK => CONNECTED_TO_audio_out_DACLRCK, -- .DACLRCK buffered_spi_mosi => CONNECTED_TO_buffered_spi_mosi, -- buffered_spi.mosi buffered_spi_clk => CONNECTED_TO_buffered_spi_clk, -- .clk buffered_spi_miso => CONNECTED_TO_buffered_spi_miso, -- .miso buffered_spi_cs => CONNECTED_TO_buffered_spi_cs, -- .cs clk_clk => CONNECTED_TO_clk_clk, -- clk.clk clock_116_mhz_clk => CONNECTED_TO_clock_116_mhz_clk, -- clock_116_mhz.clk reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n reset_controller_0_reset_in1_reset => CONNECTED_TO_reset_controller_0_reset_in1_reset, -- reset_controller_0_reset_in1.reset uart_0_external_connection_rxd => CONNECTED_TO_uart_0_external_connection_rxd, -- uart_0_external_connection.rxd uart_0_external_connection_txd => CONNECTED_TO_uart_0_external_connection_txd -- .txd );
--------------------------------------------------------------------- ---- ---- ---- WISHBONE revB2 compl. I2C Master Core; top level ---- ---- ---- ---- ---- ---- Author: Richard Herveille ---- ---- richard@asics.ws ---- ---- www.asics.ws ---- ---- ---- ---- Downloaded from: http://www.opencores.org/projects/i2c/ ---- ---- ---- --------------------------------------------------------------------- ---- ---- ---- Copyright (C) 2000 Richard Herveille ---- ---- richard@asics.ws ---- ---- ---- ---- This source file may be used and distributed without ---- ---- restriction provided that this copyright statement is not ---- ---- removed from the file and that any derivative work contains ---- ---- the original copyright notice and the associated disclaimer.---- ---- ---- ---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ---- POSSIBILITY OF SUCH DAMAGE. ---- ---- ---- --------------------------------------------------------------------- -- CVS Log -- -- $Id: i2c_master_top.vhd,v 1.7 2004/03/14 10:17:03 rherveille Exp $ -- -- $Date: 2004/03/14 10:17:03 $ -- $Revision: 1.7 $ -- $Author: rherveille $ -- $Locker: $ -- $State: Exp $ -- -- Change History: -- $Log: i2c_master_top.vhd,v $ -- Revision 1.7 2004/03/14 10:17:03 rherveille -- Fixed simulation issue when writing to CR register -- -- Revision 1.6 2003/08/09 07:01:13 rherveille -- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. -- Fixed a potential bug in the byte controller's host-acknowledge generation. -- -- Revision 1.5 2003/02/01 02:03:06 rherveille -- Fixed a few 'arbitration lost' bugs. VHDL version only. -- -- Revision 1.4 2002/12/26 16:05:47 rherveille -- Core is now a Multimaster I2C controller. -- -- Revision 1.3 2002/11/30 22:24:37 rherveille -- Cleaned up code -- -- Revision 1.2 2001/11/10 10:52:44 rherveille -- Changed PRER reset value from 0x0000 to 0xffff, conform specs. -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity i2c_master_top is generic( ARST_LVL : std_logic := '0' -- asynchronous reset level ); port ( -- wishbone signals wb_clk_i : in std_logic; -- master clock input wb_rst_i : in std_logic := '0'; -- synchronous active high reset arst_i : in std_logic := not ARST_LVL; -- asynchronous reset wb_adr_i : in unsigned(2 downto 0); -- lower address bits wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output wb_we_i : in std_logic; -- Write enable input wb_stb_i : in std_logic; -- Strobe signals / core select signal wb_cyc_i : in std_logic; -- Valid bus cycle input wb_ack_o : out std_logic; -- Bus cycle acknowledge output wb_inta_o : out std_logic; -- interrupt request output signal -- i2c lines scl_pad_i : in std_logic; -- i2c clock line input scl_pad_o : out std_logic; -- i2c clock line output scl_padoen_o : out std_logic; -- i2c clock line output enable, active low sda_pad_i : in std_logic; -- i2c data line input sda_pad_o : out std_logic; -- i2c data line output sda_padoen_o : out std_logic -- i2c data line output enable, active low ); end entity i2c_master_top; architecture structural of i2c_master_top is component i2c_master_byte_ctrl is port ( clk : in std_logic; rst : in std_logic; -- synchronous active high reset (WISHBONE compatible) nReset : in std_logic; -- asynchornous active low reset (FPGA compatible) ena : in std_logic; -- core enable signal clk_cnt : in unsigned(15 downto 0); -- 4x SCL -- input signals start, stop, read, write, ack_in : std_logic; din : in std_logic_vector(7 downto 0); -- output signals cmd_ack : out std_logic; ack_out : out std_logic; i2c_busy : out std_logic; i2c_al : out std_logic; dout : out std_logic_vector(7 downto 0); -- i2c lines scl_i : in std_logic; -- i2c clock line input scl_o : out std_logic; -- i2c clock line output scl_oen : out std_logic; -- i2c clock line output enable, active low sda_i : in std_logic; -- i2c data line input sda_o : out std_logic; -- i2c data line output sda_oen : out std_logic -- i2c data line output enable, active low ); end component i2c_master_byte_ctrl; -- registers signal prer : unsigned(15 downto 0); -- clock prescale register signal ctr : std_logic_vector(7 downto 0); -- control register signal txr : std_logic_vector(7 downto 0); -- transmit register signal rxr : std_logic_vector(7 downto 0); -- receive register signal cr : std_logic_vector(7 downto 0); -- command register signal sr : std_logic_vector(7 downto 0); -- status register -- internal reset signal signal rst_i : std_logic; -- wishbone write access signal wb_wacc : std_logic; -- internal acknowledge signal signal iack_o : std_logic; -- done signal: command completed, clear command register signal done : std_logic; -- command register signals signal sta, sto, rd, wr, ack, iack : std_logic; signal core_en : std_logic; -- core enable signal signal ien : std_logic; -- interrupt enable signal -- status register signals signal irxack, rxack : std_logic; -- received aknowledge from slave signal tip : std_logic; -- transfer in progress signal irq_flag : std_logic; -- interrupt pending flag signal i2c_busy : std_logic; -- i2c bus busy (start signal detected) signal i2c_al, al : std_logic; -- arbitration lost begin -- generate internal reset signal rst_i <= arst_i xor ARST_LVL; -- generate acknowledge output signal gen_ack_o : process(wb_clk_i) begin if (wb_clk_i'event and wb_clk_i = '1') then iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored end if; end process gen_ack_o; wb_ack_o <= iack_o; -- generate wishbone write access signal wb_wacc <= wb_cyc_i and wb_stb_i and wb_we_i; -- assign wb_dat_o assign_dato : process(wb_clk_i) begin if (wb_clk_i'event and wb_clk_i = '1') then case wb_adr_i is when "000" => wb_dat_o <= std_logic_vector(prer( 7 downto 0)); when "001" => wb_dat_o <= std_logic_vector(prer(15 downto 8)); when "010" => wb_dat_o <= ctr; when "011" => wb_dat_o <= rxr; -- write is transmit register TxR when "100" => wb_dat_o <= sr; -- write is command register CR -- Debugging registers: -- These registers are not documented. -- Functionality could change in future releases when "101" => wb_dat_o <= txr; when "110" => wb_dat_o <= cr; when "111" => wb_dat_o <= (others => '0'); when others => wb_dat_o <= (others => 'X'); -- for simulation only end case; end if; end process assign_dato; -- generate registers (CR, SR see below) gen_regs: process(rst_i, wb_clk_i) begin if (rst_i = '0') then prer <= (others => '1'); ctr <= (others => '0'); txr <= (others => '0'); elsif (wb_clk_i'event and wb_clk_i = '1') then if (wb_rst_i = '1') then prer <= (others => '1'); ctr <= (others => '0'); txr <= (others => '0'); elsif (wb_wacc = '1') then case wb_adr_i is when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i); when "001" => prer(15 downto 8) <= unsigned(wb_dat_i); when "010" => ctr <= wb_dat_i; when "011" => txr <= wb_dat_i; when "100" => null; --write to CR, avoid executing the others clause -- illegal cases, for simulation only when others => report ("Illegal write address, setting all registers to unknown."); prer <= (others => 'X'); ctr <= (others => 'X'); txr <= (others => 'X'); end case; end if; end if; end process gen_regs; -- generate command register gen_cr: process(rst_i, wb_clk_i) begin if (rst_i = '0') then cr <= (others => '0'); elsif (wb_clk_i'event and wb_clk_i = '1') then if (wb_rst_i = '1') then cr <= (others => '0'); elsif (wb_wacc = '1') then if ( (core_en = '1') and (wb_adr_i = 4) ) then -- only take new commands when i2c core enabled -- pending commands are finished cr <= wb_dat_i; end if; else if (done = '1' or i2c_al = '1') then cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost end if; cr(2 downto 1) <= (others => '0'); -- reserved bits, always '0' cr(0) <= '0'; -- clear IRQ_ACK bit end if; end if; end process gen_cr; -- decode command register sta <= cr(7); sto <= cr(6); rd <= cr(5); wr <= cr(4); ack <= cr(3); iack <= cr(0); -- decode control register core_en <= ctr(7); ien <= ctr(6); -- hookup byte controller block byte_ctrl: i2c_master_byte_ctrl port map ( clk => wb_clk_i, rst => wb_rst_i, nReset => rst_i, ena => core_en, clk_cnt => prer, start => sta, stop => sto, read => rd, write => wr, ack_in => ack, i2c_busy => i2c_busy, i2c_al => i2c_al, din => txr, cmd_ack => done, ack_out => irxack, dout => rxr, scl_i => scl_pad_i, scl_o => scl_pad_o, scl_oen => scl_padoen_o, sda_i => sda_pad_i, sda_o => sda_pad_o, sda_oen => sda_padoen_o ); -- status register block + interrupt request signal st_irq_block : block begin -- generate status register bits gen_sr_bits: process (wb_clk_i, rst_i) begin if (rst_i = '0') then al <= '0'; rxack <= '0'; tip <= '0'; irq_flag <= '0'; elsif (wb_clk_i'event and wb_clk_i = '1') then if (wb_rst_i = '1') then al <= '0'; rxack <= '0'; tip <= '0'; irq_flag <= '0'; else al <= i2c_al or (al and not sta); rxack <= irxack; tip <= (rd or wr); -- interrupt request flag is always generated irq_flag <= (done or i2c_al or irq_flag) and not iack; end if; end if; end process gen_sr_bits; -- generate interrupt request signals gen_irq: process (wb_clk_i, rst_i) begin if (rst_i = '0') then wb_inta_o <= '0'; elsif (wb_clk_i'event and wb_clk_i = '1') then if (wb_rst_i = '1') then wb_inta_o <= '0'; else -- interrupt signal is only generated when IEN (interrupt enable bit) is set wb_inta_o <= irq_flag and ien; end if; end if; end process gen_irq; -- assign status register bits sr(7) <= rxack; sr(6) <= i2c_busy; sr(5) <= al; sr(4 downto 2) <= (others => '0'); -- reserved sr(1) <= tip; sr(0) <= irq_flag; end block; end architecture structural;
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE IEEE.STD_LOGIC_ARITH.all; USE IEEE.STD_LOGIC_UNSIGNED.all; ENTITY videolatch IS PORT( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; iDRAW : IN STD_LOGIC; iLPOS : IN STD_LOGIC_VECTOR(15 DOWNTO 0); iCHAR : IN STD_LOGIC_VECTOR(15 DOWNTO 0); oDRAW : out STD_LOGIC; oLPOS : out STD_LOGIC_VECTOR(15 DOWNTO 0); oCHAR : out STD_LOGIC_VECTOR(15 DOWNTO 0) ); END videolatch; ARCHITECTURE behavioral OF videolatch IS SIGNAL DRAW : STD_LOGIC := '0'; SIGNAL LPOS : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL CHAR : STD_LOGIC_VECTOR(15 DOWNTO 0); BEGIN process(clk) begin if(rising_edge(clk)) then oDRAW <= DRAW; oLPOS <= LPOS; oCHAR <= CHAR; end if; end process; process(iDRAW) begin if(rising_edge(iDRAW)) then DRAW <= iDRAW; LPOS <= iLPOS; CHAR <= iCHAR; -- Este bloco troca a cor do preto pelo branco: agora a cor "0000" = Branco ! if( iCHAR(11 downto 8) = "0000" ) then CHAR(11 downto 8) <= "1111"; elsif( iCHAR(11 downto 8) = "1111" ) then CHAR(11 downto 8) <= "0000"; end if; end if; end process; end architecture;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Package: virage_vcomponents -- File: virage_vcomponents.vhd -- Author: Jiri Gaisler, Gaisler Research -- Description: Simple simulation models for ACTEL RAM and pads ----------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; package virage_vcomponents is component hdss1_128x32cm4sw0b port ( addr, taddr : in std_logic_vector(6 downto 0); clk : in std_logic; di, tdi : in std_logic_vector(31 downto 0); do : out std_logic_vector(31 downto 0); me, oe, we, tme, twe, awt, biste, toe : in std_logic ); end component; component hdss1_256x32cm4sw0b port ( addr, taddr : in std_logic_vector(7 downto 0); clk : in std_logic; di, tdi : in std_logic_vector(31 downto 0); do : out std_logic_vector(31 downto 0); me, oe, we, tme, twe, awt, biste, toe : in std_logic ); end component; component hdss1_512x32cm4sw0b port ( addr, taddr : in std_logic_vector(8 downto 0); clk : in std_logic; di, tdi : in std_logic_vector(31 downto 0); do : out std_logic_vector(31 downto 0); me, oe, we, tme, twe, awt, biste, toe : in std_logic ); end component; component hdss1_1024x32cm4sw0b port ( addr, taddr : in std_logic_vector(9 downto 0); clk : in std_logic; di, tdi : in std_logic_vector(31 downto 0); do : out std_logic_vector(31 downto 0); me, oe, we, tme, twe, awt, biste, toe : in std_logic ); end component; component hdss1_2048x32cm8sw0b port ( addr, taddr : in std_logic_vector(10 downto 0); clk : in std_logic; di, tdi : in std_logic_vector(31 downto 0); do : out std_logic_vector(31 downto 0); me, oe, we, tme, twe, awt, biste, toe : in std_logic ); end component; component hdss1_4096x36cm8sw0b is port ( addr, taddr : in std_logic_vector(11 downto 0); clk : in std_logic; di, tdi : in std_logic_vector(35 downto 0); do : out std_logic_vector(35 downto 0); me, oe, we, tme, twe, awt, biste, toe : in std_logic ); end component; component hdss1_16384x8cm16sw0 is port ( addr : in std_logic_vector(13 downto 0); clk : in std_logic; di : in std_logic_vector(7 downto 0); do : out std_logic_vector(7 downto 0); me, oe, we : in std_logic ); end component; component rfss2_136x32cm2sw0b port ( addra, taddra : in std_logic_vector(7 downto 0); addrb, taddrb : in std_logic_vector(7 downto 0); clka, clkb : in std_logic; dia, tdia : in std_logic_vector(31 downto 0); dob : out std_logic_vector(31 downto 0); mea, wea, tmea, twea, bistea : in std_logic; meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic ); end component; component rfss2_168x32cm2sw0b port ( addra, taddra : in std_logic_vector(7 downto 0); addrb, taddrb : in std_logic_vector(7 downto 0); clka, clkb : in std_logic; dia, tdia : in std_logic_vector(31 downto 0); dob : out std_logic_vector(31 downto 0); mea, wea, tmea, twea, bistea : in std_logic; meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic ); end component; component hdss2_64x32cm4sw0b port ( addra, taddra : in std_logic_vector(5 downto 0); addrb, taddrb : in std_logic_vector(5 downto 0); clka, clkb : in std_logic; dia, tdia : in std_logic_vector(31 downto 0); dib, tdib : in std_logic_vector(31 downto 0); doa, dob : out std_logic_vector(31 downto 0); mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic; meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic ); end component; component hdss2_128x32cm4sw0b port ( addra, taddra : in std_logic_vector(6 downto 0); addrb, taddrb : in std_logic_vector(6 downto 0); clka, clkb : in std_logic; dia, tdia : in std_logic_vector(31 downto 0); dib, tdib : in std_logic_vector(31 downto 0); doa, dob : out std_logic_vector(31 downto 0); mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic; meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic ); end component; component hdss2_256x32cm4sw0b port ( addra, taddra : in std_logic_vector(7 downto 0); addrb, taddrb : in std_logic_vector(7 downto 0); clka, clkb : in std_logic; dia, tdia : in std_logic_vector(31 downto 0); dib, tdib : in std_logic_vector(31 downto 0); doa, dob : out std_logic_vector(31 downto 0); mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic; meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic ); end component; component hdss2_512x32cm4sw0b port ( addra, taddra : in std_logic_vector(8 downto 0); addrb, taddrb : in std_logic_vector(8 downto 0); clka, clkb : in std_logic; dia, tdia : in std_logic_vector(31 downto 0); dib, tdib : in std_logic_vector(31 downto 0); doa, dob : out std_logic_vector(31 downto 0); mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic; meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic ); end component; component hdss2_512x38cm4sw0b port ( addra, taddra : in std_logic_vector(8 downto 0); addrb, taddrb : in std_logic_vector(8 downto 0); clka, clkb : in std_logic; dia, tdia : in std_logic_vector(37 downto 0); dib, tdib : in std_logic_vector(37 downto 0); doa, dob : out std_logic_vector(37 downto 0); mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic; meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic ); end component; end;
library ieee; use ieee.std_logic_1164.all; use work.pgm_types.all; use work.read_funcs.all; use std.textio.all; entity test_read_funcs is end test_read_funcs; architecture behavioural of test_read_funcs is begin process variable image : pgm_image := read_pgm_image("example.pgm"); constant test_image : pixel_array(4 downto 0, 4 downto 0) := ((1,3,5,7,9), (2,2,1,1,1), (3,1,3,1,1), (4,1,1,4,1), (5,1,1,1,5)); begin assert image.rows = 5 report "image should show 5 rows" severity error; assert image.cols = 5 report "image should show 5 cols" severity error; assert image.maxval = 255 report "image should show 255 maxval" severity error; assert image.content.all = test_image report "image should match test image" severity error; wait; end process; end behavioural;
------------------------------------------------------------------------------- -- Title : i2s_serializer -- Author : Gideon Zweijtzer <gideon.zweijtzer@gmail.com> ------------------------------------------------------------------------------- -- Description: I2S Serializer / Deserializer ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity i2s_serializer is port ( clock : in std_logic; -- equals i2s_mclk reset : in std_logic; i2s_out : out std_logic; i2s_in : in std_logic; i2s_bclk : out std_logic; i2s_fs : out std_logic; sample_pulse : out std_logic; left_sample_out : out std_logic_vector(23 downto 0); right_sample_out : out std_logic_vector(23 downto 0); left_sample_in : in std_logic_vector(23 downto 0); right_sample_in : in std_logic_vector(23 downto 0) ); end entity; architecture rtl of i2s_serializer is signal bit_count : unsigned(7 downto 0); signal shift_reg : std_logic_vector(31 downto 0) := (others => '0'); begin -- mclk = 256*fs. bclk = 64*fs (32 bits per channel) process(clock) begin if rising_edge(clock) then bit_count <= bit_count + 1; i2s_bclk <= bit_count(1); i2s_fs <= bit_count(7); sample_pulse <= '0'; if bit_count(1 downto 0) = "00" then i2s_out <= shift_reg(shift_reg'left); elsif bit_count(1 downto 0) = "10" then shift_reg <= shift_reg(shift_reg'left-1 downto 0) & i2s_in; end if; case bit_count is when X"7E" => left_sample_out <= shift_reg(shift_reg'left-2 downto shift_reg'left - 25); when X"FE" => right_sample_out <= shift_reg(shift_reg'left-2 downto shift_reg'left - 25); sample_pulse <= '1'; when X"02" => shift_reg <= left_sample_in & "0000000" & i2s_in; when X"82" => shift_reg <= right_sample_in & "0000000" & i2s_in; when others => null; end case; if reset='1' then bit_count <= (others => '1'); i2s_out <= '0'; left_sample_out <= (others => '0'); right_sample_out <= (others => '0'); end if; end if; end process; end architecture;
-------------------------------------------------------------------------------- -- -- FIFO Generator Core Demo Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: FIFO_pkg.vhd -- -- Description: -- This is the demo testbench package file for FIFO Generator core. -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE ieee.std_logic_arith.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; PACKAGE FIFO_pkg IS FUNCTION divroundup ( data_value : INTEGER; divisor : INTEGER) RETURN INTEGER; ------------------------ FUNCTION if_then_else ( condition : BOOLEAN; true_case : INTEGER; false_case : INTEGER) RETURN INTEGER; ------------------------ FUNCTION if_then_else ( condition : BOOLEAN; true_case : STD_LOGIC; false_case : STD_LOGIC) RETURN STD_LOGIC; ------------------------ FUNCTION if_then_else ( condition : BOOLEAN; true_case : TIME; false_case : TIME) RETURN TIME; ------------------------ FUNCTION log2roundup ( data_value : INTEGER) RETURN INTEGER; ------------------------ FUNCTION hexstr_to_std_logic_vec( arg1 : string; size : integer ) RETURN std_logic_vector; ------------------------ COMPONENT FIFO_rng IS GENERIC (WIDTH : integer := 8; SEED : integer := 3); PORT ( CLK : IN STD_LOGIC; RESET : IN STD_LOGIC; ENABLE : IN STD_LOGIC; RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) ); END COMPONENT; ------------------------ COMPONENT FIFO_dgen IS GENERIC ( C_DIN_WIDTH : INTEGER := 32; C_DOUT_WIDTH : INTEGER := 32; C_CH_TYPE : INTEGER := 0; TB_SEED : INTEGER := 2 ); PORT ( RESET : IN STD_LOGIC; WR_CLK : IN STD_LOGIC; PRC_WR_EN : IN STD_LOGIC; FULL : IN STD_LOGIC; WR_EN : OUT STD_LOGIC; WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) ); END COMPONENT; ------------------------ COMPONENT FIFO_dverif IS GENERIC( C_DIN_WIDTH : INTEGER := 0; C_DOUT_WIDTH : INTEGER := 0; C_USE_EMBEDDED_REG : INTEGER := 0; C_CH_TYPE : INTEGER := 0; TB_SEED : INTEGER := 2 ); PORT( RESET : IN STD_LOGIC; RD_CLK : IN STD_LOGIC; PRC_RD_EN : IN STD_LOGIC; EMPTY : IN STD_LOGIC; DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); RD_EN : OUT STD_LOGIC; DOUT_CHK : OUT STD_LOGIC ); END COMPONENT; ------------------------ COMPONENT FIFO_pctrl IS GENERIC( AXI_CHANNEL : STRING := "NONE"; C_APPLICATION_TYPE : INTEGER := 0; C_DIN_WIDTH : INTEGER := 0; C_DOUT_WIDTH : INTEGER := 0; C_WR_PNTR_WIDTH : INTEGER := 0; C_RD_PNTR_WIDTH : INTEGER := 0; C_CH_TYPE : INTEGER := 0; FREEZEON_ERROR : INTEGER := 0; TB_STOP_CNT : INTEGER := 2; TB_SEED : INTEGER := 2 ); PORT( RESET_WR : IN STD_LOGIC; RESET_RD : IN STD_LOGIC; WR_CLK : IN STD_LOGIC; RD_CLK : IN STD_LOGIC; FULL : IN STD_LOGIC; EMPTY : IN STD_LOGIC; ALMOST_FULL : IN STD_LOGIC; ALMOST_EMPTY : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); DOUT_CHK : IN STD_LOGIC; PRC_WR_EN : OUT STD_LOGIC; PRC_RD_EN : OUT STD_LOGIC; RESET_EN : OUT STD_LOGIC; SIM_DONE : OUT STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; ------------------------ COMPONENT FIFO_synth IS GENERIC( FREEZEON_ERROR : INTEGER := 0; TB_STOP_CNT : INTEGER := 0; TB_SEED : INTEGER := 1 ); PORT( S_ACLK : IN STD_LOGIC; M_ACLK : IN STD_LOGIC; RESET : IN STD_LOGIC; SIM_DONE : OUT STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; ------------------------ COMPONENT FIFO_exdes IS PORT ( S_ARESETN : IN std_logic; M_AXIS_TVALID : OUT std_logic; M_AXIS_TREADY : IN std_logic; M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0); M_AXIS_TKEEP : OUT std_logic_vector(8-1 DOWNTO 0); M_AXIS_TLAST : OUT std_logic; S_AXIS_TVALID : IN std_logic; S_AXIS_TREADY : OUT std_logic; S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0); S_AXIS_TKEEP : IN std_logic_vector(8-1 DOWNTO 0); S_AXIS_TLAST : IN std_logic; AXIS_OVERFLOW : OUT std_logic; AXIS_UNDERFLOW : OUT std_logic; M_ACLK : IN std_logic; S_ACLK : IN std_logic); END COMPONENT; ------------------------ END FIFO_pkg; PACKAGE BODY FIFO_pkg IS FUNCTION divroundup ( data_value : INTEGER; divisor : INTEGER) RETURN INTEGER IS VARIABLE div : INTEGER; BEGIN div := data_value/divisor; IF ( (data_value MOD divisor) /= 0) THEN div := div+1; END IF; RETURN div; END divroundup; --------------------------------- FUNCTION if_then_else ( condition : BOOLEAN; true_case : INTEGER; false_case : INTEGER) RETURN INTEGER IS VARIABLE retval : INTEGER := 0; BEGIN IF condition=false THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; --------------------------------- FUNCTION if_then_else ( condition : BOOLEAN; true_case : STD_LOGIC; false_case : STD_LOGIC) RETURN STD_LOGIC IS VARIABLE retval : STD_LOGIC := '0'; BEGIN IF condition=false THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; --------------------------------- FUNCTION if_then_else ( condition : BOOLEAN; true_case : TIME; false_case : TIME) RETURN TIME IS VARIABLE retval : TIME := 0 ps; BEGIN IF condition=false THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; ------------------------------- FUNCTION log2roundup ( data_value : INTEGER) RETURN INTEGER IS VARIABLE width : INTEGER := 0; VARIABLE cnt : INTEGER := 1; BEGIN IF (data_value <= 1) THEN width := 1; ELSE WHILE (cnt < data_value) LOOP width := width + 1; cnt := cnt *2; END LOOP; END IF; RETURN width; END log2roundup; ------------------------------------------------------------------------------ -- hexstr_to_std_logic_vec -- This function converts a hex string to a std_logic_vector ------------------------------------------------------------------------------ FUNCTION hexstr_to_std_logic_vec( arg1 : string; size : integer ) RETURN std_logic_vector IS VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0'); VARIABLE bin : std_logic_vector(3 DOWNTO 0); VARIABLE index : integer := 0; BEGIN FOR i IN arg1'reverse_range LOOP CASE arg1(i) IS WHEN '0' => bin := (OTHERS => '0'); WHEN '1' => bin := (0 => '1', OTHERS => '0'); WHEN '2' => bin := (1 => '1', OTHERS => '0'); WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0'); WHEN '4' => bin := (2 => '1', OTHERS => '0'); WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0'); WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0'); WHEN '7' => bin := (3 => '0', OTHERS => '1'); WHEN '8' => bin := (3 => '1', OTHERS => '0'); WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0'); WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1'); WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1'); WHEN 'B' => bin := (2 => '0', OTHERS => '1'); WHEN 'b' => bin := (2 => '0', OTHERS => '1'); WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1'); WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1'); WHEN 'D' => bin := (1 => '0', OTHERS => '1'); WHEN 'd' => bin := (1 => '0', OTHERS => '1'); WHEN 'E' => bin := (0 => '0', OTHERS => '1'); WHEN 'e' => bin := (0 => '0', OTHERS => '1'); WHEN 'F' => bin := (OTHERS => '1'); WHEN 'f' => bin := (OTHERS => '1'); WHEN OTHERS => FOR j IN 0 TO 3 LOOP bin(j) := 'X'; END LOOP; END CASE; FOR j IN 0 TO 3 LOOP IF (index*4)+j < size THEN result((index*4)+j) := bin(j); END IF; END LOOP; index := index + 1; END LOOP; RETURN result; END hexstr_to_std_logic_vec; END FIFO_pkg;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --library ims; --use ims.coprocessor.all; entity MMX_MUL_8b is port ( INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0); INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0); OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0) ); end; architecture rtl of MMX_MUL_8b is begin ------------------------------------------------------------------------- -- synthesis translate_off process begin wait for 1 ns; REPORT "(IMS) MMX 8bis MUL RESSOURCE : ALLOCATION OK !"; wait; end process; -- synthesis translate_on ------------------------------------------------------------------------- ------------------------------------------------------------------------- computation : process (INPUT_1, INPUT_2) variable rTemp1 : STD_LOGIC_VECTOR(7 downto 0); variable rTemp2 : STD_LOGIC_VECTOR(7 downto 0); variable rTemp3 : STD_LOGIC_VECTOR(7 downto 0); variable rTemp4 : STD_LOGIC_VECTOR(7 downto 0); begin rTemp1 := STD_LOGIC_VECTOR( RESIZE(UNSIGNED(INPUT_1( 7 downto 0)) * UNSIGNED(INPUT_2( 7 downto 0)), 8) ); rTemp2 := STD_LOGIC_VECTOR( RESIZE(UNSIGNED(INPUT_1(15 downto 8)) * UNSIGNED(INPUT_2(15 downto 8)), 8) ); rTemp3 := STD_LOGIC_VECTOR( RESIZE(UNSIGNED(INPUT_1(23 downto 16)) * UNSIGNED(INPUT_2(23 downto 16)), 8) ); rTemp4 := STD_LOGIC_VECTOR( RESIZE(UNSIGNED(INPUT_1(31 downto 24)) * UNSIGNED(INPUT_2(31 downto 24)), 8) ); OUTPUT_1 <= (rTemp4 & rTemp3 & rTemp2 & rTemp1); end process; ------------------------------------------------------------------------- end;
--================================================================================================================================ -- Copyright 2020 Bitvis -- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. -- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT. -- -- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on -- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and limitations under the License. --================================================================================================================================ -- Note : Any functionality not explicitly described in the documentation is subject to change at any time ---------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------ -- Description : See library quick reference (under 'doc') and README-file(s) ------------------------------------------------------------------------------------------ -- WARNING! This package will be deprecated and no longer receive updates or bug fixes! -- The generic_queue_pkg in uvvm_util/src/generic_queue_pkg.vhd has replaced ti_generic_queue_pkg library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library uvvm_util; context uvvm_util.uvvm_util_context; package ti_generic_queue_pkg is generic (type t_generic_element; scope : string := C_SCOPE; GC_QUEUE_COUNT_MAX : natural := 1000; GC_QUEUE_COUNT_THRESHOLD : natural := 950); -- When find_* doesn't find a match, they return C_NO_MATCH. constant C_NO_MATCH : integer := -1; -- A generic queue for verification type t_generic_queue is protected procedure add( constant instance : in integer; constant element : in t_generic_element); procedure add( constant element : in t_generic_element); procedure put( constant instance : in integer; constant element : in t_generic_element); procedure put( constant element : in t_generic_element); impure function get( constant instance : in integer) return t_generic_element; impure function get( constant dummy : in t_void) return t_generic_element; impure function is_empty( constant instance : in integer) return boolean; impure function is_empty( constant dummy : in t_void) return boolean; procedure set_scope( constant instance : in integer; constant scope : in string); procedure set_scope( constant scope : in string); procedure set_name( constant name : in string); impure function get_scope( constant instance : in integer) return string; impure function get_scope( constant dummy : in t_void) return string; impure function get_count( constant instance : in integer) return natural; impure function get_count( constant dummy : in t_void) return natural; procedure set_queue_count_threshold( constant instance : in integer; constant queue_count_alert_level : in natural); procedure set_queue_count_threshold( constant queue_count_alert_level : in natural); impure function get_queue_count_threshold( constant instance : in integer) return natural; impure function get_queue_count_threshold( constant dummy : in t_void) return natural; impure function get_queue_count_threshold_severity( constant dummy : in t_void) return t_alert_level; procedure set_queue_count_threshold_severity( constant alert_level : in t_alert_level); impure function get_queue_count_max( constant instance : in integer) return natural; impure function get_queue_count_max( constant dummy : in t_void) return natural; procedure set_queue_count_max( constant instance : in integer; constant queue_count_max : in natural); procedure set_queue_count_max( constant queue_count_max : in natural); procedure flush( constant instance : in integer); procedure flush( constant dummy : in t_void); procedure reset( constant instance : in integer); procedure reset( constant dummy : in t_void); procedure insert( constant instance : in integer; constant identifier_option : in t_identifier_option; constant identifier : in positive; constant element : in t_generic_element); procedure insert( constant identifier_option : in t_identifier_option; constant identifier : in positive; constant element : in t_generic_element); procedure delete( constant instance : in integer; constant identifier_option : in t_identifier_option; constant identifier_min : in positive; constant identifier_max : in positive); procedure delete( constant identifier_option : in t_identifier_option; constant identifier_min : in positive; constant identifier_max : in positive); procedure delete( constant instance : in integer; constant element : in t_generic_element ); procedure delete( constant element : in t_generic_element ); procedure delete( constant instance : in integer; constant identifier_option : in t_identifier_option; constant identifier : in positive; constant range_option : in t_range_option ); procedure delete( constant identifier_option : in t_identifier_option; constant identifier : in positive; constant range_option : in t_range_option ); impure function peek( constant instance : in integer; constant identifier_option : in t_identifier_option; constant identifier : in positive ) return t_generic_element; impure function peek( constant identifier_option : in t_identifier_option; constant identifier : in positive ) return t_generic_element; impure function peek( constant instance : in integer ) return t_generic_element; impure function peek( constant dummy : in t_void ) return t_generic_element; impure function fetch( constant instance : in integer; constant identifier_option : in t_identifier_option; constant identifier : in positive ) return t_generic_element; impure function fetch( constant identifier_option : in t_identifier_option; constant identifier : in positive ) return t_generic_element; impure function fetch( constant instance : in integer ) return t_generic_element; impure function fetch( constant dummy : in t_void ) return t_generic_element; impure function find_position( constant element : in t_generic_element) return integer; impure function find_position( constant instance : in integer; constant element : in t_generic_element) return integer; impure function find_entry_num( constant element : in t_generic_element) return integer; impure function find_entry_num( constant instance : in integer; constant element : in t_generic_element) return integer; impure function exists( constant instance : in integer; constant element : in t_generic_element ) return boolean; impure function exists( constant element : in t_generic_element ) return boolean; impure function get_entry_num( constant instance : in integer; constant position_val : in positive) return integer; impure function get_entry_num( constant position_val : in positive) return integer; procedure print_queue( constant instance : in integer); procedure print_queue( constant dummy : in t_void); end protected; end package ti_generic_queue_pkg; package body ti_generic_queue_pkg is type t_generic_queue is protected body -- Types and control variables for the linked list implementation type t_element; type t_element_ptr is access t_element; type t_element is record entry_num : natural; next_element : t_element_ptr; element_data : t_generic_element; end record; type t_element_ptr_array is array(integer range 0 to C_MAX_QUEUE_INSTANCE_NUM) of t_element_ptr; type t_string_array is array(integer range 0 to C_MAX_QUEUE_INSTANCE_NUM) of string(1 to C_LOG_SCOPE_WIDTH); variable vr_last_element : t_element_ptr_array := (others => null); -- Back entry variable vr_first_element : t_element_ptr_array := (others => null); -- Front entry variable vr_num_elements_in_queue : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => 0); -- Scope variables variable vr_scope : t_string_array := (others => (others => NUL)); variable vr_scope_is_defined : boolean_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => false); -- Name variables variable vr_name : string(1 to C_LOG_SCOPE_WIDTH) := (others => NUL); variable vr_name_is_defined : boolean := false; variable vr_queue_count_max : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => GC_QUEUE_COUNT_MAX); variable vr_queue_count_threshold : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => GC_QUEUE_COUNT_THRESHOLD); variable vr_queue_count_threshold_severity : t_alert_level := TB_WARNING; variable vr_entry_num : integer_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => 0); -- Incremented before first insert -- Fill level alert type t_queue_count_threshold_alert_frequency is (ALWAYS, FIRST_TIME_ONLY); constant C_ALERT_FREQUENCY : t_queue_count_threshold_alert_frequency := FIRST_TIME_ONLY; variable vr_queue_count_threshold_triggered : boolean_vector(0 to C_MAX_QUEUE_INSTANCE_NUM) := (others => false); ------------------------------------------------------------------------------------------------------ -- -- Helper methods (not visible from outside) -- ------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------ -- Helper method: Check if an Alert shall be triggered (to be called before adding another entry) ------------------------------------------------------------------------------------------------------ procedure perform_pre_add_checks ( constant instance : in integer ) is begin if((vr_queue_count_threshold(instance) /= 0) and (vr_num_elements_in_queue(instance) >= vr_queue_count_threshold(instance))) then if((C_ALERT_FREQUENCY = ALWAYS) or (C_ALERT_FREQUENCY = FIRST_TIME_ONLY and not vr_queue_count_threshold_triggered(instance))) then alert(vr_queue_count_threshold_severity, "Queue is now at " & to_string(vr_queue_count_threshold(instance)) & " of " & to_string(vr_queue_count_max(instance)) & " elements.", vr_scope(instance)); vr_queue_count_threshold_triggered(instance) := true; end if; end if; end procedure; ------------------------------------------------------------------------------------------------------ -- Helper method: Iterate through all entries, and match the one with element_data = element -- This also works if the element is a record or array, whereas all entries/indexes must match ------------------------------------------------------------------------------------------------------ procedure match_element_data ( instance : in integer; -- Queue instance element : in t_generic_element; -- Element to search for found_match : out boolean; -- True if a match was found. matched_position : out integer; -- valid if found_match=true matched_element_ptr : out t_element_ptr -- valid if found_match=true ) is variable v_position_ctr : integer := 1; -- Keep track of POSITION when traversing the linked list variable v_element_ptr : t_element_ptr; -- Entry currently being checked for match begin -- Default found_match := false; matched_position := C_NO_MATCH; matched_element_ptr := null; if vr_num_elements_in_queue(instance) > 0 then -- Search from front to back element v_element_ptr := vr_first_element(instance); loop if v_element_ptr.element_data = element then -- Element matched entry found_match := true; matched_position := v_position_ctr; matched_element_ptr := v_element_ptr; exit; else -- No match. if v_element_ptr.next_element = null then exit; -- Last entry. All queue entries have been searched through. end if; v_element_ptr := v_element_ptr.next_element; -- next queue entry v_position_ctr := v_position_ctr + 1; end if; end loop; end if; end procedure; -- Find and return entry that matches the identifier procedure match_identifier ( instance : in integer; -- Queue instance identifier_option : in t_identifier_option; -- Determines what 'identifier' means identifier : in positive; -- Identifier value to search for found_match : out boolean; -- True if a match was found. matched_position : out integer; -- valid if found_match=true matched_element_ptr : out t_element_ptr; -- valid if found_match=true preceding_element_ptr : out t_element_ptr -- valid if found_match=true. Element at position-1, pointing to elemnt_ptr ) is -- Search from front to back element. Init pointers/counters to the first entry: variable v_element_ptr : t_element_ptr := vr_first_element(instance); -- Entry currently being checked for match variable v_position_ctr : integer := 1; -- Keep track of POSITION when traversing the linked list begin -- Default found_match := false; matched_position := C_NO_MATCH; matched_element_ptr := null; preceding_element_ptr := null; -- If queue is not empty and indentifier in valid range if (vr_num_elements_in_queue(instance) > 0) and ((identifier_option = POSITION and identifier <= vr_num_elements_in_queue(instance)) or (identifier_option = ENTRY_NUM and identifier <= vr_entry_num(instance))) then loop -- For each element in queue: -- Check if POSITION or ENTRY_NUM matches v_element_ptr if (identifier_option = POSITION) and (v_position_ctr = identifier) then found_match := true; end if; if (identifier_option = ENTRY_NUM) and (v_element_ptr.entry_num = identifier) then found_match := true; end if; if found_match then -- This element matched. Done searching. matched_position := v_position_ctr; matched_element_ptr := v_element_ptr; exit; else -- No match. if v_element_ptr.next_element = null then -- report "last v_position_ctr = " & to_string(v_position_ctr); exit; -- Last entry. All queue entries have been searched through. end if; preceding_element_ptr := v_element_ptr; -- the entry at the postition before element_ptr v_element_ptr := v_element_ptr.next_element; -- next queue entry v_position_ctr := v_position_ctr + 1; end if; end loop; -- for each element in queue end if; -- Not empty end procedure; ------------------------------------------------------------------------------------------------------ -- -- Public methods, visible from outside -- ------------------------------------------------------------------------------------------------------ -- add : Insert element in the back of queue, i.e. at the highest position procedure add( constant instance : in integer; constant element : in t_generic_element ) is constant proc_name : string := "add"; variable v_previous_ptr : t_element_ptr; begin check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER); perform_pre_add_checks(instance); check_value(vr_num_elements_in_queue(instance) < vr_queue_count_max(instance), TB_ERROR, proc_name & "() into generic queue (of size " & to_string(vr_queue_count_max(instance)) & ") when full", vr_scope(instance), ID_NEVER); -- Increment vr_entry_num vr_entry_num(instance) := vr_entry_num(instance)+1; -- Set read and write pointers when appending element to existing list if vr_num_elements_in_queue(instance) > 0 then v_previous_ptr := vr_last_element(instance); vr_last_element(instance) := new t_element'(entry_num => vr_entry_num(instance), next_element => null, element_data => element); v_previous_ptr.next_element := vr_last_element(instance); -- Insert the new element into the linked list else -- List is empty vr_last_element(instance) := new t_element'(entry_num => vr_entry_num(instance), next_element => null, element_data => element); vr_first_element(instance) := vr_last_element(instance); -- Update read pointer, since this is the first and only element in the list. end if; -- Increment number of elements vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) + 1; end procedure; procedure add( constant element : in t_generic_element ) is begin add(1, element); end procedure; procedure put( constant instance : in integer; constant element : in t_generic_element ) is begin add(instance, element); end procedure; procedure put( constant element : in t_generic_element ) is begin put(1, element); end procedure; impure function get( constant instance : in integer ) return t_generic_element is begin return fetch(instance); end function; impure function get( constant dummy : in t_void ) return t_generic_element is begin return get(1); end function; procedure flush( constant instance : in integer ) is variable v_to_be_deallocated_ptr : t_element_ptr; begin check_value(vr_scope_is_defined(instance), TB_WARNING, "Scope name must be defined for this generic queue " &to_string(instance), "???", ID_NEVER); -- Deallocate all entries in the list -- Setting the last element to null and iterating over the queue until finding the null element vr_last_element(instance) := null; while vr_first_element(instance) /= null loop v_to_be_deallocated_ptr := vr_first_element(instance); vr_first_element(instance) := vr_first_element(instance).next_element; DEALLOCATE(v_to_be_deallocated_ptr); end loop; -- Reset the queue counter vr_num_elements_in_queue(instance) := 0; vr_queue_count_threshold_triggered(instance) := false; end procedure; procedure flush( constant dummy : in t_void ) is begin flush(1); end procedure; procedure reset( constant instance : in integer) is begin flush(instance); vr_entry_num(instance) := 0; -- Incremented before first insert end procedure; procedure reset( constant dummy : in t_void) is begin reset(1); end procedure; impure function is_empty( constant instance : in integer ) return boolean is begin if vr_num_elements_in_queue(instance) = 0 then return true; else return false; end if; end function; impure function is_empty( constant dummy : in t_void ) return boolean is begin return is_empty(1); end function; procedure set_scope( constant instance : in integer; constant scope : in string) is begin if instance = ALL_INSTANCES then if scope'length > C_LOG_SCOPE_WIDTH then vr_scope := (others => scope(1 to C_LOG_SCOPE_WIDTH)); else for idx in vr_scope'range loop vr_scope(idx) := (others => NUL); vr_scope(idx)(1 to scope'length) := scope; end loop; end if; vr_scope_is_defined := (others => true); else if scope'length > C_LOG_SCOPE_WIDTH then vr_scope(instance) := scope(1 to C_LOG_SCOPE_WIDTH); else vr_scope(instance) := (others => NUL); vr_scope(instance)(1 to scope'length) := scope; end if; vr_scope_is_defined(instance) := true; end if; end procedure; procedure set_scope( constant scope : in string) is begin set_scope(1, scope); end procedure; procedure set_name( constant name : in string) is begin vr_name(1 to name'length) := name; vr_name_is_defined := true; end procedure; impure function get_scope( constant instance : in integer ) return string is begin return to_string(vr_scope(instance)); end function; impure function get_scope( constant dummy : in t_void ) return string is begin return get_scope(1); end function; impure function get_count( constant instance : in integer ) return natural is begin return vr_num_elements_in_queue(instance); end function; impure function get_count( constant dummy : in t_void ) return natural is begin return get_count(1); end function; impure function get_queue_count_max( constant instance : in integer ) return natural is begin return vr_queue_count_max(instance); end function; impure function get_queue_count_max( constant dummy : in t_void ) return natural is begin return get_queue_count_max(1); end function; procedure set_queue_count_max( constant instance : in integer; constant queue_count_max : in natural ) is begin vr_queue_count_max(instance) := queue_count_max; check_value(vr_num_elements_in_queue(instance) < vr_queue_count_max(instance), TB_ERROR, "set_queue_count_max() new queue max count (" & to_string(vr_queue_count_max(instance)) & ") is less than current queue count(" & to_string(vr_num_elements_in_queue(instance)) & ").", vr_scope(instance), ID_NEVER); end procedure; procedure set_queue_count_max( constant queue_count_max : in natural ) is begin set_queue_count_max(1, queue_count_max); end procedure; procedure set_queue_count_threshold( constant instance : in integer; constant queue_count_alert_level : in natural ) is begin vr_queue_count_threshold(instance) := queue_count_alert_level; end procedure; procedure set_queue_count_threshold( constant queue_count_alert_level : in natural ) is begin set_queue_count_threshold(1, queue_count_alert_level); end procedure; impure function get_queue_count_threshold( constant instance : in integer ) return natural is begin return vr_queue_count_threshold(instance); end function; impure function get_queue_count_threshold( constant dummy : in t_void ) return natural is begin return get_queue_count_threshold(1); end function; impure function get_queue_count_threshold_severity( constant dummy : in t_void ) return t_alert_level is begin return vr_queue_count_threshold_severity; end function; procedure set_queue_count_threshold_severity( constant alert_level : in t_alert_level) is begin vr_queue_count_threshold_severity := alert_level; end procedure; ---------------------------------------------------- -- Insert: ---------------------------------------------------- -- Inserts element into the queue after the matching entry with specified identifier: -- -- When identifier_option = POSITION: -- identifier = position in queue, counting from 1 -- -- When identifier_option = ENTRY_NUM: -- identifier = entry number, counting from 1 procedure insert( constant instance : in integer; constant identifier_option : in t_identifier_option; constant identifier : in positive; constant element : in t_generic_element) is constant proc_name : string := "insert"; variable v_element_ptr : t_element_ptr; -- The element currently being processed variable v_new_element_ptr : t_element_ptr; -- Used when creating a new element variable v_preceding_element_ptr : t_element_ptr; -- Used when creating a new element variable v_found_match : boolean; variable v_matched_position : integer; begin -- pre insert checks check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER); perform_pre_add_checks(instance); check_value(vr_num_elements_in_queue(instance) < vr_queue_count_max(instance), TB_ERROR, proc_name & "() into generic queue (of size " & to_string(vr_queue_count_max(instance)) & ") when full", vr_scope(instance), ID_NEVER); check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, proc_name & "() into empty queue isn't supported. Use add() instead", vr_scope(instance), ID_NEVER); if identifier_option = POSITION then check_value(vr_num_elements_in_queue(instance) >= identifier, TB_ERROR, proc_name & "() into position larger than number of elements in queue. Use add() instead when inserting at the back of the queue", vr_scope(instance), ID_NEVER); end if; -- Search from front to back element. match_identifier( instance => instance , identifier_option => identifier_option , identifier => identifier , found_match => v_found_match , matched_position => v_matched_position , matched_element_ptr => v_element_ptr , preceding_element_ptr => v_preceding_element_ptr ); if v_found_match then -- Make new element vr_entry_num(instance) := vr_entry_num(instance)+1; -- Increment vr_entry_num -- POSITION: insert at matched position if identifier_option = POSITION then v_new_element_ptr := new t_element'(entry_num => vr_entry_num(instance), next_element => v_element_ptr, element_data => element); -- if match is first element if v_preceding_element_ptr = null then vr_first_element(instance) := v_new_element_ptr; -- Insert the new element into the front of the linked list else v_preceding_element_ptr.next_element := v_new_element_ptr; -- Insert the new element into the linked list end if; --ENTRY_NUM: insert at position after match else v_new_element_ptr := new t_element'(entry_num => vr_entry_num(instance), next_element => v_element_ptr.next_element, element_data => element); v_element_ptr.next_element := v_new_element_ptr; -- Insert the new element into the linked list end if; vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) + 1; -- Increment number of elements elsif identifier_option = ENTRY_NUM then if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " & "instance=" & to_string(instance) & ", identifier_option=" & t_identifier_option'image(identifier_option) & ", identifier=" & to_string(identifier) & ", element...", scope); end if; end if; end procedure; procedure insert( constant identifier_option : in t_identifier_option; constant identifier : in positive; constant element : in t_generic_element) is begin insert(1, identifier_option, identifier, element); end procedure; ---------------------------------------------------- -- delete: ---------------------------------------------------- -- Read and remove the entry matching the identifier -- -- When identifier_option = POSITION: -- identifier = position in queue, counting from 1 -- -- When identifier_option = ENTRY_NUM: -- identifier = entry number, counting from 1 procedure delete( constant instance : in integer; constant identifier_option : in t_identifier_option; constant identifier_min : in positive; constant identifier_max : in positive ) is constant proc_name : string := "delete"; variable v_matched_element_ptr : t_element_ptr; -- The element being deleted variable v_element_to_delete_ptr : t_element_ptr; -- The element being deleted variable v_matched_element_data : t_generic_element; -- Return value variable v_preceding_element_ptr : t_element_ptr; variable v_matched_position : integer; variable v_found_match : boolean; variable v_deletes_remaining : integer; begin check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER); if(vr_num_elements_in_queue(instance) < vr_queue_count_threshold(instance)) then -- reset alert trigger if set vr_queue_count_threshold_triggered(instance) := false; end if; -- delete based on POSITION : -- Note that when deleting the first position, all above positions are decremented by one. -- Find the identifier_min, delete it, and following next_element until we reach number of positions to delete if (identifier_option = POSITION) then check_value(vr_num_elements_in_queue(instance) >= identifier_max, TB_ERROR, proc_name & " where identifier_max > generic queue size", vr_scope(instance), ID_NEVER); check_value(identifier_max >= identifier_min, TB_ERROR, "Check that identifier_max >= identifier_min", vr_scope(instance), ID_NEVER); v_deletes_remaining := 1 + identifier_max - identifier_min; -- Find min position match_identifier( instance => instance , identifier_option => identifier_option , identifier => identifier_min, found_match => v_found_match , matched_position => v_matched_position , matched_element_ptr => v_matched_element_ptr , preceding_element_ptr => v_preceding_element_ptr ); if v_found_match then v_element_to_delete_ptr := v_matched_element_ptr; -- Delete element at identifier_min first while v_deletes_remaining > 0 loop -- Update pointer to the element about to be removed. if (v_preceding_element_ptr = null) then -- Removing the first entry, vr_first_element(instance) := vr_first_element(instance).next_element; else -- Removing an intermediate or last entry v_preceding_element_ptr.next_element := v_element_to_delete_ptr.next_element; -- If the element is the last entry, update vr_last_element if v_element_to_delete_ptr.next_element = null then vr_last_element(instance) := v_preceding_element_ptr; end if; end if; -- Decrement number of elements vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) - 1; -- Memory management DEALLOCATE(v_element_to_delete_ptr); v_deletes_remaining := v_deletes_remaining - 1; -- Prepare next iteration: -- Next element to delete: if v_deletes_remaining > 0 then if (v_preceding_element_ptr = null) then -- We just removed the first entry, so there's no pointer from a preceding entry. Next to delete is the first entry. v_element_to_delete_ptr := vr_first_element(instance); else -- Removed an intermediate or last entry. Next to delete is the pointer from the preceding element v_element_to_delete_ptr := v_preceding_element_ptr.next_element; end if; end if; end loop; else -- v_found_match if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " & "instance=" & to_string(instance) & ", identifier_option=" & t_identifier_option'image(identifier_option) & ", identifier_min=" & to_string(identifier_min) & ", identifier_max=" & to_string(identifier_max) & ", non-matching identifier=" & to_string(identifier_min), scope); end if; end if; -- v_found_match -- delete based on ENTRY_NUM : -- Unlike position, an entry's Entry_num is stable when deleting other entries -- Entry_num is not necessarily increasing as we follow next_element pointers. -- This means that we must do a complete search for each entry we want to delete elsif (identifier_option = ENTRY_NUM) then check_value(vr_entry_num(instance) >= identifier_max, TB_ERROR, proc_name & " where identifier_max > highest entry number", vr_scope(instance), ID_NEVER); check_value(identifier_max >= identifier_min, TB_ERROR, "Check that identifier_max >= identifier_min", vr_scope(instance), ID_NEVER); v_deletes_remaining := 1 + identifier_max - identifier_min; -- For each entry to delete, find it based on entry_num , then delete it for identifier in identifier_min to identifier_max loop match_identifier( instance => instance , identifier_option => identifier_option , identifier => identifier, found_match => v_found_match , matched_position => v_matched_position , matched_element_ptr => v_matched_element_ptr , preceding_element_ptr => v_preceding_element_ptr ); if v_found_match then v_element_to_delete_ptr := v_matched_element_ptr; -- Update pointer to the element about to be removed. if (v_preceding_element_ptr = null) then -- Removing the first entry, vr_first_element(instance) := vr_first_element(instance).next_element; else -- Removing an intermediate or last entry v_preceding_element_ptr.next_element := v_element_to_delete_ptr.next_element; -- If the element is the last entry, update vr_last_element if v_element_to_delete_ptr.next_element = null then vr_last_element(instance) := v_preceding_element_ptr; end if; end if; -- Decrement number of elements vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) - 1; -- Memory management DEALLOCATE(v_element_to_delete_ptr); else -- v_found_match if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " & "instance=" & to_string(instance) & ", identifier_option=" & t_identifier_option'image(identifier_option) & ", identifier_min=" & to_string(identifier_min) & ", identifier_max=" & to_string(identifier_max) & ", non-matching identifier=" & to_string(identifier), scope); end if; end if; -- v_found_match end loop; end if; -- identifier_option end procedure; procedure delete( constant identifier_option : in t_identifier_option; constant identifier_min : in positive; constant identifier_max : in positive ) is begin delete(1, identifier_option, identifier_min, identifier_max); end procedure; procedure delete( constant instance : in integer; constant element : in t_generic_element ) is variable v_entry_num : integer:= find_entry_num(element); begin delete(instance, ENTRY_NUM, v_entry_num, v_entry_num); end procedure; procedure delete( constant element : in t_generic_element ) is begin delete(1, element); end procedure; procedure delete( constant instance : in integer; constant identifier_option : in t_identifier_option; constant identifier : in positive; constant range_option : in t_range_option ) is begin case range_option is when SINGLE => delete(instance, identifier_option, identifier, identifier); when AND_LOWER => delete(instance, identifier_option, 1, identifier); when AND_HIGHER => if identifier_option = POSITION then delete(instance, identifier_option, identifier, vr_num_elements_in_queue(instance)); elsif identifier_option = ENTRY_NUM then delete(instance, identifier_option, identifier, vr_entry_num(instance)); end if; end case; end procedure; procedure delete( constant identifier_option : in t_identifier_option; constant identifier : in positive; constant range_option : in t_range_option ) is begin delete(1, identifier_option, identifier, range_option); end procedure; ---------------------------------------------------- -- peek: ---------------------------------------------------- -- Read the entry matching the identifier, but don't remove it. -- -- When identifier_option = POSITION: -- identifier = position in queue, counting from 1 -- -- When identifier_option = ENTRY_NUM: -- identifier = entry number, counting from 1 impure function peek( constant instance : in integer; constant identifier_option : in t_identifier_option; constant identifier : in positive ) return t_generic_element is constant proc_name : string := "peek"; variable v_matched_element_data : t_generic_element; -- Return value variable v_matched_element_ptr : t_element_ptr; -- The element currently being processed variable v_preceding_element_ptr : t_element_ptr; variable v_matched_position : integer; -- Keep track of POSITION when traversing the linked list variable v_found_match : boolean := false; begin check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER); check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, proc_name & "() from generic queue when empty", vr_scope(instance), ID_NEVER); match_identifier( instance => instance , identifier_option => identifier_option , identifier => identifier , found_match => v_found_match , matched_position => v_matched_position , matched_element_ptr => v_matched_element_ptr , preceding_element_ptr => v_preceding_element_ptr ); if v_found_match then v_matched_element_data := v_matched_element_ptr.element_data; else if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " & "instance=" & to_string(instance) & ", identifier_option=" & t_identifier_option'image(identifier_option) & ", identifier=" & to_string(identifier), scope); end if; end if; return v_matched_element_data; end function; impure function peek( constant identifier_option : in t_identifier_option; constant identifier : in positive ) return t_generic_element is begin return peek(1, identifier_option, identifier); end function; -- If no identifier is specified, return the oldest entry (first position) impure function peek( constant instance : in integer ) return t_generic_element is begin return peek(instance, POSITION, 1); end function; impure function peek( constant dummy : in t_void ) return t_generic_element is begin return peek(1); end function; ---------------------------------------------------- -- Fetch: ---------------------------------------------------- -- Read and remove the entry matching the identifier -- -- When identifier_option = POSITION: -- identifier = position in queue, counting from 1 -- -- When identifier_option = ENTRY_NUM: -- identifier = entry number, counting from 1 impure function fetch( constant instance : in integer; constant identifier_option : in t_identifier_option; constant identifier : in positive ) return t_generic_element is constant proc_name : string := "fetch"; variable v_matched_element_ptr : t_element_ptr; -- The element being fetched variable v_matched_element_data : t_generic_element; -- Return value variable v_preceding_element_ptr : t_element_ptr; variable v_matched_position : integer; variable v_found_match : boolean; begin check_value(vr_scope_is_defined(instance), TB_WARNING, proc_name & ": Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER); check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, proc_name & "() from generic queue when empty", vr_scope(instance), ID_NEVER); if(vr_num_elements_in_queue(instance) < vr_queue_count_threshold(instance)) then -- reset alert trigger if set vr_queue_count_threshold_triggered(instance) := false; end if; match_identifier( instance => instance , identifier_option => identifier_option , identifier => identifier , found_match => v_found_match , matched_position => v_matched_position , matched_element_ptr => v_matched_element_ptr , preceding_element_ptr => v_preceding_element_ptr ); if v_found_match then -- Keep info about element before removing it from queue v_matched_element_data := v_matched_element_ptr.element_data; -- Update pointer to the element about to be removed. if (v_preceding_element_ptr = null) then -- Removing the first entry, vr_first_element(instance) := vr_first_element(instance).next_element; else -- Removing an intermediate or last entry v_preceding_element_ptr.next_element := v_matched_element_ptr.next_element; -- If the element is the last entry, update vr_last_element if v_matched_element_ptr.next_element = null then vr_last_element(instance) := v_preceding_element_ptr; end if; end if; -- Decrement number of elements vr_num_elements_in_queue(instance) := vr_num_elements_in_queue(instance) - 1; -- Memory management DEALLOCATE(v_matched_element_ptr); else if (vr_num_elements_in_queue(instance) > 0) then -- if not already reported tb_error due to empty tb_error(proc_name & "() did not match an element in queue. It was called with the following parameters: " & "instance=" & to_string(instance) & ", identifier_option=" & t_identifier_option'image(identifier_option) & ", identifier=" & to_string(identifier), scope); end if; end if; return v_matched_element_data; end function; impure function fetch( constant identifier_option : in t_identifier_option; constant identifier : in positive ) return t_generic_element is begin return fetch(1, identifier_option, identifier); end function; -- If no identifier is specified, return the oldest entry (first position) impure function fetch( constant instance : in integer ) return t_generic_element is begin return fetch(instance, POSITION, 1); end function; impure function fetch( constant dummy : in t_void ) return t_generic_element is begin return fetch(1); end function; -- Returns position of entry if found, else C_NO_MATCH. impure function find_position( constant instance : in integer; constant element : in t_generic_element -- ) return integer is variable v_element_ptr : t_element_ptr; variable v_matched_position : integer; variable v_found_match : boolean; begin check_value(vr_scope_is_defined(instance), TB_WARNING, "find_position: Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER); -- Don't include this check, because we may want to use exists() on an empty queue. -- check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, "find_position() from generic queue when empty", vr_scope(instance), ID_NEVER); match_element_data( instance => instance, element => element, found_match => v_found_match, matched_position => v_matched_position, matched_element_ptr => v_element_ptr ); if v_found_match then return v_matched_position; else return C_NO_MATCH; end if; end function; impure function find_position( constant element : in t_generic_element ) return integer is begin return find_position(1, element); end function; impure function exists( constant instance : in integer; constant element : in t_generic_element ) return boolean is begin return (find_position(instance, element) /= C_NO_MATCH); end function; impure function exists( constant element : in t_generic_element ) return boolean is begin return exists(1, element); end function; -- Returns entry number or position to entry if found, else C_NO_MATCH. impure function find_entry_num( constant instance : in integer; constant element : in t_generic_element ) return integer is variable v_element_ptr : t_element_ptr; variable v_matched_position : integer; variable v_found_match : boolean; begin check_value(vr_scope_is_defined(instance), TB_WARNING, "find_entry_num(): Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER); check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, "find_entry_num() from generic queue when empty", vr_scope(instance), ID_NEVER); match_element_data( instance => instance, element => element, found_match => v_found_match, matched_position => v_matched_position, matched_element_ptr => v_element_ptr ); if v_found_match then return v_element_ptr.entry_num; else return C_NO_MATCH; end if; end function; impure function find_entry_num( constant element : in t_generic_element ) return integer is begin return find_entry_num(1, element); end function; impure function get_entry_num( constant instance : in integer; constant position_val : in positive ) return integer is variable v_found_match : boolean; variable v_matched_position : integer; variable v_matched_element_ptr : t_element_ptr; variable v_preceding_element_ptr : t_element_ptr; begin check_value(vr_scope_is_defined(instance), TB_WARNING, "get_entry_num(): Scope name must be defined for this generic queue", vr_scope(instance), ID_NEVER); check_value(vr_num_elements_in_queue(instance) > 0, TB_ERROR, "get_entry_num() from generic queue when empty", vr_scope(instance), ID_NEVER); match_identifier( instance => instance , identifier_option => POSITION , identifier => position_val, found_match => v_found_match , matched_position => v_matched_position , matched_element_ptr => v_matched_element_ptr , preceding_element_ptr => v_preceding_element_ptr ); if v_found_match then return v_matched_element_ptr.entry_num; else return -1; end if; end function get_entry_num; impure function get_entry_num( constant position_val : in positive ) return integer is begin return get_entry_num(1, position_val); end function get_entry_num; -- for debugging: -- print each entry's position and entry_num procedure print_queue( constant instance : in integer ) is variable v_element_ptr : t_element_ptr; -- The element currently being processed variable v_new_element_ptr : t_element_ptr; -- Used when creating a new element variable v_position_ctr : natural := 1; -- Keep track of POSITION when traversing the linked list variable v_found_match : boolean := false; begin -- Search from front to back element. Initalise pointers/counters to the first entry: v_element_ptr := vr_first_element(instance); if v_element_ptr = NULL then return; -- Return if queue is empty end if; loop log(ID_UVVM_DATA_QUEUE, "Pos=" & to_string(v_position_ctr) & ", entry_num=" & to_string(v_element_ptr.entry_num) , scope); if v_element_ptr.next_element = null then exit; -- Last entry. All queue entries have been searched through. end if; v_element_ptr := v_element_ptr.next_element; -- next queue entry v_position_ctr := v_position_ctr + 1; end loop; end procedure; procedure print_queue( constant dummy : in t_void) is begin print_queue(1); end procedure; end protected body; end package body ti_generic_queue_pkg;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003, Gaisler Research -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- package: uart -- File: uart.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: UART types and components ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; package uart is type uart_in_type is record rxd : std_ulogic; ctsn : std_ulogic; extclk : std_ulogic; end record; type uart_out_type is record rtsn : std_ulogic; txd : std_ulogic; scaler : std_logic_vector(17 downto 0); txen : std_ulogic; flow : std_ulogic; rxen : std_ulogic; end record; component apbuart generic ( pindex : integer := 0; paddr : integer := 0; pmask : integer := 16#fff#; console : integer := 0; pirq : integer := 0; parity : integer := 1; flow : integer := 1; fifosize : integer range 1 to 32 := 1; abits : integer := 8); port ( rst : in std_ulogic; clk : in std_ulogic; apbi : in apb_slv_in_type; apbo : out apb_slv_out_type; uarti : in uart_in_type; uarto : out uart_out_type); end component; component ahbuart generic ( hindex : integer := 0; pindex : integer := 0; paddr : integer := 0; pmask : integer := 16#fff# ); port ( rst : in std_ulogic; clk : in std_ulogic; uarti : in uart_in_type; uarto : out uart_out_type; apbi : in apb_slv_in_type; apbo : out apb_slv_out_type; ahbi : in ahb_mst_in_type; ahbo : out ahb_mst_out_type ); end component; end;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003, Gaisler Research -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- package: uart -- File: uart.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: UART types and components ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; package uart is type uart_in_type is record rxd : std_ulogic; ctsn : std_ulogic; extclk : std_ulogic; end record; type uart_out_type is record rtsn : std_ulogic; txd : std_ulogic; scaler : std_logic_vector(17 downto 0); txen : std_ulogic; flow : std_ulogic; rxen : std_ulogic; end record; component apbuart generic ( pindex : integer := 0; paddr : integer := 0; pmask : integer := 16#fff#; console : integer := 0; pirq : integer := 0; parity : integer := 1; flow : integer := 1; fifosize : integer range 1 to 32 := 1; abits : integer := 8); port ( rst : in std_ulogic; clk : in std_ulogic; apbi : in apb_slv_in_type; apbo : out apb_slv_out_type; uarti : in uart_in_type; uarto : out uart_out_type); end component; component ahbuart generic ( hindex : integer := 0; pindex : integer := 0; paddr : integer := 0; pmask : integer := 16#fff# ); port ( rst : in std_ulogic; clk : in std_ulogic; uarti : in uart_in_type; uarto : out uart_out_type; apbi : in apb_slv_in_type; apbo : out apb_slv_out_type; ahbi : in ahb_mst_in_type; ahbo : out ahb_mst_out_type ); end component; end;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- Copyright (C) 2015 - 2016, Cobham Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- -- Entity: i2c2ahbx -- File: i2c2ahbx.vhd -- Author: Jan Andersson - Aeroflex Gaisler AB -- Contact: support@gaisler.com -- Description: Simple I2C-slave providing a bridge to AMBA AHB -- This entity is typically wrapped with i2c2ahb or i2c2ahb_apb -- before use. ------------------------------------------------------------------------------- -- -- Short core documentation, for additional information see the GRLIB IP -- Library User's Manual (GRIP): -- -- The core functions as a I2C memory device. To write to the core, issue the -- following I2C bus sequence: -- -- 0. START condition -- 1. Send core's I2C address with direction = write -- 2. Send 32-bit address to be used for AMBA bus -- 3. Send data to be written -- -- The core will expect 32-bits of data and write these as a word. This can be -- changed by writing to the core's control register. See documentation further -- down. When the core's internal FIFO is full, the core will use clock -- stretching to stall the transfer. -- -- To write to the core, issue the following I2C bus sequence: -- -- 0. START condition -- 1. Send core's I2C address with direction = write -- 2. Send 32-bit address to be used for AMBA bus -- 3. Send repeated start condition -- 4. Send core's I2C address with direction = read -- 5. Read bytes -- -- The core will perform 32-bit data accesses to fill its internal buffer. This -- can be changed by writing to the core's control register (see documentation -- further down). When the buffer is empty the core will use clock stretching -- to stall the transfer. -- -- The cores control/status register is accessed via address i2caddr + 1. The -- register has the following layout: -- -- +--------+-----------------------------------------------------------------+ -- | Bit(s) | Description | -- +--------+-----------------------------------------------------------------+ -- | 7:6 | Reserved, always zero (RO) | -- | 5 | PROT: Memory protection triggered. Last access was outside | -- | | range. Updated after each AMBA access (RO) | -- | 4 | MEXC: Memory exception. Gets set if core receives AMBA ERROR | -- | | response. Updated after each AMBA access. (RO) | -- | 3 | DMAACT: Core is currently performing DMA (RO) | -- | 2 | NACK: NACK instead of using clock stretching (RW) | -- | 1:0 | HSIZE: Controls the access size core will use for AMBA accesses | -- | | Default is HSIZE = WORD. HSIZE 11 is illegal (RW) | -- +--------+-----------------------------------------------------------------+ -- -- Documentation of generics: -- -- [hindex] AHB master index -- -- [oepol] Output enable polarity -- -- [filter] Length of filters used on SCL and SDA -- library ieee; use ieee.std_logic_1164.all; library gaisler; use gaisler.i2c.all; library grlib; use grlib.amba.all; use grlib.devices.all; use grlib.stdlib.all; entity i2c2ahbx is generic ( -- AHB configuration hindex : integer := 0; oepol : integer range 0 to 1 := 0; filter : integer range 2 to 512 := 2 ); port ( rstn : in std_ulogic; clk : in std_ulogic; -- AHB master interface ahbi : in ahb_mst_in_type; ahbo : out ahb_mst_out_type; -- I2C signals i2ci : in i2c_in_type; i2co : out i2c_out_type; -- i2c2ahbi : in i2c2ahb_in_type; i2c2ahbo : out i2c2ahb_out_type ); end entity i2c2ahbx; architecture rtl of i2c2ahbx is ----------------------------------------------------------------------------- -- Constants ----------------------------------------------------------------------------- constant OEPOL_LEVEL : std_ulogic := conv_std_logic(oepol = 1); constant I2C_LOW : std_ulogic := OEPOL_LEVEL; -- OE constant I2C_HIZ : std_ulogic := not OEPOL_LEVEL; constant I2C_ACK : std_ulogic := '0'; ----------------------------------------------------------------------------- -- Types ----------------------------------------------------------------------------- type i2c_in_array is array (filter downto 0) of i2c_in_type; type state_type is (idle, checkaddr, sclhold, movebyte, handshake); type i2c2ahb_reg_type is record state : state_type; -- haddr : std_logic_vector(31 downto 0); hdata : std_logic_vector(31 downto 0); hsize : std_logic_vector(1 downto 0); hwrite : std_ulogic; mexc : std_ulogic; dodma : std_ulogic; nack : std_ulogic; prot : std_ulogic; -- Transfer phase i2caddr : std_ulogic; ahbacc : std_ulogic; ahbadd : std_ulogic; rec : std_ulogic; bcnt : std_logic_vector(1 downto 0); -- Shift register sreg : std_logic_vector(7 downto 0); cnt : std_logic_vector(2 downto 0); -- Synchronizers for inputs SCL and SDA scl : std_ulogic; sda : std_ulogic; i2ci : i2c_in_array; -- Output enables scloen : std_ulogic; sdaoen : std_ulogic; end record; ----------------------------------------------------------------------------- -- Signals ----------------------------------------------------------------------------- signal ami : ahb_dma_in_type; signal amo : ahb_dma_out_type; signal r, rin : i2c2ahb_reg_type; begin -- Generic AHB master interface ahbmst0 : ahbmst generic map (hindex => hindex, hirq => 0, venid => VENDOR_GAISLER, devid => GAISLER_I2C2AHB, version => 0, chprot => 3, incaddr => 0) port map (rstn, clk, ami, amo, ahbi, ahbo); comb: process (r, rstn, i2ci, amo, i2c2ahbi) variable v : i2c2ahb_reg_type; variable sclfilt : std_logic_vector(filter-1 downto 0); variable sdafilt : std_logic_vector(filter-1 downto 0); variable hrdata : std_logic_vector(31 downto 0); variable ahbreq : std_ulogic; variable slv : std_ulogic; variable cfg : std_ulogic; variable lb : std_ulogic; begin v := r; ahbreq := '0'; slv := '0'; cfg := '0'; lb := '0'; hrdata := (others => '0'); v.i2ci(0) := i2ci; v.i2ci(filter downto 1) := r.i2ci(filter-1 downto 0); ---------------------------------------------------------------------------- -- Bus filtering ---------------------------------------------------------------------------- for i in 0 to filter-1 loop sclfilt(i) := r.i2ci(i+1).scl; sdafilt(i) := r.i2ci(i+1).sda; end loop; -- i if andv(sclfilt) = '1' then v.scl := '1'; end if; if orv(sclfilt) = '0' then v.scl := '0'; end if; if andv(sdafilt) = '1' then v.sda := '1'; end if; if orv(sdafilt) = '0' then v.sda := '0'; end if; --------------------------------------------------------------------------- -- DMA control --------------------------------------------------------------------------- if r.dodma = '1' then if amo.active = '1' then if amo.ready = '1' then hrdata := ahbreadword(amo.rdata); case r.hsize is when "00" => v.haddr := r.haddr + 1; for i in 1 to 3 loop if i = conv_integer(r.haddr(1 downto 0)) then hrdata(31 downto 24) := hrdata(31-8*i downto 24-8*i); end if; end loop; when "01" => v.haddr := r.haddr + 2; if r.haddr(1) = '1' then hrdata(31 downto 16) := hrdata(15 downto 0); end if; when others => v.haddr := r.haddr + 4; end case; v.sreg := hrdata(31 downto 24); v.hdata(31 downto 8) := hrdata(23 downto 0); v.mexc := '0'; v.dodma := '0'; end if; if amo.mexc = '1' then v.mexc := '1'; v.dodma := '0'; end if; else ahbreq := '1'; end if; end if; --------------------------------------------------------------------------- -- I2C slave control FSM --------------------------------------------------------------------------- case r.state is when idle => -- Release bus if (r.scl and not v.scl) = '1' then v.sdaoen := I2C_HIZ; end if; when checkaddr => if r.sreg(7 downto 1) = i2c2ahbi.slvaddr then slv := '1'; end if; if r.sreg(7 downto 1) = i2c2ahbi.cfgaddr then cfg := '1'; end if; v.rec := not r.sreg(0); if (slv or cfg) = '1' then if (slv and r.dodma) = '1' then -- Core is busy performing DMA if r.nack = '1' then v.state := idle; else v.state := sclhold; end if; else v.state := handshake; end if; else -- Slave address did not match v.state := idle; end if; v.hwrite := v.rec; if (slv and not r.dodma) = '1' then v.dodma := not v.rec; end if; v.ahbacc := slv; v.bcnt := "00"; v.ahbadd := '0'; when sclhold => -- This state is used when the device has been addressed to see if SCL -- should be kept low until the core is ready to process another -- transfer. It is also used when a data byte has been transmitted or -- received to keep SCL low until a DMA operation has completed. -- In the transmit case we keep SCL low before the rising edge of the -- first byte, so we go directly to move byte. In the receive case we -- stretch the ACK cycle so we jump to handshake next. if (r.scl and not v.scl) = '1' then v.scloen := I2C_LOW; v.sdaoen := I2C_HIZ; end if; if r.dodma = '0' then if (not r.rec and not r.i2caddr) = '1' then v.state := movebyte; else v.state := handshake; end if; v.scloen := I2C_HIZ; -- Falling edge that should be detected in movebyte may have passed if (r.i2caddr or r.rec or v.scl) = '0' then v.sdaoen := r.sreg(7) xor OEPOL_LEVEL; end if; end if; when movebyte => if (r.scl and not v.scl) = '1' then if (r.i2caddr or r.rec) = '0' then v.sdaoen := r.sreg(7) xor OEPOL_LEVEL; else v.sdaoen := I2C_HIZ; end if; end if; if (not r.scl and v.scl) = '1' then v.sreg := r.sreg(6 downto 0) & r.sda; if r.cnt = "111" then if r.i2caddr = '1' then v.state := checkaddr; else v.state := handshake; end if; v.cnt := (others => '0'); else v.cnt := r.cnt + 1; end if; end if; when handshake => if ((r.hsize = "00") or ((r.hsize(0) and r.bcnt(0)) = '1') or (r.bcnt = "11")) then lb := '1'; end if; -- Falling edge if (r.scl and not v.scl) = '1' then if (r.i2caddr or not r.ahbacc) = '1' then -- Also handles first byte on AHB read access if (r.rec or r.i2caddr) = '1' then v.sdaoen := I2C_LOW; else v.sdaoen := I2C_HIZ; end if; if (not r.i2caddr and r.rec) = '1' then -- Control register access v.nack := r.sreg(2); v.hsize := r.sreg(1 downto 0); end if; else -- AHB access if r.rec = '1' then -- First we need a 4 byte address, then we handle data. v.bcnt := r.bcnt + 1; if r.ahbadd = '0' then -- We could check if the address is within the allowed memory -- area here, and nack otherwise, but we do it when the access -- is performed instead, to have one check for all cases. v.haddr := r.haddr(23 downto 0) & r.sreg; if r.bcnt = "11" then v.ahbadd := '1'; end if; v.sdaoen := I2C_LOW; elsif r.dodma = '0' then if r.bcnt = "00" then v.hdata(31 downto 24) := r.sreg; end if; if r.bcnt(1) = '0' then v.hdata(23 downto 16) := r.sreg; end if; if r.bcnt(0) = '0' then v.hdata(15 downto 8) := r.sreg; end if; v.hdata(7 downto 0) := r.sreg; if lb = '1' then v.dodma := '1'; v.bcnt := "00"; end if; v.sdaoen := I2C_LOW; end if; else -- Transmit, release bus v.sdaoen := I2C_HIZ; end if; end if; -- Previous DMA is not finished yet if (r.dodma and r.ahbacc) = '1' then if r.nack = '0' then -- Hold clock low and handle data when DMA is finished v.state := sclhold; v.scloen := I2C_LOW; else -- NAK byte v.sdaoen := I2C_HIZ; v.state := idle; end if; end if; end if; -- Risinge edge if (not r.scl and v.scl) = '1' then if (r.i2caddr or not r.ahbacc) = '1' then if r.sda = I2C_ACK then v.state := movebyte; else v.state := idle; end if; else if r.rec = '1' then v.state := movebyte; else -- Transmit, check ACK/NAK from master -- If the master NAKs the transmitted byte the transfer has ended -- and we should wait for the master's next action. If the master -- ACKs the byte the core we will continue to transmit data until -- we reach the last available byte. When the last byte has been -- transmitted we will act depending on if we are allowed to enter -- sclhold. If we can, we enter sclhold and start a new DMA -- operation, otherwise we stop communicating until the next start -- condition. v.bcnt := r.bcnt + 1; if r.sda = I2C_ACK then if lb = '1' then if r.nack = '1' then v.state := idle; else v.dodma := '1'; v.bcnt := "00"; v.state := sclhold; end if; else v.state := movebyte; end if; else v.state := idle; end if; v.hdata(31 downto 8) := r.hdata(23 downto 0); v.sreg := r.hdata(31 downto 24); end if; end if; v.i2caddr := '0'; if r.ahbacc = '0' then -- Control register access v.sreg := zero32(7 downto 6) & r.prot & r.mexc & r.dodma & r.nack & r.hsize; end if; end if; end case; if i2c2ahbi.hmask /= zero32 then if v.dodma = '1' then if ((i2c2ahbi.haddr xor r.haddr) and i2c2ahbi.hmask) /= zero32 then v.dodma := '0'; v.prot := '1'; v.state := idle; else v.prot := '0'; end if; end if; else v.prot := '0'; end if; if i2c2ahbi.en = '1' then -- STOP condition if (r.scl and v.scl and not r.sda and v.sda) = '1' then v.state := idle; end if; -- START or repeated START condition if (r.scl and v.scl and r.sda and not v.sda) = '1' then v.state := movebyte; v.cnt := (others => '0'); v.i2caddr := '1'; end if; end if; ---------------------------------------------------------------------------- -- Reset ---------------------------------------------------------------------------- if rstn = '0' then v.state := idle; v.hsize := HSIZE_WORD(1 downto 0); v.mexc := '0'; v.dodma := '0'; v.nack := '0'; v.prot := '0'; v.scl := '0'; v.scloen := I2C_HIZ; v.sdaoen := I2C_HIZ; end if; if i2c2ahbi.hmask = zero32 then v.prot := '0'; end if; ---------------------------------------------------------------------------- -- Signal assignments ---------------------------------------------------------------------------- -- Core registers rin <= v; -- AHB master control ami.address <= r.haddr; ami.wdata <= ahbdrivedata(r.hdata); ami.start <= ahbreq; ami.burst <= '0'; ami.write <= r.hwrite; ami.busy <= '0'; ami.irq <= '0'; ami.size <= '0' & r.hsize; -- Update outputs i2c2ahbo.dma <= r.dodma; i2c2ahbo.wr <= r.hwrite; i2c2ahbo.prot <= r.prot; i2co.scl <= '0'; i2co.scloen <= r.scloen; i2co.sda <= '0'; i2co.sdaoen <= r.sdaoen; i2co.enable <= i2c2ahbi.en; end process comb; reg: process (clk) begin if rising_edge(clk) then r <= rin; end if; end process reg; -- Boot message -- pragma translate_off bootmsg : report_version generic map ("i2c2ahb" & tost(hindex) & ": I2C to AHB bridge"); -- pragma translate_on end architecture rtl;
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================= -- Authors: Martin Zabel -- -- Module: Test cache_mem on Xilinx KC705 board. -- -- Description: -- ------------------------------------ -- Test cache_mem on Xilinx KC705 board using the Xilinx Memory Controller -- (MIG). -- -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; library poc; use poc.utils.all; entity cachetest_KC705 is port ( KC705_SystemClock_200MHz_p : in std_logic; KC705_SystemClock_200MHz_n : in std_logic; KC705_GPIO_LED : out std_logic_vector(7 downto 0); ddr3_dq : inout std_logic_vector(64-1 downto 0); ddr3_dqs_p : inout std_logic_vector(8-1 downto 0); ddr3_dqs_n : inout std_logic_vector(8-1 downto 0); ddr3_addr : out std_logic_vector(14-1 downto 0); ddr3_ba : out std_logic_vector(3-1 downto 0); ddr3_ras_n : out std_logic; ddr3_cas_n : out std_logic; ddr3_we_n : out std_logic; ddr3_reset_n : out std_logic; ddr3_ck_p : out std_logic_vector(1-1 downto 0); ddr3_ck_n : out std_logic_vector(1-1 downto 0); ddr3_cke : out std_logic_vector(1-1 downto 0); ddr3_cs_n : out std_logic_vector(1*1-1 downto 0); ddr3_dm : out std_logic_vector(8-1 downto 0); ddr3_odt : out std_logic_vector(1-1 downto 0)); end entity cachetest_KC705; architecture rtl of cachetest_KC705 is signal sysclk_unbuf : std_logic; signal refclk : std_logic; signal memtest_status : std_logic_vector(2 downto 0); -- Inputs / Outputs of MIG core signal sys_rst : std_logic; signal app_addr : std_logic_vector(28-1 downto 0); signal app_cmd : std_logic_vector(2 downto 0); signal app_en : std_logic; signal app_wdf_data : std_logic_vector((4*2*64)-1 downto 0); signal app_wdf_end : std_logic; signal app_wdf_mask : std_logic_vector((4*2*64)/8-1 downto 0); signal app_wdf_wren : std_logic; signal app_rd_data : std_logic_vector((4*2*64)-1 downto 0); signal app_rd_data_end : std_logic; signal app_rd_data_valid : std_logic; signal app_rdy : std_logic; signal app_wdf_rdy : std_logic; signal ui_clk : std_logic; signal ui_clk_sync_rst : std_logic; signal init_calib_complete : std_logic; -- component declaration required for Xilinx Vivado component mig_KC705_MT8JTF12864HZ_1G6 port ( ddr3_dq : inout std_logic_vector(63 downto 0); ddr3_dqs_p : inout std_logic_vector(7 downto 0); ddr3_dqs_n : inout std_logic_vector(7 downto 0); ddr3_addr : out std_logic_vector(13 downto 0); ddr3_ba : out std_logic_vector(2 downto 0); ddr3_ras_n : out std_logic; ddr3_cas_n : out std_logic; ddr3_we_n : out std_logic; ddr3_reset_n : out std_logic; ddr3_ck_p : out std_logic_vector(0 downto 0); ddr3_ck_n : out std_logic_vector(0 downto 0); ddr3_cke : out std_logic_vector(0 downto 0); ddr3_cs_n : out std_logic_vector(0 downto 0); ddr3_dm : out std_logic_vector(7 downto 0); ddr3_odt : out std_logic_vector(0 downto 0); app_addr : in std_logic_vector(27 downto 0); app_cmd : in std_logic_vector(2 downto 0); app_en : in std_logic; app_wdf_data : in std_logic_vector(511 downto 0); app_wdf_end : in std_logic; app_wdf_mask : in std_logic_vector(63 downto 0); app_wdf_wren : in std_logic; app_rd_data : out std_logic_vector(511 downto 0); app_rd_data_end : out std_logic; app_rd_data_valid : out std_logic; app_rdy : out std_logic; app_wdf_rdy : out std_logic; app_sr_req : in std_logic; app_ref_req : in std_logic; app_zq_req : in std_logic; app_sr_active : out std_logic; app_ref_ack : out std_logic; app_zq_ack : out std_logic; ui_clk : out std_logic; ui_clk_sync_rst : out std_logic; init_calib_complete : out std_logic; -- System Clock Ports sys_clk_i : in std_logic; -- Reference Clock Ports clk_ref_i : in std_logic; sys_rst : in std_logic ); end component mig_KC705_MT8JTF12864HZ_1G6; begin -- architecture rtl ----------------------------------------------------------------------------- -- Clock Buffer ----------------------------------------------------------------------------- -- This system clock is used two-fold: -- -- 1) It is used as the reference / system clock for the memory controllers -- (MIG). There it feeds only PLLs, so that, dedicated routing can be -- used and no BUFG is required. -- -- 2) It is also used for the IDELAYCTRL and temperature monitor logic. -- This requires a BUFG, but could also be driven by another 200 MHz -- clock source. If this other clock is not free-runnning, then -- IDELAYCTRL and the temperature monitor must be hold in reset until -- this other clock is stable. sysclk_ibuf : ibufds port map ( I => KC705_SystemClock_200MHz_p, IB => KC705_SystemClock_200MHz_n, O => sysclk_unbuf); -- sufficient for memory controllers only. refclk_bufg : bufg port map ( I => sysclk_unbuf, O => refclk); -- buffered 200 MHz reference clock ----------------------------------------------------------------------------- -- MemoryTester ----------------------------------------------------------------------------- MemoryTester : block -- The smallest addressable unit of the "app" interface has DQ_BITS bits. -- The smallest addressable unit of the "mem" interface has MEM_DATA_BITS bits. -- The burst length is then MEM_DATA_BITS / DQ_BITS. constant MEM_DATA_BITS : positive := 512; constant DQ_BITS : positive := 64; constant BL_BITS : natural := log2ceil(MEM_DATA_BITS / DQ_BITS); constant MEM_ADDR_BITS : natural := ite(SIMULATION, 17-3, -- 128 KByte / 8 = 16 KByte per chip (on SoDIMM) 30-3) -- 1 GB / 8 = 128 MB per chip (on SoDIMM) -BL_BITS; constant CPU_DATA_BITS : positive := 32; -- supported values: 8, 16, 32, 64, 128 constant CPU_ADDR_BITS : positive := log2ceil(MEM_DATA_BITS/CPU_DATA_BITS)+MEM_ADDR_BITS; signal cpu_rdy : std_logic; signal cpu_req : std_logic; signal cpu_write : std_logic; signal cpu_addr : unsigned(CPU_ADDR_BITS-1 downto 0); signal cpu_wdata : std_logic_vector(CPU_DATA_BITS-1 downto 0); signal cpu_rstb : std_logic; signal cpu_rdata : std_logic_vector(CPU_DATA_BITS-1 downto 0); signal mem_rdy : std_logic; signal mem_rstb : std_logic; signal mem_req : std_logic; signal mem_write : std_logic; signal mem_addr : unsigned(MEM_ADDR_BITS-1 downto 0); signal mem_wdata : std_logic_vector(MEM_DATA_BITS-1 downto 0); signal mem_wmask : std_logic_vector(MEM_DATA_BITS/8-1 downto 0); signal mem_rdata : std_logic_vector(MEM_DATA_BITS-1 downto 0); begin -- block MemoryTester fsm : entity work.memtest_fsm generic map ( A_BITS => CPU_ADDR_BITS, D_BITS => CPU_DATA_BITS) port map ( clk => ui_clk, rst => ui_clk_sync_rst, mem_rdy => cpu_rdy, mem_rstb => cpu_rstb, mem_rdata => cpu_rdata, mem_req => cpu_req, mem_write => cpu_write, mem_addr => cpu_addr, mem_wdata => cpu_wdata, status => memtest_status(2 downto 0)); cache : entity poc.cache_mem generic map ( REPLACEMENT_POLICY => "LRU", CACHE_LINES => 1024, -- 64 KiB cache / 512 bit per cache line ASSOCIATIVITY => 1, CPU_DATA_BITS => CPU_DATA_BITS, MEM_ADDR_BITS => MEM_ADDR_BITS, MEM_DATA_BITS => MEM_DATA_BITS, OUTSTANDING_REQ => 2) port map ( clk => ui_clk, rst => ui_clk_sync_rst, cpu_req => cpu_req, cpu_write => cpu_write, cpu_addr => cpu_addr, cpu_wdata => cpu_wdata, cpu_rdy => cpu_rdy, cpu_rstb => cpu_rstb, cpu_rdata => cpu_rdata, mem_req => mem_req, mem_write => mem_write, mem_addr => mem_addr, mem_wdata => mem_wdata, mem_wmask => mem_wmask, mem_rdy => mem_rdy, mem_rstb => mem_rstb, mem_rdata => mem_rdata); adapter : entity poc.ddr3_mem2mig_adapter_Series7 generic map ( D_BITS => MEM_DATA_BITS, DQ_BITS => DQ_BITS, MEM_A_BITS => MEM_ADDR_BITS, APP_A_BITS => app_addr'length) port map ( mem_req => mem_req, mem_write => mem_write, mem_addr => mem_addr, mem_wdata => mem_wdata, mem_wmask => mem_wmask, mem_rdy => mem_rdy, mem_rstb => mem_rstb, mem_rdata => mem_rdata, init_calib_complete => init_calib_complete, app_rd_data => app_rd_data, app_rd_data_end => app_rd_data_end, app_rd_data_valid => app_rd_data_valid, app_rdy => app_rdy, app_wdf_rdy => app_wdf_rdy, app_addr => app_addr, app_cmd => app_cmd, app_en => app_en, app_wdf_data => app_wdf_data, app_wdf_end => app_wdf_end, app_wdf_mask => app_wdf_mask, app_wdf_wren => app_wdf_wren); end block MemoryTester; ----------------------------------------------------------------------------- -- Memory Controller Instantiation ----------------------------------------------------------------------------- -- Apply an initial reset pulse. Required for IDELAYCTRL. sys_rst_pulse : FD generic map ( INIT => '1') port map ( D => '0', C => refclk, Q => sys_rst); mig : mig_KC705_MT8JTF12864HZ_1G6 port map ( ddr3_dq => ddr3_dq, ddr3_dqs_p => ddr3_dqs_p, ddr3_dqs_n => ddr3_dqs_n, ddr3_addr => ddr3_addr, ddr3_ba => ddr3_ba, ddr3_ras_n => ddr3_ras_n, ddr3_cas_n => ddr3_cas_n, ddr3_we_n => ddr3_we_n, ddr3_reset_n => ddr3_reset_n, ddr3_ck_p => ddr3_ck_p, ddr3_ck_n => ddr3_ck_n, ddr3_cke => ddr3_cke, ddr3_cs_n => ddr3_cs_n, ddr3_dm => ddr3_dm, ddr3_odt => ddr3_odt, sys_clk_i => sysclk_unbuf, clk_ref_i => refclk, app_addr => app_addr, app_cmd => app_cmd, app_en => app_en, app_wdf_data => app_wdf_data, app_wdf_end => app_wdf_end, app_wdf_mask => app_wdf_mask, app_wdf_wren => app_wdf_wren, app_rd_data => app_rd_data, app_rd_data_end => app_rd_data_end, app_rd_data_valid => app_rd_data_valid, app_rdy => app_rdy, app_wdf_rdy => app_wdf_rdy, app_sr_req => '0', -- reserved app_sr_active => open, app_ref_req => '0', -- unused app_ref_ack => open, app_zq_req => '0', -- unused app_zq_ack => open, ui_clk => ui_clk, ui_clk_sync_rst => ui_clk_sync_rst, init_calib_complete => init_calib_complete, sys_rst => sys_rst); -- active high ----------------------------------------------------------------------------- -- Status Output ----------------------------------------------------------------------------- KC705_GPIO_LED(7) <= ui_clk_sync_rst; KC705_GPIO_LED(6) <= '0'; KC705_GPIO_LED(5) <= '0'; KC705_GPIO_LED(4) <= '0'; KC705_GPIO_LED(3) <= init_calib_complete; KC705_GPIO_LED(2 downto 0) <= memtest_status; end architecture rtl;
-- Copyright (c) University of Florida -- -- This file is part of window_gen. -- -- window_gen is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- window_gen is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with window_gen. If not, see <http://www.gnu.org/licenses/>. -- Greg Stitt -- Patrick Cooke -- University of Florida -- Description: This entity accepts a sequence of window columns and coalesces -- them into a complete window(s). The entity implements a set of shift -- registers equal to the size of a window. The wg_coalescer reads the next -- columns of multiple rows, shifts the previous values over, and stores the -- next data to generate a new window. In other words, this entity slides the -- window by one column at a time while reusing previous data. The inputs and -- outputs are "first-word fall through" so that the next window(s) is output -- before ren is asserted. ren basically pops the current window(s) from the -- buffer. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; use work.math_custom.all; use work.window_gen_pkg.all; ------------------------------------------------------------------------------- -- Generics Description -- PARALLEL_IO : Specifies the number of input columns provided at a time, -- which also defines the maximum number of windows output -- from the entity. -- NUM_ROWS : The maximum number of rows in a generated window -- NUM_COLS : The maximum number of cols in a generated window -- DATA_WIDTH : The width in bits of each element. ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Port Descriptions (all control signals are active high) -- clk: clock -- rst: asynchronous reset -- ren : '1' to pop window(s) from buffer -- read_input : informs the source of the stream that the entity is accepting -- data -- empty : '1' when the entity has no valid window output, '0' otherwise -- input : the current column(s) of input. The exact number of columns is -- specified by the configuration option PARALLEL_IO. -- input_ready : specifies when "input" is valid -- input_done : '1' when all inputs have been passed to the entity -- is_edge : '1' if the current input is the starting (left) edge/column of a -- window. One bit for each of PARALLEL_IO input columns. -- output : PARALLEL_IO window(s) -- window_valid : '1' when an output window is valid, '0' otherwise. One bit -- for each of the PARALLEL_IO windows. The next window in the -- output sequence is always represented by the MSB. The window -- that is PARALLEL_IO-1 windows away in the sequence is -- represented by the LSB. -- done : '1' when the coalescer has created all windows after input_done is -- asserted. Note that the coalescer these windows have not -- necessarily been read by the user yet. ------------------------------------------------------------------------------- entity wg_coalescer is generic ( PARALLEL_IO : positive; NUM_ROWS : positive; NUM_COLS : positive; DATA_WIDTH : positive); port ( clk : in std_logic; rst : in std_logic; ren : in std_logic; read_input : out std_logic; empty : out std_logic; input : in std_logic_vector(NUM_ROWS*PARALLEL_IO*DATA_WIDTH-1 downto 0); input_ready : in std_logic; input_done : in std_logic; is_edge : in std_logic_vector(PARALLEL_IO-1 downto 0); output : out std_logic_vector(NUM_ROWS*(NUM_COLS+PARALLEL_IO-1)*DATA_WIDTH-1 downto 0); window_valid : out std_logic_vector(PARALLEL_IO-1 downto 0); done : out std_logic); end wg_coalescer; architecture RTL of wg_coalescer is ------------------------------------------------------------------------- -- constants and types -- the buffer increases the number of columns to the next multiple of -- PARALLEL_IO to ensure that new writes don't overlap with existing data constant BUFFER_COLS : positive := positive(ceil(real(NUM_COLS+PARALLEL_IO-1)/real(PARALLEL_IO)))*PARALLEL_IO; -- The number of output columns has to account for the extra windows when -- PARALLEL_IO > 1 constant OUTPUT_COLS : positive := NUM_COLS+PARALLEL_IO-1; -- array used to store PARALLEL_IO inputs from each row of the fifo array -- (i.e. window buffer) type input_array_t is array (0 to NUM_ROWS-1, 0 to PARALLEL_IO-1) of std_logic_vector(DATA_WIDTH-1 downto 0); -- 2D array that stores PARALLEL_IO windows in addition to the next -- PARALLEL_IO inputs type rbuf is array (integer range 0 to NUM_ROWS-1, integer range 0 to BUFFER_COLS-1) of std_logic_vector(DATA_WIDTH-1 downto 0); ------------------------------------------------------------------------- -- Functions for converting I/O to/from vector/array format -- Converts vectorized input into 2D array function devectorizeInput(input : std_logic_vector) return input_array_t is variable temp : input_array_t; begin for i in NUM_ROWS-1 downto 0 loop for j in 0 to PARALLEL_IO-1 loop temp(i, j) := getVectorElement(input, i, j, NUM_ROWS, PARALLEL_IO, DATA_WIDTH); end loop; end loop; return temp; end function; -- Converts register buffer into std_logic_vector used as output function vectorizeOutput(input : rbuf) return std_logic_vector is variable temp : std_logic_vector(NUM_ROWS*OUTPUT_COLS*DATA_WIDTH-1 downto 0); begin for i in 0 to NUM_ROWS-1 loop for j in 0 to OUTPUT_COLS-1 loop setVectorElement(input(i, j), temp, i, j, NUM_ROWS, OUTPUT_COLS, DATA_WIDTH); end loop; end loop; return temp; end function; ------------------------------------------------------------------------- -- internal signals -- the register buffer signal regs : rbuf; -- asserted when there is a valid read for a window signal get_next_window : std_logic; -- asserted when an element in the row with the corresponding index is the -- top left element (i.e. the edge) of a generated window signal is_edge_s : std_logic_vector(0 to BUFFER_COLS-1); -- array that stores the inputs in devectorized form signal input_array : input_array_t; begin -------------------------------------------------------------------- -- Create the buffer of registers and shifting logic process(clk, rst) begin if (rst = '1') then for i in 0 to NUM_ROWS-1 loop for j in 0 to BUFFER_COLS-1 loop regs(i, j) <= std_logic_vector(to_unsigned(0, DATA_WIDTH)); end loop; end loop; for i in 0 to BUFFER_COLS-1 loop is_edge_s(i) <= '0'; end loop; elsif (rising_edge(clk)) then if (get_next_window = '1') then -- shift all registers to next window for i in 0 to NUM_ROWS-1 loop -- the top PARALLEL_IO regs get loaded directly, so don't -- shift anything into them for j in 0 to BUFFER_COLS-PARALLEL_IO-1 loop regs(i, j) <= regs(i, j+PARALLEL_IO); end loop; end loop; -- shift all edge status bits for j in 0 to BUFFER_COLS-PARALLEL_IO-1 loop is_edge_s(j) <= is_edge_s(j+PARALLEL_IO); end loop; -- load in the new inputs for i in 0 to NUM_ROWS-1 loop for j in 0 to PARALLEL_IO-1 loop regs(i, BUFFER_COLS-PARALLEL_IO+j) <= input_array(i, j); end loop; end loop; -- load in the new edge bits for j in 0 to PARALLEL_IO-1 loop is_edge_s(j+BUFFER_COLS-PARALLEL_IO) <= input_ready and is_edge(PARALLEL_IO-j-1); end loop; end if; end if; end process; -------------------------------------------------------------------- -- control logic -- convert input vector into 2D array input_array <= devectorizeInput(input); -- convert reg buffer into std_logic_vector output output <= vectorizeOutput(regs); -- get the next window (by shifting the buffer), but only at valid times: -- 1) When the user requests a read (not checked for valid) -- 2) When the current (0,0) element is not the edge of a window (skip it) -- In both cases, a new input has to be ready and the input not done get_next_window <= (ren or not is_edge_s(0)) and (input_ready or input_done); -- read an input from the fifo_array/window_buffer everytime we get a new window read_input <= get_next_window; -- empty when there is no input available (nothing to shift in) or when a -- window is not available empty <= (not input_ready and not input_done) or (not is_edge_s(0)); -- empty <= (not input_ready and not input_done) or (not is_edge_s(PARALLEL_IO-1)); -- output valid status of PARALLEL_IO windows -- MSB is the first window, LSB is the last process(is_edge_s) begin for i in 0 to PARALLEL_IO-1 loop window_valid(PARALLEL_IO-i-1) <= is_edge_s(i); end loop; end process; -- determine when reg_buffer has output all windows process(is_edge_s, input_done) begin -- done when there are no more inputs and all the windows currently in -- the buffer are gone if (input_done = '1' and is_edge_s = std_logic_vector(to_unsigned(0,is_edge_s'length))) then done <= '1'; else done <= '0'; end if; end process; end RTL;
------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on entity xlclockdriver is generic ( period: integer := 2; log_2_period: integer := 0; pipeline_regs: integer := 5; use_bufg: integer := 0 ); port ( sysclk: in std_logic; sysclr: in std_logic; sysce: in std_logic; clk: out std_logic; clr: out std_logic; ce: out std_logic; ce_logic: out std_logic ); end xlclockdriver; architecture behavior of xlclockdriver is component bufg port ( i: in std_logic; o: out std_logic ); end component; component synth_reg_w_init generic ( width: integer; init_index: integer; init_value: bit_vector; latency: integer ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; function size_of_uint(inp: integer; power_of_2: boolean) return integer is constant inp_vec: std_logic_vector(31 downto 0) := integer_to_std_logic_vector(inp,32, xlUnsigned); variable result: integer; begin result := 32; for i in 0 to 31 loop if inp_vec(i) = '1' then result := i; end if; end loop; if power_of_2 then return result; else return result+1; end if; end; function is_power_of_2(inp: std_logic_vector) return boolean is constant width: integer := inp'length; variable vec: std_logic_vector(width - 1 downto 0); variable single_bit_set: boolean; variable more_than_one_bit_set: boolean; variable result: boolean; begin vec := inp; single_bit_set := false; more_than_one_bit_set := false; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if width > 0 then for i in 0 to width - 1 loop if vec(i) = '1' then if single_bit_set then more_than_one_bit_set := true; end if; single_bit_set := true; end if; end loop; end if; if (single_bit_set and not(more_than_one_bit_set)) then result := true; else result := false; end if; return result; end; function ce_reg_init_val(index, period : integer) return integer is variable result: integer; begin result := 0; if ((index mod period) = 0) then result := 1; end if; return result; end; function remaining_pipe_regs(num_pipeline_regs, period : integer) return integer is variable factor, result: integer; begin factor := (num_pipeline_regs / period); result := num_pipeline_regs - (period * factor) + 1; return result; end; function sg_min(L, R: INTEGER) return INTEGER is begin if L < R then return L; else return R; end if; end; constant max_pipeline_regs : integer := 8; constant pipe_regs : integer := 5; constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs); constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period); constant period_floor: integer := max(2, period); constant power_of_2_counter: boolean := is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned)); constant cnt_width: integer := size_of_uint(period_floor, power_of_2_counter); constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) := integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned); constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) := integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned); constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) := integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned); signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0'); signal ce_vec : std_logic_vector(num_pipeline_regs downto 0); attribute MAX_FANOUT : string; attribute MAX_FANOUT of ce_vec:signal is "REDUCE"; signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0); attribute MAX_FANOUT of ce_vec_logic:signal is "REDUCE"; signal internal_ce: std_logic_vector(0 downto 0); signal internal_ce_logic: std_logic_vector(0 downto 0); signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0); begin clk <= sysclk; clr <= sysclr; cntr_gen: process(sysclk) begin if sysclk'event and sysclk = '1' then if (sysce = '1') then if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then clk_num <= (others => '0'); else clk_num <= clk_num + 1; end if; end if; end if; end process; clr_gen: process(clk_num, sysclr) begin if power_of_2_counter then cnt_clr(0) <= sysclr; else if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1 or sysclr = '1') then cnt_clr(0) <= '1'; else cnt_clr(0) <= '0'; end if; end if; end process; clr_reg: synth_reg_w_init generic map ( width => 1, init_index => 0, init_value => b"0000", latency => 1 ) port map ( i => cnt_clr, ce => sysce, clr => sysclr, clk => sysclk, o => cnt_clr_dly ); pipelined_ce : if period > 1 generate ce_gen: process(clk_num) begin if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then ce_vec(num_pipeline_regs) <= '1'; else ce_vec(num_pipeline_regs) <= '0'; end if; end process; ce_pipeline: for index in num_pipeline_regs downto 1 generate ce_reg : synth_reg_w_init generic map ( width => 1, init_index => ce_reg_init_val(index, period), init_value => b"0000", latency => 1 ) port map ( i => ce_vec(index downto index), ce => sysce, clr => sysclr, clk => sysclk, o => ce_vec(index-1 downto index-1) ); end generate; internal_ce <= ce_vec(0 downto 0); end generate; pipelined_ce_logic: if period > 1 generate ce_gen_logic: process(clk_num) begin if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then ce_vec_logic(num_pipeline_regs) <= '1'; else ce_vec_logic(num_pipeline_regs) <= '0'; end if; end process; ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate ce_logic_reg : synth_reg_w_init generic map ( width => 1, init_index => ce_reg_init_val(index, period), init_value => b"0000", latency => 1 ) port map ( i => ce_vec_logic(index downto index), ce => sysce, clr => sysclr, clk => sysclk, o => ce_vec_logic(index-1 downto index-1) ); end generate; internal_ce_logic <= ce_vec_logic(0 downto 0); end generate; use_bufg_true: if period > 1 and use_bufg = 1 generate ce_bufg_inst: bufg port map ( i => internal_ce(0), o => ce ); ce_bufg_inst_logic: bufg port map ( i => internal_ce_logic(0), o => ce_logic ); end generate; use_bufg_false: if period > 1 and (use_bufg = 0) generate ce <= internal_ce(0); ce_logic <= internal_ce_logic(0); end generate; generate_system_clk: if period = 1 generate ce <= sysce; ce_logic <= sysce; end generate; end architecture behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity xland2 is port ( a : in std_logic; b : in std_logic; dout : out std_logic ); end xland2; architecture behavior of xland2 is begin dout <= a and b; end behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity default_clock_driver is port ( sysce: in std_logic; sysce_clr: in std_logic; sysclk: in std_logic; ce_1: out std_logic; ce_logic_1: out std_logic; clk_1: out std_logic ); end default_clock_driver; architecture structural of default_clock_driver is attribute syn_noprune: boolean; attribute syn_noprune of structural : architecture is true; attribute optimize_primitives: boolean; attribute optimize_primitives of structural : architecture is false; attribute dont_touch: boolean; attribute dont_touch of structural : architecture is true; signal sysce_clr_x0: std_logic; signal sysce_x0: std_logic; signal sysclk_x0: std_logic; signal xlclockdriver_1_ce: std_logic; signal xlclockdriver_1_ce_logic: std_logic; signal xlclockdriver_1_clk: std_logic; begin sysce_x0 <= sysce; sysce_clr_x0 <= sysce_clr; sysclk_x0 <= sysclk; ce_1 <= xlclockdriver_1_ce; ce_logic_1 <= xlclockdriver_1_ce_logic; clk_1 <= xlclockdriver_1_clk; xlclockdriver_1: entity work.xlclockdriver generic map ( log_2_period => 1, period => 1, use_bufg => 0 ) port map ( sysce => sysce_x0, sysclk => sysclk_x0, sysclr => sysce_clr_x0, ce => xlclockdriver_1_ce, ce_logic => xlclockdriver_1_ce_logic, clk => xlclockdriver_1_clk ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity plb_clock_driver is port ( sysce: in std_logic; sysce_clr: in std_logic; sysclk: in std_logic; plb_ce_1: out std_logic; plb_clk_1: out std_logic ); end plb_clock_driver; architecture structural of plb_clock_driver is attribute syn_noprune: boolean; attribute syn_noprune of structural : architecture is true; attribute optimize_primitives: boolean; attribute optimize_primitives of structural : architecture is false; attribute dont_touch: boolean; attribute dont_touch of structural : architecture is true; signal sysce_clr_x0: std_logic; signal sysce_x0: std_logic; signal sysclk_x0: std_logic; signal xlclockdriver_1_ce: std_logic; signal xlclockdriver_1_clk: std_logic; begin sysce_x0 <= sysce; sysce_clr_x0 <= sysce_clr; sysclk_x0 <= sysclk; plb_ce_1 <= xlclockdriver_1_ce; plb_clk_1 <= xlclockdriver_1_clk; xlclockdriver_1: entity work.xlclockdriver generic map ( log_2_period => 1, period => 1, use_bufg => 0 ) port map ( sysce => sysce_x0, sysclk => sysclk_x0, sysclr => sysce_clr_x0, ce => xlclockdriver_1_ce, clk => xlclockdriver_1_clk ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity sg_2d_fir_cw is port ( active_video_i: in std_logic; ce: in std_logic := '1'; clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz) hblank_i: in std_logic; hsync_i: in std_logic; plb_abus: in std_logic_vector(31 downto 0); plb_pavalid: in std_logic; plb_rnw: in std_logic; plb_wrdbus: in std_logic_vector(31 downto 0); reset: in std_logic; sg_plb_addrpref: in std_logic_vector(19 downto 0); splb_rst: in std_logic; vblank_i: in std_logic; video_data_i: in std_logic_vector(23 downto 0); vsync_i: in std_logic; xps_ce: in std_logic := '1'; xps_clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz) active_video_o: out std_logic; hblank_o: out std_logic; hsync_o: out std_logic; sl_addrack: out std_logic; sl_rdcomp: out std_logic; sl_rddack: out std_logic; sl_rddbus: out std_logic_vector(31 downto 0); sl_wait: out std_logic; sl_wrcomp: out std_logic; sl_wrdack: out std_logic; vblank_o: out std_logic; video_data_o: out std_logic_vector(23 downto 0); vsync_o: out std_logic ); end sg_2d_fir_cw; architecture structural of sg_2d_fir_cw is component block_memory_generator_spartan6_6_2_80846d0865f6122e port ( addra: in std_logic_vector(4 downto 0); addrb: in std_logic_vector(4 downto 0); clka: in std_logic; clkb: in std_logic; dina: in std_logic_vector(6 downto 0); dinb: in std_logic_vector(6 downto 0); ena: in std_logic; enb: in std_logic; wea: in std_logic_vector(0 downto 0); web: in std_logic_vector(0 downto 0); douta: out std_logic_vector(6 downto 0); doutb: out std_logic_vector(6 downto 0) ); end component; attribute syn_black_box: boolean; attribute syn_black_box of block_memory_generator_spartan6_6_2_80846d0865f6122e: component is true; attribute box_type: string; attribute box_type of block_memory_generator_spartan6_6_2_80846d0865f6122e: component is "black_box"; attribute syn_noprune: boolean; attribute optimize_primitives: boolean; attribute dont_touch: boolean; attribute syn_noprune of block_memory_generator_spartan6_6_2_80846d0865f6122e: component is true; attribute optimize_primitives of block_memory_generator_spartan6_6_2_80846d0865f6122e: component is false; attribute dont_touch of block_memory_generator_spartan6_6_2_80846d0865f6122e: component is true; component xlpersistentdff port ( clk: in std_logic; d: in std_logic; q: out std_logic ); end component; attribute syn_black_box of xlpersistentdff: component is true; attribute box_type of xlpersistentdff: component is "black_box"; attribute syn_noprune of xlpersistentdff: component is true; attribute optimize_primitives of xlpersistentdff: component is false; attribute dont_touch of xlpersistentdff: component is true; signal active_video_i_net: std_logic; signal active_video_o_net: std_logic; signal addr_net: std_logic_vector(4 downto 0); signal addr_x0_net: std_logic_vector(4 downto 0); signal ce_1_sg_x54: std_logic; attribute MAX_FANOUT: string; attribute MAX_FANOUT of ce_1_sg_x54: signal is "REDUCE"; signal ce_logic_1_sg_x25: std_logic; signal clkNet: std_logic; signal clkNet_x0: std_logic; signal clk_1_sg_x54: std_logic; signal coef_gain_reg_ce: std_logic; signal coef_update_reg_ce: std_logic; signal data_in_net: std_logic_vector(6 downto 0); signal data_in_x0_net: std_logic; signal data_in_x1_net: std_logic_vector(19 downto 0); signal data_in_x2_net: std_logic_vector(6 downto 0); signal data_out_net: std_logic_vector(19 downto 0); signal data_out_x0_net: std_logic; signal data_out_x1_net: std_logic_vector(6 downto 0); signal data_out_x2_net: std_logic_vector(6 downto 0); signal en_net: std_logic; signal en_x0_net: std_logic; signal hblank_i_net: std_logic; signal hblank_o_net: std_logic; signal hsync_i_net: std_logic; signal hsync_o_net: std_logic; signal persistentdff_inst_q: std_logic; attribute syn_keep: boolean; attribute syn_keep of persistentdff_inst_q: signal is true; attribute keep: boolean; attribute keep of persistentdff_inst_q: signal is true; attribute preserve_signal: boolean; attribute preserve_signal of persistentdff_inst_q: signal is true; signal plb_abus_net: std_logic_vector(31 downto 0); signal plb_ce_1_sg_x1: std_logic; attribute MAX_FANOUT of plb_ce_1_sg_x1: signal is "REDUCE"; signal plb_clk_1_sg_x1: std_logic; signal plb_pavalid_net: std_logic; signal plb_rnw_net: std_logic; signal plb_wrdbus_net: std_logic_vector(31 downto 0); signal reset_net: std_logic; signal sg_plb_addrpref_net: std_logic_vector(19 downto 0); signal sl_addrack_net: std_logic; signal sl_rdcomp_net: std_logic; signal sl_rddack_net: std_logic; signal sl_rddbus_net: std_logic_vector(31 downto 0); signal sl_wait_net: std_logic; signal sl_wrdack_x1: std_logic; signal sl_wrdack_x2: std_logic; signal splb_rst_net: std_logic; signal vblank_i_net: std_logic; signal vblank_o_net: std_logic; signal video_data_i_net: std_logic_vector(23 downto 0); signal video_data_o_net: std_logic_vector(23 downto 0); signal vsync_i_net: std_logic; signal vsync_o_net: std_logic; signal we_net: std_logic; signal we_x0_net: std_logic; begin active_video_i_net <= active_video_i; clkNet <= clk; hblank_i_net <= hblank_i; hsync_i_net <= hsync_i; plb_abus_net <= plb_abus; plb_pavalid_net <= plb_pavalid; plb_rnw_net <= plb_rnw; plb_wrdbus_net <= plb_wrdbus; reset_net <= reset; sg_plb_addrpref_net <= sg_plb_addrpref; splb_rst_net <= splb_rst; vblank_i_net <= vblank_i; video_data_i_net <= video_data_i; vsync_i_net <= vsync_i; clkNet_x0 <= xps_clk; active_video_o <= active_video_o_net; hblank_o <= hblank_o_net; hsync_o <= hsync_o_net; sl_addrack <= sl_addrack_net; sl_rdcomp <= sl_rdcomp_net; sl_rddack <= sl_rddack_net; sl_rddbus <= sl_rddbus_net; sl_wait <= sl_wait_net; sl_wrcomp <= sl_wrdack_x2; sl_wrdack <= sl_wrdack_x1; vblank_o <= vblank_o_net; video_data_o <= video_data_o_net; vsync_o <= vsync_o_net; coef_buffer: block_memory_generator_spartan6_6_2_80846d0865f6122e port map ( addra => addr_net, addrb => addr_x0_net, clka => clk_1_sg_x54, clkb => plb_clk_1_sg_x1, dina => data_in_net, dinb => data_in_x2_net, ena => ce_1_sg_x54, enb => plb_ce_1_sg_x1, wea(0) => we_net, web(0) => we_x0_net, douta => data_out_x1_net, doutb => data_out_x2_net ); coef_gain: entity work.synth_reg_w_init generic map ( width => 20, init_index => 2, init_value => b"11111111111111111111", latency => 1 ) port map ( ce => coef_gain_reg_ce, clk => plb_clk_1_sg_x1, clr => '0', i => data_in_x1_net, o => data_out_net ); coef_gain_ce_and2_comp: entity work.xland2 port map ( a => plb_ce_1_sg_x1, b => en_x0_net, dout => coef_gain_reg_ce ); coef_update: entity work.synth_reg_w_init generic map ( width => 1, init_index => 2, init_value => b"1", latency => 1 ) port map ( ce => coef_update_reg_ce, clk => plb_clk_1_sg_x1, clr => '0', i(0) => data_in_x0_net, o(0) => data_out_x0_net ); coef_update_ce_and2_comp: entity work.xland2 port map ( a => plb_ce_1_sg_x1, b => en_net, dout => coef_update_reg_ce ); default_clock_driver_x0: entity work.default_clock_driver port map ( sysce => '1', sysce_clr => '0', sysclk => clkNet, ce_1 => ce_1_sg_x54, ce_logic_1 => ce_logic_1_sg_x25, clk_1 => clk_1_sg_x54 ); persistentdff_inst: xlpersistentdff port map ( clk => clkNet, d => persistentdff_inst_q, q => persistentdff_inst_q ); plb_clock_driver_x0: entity work.plb_clock_driver port map ( sysce => '1', sysce_clr => '0', sysclk => clkNet_x0, plb_ce_1 => plb_ce_1_sg_x1, plb_clk_1 => plb_clk_1_sg_x1 ); sg_2d_fir_x0: entity work.sg_2d_fir port map ( active_video_i => active_video_i_net, ce_1 => ce_1_sg_x54, ce_logic_1 => ce_logic_1_sg_x25, clk_1 => clk_1_sg_x54, data_out => data_out_net, data_out_x0 => data_out_x0_net, data_out_x1 => data_out_x1_net, data_out_x2 => data_out_x2_net, dout => data_out_x0_net, dout_x0 => data_out_net, hblank_i => hblank_i_net, hsync_i => hsync_i_net, plb_abus => plb_abus_net, plb_ce_1 => plb_ce_1_sg_x1, plb_clk_1 => plb_clk_1_sg_x1, plb_pavalid => plb_pavalid_net, plb_rnw => plb_rnw_net, plb_wrdbus => plb_wrdbus_net, reset => reset_net, sg_plb_addrpref => sg_plb_addrpref_net, splb_rst => splb_rst_net, vblank_i => vblank_i_net, video_data_i => video_data_i_net, vsync_i => vsync_i_net, active_video_o => active_video_o_net, addr => addr_net, addr_x0 => addr_x0_net, data_in => data_in_net, data_in_x0 => data_in_x0_net, data_in_x1 => data_in_x1_net, data_in_x2 => data_in_x2_net, en => en_net, en_x0 => en_x0_net, hblank_o => hblank_o_net, hsync_o => hsync_o_net, sl_addrack => sl_addrack_net, sl_rdcomp => sl_rdcomp_net, sl_rddack => sl_rddack_net, sl_rddbus => sl_rddbus_net, sl_wait => sl_wait_net, sl_wrcomp => sl_wrdack_x2, sl_wrdack => sl_wrdack_x1, vblank_o => vblank_o_net, video_data_o => video_data_o_net, vsync_o => vsync_o_net, we => we_net, we_x0 => we_x0_net ); end structural;
------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.conv_pkg.all; -- synopsys translate_off library unisim; use unisim.vcomponents.all; -- synopsys translate_on entity xlclockdriver is generic ( period: integer := 2; log_2_period: integer := 0; pipeline_regs: integer := 5; use_bufg: integer := 0 ); port ( sysclk: in std_logic; sysclr: in std_logic; sysce: in std_logic; clk: out std_logic; clr: out std_logic; ce: out std_logic; ce_logic: out std_logic ); end xlclockdriver; architecture behavior of xlclockdriver is component bufg port ( i: in std_logic; o: out std_logic ); end component; component synth_reg_w_init generic ( width: integer; init_index: integer; init_value: bit_vector; latency: integer ); port ( i: in std_logic_vector(width - 1 downto 0); ce: in std_logic; clr: in std_logic; clk: in std_logic; o: out std_logic_vector(width - 1 downto 0) ); end component; function size_of_uint(inp: integer; power_of_2: boolean) return integer is constant inp_vec: std_logic_vector(31 downto 0) := integer_to_std_logic_vector(inp,32, xlUnsigned); variable result: integer; begin result := 32; for i in 0 to 31 loop if inp_vec(i) = '1' then result := i; end if; end loop; if power_of_2 then return result; else return result+1; end if; end; function is_power_of_2(inp: std_logic_vector) return boolean is constant width: integer := inp'length; variable vec: std_logic_vector(width - 1 downto 0); variable single_bit_set: boolean; variable more_than_one_bit_set: boolean; variable result: boolean; begin vec := inp; single_bit_set := false; more_than_one_bit_set := false; -- synopsys translate_off if (is_XorU(vec)) then return false; end if; -- synopsys translate_on if width > 0 then for i in 0 to width - 1 loop if vec(i) = '1' then if single_bit_set then more_than_one_bit_set := true; end if; single_bit_set := true; end if; end loop; end if; if (single_bit_set and not(more_than_one_bit_set)) then result := true; else result := false; end if; return result; end; function ce_reg_init_val(index, period : integer) return integer is variable result: integer; begin result := 0; if ((index mod period) = 0) then result := 1; end if; return result; end; function remaining_pipe_regs(num_pipeline_regs, period : integer) return integer is variable factor, result: integer; begin factor := (num_pipeline_regs / period); result := num_pipeline_regs - (period * factor) + 1; return result; end; function sg_min(L, R: INTEGER) return INTEGER is begin if L < R then return L; else return R; end if; end; constant max_pipeline_regs : integer := 8; constant pipe_regs : integer := 5; constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs); constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period); constant period_floor: integer := max(2, period); constant power_of_2_counter: boolean := is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned)); constant cnt_width: integer := size_of_uint(period_floor, power_of_2_counter); constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) := integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned); constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) := integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned); constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) := integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned); signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0'); signal ce_vec : std_logic_vector(num_pipeline_regs downto 0); attribute MAX_FANOUT : string; attribute MAX_FANOUT of ce_vec:signal is "REDUCE"; signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0); attribute MAX_FANOUT of ce_vec_logic:signal is "REDUCE"; signal internal_ce: std_logic_vector(0 downto 0); signal internal_ce_logic: std_logic_vector(0 downto 0); signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0); begin clk <= sysclk; clr <= sysclr; cntr_gen: process(sysclk) begin if sysclk'event and sysclk = '1' then if (sysce = '1') then if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then clk_num <= (others => '0'); else clk_num <= clk_num + 1; end if; end if; end if; end process; clr_gen: process(clk_num, sysclr) begin if power_of_2_counter then cnt_clr(0) <= sysclr; else if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1 or sysclr = '1') then cnt_clr(0) <= '1'; else cnt_clr(0) <= '0'; end if; end if; end process; clr_reg: synth_reg_w_init generic map ( width => 1, init_index => 0, init_value => b"0000", latency => 1 ) port map ( i => cnt_clr, ce => sysce, clr => sysclr, clk => sysclk, o => cnt_clr_dly ); pipelined_ce : if period > 1 generate ce_gen: process(clk_num) begin if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then ce_vec(num_pipeline_regs) <= '1'; else ce_vec(num_pipeline_regs) <= '0'; end if; end process; ce_pipeline: for index in num_pipeline_regs downto 1 generate ce_reg : synth_reg_w_init generic map ( width => 1, init_index => ce_reg_init_val(index, period), init_value => b"0000", latency => 1 ) port map ( i => ce_vec(index downto index), ce => sysce, clr => sysclr, clk => sysclk, o => ce_vec(index-1 downto index-1) ); end generate; internal_ce <= ce_vec(0 downto 0); end generate; pipelined_ce_logic: if period > 1 generate ce_gen_logic: process(clk_num) begin if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then ce_vec_logic(num_pipeline_regs) <= '1'; else ce_vec_logic(num_pipeline_regs) <= '0'; end if; end process; ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate ce_logic_reg : synth_reg_w_init generic map ( width => 1, init_index => ce_reg_init_val(index, period), init_value => b"0000", latency => 1 ) port map ( i => ce_vec_logic(index downto index), ce => sysce, clr => sysclr, clk => sysclk, o => ce_vec_logic(index-1 downto index-1) ); end generate; internal_ce_logic <= ce_vec_logic(0 downto 0); end generate; use_bufg_true: if period > 1 and use_bufg = 1 generate ce_bufg_inst: bufg port map ( i => internal_ce(0), o => ce ); ce_bufg_inst_logic: bufg port map ( i => internal_ce_logic(0), o => ce_logic ); end generate; use_bufg_false: if period > 1 and (use_bufg = 0) generate ce <= internal_ce(0); ce_logic <= internal_ce_logic(0); end generate; generate_system_clk: if period = 1 generate ce <= sysce; ce_logic <= sysce; end generate; end architecture behavior; ------------------------------------------------------------------- -- System Generator version 13.2 VHDL source file. -- -- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This -- text/file contains proprietary, confidential information of Xilinx, -- Inc., is distributed under license from Xilinx, Inc., and may be used, -- copied and/or disclosed only pursuant to the terms of a valid license -- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use -- this text/file solely for design, simulation, implementation and -- creation of design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly prohibited -- and immediately terminates your license unless covered by a separate -- agreement. -- -- Xilinx is providing this design, code, or information "as is" solely -- for use in developing programs and solutions for Xilinx devices. By -- providing this design, code, or information as one possible -- implementation of this feature, application or standard, Xilinx is -- making no representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining any rights -- you may require for your implementation. Xilinx expressly disclaims -- any warranty whatsoever with respect to the adequacy of the -- implementation, including but not limited to warranties of -- merchantability or fitness for a particular purpose. -- -- Xilinx products are not intended for use in life support appliances, -- devices, or systems. Use in such applications is expressly prohibited. -- -- Any modifications that are made to the source code are done at the user's -- sole risk and will be unsupported. -- -- This copyright and support notice must be retained as part of this -- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights -- reserved. ------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity xland2 is port ( a : in std_logic; b : in std_logic; dout : out std_logic ); end xland2; architecture behavior of xland2 is begin dout <= a and b; end behavior; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity default_clock_driver is port ( sysce: in std_logic; sysce_clr: in std_logic; sysclk: in std_logic; ce_1: out std_logic; ce_logic_1: out std_logic; clk_1: out std_logic ); end default_clock_driver; architecture structural of default_clock_driver is attribute syn_noprune: boolean; attribute syn_noprune of structural : architecture is true; attribute optimize_primitives: boolean; attribute optimize_primitives of structural : architecture is false; attribute dont_touch: boolean; attribute dont_touch of structural : architecture is true; signal sysce_clr_x0: std_logic; signal sysce_x0: std_logic; signal sysclk_x0: std_logic; signal xlclockdriver_1_ce: std_logic; signal xlclockdriver_1_ce_logic: std_logic; signal xlclockdriver_1_clk: std_logic; begin sysce_x0 <= sysce; sysce_clr_x0 <= sysce_clr; sysclk_x0 <= sysclk; ce_1 <= xlclockdriver_1_ce; ce_logic_1 <= xlclockdriver_1_ce_logic; clk_1 <= xlclockdriver_1_clk; xlclockdriver_1: entity work.xlclockdriver generic map ( log_2_period => 1, period => 1, use_bufg => 0 ) port map ( sysce => sysce_x0, sysclk => sysclk_x0, sysclr => sysce_clr_x0, ce => xlclockdriver_1_ce, ce_logic => xlclockdriver_1_ce_logic, clk => xlclockdriver_1_clk ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity plb_clock_driver is port ( sysce: in std_logic; sysce_clr: in std_logic; sysclk: in std_logic; plb_ce_1: out std_logic; plb_clk_1: out std_logic ); end plb_clock_driver; architecture structural of plb_clock_driver is attribute syn_noprune: boolean; attribute syn_noprune of structural : architecture is true; attribute optimize_primitives: boolean; attribute optimize_primitives of structural : architecture is false; attribute dont_touch: boolean; attribute dont_touch of structural : architecture is true; signal sysce_clr_x0: std_logic; signal sysce_x0: std_logic; signal sysclk_x0: std_logic; signal xlclockdriver_1_ce: std_logic; signal xlclockdriver_1_clk: std_logic; begin sysce_x0 <= sysce; sysce_clr_x0 <= sysce_clr; sysclk_x0 <= sysclk; plb_ce_1 <= xlclockdriver_1_ce; plb_clk_1 <= xlclockdriver_1_clk; xlclockdriver_1: entity work.xlclockdriver generic map ( log_2_period => 1, period => 1, use_bufg => 0 ) port map ( sysce => sysce_x0, sysclk => sysclk_x0, sysclr => sysce_clr_x0, ce => xlclockdriver_1_ce, clk => xlclockdriver_1_clk ); end structural; library IEEE; use IEEE.std_logic_1164.all; use work.conv_pkg.all; entity sg_2d_fir_cw is port ( active_video_i: in std_logic; ce: in std_logic := '1'; clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz) hblank_i: in std_logic; hsync_i: in std_logic; plb_abus: in std_logic_vector(31 downto 0); plb_pavalid: in std_logic; plb_rnw: in std_logic; plb_wrdbus: in std_logic_vector(31 downto 0); reset: in std_logic; sg_plb_addrpref: in std_logic_vector(19 downto 0); splb_rst: in std_logic; vblank_i: in std_logic; video_data_i: in std_logic_vector(23 downto 0); vsync_i: in std_logic; xps_ce: in std_logic := '1'; xps_clk: in std_logic; -- clock period = 10.0 ns (100.0 Mhz) active_video_o: out std_logic; hblank_o: out std_logic; hsync_o: out std_logic; sl_addrack: out std_logic; sl_rdcomp: out std_logic; sl_rddack: out std_logic; sl_rddbus: out std_logic_vector(31 downto 0); sl_wait: out std_logic; sl_wrcomp: out std_logic; sl_wrdack: out std_logic; vblank_o: out std_logic; video_data_o: out std_logic_vector(23 downto 0); vsync_o: out std_logic ); end sg_2d_fir_cw; architecture structural of sg_2d_fir_cw is component block_memory_generator_spartan6_6_2_80846d0865f6122e port ( addra: in std_logic_vector(4 downto 0); addrb: in std_logic_vector(4 downto 0); clka: in std_logic; clkb: in std_logic; dina: in std_logic_vector(6 downto 0); dinb: in std_logic_vector(6 downto 0); ena: in std_logic; enb: in std_logic; wea: in std_logic_vector(0 downto 0); web: in std_logic_vector(0 downto 0); douta: out std_logic_vector(6 downto 0); doutb: out std_logic_vector(6 downto 0) ); end component; attribute syn_black_box: boolean; attribute syn_black_box of block_memory_generator_spartan6_6_2_80846d0865f6122e: component is true; attribute box_type: string; attribute box_type of block_memory_generator_spartan6_6_2_80846d0865f6122e: component is "black_box"; attribute syn_noprune: boolean; attribute optimize_primitives: boolean; attribute dont_touch: boolean; attribute syn_noprune of block_memory_generator_spartan6_6_2_80846d0865f6122e: component is true; attribute optimize_primitives of block_memory_generator_spartan6_6_2_80846d0865f6122e: component is false; attribute dont_touch of block_memory_generator_spartan6_6_2_80846d0865f6122e: component is true; component xlpersistentdff port ( clk: in std_logic; d: in std_logic; q: out std_logic ); end component; attribute syn_black_box of xlpersistentdff: component is true; attribute box_type of xlpersistentdff: component is "black_box"; attribute syn_noprune of xlpersistentdff: component is true; attribute optimize_primitives of xlpersistentdff: component is false; attribute dont_touch of xlpersistentdff: component is true; signal active_video_i_net: std_logic; signal active_video_o_net: std_logic; signal addr_net: std_logic_vector(4 downto 0); signal addr_x0_net: std_logic_vector(4 downto 0); signal ce_1_sg_x54: std_logic; attribute MAX_FANOUT: string; attribute MAX_FANOUT of ce_1_sg_x54: signal is "REDUCE"; signal ce_logic_1_sg_x25: std_logic; signal clkNet: std_logic; signal clkNet_x0: std_logic; signal clk_1_sg_x54: std_logic; signal coef_gain_reg_ce: std_logic; signal coef_update_reg_ce: std_logic; signal data_in_net: std_logic_vector(6 downto 0); signal data_in_x0_net: std_logic; signal data_in_x1_net: std_logic_vector(19 downto 0); signal data_in_x2_net: std_logic_vector(6 downto 0); signal data_out_net: std_logic_vector(19 downto 0); signal data_out_x0_net: std_logic; signal data_out_x1_net: std_logic_vector(6 downto 0); signal data_out_x2_net: std_logic_vector(6 downto 0); signal en_net: std_logic; signal en_x0_net: std_logic; signal hblank_i_net: std_logic; signal hblank_o_net: std_logic; signal hsync_i_net: std_logic; signal hsync_o_net: std_logic; signal persistentdff_inst_q: std_logic; attribute syn_keep: boolean; attribute syn_keep of persistentdff_inst_q: signal is true; attribute keep: boolean; attribute keep of persistentdff_inst_q: signal is true; attribute preserve_signal: boolean; attribute preserve_signal of persistentdff_inst_q: signal is true; signal plb_abus_net: std_logic_vector(31 downto 0); signal plb_ce_1_sg_x1: std_logic; attribute MAX_FANOUT of plb_ce_1_sg_x1: signal is "REDUCE"; signal plb_clk_1_sg_x1: std_logic; signal plb_pavalid_net: std_logic; signal plb_rnw_net: std_logic; signal plb_wrdbus_net: std_logic_vector(31 downto 0); signal reset_net: std_logic; signal sg_plb_addrpref_net: std_logic_vector(19 downto 0); signal sl_addrack_net: std_logic; signal sl_rdcomp_net: std_logic; signal sl_rddack_net: std_logic; signal sl_rddbus_net: std_logic_vector(31 downto 0); signal sl_wait_net: std_logic; signal sl_wrdack_x1: std_logic; signal sl_wrdack_x2: std_logic; signal splb_rst_net: std_logic; signal vblank_i_net: std_logic; signal vblank_o_net: std_logic; signal video_data_i_net: std_logic_vector(23 downto 0); signal video_data_o_net: std_logic_vector(23 downto 0); signal vsync_i_net: std_logic; signal vsync_o_net: std_logic; signal we_net: std_logic; signal we_x0_net: std_logic; begin active_video_i_net <= active_video_i; clkNet <= clk; hblank_i_net <= hblank_i; hsync_i_net <= hsync_i; plb_abus_net <= plb_abus; plb_pavalid_net <= plb_pavalid; plb_rnw_net <= plb_rnw; plb_wrdbus_net <= plb_wrdbus; reset_net <= reset; sg_plb_addrpref_net <= sg_plb_addrpref; splb_rst_net <= splb_rst; vblank_i_net <= vblank_i; video_data_i_net <= video_data_i; vsync_i_net <= vsync_i; clkNet_x0 <= xps_clk; active_video_o <= active_video_o_net; hblank_o <= hblank_o_net; hsync_o <= hsync_o_net; sl_addrack <= sl_addrack_net; sl_rdcomp <= sl_rdcomp_net; sl_rddack <= sl_rddack_net; sl_rddbus <= sl_rddbus_net; sl_wait <= sl_wait_net; sl_wrcomp <= sl_wrdack_x2; sl_wrdack <= sl_wrdack_x1; vblank_o <= vblank_o_net; video_data_o <= video_data_o_net; vsync_o <= vsync_o_net; coef_buffer: block_memory_generator_spartan6_6_2_80846d0865f6122e port map ( addra => addr_net, addrb => addr_x0_net, clka => clk_1_sg_x54, clkb => plb_clk_1_sg_x1, dina => data_in_net, dinb => data_in_x2_net, ena => ce_1_sg_x54, enb => plb_ce_1_sg_x1, wea(0) => we_net, web(0) => we_x0_net, douta => data_out_x1_net, doutb => data_out_x2_net ); coef_gain: entity work.synth_reg_w_init generic map ( width => 20, init_index => 2, init_value => b"11111111111111111111", latency => 1 ) port map ( ce => coef_gain_reg_ce, clk => plb_clk_1_sg_x1, clr => '0', i => data_in_x1_net, o => data_out_net ); coef_gain_ce_and2_comp: entity work.xland2 port map ( a => plb_ce_1_sg_x1, b => en_x0_net, dout => coef_gain_reg_ce ); coef_update: entity work.synth_reg_w_init generic map ( width => 1, init_index => 2, init_value => b"1", latency => 1 ) port map ( ce => coef_update_reg_ce, clk => plb_clk_1_sg_x1, clr => '0', i(0) => data_in_x0_net, o(0) => data_out_x0_net ); coef_update_ce_and2_comp: entity work.xland2 port map ( a => plb_ce_1_sg_x1, b => en_net, dout => coef_update_reg_ce ); default_clock_driver_x0: entity work.default_clock_driver port map ( sysce => '1', sysce_clr => '0', sysclk => clkNet, ce_1 => ce_1_sg_x54, ce_logic_1 => ce_logic_1_sg_x25, clk_1 => clk_1_sg_x54 ); persistentdff_inst: xlpersistentdff port map ( clk => clkNet, d => persistentdff_inst_q, q => persistentdff_inst_q ); plb_clock_driver_x0: entity work.plb_clock_driver port map ( sysce => '1', sysce_clr => '0', sysclk => clkNet_x0, plb_ce_1 => plb_ce_1_sg_x1, plb_clk_1 => plb_clk_1_sg_x1 ); sg_2d_fir_x0: entity work.sg_2d_fir port map ( active_video_i => active_video_i_net, ce_1 => ce_1_sg_x54, ce_logic_1 => ce_logic_1_sg_x25, clk_1 => clk_1_sg_x54, data_out => data_out_net, data_out_x0 => data_out_x0_net, data_out_x1 => data_out_x1_net, data_out_x2 => data_out_x2_net, dout => data_out_x0_net, dout_x0 => data_out_net, hblank_i => hblank_i_net, hsync_i => hsync_i_net, plb_abus => plb_abus_net, plb_ce_1 => plb_ce_1_sg_x1, plb_clk_1 => plb_clk_1_sg_x1, plb_pavalid => plb_pavalid_net, plb_rnw => plb_rnw_net, plb_wrdbus => plb_wrdbus_net, reset => reset_net, sg_plb_addrpref => sg_plb_addrpref_net, splb_rst => splb_rst_net, vblank_i => vblank_i_net, video_data_i => video_data_i_net, vsync_i => vsync_i_net, active_video_o => active_video_o_net, addr => addr_net, addr_x0 => addr_x0_net, data_in => data_in_net, data_in_x0 => data_in_x0_net, data_in_x1 => data_in_x1_net, data_in_x2 => data_in_x2_net, en => en_net, en_x0 => en_x0_net, hblank_o => hblank_o_net, hsync_o => hsync_o_net, sl_addrack => sl_addrack_net, sl_rdcomp => sl_rdcomp_net, sl_rddack => sl_rddack_net, sl_rddbus => sl_rddbus_net, sl_wait => sl_wait_net, sl_wrcomp => sl_wrdack_x2, sl_wrdack => sl_wrdack_x1, vblank_o => vblank_o_net, video_data_o => video_data_o_net, vsync_o => vsync_o_net, we => we_net, we_x0 => we_x0_net ); end structural;
-- file: genclks_tb.vhd -- -- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------ -- Clocking wizard demonstration testbench ------------------------------------------------------------------------------ -- This demonstration testbench instantiates the example design for the -- clocking wizard. Input clocks are toggled, which cause the clocking -- network to lock and the counters to increment. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; use ieee.std_logic_textio.all; library std; use std.textio.all; library work; use work.all; entity genclks_tb is end genclks_tb; architecture test of genclks_tb is -- Clock to Q delay of 100 ps constant TCQ : time := 100 ps; -- timescale is 1ps constant ONE_NS : time := 1 ns; -- how many cycles to run constant COUNT_PHASE : integer := 1024 + 1; -- we'll be using the period in many locations constant PER1 : time := 40.000 ns; -- Declare the input clock signals signal CLK_IN1 : std_logic := '1'; -- The high bits of the sampling counters signal COUNT : std_logic_vector(3 downto 1); -- Status and control signals signal RESET : std_logic := '0'; signal LOCKED : std_logic; signal COUNTER_RESET : std_logic := '0'; signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0'); -- signal defined to stop mti simulation without severity failure in the report signal end_of_sim : std_logic := '0'; signal CLK_OUT : std_logic_vector(3 downto 1); --Freq Check using the M & D values setting and actual Frequency generated component genclks_exdes port (-- Clock in ports CLK_IN1 : in std_logic; -- Reset that only drives logic in example design COUNTER_RESET : in std_logic; CLK_OUT : out std_logic_vector(3 downto 1) ; -- High bits of counters driven by clocks COUNT : out std_logic_vector(3 downto 1); -- Status and control signals RESET : in std_logic; LOCKED : out std_logic ); end component; begin -- Input clock generation -------------------------------------- process begin CLK_IN1 <= not CLK_IN1; wait for (PER1/2); end process; -- Test sequence process procedure simtimeprint is variable outline : line; begin write(outline, string'("## SYSTEM_CYCLE_COUNTER ")); write(outline, NOW/PER1); write(outline, string'(" ns")); writeline(output,outline); end simtimeprint; procedure simfreqprint (period : time; clk_num : integer) is variable outputline : LINE; variable str1 : string(1 to 16); variable str2 : integer; variable str3 : string(1 to 2); variable str4 : integer; variable str5 : string(1 to 4); begin str1 := "Freq of CLK_OUT("; str2 := clk_num; str3 := ") "; str4 := 1000000 ps/period ; str5 := " MHz" ; write(outputline, str1 ); write(outputline, str2); write(outputline, str3); write(outputline, str4); write(outputline, str5); writeline(output, outputline); end simfreqprint; begin report "Timing checks are not valid" severity note; RESET <= '1'; wait for (PER1*6); RESET <= '0'; wait until LOCKED = '1'; wait for (PER1*20); COUNTER_RESET <= '1'; wait for (PER1*19.5); COUNTER_RESET <= '0'; wait for (PER1*1); report "Timing checks are valid" severity note; wait for (PER1*COUNT_PHASE); simtimeprint; end_of_sim <= '1'; wait for 1 ps; report "Simulation Stopped." severity failure; wait; end process; process (CLK_IN1) procedure simtimeprint is variable outline : line; begin write(outline, string'("## SYSTEM_CYCLE_COUNTER ")); write(outline, NOW/PER1); write(outline, string'(" ns")); writeline(output,outline); end simtimeprint; begin if (CLK_IN1'event and CLK_IN1='1') then timeout_counter <= timeout_counter + '1'; if (timeout_counter = "10000000000000") then if (LOCKED /= '1') then simtimeprint; report "NO LOCK signal" severity failure; end if; end if; end if; end process; -- Instantiation of the example design containing the clock -- network and sampling counters ----------------------------------------------------------- dut : genclks_exdes port map (-- Clock in ports CLK_IN1 => CLK_IN1, -- Reset for logic in example design COUNTER_RESET => COUNTER_RESET, CLK_OUT => CLK_OUT, -- High bits of the counters COUNT => COUNT, -- Status and control signals RESET => RESET, LOCKED => LOCKED); -- Freq Check end test;
-- file: genclks_tb.vhd -- -- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------ -- Clocking wizard demonstration testbench ------------------------------------------------------------------------------ -- This demonstration testbench instantiates the example design for the -- clocking wizard. Input clocks are toggled, which cause the clocking -- network to lock and the counters to increment. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; use ieee.std_logic_textio.all; library std; use std.textio.all; library work; use work.all; entity genclks_tb is end genclks_tb; architecture test of genclks_tb is -- Clock to Q delay of 100 ps constant TCQ : time := 100 ps; -- timescale is 1ps constant ONE_NS : time := 1 ns; -- how many cycles to run constant COUNT_PHASE : integer := 1024 + 1; -- we'll be using the period in many locations constant PER1 : time := 40.000 ns; -- Declare the input clock signals signal CLK_IN1 : std_logic := '1'; -- The high bits of the sampling counters signal COUNT : std_logic_vector(3 downto 1); -- Status and control signals signal RESET : std_logic := '0'; signal LOCKED : std_logic; signal COUNTER_RESET : std_logic := '0'; signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0'); -- signal defined to stop mti simulation without severity failure in the report signal end_of_sim : std_logic := '0'; signal CLK_OUT : std_logic_vector(3 downto 1); --Freq Check using the M & D values setting and actual Frequency generated component genclks_exdes port (-- Clock in ports CLK_IN1 : in std_logic; -- Reset that only drives logic in example design COUNTER_RESET : in std_logic; CLK_OUT : out std_logic_vector(3 downto 1) ; -- High bits of counters driven by clocks COUNT : out std_logic_vector(3 downto 1); -- Status and control signals RESET : in std_logic; LOCKED : out std_logic ); end component; begin -- Input clock generation -------------------------------------- process begin CLK_IN1 <= not CLK_IN1; wait for (PER1/2); end process; -- Test sequence process procedure simtimeprint is variable outline : line; begin write(outline, string'("## SYSTEM_CYCLE_COUNTER ")); write(outline, NOW/PER1); write(outline, string'(" ns")); writeline(output,outline); end simtimeprint; procedure simfreqprint (period : time; clk_num : integer) is variable outputline : LINE; variable str1 : string(1 to 16); variable str2 : integer; variable str3 : string(1 to 2); variable str4 : integer; variable str5 : string(1 to 4); begin str1 := "Freq of CLK_OUT("; str2 := clk_num; str3 := ") "; str4 := 1000000 ps/period ; str5 := " MHz" ; write(outputline, str1 ); write(outputline, str2); write(outputline, str3); write(outputline, str4); write(outputline, str5); writeline(output, outputline); end simfreqprint; begin report "Timing checks are not valid" severity note; RESET <= '1'; wait for (PER1*6); RESET <= '0'; wait until LOCKED = '1'; wait for (PER1*20); COUNTER_RESET <= '1'; wait for (PER1*19.5); COUNTER_RESET <= '0'; wait for (PER1*1); report "Timing checks are valid" severity note; wait for (PER1*COUNT_PHASE); simtimeprint; end_of_sim <= '1'; wait for 1 ps; report "Simulation Stopped." severity failure; wait; end process; process (CLK_IN1) procedure simtimeprint is variable outline : line; begin write(outline, string'("## SYSTEM_CYCLE_COUNTER ")); write(outline, NOW/PER1); write(outline, string'(" ns")); writeline(output,outline); end simtimeprint; begin if (CLK_IN1'event and CLK_IN1='1') then timeout_counter <= timeout_counter + '1'; if (timeout_counter = "10000000000000") then if (LOCKED /= '1') then simtimeprint; report "NO LOCK signal" severity failure; end if; end if; end if; end process; -- Instantiation of the example design containing the clock -- network and sampling counters ----------------------------------------------------------- dut : genclks_exdes port map (-- Clock in ports CLK_IN1 => CLK_IN1, -- Reset for logic in example design COUNTER_RESET => COUNTER_RESET, CLK_OUT => CLK_OUT, -- High bits of the counters COUNT => COUNT, -- Status and control signals RESET => RESET, LOCKED => LOCKED); -- Freq Check end test;
library IEEE; use IEEE.STD_LOGIC_1164.all; entity top is generic( N: integer := 4 ); port( clk : in STD_LOGIC; reset : in STD_LOGIC; d1 : in STD_LOGIC_VECTOR(N-1 downto 0); d2 : in STD_LOGIC_VECTOR(N-1 downto 0); r : out STD_LOGIC_VECTOR(2*N-1 downto 0) ); end top; architecture top of top is component control_unit port ( clk,reset : in STD_LOGIC; X: in STD_LOGIC_vector(4 downto 1); Y: out STD_LOGIC_vector(12 downto 1) ); end component; component operational_unit port( clk,rst : in STD_LOGIC; y : in STD_LOGIC_VECTOR(12 downto 1); d1 : in STD_LOGIC_VECTOR(N-1 downto 0); d2 : in STD_LOGIC_VECTOR(N-1 downto 0); r:out STD_LOGIC_VECTOR(2*N-1 downto 0); x:out STD_LOGIC_vector(4 downto 1) ); end component; signal y : std_logic_vector(12 downto 1); signal x : std_logic_vector(4 downto 1); begin dd1:control_unit port map (clk,reset,x,y); dd2:operational_unit port map (clk => clk ,rst => reset,d1 => d1, d2 =>d2, y=>y, x=>x, r =>r); end top;
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY Mxor IS PORT( A, B: IN STD_LOGIC; R: OUT STD_LOGIC ); END Mxor; ARCHITECTURE pure_logic OF Mxor IS COMPONENT Mor IS PORT ( A, B: IN STD_LOGIC; R: OUT STD_LOGIC ); END COMPONENT; COMPONENT Mand IS PORT ( A, B: IN STD_LOGIC; R: OUT STD_LOGIC ); END COMPONENT; COMPONENT Mnot IS PORT ( A: IN STD_LOGIC; R: OUT STD_LOGIC ); END COMPONENT; signal signal_result: STD_LOGIC; signal signal_result2: STD_LOGIC; signal X: STD_LOGIC; signal Y: STD_LOGIC; BEGIN G1: Mnot port map(A, signal_result); G2: Mnot port map(B, signal_result2); G3: Mand port map(signal_result, B, x); G4: Mand port map(A, signal_result2, y); G5: Mor port map(X, Y, R); END pure_logic;
--------------------------------------------------------------------------- -- -- Module : decode_8b10b_rtl.vhd -- -- Version : 1.1 -- -- Last Update : 2008-10-31 -- -- Project : 8b/10b Decoder Reference Design -- -- Description : Top-level, synthesizable 8b/10b decoder core file -- -- Company : Xilinx, Inc. -- -- DISCLAIMER OF LIABILITY -- -- This file contains proprietary and confidential information of -- Xilinx, Inc. ("Xilinx"), that is distributed under a license -- from Xilinx, and may be used, copied and/or disclosed only -- pursuant to the terms of a valid license agreement with Xilinx. -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx -- does not warrant that functions included in the Materials will -- meet the requirements of Licensee, or that the operation of the -- Materials will be uninterrupted or error-free, or that defects -- in the Materials will be corrected. Furthermore, Xilinx does -- not warrant or make any representations regarding use, or the -- results of the use, of the Materials in terms of correctness, -- accuracy, reliability or otherwise. -- -- Xilinx products are not designed or intended to be fail-safe, -- or for use in any application requiring fail-safe performance, -- such as life-support or safety devices or systems, Class III -- medical devices, nuclear facilities, applications related to -- the deployment of airbags, or any other applications that could -- lead to death, personal injury or severe property or -- environmental damage (individually and collectively, "critical -- applications"). Customer assumes the sole risk and liability -- of any use of Xilinx products in critical applications, -- subject only to applicable laws and regulations governing -- limitations on product liability. -- -- Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2008 Xilinx, Inc. -- All rights reserved. -- -- This disclaimer and copyright notice must be retained as part -- of this file at all times. -- ------------------------------------------------------------------------------- -- -- History -- -- Date Version Description -- -- 10/31/2008 1.1 Initial release -- ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_arith.ALL; LIBRARY decode_8b10b; USE decode_8b10b.decode_8b10b_pkg.ALL; ----------------------------------------------------------------------------- -- Entity Declaration ----------------------------------------------------------------------------- ENTITY decode_8b10b_rtl IS GENERIC ( C_DECODE_TYPE : INTEGER := 0; C_ELABORATION_DIR : STRING := "./../../src/"; C_HAS_BPORTS : INTEGER := 0; C_HAS_CE : INTEGER := 0; C_HAS_CE_B : INTEGER := 0; C_HAS_CODE_ERR : INTEGER := 0; C_HAS_CODE_ERR_B : INTEGER := 0; C_HAS_DISP_ERR : INTEGER := 0; C_HAS_DISP_ERR_B : INTEGER := 0; C_HAS_DISP_IN : INTEGER := 0; C_HAS_DISP_IN_B : INTEGER := 0; C_HAS_ND : INTEGER := 0; C_HAS_ND_B : INTEGER := 0; C_HAS_RUN_DISP : INTEGER := 0; C_HAS_RUN_DISP_B : INTEGER := 0; C_HAS_SINIT : INTEGER := 0; C_HAS_SINIT_B : INTEGER := 0; C_HAS_SYM_DISP : INTEGER := 0; C_HAS_SYM_DISP_B : INTEGER := 0; C_SINIT_DOUT : STRING := "00000000"; C_SINIT_DOUT_B : STRING := "00000000"; C_SINIT_KOUT : INTEGER := 0; C_SINIT_KOUT_B : INTEGER := 0; C_SINIT_RUN_DISP : INTEGER := 0; C_SINIT_RUN_DISP_B : INTEGER := 0 ); PORT ( CLK : IN STD_LOGIC := '0'; DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0'); DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ; KOUT : OUT STD_LOGIC ; CE : IN STD_LOGIC := '0'; CE_B : IN STD_LOGIC := '0'; CLK_B : IN STD_LOGIC := '0'; DIN_B : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0'); DISP_IN : IN STD_LOGIC := '0'; DISP_IN_B : IN STD_LOGIC := '0'; SINIT : IN STD_LOGIC := '0'; SINIT_B : IN STD_LOGIC := '0'; CODE_ERR : OUT STD_LOGIC := '0'; CODE_ERR_B : OUT STD_LOGIC := '0'; DISP_ERR : OUT STD_LOGIC := '0'; DISP_ERR_B : OUT STD_LOGIC := '0'; DOUT_B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ; KOUT_B : OUT STD_LOGIC ; ND : OUT STD_LOGIC := '0'; ND_B : OUT STD_LOGIC := '0'; RUN_DISP : OUT STD_LOGIC ; RUN_DISP_B : OUT STD_LOGIC ; SYM_DISP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ; SYM_DISP_B : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ); END decode_8b10b_rtl; -------------------------------------------------------------------------------- -- Generic Definitions: -------------------------------------------------------------------------------- -- C_DECODE_TYPE : Implementation: 0=Slice based, 1=BlockRam -- C_ELABORATION_DIR : Directory path for mif file -- C_HAS_BPORTS : 1 indicates second decoder should be generated -- C_HAS_CE : 1 indicates ce port is present -- C_HAS_CE_B : 1 indicates ce_b port is present (if c_has_bports=1) -- C_HAS_CODE_ERR : 1 indicates code_err port is present -- C_HAS_CODE_ERR_B : 1 indicates code_err_b port is present -- (if c_has_bports=1) -- C_HAS_DISP_ERR : 1 indicates disp_err port is present -- C_HAS_DISP_ERR_B : 1 indicates disp_err_b port is present -- (if c_has_bports=1) -- C_HAS_DISP_IN : 1 indicates disp_in port is present -- C_HAS_DISP_IN_B : 1 indicates disp_in_b port is present -- (if c_has_bports=1) -- C_HAS_ND : 1 indicates nd port is present -- C_HAS_ND_B : 1 indicates nd_b port is present (if c_has_bports=1) -- C_HAS_RUN_DISP : 1 indicates run_disp port is present -- C_HAS_RUN_DISP_B : 1 indicates run_disp_b port is present -- (if c_has_bports=1) -- C_HAS_SINIT : 1 indicates sinit port is present -- C_HAS_SINIT_B : 1 indicates sinit_b port is present -- (if c_has_bports=1) -- C_HAS_SYM_DISP : 1 indicates sym_disp port is present -- C_HAS_SYM_DISP_B : 1 indicates sym_disp_b port is present -- (if c_has_bports=1) -- C_SINIT_DOUT : 8-bit binary string, dout value when sinit is active -- C_SINIT_DOUT_B : 8-bit binary string, dout_b value when sinit_b is -- active -- C_SINIT_KOUT : controls kout output when sinit is active -- C_SINIT_KOUT_B : controls kout_b output when sinit_b is active -- C_SINIT_RUN_DISP : Initializes run_disp (and disp_in) value to -- positive(1) or negative(0) -- C_SINIT_RUN_DISP_B : Initializes run_disp_b (and disp_in_b) value to -- positive(1) or negative(0) -------------------------------------------------------------------------------- -- Port Definitions: -------------------------------------------------------------------------------- -- Mandatory Pins -- CLK : Clock Input -- DIN : Encoded Symbol Input -- DOUT : Data Output, decoded data byte -- KOUT : Command Output ------------------------------------------------------------------------- -- Optional Pins -- CE : Clock Enable -- CE_B : Clock Enable (B port) -- CLK_B : Clock Input (B port) -- DIN_B : Encoded Symbol Input (B port) -- DISP_IN : Disparity Input (running disparity in) -- DISP_IN_B : Disparity Input (running disparity in) (B port) -- SINIT : Synchronous Initialization. Resets core to known state. -- SINIT_B : Synchronous Initialization. Resets core to known state. -- (B port) -- CODE_ERR : Code Error, indicates that input symbol did not correspond -- to a valid member of the code set. -- CODE_ERR_B : Code Error, indicates that input symbol did not correspond -- to a valid member of the code set. (B port) -- DISP_ERR : Disparity Error -- DISP_ERR_B : Disparity Error (B port) -- DOUT_B : Data Output, decoded data byte (B port) -- KOUT_B : Command Output (B port) -- ND : New Data -- ND_B : New Data (B port) -- RUN_DISP : Running Disparity -- RUN_DISP_B : Running Disparity (B port) -- SYM_DISP : Symbol Disparity -- SYM_DISP_B : Symbol Disparity (B port) ------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- ARCHITECTURE xilinx OF decode_8b10b_rtl IS ------------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------------- SIGNAL dout_i : STD_LOGIC_VECTOR(7 DOWNTO 0) := str_to_slv(C_SINIT_DOUT,8); --convert C_SINIT_DOUT string to 8bit std_logic_vector SIGNAL kout_i : STD_LOGIC := bint_2_sl(C_SINIT_KOUT); --convert C_SINIT_KOUT integer to std_logic SIGNAL clk_b_i : STD_LOGIC := '0'; SIGNAL din_b_i : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0'); SIGNAL ce_i : STD_LOGIC := '0'; SIGNAL ce_b_i : STD_LOGIC := '0'; SIGNAL disp_in_i : STD_LOGIC := '0'; SIGNAL disp_in_b_i : STD_LOGIC := '0'; SIGNAL sinit_i : STD_LOGIC := '0'; SIGNAL sinit_b_i : STD_LOGIC := '0'; SIGNAL code_err_i : STD_LOGIC := '0'; SIGNAL code_err_b_i : STD_LOGIC := '0'; SIGNAL disp_err_i : STD_LOGIC := '0'; SIGNAL disp_err_b_i : STD_LOGIC := '0'; SIGNAL dout_b_i : STD_LOGIC_VECTOR(7 DOWNTO 0) := str_to_slv(C_SINIT_DOUT_B,8); --convert C_SINIT_DOUT_B string to 8bit std_logic_vector SIGNAL kout_b_i : STD_LOGIC := bint_2_sl(C_SINIT_KOUT_B); --convert C_SINIT_KOUT_B integer to std_logic SIGNAL nd_i : STD_LOGIC := '0'; SIGNAL nd_b_i : STD_LOGIC := '0'; SIGNAL run_disp_i : STD_LOGIC := bint_2_sl(C_SINIT_RUN_DISP); --convert C_SINIT_RUN_DISP integer to std logic SIGNAL run_disp_b_i : STD_LOGIC := bint_2_sl(C_SINIT_RUN_DISP_B); --convert C_SINIT_RUN_DISP_B integer to std logic SIGNAL sym_disp_i : STD_LOGIC_VECTOR(1 DOWNTO 0) := conv_std_logic_vector(C_SINIT_RUN_DISP,2); --convert C_SINIT_RUN_DISP integer to slv SIGNAL sym_disp_b_i : STD_LOGIC_VECTOR(1 DOWNTO 0) := conv_std_logic_vector(C_SINIT_RUN_DISP_B,2); --convert C_SINIT_RUN_DISP_B integer to slv ------------------------------------------------------------------------------- -- Begin Architecture ------------------------------------------------------------------------------- BEGIN ----------------------------------------------------------------------------- -- LUT-based decoder ----------------------------------------------------------------------------- glut : IF (C_DECODE_TYPE = 0) GENERATE ldec : ENTITY decode_8b10b.decode_8b10b_lut GENERIC MAP ( C_HAS_BPORTS => C_HAS_BPORTS, C_HAS_CODE_ERR => C_HAS_CODE_ERR, C_HAS_CODE_ERR_B => C_HAS_CODE_ERR_B, C_HAS_DISP_ERR => C_HAS_DISP_ERR, C_HAS_DISP_ERR_B => C_HAS_DISP_ERR_B, C_HAS_DISP_IN => C_HAS_DISP_IN, C_HAS_DISP_IN_B => C_HAS_DISP_IN_B, C_HAS_ND => C_HAS_ND, C_HAS_ND_B => C_HAS_ND_B, C_HAS_SYM_DISP => C_HAS_SYM_DISP, C_HAS_SYM_DISP_B => C_HAS_SYM_DISP_B, C_HAS_RUN_DISP => C_HAS_RUN_DISP, C_HAS_RUN_DISP_B => C_HAS_RUN_DISP_B, C_SINIT_DOUT => C_SINIT_DOUT, C_SINIT_DOUT_B => C_SINIT_DOUT_B, C_SINIT_KOUT => C_SINIT_KOUT, C_SINIT_KOUT_B => C_SINIT_KOUT_B, C_SINIT_RUN_DISP => C_SINIT_RUN_DISP, C_SINIT_RUN_DISP_B => C_SINIT_RUN_DISP_B ) PORT MAP( CLK => CLK, DIN => DIN, DOUT => dout_i, KOUT => kout_i, CE => ce_i, DISP_IN => disp_in_i, SINIT => sinit_i, CODE_ERR => code_err_i, DISP_ERR => disp_err_i, ND => nd_i, RUN_DISP => run_disp_i, SYM_DISP => sym_disp_i, CLK_B => clk_b_i, DIN_B => din_b_i, DOUT_B => dout_b_i, KOUT_B => kout_b_i, CE_B => ce_b_i, DISP_IN_B => disp_in_b_i, SINIT_B => sinit_b_i, CODE_ERR_B => code_err_b_i, DISP_ERR_B => disp_err_b_i, ND_B => nd_b_i, RUN_DISP_B => run_disp_b_i, SYM_DISP_B => sym_disp_b_i ); END GENERATE glut; ----------------------------------------------------------------------------- -- BRAM-based decoder ----------------------------------------------------------------------------- gbram : IF (C_DECODE_TYPE /= 0) GENERATE bdec : ENTITY decode_8b10b.decode_8b10b_bram GENERIC MAP ( C_ELABORATION_DIR => C_ELABORATION_DIR, C_HAS_BPORTS => C_HAS_BPORTS, C_HAS_DISP_IN => C_HAS_DISP_IN, C_HAS_DISP_IN_B => C_HAS_DISP_IN_B, C_HAS_DISP_ERR => C_HAS_DISP_ERR, C_HAS_DISP_ERR_B => C_HAS_DISP_ERR_B, C_HAS_RUN_DISP => C_HAS_RUN_DISP, C_HAS_RUN_DISP_B => C_HAS_RUN_DISP_B, C_HAS_SYM_DISP => C_HAS_SYM_DISP, C_HAS_SYM_DISP_B => C_HAS_SYM_DISP_B, C_HAS_ND => C_HAS_ND, C_HAS_ND_B => C_HAS_ND_B, C_SINIT_DOUT => C_SINIT_DOUT, C_SINIT_DOUT_B => C_SINIT_DOUT_B, C_SINIT_KOUT => C_SINIT_KOUT, C_SINIT_KOUT_B => C_SINIT_KOUT_B, C_SINIT_RUN_DISP => C_SINIT_RUN_DISP, C_SINIT_RUN_DISP_B => C_SINIT_RUN_DISP_B ) PORT MAP( CLK => CLK, DIN => DIN, DOUT => dout_i, KOUT => kout_i, CE => ce_i, DISP_IN => disp_in_i, SINIT => sinit_i, CODE_ERR => code_err_i, DISP_ERR => disp_err_i, ND => nd_i, RUN_DISP => run_disp_i, SYM_DISP => sym_disp_i, CLK_B => clk_b_i, DIN_B => din_b_i, DOUT_B => dout_b_i, KOUT_B => kout_b_i, CE_B => ce_b_i, DISP_IN_B => disp_in_b_i, SINIT_B => sinit_b_i, CODE_ERR_B => code_err_b_i, DISP_ERR_B => disp_err_b_i, ND_B => nd_b_i, RUN_DISP_B => run_disp_b_i, SYM_DISP_B => sym_disp_b_i ); END GENERATE gbram; --------------------------------------------------------------------------- -- Mandatory A Ports --------------------------------------------------------------------------- DOUT <= dout_i; KOUT <= kout_i; --------------------------------------------------------------------------- -- Optional A Ports --tying off unused ports --------------------------------------------------------------------------- --Inputs --ce gen : IF (C_HAS_CE/=0) GENERATE ce_i <= CE; END GENERATE gen; ngen : IF (C_HAS_CE = 0) GENERATE ce_i <= '1'; END GENERATE ngen; --disp_in gdi : IF (C_HAS_DISP_IN /= 0) GENERATE disp_in_i <= DISP_IN; END GENERATE gdi; ngdi : IF (C_HAS_DISP_IN = 0) GENERATE disp_in_i <= '0'; END GENERATE ngdi; --sinit gs : IF (C_HAS_SINIT /= 0) GENERATE sinit_i <= SINIT; END GENERATE gs; ngs : IF (C_HAS_SINIT = 0) GENERATE sinit_i <= '0'; END GENERATE ngs; --Outputs --nd gnd : IF (C_HAS_ND /= 0) GENERATE ASSERT (C_HAS_CE /= 0) REPORT "Invalid configuration: ND port requires CE port" SEVERITY WARNING; ND <= nd_i; END GENERATE gnd; ngnd : IF (C_HAS_ND = 0) GENERATE ND <= '0'; END GENERATE ngnd; --code_err gce : IF (C_HAS_CODE_ERR /= 0) GENERATE CODE_ERR <= code_err_i; END GENERATE gce; ngce : IF (C_HAS_CODE_ERR = 0) GENERATE CODE_ERR <= '0'; END GENERATE ngce; --disp_err gder : IF (C_HAS_DISP_ERR /= 0) GENERATE DISP_ERR <= disp_err_i; END GENERATE gder; ngder : IF (C_HAS_DISP_ERR = 0) GENERATE DISP_ERR <= '0'; END GENERATE ngder; --run_disp grd : IF (C_HAS_RUN_DISP /= 0) GENERATE RUN_DISP <= run_disp_i; END GENERATE grd; ngrd : IF (C_HAS_RUN_DISP = 0) GENERATE RUN_DISP <= '0'; END GENERATE ngrd; --sym_disp gsd : IF (C_HAS_SYM_DISP /= 0) GENERATE SYM_DISP <= sym_disp_i; END GENERATE gsd; ngsd : IF (C_HAS_SYM_DISP = 0) GENERATE SYM_DISP <= "00"; END GENERATE ngsd; ---------------------------------------------------------------------------- -- Optional B Ports -- tying off unused ports ---------------------------------------------------------------------------- --Mandatory B ports (if B ports are selected) gbpt : IF (C_HAS_BPORTS /= 0) GENERATE din_b_i <= DIN_B; clk_b_i <= CLK_B; DOUT_B <= dout_b_i; KOUT_B <= kout_b_i; END GENERATE gbpt; ngbpt : IF (C_HAS_BPORTS = 0) GENERATE din_b_i <= (OTHERS => '0'); clk_b_i <= '0'; DOUT_B <= (OTHERS => '0'); KOUT_B <= '0'; END GENERATE ngbpt; --Inputs --ce_b genb : IF (C_HAS_CE_B /= 0 AND C_HAS_BPORTS /= 0) GENERATE ce_b_i <= CE_B; END GENERATE genb; ngenb : IF (C_HAS_CE_B = 0 OR C_HAS_BPORTS = 0) GENERATE ce_b_i <= '1'; END GENERATE ngenb; ASSERT (NOT(C_HAS_CE_B /= 0 AND C_HAS_BPORTS = 0)) REPORT "Invalid configuration: Will not generate CE_B when C_HAS_BPORTS=0" SEVERITY WARNING; --disp_in_b gdib : IF (C_HAS_DISP_IN_B /= 0 AND C_HAS_BPORTS /= 0) GENERATE disp_in_b_i <= DISP_IN_B; END GENERATE gdib; ngdib : IF (C_HAS_DISP_IN_B = 0 OR C_HAS_BPORTS = 0) GENERATE disp_in_b_i <= '0'; END GENERATE ngdib; ASSERT (NOT(C_HAS_DISP_IN_B /= 0 AND C_HAS_BPORTS = 0)) REPORT "Invalid configuration: Will not generate DISP_IN_B when " & "C_HAS_BPORTS=0" SEVERITY WARNING; --sinit_b gsb : IF (C_HAS_SINIT_B /= 0 AND C_HAS_BPORTS /= 0) GENERATE sinit_b_i <= SINIT_B; END GENERATE gsb; ngsb : IF (C_HAS_SINIT_B = 0 OR C_HAS_BPORTS = 0) GENERATE sinit_b_i <= '0'; END GENERATE ngsb; ASSERT (NOT(C_HAS_SINIT_B /= 0 AND C_HAS_BPORTS = 0)) REPORT "Invalid configuration: Will not generate SINIT_B when C_HAS_BPORTS=0" SEVERITY WARNING; --Outputs --code_err_b gceb : IF (C_HAS_CODE_ERR_B /= 0 AND C_HAS_BPORTS /= 0) GENERATE CODE_ERR_B <= code_err_b_i; END GENERATE gceb; ngceb : IF (C_HAS_CODE_ERR_B = 0 OR C_HAS_BPORTS = 0) GENERATE CODE_ERR_B <= '0'; END GENERATE ngceb; ASSERT (NOT(C_HAS_CODE_ERR_B /= 0 AND C_HAS_BPORTS = 0)) REPORT "Invalid configuration: Will not generate CODE_ERR_B when " & "C_HAS_BPORTS=0" SEVERITY WARNING; --disp_err_b gdeb : IF (C_HAS_DISP_ERR_B /= 0 AND C_HAS_BPORTS /= 0) GENERATE DISP_ERR_B <= disp_err_b_i; END GENERATE gdeb; ngdeb : IF (C_HAS_DISP_ERR_B = 0 OR C_HAS_BPORTS = 0) GENERATE DISP_ERR_B <= '0'; END GENERATE ngdeb; ASSERT (NOT(C_HAS_DISP_ERR_B /= 0 AND C_HAS_BPORTS = 0)) REPORT "Invalid configuration: Will not generate DISP_ERR_B when " & "C_HAS_BPORTS=0" SEVERITY WARNING; --nd_b gndb : IF (C_HAS_ND_B /= 0 AND C_HAS_BPORTS /= 0) GENERATE ASSERT (C_HAS_CE_B /= 0) REPORT "Invalid configuration: ND_B port requires CE_B port" SEVERITY WARNING; ND_B <= nd_b_i; END GENERATE gndb; ngndb : IF (C_HAS_ND_B = 0 OR C_HAS_BPORTS = 0) GENERATE ND_B <= '0'; END GENERATE ngndb; ASSERT (NOT(C_HAS_ND_B /= 0 AND C_HAS_BPORTS = 0)) REPORT "Invalid configuration: Will not generate ND_B when C_HAS_BPORTS=0" SEVERITY WARNING; --run_disp_b grdb : IF (C_HAS_RUN_DISP_B /= 0 AND C_HAS_BPORTS /= 0) GENERATE RUN_DISP_B <= run_disp_b_i; END GENERATE grdb; ngrdb : IF (C_HAS_RUN_DISP_B = 0 OR C_HAS_BPORTS = 0) GENERATE RUN_DISP_B <= '0'; END GENERATE ngrdb; ASSERT (NOT(C_HAS_RUN_DISP_B /= 0 AND C_HAS_BPORTS = 0)) REPORT "Invalid configuration: Will not generate RUN_DISP_B when " & "C_HAS_BPORTS=0" SEVERITY WARNING; --sym_disp_b gsdb : IF (C_HAS_SYM_DISP_B /= 0 AND C_HAS_BPORTS /= 0) GENERATE SYM_DISP_B <= sym_disp_b_i; END GENERATE gsdb; ngsdb : IF (C_HAS_SYM_DISP_B = 0 OR C_HAS_BPORTS = 0) GENERATE SYM_DISP_B <= "00"; END GENERATE ngsdb; ASSERT (NOT(C_HAS_SYM_DISP_B /= 0 AND C_HAS_BPORTS = 0)) REPORT "Invalid configuration: Will not generate SYM_DISP_B when " & "C_HAS_BPORTS=0" SEVERITY WARNING; END xilinx;
--------------------------------------------------------- -- MC613 - UNICAMP -- -- Minesweeper -- -- Caian Benedicto -- Brunno Rodrigues Arangues --------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; library work; use work.all; entity vga_game_dec is port( -- Estado do jogo game_state : in std_logic_vector (1 downto 0); -- Tipo do elemento e indice na ROM element : in std_logic_vector (7 downto 0); elemidx : out std_logic_vector (5 downto 0) ); end entity; architecture vga_game_dec_logic of vga_game_dec is signal w, e, f, c, m : std_logic; begin -- Vitoria w <= game_state(0); -- Fim do jogo e <= game_state(1); -- Elemento mina m <= '1' when element(3 downto 0) = "1111" else '0'; f <= element(4); c <= element(5); process (w, e, f, c, m) begin if ((not c and not e and not f and not w) or (not c and not f and not m and not w)) = '1' then -- Bloco fechado elemidx <= "001001"; elsif ((c and e and not f and not m) or (c and not f and not m and not w)) = '1' then -- Bloco de numero elemidx <= "00" & element(3 downto 0); elsif (c and not f and m and not w) = '1' then -- Explosao elemidx <= "001101"; elsif ((not c and e and f and m) or (not c and e and m and w) or (not c and not e and f and not w)) = '1' then -- Bandeira elemidx <= "001010"; elsif (not c and e and not f and m and not w) = '1' then -- Mina elemidx <= "001011"; elsif (not c and e and f and not m and not w) = '1' then -- Bandeira errada elemidx <= "001100"; else -- Situacao de erro elemidx <= "001110"; end if; end process; end architecture;
--! @file poly_dds_tb.vhd --! @brief Polyphase Direct Digital Synthesizer Testbench --! @author Scott Teal (Scott@Teals.org) --! @date 2013-12-17 --! @copyright --! Copyright 2013 Richard Scott Teal, Jr. --! --! Licensed under the Apache License, Version 2.0 (the "License"); you may not --! use this file except in compliance with the License. You may obtain a copy --! of the License at --! --! http://www.apache.org/licenses/LICENSE-2.0 --! --! Unless required by applicable law or agreed to in writing, software --! distributed under the License is distributed on an "AS IS" BASIS, WITHOUT --! WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the --! License for the specific language governing permissions and limitations --! under the License. --! Standard IEEE library library ieee; use ieee.std_logic_1164.all; use ieee.math_real.all; use ieee.numeric_std.all; library boostdsp; use boostdsp.fixed_pkg.all; use boostdsp.util_pkg.all; use boostdsp.rf_blocks_pkg; --! Tests the boostdsp.dds entity. entity poly_dds_tb is end entity; architecture sim of poly_dds_tb is constant NUM_CHANNELS : positive := 16; constant CH_MAX : positive := NUM_CHANNELS - 1; constant clk_p : time := 10 ns; constant clk_hp : time := clk_p / 2; signal clk : std_logic := '0'; signal rst : std_logic := '1'; signal freq : ufixed(-1 downto -9) := to_ufixed(0.1, -1, -9); signal phase : ufixed(-1 downto -9) := to_ufixed(0, -1, -9); signal i_out : sfixed_vector(0 to CH_MAX)(1 downto -6); signal q_out : sfixed_vector(0 to CH_MAX)(1 downto -6); signal vis_i_out : signed_vector(0 to CH_MAX)(7 downto 0); signal vis_q_out : signed_vector(0 to CH_MAX)(7 downto 0); signal vis_combined_i : signed(7 downto 0); signal vis_combined_q : signed(7 downto 0); begin --! Polyphase DDS Unit Under Test uut: rf_blocks_pkg.poly_dds port map( clk => clk, rst => rst, freq => freq, phase => phase, i_out => i_out, q_out => q_out ); --! Clock generator clk_proc : process begin wait for clk_hp; clk <= not clk; end process; --! Reset generator rst_proc : process begin wait for clk_p * 4; rst <= '0'; wait; end process; --! Test the phase shifting input phase_test_proc : process begin wait for clk_p * 20; phase <= to_ufixed(0.2, phase); wait for clk_p * 20; phase <= to_ufixed(0.5, phase); wait for clk_p * 20; phase <= to_ufixed(0, phase); wait; end process; --! Visualize all generated sinusoids visualize : for i in i_out'range generate vis_i_out(i) <= sfixed_as_signed(i_out(i)); vis_q_out(i) <= sfixed_as_signed(q_out(i)); end generate; --! Upconvert and serialize all sinusoids to get high-speed sinusoids visualize_combined : process begin wait until rising_edge(clk); wait for clk_p / (i_out'length + 2); while true loop for i in i_out'range loop vis_combined_i <= vis_i_out(i); vis_combined_q <= vis_q_out(i); wait for clk_p / i_out'length; end loop; end loop; end process; end sim;