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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** CORE ***
--*** ***
--*** DP_INVSQR_CORE.VHD ***
--*** ***
--*** Function: 54 bit Inverse Square Root ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 24/04/09 - SIII/SIV multiplier support ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** SII Latency = 31 + 2*doublespeed ***
--*** SIII/IV Latency = 30 + doublespeed ***
--*** 1. Output is rounded already, LSB always 0 ***
--***************************************************
ENTITY dp_invsqr_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
odd : IN STD_LOGIC;
invroot : OUT STD_LOGIC_VECTOR (54 DOWNTO 1)
);
END dp_invsqr_core;
ARCHITECTURE rtl OF dp_invsqr_core IS
--SII mullatency = speed+5, SIII/IV mullatency = 4
constant mullatency : positive := doublespeed+5 - device*(1+doublespeed);
signal zerovec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal evennum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddnum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guessvec : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddff : STD_LOGIC_VECTOR (25+doublespeed DOWNTO 1);
signal scalenumff : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guess : STD_LOGIC_VECTOR (18 DOWNTO 1);
-- 1st iteration
signal radicanddelone : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal guessdel : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal multoneone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonetwo : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal multonetwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal suboneff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonethr : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal guessonevec : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- 2ns iteration
signal radicanddeltwo : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal guessonevecdelone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal guessonevecdeltwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multtwoone : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal multtwotwo : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multtwotwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal finaladdsub : STD_LOGIC;
signal finaladdsubff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal finaladdff : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal multtwothr : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal finalguessvec : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal invrootvec : STD_LOGIC_VECTOR (53 DOWNTO 1);
component fp_invsqr_est IS
GENERIC (synthesize : integer := 0); -- 0 = behavioral, 1 = syntheziable
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invroot : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
end component;
component dp_fxadd IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
oddnum <= conv_std_logic_vector(185363,18); -- mult by 2^-.5 (odd exp)
evennum <= conv_std_logic_vector(262143,18); -- mult by 1 (even exp)
gza: FOR k IN 1 TO 54 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- in level 0, out level 5
look: fp_invsqr_est
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radicand=>radicand(54 DOWNTO 36),invroot=>guessvec);
pta: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 25+doublespeed LOOP
oddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
oddff(1) <= odd;
FOR k IN 2 TO 25+doublespeed LOOP
oddff(k) <= oddff(k-1);
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= (oddnum(k) AND oddff(4)) OR (evennum(k) AND NOT(oddff(4)));
END LOOP;
END IF;
END IF;
END PROCESS;
-- in level 5, out level 7
mulscale: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>18,pipes=>2,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessvec,databb=>scalenumff,
result=>guess);
--*********************
--*** ITERATION ONE ***
--*********************
--X' = X/2(3-YXX)
deloneone: fp_del
GENERIC MAP(width=>54,pipes=>9)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicand,cc=>radicanddelone);
delonetwo: fp_del
GENERIC MAP(width=>18,pipes=>7)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guess,cc=>guessdel);
-- in level 7, out level 9 (18x18=36)
oneone: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36,pipes=>2,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guess,databb=>guess,
result=>multoneone);
-- in level 9, out level 12 (36x36=37)
onetwo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>37,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>radicanddelone(54 DOWNTO 19),databb=>multoneone,
result=>multonetwo);
-- multonetwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (37 DOWNTO 2), otherwise (38 DOWNTO 3)
-- round bit in position 1 or 2
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= '0';
suboneff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--invert here so that borrow can be added in simple expression
-- level 13
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= NOT((multonetwo(k) AND oddff(12)) OR (multonetwo(k+1) AND NOT(oddff(12))));
END LOOP;
-- level 14
suboneff <= ("11" & zerovec(34 DOWNTO 1)) +
('1' & multonetwoff(36 DOWNTO 2)) +
(zerovec(35 DOWNTO 1) & multonetwoff(1));
END IF;
END IF;
END PROCESS;
-- in level 14, out level 17 (36x18=37)
onethr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>18,widthcc=>37,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>suboneff,databb=>guessdel,
result=>multonethr);
-- mult by 2 - subone is about 1 (1.000 or 0.9999) so will effectively multiply by 0.5
guessonevec <= multonethr(36 DOWNTO 1);
--************************
--*** SECOND ITERATION ***
--************************
--X' = X/2(3-YXX)
deltwoone: fp_del
GENERIC MAP(width=>54,pipes=>11)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicanddelone,cc=>radicanddeltwo);
-- SII level in 17, level out 26+doublespeed
-- SIII/IV level in 17, level out 25
deltwotwo: fp_del
GENERIC MAP(width=>36,pipes=>(9+doublespeed-device*(1+doublespeed)))
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guessonevec,cc=>guessonevecdelone);
deltwothr: fp_del
GENERIC MAP (width=>36,pipes=>4)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guessonevecdelone,cc=>guessonevecdeltwo);
-- in level 17, out level 20 (36x36=54)
twoone: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>54,pipes=>3,
accuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessonevec,databb=>guessonevec,
result=>multtwoone);
-- in level 20,
-- SII out level 25/26 - 25+doublespeed
-- SIII/SIV out level 24
twotwo: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,pipes=>mullatency,
accuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multtwoone,databb=>radicanddeltwo,
result=>multtwotwo);
-- multtwotwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (55 DOWNTO 2), otherwise (56 DOWNTO 3)
-- round bit in position 1 or 2
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multtwotwoff(k) <= '0';
END LOOP;
finaladdsubff <= "0000";
FOR k IN 1 TO 55 LOOP
finaladdff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
-- SII in level 25+doublespeed, out level 26+doublespeed
-- SIII in level 24, out level 25
-- if multwotwo > 1, subtwo negative, subtract multwothr from guessonevec
-- if multwotwo <= 1, subtwo positive, add multwothr to guessonevec
FOR k IN 1 TO 36 LOOP
multtwotwoff(k) <= ((multtwotwo(k+6) AND oddff(25+doublespeed-device*(1+doublespeed))) OR
(multtwotwo(k+7) AND NOT(oddff(25+doublespeed-device*(1+doublespeed))))) XOR finaladdsub;
END LOOP;
finaladdsubff(1) <= finaladdsub;
FOR k IN 2 TO 4 LOOP
finaladdsubff(k) <= finaladdsubff(k-1);
END LOOP;
-- makes sure no overflow happens here, for example if less than 30 leading 1s/0s
-- in multtwotwoff
-- SII level in 29+doublespeed level out 30+doublespeed
-- SIII level in 28 level out 29
FOR k IN 1 TO 26 LOOP
finaladdff(k) <= multtwothr(k+10) XOR NOT(finaladdsubff(4));
END LOOP;
FOR k IN 27 TO 55 LOOP
finaladdff(k) <= NOT(finaladdsubff(4));
END LOOP;
END IF;
END IF;
END PROCESS;
-- doesnt have to be near msb
finaladdsub <= multtwotwo(60);
-- SII level in (26+doublespeed), level out (29+doublespeed)
-- SII level in 25, level out 28
twothr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multtwotwoff,databb=>guessonevecdelone,
result=>multtwothr);
finalguessvec <= guessonevecdeltwo & zerovec(17 DOWNTO 1);
-- SII level in 30+doublespeed, level out 31+2*doublespeed
-- SIII level in 29, level out 30+doublespeed
final: dp_fxadd
GENERIC MAP (width=>53,pipes=>doublespeed+1,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>finalguessvec,bb=>finaladdff(55 DOWNTO 3),carryin=>finaladdff(2),
cc=>invrootvec);
invroot <= invrootvec & '0';
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** CORE ***
--*** ***
--*** DP_INVSQR_CORE.VHD ***
--*** ***
--*** Function: 54 bit Inverse Square Root ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 24/04/09 - SIII/SIV multiplier support ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** SII Latency = 31 + 2*doublespeed ***
--*** SIII/IV Latency = 30 + doublespeed ***
--*** 1. Output is rounded already, LSB always 0 ***
--***************************************************
ENTITY dp_invsqr_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
odd : IN STD_LOGIC;
invroot : OUT STD_LOGIC_VECTOR (54 DOWNTO 1)
);
END dp_invsqr_core;
ARCHITECTURE rtl OF dp_invsqr_core IS
--SII mullatency = speed+5, SIII/IV mullatency = 4
constant mullatency : positive := doublespeed+5 - device*(1+doublespeed);
signal zerovec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal evennum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddnum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guessvec : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddff : STD_LOGIC_VECTOR (25+doublespeed DOWNTO 1);
signal scalenumff : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guess : STD_LOGIC_VECTOR (18 DOWNTO 1);
-- 1st iteration
signal radicanddelone : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal guessdel : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal multoneone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonetwo : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal multonetwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal suboneff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonethr : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal guessonevec : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- 2ns iteration
signal radicanddeltwo : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal guessonevecdelone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal guessonevecdeltwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multtwoone : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal multtwotwo : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multtwotwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal finaladdsub : STD_LOGIC;
signal finaladdsubff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal finaladdff : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal multtwothr : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal finalguessvec : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal invrootvec : STD_LOGIC_VECTOR (53 DOWNTO 1);
component fp_invsqr_est IS
GENERIC (synthesize : integer := 0); -- 0 = behavioral, 1 = syntheziable
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invroot : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
end component;
component dp_fxadd IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
oddnum <= conv_std_logic_vector(185363,18); -- mult by 2^-.5 (odd exp)
evennum <= conv_std_logic_vector(262143,18); -- mult by 1 (even exp)
gza: FOR k IN 1 TO 54 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- in level 0, out level 5
look: fp_invsqr_est
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radicand=>radicand(54 DOWNTO 36),invroot=>guessvec);
pta: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 25+doublespeed LOOP
oddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
oddff(1) <= odd;
FOR k IN 2 TO 25+doublespeed LOOP
oddff(k) <= oddff(k-1);
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= (oddnum(k) AND oddff(4)) OR (evennum(k) AND NOT(oddff(4)));
END LOOP;
END IF;
END IF;
END PROCESS;
-- in level 5, out level 7
mulscale: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>18,pipes=>2,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessvec,databb=>scalenumff,
result=>guess);
--*********************
--*** ITERATION ONE ***
--*********************
--X' = X/2(3-YXX)
deloneone: fp_del
GENERIC MAP(width=>54,pipes=>9)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicand,cc=>radicanddelone);
delonetwo: fp_del
GENERIC MAP(width=>18,pipes=>7)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guess,cc=>guessdel);
-- in level 7, out level 9 (18x18=36)
oneone: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36,pipes=>2,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guess,databb=>guess,
result=>multoneone);
-- in level 9, out level 12 (36x36=37)
onetwo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>37,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>radicanddelone(54 DOWNTO 19),databb=>multoneone,
result=>multonetwo);
-- multonetwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (37 DOWNTO 2), otherwise (38 DOWNTO 3)
-- round bit in position 1 or 2
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= '0';
suboneff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--invert here so that borrow can be added in simple expression
-- level 13
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= NOT((multonetwo(k) AND oddff(12)) OR (multonetwo(k+1) AND NOT(oddff(12))));
END LOOP;
-- level 14
suboneff <= ("11" & zerovec(34 DOWNTO 1)) +
('1' & multonetwoff(36 DOWNTO 2)) +
(zerovec(35 DOWNTO 1) & multonetwoff(1));
END IF;
END IF;
END PROCESS;
-- in level 14, out level 17 (36x18=37)
onethr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>18,widthcc=>37,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>suboneff,databb=>guessdel,
result=>multonethr);
-- mult by 2 - subone is about 1 (1.000 or 0.9999) so will effectively multiply by 0.5
guessonevec <= multonethr(36 DOWNTO 1);
--************************
--*** SECOND ITERATION ***
--************************
--X' = X/2(3-YXX)
deltwoone: fp_del
GENERIC MAP(width=>54,pipes=>11)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicanddelone,cc=>radicanddeltwo);
-- SII level in 17, level out 26+doublespeed
-- SIII/IV level in 17, level out 25
deltwotwo: fp_del
GENERIC MAP(width=>36,pipes=>(9+doublespeed-device*(1+doublespeed)))
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guessonevec,cc=>guessonevecdelone);
deltwothr: fp_del
GENERIC MAP (width=>36,pipes=>4)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guessonevecdelone,cc=>guessonevecdeltwo);
-- in level 17, out level 20 (36x36=54)
twoone: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>54,pipes=>3,
accuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessonevec,databb=>guessonevec,
result=>multtwoone);
-- in level 20,
-- SII out level 25/26 - 25+doublespeed
-- SIII/SIV out level 24
twotwo: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,pipes=>mullatency,
accuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multtwoone,databb=>radicanddeltwo,
result=>multtwotwo);
-- multtwotwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (55 DOWNTO 2), otherwise (56 DOWNTO 3)
-- round bit in position 1 or 2
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multtwotwoff(k) <= '0';
END LOOP;
finaladdsubff <= "0000";
FOR k IN 1 TO 55 LOOP
finaladdff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
-- SII in level 25+doublespeed, out level 26+doublespeed
-- SIII in level 24, out level 25
-- if multwotwo > 1, subtwo negative, subtract multwothr from guessonevec
-- if multwotwo <= 1, subtwo positive, add multwothr to guessonevec
FOR k IN 1 TO 36 LOOP
multtwotwoff(k) <= ((multtwotwo(k+6) AND oddff(25+doublespeed-device*(1+doublespeed))) OR
(multtwotwo(k+7) AND NOT(oddff(25+doublespeed-device*(1+doublespeed))))) XOR finaladdsub;
END LOOP;
finaladdsubff(1) <= finaladdsub;
FOR k IN 2 TO 4 LOOP
finaladdsubff(k) <= finaladdsubff(k-1);
END LOOP;
-- makes sure no overflow happens here, for example if less than 30 leading 1s/0s
-- in multtwotwoff
-- SII level in 29+doublespeed level out 30+doublespeed
-- SIII level in 28 level out 29
FOR k IN 1 TO 26 LOOP
finaladdff(k) <= multtwothr(k+10) XOR NOT(finaladdsubff(4));
END LOOP;
FOR k IN 27 TO 55 LOOP
finaladdff(k) <= NOT(finaladdsubff(4));
END LOOP;
END IF;
END IF;
END PROCESS;
-- doesnt have to be near msb
finaladdsub <= multtwotwo(60);
-- SII level in (26+doublespeed), level out (29+doublespeed)
-- SII level in 25, level out 28
twothr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multtwotwoff,databb=>guessonevecdelone,
result=>multtwothr);
finalguessvec <= guessonevecdeltwo & zerovec(17 DOWNTO 1);
-- SII level in 30+doublespeed, level out 31+2*doublespeed
-- SIII level in 29, level out 30+doublespeed
final: dp_fxadd
GENERIC MAP (width=>53,pipes=>doublespeed+1,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>finalguessvec,bb=>finaladdff(55 DOWNTO 3),carryin=>finaladdff(2),
cc=>invrootvec);
invroot <= invrootvec & '0';
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** CORE ***
--*** ***
--*** DP_INVSQR_CORE.VHD ***
--*** ***
--*** Function: 54 bit Inverse Square Root ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 24/04/09 - SIII/SIV multiplier support ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** SII Latency = 31 + 2*doublespeed ***
--*** SIII/IV Latency = 30 + doublespeed ***
--*** 1. Output is rounded already, LSB always 0 ***
--***************************************************
ENTITY dp_invsqr_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
odd : IN STD_LOGIC;
invroot : OUT STD_LOGIC_VECTOR (54 DOWNTO 1)
);
END dp_invsqr_core;
ARCHITECTURE rtl OF dp_invsqr_core IS
--SII mullatency = speed+5, SIII/IV mullatency = 4
constant mullatency : positive := doublespeed+5 - device*(1+doublespeed);
signal zerovec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal evennum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddnum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guessvec : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddff : STD_LOGIC_VECTOR (25+doublespeed DOWNTO 1);
signal scalenumff : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guess : STD_LOGIC_VECTOR (18 DOWNTO 1);
-- 1st iteration
signal radicanddelone : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal guessdel : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal multoneone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonetwo : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal multonetwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal suboneff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonethr : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal guessonevec : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- 2ns iteration
signal radicanddeltwo : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal guessonevecdelone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal guessonevecdeltwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multtwoone : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal multtwotwo : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multtwotwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal finaladdsub : STD_LOGIC;
signal finaladdsubff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal finaladdff : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal multtwothr : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal finalguessvec : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal invrootvec : STD_LOGIC_VECTOR (53 DOWNTO 1);
component fp_invsqr_est IS
GENERIC (synthesize : integer := 0); -- 0 = behavioral, 1 = syntheziable
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invroot : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
end component;
component dp_fxadd IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
oddnum <= conv_std_logic_vector(185363,18); -- mult by 2^-.5 (odd exp)
evennum <= conv_std_logic_vector(262143,18); -- mult by 1 (even exp)
gza: FOR k IN 1 TO 54 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- in level 0, out level 5
look: fp_invsqr_est
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radicand=>radicand(54 DOWNTO 36),invroot=>guessvec);
pta: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 25+doublespeed LOOP
oddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
oddff(1) <= odd;
FOR k IN 2 TO 25+doublespeed LOOP
oddff(k) <= oddff(k-1);
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= (oddnum(k) AND oddff(4)) OR (evennum(k) AND NOT(oddff(4)));
END LOOP;
END IF;
END IF;
END PROCESS;
-- in level 5, out level 7
mulscale: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>18,pipes=>2,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessvec,databb=>scalenumff,
result=>guess);
--*********************
--*** ITERATION ONE ***
--*********************
--X' = X/2(3-YXX)
deloneone: fp_del
GENERIC MAP(width=>54,pipes=>9)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicand,cc=>radicanddelone);
delonetwo: fp_del
GENERIC MAP(width=>18,pipes=>7)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guess,cc=>guessdel);
-- in level 7, out level 9 (18x18=36)
oneone: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36,pipes=>2,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guess,databb=>guess,
result=>multoneone);
-- in level 9, out level 12 (36x36=37)
onetwo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>37,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>radicanddelone(54 DOWNTO 19),databb=>multoneone,
result=>multonetwo);
-- multonetwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (37 DOWNTO 2), otherwise (38 DOWNTO 3)
-- round bit in position 1 or 2
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= '0';
suboneff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--invert here so that borrow can be added in simple expression
-- level 13
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= NOT((multonetwo(k) AND oddff(12)) OR (multonetwo(k+1) AND NOT(oddff(12))));
END LOOP;
-- level 14
suboneff <= ("11" & zerovec(34 DOWNTO 1)) +
('1' & multonetwoff(36 DOWNTO 2)) +
(zerovec(35 DOWNTO 1) & multonetwoff(1));
END IF;
END IF;
END PROCESS;
-- in level 14, out level 17 (36x18=37)
onethr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>18,widthcc=>37,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>suboneff,databb=>guessdel,
result=>multonethr);
-- mult by 2 - subone is about 1 (1.000 or 0.9999) so will effectively multiply by 0.5
guessonevec <= multonethr(36 DOWNTO 1);
--************************
--*** SECOND ITERATION ***
--************************
--X' = X/2(3-YXX)
deltwoone: fp_del
GENERIC MAP(width=>54,pipes=>11)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicanddelone,cc=>radicanddeltwo);
-- SII level in 17, level out 26+doublespeed
-- SIII/IV level in 17, level out 25
deltwotwo: fp_del
GENERIC MAP(width=>36,pipes=>(9+doublespeed-device*(1+doublespeed)))
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guessonevec,cc=>guessonevecdelone);
deltwothr: fp_del
GENERIC MAP (width=>36,pipes=>4)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guessonevecdelone,cc=>guessonevecdeltwo);
-- in level 17, out level 20 (36x36=54)
twoone: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>54,pipes=>3,
accuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessonevec,databb=>guessonevec,
result=>multtwoone);
-- in level 20,
-- SII out level 25/26 - 25+doublespeed
-- SIII/SIV out level 24
twotwo: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,pipes=>mullatency,
accuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multtwoone,databb=>radicanddeltwo,
result=>multtwotwo);
-- multtwotwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (55 DOWNTO 2), otherwise (56 DOWNTO 3)
-- round bit in position 1 or 2
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multtwotwoff(k) <= '0';
END LOOP;
finaladdsubff <= "0000";
FOR k IN 1 TO 55 LOOP
finaladdff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
-- SII in level 25+doublespeed, out level 26+doublespeed
-- SIII in level 24, out level 25
-- if multwotwo > 1, subtwo negative, subtract multwothr from guessonevec
-- if multwotwo <= 1, subtwo positive, add multwothr to guessonevec
FOR k IN 1 TO 36 LOOP
multtwotwoff(k) <= ((multtwotwo(k+6) AND oddff(25+doublespeed-device*(1+doublespeed))) OR
(multtwotwo(k+7) AND NOT(oddff(25+doublespeed-device*(1+doublespeed))))) XOR finaladdsub;
END LOOP;
finaladdsubff(1) <= finaladdsub;
FOR k IN 2 TO 4 LOOP
finaladdsubff(k) <= finaladdsubff(k-1);
END LOOP;
-- makes sure no overflow happens here, for example if less than 30 leading 1s/0s
-- in multtwotwoff
-- SII level in 29+doublespeed level out 30+doublespeed
-- SIII level in 28 level out 29
FOR k IN 1 TO 26 LOOP
finaladdff(k) <= multtwothr(k+10) XOR NOT(finaladdsubff(4));
END LOOP;
FOR k IN 27 TO 55 LOOP
finaladdff(k) <= NOT(finaladdsubff(4));
END LOOP;
END IF;
END IF;
END PROCESS;
-- doesnt have to be near msb
finaladdsub <= multtwotwo(60);
-- SII level in (26+doublespeed), level out (29+doublespeed)
-- SII level in 25, level out 28
twothr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multtwotwoff,databb=>guessonevecdelone,
result=>multtwothr);
finalguessvec <= guessonevecdeltwo & zerovec(17 DOWNTO 1);
-- SII level in 30+doublespeed, level out 31+2*doublespeed
-- SIII level in 29, level out 30+doublespeed
final: dp_fxadd
GENERIC MAP (width=>53,pipes=>doublespeed+1,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>finalguessvec,bb=>finaladdff(55 DOWNTO 3),carryin=>finaladdff(2),
cc=>invrootvec);
invroot <= invrootvec & '0';
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** CORE ***
--*** ***
--*** DP_INVSQR_CORE.VHD ***
--*** ***
--*** Function: 54 bit Inverse Square Root ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 24/04/09 - SIII/SIV multiplier support ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** SII Latency = 31 + 2*doublespeed ***
--*** SIII/IV Latency = 30 + doublespeed ***
--*** 1. Output is rounded already, LSB always 0 ***
--***************************************************
ENTITY dp_invsqr_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
odd : IN STD_LOGIC;
invroot : OUT STD_LOGIC_VECTOR (54 DOWNTO 1)
);
END dp_invsqr_core;
ARCHITECTURE rtl OF dp_invsqr_core IS
--SII mullatency = speed+5, SIII/IV mullatency = 4
constant mullatency : positive := doublespeed+5 - device*(1+doublespeed);
signal zerovec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal evennum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddnum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guessvec : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddff : STD_LOGIC_VECTOR (25+doublespeed DOWNTO 1);
signal scalenumff : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guess : STD_LOGIC_VECTOR (18 DOWNTO 1);
-- 1st iteration
signal radicanddelone : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal guessdel : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal multoneone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonetwo : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal multonetwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal suboneff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonethr : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal guessonevec : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- 2ns iteration
signal radicanddeltwo : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal guessonevecdelone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal guessonevecdeltwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multtwoone : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal multtwotwo : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multtwotwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal finaladdsub : STD_LOGIC;
signal finaladdsubff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal finaladdff : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal multtwothr : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal finalguessvec : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal invrootvec : STD_LOGIC_VECTOR (53 DOWNTO 1);
component fp_invsqr_est IS
GENERIC (synthesize : integer := 0); -- 0 = behavioral, 1 = syntheziable
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invroot : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
end component;
component dp_fxadd IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
oddnum <= conv_std_logic_vector(185363,18); -- mult by 2^-.5 (odd exp)
evennum <= conv_std_logic_vector(262143,18); -- mult by 1 (even exp)
gza: FOR k IN 1 TO 54 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- in level 0, out level 5
look: fp_invsqr_est
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radicand=>radicand(54 DOWNTO 36),invroot=>guessvec);
pta: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 25+doublespeed LOOP
oddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
oddff(1) <= odd;
FOR k IN 2 TO 25+doublespeed LOOP
oddff(k) <= oddff(k-1);
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= (oddnum(k) AND oddff(4)) OR (evennum(k) AND NOT(oddff(4)));
END LOOP;
END IF;
END IF;
END PROCESS;
-- in level 5, out level 7
mulscale: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>18,pipes=>2,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessvec,databb=>scalenumff,
result=>guess);
--*********************
--*** ITERATION ONE ***
--*********************
--X' = X/2(3-YXX)
deloneone: fp_del
GENERIC MAP(width=>54,pipes=>9)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicand,cc=>radicanddelone);
delonetwo: fp_del
GENERIC MAP(width=>18,pipes=>7)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guess,cc=>guessdel);
-- in level 7, out level 9 (18x18=36)
oneone: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36,pipes=>2,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guess,databb=>guess,
result=>multoneone);
-- in level 9, out level 12 (36x36=37)
onetwo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>37,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>radicanddelone(54 DOWNTO 19),databb=>multoneone,
result=>multonetwo);
-- multonetwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (37 DOWNTO 2), otherwise (38 DOWNTO 3)
-- round bit in position 1 or 2
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= '0';
suboneff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--invert here so that borrow can be added in simple expression
-- level 13
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= NOT((multonetwo(k) AND oddff(12)) OR (multonetwo(k+1) AND NOT(oddff(12))));
END LOOP;
-- level 14
suboneff <= ("11" & zerovec(34 DOWNTO 1)) +
('1' & multonetwoff(36 DOWNTO 2)) +
(zerovec(35 DOWNTO 1) & multonetwoff(1));
END IF;
END IF;
END PROCESS;
-- in level 14, out level 17 (36x18=37)
onethr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>18,widthcc=>37,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>suboneff,databb=>guessdel,
result=>multonethr);
-- mult by 2 - subone is about 1 (1.000 or 0.9999) so will effectively multiply by 0.5
guessonevec <= multonethr(36 DOWNTO 1);
--************************
--*** SECOND ITERATION ***
--************************
--X' = X/2(3-YXX)
deltwoone: fp_del
GENERIC MAP(width=>54,pipes=>11)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicanddelone,cc=>radicanddeltwo);
-- SII level in 17, level out 26+doublespeed
-- SIII/IV level in 17, level out 25
deltwotwo: fp_del
GENERIC MAP(width=>36,pipes=>(9+doublespeed-device*(1+doublespeed)))
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guessonevec,cc=>guessonevecdelone);
deltwothr: fp_del
GENERIC MAP (width=>36,pipes=>4)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guessonevecdelone,cc=>guessonevecdeltwo);
-- in level 17, out level 20 (36x36=54)
twoone: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>54,pipes=>3,
accuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessonevec,databb=>guessonevec,
result=>multtwoone);
-- in level 20,
-- SII out level 25/26 - 25+doublespeed
-- SIII/SIV out level 24
twotwo: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,pipes=>mullatency,
accuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multtwoone,databb=>radicanddeltwo,
result=>multtwotwo);
-- multtwotwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (55 DOWNTO 2), otherwise (56 DOWNTO 3)
-- round bit in position 1 or 2
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multtwotwoff(k) <= '0';
END LOOP;
finaladdsubff <= "0000";
FOR k IN 1 TO 55 LOOP
finaladdff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
-- SII in level 25+doublespeed, out level 26+doublespeed
-- SIII in level 24, out level 25
-- if multwotwo > 1, subtwo negative, subtract multwothr from guessonevec
-- if multwotwo <= 1, subtwo positive, add multwothr to guessonevec
FOR k IN 1 TO 36 LOOP
multtwotwoff(k) <= ((multtwotwo(k+6) AND oddff(25+doublespeed-device*(1+doublespeed))) OR
(multtwotwo(k+7) AND NOT(oddff(25+doublespeed-device*(1+doublespeed))))) XOR finaladdsub;
END LOOP;
finaladdsubff(1) <= finaladdsub;
FOR k IN 2 TO 4 LOOP
finaladdsubff(k) <= finaladdsubff(k-1);
END LOOP;
-- makes sure no overflow happens here, for example if less than 30 leading 1s/0s
-- in multtwotwoff
-- SII level in 29+doublespeed level out 30+doublespeed
-- SIII level in 28 level out 29
FOR k IN 1 TO 26 LOOP
finaladdff(k) <= multtwothr(k+10) XOR NOT(finaladdsubff(4));
END LOOP;
FOR k IN 27 TO 55 LOOP
finaladdff(k) <= NOT(finaladdsubff(4));
END LOOP;
END IF;
END IF;
END PROCESS;
-- doesnt have to be near msb
finaladdsub <= multtwotwo(60);
-- SII level in (26+doublespeed), level out (29+doublespeed)
-- SII level in 25, level out 28
twothr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multtwotwoff,databb=>guessonevecdelone,
result=>multtwothr);
finalguessvec <= guessonevecdeltwo & zerovec(17 DOWNTO 1);
-- SII level in 30+doublespeed, level out 31+2*doublespeed
-- SIII level in 29, level out 30+doublespeed
final: dp_fxadd
GENERIC MAP (width=>53,pipes=>doublespeed+1,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>finalguessvec,bb=>finaladdff(55 DOWNTO 3),carryin=>finaladdff(2),
cc=>invrootvec);
invroot <= invrootvec & '0';
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** CORE ***
--*** ***
--*** DP_INVSQR_CORE.VHD ***
--*** ***
--*** Function: 54 bit Inverse Square Root ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 24/04/09 - SIII/SIV multiplier support ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** SII Latency = 31 + 2*doublespeed ***
--*** SIII/IV Latency = 30 + doublespeed ***
--*** 1. Output is rounded already, LSB always 0 ***
--***************************************************
ENTITY dp_invsqr_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
odd : IN STD_LOGIC;
invroot : OUT STD_LOGIC_VECTOR (54 DOWNTO 1)
);
END dp_invsqr_core;
ARCHITECTURE rtl OF dp_invsqr_core IS
--SII mullatency = speed+5, SIII/IV mullatency = 4
constant mullatency : positive := doublespeed+5 - device*(1+doublespeed);
signal zerovec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal evennum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddnum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guessvec : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddff : STD_LOGIC_VECTOR (25+doublespeed DOWNTO 1);
signal scalenumff : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guess : STD_LOGIC_VECTOR (18 DOWNTO 1);
-- 1st iteration
signal radicanddelone : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal guessdel : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal multoneone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonetwo : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal multonetwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal suboneff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonethr : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal guessonevec : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- 2ns iteration
signal radicanddeltwo : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal guessonevecdelone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal guessonevecdeltwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multtwoone : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal multtwotwo : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multtwotwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal finaladdsub : STD_LOGIC;
signal finaladdsubff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal finaladdff : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal multtwothr : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal finalguessvec : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal invrootvec : STD_LOGIC_VECTOR (53 DOWNTO 1);
component fp_invsqr_est IS
GENERIC (synthesize : integer := 0); -- 0 = behavioral, 1 = syntheziable
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invroot : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
end component;
component dp_fxadd IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
oddnum <= conv_std_logic_vector(185363,18); -- mult by 2^-.5 (odd exp)
evennum <= conv_std_logic_vector(262143,18); -- mult by 1 (even exp)
gza: FOR k IN 1 TO 54 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- in level 0, out level 5
look: fp_invsqr_est
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radicand=>radicand(54 DOWNTO 36),invroot=>guessvec);
pta: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 25+doublespeed LOOP
oddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
oddff(1) <= odd;
FOR k IN 2 TO 25+doublespeed LOOP
oddff(k) <= oddff(k-1);
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= (oddnum(k) AND oddff(4)) OR (evennum(k) AND NOT(oddff(4)));
END LOOP;
END IF;
END IF;
END PROCESS;
-- in level 5, out level 7
mulscale: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>18,pipes=>2,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessvec,databb=>scalenumff,
result=>guess);
--*********************
--*** ITERATION ONE ***
--*********************
--X' = X/2(3-YXX)
deloneone: fp_del
GENERIC MAP(width=>54,pipes=>9)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicand,cc=>radicanddelone);
delonetwo: fp_del
GENERIC MAP(width=>18,pipes=>7)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guess,cc=>guessdel);
-- in level 7, out level 9 (18x18=36)
oneone: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36,pipes=>2,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guess,databb=>guess,
result=>multoneone);
-- in level 9, out level 12 (36x36=37)
onetwo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>37,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>radicanddelone(54 DOWNTO 19),databb=>multoneone,
result=>multonetwo);
-- multonetwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (37 DOWNTO 2), otherwise (38 DOWNTO 3)
-- round bit in position 1 or 2
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= '0';
suboneff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--invert here so that borrow can be added in simple expression
-- level 13
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= NOT((multonetwo(k) AND oddff(12)) OR (multonetwo(k+1) AND NOT(oddff(12))));
END LOOP;
-- level 14
suboneff <= ("11" & zerovec(34 DOWNTO 1)) +
('1' & multonetwoff(36 DOWNTO 2)) +
(zerovec(35 DOWNTO 1) & multonetwoff(1));
END IF;
END IF;
END PROCESS;
-- in level 14, out level 17 (36x18=37)
onethr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>18,widthcc=>37,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>suboneff,databb=>guessdel,
result=>multonethr);
-- mult by 2 - subone is about 1 (1.000 or 0.9999) so will effectively multiply by 0.5
guessonevec <= multonethr(36 DOWNTO 1);
--************************
--*** SECOND ITERATION ***
--************************
--X' = X/2(3-YXX)
deltwoone: fp_del
GENERIC MAP(width=>54,pipes=>11)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicanddelone,cc=>radicanddeltwo);
-- SII level in 17, level out 26+doublespeed
-- SIII/IV level in 17, level out 25
deltwotwo: fp_del
GENERIC MAP(width=>36,pipes=>(9+doublespeed-device*(1+doublespeed)))
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guessonevec,cc=>guessonevecdelone);
deltwothr: fp_del
GENERIC MAP (width=>36,pipes=>4)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guessonevecdelone,cc=>guessonevecdeltwo);
-- in level 17, out level 20 (36x36=54)
twoone: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>54,pipes=>3,
accuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessonevec,databb=>guessonevec,
result=>multtwoone);
-- in level 20,
-- SII out level 25/26 - 25+doublespeed
-- SIII/SIV out level 24
twotwo: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,pipes=>mullatency,
accuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multtwoone,databb=>radicanddeltwo,
result=>multtwotwo);
-- multtwotwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (55 DOWNTO 2), otherwise (56 DOWNTO 3)
-- round bit in position 1 or 2
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multtwotwoff(k) <= '0';
END LOOP;
finaladdsubff <= "0000";
FOR k IN 1 TO 55 LOOP
finaladdff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
-- SII in level 25+doublespeed, out level 26+doublespeed
-- SIII in level 24, out level 25
-- if multwotwo > 1, subtwo negative, subtract multwothr from guessonevec
-- if multwotwo <= 1, subtwo positive, add multwothr to guessonevec
FOR k IN 1 TO 36 LOOP
multtwotwoff(k) <= ((multtwotwo(k+6) AND oddff(25+doublespeed-device*(1+doublespeed))) OR
(multtwotwo(k+7) AND NOT(oddff(25+doublespeed-device*(1+doublespeed))))) XOR finaladdsub;
END LOOP;
finaladdsubff(1) <= finaladdsub;
FOR k IN 2 TO 4 LOOP
finaladdsubff(k) <= finaladdsubff(k-1);
END LOOP;
-- makes sure no overflow happens here, for example if less than 30 leading 1s/0s
-- in multtwotwoff
-- SII level in 29+doublespeed level out 30+doublespeed
-- SIII level in 28 level out 29
FOR k IN 1 TO 26 LOOP
finaladdff(k) <= multtwothr(k+10) XOR NOT(finaladdsubff(4));
END LOOP;
FOR k IN 27 TO 55 LOOP
finaladdff(k) <= NOT(finaladdsubff(4));
END LOOP;
END IF;
END IF;
END PROCESS;
-- doesnt have to be near msb
finaladdsub <= multtwotwo(60);
-- SII level in (26+doublespeed), level out (29+doublespeed)
-- SII level in 25, level out 28
twothr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multtwotwoff,databb=>guessonevecdelone,
result=>multtwothr);
finalguessvec <= guessonevecdeltwo & zerovec(17 DOWNTO 1);
-- SII level in 30+doublespeed, level out 31+2*doublespeed
-- SIII level in 29, level out 30+doublespeed
final: dp_fxadd
GENERIC MAP (width=>53,pipes=>doublespeed+1,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>finalguessvec,bb=>finaladdff(55 DOWNTO 3),carryin=>finaladdff(2),
cc=>invrootvec);
invroot <= invrootvec & '0';
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** CORE ***
--*** ***
--*** DP_INVSQR_CORE.VHD ***
--*** ***
--*** Function: 54 bit Inverse Square Root ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 24/04/09 - SIII/SIV multiplier support ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** SII Latency = 31 + 2*doublespeed ***
--*** SIII/IV Latency = 30 + doublespeed ***
--*** 1. Output is rounded already, LSB always 0 ***
--***************************************************
ENTITY dp_invsqr_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
odd : IN STD_LOGIC;
invroot : OUT STD_LOGIC_VECTOR (54 DOWNTO 1)
);
END dp_invsqr_core;
ARCHITECTURE rtl OF dp_invsqr_core IS
--SII mullatency = speed+5, SIII/IV mullatency = 4
constant mullatency : positive := doublespeed+5 - device*(1+doublespeed);
signal zerovec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal evennum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddnum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guessvec : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddff : STD_LOGIC_VECTOR (25+doublespeed DOWNTO 1);
signal scalenumff : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guess : STD_LOGIC_VECTOR (18 DOWNTO 1);
-- 1st iteration
signal radicanddelone : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal guessdel : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal multoneone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonetwo : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal multonetwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal suboneff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonethr : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal guessonevec : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- 2ns iteration
signal radicanddeltwo : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal guessonevecdelone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal guessonevecdeltwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multtwoone : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal multtwotwo : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multtwotwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal finaladdsub : STD_LOGIC;
signal finaladdsubff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal finaladdff : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal multtwothr : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal finalguessvec : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal invrootvec : STD_LOGIC_VECTOR (53 DOWNTO 1);
component fp_invsqr_est IS
GENERIC (synthesize : integer := 0); -- 0 = behavioral, 1 = syntheziable
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invroot : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
end component;
component dp_fxadd IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
oddnum <= conv_std_logic_vector(185363,18); -- mult by 2^-.5 (odd exp)
evennum <= conv_std_logic_vector(262143,18); -- mult by 1 (even exp)
gza: FOR k IN 1 TO 54 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- in level 0, out level 5
look: fp_invsqr_est
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radicand=>radicand(54 DOWNTO 36),invroot=>guessvec);
pta: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 25+doublespeed LOOP
oddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
oddff(1) <= odd;
FOR k IN 2 TO 25+doublespeed LOOP
oddff(k) <= oddff(k-1);
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= (oddnum(k) AND oddff(4)) OR (evennum(k) AND NOT(oddff(4)));
END LOOP;
END IF;
END IF;
END PROCESS;
-- in level 5, out level 7
mulscale: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>18,pipes=>2,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessvec,databb=>scalenumff,
result=>guess);
--*********************
--*** ITERATION ONE ***
--*********************
--X' = X/2(3-YXX)
deloneone: fp_del
GENERIC MAP(width=>54,pipes=>9)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicand,cc=>radicanddelone);
delonetwo: fp_del
GENERIC MAP(width=>18,pipes=>7)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guess,cc=>guessdel);
-- in level 7, out level 9 (18x18=36)
oneone: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36,pipes=>2,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guess,databb=>guess,
result=>multoneone);
-- in level 9, out level 12 (36x36=37)
onetwo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>37,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>radicanddelone(54 DOWNTO 19),databb=>multoneone,
result=>multonetwo);
-- multonetwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (37 DOWNTO 2), otherwise (38 DOWNTO 3)
-- round bit in position 1 or 2
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= '0';
suboneff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--invert here so that borrow can be added in simple expression
-- level 13
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= NOT((multonetwo(k) AND oddff(12)) OR (multonetwo(k+1) AND NOT(oddff(12))));
END LOOP;
-- level 14
suboneff <= ("11" & zerovec(34 DOWNTO 1)) +
('1' & multonetwoff(36 DOWNTO 2)) +
(zerovec(35 DOWNTO 1) & multonetwoff(1));
END IF;
END IF;
END PROCESS;
-- in level 14, out level 17 (36x18=37)
onethr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>18,widthcc=>37,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>suboneff,databb=>guessdel,
result=>multonethr);
-- mult by 2 - subone is about 1 (1.000 or 0.9999) so will effectively multiply by 0.5
guessonevec <= multonethr(36 DOWNTO 1);
--************************
--*** SECOND ITERATION ***
--************************
--X' = X/2(3-YXX)
deltwoone: fp_del
GENERIC MAP(width=>54,pipes=>11)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicanddelone,cc=>radicanddeltwo);
-- SII level in 17, level out 26+doublespeed
-- SIII/IV level in 17, level out 25
deltwotwo: fp_del
GENERIC MAP(width=>36,pipes=>(9+doublespeed-device*(1+doublespeed)))
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guessonevec,cc=>guessonevecdelone);
deltwothr: fp_del
GENERIC MAP (width=>36,pipes=>4)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guessonevecdelone,cc=>guessonevecdeltwo);
-- in level 17, out level 20 (36x36=54)
twoone: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>54,pipes=>3,
accuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessonevec,databb=>guessonevec,
result=>multtwoone);
-- in level 20,
-- SII out level 25/26 - 25+doublespeed
-- SIII/SIV out level 24
twotwo: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,pipes=>mullatency,
accuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multtwoone,databb=>radicanddeltwo,
result=>multtwotwo);
-- multtwotwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (55 DOWNTO 2), otherwise (56 DOWNTO 3)
-- round bit in position 1 or 2
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multtwotwoff(k) <= '0';
END LOOP;
finaladdsubff <= "0000";
FOR k IN 1 TO 55 LOOP
finaladdff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
-- SII in level 25+doublespeed, out level 26+doublespeed
-- SIII in level 24, out level 25
-- if multwotwo > 1, subtwo negative, subtract multwothr from guessonevec
-- if multwotwo <= 1, subtwo positive, add multwothr to guessonevec
FOR k IN 1 TO 36 LOOP
multtwotwoff(k) <= ((multtwotwo(k+6) AND oddff(25+doublespeed-device*(1+doublespeed))) OR
(multtwotwo(k+7) AND NOT(oddff(25+doublespeed-device*(1+doublespeed))))) XOR finaladdsub;
END LOOP;
finaladdsubff(1) <= finaladdsub;
FOR k IN 2 TO 4 LOOP
finaladdsubff(k) <= finaladdsubff(k-1);
END LOOP;
-- makes sure no overflow happens here, for example if less than 30 leading 1s/0s
-- in multtwotwoff
-- SII level in 29+doublespeed level out 30+doublespeed
-- SIII level in 28 level out 29
FOR k IN 1 TO 26 LOOP
finaladdff(k) <= multtwothr(k+10) XOR NOT(finaladdsubff(4));
END LOOP;
FOR k IN 27 TO 55 LOOP
finaladdff(k) <= NOT(finaladdsubff(4));
END LOOP;
END IF;
END IF;
END PROCESS;
-- doesnt have to be near msb
finaladdsub <= multtwotwo(60);
-- SII level in (26+doublespeed), level out (29+doublespeed)
-- SII level in 25, level out 28
twothr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multtwotwoff,databb=>guessonevecdelone,
result=>multtwothr);
finalguessvec <= guessonevecdeltwo & zerovec(17 DOWNTO 1);
-- SII level in 30+doublespeed, level out 31+2*doublespeed
-- SIII level in 29, level out 30+doublespeed
final: dp_fxadd
GENERIC MAP (width=>53,pipes=>doublespeed+1,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>finalguessvec,bb=>finaladdff(55 DOWNTO 3),carryin=>finaladdff(2),
cc=>invrootvec);
invroot <= invrootvec & '0';
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** CORE ***
--*** ***
--*** DP_INVSQR_CORE.VHD ***
--*** ***
--*** Function: 54 bit Inverse Square Root ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 24/04/09 - SIII/SIV multiplier support ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** SII Latency = 31 + 2*doublespeed ***
--*** SIII/IV Latency = 30 + doublespeed ***
--*** 1. Output is rounded already, LSB always 0 ***
--***************************************************
ENTITY dp_invsqr_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
odd : IN STD_LOGIC;
invroot : OUT STD_LOGIC_VECTOR (54 DOWNTO 1)
);
END dp_invsqr_core;
ARCHITECTURE rtl OF dp_invsqr_core IS
--SII mullatency = speed+5, SIII/IV mullatency = 4
constant mullatency : positive := doublespeed+5 - device*(1+doublespeed);
signal zerovec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal evennum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddnum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guessvec : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddff : STD_LOGIC_VECTOR (25+doublespeed DOWNTO 1);
signal scalenumff : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guess : STD_LOGIC_VECTOR (18 DOWNTO 1);
-- 1st iteration
signal radicanddelone : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal guessdel : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal multoneone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonetwo : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal multonetwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal suboneff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonethr : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal guessonevec : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- 2ns iteration
signal radicanddeltwo : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal guessonevecdelone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal guessonevecdeltwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multtwoone : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal multtwotwo : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multtwotwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal finaladdsub : STD_LOGIC;
signal finaladdsubff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal finaladdff : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal multtwothr : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal finalguessvec : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal invrootvec : STD_LOGIC_VECTOR (53 DOWNTO 1);
component fp_invsqr_est IS
GENERIC (synthesize : integer := 0); -- 0 = behavioral, 1 = syntheziable
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invroot : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
end component;
component dp_fxadd IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
oddnum <= conv_std_logic_vector(185363,18); -- mult by 2^-.5 (odd exp)
evennum <= conv_std_logic_vector(262143,18); -- mult by 1 (even exp)
gza: FOR k IN 1 TO 54 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- in level 0, out level 5
look: fp_invsqr_est
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radicand=>radicand(54 DOWNTO 36),invroot=>guessvec);
pta: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 25+doublespeed LOOP
oddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
oddff(1) <= odd;
FOR k IN 2 TO 25+doublespeed LOOP
oddff(k) <= oddff(k-1);
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= (oddnum(k) AND oddff(4)) OR (evennum(k) AND NOT(oddff(4)));
END LOOP;
END IF;
END IF;
END PROCESS;
-- in level 5, out level 7
mulscale: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>18,pipes=>2,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessvec,databb=>scalenumff,
result=>guess);
--*********************
--*** ITERATION ONE ***
--*********************
--X' = X/2(3-YXX)
deloneone: fp_del
GENERIC MAP(width=>54,pipes=>9)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicand,cc=>radicanddelone);
delonetwo: fp_del
GENERIC MAP(width=>18,pipes=>7)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guess,cc=>guessdel);
-- in level 7, out level 9 (18x18=36)
oneone: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36,pipes=>2,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guess,databb=>guess,
result=>multoneone);
-- in level 9, out level 12 (36x36=37)
onetwo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>37,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>radicanddelone(54 DOWNTO 19),databb=>multoneone,
result=>multonetwo);
-- multonetwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (37 DOWNTO 2), otherwise (38 DOWNTO 3)
-- round bit in position 1 or 2
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= '0';
suboneff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--invert here so that borrow can be added in simple expression
-- level 13
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= NOT((multonetwo(k) AND oddff(12)) OR (multonetwo(k+1) AND NOT(oddff(12))));
END LOOP;
-- level 14
suboneff <= ("11" & zerovec(34 DOWNTO 1)) +
('1' & multonetwoff(36 DOWNTO 2)) +
(zerovec(35 DOWNTO 1) & multonetwoff(1));
END IF;
END IF;
END PROCESS;
-- in level 14, out level 17 (36x18=37)
onethr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>18,widthcc=>37,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>suboneff,databb=>guessdel,
result=>multonethr);
-- mult by 2 - subone is about 1 (1.000 or 0.9999) so will effectively multiply by 0.5
guessonevec <= multonethr(36 DOWNTO 1);
--************************
--*** SECOND ITERATION ***
--************************
--X' = X/2(3-YXX)
deltwoone: fp_del
GENERIC MAP(width=>54,pipes=>11)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicanddelone,cc=>radicanddeltwo);
-- SII level in 17, level out 26+doublespeed
-- SIII/IV level in 17, level out 25
deltwotwo: fp_del
GENERIC MAP(width=>36,pipes=>(9+doublespeed-device*(1+doublespeed)))
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guessonevec,cc=>guessonevecdelone);
deltwothr: fp_del
GENERIC MAP (width=>36,pipes=>4)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guessonevecdelone,cc=>guessonevecdeltwo);
-- in level 17, out level 20 (36x36=54)
twoone: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>54,pipes=>3,
accuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessonevec,databb=>guessonevec,
result=>multtwoone);
-- in level 20,
-- SII out level 25/26 - 25+doublespeed
-- SIII/SIV out level 24
twotwo: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,pipes=>mullatency,
accuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multtwoone,databb=>radicanddeltwo,
result=>multtwotwo);
-- multtwotwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (55 DOWNTO 2), otherwise (56 DOWNTO 3)
-- round bit in position 1 or 2
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multtwotwoff(k) <= '0';
END LOOP;
finaladdsubff <= "0000";
FOR k IN 1 TO 55 LOOP
finaladdff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
-- SII in level 25+doublespeed, out level 26+doublespeed
-- SIII in level 24, out level 25
-- if multwotwo > 1, subtwo negative, subtract multwothr from guessonevec
-- if multwotwo <= 1, subtwo positive, add multwothr to guessonevec
FOR k IN 1 TO 36 LOOP
multtwotwoff(k) <= ((multtwotwo(k+6) AND oddff(25+doublespeed-device*(1+doublespeed))) OR
(multtwotwo(k+7) AND NOT(oddff(25+doublespeed-device*(1+doublespeed))))) XOR finaladdsub;
END LOOP;
finaladdsubff(1) <= finaladdsub;
FOR k IN 2 TO 4 LOOP
finaladdsubff(k) <= finaladdsubff(k-1);
END LOOP;
-- makes sure no overflow happens here, for example if less than 30 leading 1s/0s
-- in multtwotwoff
-- SII level in 29+doublespeed level out 30+doublespeed
-- SIII level in 28 level out 29
FOR k IN 1 TO 26 LOOP
finaladdff(k) <= multtwothr(k+10) XOR NOT(finaladdsubff(4));
END LOOP;
FOR k IN 27 TO 55 LOOP
finaladdff(k) <= NOT(finaladdsubff(4));
END LOOP;
END IF;
END IF;
END PROCESS;
-- doesnt have to be near msb
finaladdsub <= multtwotwo(60);
-- SII level in (26+doublespeed), level out (29+doublespeed)
-- SII level in 25, level out 28
twothr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multtwotwoff,databb=>guessonevecdelone,
result=>multtwothr);
finalguessvec <= guessonevecdeltwo & zerovec(17 DOWNTO 1);
-- SII level in 30+doublespeed, level out 31+2*doublespeed
-- SIII level in 29, level out 30+doublespeed
final: dp_fxadd
GENERIC MAP (width=>53,pipes=>doublespeed+1,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>finalguessvec,bb=>finaladdff(55 DOWNTO 3),carryin=>finaladdff(2),
cc=>invrootvec);
invroot <= invrootvec & '0';
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** CORE ***
--*** ***
--*** DP_INVSQR_CORE.VHD ***
--*** ***
--*** Function: 54 bit Inverse Square Root ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 24/04/09 - SIII/SIV multiplier support ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** SII Latency = 31 + 2*doublespeed ***
--*** SIII/IV Latency = 30 + doublespeed ***
--*** 1. Output is rounded already, LSB always 0 ***
--***************************************************
ENTITY dp_invsqr_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
odd : IN STD_LOGIC;
invroot : OUT STD_LOGIC_VECTOR (54 DOWNTO 1)
);
END dp_invsqr_core;
ARCHITECTURE rtl OF dp_invsqr_core IS
--SII mullatency = speed+5, SIII/IV mullatency = 4
constant mullatency : positive := doublespeed+5 - device*(1+doublespeed);
signal zerovec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal evennum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddnum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guessvec : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddff : STD_LOGIC_VECTOR (25+doublespeed DOWNTO 1);
signal scalenumff : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guess : STD_LOGIC_VECTOR (18 DOWNTO 1);
-- 1st iteration
signal radicanddelone : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal guessdel : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal multoneone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonetwo : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal multonetwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal suboneff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonethr : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal guessonevec : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- 2ns iteration
signal radicanddeltwo : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal guessonevecdelone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal guessonevecdeltwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multtwoone : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal multtwotwo : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multtwotwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal finaladdsub : STD_LOGIC;
signal finaladdsubff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal finaladdff : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal multtwothr : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal finalguessvec : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal invrootvec : STD_LOGIC_VECTOR (53 DOWNTO 1);
component fp_invsqr_est IS
GENERIC (synthesize : integer := 0); -- 0 = behavioral, 1 = syntheziable
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invroot : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
end component;
component dp_fxadd IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
oddnum <= conv_std_logic_vector(185363,18); -- mult by 2^-.5 (odd exp)
evennum <= conv_std_logic_vector(262143,18); -- mult by 1 (even exp)
gza: FOR k IN 1 TO 54 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- in level 0, out level 5
look: fp_invsqr_est
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radicand=>radicand(54 DOWNTO 36),invroot=>guessvec);
pta: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 25+doublespeed LOOP
oddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
oddff(1) <= odd;
FOR k IN 2 TO 25+doublespeed LOOP
oddff(k) <= oddff(k-1);
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= (oddnum(k) AND oddff(4)) OR (evennum(k) AND NOT(oddff(4)));
END LOOP;
END IF;
END IF;
END PROCESS;
-- in level 5, out level 7
mulscale: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>18,pipes=>2,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessvec,databb=>scalenumff,
result=>guess);
--*********************
--*** ITERATION ONE ***
--*********************
--X' = X/2(3-YXX)
deloneone: fp_del
GENERIC MAP(width=>54,pipes=>9)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicand,cc=>radicanddelone);
delonetwo: fp_del
GENERIC MAP(width=>18,pipes=>7)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guess,cc=>guessdel);
-- in level 7, out level 9 (18x18=36)
oneone: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36,pipes=>2,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guess,databb=>guess,
result=>multoneone);
-- in level 9, out level 12 (36x36=37)
onetwo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>37,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>radicanddelone(54 DOWNTO 19),databb=>multoneone,
result=>multonetwo);
-- multonetwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (37 DOWNTO 2), otherwise (38 DOWNTO 3)
-- round bit in position 1 or 2
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= '0';
suboneff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--invert here so that borrow can be added in simple expression
-- level 13
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= NOT((multonetwo(k) AND oddff(12)) OR (multonetwo(k+1) AND NOT(oddff(12))));
END LOOP;
-- level 14
suboneff <= ("11" & zerovec(34 DOWNTO 1)) +
('1' & multonetwoff(36 DOWNTO 2)) +
(zerovec(35 DOWNTO 1) & multonetwoff(1));
END IF;
END IF;
END PROCESS;
-- in level 14, out level 17 (36x18=37)
onethr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>18,widthcc=>37,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>suboneff,databb=>guessdel,
result=>multonethr);
-- mult by 2 - subone is about 1 (1.000 or 0.9999) so will effectively multiply by 0.5
guessonevec <= multonethr(36 DOWNTO 1);
--************************
--*** SECOND ITERATION ***
--************************
--X' = X/2(3-YXX)
deltwoone: fp_del
GENERIC MAP(width=>54,pipes=>11)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicanddelone,cc=>radicanddeltwo);
-- SII level in 17, level out 26+doublespeed
-- SIII/IV level in 17, level out 25
deltwotwo: fp_del
GENERIC MAP(width=>36,pipes=>(9+doublespeed-device*(1+doublespeed)))
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guessonevec,cc=>guessonevecdelone);
deltwothr: fp_del
GENERIC MAP (width=>36,pipes=>4)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guessonevecdelone,cc=>guessonevecdeltwo);
-- in level 17, out level 20 (36x36=54)
twoone: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>54,pipes=>3,
accuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessonevec,databb=>guessonevec,
result=>multtwoone);
-- in level 20,
-- SII out level 25/26 - 25+doublespeed
-- SIII/SIV out level 24
twotwo: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,pipes=>mullatency,
accuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multtwoone,databb=>radicanddeltwo,
result=>multtwotwo);
-- multtwotwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (55 DOWNTO 2), otherwise (56 DOWNTO 3)
-- round bit in position 1 or 2
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multtwotwoff(k) <= '0';
END LOOP;
finaladdsubff <= "0000";
FOR k IN 1 TO 55 LOOP
finaladdff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
-- SII in level 25+doublespeed, out level 26+doublespeed
-- SIII in level 24, out level 25
-- if multwotwo > 1, subtwo negative, subtract multwothr from guessonevec
-- if multwotwo <= 1, subtwo positive, add multwothr to guessonevec
FOR k IN 1 TO 36 LOOP
multtwotwoff(k) <= ((multtwotwo(k+6) AND oddff(25+doublespeed-device*(1+doublespeed))) OR
(multtwotwo(k+7) AND NOT(oddff(25+doublespeed-device*(1+doublespeed))))) XOR finaladdsub;
END LOOP;
finaladdsubff(1) <= finaladdsub;
FOR k IN 2 TO 4 LOOP
finaladdsubff(k) <= finaladdsubff(k-1);
END LOOP;
-- makes sure no overflow happens here, for example if less than 30 leading 1s/0s
-- in multtwotwoff
-- SII level in 29+doublespeed level out 30+doublespeed
-- SIII level in 28 level out 29
FOR k IN 1 TO 26 LOOP
finaladdff(k) <= multtwothr(k+10) XOR NOT(finaladdsubff(4));
END LOOP;
FOR k IN 27 TO 55 LOOP
finaladdff(k) <= NOT(finaladdsubff(4));
END LOOP;
END IF;
END IF;
END PROCESS;
-- doesnt have to be near msb
finaladdsub <= multtwotwo(60);
-- SII level in (26+doublespeed), level out (29+doublespeed)
-- SII level in 25, level out 28
twothr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multtwotwoff,databb=>guessonevecdelone,
result=>multtwothr);
finalguessvec <= guessonevecdeltwo & zerovec(17 DOWNTO 1);
-- SII level in 30+doublespeed, level out 31+2*doublespeed
-- SIII level in 29, level out 30+doublespeed
final: dp_fxadd
GENERIC MAP (width=>53,pipes=>doublespeed+1,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>finalguessvec,bb=>finaladdff(55 DOWNTO 3),carryin=>finaladdff(2),
cc=>invrootvec);
invroot <= invrootvec & '0';
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** CORE ***
--*** ***
--*** DP_INVSQR_CORE.VHD ***
--*** ***
--*** Function: 54 bit Inverse Square Root ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 24/04/09 - SIII/SIV multiplier support ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** SII Latency = 31 + 2*doublespeed ***
--*** SIII/IV Latency = 30 + doublespeed ***
--*** 1. Output is rounded already, LSB always 0 ***
--***************************************************
ENTITY dp_invsqr_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
odd : IN STD_LOGIC;
invroot : OUT STD_LOGIC_VECTOR (54 DOWNTO 1)
);
END dp_invsqr_core;
ARCHITECTURE rtl OF dp_invsqr_core IS
--SII mullatency = speed+5, SIII/IV mullatency = 4
constant mullatency : positive := doublespeed+5 - device*(1+doublespeed);
signal zerovec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal evennum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddnum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guessvec : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddff : STD_LOGIC_VECTOR (25+doublespeed DOWNTO 1);
signal scalenumff : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guess : STD_LOGIC_VECTOR (18 DOWNTO 1);
-- 1st iteration
signal radicanddelone : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal guessdel : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal multoneone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonetwo : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal multonetwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal suboneff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonethr : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal guessonevec : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- 2ns iteration
signal radicanddeltwo : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal guessonevecdelone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal guessonevecdeltwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multtwoone : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal multtwotwo : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multtwotwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal finaladdsub : STD_LOGIC;
signal finaladdsubff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal finaladdff : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal multtwothr : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal finalguessvec : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal invrootvec : STD_LOGIC_VECTOR (53 DOWNTO 1);
component fp_invsqr_est IS
GENERIC (synthesize : integer := 0); -- 0 = behavioral, 1 = syntheziable
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invroot : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
end component;
component dp_fxadd IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
oddnum <= conv_std_logic_vector(185363,18); -- mult by 2^-.5 (odd exp)
evennum <= conv_std_logic_vector(262143,18); -- mult by 1 (even exp)
gza: FOR k IN 1 TO 54 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- in level 0, out level 5
look: fp_invsqr_est
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radicand=>radicand(54 DOWNTO 36),invroot=>guessvec);
pta: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 25+doublespeed LOOP
oddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
oddff(1) <= odd;
FOR k IN 2 TO 25+doublespeed LOOP
oddff(k) <= oddff(k-1);
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= (oddnum(k) AND oddff(4)) OR (evennum(k) AND NOT(oddff(4)));
END LOOP;
END IF;
END IF;
END PROCESS;
-- in level 5, out level 7
mulscale: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>18,pipes=>2,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessvec,databb=>scalenumff,
result=>guess);
--*********************
--*** ITERATION ONE ***
--*********************
--X' = X/2(3-YXX)
deloneone: fp_del
GENERIC MAP(width=>54,pipes=>9)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicand,cc=>radicanddelone);
delonetwo: fp_del
GENERIC MAP(width=>18,pipes=>7)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guess,cc=>guessdel);
-- in level 7, out level 9 (18x18=36)
oneone: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36,pipes=>2,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guess,databb=>guess,
result=>multoneone);
-- in level 9, out level 12 (36x36=37)
onetwo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>37,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>radicanddelone(54 DOWNTO 19),databb=>multoneone,
result=>multonetwo);
-- multonetwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (37 DOWNTO 2), otherwise (38 DOWNTO 3)
-- round bit in position 1 or 2
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= '0';
suboneff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--invert here so that borrow can be added in simple expression
-- level 13
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= NOT((multonetwo(k) AND oddff(12)) OR (multonetwo(k+1) AND NOT(oddff(12))));
END LOOP;
-- level 14
suboneff <= ("11" & zerovec(34 DOWNTO 1)) +
('1' & multonetwoff(36 DOWNTO 2)) +
(zerovec(35 DOWNTO 1) & multonetwoff(1));
END IF;
END IF;
END PROCESS;
-- in level 14, out level 17 (36x18=37)
onethr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>18,widthcc=>37,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>suboneff,databb=>guessdel,
result=>multonethr);
-- mult by 2 - subone is about 1 (1.000 or 0.9999) so will effectively multiply by 0.5
guessonevec <= multonethr(36 DOWNTO 1);
--************************
--*** SECOND ITERATION ***
--************************
--X' = X/2(3-YXX)
deltwoone: fp_del
GENERIC MAP(width=>54,pipes=>11)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicanddelone,cc=>radicanddeltwo);
-- SII level in 17, level out 26+doublespeed
-- SIII/IV level in 17, level out 25
deltwotwo: fp_del
GENERIC MAP(width=>36,pipes=>(9+doublespeed-device*(1+doublespeed)))
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guessonevec,cc=>guessonevecdelone);
deltwothr: fp_del
GENERIC MAP (width=>36,pipes=>4)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guessonevecdelone,cc=>guessonevecdeltwo);
-- in level 17, out level 20 (36x36=54)
twoone: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>54,pipes=>3,
accuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessonevec,databb=>guessonevec,
result=>multtwoone);
-- in level 20,
-- SII out level 25/26 - 25+doublespeed
-- SIII/SIV out level 24
twotwo: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,pipes=>mullatency,
accuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multtwoone,databb=>radicanddeltwo,
result=>multtwotwo);
-- multtwotwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (55 DOWNTO 2), otherwise (56 DOWNTO 3)
-- round bit in position 1 or 2
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multtwotwoff(k) <= '0';
END LOOP;
finaladdsubff <= "0000";
FOR k IN 1 TO 55 LOOP
finaladdff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
-- SII in level 25+doublespeed, out level 26+doublespeed
-- SIII in level 24, out level 25
-- if multwotwo > 1, subtwo negative, subtract multwothr from guessonevec
-- if multwotwo <= 1, subtwo positive, add multwothr to guessonevec
FOR k IN 1 TO 36 LOOP
multtwotwoff(k) <= ((multtwotwo(k+6) AND oddff(25+doublespeed-device*(1+doublespeed))) OR
(multtwotwo(k+7) AND NOT(oddff(25+doublespeed-device*(1+doublespeed))))) XOR finaladdsub;
END LOOP;
finaladdsubff(1) <= finaladdsub;
FOR k IN 2 TO 4 LOOP
finaladdsubff(k) <= finaladdsubff(k-1);
END LOOP;
-- makes sure no overflow happens here, for example if less than 30 leading 1s/0s
-- in multtwotwoff
-- SII level in 29+doublespeed level out 30+doublespeed
-- SIII level in 28 level out 29
FOR k IN 1 TO 26 LOOP
finaladdff(k) <= multtwothr(k+10) XOR NOT(finaladdsubff(4));
END LOOP;
FOR k IN 27 TO 55 LOOP
finaladdff(k) <= NOT(finaladdsubff(4));
END LOOP;
END IF;
END IF;
END PROCESS;
-- doesnt have to be near msb
finaladdsub <= multtwotwo(60);
-- SII level in (26+doublespeed), level out (29+doublespeed)
-- SII level in 25, level out 28
twothr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multtwotwoff,databb=>guessonevecdelone,
result=>multtwothr);
finalguessvec <= guessonevecdeltwo & zerovec(17 DOWNTO 1);
-- SII level in 30+doublespeed, level out 31+2*doublespeed
-- SIII level in 29, level out 30+doublespeed
final: dp_fxadd
GENERIC MAP (width=>53,pipes=>doublespeed+1,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>finalguessvec,bb=>finaladdff(55 DOWNTO 3),carryin=>finaladdff(2),
cc=>invrootvec);
invroot <= invrootvec & '0';
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** CORE ***
--*** ***
--*** DP_INVSQR_CORE.VHD ***
--*** ***
--*** Function: 54 bit Inverse Square Root ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 24/04/09 - SIII/SIV multiplier support ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** SII Latency = 31 + 2*doublespeed ***
--*** SIII/IV Latency = 30 + doublespeed ***
--*** 1. Output is rounded already, LSB always 0 ***
--***************************************************
ENTITY dp_invsqr_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
odd : IN STD_LOGIC;
invroot : OUT STD_LOGIC_VECTOR (54 DOWNTO 1)
);
END dp_invsqr_core;
ARCHITECTURE rtl OF dp_invsqr_core IS
--SII mullatency = speed+5, SIII/IV mullatency = 4
constant mullatency : positive := doublespeed+5 - device*(1+doublespeed);
signal zerovec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal evennum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddnum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guessvec : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddff : STD_LOGIC_VECTOR (25+doublespeed DOWNTO 1);
signal scalenumff : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guess : STD_LOGIC_VECTOR (18 DOWNTO 1);
-- 1st iteration
signal radicanddelone : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal guessdel : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal multoneone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonetwo : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal multonetwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal suboneff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonethr : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal guessonevec : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- 2ns iteration
signal radicanddeltwo : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal guessonevecdelone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal guessonevecdeltwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multtwoone : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal multtwotwo : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multtwotwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal finaladdsub : STD_LOGIC;
signal finaladdsubff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal finaladdff : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal multtwothr : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal finalguessvec : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal invrootvec : STD_LOGIC_VECTOR (53 DOWNTO 1);
component fp_invsqr_est IS
GENERIC (synthesize : integer := 0); -- 0 = behavioral, 1 = syntheziable
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invroot : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
end component;
component dp_fxadd IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
oddnum <= conv_std_logic_vector(185363,18); -- mult by 2^-.5 (odd exp)
evennum <= conv_std_logic_vector(262143,18); -- mult by 1 (even exp)
gza: FOR k IN 1 TO 54 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- in level 0, out level 5
look: fp_invsqr_est
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radicand=>radicand(54 DOWNTO 36),invroot=>guessvec);
pta: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 25+doublespeed LOOP
oddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
oddff(1) <= odd;
FOR k IN 2 TO 25+doublespeed LOOP
oddff(k) <= oddff(k-1);
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= (oddnum(k) AND oddff(4)) OR (evennum(k) AND NOT(oddff(4)));
END LOOP;
END IF;
END IF;
END PROCESS;
-- in level 5, out level 7
mulscale: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>18,pipes=>2,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessvec,databb=>scalenumff,
result=>guess);
--*********************
--*** ITERATION ONE ***
--*********************
--X' = X/2(3-YXX)
deloneone: fp_del
GENERIC MAP(width=>54,pipes=>9)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicand,cc=>radicanddelone);
delonetwo: fp_del
GENERIC MAP(width=>18,pipes=>7)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guess,cc=>guessdel);
-- in level 7, out level 9 (18x18=36)
oneone: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36,pipes=>2,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guess,databb=>guess,
result=>multoneone);
-- in level 9, out level 12 (36x36=37)
onetwo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>37,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>radicanddelone(54 DOWNTO 19),databb=>multoneone,
result=>multonetwo);
-- multonetwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (37 DOWNTO 2), otherwise (38 DOWNTO 3)
-- round bit in position 1 or 2
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= '0';
suboneff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--invert here so that borrow can be added in simple expression
-- level 13
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= NOT((multonetwo(k) AND oddff(12)) OR (multonetwo(k+1) AND NOT(oddff(12))));
END LOOP;
-- level 14
suboneff <= ("11" & zerovec(34 DOWNTO 1)) +
('1' & multonetwoff(36 DOWNTO 2)) +
(zerovec(35 DOWNTO 1) & multonetwoff(1));
END IF;
END IF;
END PROCESS;
-- in level 14, out level 17 (36x18=37)
onethr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>18,widthcc=>37,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>suboneff,databb=>guessdel,
result=>multonethr);
-- mult by 2 - subone is about 1 (1.000 or 0.9999) so will effectively multiply by 0.5
guessonevec <= multonethr(36 DOWNTO 1);
--************************
--*** SECOND ITERATION ***
--************************
--X' = X/2(3-YXX)
deltwoone: fp_del
GENERIC MAP(width=>54,pipes=>11)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicanddelone,cc=>radicanddeltwo);
-- SII level in 17, level out 26+doublespeed
-- SIII/IV level in 17, level out 25
deltwotwo: fp_del
GENERIC MAP(width=>36,pipes=>(9+doublespeed-device*(1+doublespeed)))
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guessonevec,cc=>guessonevecdelone);
deltwothr: fp_del
GENERIC MAP (width=>36,pipes=>4)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guessonevecdelone,cc=>guessonevecdeltwo);
-- in level 17, out level 20 (36x36=54)
twoone: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>54,pipes=>3,
accuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessonevec,databb=>guessonevec,
result=>multtwoone);
-- in level 20,
-- SII out level 25/26 - 25+doublespeed
-- SIII/SIV out level 24
twotwo: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,pipes=>mullatency,
accuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multtwoone,databb=>radicanddeltwo,
result=>multtwotwo);
-- multtwotwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (55 DOWNTO 2), otherwise (56 DOWNTO 3)
-- round bit in position 1 or 2
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multtwotwoff(k) <= '0';
END LOOP;
finaladdsubff <= "0000";
FOR k IN 1 TO 55 LOOP
finaladdff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
-- SII in level 25+doublespeed, out level 26+doublespeed
-- SIII in level 24, out level 25
-- if multwotwo > 1, subtwo negative, subtract multwothr from guessonevec
-- if multwotwo <= 1, subtwo positive, add multwothr to guessonevec
FOR k IN 1 TO 36 LOOP
multtwotwoff(k) <= ((multtwotwo(k+6) AND oddff(25+doublespeed-device*(1+doublespeed))) OR
(multtwotwo(k+7) AND NOT(oddff(25+doublespeed-device*(1+doublespeed))))) XOR finaladdsub;
END LOOP;
finaladdsubff(1) <= finaladdsub;
FOR k IN 2 TO 4 LOOP
finaladdsubff(k) <= finaladdsubff(k-1);
END LOOP;
-- makes sure no overflow happens here, for example if less than 30 leading 1s/0s
-- in multtwotwoff
-- SII level in 29+doublespeed level out 30+doublespeed
-- SIII level in 28 level out 29
FOR k IN 1 TO 26 LOOP
finaladdff(k) <= multtwothr(k+10) XOR NOT(finaladdsubff(4));
END LOOP;
FOR k IN 27 TO 55 LOOP
finaladdff(k) <= NOT(finaladdsubff(4));
END LOOP;
END IF;
END IF;
END PROCESS;
-- doesnt have to be near msb
finaladdsub <= multtwotwo(60);
-- SII level in (26+doublespeed), level out (29+doublespeed)
-- SII level in 25, level out 28
twothr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multtwotwoff,databb=>guessonevecdelone,
result=>multtwothr);
finalguessvec <= guessonevecdeltwo & zerovec(17 DOWNTO 1);
-- SII level in 30+doublespeed, level out 31+2*doublespeed
-- SIII level in 29, level out 30+doublespeed
final: dp_fxadd
GENERIC MAP (width=>53,pipes=>doublespeed+1,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>finalguessvec,bb=>finaladdff(55 DOWNTO 3),carryin=>finaladdff(2),
cc=>invrootvec);
invroot <= invrootvec & '0';
END rtl;
|
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementation, use multiplexed channels
--
--
-- "The Filter was a classic multi-mode (state variable) VCF design. There was
-- no way to create a variable transconductance amplifier in our NMOS process,
-- so I simply used FETs as voltage-controlled resistors to control the cutoff
-- frequency. An 11-bit D/A converter generates the control voltage for the
-- FETs (it's actually a 12-bit D/A, but the LSB had no audible affect so I
-- disconnected it!)."
-- "Filter resonance was controlled by a 4-bit weighted resistor ladder. Each
-- bit would turn on one of the weighted resistors and allow a portion of the
-- output to feed back to the input. The state-variable design provided
-- simultaneous low-pass, band-pass and high-pass outputs. Analog switches
-- selected which combination of outputs were sent to the final amplifier (a
-- notch filter was created by enabling both the high and low-pass outputs
-- simultaneously)."
-- "The filter is the worst part of SID because I could not create high-gain
-- op-amps in NMOS, which were essential to a resonant filter. In addition,
-- the resistance of the FETs varied considerably with processing, so different
-- lots of SID chips had different cutoff frequency characteristics. I knew it
-- wouldn't work very well, but it was better than nothing and I didn't have
-- time to make it better."
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end sid6581;
architecture Behavioral of sid6581 is
--Implementation Digital to Analog converter
component pwm_sddac is
port (
clk_i : in std_logic; -- main clock signal, the higher the better
reset : in std_logic; -- reset input active high
dac_o : out std_logic; -- PWM output after a simple low-pass filter this is to be considered an analog signal
dac_i : in std_logic_vector(9 downto 0) -- binary input of signal to be converted
);
end component;
component pwm_sdadc is
port (
clk : in std_logic; -- main clock signal (actually the higher the better)
reset : in std_logic; --
ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted
ADC_in : in std_logic -- "analog" paddle input pin
);
end component;
-- Implementation of the SID voices (sound channels)
component sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); --
Freq_hi : in std_logic_vector(7 downto 0); --
Pw_lo : in std_logic_vector(7 downto 0); --
Pw_hi : in std_logic_vector(3 downto 0); --
Control : in std_logic_vector(7 downto 0); --
Att_dec : in std_logic_vector(7 downto 0); --
Sus_Rel : in std_logic_vector(7 downto 0); --
PA_MSB_in : in std_logic; --
PA_MSB_out : out std_logic; --
Osc : out std_logic_vector(7 downto 0); --
Env : out std_logic_vector(7 downto 0); --
voice : out std_logic_vector(11 downto 0) --
);
end component;
component sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end component;
-------------------------------------------------------------------------------
--constant <name>: <type> := <value>;
-- DC offset required to play samples, this is actually a bug of the real 6581,
-- that was converted into an advantage to play samples
constant DC_offset : std_logic_vector(13 downto 0) := "00111111111111";
-------------------------------------------------------------------------------
signal Voice_1_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_1_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_2_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_3_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Res_Filt : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Mode_Vol : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotX : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotY : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Osc3_Random : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Env3 : std_logic_vector(7 downto 0) := (others => '0');
signal do_buf : std_logic_vector(7 downto 0) := (others => '0');
signal voice_1 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_2 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_3 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_mixed : std_logic_vector(13 downto 0) := (others => '0');
signal voice_volume : std_logic_vector(35 downto 0) := (others => '0');
signal divide_0 : std_logic_vector(31 downto 0) := (others => '0');
signal voice_1_PA_MSB : std_logic := '0';
signal voice_2_PA_MSB : std_logic := '0';
signal voice_3_PA_MSB : std_logic := '0';
-------------------------------------------------------------------------------
begin
digital_to_analog: pwm_sddac
port map(
clk_i => clk_DAC,
reset => reset,
dac_i => voice_volume(17 downto 8),
dac_o => audio_out
);
paddle_x: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotX,
ADC_in => pot_x
);
paddle_y: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotY,
ADC_in => pot_y
);
sid_voice_1: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_1_Freq_lo,
Freq_hi => Voice_1_Freq_hi,
Pw_lo => Voice_1_Pw_lo,
Pw_hi => Voice_1_Pw_hi,
Control => Voice_1_Control,
Att_dec => Voice_1_Att_dec,
Sus_Rel => Voice_1_Sus_Rel,
PA_MSB_in => voice_3_PA_MSB,
PA_MSB_out => voice_1_PA_MSB,
Osc => Voice_1_Osc,
Env => Voice_1_Env,
voice => voice_1
);
sid_voice_2: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_2_Freq_lo,
Freq_hi => Voice_2_Freq_hi,
Pw_lo => Voice_2_Pw_lo,
Pw_hi => Voice_2_Pw_hi,
Control => Voice_2_Control,
Att_dec => Voice_2_Att_dec,
Sus_Rel => Voice_2_Sus_Rel,
PA_MSB_in => voice_1_PA_MSB,
PA_MSB_out => voice_2_PA_MSB,
Osc => Voice_2_Osc,
Env => Voice_2_Env,
voice => voice_2
);
sid_voice_3: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_3_Freq_lo,
Freq_hi => Voice_3_Freq_hi,
Pw_lo => Voice_3_Pw_lo,
Pw_hi => Voice_3_Pw_hi,
Control => Voice_3_Control,
Att_dec => Voice_3_Att_dec,
Sus_Rel => Voice_3_Sus_Rel,
PA_MSB_in => voice_2_PA_MSB,
PA_MSB_out => voice_3_PA_MSB,
Osc => Misc_Osc3_Random,
Env => Misc_Env3,
voice => voice_3
);
-------------------------------------------------------------------------------------
do <= do_buf;
-- SID filters
fblk: block
signal voice1_signed: signed(12 downto 0);
signal voice2_signed: signed(12 downto 0);
signal voice3_signed: signed(12 downto 0);
constant ext_in_signed: signed(12 downto 0) := to_signed(0,13);
signal filtered_audio: signed(18 downto 0);
signal tick_q1, tick_q2: std_logic;
signal input_valid: std_logic;
signal unsigned_audio: std_logic_vector(17 downto 0);
signal unsigned_filt: std_logic_vector(18 downto 0);
signal ff1: std_logic;
begin
process (clk_1MHz,reset)
begin
if reset='1' then
ff1<='0';
else
if rising_edge(clk_1MHz) then
ff1<=not ff1;
end if;
end if;
end process;
process(clk32)
begin
if rising_edge(clk32) then
tick_q1 <= ff1;
tick_q2 <= tick_q1;
end if;
end process;
input_valid<='1' when tick_q1 /=tick_q2 else '0';
voice1_signed <= signed(voice_1 & "0") - 4096;
voice2_signed <= signed(voice_2 & "0") - 4096;
voice3_signed <= signed(voice_3 & "0") - 4096;
filters: sid_filters
port map (
clk => clk32,
rst => reset,
-- SID registers.
Fc_lo => Filter_Fc_lo,
Fc_hi => Filter_Fc_hi,
Res_Filt => Filter_Res_Filt,
Mode_Vol => Filter_Mode_Vol,
-- Voices - resampled to 13 bit
voice1 => voice1_signed,
voice2 => voice2_signed,
voice3 => voice3_signed,
--
input_valid => input_valid,
ext_in => ext_in_signed,
sound => filtered_audio,
valid => open
);
unsigned_filt <= std_logic_vector(filtered_audio + "1000000000000000000");
unsigned_audio <= unsigned_filt(18 downto 1);
audio_data <= unsigned_audio;
end block;
-- Register decoding
register_decoder:process(clk32)
begin
if rising_edge(clk32) then
if (reset = '1') then
--------------------------------------- Voice-1
Voice_1_Freq_lo <= (others => '0');
Voice_1_Freq_hi <= (others => '0');
Voice_1_Pw_lo <= (others => '0');
Voice_1_Pw_hi <= (others => '0');
Voice_1_Control <= (others => '0');
Voice_1_Att_dec <= (others => '0');
Voice_1_Sus_Rel <= (others => '0');
--------------------------------------- Voice-2
Voice_2_Freq_lo <= (others => '0');
Voice_2_Freq_hi <= (others => '0');
Voice_2_Pw_lo <= (others => '0');
Voice_2_Pw_hi <= (others => '0');
Voice_2_Control <= (others => '0');
Voice_2_Att_dec <= (others => '0');
Voice_2_Sus_Rel <= (others => '0');
--------------------------------------- Voice-3
Voice_3_Freq_lo <= (others => '0');
Voice_3_Freq_hi <= (others => '0');
Voice_3_Pw_lo <= (others => '0');
Voice_3_Pw_hi <= (others => '0');
Voice_3_Control <= (others => '0');
Voice_3_Att_dec <= (others => '0');
Voice_3_Sus_Rel <= (others => '0');
--------------------------------------- Filter & volume
Filter_Fc_lo <= (others => '0');
Filter_Fc_hi <= (others => '0');
Filter_Res_Filt <= (others => '0');
Filter_Mode_Vol <= (others => '0');
else
Voice_1_Freq_lo <= Voice_1_Freq_lo;
Voice_1_Freq_hi <= Voice_1_Freq_hi;
Voice_1_Pw_lo <= Voice_1_Pw_lo;
Voice_1_Pw_hi <= Voice_1_Pw_hi;
Voice_1_Control <= Voice_1_Control;
Voice_1_Att_dec <= Voice_1_Att_dec;
Voice_1_Sus_Rel <= Voice_1_Sus_Rel;
Voice_2_Freq_lo <= Voice_2_Freq_lo;
Voice_2_Freq_hi <= Voice_2_Freq_hi;
Voice_2_Pw_lo <= Voice_2_Pw_lo;
Voice_2_Pw_hi <= Voice_2_Pw_hi;
Voice_2_Control <= Voice_2_Control;
Voice_2_Att_dec <= Voice_2_Att_dec;
Voice_2_Sus_Rel <= Voice_2_Sus_Rel;
Voice_3_Freq_lo <= Voice_3_Freq_lo;
Voice_3_Freq_hi <= Voice_3_Freq_hi;
Voice_3_Pw_lo <= Voice_3_Pw_lo;
Voice_3_Pw_hi <= Voice_3_Pw_hi;
Voice_3_Control <= Voice_3_Control;
Voice_3_Att_dec <= Voice_3_Att_dec;
Voice_3_Sus_Rel <= Voice_3_Sus_Rel;
Filter_Fc_lo <= Filter_Fc_lo;
Filter_Fc_hi <= Filter_Fc_hi;
Filter_Res_Filt <= Filter_Res_Filt;
Filter_Mode_Vol <= Filter_Mode_Vol;
do_buf <= (others => '0');
if (cs='1') then
if (we='1') then -- Write to SID-register
------------------------
case addr is
-------------------------------------- Voice-1
when "00000" => Voice_1_Freq_lo <= di;
when "00001" => Voice_1_Freq_hi <= di;
when "00010" => Voice_1_Pw_lo <= di;
when "00011" => Voice_1_Pw_hi <= di(3 downto 0);
when "00100" => Voice_1_Control <= di;
when "00101" => Voice_1_Att_dec <= di;
when "00110" => Voice_1_Sus_Rel <= di;
--------------------------------------- Voice-2
when "00111" => Voice_2_Freq_lo <= di;
when "01000" => Voice_2_Freq_hi <= di;
when "01001" => Voice_2_Pw_lo <= di;
when "01010" => Voice_2_Pw_hi <= di(3 downto 0);
when "01011" => Voice_2_Control <= di;
when "01100" => Voice_2_Att_dec <= di;
when "01101" => Voice_2_Sus_Rel <= di;
--------------------------------------- Voice-3
when "01110" => Voice_3_Freq_lo <= di;
when "01111" => Voice_3_Freq_hi <= di;
when "10000" => Voice_3_Pw_lo <= di;
when "10001" => Voice_3_Pw_hi <= di(3 downto 0);
when "10010" => Voice_3_Control <= di;
when "10011" => Voice_3_Att_dec <= di;
when "10100" => Voice_3_Sus_Rel <= di;
--------------------------------------- Filter & volume
when "10101" => Filter_Fc_lo <= di;
when "10110" => Filter_Fc_hi <= di;
when "10111" => Filter_Res_Filt <= di;
when "11000" => Filter_Mode_Vol <= di;
--------------------------------------
when others => null;
end case;
else -- Read from SID-register
-------------------------
--case CONV_INTEGER(addr) is
case addr is
-------------------------------------- Misc
when "11001" => do_buf <= Misc_PotX;
when "11010" => do_buf <= Misc_PotY;
when "11011" => do_buf <= Misc_Osc3_Random;
when "11100" => do_buf <= Misc_Env3;
--------------------------------------
-- when others => null;
when others => do_buf <= (others => '0');
end case;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementation, use multiplexed channels
--
--
-- "The Filter was a classic multi-mode (state variable) VCF design. There was
-- no way to create a variable transconductance amplifier in our NMOS process,
-- so I simply used FETs as voltage-controlled resistors to control the cutoff
-- frequency. An 11-bit D/A converter generates the control voltage for the
-- FETs (it's actually a 12-bit D/A, but the LSB had no audible affect so I
-- disconnected it!)."
-- "Filter resonance was controlled by a 4-bit weighted resistor ladder. Each
-- bit would turn on one of the weighted resistors and allow a portion of the
-- output to feed back to the input. The state-variable design provided
-- simultaneous low-pass, band-pass and high-pass outputs. Analog switches
-- selected which combination of outputs were sent to the final amplifier (a
-- notch filter was created by enabling both the high and low-pass outputs
-- simultaneously)."
-- "The filter is the worst part of SID because I could not create high-gain
-- op-amps in NMOS, which were essential to a resonant filter. In addition,
-- the resistance of the FETs varied considerably with processing, so different
-- lots of SID chips had different cutoff frequency characteristics. I knew it
-- wouldn't work very well, but it was better than nothing and I didn't have
-- time to make it better."
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end sid6581;
architecture Behavioral of sid6581 is
--Implementation Digital to Analog converter
component pwm_sddac is
port (
clk_i : in std_logic; -- main clock signal, the higher the better
reset : in std_logic; -- reset input active high
dac_o : out std_logic; -- PWM output after a simple low-pass filter this is to be considered an analog signal
dac_i : in std_logic_vector(9 downto 0) -- binary input of signal to be converted
);
end component;
component pwm_sdadc is
port (
clk : in std_logic; -- main clock signal (actually the higher the better)
reset : in std_logic; --
ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted
ADC_in : in std_logic -- "analog" paddle input pin
);
end component;
-- Implementation of the SID voices (sound channels)
component sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); --
Freq_hi : in std_logic_vector(7 downto 0); --
Pw_lo : in std_logic_vector(7 downto 0); --
Pw_hi : in std_logic_vector(3 downto 0); --
Control : in std_logic_vector(7 downto 0); --
Att_dec : in std_logic_vector(7 downto 0); --
Sus_Rel : in std_logic_vector(7 downto 0); --
PA_MSB_in : in std_logic; --
PA_MSB_out : out std_logic; --
Osc : out std_logic_vector(7 downto 0); --
Env : out std_logic_vector(7 downto 0); --
voice : out std_logic_vector(11 downto 0) --
);
end component;
component sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end component;
-------------------------------------------------------------------------------
--constant <name>: <type> := <value>;
-- DC offset required to play samples, this is actually a bug of the real 6581,
-- that was converted into an advantage to play samples
constant DC_offset : std_logic_vector(13 downto 0) := "00111111111111";
-------------------------------------------------------------------------------
signal Voice_1_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_1_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_2_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_3_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Res_Filt : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Mode_Vol : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotX : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotY : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Osc3_Random : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Env3 : std_logic_vector(7 downto 0) := (others => '0');
signal do_buf : std_logic_vector(7 downto 0) := (others => '0');
signal voice_1 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_2 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_3 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_mixed : std_logic_vector(13 downto 0) := (others => '0');
signal voice_volume : std_logic_vector(35 downto 0) := (others => '0');
signal divide_0 : std_logic_vector(31 downto 0) := (others => '0');
signal voice_1_PA_MSB : std_logic := '0';
signal voice_2_PA_MSB : std_logic := '0';
signal voice_3_PA_MSB : std_logic := '0';
-------------------------------------------------------------------------------
begin
digital_to_analog: pwm_sddac
port map(
clk_i => clk_DAC,
reset => reset,
dac_i => voice_volume(17 downto 8),
dac_o => audio_out
);
paddle_x: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotX,
ADC_in => pot_x
);
paddle_y: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotY,
ADC_in => pot_y
);
sid_voice_1: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_1_Freq_lo,
Freq_hi => Voice_1_Freq_hi,
Pw_lo => Voice_1_Pw_lo,
Pw_hi => Voice_1_Pw_hi,
Control => Voice_1_Control,
Att_dec => Voice_1_Att_dec,
Sus_Rel => Voice_1_Sus_Rel,
PA_MSB_in => voice_3_PA_MSB,
PA_MSB_out => voice_1_PA_MSB,
Osc => Voice_1_Osc,
Env => Voice_1_Env,
voice => voice_1
);
sid_voice_2: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_2_Freq_lo,
Freq_hi => Voice_2_Freq_hi,
Pw_lo => Voice_2_Pw_lo,
Pw_hi => Voice_2_Pw_hi,
Control => Voice_2_Control,
Att_dec => Voice_2_Att_dec,
Sus_Rel => Voice_2_Sus_Rel,
PA_MSB_in => voice_1_PA_MSB,
PA_MSB_out => voice_2_PA_MSB,
Osc => Voice_2_Osc,
Env => Voice_2_Env,
voice => voice_2
);
sid_voice_3: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_3_Freq_lo,
Freq_hi => Voice_3_Freq_hi,
Pw_lo => Voice_3_Pw_lo,
Pw_hi => Voice_3_Pw_hi,
Control => Voice_3_Control,
Att_dec => Voice_3_Att_dec,
Sus_Rel => Voice_3_Sus_Rel,
PA_MSB_in => voice_2_PA_MSB,
PA_MSB_out => voice_3_PA_MSB,
Osc => Misc_Osc3_Random,
Env => Misc_Env3,
voice => voice_3
);
-------------------------------------------------------------------------------------
do <= do_buf;
-- SID filters
fblk: block
signal voice1_signed: signed(12 downto 0);
signal voice2_signed: signed(12 downto 0);
signal voice3_signed: signed(12 downto 0);
constant ext_in_signed: signed(12 downto 0) := to_signed(0,13);
signal filtered_audio: signed(18 downto 0);
signal tick_q1, tick_q2: std_logic;
signal input_valid: std_logic;
signal unsigned_audio: std_logic_vector(17 downto 0);
signal unsigned_filt: std_logic_vector(18 downto 0);
signal ff1: std_logic;
begin
process (clk_1MHz,reset)
begin
if reset='1' then
ff1<='0';
else
if rising_edge(clk_1MHz) then
ff1<=not ff1;
end if;
end if;
end process;
process(clk32)
begin
if rising_edge(clk32) then
tick_q1 <= ff1;
tick_q2 <= tick_q1;
end if;
end process;
input_valid<='1' when tick_q1 /=tick_q2 else '0';
voice1_signed <= signed(voice_1 & "0") - 4096;
voice2_signed <= signed(voice_2 & "0") - 4096;
voice3_signed <= signed(voice_3 & "0") - 4096;
filters: sid_filters
port map (
clk => clk32,
rst => reset,
-- SID registers.
Fc_lo => Filter_Fc_lo,
Fc_hi => Filter_Fc_hi,
Res_Filt => Filter_Res_Filt,
Mode_Vol => Filter_Mode_Vol,
-- Voices - resampled to 13 bit
voice1 => voice1_signed,
voice2 => voice2_signed,
voice3 => voice3_signed,
--
input_valid => input_valid,
ext_in => ext_in_signed,
sound => filtered_audio,
valid => open
);
unsigned_filt <= std_logic_vector(filtered_audio + "1000000000000000000");
unsigned_audio <= unsigned_filt(18 downto 1);
audio_data <= unsigned_audio;
end block;
-- Register decoding
register_decoder:process(clk32)
begin
if rising_edge(clk32) then
if (reset = '1') then
--------------------------------------- Voice-1
Voice_1_Freq_lo <= (others => '0');
Voice_1_Freq_hi <= (others => '0');
Voice_1_Pw_lo <= (others => '0');
Voice_1_Pw_hi <= (others => '0');
Voice_1_Control <= (others => '0');
Voice_1_Att_dec <= (others => '0');
Voice_1_Sus_Rel <= (others => '0');
--------------------------------------- Voice-2
Voice_2_Freq_lo <= (others => '0');
Voice_2_Freq_hi <= (others => '0');
Voice_2_Pw_lo <= (others => '0');
Voice_2_Pw_hi <= (others => '0');
Voice_2_Control <= (others => '0');
Voice_2_Att_dec <= (others => '0');
Voice_2_Sus_Rel <= (others => '0');
--------------------------------------- Voice-3
Voice_3_Freq_lo <= (others => '0');
Voice_3_Freq_hi <= (others => '0');
Voice_3_Pw_lo <= (others => '0');
Voice_3_Pw_hi <= (others => '0');
Voice_3_Control <= (others => '0');
Voice_3_Att_dec <= (others => '0');
Voice_3_Sus_Rel <= (others => '0');
--------------------------------------- Filter & volume
Filter_Fc_lo <= (others => '0');
Filter_Fc_hi <= (others => '0');
Filter_Res_Filt <= (others => '0');
Filter_Mode_Vol <= (others => '0');
else
Voice_1_Freq_lo <= Voice_1_Freq_lo;
Voice_1_Freq_hi <= Voice_1_Freq_hi;
Voice_1_Pw_lo <= Voice_1_Pw_lo;
Voice_1_Pw_hi <= Voice_1_Pw_hi;
Voice_1_Control <= Voice_1_Control;
Voice_1_Att_dec <= Voice_1_Att_dec;
Voice_1_Sus_Rel <= Voice_1_Sus_Rel;
Voice_2_Freq_lo <= Voice_2_Freq_lo;
Voice_2_Freq_hi <= Voice_2_Freq_hi;
Voice_2_Pw_lo <= Voice_2_Pw_lo;
Voice_2_Pw_hi <= Voice_2_Pw_hi;
Voice_2_Control <= Voice_2_Control;
Voice_2_Att_dec <= Voice_2_Att_dec;
Voice_2_Sus_Rel <= Voice_2_Sus_Rel;
Voice_3_Freq_lo <= Voice_3_Freq_lo;
Voice_3_Freq_hi <= Voice_3_Freq_hi;
Voice_3_Pw_lo <= Voice_3_Pw_lo;
Voice_3_Pw_hi <= Voice_3_Pw_hi;
Voice_3_Control <= Voice_3_Control;
Voice_3_Att_dec <= Voice_3_Att_dec;
Voice_3_Sus_Rel <= Voice_3_Sus_Rel;
Filter_Fc_lo <= Filter_Fc_lo;
Filter_Fc_hi <= Filter_Fc_hi;
Filter_Res_Filt <= Filter_Res_Filt;
Filter_Mode_Vol <= Filter_Mode_Vol;
do_buf <= (others => '0');
if (cs='1') then
if (we='1') then -- Write to SID-register
------------------------
case addr is
-------------------------------------- Voice-1
when "00000" => Voice_1_Freq_lo <= di;
when "00001" => Voice_1_Freq_hi <= di;
when "00010" => Voice_1_Pw_lo <= di;
when "00011" => Voice_1_Pw_hi <= di(3 downto 0);
when "00100" => Voice_1_Control <= di;
when "00101" => Voice_1_Att_dec <= di;
when "00110" => Voice_1_Sus_Rel <= di;
--------------------------------------- Voice-2
when "00111" => Voice_2_Freq_lo <= di;
when "01000" => Voice_2_Freq_hi <= di;
when "01001" => Voice_2_Pw_lo <= di;
when "01010" => Voice_2_Pw_hi <= di(3 downto 0);
when "01011" => Voice_2_Control <= di;
when "01100" => Voice_2_Att_dec <= di;
when "01101" => Voice_2_Sus_Rel <= di;
--------------------------------------- Voice-3
when "01110" => Voice_3_Freq_lo <= di;
when "01111" => Voice_3_Freq_hi <= di;
when "10000" => Voice_3_Pw_lo <= di;
when "10001" => Voice_3_Pw_hi <= di(3 downto 0);
when "10010" => Voice_3_Control <= di;
when "10011" => Voice_3_Att_dec <= di;
when "10100" => Voice_3_Sus_Rel <= di;
--------------------------------------- Filter & volume
when "10101" => Filter_Fc_lo <= di;
when "10110" => Filter_Fc_hi <= di;
when "10111" => Filter_Res_Filt <= di;
when "11000" => Filter_Mode_Vol <= di;
--------------------------------------
when others => null;
end case;
else -- Read from SID-register
-------------------------
--case CONV_INTEGER(addr) is
case addr is
-------------------------------------- Misc
when "11001" => do_buf <= Misc_PotX;
when "11010" => do_buf <= Misc_PotY;
when "11011" => do_buf <= Misc_Osc3_Random;
when "11100" => do_buf <= Misc_Env3;
--------------------------------------
-- when others => null;
when others => do_buf <= (others => '0');
end case;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementation, use multiplexed channels
--
--
-- "The Filter was a classic multi-mode (state variable) VCF design. There was
-- no way to create a variable transconductance amplifier in our NMOS process,
-- so I simply used FETs as voltage-controlled resistors to control the cutoff
-- frequency. An 11-bit D/A converter generates the control voltage for the
-- FETs (it's actually a 12-bit D/A, but the LSB had no audible affect so I
-- disconnected it!)."
-- "Filter resonance was controlled by a 4-bit weighted resistor ladder. Each
-- bit would turn on one of the weighted resistors and allow a portion of the
-- output to feed back to the input. The state-variable design provided
-- simultaneous low-pass, band-pass and high-pass outputs. Analog switches
-- selected which combination of outputs were sent to the final amplifier (a
-- notch filter was created by enabling both the high and low-pass outputs
-- simultaneously)."
-- "The filter is the worst part of SID because I could not create high-gain
-- op-amps in NMOS, which were essential to a resonant filter. In addition,
-- the resistance of the FETs varied considerably with processing, so different
-- lots of SID chips had different cutoff frequency characteristics. I knew it
-- wouldn't work very well, but it was better than nothing and I didn't have
-- time to make it better."
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end sid6581;
architecture Behavioral of sid6581 is
--Implementation Digital to Analog converter
component pwm_sddac is
port (
clk_i : in std_logic; -- main clock signal, the higher the better
reset : in std_logic; -- reset input active high
dac_o : out std_logic; -- PWM output after a simple low-pass filter this is to be considered an analog signal
dac_i : in std_logic_vector(9 downto 0) -- binary input of signal to be converted
);
end component;
component pwm_sdadc is
port (
clk : in std_logic; -- main clock signal (actually the higher the better)
reset : in std_logic; --
ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted
ADC_in : in std_logic -- "analog" paddle input pin
);
end component;
-- Implementation of the SID voices (sound channels)
component sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); --
Freq_hi : in std_logic_vector(7 downto 0); --
Pw_lo : in std_logic_vector(7 downto 0); --
Pw_hi : in std_logic_vector(3 downto 0); --
Control : in std_logic_vector(7 downto 0); --
Att_dec : in std_logic_vector(7 downto 0); --
Sus_Rel : in std_logic_vector(7 downto 0); --
PA_MSB_in : in std_logic; --
PA_MSB_out : out std_logic; --
Osc : out std_logic_vector(7 downto 0); --
Env : out std_logic_vector(7 downto 0); --
voice : out std_logic_vector(11 downto 0) --
);
end component;
component sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end component;
-------------------------------------------------------------------------------
--constant <name>: <type> := <value>;
-- DC offset required to play samples, this is actually a bug of the real 6581,
-- that was converted into an advantage to play samples
constant DC_offset : std_logic_vector(13 downto 0) := "00111111111111";
-------------------------------------------------------------------------------
signal Voice_1_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_1_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_2_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_3_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Res_Filt : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Mode_Vol : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotX : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotY : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Osc3_Random : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Env3 : std_logic_vector(7 downto 0) := (others => '0');
signal do_buf : std_logic_vector(7 downto 0) := (others => '0');
signal voice_1 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_2 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_3 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_mixed : std_logic_vector(13 downto 0) := (others => '0');
signal voice_volume : std_logic_vector(35 downto 0) := (others => '0');
signal divide_0 : std_logic_vector(31 downto 0) := (others => '0');
signal voice_1_PA_MSB : std_logic := '0';
signal voice_2_PA_MSB : std_logic := '0';
signal voice_3_PA_MSB : std_logic := '0';
-------------------------------------------------------------------------------
begin
digital_to_analog: pwm_sddac
port map(
clk_i => clk_DAC,
reset => reset,
dac_i => voice_volume(17 downto 8),
dac_o => audio_out
);
paddle_x: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotX,
ADC_in => pot_x
);
paddle_y: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotY,
ADC_in => pot_y
);
sid_voice_1: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_1_Freq_lo,
Freq_hi => Voice_1_Freq_hi,
Pw_lo => Voice_1_Pw_lo,
Pw_hi => Voice_1_Pw_hi,
Control => Voice_1_Control,
Att_dec => Voice_1_Att_dec,
Sus_Rel => Voice_1_Sus_Rel,
PA_MSB_in => voice_3_PA_MSB,
PA_MSB_out => voice_1_PA_MSB,
Osc => Voice_1_Osc,
Env => Voice_1_Env,
voice => voice_1
);
sid_voice_2: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_2_Freq_lo,
Freq_hi => Voice_2_Freq_hi,
Pw_lo => Voice_2_Pw_lo,
Pw_hi => Voice_2_Pw_hi,
Control => Voice_2_Control,
Att_dec => Voice_2_Att_dec,
Sus_Rel => Voice_2_Sus_Rel,
PA_MSB_in => voice_1_PA_MSB,
PA_MSB_out => voice_2_PA_MSB,
Osc => Voice_2_Osc,
Env => Voice_2_Env,
voice => voice_2
);
sid_voice_3: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_3_Freq_lo,
Freq_hi => Voice_3_Freq_hi,
Pw_lo => Voice_3_Pw_lo,
Pw_hi => Voice_3_Pw_hi,
Control => Voice_3_Control,
Att_dec => Voice_3_Att_dec,
Sus_Rel => Voice_3_Sus_Rel,
PA_MSB_in => voice_2_PA_MSB,
PA_MSB_out => voice_3_PA_MSB,
Osc => Misc_Osc3_Random,
Env => Misc_Env3,
voice => voice_3
);
-------------------------------------------------------------------------------------
do <= do_buf;
-- SID filters
fblk: block
signal voice1_signed: signed(12 downto 0);
signal voice2_signed: signed(12 downto 0);
signal voice3_signed: signed(12 downto 0);
constant ext_in_signed: signed(12 downto 0) := to_signed(0,13);
signal filtered_audio: signed(18 downto 0);
signal tick_q1, tick_q2: std_logic;
signal input_valid: std_logic;
signal unsigned_audio: std_logic_vector(17 downto 0);
signal unsigned_filt: std_logic_vector(18 downto 0);
signal ff1: std_logic;
begin
process (clk_1MHz,reset)
begin
if reset='1' then
ff1<='0';
else
if rising_edge(clk_1MHz) then
ff1<=not ff1;
end if;
end if;
end process;
process(clk32)
begin
if rising_edge(clk32) then
tick_q1 <= ff1;
tick_q2 <= tick_q1;
end if;
end process;
input_valid<='1' when tick_q1 /=tick_q2 else '0';
voice1_signed <= signed(voice_1 & "0") - 4096;
voice2_signed <= signed(voice_2 & "0") - 4096;
voice3_signed <= signed(voice_3 & "0") - 4096;
filters: sid_filters
port map (
clk => clk32,
rst => reset,
-- SID registers.
Fc_lo => Filter_Fc_lo,
Fc_hi => Filter_Fc_hi,
Res_Filt => Filter_Res_Filt,
Mode_Vol => Filter_Mode_Vol,
-- Voices - resampled to 13 bit
voice1 => voice1_signed,
voice2 => voice2_signed,
voice3 => voice3_signed,
--
input_valid => input_valid,
ext_in => ext_in_signed,
sound => filtered_audio,
valid => open
);
unsigned_filt <= std_logic_vector(filtered_audio + "1000000000000000000");
unsigned_audio <= unsigned_filt(18 downto 1);
audio_data <= unsigned_audio;
end block;
-- Register decoding
register_decoder:process(clk32)
begin
if rising_edge(clk32) then
if (reset = '1') then
--------------------------------------- Voice-1
Voice_1_Freq_lo <= (others => '0');
Voice_1_Freq_hi <= (others => '0');
Voice_1_Pw_lo <= (others => '0');
Voice_1_Pw_hi <= (others => '0');
Voice_1_Control <= (others => '0');
Voice_1_Att_dec <= (others => '0');
Voice_1_Sus_Rel <= (others => '0');
--------------------------------------- Voice-2
Voice_2_Freq_lo <= (others => '0');
Voice_2_Freq_hi <= (others => '0');
Voice_2_Pw_lo <= (others => '0');
Voice_2_Pw_hi <= (others => '0');
Voice_2_Control <= (others => '0');
Voice_2_Att_dec <= (others => '0');
Voice_2_Sus_Rel <= (others => '0');
--------------------------------------- Voice-3
Voice_3_Freq_lo <= (others => '0');
Voice_3_Freq_hi <= (others => '0');
Voice_3_Pw_lo <= (others => '0');
Voice_3_Pw_hi <= (others => '0');
Voice_3_Control <= (others => '0');
Voice_3_Att_dec <= (others => '0');
Voice_3_Sus_Rel <= (others => '0');
--------------------------------------- Filter & volume
Filter_Fc_lo <= (others => '0');
Filter_Fc_hi <= (others => '0');
Filter_Res_Filt <= (others => '0');
Filter_Mode_Vol <= (others => '0');
else
Voice_1_Freq_lo <= Voice_1_Freq_lo;
Voice_1_Freq_hi <= Voice_1_Freq_hi;
Voice_1_Pw_lo <= Voice_1_Pw_lo;
Voice_1_Pw_hi <= Voice_1_Pw_hi;
Voice_1_Control <= Voice_1_Control;
Voice_1_Att_dec <= Voice_1_Att_dec;
Voice_1_Sus_Rel <= Voice_1_Sus_Rel;
Voice_2_Freq_lo <= Voice_2_Freq_lo;
Voice_2_Freq_hi <= Voice_2_Freq_hi;
Voice_2_Pw_lo <= Voice_2_Pw_lo;
Voice_2_Pw_hi <= Voice_2_Pw_hi;
Voice_2_Control <= Voice_2_Control;
Voice_2_Att_dec <= Voice_2_Att_dec;
Voice_2_Sus_Rel <= Voice_2_Sus_Rel;
Voice_3_Freq_lo <= Voice_3_Freq_lo;
Voice_3_Freq_hi <= Voice_3_Freq_hi;
Voice_3_Pw_lo <= Voice_3_Pw_lo;
Voice_3_Pw_hi <= Voice_3_Pw_hi;
Voice_3_Control <= Voice_3_Control;
Voice_3_Att_dec <= Voice_3_Att_dec;
Voice_3_Sus_Rel <= Voice_3_Sus_Rel;
Filter_Fc_lo <= Filter_Fc_lo;
Filter_Fc_hi <= Filter_Fc_hi;
Filter_Res_Filt <= Filter_Res_Filt;
Filter_Mode_Vol <= Filter_Mode_Vol;
do_buf <= (others => '0');
if (cs='1') then
if (we='1') then -- Write to SID-register
------------------------
case addr is
-------------------------------------- Voice-1
when "00000" => Voice_1_Freq_lo <= di;
when "00001" => Voice_1_Freq_hi <= di;
when "00010" => Voice_1_Pw_lo <= di;
when "00011" => Voice_1_Pw_hi <= di(3 downto 0);
when "00100" => Voice_1_Control <= di;
when "00101" => Voice_1_Att_dec <= di;
when "00110" => Voice_1_Sus_Rel <= di;
--------------------------------------- Voice-2
when "00111" => Voice_2_Freq_lo <= di;
when "01000" => Voice_2_Freq_hi <= di;
when "01001" => Voice_2_Pw_lo <= di;
when "01010" => Voice_2_Pw_hi <= di(3 downto 0);
when "01011" => Voice_2_Control <= di;
when "01100" => Voice_2_Att_dec <= di;
when "01101" => Voice_2_Sus_Rel <= di;
--------------------------------------- Voice-3
when "01110" => Voice_3_Freq_lo <= di;
when "01111" => Voice_3_Freq_hi <= di;
when "10000" => Voice_3_Pw_lo <= di;
when "10001" => Voice_3_Pw_hi <= di(3 downto 0);
when "10010" => Voice_3_Control <= di;
when "10011" => Voice_3_Att_dec <= di;
when "10100" => Voice_3_Sus_Rel <= di;
--------------------------------------- Filter & volume
when "10101" => Filter_Fc_lo <= di;
when "10110" => Filter_Fc_hi <= di;
when "10111" => Filter_Res_Filt <= di;
when "11000" => Filter_Mode_Vol <= di;
--------------------------------------
when others => null;
end case;
else -- Read from SID-register
-------------------------
--case CONV_INTEGER(addr) is
case addr is
-------------------------------------- Misc
when "11001" => do_buf <= Misc_PotX;
when "11010" => do_buf <= Misc_PotY;
when "11011" => do_buf <= Misc_Osc3_Random;
when "11100" => do_buf <= Misc_Env3;
--------------------------------------
-- when others => null;
when others => do_buf <= (others => '0');
end case;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementation, use multiplexed channels
--
--
-- "The Filter was a classic multi-mode (state variable) VCF design. There was
-- no way to create a variable transconductance amplifier in our NMOS process,
-- so I simply used FETs as voltage-controlled resistors to control the cutoff
-- frequency. An 11-bit D/A converter generates the control voltage for the
-- FETs (it's actually a 12-bit D/A, but the LSB had no audible affect so I
-- disconnected it!)."
-- "Filter resonance was controlled by a 4-bit weighted resistor ladder. Each
-- bit would turn on one of the weighted resistors and allow a portion of the
-- output to feed back to the input. The state-variable design provided
-- simultaneous low-pass, band-pass and high-pass outputs. Analog switches
-- selected which combination of outputs were sent to the final amplifier (a
-- notch filter was created by enabling both the high and low-pass outputs
-- simultaneously)."
-- "The filter is the worst part of SID because I could not create high-gain
-- op-amps in NMOS, which were essential to a resonant filter. In addition,
-- the resistance of the FETs varied considerably with processing, so different
-- lots of SID chips had different cutoff frequency characteristics. I knew it
-- wouldn't work very well, but it was better than nothing and I didn't have
-- time to make it better."
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end sid6581;
architecture Behavioral of sid6581 is
--Implementation Digital to Analog converter
component pwm_sddac is
port (
clk_i : in std_logic; -- main clock signal, the higher the better
reset : in std_logic; -- reset input active high
dac_o : out std_logic; -- PWM output after a simple low-pass filter this is to be considered an analog signal
dac_i : in std_logic_vector(9 downto 0) -- binary input of signal to be converted
);
end component;
component pwm_sdadc is
port (
clk : in std_logic; -- main clock signal (actually the higher the better)
reset : in std_logic; --
ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted
ADC_in : in std_logic -- "analog" paddle input pin
);
end component;
-- Implementation of the SID voices (sound channels)
component sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); --
Freq_hi : in std_logic_vector(7 downto 0); --
Pw_lo : in std_logic_vector(7 downto 0); --
Pw_hi : in std_logic_vector(3 downto 0); --
Control : in std_logic_vector(7 downto 0); --
Att_dec : in std_logic_vector(7 downto 0); --
Sus_Rel : in std_logic_vector(7 downto 0); --
PA_MSB_in : in std_logic; --
PA_MSB_out : out std_logic; --
Osc : out std_logic_vector(7 downto 0); --
Env : out std_logic_vector(7 downto 0); --
voice : out std_logic_vector(11 downto 0) --
);
end component;
component sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end component;
-------------------------------------------------------------------------------
--constant <name>: <type> := <value>;
-- DC offset required to play samples, this is actually a bug of the real 6581,
-- that was converted into an advantage to play samples
constant DC_offset : std_logic_vector(13 downto 0) := "00111111111111";
-------------------------------------------------------------------------------
signal Voice_1_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_1_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_2_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_3_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Res_Filt : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Mode_Vol : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotX : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotY : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Osc3_Random : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Env3 : std_logic_vector(7 downto 0) := (others => '0');
signal do_buf : std_logic_vector(7 downto 0) := (others => '0');
signal voice_1 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_2 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_3 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_mixed : std_logic_vector(13 downto 0) := (others => '0');
signal voice_volume : std_logic_vector(35 downto 0) := (others => '0');
signal divide_0 : std_logic_vector(31 downto 0) := (others => '0');
signal voice_1_PA_MSB : std_logic := '0';
signal voice_2_PA_MSB : std_logic := '0';
signal voice_3_PA_MSB : std_logic := '0';
-------------------------------------------------------------------------------
begin
digital_to_analog: pwm_sddac
port map(
clk_i => clk_DAC,
reset => reset,
dac_i => voice_volume(17 downto 8),
dac_o => audio_out
);
paddle_x: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotX,
ADC_in => pot_x
);
paddle_y: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotY,
ADC_in => pot_y
);
sid_voice_1: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_1_Freq_lo,
Freq_hi => Voice_1_Freq_hi,
Pw_lo => Voice_1_Pw_lo,
Pw_hi => Voice_1_Pw_hi,
Control => Voice_1_Control,
Att_dec => Voice_1_Att_dec,
Sus_Rel => Voice_1_Sus_Rel,
PA_MSB_in => voice_3_PA_MSB,
PA_MSB_out => voice_1_PA_MSB,
Osc => Voice_1_Osc,
Env => Voice_1_Env,
voice => voice_1
);
sid_voice_2: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_2_Freq_lo,
Freq_hi => Voice_2_Freq_hi,
Pw_lo => Voice_2_Pw_lo,
Pw_hi => Voice_2_Pw_hi,
Control => Voice_2_Control,
Att_dec => Voice_2_Att_dec,
Sus_Rel => Voice_2_Sus_Rel,
PA_MSB_in => voice_1_PA_MSB,
PA_MSB_out => voice_2_PA_MSB,
Osc => Voice_2_Osc,
Env => Voice_2_Env,
voice => voice_2
);
sid_voice_3: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_3_Freq_lo,
Freq_hi => Voice_3_Freq_hi,
Pw_lo => Voice_3_Pw_lo,
Pw_hi => Voice_3_Pw_hi,
Control => Voice_3_Control,
Att_dec => Voice_3_Att_dec,
Sus_Rel => Voice_3_Sus_Rel,
PA_MSB_in => voice_2_PA_MSB,
PA_MSB_out => voice_3_PA_MSB,
Osc => Misc_Osc3_Random,
Env => Misc_Env3,
voice => voice_3
);
-------------------------------------------------------------------------------------
do <= do_buf;
-- SID filters
fblk: block
signal voice1_signed: signed(12 downto 0);
signal voice2_signed: signed(12 downto 0);
signal voice3_signed: signed(12 downto 0);
constant ext_in_signed: signed(12 downto 0) := to_signed(0,13);
signal filtered_audio: signed(18 downto 0);
signal tick_q1, tick_q2: std_logic;
signal input_valid: std_logic;
signal unsigned_audio: std_logic_vector(17 downto 0);
signal unsigned_filt: std_logic_vector(18 downto 0);
signal ff1: std_logic;
begin
process (clk_1MHz,reset)
begin
if reset='1' then
ff1<='0';
else
if rising_edge(clk_1MHz) then
ff1<=not ff1;
end if;
end if;
end process;
process(clk32)
begin
if rising_edge(clk32) then
tick_q1 <= ff1;
tick_q2 <= tick_q1;
end if;
end process;
input_valid<='1' when tick_q1 /=tick_q2 else '0';
voice1_signed <= signed(voice_1 & "0") - 4096;
voice2_signed <= signed(voice_2 & "0") - 4096;
voice3_signed <= signed(voice_3 & "0") - 4096;
filters: sid_filters
port map (
clk => clk32,
rst => reset,
-- SID registers.
Fc_lo => Filter_Fc_lo,
Fc_hi => Filter_Fc_hi,
Res_Filt => Filter_Res_Filt,
Mode_Vol => Filter_Mode_Vol,
-- Voices - resampled to 13 bit
voice1 => voice1_signed,
voice2 => voice2_signed,
voice3 => voice3_signed,
--
input_valid => input_valid,
ext_in => ext_in_signed,
sound => filtered_audio,
valid => open
);
unsigned_filt <= std_logic_vector(filtered_audio + "1000000000000000000");
unsigned_audio <= unsigned_filt(18 downto 1);
audio_data <= unsigned_audio;
end block;
-- Register decoding
register_decoder:process(clk32)
begin
if rising_edge(clk32) then
if (reset = '1') then
--------------------------------------- Voice-1
Voice_1_Freq_lo <= (others => '0');
Voice_1_Freq_hi <= (others => '0');
Voice_1_Pw_lo <= (others => '0');
Voice_1_Pw_hi <= (others => '0');
Voice_1_Control <= (others => '0');
Voice_1_Att_dec <= (others => '0');
Voice_1_Sus_Rel <= (others => '0');
--------------------------------------- Voice-2
Voice_2_Freq_lo <= (others => '0');
Voice_2_Freq_hi <= (others => '0');
Voice_2_Pw_lo <= (others => '0');
Voice_2_Pw_hi <= (others => '0');
Voice_2_Control <= (others => '0');
Voice_2_Att_dec <= (others => '0');
Voice_2_Sus_Rel <= (others => '0');
--------------------------------------- Voice-3
Voice_3_Freq_lo <= (others => '0');
Voice_3_Freq_hi <= (others => '0');
Voice_3_Pw_lo <= (others => '0');
Voice_3_Pw_hi <= (others => '0');
Voice_3_Control <= (others => '0');
Voice_3_Att_dec <= (others => '0');
Voice_3_Sus_Rel <= (others => '0');
--------------------------------------- Filter & volume
Filter_Fc_lo <= (others => '0');
Filter_Fc_hi <= (others => '0');
Filter_Res_Filt <= (others => '0');
Filter_Mode_Vol <= (others => '0');
else
Voice_1_Freq_lo <= Voice_1_Freq_lo;
Voice_1_Freq_hi <= Voice_1_Freq_hi;
Voice_1_Pw_lo <= Voice_1_Pw_lo;
Voice_1_Pw_hi <= Voice_1_Pw_hi;
Voice_1_Control <= Voice_1_Control;
Voice_1_Att_dec <= Voice_1_Att_dec;
Voice_1_Sus_Rel <= Voice_1_Sus_Rel;
Voice_2_Freq_lo <= Voice_2_Freq_lo;
Voice_2_Freq_hi <= Voice_2_Freq_hi;
Voice_2_Pw_lo <= Voice_2_Pw_lo;
Voice_2_Pw_hi <= Voice_2_Pw_hi;
Voice_2_Control <= Voice_2_Control;
Voice_2_Att_dec <= Voice_2_Att_dec;
Voice_2_Sus_Rel <= Voice_2_Sus_Rel;
Voice_3_Freq_lo <= Voice_3_Freq_lo;
Voice_3_Freq_hi <= Voice_3_Freq_hi;
Voice_3_Pw_lo <= Voice_3_Pw_lo;
Voice_3_Pw_hi <= Voice_3_Pw_hi;
Voice_3_Control <= Voice_3_Control;
Voice_3_Att_dec <= Voice_3_Att_dec;
Voice_3_Sus_Rel <= Voice_3_Sus_Rel;
Filter_Fc_lo <= Filter_Fc_lo;
Filter_Fc_hi <= Filter_Fc_hi;
Filter_Res_Filt <= Filter_Res_Filt;
Filter_Mode_Vol <= Filter_Mode_Vol;
do_buf <= (others => '0');
if (cs='1') then
if (we='1') then -- Write to SID-register
------------------------
case addr is
-------------------------------------- Voice-1
when "00000" => Voice_1_Freq_lo <= di;
when "00001" => Voice_1_Freq_hi <= di;
when "00010" => Voice_1_Pw_lo <= di;
when "00011" => Voice_1_Pw_hi <= di(3 downto 0);
when "00100" => Voice_1_Control <= di;
when "00101" => Voice_1_Att_dec <= di;
when "00110" => Voice_1_Sus_Rel <= di;
--------------------------------------- Voice-2
when "00111" => Voice_2_Freq_lo <= di;
when "01000" => Voice_2_Freq_hi <= di;
when "01001" => Voice_2_Pw_lo <= di;
when "01010" => Voice_2_Pw_hi <= di(3 downto 0);
when "01011" => Voice_2_Control <= di;
when "01100" => Voice_2_Att_dec <= di;
when "01101" => Voice_2_Sus_Rel <= di;
--------------------------------------- Voice-3
when "01110" => Voice_3_Freq_lo <= di;
when "01111" => Voice_3_Freq_hi <= di;
when "10000" => Voice_3_Pw_lo <= di;
when "10001" => Voice_3_Pw_hi <= di(3 downto 0);
when "10010" => Voice_3_Control <= di;
when "10011" => Voice_3_Att_dec <= di;
when "10100" => Voice_3_Sus_Rel <= di;
--------------------------------------- Filter & volume
when "10101" => Filter_Fc_lo <= di;
when "10110" => Filter_Fc_hi <= di;
when "10111" => Filter_Res_Filt <= di;
when "11000" => Filter_Mode_Vol <= di;
--------------------------------------
when others => null;
end case;
else -- Read from SID-register
-------------------------
--case CONV_INTEGER(addr) is
case addr is
-------------------------------------- Misc
when "11001" => do_buf <= Misc_PotX;
when "11010" => do_buf <= Misc_PotY;
when "11011" => do_buf <= Misc_Osc3_Random;
when "11100" => do_buf <= Misc_Env3;
--------------------------------------
-- when others => null;
when others => do_buf <= (others => '0');
end case;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementation, use multiplexed channels
--
--
-- "The Filter was a classic multi-mode (state variable) VCF design. There was
-- no way to create a variable transconductance amplifier in our NMOS process,
-- so I simply used FETs as voltage-controlled resistors to control the cutoff
-- frequency. An 11-bit D/A converter generates the control voltage for the
-- FETs (it's actually a 12-bit D/A, but the LSB had no audible affect so I
-- disconnected it!)."
-- "Filter resonance was controlled by a 4-bit weighted resistor ladder. Each
-- bit would turn on one of the weighted resistors and allow a portion of the
-- output to feed back to the input. The state-variable design provided
-- simultaneous low-pass, band-pass and high-pass outputs. Analog switches
-- selected which combination of outputs were sent to the final amplifier (a
-- notch filter was created by enabling both the high and low-pass outputs
-- simultaneously)."
-- "The filter is the worst part of SID because I could not create high-gain
-- op-amps in NMOS, which were essential to a resonant filter. In addition,
-- the resistance of the FETs varied considerably with processing, so different
-- lots of SID chips had different cutoff frequency characteristics. I knew it
-- wouldn't work very well, but it was better than nothing and I didn't have
-- time to make it better."
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end sid6581;
architecture Behavioral of sid6581 is
--Implementation Digital to Analog converter
component pwm_sddac is
port (
clk_i : in std_logic; -- main clock signal, the higher the better
reset : in std_logic; -- reset input active high
dac_o : out std_logic; -- PWM output after a simple low-pass filter this is to be considered an analog signal
dac_i : in std_logic_vector(9 downto 0) -- binary input of signal to be converted
);
end component;
component pwm_sdadc is
port (
clk : in std_logic; -- main clock signal (actually the higher the better)
reset : in std_logic; --
ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted
ADC_in : in std_logic -- "analog" paddle input pin
);
end component;
-- Implementation of the SID voices (sound channels)
component sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); --
Freq_hi : in std_logic_vector(7 downto 0); --
Pw_lo : in std_logic_vector(7 downto 0); --
Pw_hi : in std_logic_vector(3 downto 0); --
Control : in std_logic_vector(7 downto 0); --
Att_dec : in std_logic_vector(7 downto 0); --
Sus_Rel : in std_logic_vector(7 downto 0); --
PA_MSB_in : in std_logic; --
PA_MSB_out : out std_logic; --
Osc : out std_logic_vector(7 downto 0); --
Env : out std_logic_vector(7 downto 0); --
voice : out std_logic_vector(11 downto 0) --
);
end component;
component sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end component;
-------------------------------------------------------------------------------
--constant <name>: <type> := <value>;
-- DC offset required to play samples, this is actually a bug of the real 6581,
-- that was converted into an advantage to play samples
constant DC_offset : std_logic_vector(13 downto 0) := "00111111111111";
-------------------------------------------------------------------------------
signal Voice_1_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_1_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_2_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_3_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Res_Filt : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Mode_Vol : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotX : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotY : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Osc3_Random : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Env3 : std_logic_vector(7 downto 0) := (others => '0');
signal do_buf : std_logic_vector(7 downto 0) := (others => '0');
signal voice_1 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_2 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_3 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_mixed : std_logic_vector(13 downto 0) := (others => '0');
signal voice_volume : std_logic_vector(35 downto 0) := (others => '0');
signal divide_0 : std_logic_vector(31 downto 0) := (others => '0');
signal voice_1_PA_MSB : std_logic := '0';
signal voice_2_PA_MSB : std_logic := '0';
signal voice_3_PA_MSB : std_logic := '0';
-------------------------------------------------------------------------------
begin
digital_to_analog: pwm_sddac
port map(
clk_i => clk_DAC,
reset => reset,
dac_i => voice_volume(17 downto 8),
dac_o => audio_out
);
paddle_x: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotX,
ADC_in => pot_x
);
paddle_y: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotY,
ADC_in => pot_y
);
sid_voice_1: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_1_Freq_lo,
Freq_hi => Voice_1_Freq_hi,
Pw_lo => Voice_1_Pw_lo,
Pw_hi => Voice_1_Pw_hi,
Control => Voice_1_Control,
Att_dec => Voice_1_Att_dec,
Sus_Rel => Voice_1_Sus_Rel,
PA_MSB_in => voice_3_PA_MSB,
PA_MSB_out => voice_1_PA_MSB,
Osc => Voice_1_Osc,
Env => Voice_1_Env,
voice => voice_1
);
sid_voice_2: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_2_Freq_lo,
Freq_hi => Voice_2_Freq_hi,
Pw_lo => Voice_2_Pw_lo,
Pw_hi => Voice_2_Pw_hi,
Control => Voice_2_Control,
Att_dec => Voice_2_Att_dec,
Sus_Rel => Voice_2_Sus_Rel,
PA_MSB_in => voice_1_PA_MSB,
PA_MSB_out => voice_2_PA_MSB,
Osc => Voice_2_Osc,
Env => Voice_2_Env,
voice => voice_2
);
sid_voice_3: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_3_Freq_lo,
Freq_hi => Voice_3_Freq_hi,
Pw_lo => Voice_3_Pw_lo,
Pw_hi => Voice_3_Pw_hi,
Control => Voice_3_Control,
Att_dec => Voice_3_Att_dec,
Sus_Rel => Voice_3_Sus_Rel,
PA_MSB_in => voice_2_PA_MSB,
PA_MSB_out => voice_3_PA_MSB,
Osc => Misc_Osc3_Random,
Env => Misc_Env3,
voice => voice_3
);
-------------------------------------------------------------------------------------
do <= do_buf;
-- SID filters
fblk: block
signal voice1_signed: signed(12 downto 0);
signal voice2_signed: signed(12 downto 0);
signal voice3_signed: signed(12 downto 0);
constant ext_in_signed: signed(12 downto 0) := to_signed(0,13);
signal filtered_audio: signed(18 downto 0);
signal tick_q1, tick_q2: std_logic;
signal input_valid: std_logic;
signal unsigned_audio: std_logic_vector(17 downto 0);
signal unsigned_filt: std_logic_vector(18 downto 0);
signal ff1: std_logic;
begin
process (clk_1MHz,reset)
begin
if reset='1' then
ff1<='0';
else
if rising_edge(clk_1MHz) then
ff1<=not ff1;
end if;
end if;
end process;
process(clk32)
begin
if rising_edge(clk32) then
tick_q1 <= ff1;
tick_q2 <= tick_q1;
end if;
end process;
input_valid<='1' when tick_q1 /=tick_q2 else '0';
voice1_signed <= signed(voice_1 & "0") - 4096;
voice2_signed <= signed(voice_2 & "0") - 4096;
voice3_signed <= signed(voice_3 & "0") - 4096;
filters: sid_filters
port map (
clk => clk32,
rst => reset,
-- SID registers.
Fc_lo => Filter_Fc_lo,
Fc_hi => Filter_Fc_hi,
Res_Filt => Filter_Res_Filt,
Mode_Vol => Filter_Mode_Vol,
-- Voices - resampled to 13 bit
voice1 => voice1_signed,
voice2 => voice2_signed,
voice3 => voice3_signed,
--
input_valid => input_valid,
ext_in => ext_in_signed,
sound => filtered_audio,
valid => open
);
unsigned_filt <= std_logic_vector(filtered_audio + "1000000000000000000");
unsigned_audio <= unsigned_filt(18 downto 1);
audio_data <= unsigned_audio;
end block;
-- Register decoding
register_decoder:process(clk32)
begin
if rising_edge(clk32) then
if (reset = '1') then
--------------------------------------- Voice-1
Voice_1_Freq_lo <= (others => '0');
Voice_1_Freq_hi <= (others => '0');
Voice_1_Pw_lo <= (others => '0');
Voice_1_Pw_hi <= (others => '0');
Voice_1_Control <= (others => '0');
Voice_1_Att_dec <= (others => '0');
Voice_1_Sus_Rel <= (others => '0');
--------------------------------------- Voice-2
Voice_2_Freq_lo <= (others => '0');
Voice_2_Freq_hi <= (others => '0');
Voice_2_Pw_lo <= (others => '0');
Voice_2_Pw_hi <= (others => '0');
Voice_2_Control <= (others => '0');
Voice_2_Att_dec <= (others => '0');
Voice_2_Sus_Rel <= (others => '0');
--------------------------------------- Voice-3
Voice_3_Freq_lo <= (others => '0');
Voice_3_Freq_hi <= (others => '0');
Voice_3_Pw_lo <= (others => '0');
Voice_3_Pw_hi <= (others => '0');
Voice_3_Control <= (others => '0');
Voice_3_Att_dec <= (others => '0');
Voice_3_Sus_Rel <= (others => '0');
--------------------------------------- Filter & volume
Filter_Fc_lo <= (others => '0');
Filter_Fc_hi <= (others => '0');
Filter_Res_Filt <= (others => '0');
Filter_Mode_Vol <= (others => '0');
else
Voice_1_Freq_lo <= Voice_1_Freq_lo;
Voice_1_Freq_hi <= Voice_1_Freq_hi;
Voice_1_Pw_lo <= Voice_1_Pw_lo;
Voice_1_Pw_hi <= Voice_1_Pw_hi;
Voice_1_Control <= Voice_1_Control;
Voice_1_Att_dec <= Voice_1_Att_dec;
Voice_1_Sus_Rel <= Voice_1_Sus_Rel;
Voice_2_Freq_lo <= Voice_2_Freq_lo;
Voice_2_Freq_hi <= Voice_2_Freq_hi;
Voice_2_Pw_lo <= Voice_2_Pw_lo;
Voice_2_Pw_hi <= Voice_2_Pw_hi;
Voice_2_Control <= Voice_2_Control;
Voice_2_Att_dec <= Voice_2_Att_dec;
Voice_2_Sus_Rel <= Voice_2_Sus_Rel;
Voice_3_Freq_lo <= Voice_3_Freq_lo;
Voice_3_Freq_hi <= Voice_3_Freq_hi;
Voice_3_Pw_lo <= Voice_3_Pw_lo;
Voice_3_Pw_hi <= Voice_3_Pw_hi;
Voice_3_Control <= Voice_3_Control;
Voice_3_Att_dec <= Voice_3_Att_dec;
Voice_3_Sus_Rel <= Voice_3_Sus_Rel;
Filter_Fc_lo <= Filter_Fc_lo;
Filter_Fc_hi <= Filter_Fc_hi;
Filter_Res_Filt <= Filter_Res_Filt;
Filter_Mode_Vol <= Filter_Mode_Vol;
do_buf <= (others => '0');
if (cs='1') then
if (we='1') then -- Write to SID-register
------------------------
case addr is
-------------------------------------- Voice-1
when "00000" => Voice_1_Freq_lo <= di;
when "00001" => Voice_1_Freq_hi <= di;
when "00010" => Voice_1_Pw_lo <= di;
when "00011" => Voice_1_Pw_hi <= di(3 downto 0);
when "00100" => Voice_1_Control <= di;
when "00101" => Voice_1_Att_dec <= di;
when "00110" => Voice_1_Sus_Rel <= di;
--------------------------------------- Voice-2
when "00111" => Voice_2_Freq_lo <= di;
when "01000" => Voice_2_Freq_hi <= di;
when "01001" => Voice_2_Pw_lo <= di;
when "01010" => Voice_2_Pw_hi <= di(3 downto 0);
when "01011" => Voice_2_Control <= di;
when "01100" => Voice_2_Att_dec <= di;
when "01101" => Voice_2_Sus_Rel <= di;
--------------------------------------- Voice-3
when "01110" => Voice_3_Freq_lo <= di;
when "01111" => Voice_3_Freq_hi <= di;
when "10000" => Voice_3_Pw_lo <= di;
when "10001" => Voice_3_Pw_hi <= di(3 downto 0);
when "10010" => Voice_3_Control <= di;
when "10011" => Voice_3_Att_dec <= di;
when "10100" => Voice_3_Sus_Rel <= di;
--------------------------------------- Filter & volume
when "10101" => Filter_Fc_lo <= di;
when "10110" => Filter_Fc_hi <= di;
when "10111" => Filter_Res_Filt <= di;
when "11000" => Filter_Mode_Vol <= di;
--------------------------------------
when others => null;
end case;
else -- Read from SID-register
-------------------------
--case CONV_INTEGER(addr) is
case addr is
-------------------------------------- Misc
when "11001" => do_buf <= Misc_PotX;
when "11010" => do_buf <= Misc_PotY;
when "11011" => do_buf <= Misc_Osc3_Random;
when "11100" => do_buf <= Misc_Env3;
--------------------------------------
-- when others => null;
when others => do_buf <= (others => '0');
end case;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementation, use multiplexed channels
--
--
-- "The Filter was a classic multi-mode (state variable) VCF design. There was
-- no way to create a variable transconductance amplifier in our NMOS process,
-- so I simply used FETs as voltage-controlled resistors to control the cutoff
-- frequency. An 11-bit D/A converter generates the control voltage for the
-- FETs (it's actually a 12-bit D/A, but the LSB had no audible affect so I
-- disconnected it!)."
-- "Filter resonance was controlled by a 4-bit weighted resistor ladder. Each
-- bit would turn on one of the weighted resistors and allow a portion of the
-- output to feed back to the input. The state-variable design provided
-- simultaneous low-pass, band-pass and high-pass outputs. Analog switches
-- selected which combination of outputs were sent to the final amplifier (a
-- notch filter was created by enabling both the high and low-pass outputs
-- simultaneously)."
-- "The filter is the worst part of SID because I could not create high-gain
-- op-amps in NMOS, which were essential to a resonant filter. In addition,
-- the resistance of the FETs varied considerably with processing, so different
-- lots of SID chips had different cutoff frequency characteristics. I knew it
-- wouldn't work very well, but it was better than nothing and I didn't have
-- time to make it better."
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end sid6581;
architecture Behavioral of sid6581 is
--Implementation Digital to Analog converter
component pwm_sddac is
port (
clk_i : in std_logic; -- main clock signal, the higher the better
reset : in std_logic; -- reset input active high
dac_o : out std_logic; -- PWM output after a simple low-pass filter this is to be considered an analog signal
dac_i : in std_logic_vector(9 downto 0) -- binary input of signal to be converted
);
end component;
component pwm_sdadc is
port (
clk : in std_logic; -- main clock signal (actually the higher the better)
reset : in std_logic; --
ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted
ADC_in : in std_logic -- "analog" paddle input pin
);
end component;
-- Implementation of the SID voices (sound channels)
component sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); --
Freq_hi : in std_logic_vector(7 downto 0); --
Pw_lo : in std_logic_vector(7 downto 0); --
Pw_hi : in std_logic_vector(3 downto 0); --
Control : in std_logic_vector(7 downto 0); --
Att_dec : in std_logic_vector(7 downto 0); --
Sus_Rel : in std_logic_vector(7 downto 0); --
PA_MSB_in : in std_logic; --
PA_MSB_out : out std_logic; --
Osc : out std_logic_vector(7 downto 0); --
Env : out std_logic_vector(7 downto 0); --
voice : out std_logic_vector(11 downto 0) --
);
end component;
component sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end component;
-------------------------------------------------------------------------------
--constant <name>: <type> := <value>;
-- DC offset required to play samples, this is actually a bug of the real 6581,
-- that was converted into an advantage to play samples
constant DC_offset : std_logic_vector(13 downto 0) := "00111111111111";
-------------------------------------------------------------------------------
signal Voice_1_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_1_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_2_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_3_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Res_Filt : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Mode_Vol : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotX : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotY : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Osc3_Random : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Env3 : std_logic_vector(7 downto 0) := (others => '0');
signal do_buf : std_logic_vector(7 downto 0) := (others => '0');
signal voice_1 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_2 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_3 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_mixed : std_logic_vector(13 downto 0) := (others => '0');
signal voice_volume : std_logic_vector(35 downto 0) := (others => '0');
signal divide_0 : std_logic_vector(31 downto 0) := (others => '0');
signal voice_1_PA_MSB : std_logic := '0';
signal voice_2_PA_MSB : std_logic := '0';
signal voice_3_PA_MSB : std_logic := '0';
-------------------------------------------------------------------------------
begin
digital_to_analog: pwm_sddac
port map(
clk_i => clk_DAC,
reset => reset,
dac_i => voice_volume(17 downto 8),
dac_o => audio_out
);
paddle_x: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotX,
ADC_in => pot_x
);
paddle_y: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotY,
ADC_in => pot_y
);
sid_voice_1: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_1_Freq_lo,
Freq_hi => Voice_1_Freq_hi,
Pw_lo => Voice_1_Pw_lo,
Pw_hi => Voice_1_Pw_hi,
Control => Voice_1_Control,
Att_dec => Voice_1_Att_dec,
Sus_Rel => Voice_1_Sus_Rel,
PA_MSB_in => voice_3_PA_MSB,
PA_MSB_out => voice_1_PA_MSB,
Osc => Voice_1_Osc,
Env => Voice_1_Env,
voice => voice_1
);
sid_voice_2: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_2_Freq_lo,
Freq_hi => Voice_2_Freq_hi,
Pw_lo => Voice_2_Pw_lo,
Pw_hi => Voice_2_Pw_hi,
Control => Voice_2_Control,
Att_dec => Voice_2_Att_dec,
Sus_Rel => Voice_2_Sus_Rel,
PA_MSB_in => voice_1_PA_MSB,
PA_MSB_out => voice_2_PA_MSB,
Osc => Voice_2_Osc,
Env => Voice_2_Env,
voice => voice_2
);
sid_voice_3: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_3_Freq_lo,
Freq_hi => Voice_3_Freq_hi,
Pw_lo => Voice_3_Pw_lo,
Pw_hi => Voice_3_Pw_hi,
Control => Voice_3_Control,
Att_dec => Voice_3_Att_dec,
Sus_Rel => Voice_3_Sus_Rel,
PA_MSB_in => voice_2_PA_MSB,
PA_MSB_out => voice_3_PA_MSB,
Osc => Misc_Osc3_Random,
Env => Misc_Env3,
voice => voice_3
);
-------------------------------------------------------------------------------------
do <= do_buf;
-- SID filters
fblk: block
signal voice1_signed: signed(12 downto 0);
signal voice2_signed: signed(12 downto 0);
signal voice3_signed: signed(12 downto 0);
constant ext_in_signed: signed(12 downto 0) := to_signed(0,13);
signal filtered_audio: signed(18 downto 0);
signal tick_q1, tick_q2: std_logic;
signal input_valid: std_logic;
signal unsigned_audio: std_logic_vector(17 downto 0);
signal unsigned_filt: std_logic_vector(18 downto 0);
signal ff1: std_logic;
begin
process (clk_1MHz,reset)
begin
if reset='1' then
ff1<='0';
else
if rising_edge(clk_1MHz) then
ff1<=not ff1;
end if;
end if;
end process;
process(clk32)
begin
if rising_edge(clk32) then
tick_q1 <= ff1;
tick_q2 <= tick_q1;
end if;
end process;
input_valid<='1' when tick_q1 /=tick_q2 else '0';
voice1_signed <= signed(voice_1 & "0") - 4096;
voice2_signed <= signed(voice_2 & "0") - 4096;
voice3_signed <= signed(voice_3 & "0") - 4096;
filters: sid_filters
port map (
clk => clk32,
rst => reset,
-- SID registers.
Fc_lo => Filter_Fc_lo,
Fc_hi => Filter_Fc_hi,
Res_Filt => Filter_Res_Filt,
Mode_Vol => Filter_Mode_Vol,
-- Voices - resampled to 13 bit
voice1 => voice1_signed,
voice2 => voice2_signed,
voice3 => voice3_signed,
--
input_valid => input_valid,
ext_in => ext_in_signed,
sound => filtered_audio,
valid => open
);
unsigned_filt <= std_logic_vector(filtered_audio + "1000000000000000000");
unsigned_audio <= unsigned_filt(18 downto 1);
audio_data <= unsigned_audio;
end block;
-- Register decoding
register_decoder:process(clk32)
begin
if rising_edge(clk32) then
if (reset = '1') then
--------------------------------------- Voice-1
Voice_1_Freq_lo <= (others => '0');
Voice_1_Freq_hi <= (others => '0');
Voice_1_Pw_lo <= (others => '0');
Voice_1_Pw_hi <= (others => '0');
Voice_1_Control <= (others => '0');
Voice_1_Att_dec <= (others => '0');
Voice_1_Sus_Rel <= (others => '0');
--------------------------------------- Voice-2
Voice_2_Freq_lo <= (others => '0');
Voice_2_Freq_hi <= (others => '0');
Voice_2_Pw_lo <= (others => '0');
Voice_2_Pw_hi <= (others => '0');
Voice_2_Control <= (others => '0');
Voice_2_Att_dec <= (others => '0');
Voice_2_Sus_Rel <= (others => '0');
--------------------------------------- Voice-3
Voice_3_Freq_lo <= (others => '0');
Voice_3_Freq_hi <= (others => '0');
Voice_3_Pw_lo <= (others => '0');
Voice_3_Pw_hi <= (others => '0');
Voice_3_Control <= (others => '0');
Voice_3_Att_dec <= (others => '0');
Voice_3_Sus_Rel <= (others => '0');
--------------------------------------- Filter & volume
Filter_Fc_lo <= (others => '0');
Filter_Fc_hi <= (others => '0');
Filter_Res_Filt <= (others => '0');
Filter_Mode_Vol <= (others => '0');
else
Voice_1_Freq_lo <= Voice_1_Freq_lo;
Voice_1_Freq_hi <= Voice_1_Freq_hi;
Voice_1_Pw_lo <= Voice_1_Pw_lo;
Voice_1_Pw_hi <= Voice_1_Pw_hi;
Voice_1_Control <= Voice_1_Control;
Voice_1_Att_dec <= Voice_1_Att_dec;
Voice_1_Sus_Rel <= Voice_1_Sus_Rel;
Voice_2_Freq_lo <= Voice_2_Freq_lo;
Voice_2_Freq_hi <= Voice_2_Freq_hi;
Voice_2_Pw_lo <= Voice_2_Pw_lo;
Voice_2_Pw_hi <= Voice_2_Pw_hi;
Voice_2_Control <= Voice_2_Control;
Voice_2_Att_dec <= Voice_2_Att_dec;
Voice_2_Sus_Rel <= Voice_2_Sus_Rel;
Voice_3_Freq_lo <= Voice_3_Freq_lo;
Voice_3_Freq_hi <= Voice_3_Freq_hi;
Voice_3_Pw_lo <= Voice_3_Pw_lo;
Voice_3_Pw_hi <= Voice_3_Pw_hi;
Voice_3_Control <= Voice_3_Control;
Voice_3_Att_dec <= Voice_3_Att_dec;
Voice_3_Sus_Rel <= Voice_3_Sus_Rel;
Filter_Fc_lo <= Filter_Fc_lo;
Filter_Fc_hi <= Filter_Fc_hi;
Filter_Res_Filt <= Filter_Res_Filt;
Filter_Mode_Vol <= Filter_Mode_Vol;
do_buf <= (others => '0');
if (cs='1') then
if (we='1') then -- Write to SID-register
------------------------
case addr is
-------------------------------------- Voice-1
when "00000" => Voice_1_Freq_lo <= di;
when "00001" => Voice_1_Freq_hi <= di;
when "00010" => Voice_1_Pw_lo <= di;
when "00011" => Voice_1_Pw_hi <= di(3 downto 0);
when "00100" => Voice_1_Control <= di;
when "00101" => Voice_1_Att_dec <= di;
when "00110" => Voice_1_Sus_Rel <= di;
--------------------------------------- Voice-2
when "00111" => Voice_2_Freq_lo <= di;
when "01000" => Voice_2_Freq_hi <= di;
when "01001" => Voice_2_Pw_lo <= di;
when "01010" => Voice_2_Pw_hi <= di(3 downto 0);
when "01011" => Voice_2_Control <= di;
when "01100" => Voice_2_Att_dec <= di;
when "01101" => Voice_2_Sus_Rel <= di;
--------------------------------------- Voice-3
when "01110" => Voice_3_Freq_lo <= di;
when "01111" => Voice_3_Freq_hi <= di;
when "10000" => Voice_3_Pw_lo <= di;
when "10001" => Voice_3_Pw_hi <= di(3 downto 0);
when "10010" => Voice_3_Control <= di;
when "10011" => Voice_3_Att_dec <= di;
when "10100" => Voice_3_Sus_Rel <= di;
--------------------------------------- Filter & volume
when "10101" => Filter_Fc_lo <= di;
when "10110" => Filter_Fc_hi <= di;
when "10111" => Filter_Res_Filt <= di;
when "11000" => Filter_Mode_Vol <= di;
--------------------------------------
when others => null;
end case;
else -- Read from SID-register
-------------------------
--case CONV_INTEGER(addr) is
case addr is
-------------------------------------- Misc
when "11001" => do_buf <= Misc_PotX;
when "11010" => do_buf <= Misc_PotY;
when "11011" => do_buf <= Misc_Osc3_Random;
when "11100" => do_buf <= Misc_Env3;
--------------------------------------
-- when others => null;
when others => do_buf <= (others => '0');
end case;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementation, use multiplexed channels
--
--
-- "The Filter was a classic multi-mode (state variable) VCF design. There was
-- no way to create a variable transconductance amplifier in our NMOS process,
-- so I simply used FETs as voltage-controlled resistors to control the cutoff
-- frequency. An 11-bit D/A converter generates the control voltage for the
-- FETs (it's actually a 12-bit D/A, but the LSB had no audible affect so I
-- disconnected it!)."
-- "Filter resonance was controlled by a 4-bit weighted resistor ladder. Each
-- bit would turn on one of the weighted resistors and allow a portion of the
-- output to feed back to the input. The state-variable design provided
-- simultaneous low-pass, band-pass and high-pass outputs. Analog switches
-- selected which combination of outputs were sent to the final amplifier (a
-- notch filter was created by enabling both the high and low-pass outputs
-- simultaneously)."
-- "The filter is the worst part of SID because I could not create high-gain
-- op-amps in NMOS, which were essential to a resonant filter. In addition,
-- the resistance of the FETs varied considerably with processing, so different
-- lots of SID chips had different cutoff frequency characteristics. I knew it
-- wouldn't work very well, but it was better than nothing and I didn't have
-- time to make it better."
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end sid6581;
architecture Behavioral of sid6581 is
--Implementation Digital to Analog converter
component pwm_sddac is
port (
clk_i : in std_logic; -- main clock signal, the higher the better
reset : in std_logic; -- reset input active high
dac_o : out std_logic; -- PWM output after a simple low-pass filter this is to be considered an analog signal
dac_i : in std_logic_vector(9 downto 0) -- binary input of signal to be converted
);
end component;
component pwm_sdadc is
port (
clk : in std_logic; -- main clock signal (actually the higher the better)
reset : in std_logic; --
ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted
ADC_in : in std_logic -- "analog" paddle input pin
);
end component;
-- Implementation of the SID voices (sound channels)
component sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); --
Freq_hi : in std_logic_vector(7 downto 0); --
Pw_lo : in std_logic_vector(7 downto 0); --
Pw_hi : in std_logic_vector(3 downto 0); --
Control : in std_logic_vector(7 downto 0); --
Att_dec : in std_logic_vector(7 downto 0); --
Sus_Rel : in std_logic_vector(7 downto 0); --
PA_MSB_in : in std_logic; --
PA_MSB_out : out std_logic; --
Osc : out std_logic_vector(7 downto 0); --
Env : out std_logic_vector(7 downto 0); --
voice : out std_logic_vector(11 downto 0) --
);
end component;
component sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end component;
-------------------------------------------------------------------------------
--constant <name>: <type> := <value>;
-- DC offset required to play samples, this is actually a bug of the real 6581,
-- that was converted into an advantage to play samples
constant DC_offset : std_logic_vector(13 downto 0) := "00111111111111";
-------------------------------------------------------------------------------
signal Voice_1_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_1_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_2_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_3_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Res_Filt : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Mode_Vol : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotX : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotY : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Osc3_Random : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Env3 : std_logic_vector(7 downto 0) := (others => '0');
signal do_buf : std_logic_vector(7 downto 0) := (others => '0');
signal voice_1 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_2 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_3 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_mixed : std_logic_vector(13 downto 0) := (others => '0');
signal voice_volume : std_logic_vector(35 downto 0) := (others => '0');
signal divide_0 : std_logic_vector(31 downto 0) := (others => '0');
signal voice_1_PA_MSB : std_logic := '0';
signal voice_2_PA_MSB : std_logic := '0';
signal voice_3_PA_MSB : std_logic := '0';
-------------------------------------------------------------------------------
begin
digital_to_analog: pwm_sddac
port map(
clk_i => clk_DAC,
reset => reset,
dac_i => voice_volume(17 downto 8),
dac_o => audio_out
);
paddle_x: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotX,
ADC_in => pot_x
);
paddle_y: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotY,
ADC_in => pot_y
);
sid_voice_1: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_1_Freq_lo,
Freq_hi => Voice_1_Freq_hi,
Pw_lo => Voice_1_Pw_lo,
Pw_hi => Voice_1_Pw_hi,
Control => Voice_1_Control,
Att_dec => Voice_1_Att_dec,
Sus_Rel => Voice_1_Sus_Rel,
PA_MSB_in => voice_3_PA_MSB,
PA_MSB_out => voice_1_PA_MSB,
Osc => Voice_1_Osc,
Env => Voice_1_Env,
voice => voice_1
);
sid_voice_2: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_2_Freq_lo,
Freq_hi => Voice_2_Freq_hi,
Pw_lo => Voice_2_Pw_lo,
Pw_hi => Voice_2_Pw_hi,
Control => Voice_2_Control,
Att_dec => Voice_2_Att_dec,
Sus_Rel => Voice_2_Sus_Rel,
PA_MSB_in => voice_1_PA_MSB,
PA_MSB_out => voice_2_PA_MSB,
Osc => Voice_2_Osc,
Env => Voice_2_Env,
voice => voice_2
);
sid_voice_3: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_3_Freq_lo,
Freq_hi => Voice_3_Freq_hi,
Pw_lo => Voice_3_Pw_lo,
Pw_hi => Voice_3_Pw_hi,
Control => Voice_3_Control,
Att_dec => Voice_3_Att_dec,
Sus_Rel => Voice_3_Sus_Rel,
PA_MSB_in => voice_2_PA_MSB,
PA_MSB_out => voice_3_PA_MSB,
Osc => Misc_Osc3_Random,
Env => Misc_Env3,
voice => voice_3
);
-------------------------------------------------------------------------------------
do <= do_buf;
-- SID filters
fblk: block
signal voice1_signed: signed(12 downto 0);
signal voice2_signed: signed(12 downto 0);
signal voice3_signed: signed(12 downto 0);
constant ext_in_signed: signed(12 downto 0) := to_signed(0,13);
signal filtered_audio: signed(18 downto 0);
signal tick_q1, tick_q2: std_logic;
signal input_valid: std_logic;
signal unsigned_audio: std_logic_vector(17 downto 0);
signal unsigned_filt: std_logic_vector(18 downto 0);
signal ff1: std_logic;
begin
process (clk_1MHz,reset)
begin
if reset='1' then
ff1<='0';
else
if rising_edge(clk_1MHz) then
ff1<=not ff1;
end if;
end if;
end process;
process(clk32)
begin
if rising_edge(clk32) then
tick_q1 <= ff1;
tick_q2 <= tick_q1;
end if;
end process;
input_valid<='1' when tick_q1 /=tick_q2 else '0';
voice1_signed <= signed(voice_1 & "0") - 4096;
voice2_signed <= signed(voice_2 & "0") - 4096;
voice3_signed <= signed(voice_3 & "0") - 4096;
filters: sid_filters
port map (
clk => clk32,
rst => reset,
-- SID registers.
Fc_lo => Filter_Fc_lo,
Fc_hi => Filter_Fc_hi,
Res_Filt => Filter_Res_Filt,
Mode_Vol => Filter_Mode_Vol,
-- Voices - resampled to 13 bit
voice1 => voice1_signed,
voice2 => voice2_signed,
voice3 => voice3_signed,
--
input_valid => input_valid,
ext_in => ext_in_signed,
sound => filtered_audio,
valid => open
);
unsigned_filt <= std_logic_vector(filtered_audio + "1000000000000000000");
unsigned_audio <= unsigned_filt(18 downto 1);
audio_data <= unsigned_audio;
end block;
-- Register decoding
register_decoder:process(clk32)
begin
if rising_edge(clk32) then
if (reset = '1') then
--------------------------------------- Voice-1
Voice_1_Freq_lo <= (others => '0');
Voice_1_Freq_hi <= (others => '0');
Voice_1_Pw_lo <= (others => '0');
Voice_1_Pw_hi <= (others => '0');
Voice_1_Control <= (others => '0');
Voice_1_Att_dec <= (others => '0');
Voice_1_Sus_Rel <= (others => '0');
--------------------------------------- Voice-2
Voice_2_Freq_lo <= (others => '0');
Voice_2_Freq_hi <= (others => '0');
Voice_2_Pw_lo <= (others => '0');
Voice_2_Pw_hi <= (others => '0');
Voice_2_Control <= (others => '0');
Voice_2_Att_dec <= (others => '0');
Voice_2_Sus_Rel <= (others => '0');
--------------------------------------- Voice-3
Voice_3_Freq_lo <= (others => '0');
Voice_3_Freq_hi <= (others => '0');
Voice_3_Pw_lo <= (others => '0');
Voice_3_Pw_hi <= (others => '0');
Voice_3_Control <= (others => '0');
Voice_3_Att_dec <= (others => '0');
Voice_3_Sus_Rel <= (others => '0');
--------------------------------------- Filter & volume
Filter_Fc_lo <= (others => '0');
Filter_Fc_hi <= (others => '0');
Filter_Res_Filt <= (others => '0');
Filter_Mode_Vol <= (others => '0');
else
Voice_1_Freq_lo <= Voice_1_Freq_lo;
Voice_1_Freq_hi <= Voice_1_Freq_hi;
Voice_1_Pw_lo <= Voice_1_Pw_lo;
Voice_1_Pw_hi <= Voice_1_Pw_hi;
Voice_1_Control <= Voice_1_Control;
Voice_1_Att_dec <= Voice_1_Att_dec;
Voice_1_Sus_Rel <= Voice_1_Sus_Rel;
Voice_2_Freq_lo <= Voice_2_Freq_lo;
Voice_2_Freq_hi <= Voice_2_Freq_hi;
Voice_2_Pw_lo <= Voice_2_Pw_lo;
Voice_2_Pw_hi <= Voice_2_Pw_hi;
Voice_2_Control <= Voice_2_Control;
Voice_2_Att_dec <= Voice_2_Att_dec;
Voice_2_Sus_Rel <= Voice_2_Sus_Rel;
Voice_3_Freq_lo <= Voice_3_Freq_lo;
Voice_3_Freq_hi <= Voice_3_Freq_hi;
Voice_3_Pw_lo <= Voice_3_Pw_lo;
Voice_3_Pw_hi <= Voice_3_Pw_hi;
Voice_3_Control <= Voice_3_Control;
Voice_3_Att_dec <= Voice_3_Att_dec;
Voice_3_Sus_Rel <= Voice_3_Sus_Rel;
Filter_Fc_lo <= Filter_Fc_lo;
Filter_Fc_hi <= Filter_Fc_hi;
Filter_Res_Filt <= Filter_Res_Filt;
Filter_Mode_Vol <= Filter_Mode_Vol;
do_buf <= (others => '0');
if (cs='1') then
if (we='1') then -- Write to SID-register
------------------------
case addr is
-------------------------------------- Voice-1
when "00000" => Voice_1_Freq_lo <= di;
when "00001" => Voice_1_Freq_hi <= di;
when "00010" => Voice_1_Pw_lo <= di;
when "00011" => Voice_1_Pw_hi <= di(3 downto 0);
when "00100" => Voice_1_Control <= di;
when "00101" => Voice_1_Att_dec <= di;
when "00110" => Voice_1_Sus_Rel <= di;
--------------------------------------- Voice-2
when "00111" => Voice_2_Freq_lo <= di;
when "01000" => Voice_2_Freq_hi <= di;
when "01001" => Voice_2_Pw_lo <= di;
when "01010" => Voice_2_Pw_hi <= di(3 downto 0);
when "01011" => Voice_2_Control <= di;
when "01100" => Voice_2_Att_dec <= di;
when "01101" => Voice_2_Sus_Rel <= di;
--------------------------------------- Voice-3
when "01110" => Voice_3_Freq_lo <= di;
when "01111" => Voice_3_Freq_hi <= di;
when "10000" => Voice_3_Pw_lo <= di;
when "10001" => Voice_3_Pw_hi <= di(3 downto 0);
when "10010" => Voice_3_Control <= di;
when "10011" => Voice_3_Att_dec <= di;
when "10100" => Voice_3_Sus_Rel <= di;
--------------------------------------- Filter & volume
when "10101" => Filter_Fc_lo <= di;
when "10110" => Filter_Fc_hi <= di;
when "10111" => Filter_Res_Filt <= di;
when "11000" => Filter_Mode_Vol <= di;
--------------------------------------
when others => null;
end case;
else -- Read from SID-register
-------------------------
--case CONV_INTEGER(addr) is
case addr is
-------------------------------------- Misc
when "11001" => do_buf <= Misc_PotX;
when "11010" => do_buf <= Misc_PotY;
when "11011" => do_buf <= Misc_Osc3_Random;
when "11100" => do_buf <= Misc_Env3;
--------------------------------------
-- when others => null;
when others => do_buf <= (others => '0');
end case;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementation, use multiplexed channels
--
--
-- "The Filter was a classic multi-mode (state variable) VCF design. There was
-- no way to create a variable transconductance amplifier in our NMOS process,
-- so I simply used FETs as voltage-controlled resistors to control the cutoff
-- frequency. An 11-bit D/A converter generates the control voltage for the
-- FETs (it's actually a 12-bit D/A, but the LSB had no audible affect so I
-- disconnected it!)."
-- "Filter resonance was controlled by a 4-bit weighted resistor ladder. Each
-- bit would turn on one of the weighted resistors and allow a portion of the
-- output to feed back to the input. The state-variable design provided
-- simultaneous low-pass, band-pass and high-pass outputs. Analog switches
-- selected which combination of outputs were sent to the final amplifier (a
-- notch filter was created by enabling both the high and low-pass outputs
-- simultaneously)."
-- "The filter is the worst part of SID because I could not create high-gain
-- op-amps in NMOS, which were essential to a resonant filter. In addition,
-- the resistance of the FETs varied considerably with processing, so different
-- lots of SID chips had different cutoff frequency characteristics. I knew it
-- wouldn't work very well, but it was better than nothing and I didn't have
-- time to make it better."
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end sid6581;
architecture Behavioral of sid6581 is
--Implementation Digital to Analog converter
component pwm_sddac is
port (
clk_i : in std_logic; -- main clock signal, the higher the better
reset : in std_logic; -- reset input active high
dac_o : out std_logic; -- PWM output after a simple low-pass filter this is to be considered an analog signal
dac_i : in std_logic_vector(9 downto 0) -- binary input of signal to be converted
);
end component;
component pwm_sdadc is
port (
clk : in std_logic; -- main clock signal (actually the higher the better)
reset : in std_logic; --
ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted
ADC_in : in std_logic -- "analog" paddle input pin
);
end component;
-- Implementation of the SID voices (sound channels)
component sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); --
Freq_hi : in std_logic_vector(7 downto 0); --
Pw_lo : in std_logic_vector(7 downto 0); --
Pw_hi : in std_logic_vector(3 downto 0); --
Control : in std_logic_vector(7 downto 0); --
Att_dec : in std_logic_vector(7 downto 0); --
Sus_Rel : in std_logic_vector(7 downto 0); --
PA_MSB_in : in std_logic; --
PA_MSB_out : out std_logic; --
Osc : out std_logic_vector(7 downto 0); --
Env : out std_logic_vector(7 downto 0); --
voice : out std_logic_vector(11 downto 0) --
);
end component;
component sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end component;
-------------------------------------------------------------------------------
--constant <name>: <type> := <value>;
-- DC offset required to play samples, this is actually a bug of the real 6581,
-- that was converted into an advantage to play samples
constant DC_offset : std_logic_vector(13 downto 0) := "00111111111111";
-------------------------------------------------------------------------------
signal Voice_1_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_1_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_2_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_3_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Res_Filt : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Mode_Vol : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotX : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotY : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Osc3_Random : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Env3 : std_logic_vector(7 downto 0) := (others => '0');
signal do_buf : std_logic_vector(7 downto 0) := (others => '0');
signal voice_1 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_2 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_3 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_mixed : std_logic_vector(13 downto 0) := (others => '0');
signal voice_volume : std_logic_vector(35 downto 0) := (others => '0');
signal divide_0 : std_logic_vector(31 downto 0) := (others => '0');
signal voice_1_PA_MSB : std_logic := '0';
signal voice_2_PA_MSB : std_logic := '0';
signal voice_3_PA_MSB : std_logic := '0';
-------------------------------------------------------------------------------
begin
digital_to_analog: pwm_sddac
port map(
clk_i => clk_DAC,
reset => reset,
dac_i => voice_volume(17 downto 8),
dac_o => audio_out
);
paddle_x: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotX,
ADC_in => pot_x
);
paddle_y: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotY,
ADC_in => pot_y
);
sid_voice_1: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_1_Freq_lo,
Freq_hi => Voice_1_Freq_hi,
Pw_lo => Voice_1_Pw_lo,
Pw_hi => Voice_1_Pw_hi,
Control => Voice_1_Control,
Att_dec => Voice_1_Att_dec,
Sus_Rel => Voice_1_Sus_Rel,
PA_MSB_in => voice_3_PA_MSB,
PA_MSB_out => voice_1_PA_MSB,
Osc => Voice_1_Osc,
Env => Voice_1_Env,
voice => voice_1
);
sid_voice_2: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_2_Freq_lo,
Freq_hi => Voice_2_Freq_hi,
Pw_lo => Voice_2_Pw_lo,
Pw_hi => Voice_2_Pw_hi,
Control => Voice_2_Control,
Att_dec => Voice_2_Att_dec,
Sus_Rel => Voice_2_Sus_Rel,
PA_MSB_in => voice_1_PA_MSB,
PA_MSB_out => voice_2_PA_MSB,
Osc => Voice_2_Osc,
Env => Voice_2_Env,
voice => voice_2
);
sid_voice_3: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_3_Freq_lo,
Freq_hi => Voice_3_Freq_hi,
Pw_lo => Voice_3_Pw_lo,
Pw_hi => Voice_3_Pw_hi,
Control => Voice_3_Control,
Att_dec => Voice_3_Att_dec,
Sus_Rel => Voice_3_Sus_Rel,
PA_MSB_in => voice_2_PA_MSB,
PA_MSB_out => voice_3_PA_MSB,
Osc => Misc_Osc3_Random,
Env => Misc_Env3,
voice => voice_3
);
-------------------------------------------------------------------------------------
do <= do_buf;
-- SID filters
fblk: block
signal voice1_signed: signed(12 downto 0);
signal voice2_signed: signed(12 downto 0);
signal voice3_signed: signed(12 downto 0);
constant ext_in_signed: signed(12 downto 0) := to_signed(0,13);
signal filtered_audio: signed(18 downto 0);
signal tick_q1, tick_q2: std_logic;
signal input_valid: std_logic;
signal unsigned_audio: std_logic_vector(17 downto 0);
signal unsigned_filt: std_logic_vector(18 downto 0);
signal ff1: std_logic;
begin
process (clk_1MHz,reset)
begin
if reset='1' then
ff1<='0';
else
if rising_edge(clk_1MHz) then
ff1<=not ff1;
end if;
end if;
end process;
process(clk32)
begin
if rising_edge(clk32) then
tick_q1 <= ff1;
tick_q2 <= tick_q1;
end if;
end process;
input_valid<='1' when tick_q1 /=tick_q2 else '0';
voice1_signed <= signed(voice_1 & "0") - 4096;
voice2_signed <= signed(voice_2 & "0") - 4096;
voice3_signed <= signed(voice_3 & "0") - 4096;
filters: sid_filters
port map (
clk => clk32,
rst => reset,
-- SID registers.
Fc_lo => Filter_Fc_lo,
Fc_hi => Filter_Fc_hi,
Res_Filt => Filter_Res_Filt,
Mode_Vol => Filter_Mode_Vol,
-- Voices - resampled to 13 bit
voice1 => voice1_signed,
voice2 => voice2_signed,
voice3 => voice3_signed,
--
input_valid => input_valid,
ext_in => ext_in_signed,
sound => filtered_audio,
valid => open
);
unsigned_filt <= std_logic_vector(filtered_audio + "1000000000000000000");
unsigned_audio <= unsigned_filt(18 downto 1);
audio_data <= unsigned_audio;
end block;
-- Register decoding
register_decoder:process(clk32)
begin
if rising_edge(clk32) then
if (reset = '1') then
--------------------------------------- Voice-1
Voice_1_Freq_lo <= (others => '0');
Voice_1_Freq_hi <= (others => '0');
Voice_1_Pw_lo <= (others => '0');
Voice_1_Pw_hi <= (others => '0');
Voice_1_Control <= (others => '0');
Voice_1_Att_dec <= (others => '0');
Voice_1_Sus_Rel <= (others => '0');
--------------------------------------- Voice-2
Voice_2_Freq_lo <= (others => '0');
Voice_2_Freq_hi <= (others => '0');
Voice_2_Pw_lo <= (others => '0');
Voice_2_Pw_hi <= (others => '0');
Voice_2_Control <= (others => '0');
Voice_2_Att_dec <= (others => '0');
Voice_2_Sus_Rel <= (others => '0');
--------------------------------------- Voice-3
Voice_3_Freq_lo <= (others => '0');
Voice_3_Freq_hi <= (others => '0');
Voice_3_Pw_lo <= (others => '0');
Voice_3_Pw_hi <= (others => '0');
Voice_3_Control <= (others => '0');
Voice_3_Att_dec <= (others => '0');
Voice_3_Sus_Rel <= (others => '0');
--------------------------------------- Filter & volume
Filter_Fc_lo <= (others => '0');
Filter_Fc_hi <= (others => '0');
Filter_Res_Filt <= (others => '0');
Filter_Mode_Vol <= (others => '0');
else
Voice_1_Freq_lo <= Voice_1_Freq_lo;
Voice_1_Freq_hi <= Voice_1_Freq_hi;
Voice_1_Pw_lo <= Voice_1_Pw_lo;
Voice_1_Pw_hi <= Voice_1_Pw_hi;
Voice_1_Control <= Voice_1_Control;
Voice_1_Att_dec <= Voice_1_Att_dec;
Voice_1_Sus_Rel <= Voice_1_Sus_Rel;
Voice_2_Freq_lo <= Voice_2_Freq_lo;
Voice_2_Freq_hi <= Voice_2_Freq_hi;
Voice_2_Pw_lo <= Voice_2_Pw_lo;
Voice_2_Pw_hi <= Voice_2_Pw_hi;
Voice_2_Control <= Voice_2_Control;
Voice_2_Att_dec <= Voice_2_Att_dec;
Voice_2_Sus_Rel <= Voice_2_Sus_Rel;
Voice_3_Freq_lo <= Voice_3_Freq_lo;
Voice_3_Freq_hi <= Voice_3_Freq_hi;
Voice_3_Pw_lo <= Voice_3_Pw_lo;
Voice_3_Pw_hi <= Voice_3_Pw_hi;
Voice_3_Control <= Voice_3_Control;
Voice_3_Att_dec <= Voice_3_Att_dec;
Voice_3_Sus_Rel <= Voice_3_Sus_Rel;
Filter_Fc_lo <= Filter_Fc_lo;
Filter_Fc_hi <= Filter_Fc_hi;
Filter_Res_Filt <= Filter_Res_Filt;
Filter_Mode_Vol <= Filter_Mode_Vol;
do_buf <= (others => '0');
if (cs='1') then
if (we='1') then -- Write to SID-register
------------------------
case addr is
-------------------------------------- Voice-1
when "00000" => Voice_1_Freq_lo <= di;
when "00001" => Voice_1_Freq_hi <= di;
when "00010" => Voice_1_Pw_lo <= di;
when "00011" => Voice_1_Pw_hi <= di(3 downto 0);
when "00100" => Voice_1_Control <= di;
when "00101" => Voice_1_Att_dec <= di;
when "00110" => Voice_1_Sus_Rel <= di;
--------------------------------------- Voice-2
when "00111" => Voice_2_Freq_lo <= di;
when "01000" => Voice_2_Freq_hi <= di;
when "01001" => Voice_2_Pw_lo <= di;
when "01010" => Voice_2_Pw_hi <= di(3 downto 0);
when "01011" => Voice_2_Control <= di;
when "01100" => Voice_2_Att_dec <= di;
when "01101" => Voice_2_Sus_Rel <= di;
--------------------------------------- Voice-3
when "01110" => Voice_3_Freq_lo <= di;
when "01111" => Voice_3_Freq_hi <= di;
when "10000" => Voice_3_Pw_lo <= di;
when "10001" => Voice_3_Pw_hi <= di(3 downto 0);
when "10010" => Voice_3_Control <= di;
when "10011" => Voice_3_Att_dec <= di;
when "10100" => Voice_3_Sus_Rel <= di;
--------------------------------------- Filter & volume
when "10101" => Filter_Fc_lo <= di;
when "10110" => Filter_Fc_hi <= di;
when "10111" => Filter_Res_Filt <= di;
when "11000" => Filter_Mode_Vol <= di;
--------------------------------------
when others => null;
end case;
else -- Read from SID-register
-------------------------
--case CONV_INTEGER(addr) is
case addr is
-------------------------------------- Misc
when "11001" => do_buf <= Misc_PotX;
when "11010" => do_buf <= Misc_PotY;
when "11011" => do_buf <= Misc_Osc3_Random;
when "11100" => do_buf <= Misc_Env3;
--------------------------------------
-- when others => null;
when others => do_buf <= (others => '0');
end case;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementation, use multiplexed channels
--
--
-- "The Filter was a classic multi-mode (state variable) VCF design. There was
-- no way to create a variable transconductance amplifier in our NMOS process,
-- so I simply used FETs as voltage-controlled resistors to control the cutoff
-- frequency. An 11-bit D/A converter generates the control voltage for the
-- FETs (it's actually a 12-bit D/A, but the LSB had no audible affect so I
-- disconnected it!)."
-- "Filter resonance was controlled by a 4-bit weighted resistor ladder. Each
-- bit would turn on one of the weighted resistors and allow a portion of the
-- output to feed back to the input. The state-variable design provided
-- simultaneous low-pass, band-pass and high-pass outputs. Analog switches
-- selected which combination of outputs were sent to the final amplifier (a
-- notch filter was created by enabling both the high and low-pass outputs
-- simultaneously)."
-- "The filter is the worst part of SID because I could not create high-gain
-- op-amps in NMOS, which were essential to a resonant filter. In addition,
-- the resistance of the FETs varied considerably with processing, so different
-- lots of SID chips had different cutoff frequency characteristics. I knew it
-- wouldn't work very well, but it was better than nothing and I didn't have
-- time to make it better."
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end sid6581;
architecture Behavioral of sid6581 is
--Implementation Digital to Analog converter
component pwm_sddac is
port (
clk_i : in std_logic; -- main clock signal, the higher the better
reset : in std_logic; -- reset input active high
dac_o : out std_logic; -- PWM output after a simple low-pass filter this is to be considered an analog signal
dac_i : in std_logic_vector(9 downto 0) -- binary input of signal to be converted
);
end component;
component pwm_sdadc is
port (
clk : in std_logic; -- main clock signal (actually the higher the better)
reset : in std_logic; --
ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted
ADC_in : in std_logic -- "analog" paddle input pin
);
end component;
-- Implementation of the SID voices (sound channels)
component sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); --
Freq_hi : in std_logic_vector(7 downto 0); --
Pw_lo : in std_logic_vector(7 downto 0); --
Pw_hi : in std_logic_vector(3 downto 0); --
Control : in std_logic_vector(7 downto 0); --
Att_dec : in std_logic_vector(7 downto 0); --
Sus_Rel : in std_logic_vector(7 downto 0); --
PA_MSB_in : in std_logic; --
PA_MSB_out : out std_logic; --
Osc : out std_logic_vector(7 downto 0); --
Env : out std_logic_vector(7 downto 0); --
voice : out std_logic_vector(11 downto 0) --
);
end component;
component sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end component;
-------------------------------------------------------------------------------
--constant <name>: <type> := <value>;
-- DC offset required to play samples, this is actually a bug of the real 6581,
-- that was converted into an advantage to play samples
constant DC_offset : std_logic_vector(13 downto 0) := "00111111111111";
-------------------------------------------------------------------------------
signal Voice_1_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_1_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_2_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_3_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Res_Filt : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Mode_Vol : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotX : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotY : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Osc3_Random : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Env3 : std_logic_vector(7 downto 0) := (others => '0');
signal do_buf : std_logic_vector(7 downto 0) := (others => '0');
signal voice_1 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_2 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_3 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_mixed : std_logic_vector(13 downto 0) := (others => '0');
signal voice_volume : std_logic_vector(35 downto 0) := (others => '0');
signal divide_0 : std_logic_vector(31 downto 0) := (others => '0');
signal voice_1_PA_MSB : std_logic := '0';
signal voice_2_PA_MSB : std_logic := '0';
signal voice_3_PA_MSB : std_logic := '0';
-------------------------------------------------------------------------------
begin
digital_to_analog: pwm_sddac
port map(
clk_i => clk_DAC,
reset => reset,
dac_i => voice_volume(17 downto 8),
dac_o => audio_out
);
paddle_x: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotX,
ADC_in => pot_x
);
paddle_y: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotY,
ADC_in => pot_y
);
sid_voice_1: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_1_Freq_lo,
Freq_hi => Voice_1_Freq_hi,
Pw_lo => Voice_1_Pw_lo,
Pw_hi => Voice_1_Pw_hi,
Control => Voice_1_Control,
Att_dec => Voice_1_Att_dec,
Sus_Rel => Voice_1_Sus_Rel,
PA_MSB_in => voice_3_PA_MSB,
PA_MSB_out => voice_1_PA_MSB,
Osc => Voice_1_Osc,
Env => Voice_1_Env,
voice => voice_1
);
sid_voice_2: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_2_Freq_lo,
Freq_hi => Voice_2_Freq_hi,
Pw_lo => Voice_2_Pw_lo,
Pw_hi => Voice_2_Pw_hi,
Control => Voice_2_Control,
Att_dec => Voice_2_Att_dec,
Sus_Rel => Voice_2_Sus_Rel,
PA_MSB_in => voice_1_PA_MSB,
PA_MSB_out => voice_2_PA_MSB,
Osc => Voice_2_Osc,
Env => Voice_2_Env,
voice => voice_2
);
sid_voice_3: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_3_Freq_lo,
Freq_hi => Voice_3_Freq_hi,
Pw_lo => Voice_3_Pw_lo,
Pw_hi => Voice_3_Pw_hi,
Control => Voice_3_Control,
Att_dec => Voice_3_Att_dec,
Sus_Rel => Voice_3_Sus_Rel,
PA_MSB_in => voice_2_PA_MSB,
PA_MSB_out => voice_3_PA_MSB,
Osc => Misc_Osc3_Random,
Env => Misc_Env3,
voice => voice_3
);
-------------------------------------------------------------------------------------
do <= do_buf;
-- SID filters
fblk: block
signal voice1_signed: signed(12 downto 0);
signal voice2_signed: signed(12 downto 0);
signal voice3_signed: signed(12 downto 0);
constant ext_in_signed: signed(12 downto 0) := to_signed(0,13);
signal filtered_audio: signed(18 downto 0);
signal tick_q1, tick_q2: std_logic;
signal input_valid: std_logic;
signal unsigned_audio: std_logic_vector(17 downto 0);
signal unsigned_filt: std_logic_vector(18 downto 0);
signal ff1: std_logic;
begin
process (clk_1MHz,reset)
begin
if reset='1' then
ff1<='0';
else
if rising_edge(clk_1MHz) then
ff1<=not ff1;
end if;
end if;
end process;
process(clk32)
begin
if rising_edge(clk32) then
tick_q1 <= ff1;
tick_q2 <= tick_q1;
end if;
end process;
input_valid<='1' when tick_q1 /=tick_q2 else '0';
voice1_signed <= signed(voice_1 & "0") - 4096;
voice2_signed <= signed(voice_2 & "0") - 4096;
voice3_signed <= signed(voice_3 & "0") - 4096;
filters: sid_filters
port map (
clk => clk32,
rst => reset,
-- SID registers.
Fc_lo => Filter_Fc_lo,
Fc_hi => Filter_Fc_hi,
Res_Filt => Filter_Res_Filt,
Mode_Vol => Filter_Mode_Vol,
-- Voices - resampled to 13 bit
voice1 => voice1_signed,
voice2 => voice2_signed,
voice3 => voice3_signed,
--
input_valid => input_valid,
ext_in => ext_in_signed,
sound => filtered_audio,
valid => open
);
unsigned_filt <= std_logic_vector(filtered_audio + "1000000000000000000");
unsigned_audio <= unsigned_filt(18 downto 1);
audio_data <= unsigned_audio;
end block;
-- Register decoding
register_decoder:process(clk32)
begin
if rising_edge(clk32) then
if (reset = '1') then
--------------------------------------- Voice-1
Voice_1_Freq_lo <= (others => '0');
Voice_1_Freq_hi <= (others => '0');
Voice_1_Pw_lo <= (others => '0');
Voice_1_Pw_hi <= (others => '0');
Voice_1_Control <= (others => '0');
Voice_1_Att_dec <= (others => '0');
Voice_1_Sus_Rel <= (others => '0');
--------------------------------------- Voice-2
Voice_2_Freq_lo <= (others => '0');
Voice_2_Freq_hi <= (others => '0');
Voice_2_Pw_lo <= (others => '0');
Voice_2_Pw_hi <= (others => '0');
Voice_2_Control <= (others => '0');
Voice_2_Att_dec <= (others => '0');
Voice_2_Sus_Rel <= (others => '0');
--------------------------------------- Voice-3
Voice_3_Freq_lo <= (others => '0');
Voice_3_Freq_hi <= (others => '0');
Voice_3_Pw_lo <= (others => '0');
Voice_3_Pw_hi <= (others => '0');
Voice_3_Control <= (others => '0');
Voice_3_Att_dec <= (others => '0');
Voice_3_Sus_Rel <= (others => '0');
--------------------------------------- Filter & volume
Filter_Fc_lo <= (others => '0');
Filter_Fc_hi <= (others => '0');
Filter_Res_Filt <= (others => '0');
Filter_Mode_Vol <= (others => '0');
else
Voice_1_Freq_lo <= Voice_1_Freq_lo;
Voice_1_Freq_hi <= Voice_1_Freq_hi;
Voice_1_Pw_lo <= Voice_1_Pw_lo;
Voice_1_Pw_hi <= Voice_1_Pw_hi;
Voice_1_Control <= Voice_1_Control;
Voice_1_Att_dec <= Voice_1_Att_dec;
Voice_1_Sus_Rel <= Voice_1_Sus_Rel;
Voice_2_Freq_lo <= Voice_2_Freq_lo;
Voice_2_Freq_hi <= Voice_2_Freq_hi;
Voice_2_Pw_lo <= Voice_2_Pw_lo;
Voice_2_Pw_hi <= Voice_2_Pw_hi;
Voice_2_Control <= Voice_2_Control;
Voice_2_Att_dec <= Voice_2_Att_dec;
Voice_2_Sus_Rel <= Voice_2_Sus_Rel;
Voice_3_Freq_lo <= Voice_3_Freq_lo;
Voice_3_Freq_hi <= Voice_3_Freq_hi;
Voice_3_Pw_lo <= Voice_3_Pw_lo;
Voice_3_Pw_hi <= Voice_3_Pw_hi;
Voice_3_Control <= Voice_3_Control;
Voice_3_Att_dec <= Voice_3_Att_dec;
Voice_3_Sus_Rel <= Voice_3_Sus_Rel;
Filter_Fc_lo <= Filter_Fc_lo;
Filter_Fc_hi <= Filter_Fc_hi;
Filter_Res_Filt <= Filter_Res_Filt;
Filter_Mode_Vol <= Filter_Mode_Vol;
do_buf <= (others => '0');
if (cs='1') then
if (we='1') then -- Write to SID-register
------------------------
case addr is
-------------------------------------- Voice-1
when "00000" => Voice_1_Freq_lo <= di;
when "00001" => Voice_1_Freq_hi <= di;
when "00010" => Voice_1_Pw_lo <= di;
when "00011" => Voice_1_Pw_hi <= di(3 downto 0);
when "00100" => Voice_1_Control <= di;
when "00101" => Voice_1_Att_dec <= di;
when "00110" => Voice_1_Sus_Rel <= di;
--------------------------------------- Voice-2
when "00111" => Voice_2_Freq_lo <= di;
when "01000" => Voice_2_Freq_hi <= di;
when "01001" => Voice_2_Pw_lo <= di;
when "01010" => Voice_2_Pw_hi <= di(3 downto 0);
when "01011" => Voice_2_Control <= di;
when "01100" => Voice_2_Att_dec <= di;
when "01101" => Voice_2_Sus_Rel <= di;
--------------------------------------- Voice-3
when "01110" => Voice_3_Freq_lo <= di;
when "01111" => Voice_3_Freq_hi <= di;
when "10000" => Voice_3_Pw_lo <= di;
when "10001" => Voice_3_Pw_hi <= di(3 downto 0);
when "10010" => Voice_3_Control <= di;
when "10011" => Voice_3_Att_dec <= di;
when "10100" => Voice_3_Sus_Rel <= di;
--------------------------------------- Filter & volume
when "10101" => Filter_Fc_lo <= di;
when "10110" => Filter_Fc_hi <= di;
when "10111" => Filter_Res_Filt <= di;
when "11000" => Filter_Mode_Vol <= di;
--------------------------------------
when others => null;
end case;
else -- Read from SID-register
-------------------------
--case CONV_INTEGER(addr) is
case addr is
-------------------------------------- Misc
when "11001" => do_buf <= Misc_PotX;
when "11010" => do_buf <= Misc_PotY;
when "11011" => do_buf <= Misc_Osc3_Random;
when "11100" => do_buf <= Misc_Env3;
--------------------------------------
-- when others => null;
when others => do_buf <= (others => '0');
end case;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementation, use multiplexed channels
--
--
-- "The Filter was a classic multi-mode (state variable) VCF design. There was
-- no way to create a variable transconductance amplifier in our NMOS process,
-- so I simply used FETs as voltage-controlled resistors to control the cutoff
-- frequency. An 11-bit D/A converter generates the control voltage for the
-- FETs (it's actually a 12-bit D/A, but the LSB had no audible affect so I
-- disconnected it!)."
-- "Filter resonance was controlled by a 4-bit weighted resistor ladder. Each
-- bit would turn on one of the weighted resistors and allow a portion of the
-- output to feed back to the input. The state-variable design provided
-- simultaneous low-pass, band-pass and high-pass outputs. Analog switches
-- selected which combination of outputs were sent to the final amplifier (a
-- notch filter was created by enabling both the high and low-pass outputs
-- simultaneously)."
-- "The filter is the worst part of SID because I could not create high-gain
-- op-amps in NMOS, which were essential to a resonant filter. In addition,
-- the resistance of the FETs varied considerably with processing, so different
-- lots of SID chips had different cutoff frequency characteristics. I knew it
-- wouldn't work very well, but it was better than nothing and I didn't have
-- time to make it better."
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end sid6581;
architecture Behavioral of sid6581 is
--Implementation Digital to Analog converter
component pwm_sddac is
port (
clk_i : in std_logic; -- main clock signal, the higher the better
reset : in std_logic; -- reset input active high
dac_o : out std_logic; -- PWM output after a simple low-pass filter this is to be considered an analog signal
dac_i : in std_logic_vector(9 downto 0) -- binary input of signal to be converted
);
end component;
component pwm_sdadc is
port (
clk : in std_logic; -- main clock signal (actually the higher the better)
reset : in std_logic; --
ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted
ADC_in : in std_logic -- "analog" paddle input pin
);
end component;
-- Implementation of the SID voices (sound channels)
component sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); --
Freq_hi : in std_logic_vector(7 downto 0); --
Pw_lo : in std_logic_vector(7 downto 0); --
Pw_hi : in std_logic_vector(3 downto 0); --
Control : in std_logic_vector(7 downto 0); --
Att_dec : in std_logic_vector(7 downto 0); --
Sus_Rel : in std_logic_vector(7 downto 0); --
PA_MSB_in : in std_logic; --
PA_MSB_out : out std_logic; --
Osc : out std_logic_vector(7 downto 0); --
Env : out std_logic_vector(7 downto 0); --
voice : out std_logic_vector(11 downto 0) --
);
end component;
component sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end component;
-------------------------------------------------------------------------------
--constant <name>: <type> := <value>;
-- DC offset required to play samples, this is actually a bug of the real 6581,
-- that was converted into an advantage to play samples
constant DC_offset : std_logic_vector(13 downto 0) := "00111111111111";
-------------------------------------------------------------------------------
signal Voice_1_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_1_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_2_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_3_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Res_Filt : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Mode_Vol : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotX : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotY : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Osc3_Random : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Env3 : std_logic_vector(7 downto 0) := (others => '0');
signal do_buf : std_logic_vector(7 downto 0) := (others => '0');
signal voice_1 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_2 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_3 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_mixed : std_logic_vector(13 downto 0) := (others => '0');
signal voice_volume : std_logic_vector(35 downto 0) := (others => '0');
signal divide_0 : std_logic_vector(31 downto 0) := (others => '0');
signal voice_1_PA_MSB : std_logic := '0';
signal voice_2_PA_MSB : std_logic := '0';
signal voice_3_PA_MSB : std_logic := '0';
-------------------------------------------------------------------------------
begin
digital_to_analog: pwm_sddac
port map(
clk_i => clk_DAC,
reset => reset,
dac_i => voice_volume(17 downto 8),
dac_o => audio_out
);
paddle_x: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotX,
ADC_in => pot_x
);
paddle_y: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotY,
ADC_in => pot_y
);
sid_voice_1: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_1_Freq_lo,
Freq_hi => Voice_1_Freq_hi,
Pw_lo => Voice_1_Pw_lo,
Pw_hi => Voice_1_Pw_hi,
Control => Voice_1_Control,
Att_dec => Voice_1_Att_dec,
Sus_Rel => Voice_1_Sus_Rel,
PA_MSB_in => voice_3_PA_MSB,
PA_MSB_out => voice_1_PA_MSB,
Osc => Voice_1_Osc,
Env => Voice_1_Env,
voice => voice_1
);
sid_voice_2: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_2_Freq_lo,
Freq_hi => Voice_2_Freq_hi,
Pw_lo => Voice_2_Pw_lo,
Pw_hi => Voice_2_Pw_hi,
Control => Voice_2_Control,
Att_dec => Voice_2_Att_dec,
Sus_Rel => Voice_2_Sus_Rel,
PA_MSB_in => voice_1_PA_MSB,
PA_MSB_out => voice_2_PA_MSB,
Osc => Voice_2_Osc,
Env => Voice_2_Env,
voice => voice_2
);
sid_voice_3: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_3_Freq_lo,
Freq_hi => Voice_3_Freq_hi,
Pw_lo => Voice_3_Pw_lo,
Pw_hi => Voice_3_Pw_hi,
Control => Voice_3_Control,
Att_dec => Voice_3_Att_dec,
Sus_Rel => Voice_3_Sus_Rel,
PA_MSB_in => voice_2_PA_MSB,
PA_MSB_out => voice_3_PA_MSB,
Osc => Misc_Osc3_Random,
Env => Misc_Env3,
voice => voice_3
);
-------------------------------------------------------------------------------------
do <= do_buf;
-- SID filters
fblk: block
signal voice1_signed: signed(12 downto 0);
signal voice2_signed: signed(12 downto 0);
signal voice3_signed: signed(12 downto 0);
constant ext_in_signed: signed(12 downto 0) := to_signed(0,13);
signal filtered_audio: signed(18 downto 0);
signal tick_q1, tick_q2: std_logic;
signal input_valid: std_logic;
signal unsigned_audio: std_logic_vector(17 downto 0);
signal unsigned_filt: std_logic_vector(18 downto 0);
signal ff1: std_logic;
begin
process (clk_1MHz,reset)
begin
if reset='1' then
ff1<='0';
else
if rising_edge(clk_1MHz) then
ff1<=not ff1;
end if;
end if;
end process;
process(clk32)
begin
if rising_edge(clk32) then
tick_q1 <= ff1;
tick_q2 <= tick_q1;
end if;
end process;
input_valid<='1' when tick_q1 /=tick_q2 else '0';
voice1_signed <= signed(voice_1 & "0") - 4096;
voice2_signed <= signed(voice_2 & "0") - 4096;
voice3_signed <= signed(voice_3 & "0") - 4096;
filters: sid_filters
port map (
clk => clk32,
rst => reset,
-- SID registers.
Fc_lo => Filter_Fc_lo,
Fc_hi => Filter_Fc_hi,
Res_Filt => Filter_Res_Filt,
Mode_Vol => Filter_Mode_Vol,
-- Voices - resampled to 13 bit
voice1 => voice1_signed,
voice2 => voice2_signed,
voice3 => voice3_signed,
--
input_valid => input_valid,
ext_in => ext_in_signed,
sound => filtered_audio,
valid => open
);
unsigned_filt <= std_logic_vector(filtered_audio + "1000000000000000000");
unsigned_audio <= unsigned_filt(18 downto 1);
audio_data <= unsigned_audio;
end block;
-- Register decoding
register_decoder:process(clk32)
begin
if rising_edge(clk32) then
if (reset = '1') then
--------------------------------------- Voice-1
Voice_1_Freq_lo <= (others => '0');
Voice_1_Freq_hi <= (others => '0');
Voice_1_Pw_lo <= (others => '0');
Voice_1_Pw_hi <= (others => '0');
Voice_1_Control <= (others => '0');
Voice_1_Att_dec <= (others => '0');
Voice_1_Sus_Rel <= (others => '0');
--------------------------------------- Voice-2
Voice_2_Freq_lo <= (others => '0');
Voice_2_Freq_hi <= (others => '0');
Voice_2_Pw_lo <= (others => '0');
Voice_2_Pw_hi <= (others => '0');
Voice_2_Control <= (others => '0');
Voice_2_Att_dec <= (others => '0');
Voice_2_Sus_Rel <= (others => '0');
--------------------------------------- Voice-3
Voice_3_Freq_lo <= (others => '0');
Voice_3_Freq_hi <= (others => '0');
Voice_3_Pw_lo <= (others => '0');
Voice_3_Pw_hi <= (others => '0');
Voice_3_Control <= (others => '0');
Voice_3_Att_dec <= (others => '0');
Voice_3_Sus_Rel <= (others => '0');
--------------------------------------- Filter & volume
Filter_Fc_lo <= (others => '0');
Filter_Fc_hi <= (others => '0');
Filter_Res_Filt <= (others => '0');
Filter_Mode_Vol <= (others => '0');
else
Voice_1_Freq_lo <= Voice_1_Freq_lo;
Voice_1_Freq_hi <= Voice_1_Freq_hi;
Voice_1_Pw_lo <= Voice_1_Pw_lo;
Voice_1_Pw_hi <= Voice_1_Pw_hi;
Voice_1_Control <= Voice_1_Control;
Voice_1_Att_dec <= Voice_1_Att_dec;
Voice_1_Sus_Rel <= Voice_1_Sus_Rel;
Voice_2_Freq_lo <= Voice_2_Freq_lo;
Voice_2_Freq_hi <= Voice_2_Freq_hi;
Voice_2_Pw_lo <= Voice_2_Pw_lo;
Voice_2_Pw_hi <= Voice_2_Pw_hi;
Voice_2_Control <= Voice_2_Control;
Voice_2_Att_dec <= Voice_2_Att_dec;
Voice_2_Sus_Rel <= Voice_2_Sus_Rel;
Voice_3_Freq_lo <= Voice_3_Freq_lo;
Voice_3_Freq_hi <= Voice_3_Freq_hi;
Voice_3_Pw_lo <= Voice_3_Pw_lo;
Voice_3_Pw_hi <= Voice_3_Pw_hi;
Voice_3_Control <= Voice_3_Control;
Voice_3_Att_dec <= Voice_3_Att_dec;
Voice_3_Sus_Rel <= Voice_3_Sus_Rel;
Filter_Fc_lo <= Filter_Fc_lo;
Filter_Fc_hi <= Filter_Fc_hi;
Filter_Res_Filt <= Filter_Res_Filt;
Filter_Mode_Vol <= Filter_Mode_Vol;
do_buf <= (others => '0');
if (cs='1') then
if (we='1') then -- Write to SID-register
------------------------
case addr is
-------------------------------------- Voice-1
when "00000" => Voice_1_Freq_lo <= di;
when "00001" => Voice_1_Freq_hi <= di;
when "00010" => Voice_1_Pw_lo <= di;
when "00011" => Voice_1_Pw_hi <= di(3 downto 0);
when "00100" => Voice_1_Control <= di;
when "00101" => Voice_1_Att_dec <= di;
when "00110" => Voice_1_Sus_Rel <= di;
--------------------------------------- Voice-2
when "00111" => Voice_2_Freq_lo <= di;
when "01000" => Voice_2_Freq_hi <= di;
when "01001" => Voice_2_Pw_lo <= di;
when "01010" => Voice_2_Pw_hi <= di(3 downto 0);
when "01011" => Voice_2_Control <= di;
when "01100" => Voice_2_Att_dec <= di;
when "01101" => Voice_2_Sus_Rel <= di;
--------------------------------------- Voice-3
when "01110" => Voice_3_Freq_lo <= di;
when "01111" => Voice_3_Freq_hi <= di;
when "10000" => Voice_3_Pw_lo <= di;
when "10001" => Voice_3_Pw_hi <= di(3 downto 0);
when "10010" => Voice_3_Control <= di;
when "10011" => Voice_3_Att_dec <= di;
when "10100" => Voice_3_Sus_Rel <= di;
--------------------------------------- Filter & volume
when "10101" => Filter_Fc_lo <= di;
when "10110" => Filter_Fc_hi <= di;
when "10111" => Filter_Res_Filt <= di;
when "11000" => Filter_Mode_Vol <= di;
--------------------------------------
when others => null;
end case;
else -- Read from SID-register
-------------------------
--case CONV_INTEGER(addr) is
case addr is
-------------------------------------- Misc
when "11001" => do_buf <= Misc_PotX;
when "11010" => do_buf <= Misc_PotY;
when "11011" => do_buf <= Misc_Osc3_Random;
when "11100" => do_buf <= Misc_Env3;
--------------------------------------
-- when others => null;
when others => do_buf <= (others => '0');
end case;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementation, use multiplexed channels
--
--
-- "The Filter was a classic multi-mode (state variable) VCF design. There was
-- no way to create a variable transconductance amplifier in our NMOS process,
-- so I simply used FETs as voltage-controlled resistors to control the cutoff
-- frequency. An 11-bit D/A converter generates the control voltage for the
-- FETs (it's actually a 12-bit D/A, but the LSB had no audible affect so I
-- disconnected it!)."
-- "Filter resonance was controlled by a 4-bit weighted resistor ladder. Each
-- bit would turn on one of the weighted resistors and allow a portion of the
-- output to feed back to the input. The state-variable design provided
-- simultaneous low-pass, band-pass and high-pass outputs. Analog switches
-- selected which combination of outputs were sent to the final amplifier (a
-- notch filter was created by enabling both the high and low-pass outputs
-- simultaneously)."
-- "The filter is the worst part of SID because I could not create high-gain
-- op-amps in NMOS, which were essential to a resonant filter. In addition,
-- the resistance of the FETs varied considerably with processing, so different
-- lots of SID chips had different cutoff frequency characteristics. I knew it
-- wouldn't work very well, but it was better than nothing and I didn't have
-- time to make it better."
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end sid6581;
architecture Behavioral of sid6581 is
--Implementation Digital to Analog converter
component pwm_sddac is
port (
clk_i : in std_logic; -- main clock signal, the higher the better
reset : in std_logic; -- reset input active high
dac_o : out std_logic; -- PWM output after a simple low-pass filter this is to be considered an analog signal
dac_i : in std_logic_vector(9 downto 0) -- binary input of signal to be converted
);
end component;
component pwm_sdadc is
port (
clk : in std_logic; -- main clock signal (actually the higher the better)
reset : in std_logic; --
ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted
ADC_in : in std_logic -- "analog" paddle input pin
);
end component;
-- Implementation of the SID voices (sound channels)
component sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); --
Freq_hi : in std_logic_vector(7 downto 0); --
Pw_lo : in std_logic_vector(7 downto 0); --
Pw_hi : in std_logic_vector(3 downto 0); --
Control : in std_logic_vector(7 downto 0); --
Att_dec : in std_logic_vector(7 downto 0); --
Sus_Rel : in std_logic_vector(7 downto 0); --
PA_MSB_in : in std_logic; --
PA_MSB_out : out std_logic; --
Osc : out std_logic_vector(7 downto 0); --
Env : out std_logic_vector(7 downto 0); --
voice : out std_logic_vector(11 downto 0) --
);
end component;
component sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end component;
-------------------------------------------------------------------------------
--constant <name>: <type> := <value>;
-- DC offset required to play samples, this is actually a bug of the real 6581,
-- that was converted into an advantage to play samples
constant DC_offset : std_logic_vector(13 downto 0) := "00111111111111";
-------------------------------------------------------------------------------
signal Voice_1_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_1_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_2_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_3_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Res_Filt : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Mode_Vol : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotX : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotY : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Osc3_Random : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Env3 : std_logic_vector(7 downto 0) := (others => '0');
signal do_buf : std_logic_vector(7 downto 0) := (others => '0');
signal voice_1 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_2 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_3 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_mixed : std_logic_vector(13 downto 0) := (others => '0');
signal voice_volume : std_logic_vector(35 downto 0) := (others => '0');
signal divide_0 : std_logic_vector(31 downto 0) := (others => '0');
signal voice_1_PA_MSB : std_logic := '0';
signal voice_2_PA_MSB : std_logic := '0';
signal voice_3_PA_MSB : std_logic := '0';
-------------------------------------------------------------------------------
begin
digital_to_analog: pwm_sddac
port map(
clk_i => clk_DAC,
reset => reset,
dac_i => voice_volume(17 downto 8),
dac_o => audio_out
);
paddle_x: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotX,
ADC_in => pot_x
);
paddle_y: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotY,
ADC_in => pot_y
);
sid_voice_1: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_1_Freq_lo,
Freq_hi => Voice_1_Freq_hi,
Pw_lo => Voice_1_Pw_lo,
Pw_hi => Voice_1_Pw_hi,
Control => Voice_1_Control,
Att_dec => Voice_1_Att_dec,
Sus_Rel => Voice_1_Sus_Rel,
PA_MSB_in => voice_3_PA_MSB,
PA_MSB_out => voice_1_PA_MSB,
Osc => Voice_1_Osc,
Env => Voice_1_Env,
voice => voice_1
);
sid_voice_2: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_2_Freq_lo,
Freq_hi => Voice_2_Freq_hi,
Pw_lo => Voice_2_Pw_lo,
Pw_hi => Voice_2_Pw_hi,
Control => Voice_2_Control,
Att_dec => Voice_2_Att_dec,
Sus_Rel => Voice_2_Sus_Rel,
PA_MSB_in => voice_1_PA_MSB,
PA_MSB_out => voice_2_PA_MSB,
Osc => Voice_2_Osc,
Env => Voice_2_Env,
voice => voice_2
);
sid_voice_3: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_3_Freq_lo,
Freq_hi => Voice_3_Freq_hi,
Pw_lo => Voice_3_Pw_lo,
Pw_hi => Voice_3_Pw_hi,
Control => Voice_3_Control,
Att_dec => Voice_3_Att_dec,
Sus_Rel => Voice_3_Sus_Rel,
PA_MSB_in => voice_2_PA_MSB,
PA_MSB_out => voice_3_PA_MSB,
Osc => Misc_Osc3_Random,
Env => Misc_Env3,
voice => voice_3
);
-------------------------------------------------------------------------------------
do <= do_buf;
-- SID filters
fblk: block
signal voice1_signed: signed(12 downto 0);
signal voice2_signed: signed(12 downto 0);
signal voice3_signed: signed(12 downto 0);
constant ext_in_signed: signed(12 downto 0) := to_signed(0,13);
signal filtered_audio: signed(18 downto 0);
signal tick_q1, tick_q2: std_logic;
signal input_valid: std_logic;
signal unsigned_audio: std_logic_vector(17 downto 0);
signal unsigned_filt: std_logic_vector(18 downto 0);
signal ff1: std_logic;
begin
process (clk_1MHz,reset)
begin
if reset='1' then
ff1<='0';
else
if rising_edge(clk_1MHz) then
ff1<=not ff1;
end if;
end if;
end process;
process(clk32)
begin
if rising_edge(clk32) then
tick_q1 <= ff1;
tick_q2 <= tick_q1;
end if;
end process;
input_valid<='1' when tick_q1 /=tick_q2 else '0';
voice1_signed <= signed(voice_1 & "0") - 4096;
voice2_signed <= signed(voice_2 & "0") - 4096;
voice3_signed <= signed(voice_3 & "0") - 4096;
filters: sid_filters
port map (
clk => clk32,
rst => reset,
-- SID registers.
Fc_lo => Filter_Fc_lo,
Fc_hi => Filter_Fc_hi,
Res_Filt => Filter_Res_Filt,
Mode_Vol => Filter_Mode_Vol,
-- Voices - resampled to 13 bit
voice1 => voice1_signed,
voice2 => voice2_signed,
voice3 => voice3_signed,
--
input_valid => input_valid,
ext_in => ext_in_signed,
sound => filtered_audio,
valid => open
);
unsigned_filt <= std_logic_vector(filtered_audio + "1000000000000000000");
unsigned_audio <= unsigned_filt(18 downto 1);
audio_data <= unsigned_audio;
end block;
-- Register decoding
register_decoder:process(clk32)
begin
if rising_edge(clk32) then
if (reset = '1') then
--------------------------------------- Voice-1
Voice_1_Freq_lo <= (others => '0');
Voice_1_Freq_hi <= (others => '0');
Voice_1_Pw_lo <= (others => '0');
Voice_1_Pw_hi <= (others => '0');
Voice_1_Control <= (others => '0');
Voice_1_Att_dec <= (others => '0');
Voice_1_Sus_Rel <= (others => '0');
--------------------------------------- Voice-2
Voice_2_Freq_lo <= (others => '0');
Voice_2_Freq_hi <= (others => '0');
Voice_2_Pw_lo <= (others => '0');
Voice_2_Pw_hi <= (others => '0');
Voice_2_Control <= (others => '0');
Voice_2_Att_dec <= (others => '0');
Voice_2_Sus_Rel <= (others => '0');
--------------------------------------- Voice-3
Voice_3_Freq_lo <= (others => '0');
Voice_3_Freq_hi <= (others => '0');
Voice_3_Pw_lo <= (others => '0');
Voice_3_Pw_hi <= (others => '0');
Voice_3_Control <= (others => '0');
Voice_3_Att_dec <= (others => '0');
Voice_3_Sus_Rel <= (others => '0');
--------------------------------------- Filter & volume
Filter_Fc_lo <= (others => '0');
Filter_Fc_hi <= (others => '0');
Filter_Res_Filt <= (others => '0');
Filter_Mode_Vol <= (others => '0');
else
Voice_1_Freq_lo <= Voice_1_Freq_lo;
Voice_1_Freq_hi <= Voice_1_Freq_hi;
Voice_1_Pw_lo <= Voice_1_Pw_lo;
Voice_1_Pw_hi <= Voice_1_Pw_hi;
Voice_1_Control <= Voice_1_Control;
Voice_1_Att_dec <= Voice_1_Att_dec;
Voice_1_Sus_Rel <= Voice_1_Sus_Rel;
Voice_2_Freq_lo <= Voice_2_Freq_lo;
Voice_2_Freq_hi <= Voice_2_Freq_hi;
Voice_2_Pw_lo <= Voice_2_Pw_lo;
Voice_2_Pw_hi <= Voice_2_Pw_hi;
Voice_2_Control <= Voice_2_Control;
Voice_2_Att_dec <= Voice_2_Att_dec;
Voice_2_Sus_Rel <= Voice_2_Sus_Rel;
Voice_3_Freq_lo <= Voice_3_Freq_lo;
Voice_3_Freq_hi <= Voice_3_Freq_hi;
Voice_3_Pw_lo <= Voice_3_Pw_lo;
Voice_3_Pw_hi <= Voice_3_Pw_hi;
Voice_3_Control <= Voice_3_Control;
Voice_3_Att_dec <= Voice_3_Att_dec;
Voice_3_Sus_Rel <= Voice_3_Sus_Rel;
Filter_Fc_lo <= Filter_Fc_lo;
Filter_Fc_hi <= Filter_Fc_hi;
Filter_Res_Filt <= Filter_Res_Filt;
Filter_Mode_Vol <= Filter_Mode_Vol;
do_buf <= (others => '0');
if (cs='1') then
if (we='1') then -- Write to SID-register
------------------------
case addr is
-------------------------------------- Voice-1
when "00000" => Voice_1_Freq_lo <= di;
when "00001" => Voice_1_Freq_hi <= di;
when "00010" => Voice_1_Pw_lo <= di;
when "00011" => Voice_1_Pw_hi <= di(3 downto 0);
when "00100" => Voice_1_Control <= di;
when "00101" => Voice_1_Att_dec <= di;
when "00110" => Voice_1_Sus_Rel <= di;
--------------------------------------- Voice-2
when "00111" => Voice_2_Freq_lo <= di;
when "01000" => Voice_2_Freq_hi <= di;
when "01001" => Voice_2_Pw_lo <= di;
when "01010" => Voice_2_Pw_hi <= di(3 downto 0);
when "01011" => Voice_2_Control <= di;
when "01100" => Voice_2_Att_dec <= di;
when "01101" => Voice_2_Sus_Rel <= di;
--------------------------------------- Voice-3
when "01110" => Voice_3_Freq_lo <= di;
when "01111" => Voice_3_Freq_hi <= di;
when "10000" => Voice_3_Pw_lo <= di;
when "10001" => Voice_3_Pw_hi <= di(3 downto 0);
when "10010" => Voice_3_Control <= di;
when "10011" => Voice_3_Att_dec <= di;
when "10100" => Voice_3_Sus_Rel <= di;
--------------------------------------- Filter & volume
when "10101" => Filter_Fc_lo <= di;
when "10110" => Filter_Fc_hi <= di;
when "10111" => Filter_Res_Filt <= di;
when "11000" => Filter_Mode_Vol <= di;
--------------------------------------
when others => null;
end case;
else -- Read from SID-register
-------------------------
--case CONV_INTEGER(addr) is
case addr is
-------------------------------------- Misc
when "11001" => do_buf <= Misc_PotX;
when "11010" => do_buf <= Misc_PotY;
when "11011" => do_buf <= Misc_Osc3_Random;
when "11100" => do_buf <= Misc_Env3;
--------------------------------------
-- when others => null;
when others => do_buf <= (others => '0');
end case;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementation, use multiplexed channels
--
--
-- "The Filter was a classic multi-mode (state variable) VCF design. There was
-- no way to create a variable transconductance amplifier in our NMOS process,
-- so I simply used FETs as voltage-controlled resistors to control the cutoff
-- frequency. An 11-bit D/A converter generates the control voltage for the
-- FETs (it's actually a 12-bit D/A, but the LSB had no audible affect so I
-- disconnected it!)."
-- "Filter resonance was controlled by a 4-bit weighted resistor ladder. Each
-- bit would turn on one of the weighted resistors and allow a portion of the
-- output to feed back to the input. The state-variable design provided
-- simultaneous low-pass, band-pass and high-pass outputs. Analog switches
-- selected which combination of outputs were sent to the final amplifier (a
-- notch filter was created by enabling both the high and low-pass outputs
-- simultaneously)."
-- "The filter is the worst part of SID because I could not create high-gain
-- op-amps in NMOS, which were essential to a resonant filter. In addition,
-- the resistance of the FETs varied considerably with processing, so different
-- lots of SID chips had different cutoff frequency characteristics. I knew it
-- wouldn't work very well, but it was better than nothing and I didn't have
-- time to make it better."
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end sid6581;
architecture Behavioral of sid6581 is
--Implementation Digital to Analog converter
component pwm_sddac is
port (
clk_i : in std_logic; -- main clock signal, the higher the better
reset : in std_logic; -- reset input active high
dac_o : out std_logic; -- PWM output after a simple low-pass filter this is to be considered an analog signal
dac_i : in std_logic_vector(9 downto 0) -- binary input of signal to be converted
);
end component;
component pwm_sdadc is
port (
clk : in std_logic; -- main clock signal (actually the higher the better)
reset : in std_logic; --
ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted
ADC_in : in std_logic -- "analog" paddle input pin
);
end component;
-- Implementation of the SID voices (sound channels)
component sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); --
Freq_hi : in std_logic_vector(7 downto 0); --
Pw_lo : in std_logic_vector(7 downto 0); --
Pw_hi : in std_logic_vector(3 downto 0); --
Control : in std_logic_vector(7 downto 0); --
Att_dec : in std_logic_vector(7 downto 0); --
Sus_Rel : in std_logic_vector(7 downto 0); --
PA_MSB_in : in std_logic; --
PA_MSB_out : out std_logic; --
Osc : out std_logic_vector(7 downto 0); --
Env : out std_logic_vector(7 downto 0); --
voice : out std_logic_vector(11 downto 0) --
);
end component;
component sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end component;
-------------------------------------------------------------------------------
--constant <name>: <type> := <value>;
-- DC offset required to play samples, this is actually a bug of the real 6581,
-- that was converted into an advantage to play samples
constant DC_offset : std_logic_vector(13 downto 0) := "00111111111111";
-------------------------------------------------------------------------------
signal Voice_1_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_1_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_2_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_3_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Res_Filt : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Mode_Vol : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotX : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotY : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Osc3_Random : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Env3 : std_logic_vector(7 downto 0) := (others => '0');
signal do_buf : std_logic_vector(7 downto 0) := (others => '0');
signal voice_1 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_2 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_3 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_mixed : std_logic_vector(13 downto 0) := (others => '0');
signal voice_volume : std_logic_vector(35 downto 0) := (others => '0');
signal divide_0 : std_logic_vector(31 downto 0) := (others => '0');
signal voice_1_PA_MSB : std_logic := '0';
signal voice_2_PA_MSB : std_logic := '0';
signal voice_3_PA_MSB : std_logic := '0';
-------------------------------------------------------------------------------
begin
digital_to_analog: pwm_sddac
port map(
clk_i => clk_DAC,
reset => reset,
dac_i => voice_volume(17 downto 8),
dac_o => audio_out
);
paddle_x: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotX,
ADC_in => pot_x
);
paddle_y: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotY,
ADC_in => pot_y
);
sid_voice_1: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_1_Freq_lo,
Freq_hi => Voice_1_Freq_hi,
Pw_lo => Voice_1_Pw_lo,
Pw_hi => Voice_1_Pw_hi,
Control => Voice_1_Control,
Att_dec => Voice_1_Att_dec,
Sus_Rel => Voice_1_Sus_Rel,
PA_MSB_in => voice_3_PA_MSB,
PA_MSB_out => voice_1_PA_MSB,
Osc => Voice_1_Osc,
Env => Voice_1_Env,
voice => voice_1
);
sid_voice_2: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_2_Freq_lo,
Freq_hi => Voice_2_Freq_hi,
Pw_lo => Voice_2_Pw_lo,
Pw_hi => Voice_2_Pw_hi,
Control => Voice_2_Control,
Att_dec => Voice_2_Att_dec,
Sus_Rel => Voice_2_Sus_Rel,
PA_MSB_in => voice_1_PA_MSB,
PA_MSB_out => voice_2_PA_MSB,
Osc => Voice_2_Osc,
Env => Voice_2_Env,
voice => voice_2
);
sid_voice_3: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_3_Freq_lo,
Freq_hi => Voice_3_Freq_hi,
Pw_lo => Voice_3_Pw_lo,
Pw_hi => Voice_3_Pw_hi,
Control => Voice_3_Control,
Att_dec => Voice_3_Att_dec,
Sus_Rel => Voice_3_Sus_Rel,
PA_MSB_in => voice_2_PA_MSB,
PA_MSB_out => voice_3_PA_MSB,
Osc => Misc_Osc3_Random,
Env => Misc_Env3,
voice => voice_3
);
-------------------------------------------------------------------------------------
do <= do_buf;
-- SID filters
fblk: block
signal voice1_signed: signed(12 downto 0);
signal voice2_signed: signed(12 downto 0);
signal voice3_signed: signed(12 downto 0);
constant ext_in_signed: signed(12 downto 0) := to_signed(0,13);
signal filtered_audio: signed(18 downto 0);
signal tick_q1, tick_q2: std_logic;
signal input_valid: std_logic;
signal unsigned_audio: std_logic_vector(17 downto 0);
signal unsigned_filt: std_logic_vector(18 downto 0);
signal ff1: std_logic;
begin
process (clk_1MHz,reset)
begin
if reset='1' then
ff1<='0';
else
if rising_edge(clk_1MHz) then
ff1<=not ff1;
end if;
end if;
end process;
process(clk32)
begin
if rising_edge(clk32) then
tick_q1 <= ff1;
tick_q2 <= tick_q1;
end if;
end process;
input_valid<='1' when tick_q1 /=tick_q2 else '0';
voice1_signed <= signed(voice_1 & "0") - 4096;
voice2_signed <= signed(voice_2 & "0") - 4096;
voice3_signed <= signed(voice_3 & "0") - 4096;
filters: sid_filters
port map (
clk => clk32,
rst => reset,
-- SID registers.
Fc_lo => Filter_Fc_lo,
Fc_hi => Filter_Fc_hi,
Res_Filt => Filter_Res_Filt,
Mode_Vol => Filter_Mode_Vol,
-- Voices - resampled to 13 bit
voice1 => voice1_signed,
voice2 => voice2_signed,
voice3 => voice3_signed,
--
input_valid => input_valid,
ext_in => ext_in_signed,
sound => filtered_audio,
valid => open
);
unsigned_filt <= std_logic_vector(filtered_audio + "1000000000000000000");
unsigned_audio <= unsigned_filt(18 downto 1);
audio_data <= unsigned_audio;
end block;
-- Register decoding
register_decoder:process(clk32)
begin
if rising_edge(clk32) then
if (reset = '1') then
--------------------------------------- Voice-1
Voice_1_Freq_lo <= (others => '0');
Voice_1_Freq_hi <= (others => '0');
Voice_1_Pw_lo <= (others => '0');
Voice_1_Pw_hi <= (others => '0');
Voice_1_Control <= (others => '0');
Voice_1_Att_dec <= (others => '0');
Voice_1_Sus_Rel <= (others => '0');
--------------------------------------- Voice-2
Voice_2_Freq_lo <= (others => '0');
Voice_2_Freq_hi <= (others => '0');
Voice_2_Pw_lo <= (others => '0');
Voice_2_Pw_hi <= (others => '0');
Voice_2_Control <= (others => '0');
Voice_2_Att_dec <= (others => '0');
Voice_2_Sus_Rel <= (others => '0');
--------------------------------------- Voice-3
Voice_3_Freq_lo <= (others => '0');
Voice_3_Freq_hi <= (others => '0');
Voice_3_Pw_lo <= (others => '0');
Voice_3_Pw_hi <= (others => '0');
Voice_3_Control <= (others => '0');
Voice_3_Att_dec <= (others => '0');
Voice_3_Sus_Rel <= (others => '0');
--------------------------------------- Filter & volume
Filter_Fc_lo <= (others => '0');
Filter_Fc_hi <= (others => '0');
Filter_Res_Filt <= (others => '0');
Filter_Mode_Vol <= (others => '0');
else
Voice_1_Freq_lo <= Voice_1_Freq_lo;
Voice_1_Freq_hi <= Voice_1_Freq_hi;
Voice_1_Pw_lo <= Voice_1_Pw_lo;
Voice_1_Pw_hi <= Voice_1_Pw_hi;
Voice_1_Control <= Voice_1_Control;
Voice_1_Att_dec <= Voice_1_Att_dec;
Voice_1_Sus_Rel <= Voice_1_Sus_Rel;
Voice_2_Freq_lo <= Voice_2_Freq_lo;
Voice_2_Freq_hi <= Voice_2_Freq_hi;
Voice_2_Pw_lo <= Voice_2_Pw_lo;
Voice_2_Pw_hi <= Voice_2_Pw_hi;
Voice_2_Control <= Voice_2_Control;
Voice_2_Att_dec <= Voice_2_Att_dec;
Voice_2_Sus_Rel <= Voice_2_Sus_Rel;
Voice_3_Freq_lo <= Voice_3_Freq_lo;
Voice_3_Freq_hi <= Voice_3_Freq_hi;
Voice_3_Pw_lo <= Voice_3_Pw_lo;
Voice_3_Pw_hi <= Voice_3_Pw_hi;
Voice_3_Control <= Voice_3_Control;
Voice_3_Att_dec <= Voice_3_Att_dec;
Voice_3_Sus_Rel <= Voice_3_Sus_Rel;
Filter_Fc_lo <= Filter_Fc_lo;
Filter_Fc_hi <= Filter_Fc_hi;
Filter_Res_Filt <= Filter_Res_Filt;
Filter_Mode_Vol <= Filter_Mode_Vol;
do_buf <= (others => '0');
if (cs='1') then
if (we='1') then -- Write to SID-register
------------------------
case addr is
-------------------------------------- Voice-1
when "00000" => Voice_1_Freq_lo <= di;
when "00001" => Voice_1_Freq_hi <= di;
when "00010" => Voice_1_Pw_lo <= di;
when "00011" => Voice_1_Pw_hi <= di(3 downto 0);
when "00100" => Voice_1_Control <= di;
when "00101" => Voice_1_Att_dec <= di;
when "00110" => Voice_1_Sus_Rel <= di;
--------------------------------------- Voice-2
when "00111" => Voice_2_Freq_lo <= di;
when "01000" => Voice_2_Freq_hi <= di;
when "01001" => Voice_2_Pw_lo <= di;
when "01010" => Voice_2_Pw_hi <= di(3 downto 0);
when "01011" => Voice_2_Control <= di;
when "01100" => Voice_2_Att_dec <= di;
when "01101" => Voice_2_Sus_Rel <= di;
--------------------------------------- Voice-3
when "01110" => Voice_3_Freq_lo <= di;
when "01111" => Voice_3_Freq_hi <= di;
when "10000" => Voice_3_Pw_lo <= di;
when "10001" => Voice_3_Pw_hi <= di(3 downto 0);
when "10010" => Voice_3_Control <= di;
when "10011" => Voice_3_Att_dec <= di;
when "10100" => Voice_3_Sus_Rel <= di;
--------------------------------------- Filter & volume
when "10101" => Filter_Fc_lo <= di;
when "10110" => Filter_Fc_hi <= di;
when "10111" => Filter_Res_Filt <= di;
when "11000" => Filter_Mode_Vol <= di;
--------------------------------------
when others => null;
end case;
else -- Read from SID-register
-------------------------
--case CONV_INTEGER(addr) is
case addr is
-------------------------------------- Misc
when "11001" => do_buf <= Misc_PotX;
when "11010" => do_buf <= Misc_PotY;
when "11011" => do_buf <= Misc_Osc3_Random;
when "11100" => do_buf <= Misc_Env3;
--------------------------------------
-- when others => null;
when others => do_buf <= (others => '0');
end case;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementation, use multiplexed channels
--
--
-- "The Filter was a classic multi-mode (state variable) VCF design. There was
-- no way to create a variable transconductance amplifier in our NMOS process,
-- so I simply used FETs as voltage-controlled resistors to control the cutoff
-- frequency. An 11-bit D/A converter generates the control voltage for the
-- FETs (it's actually a 12-bit D/A, but the LSB had no audible affect so I
-- disconnected it!)."
-- "Filter resonance was controlled by a 4-bit weighted resistor ladder. Each
-- bit would turn on one of the weighted resistors and allow a portion of the
-- output to feed back to the input. The state-variable design provided
-- simultaneous low-pass, band-pass and high-pass outputs. Analog switches
-- selected which combination of outputs were sent to the final amplifier (a
-- notch filter was created by enabling both the high and low-pass outputs
-- simultaneously)."
-- "The filter is the worst part of SID because I could not create high-gain
-- op-amps in NMOS, which were essential to a resonant filter. In addition,
-- the resistance of the FETs varied considerably with processing, so different
-- lots of SID chips had different cutoff frequency characteristics. I knew it
-- wouldn't work very well, but it was better than nothing and I didn't have
-- time to make it better."
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end sid6581;
architecture Behavioral of sid6581 is
--Implementation Digital to Analog converter
component pwm_sddac is
port (
clk_i : in std_logic; -- main clock signal, the higher the better
reset : in std_logic; -- reset input active high
dac_o : out std_logic; -- PWM output after a simple low-pass filter this is to be considered an analog signal
dac_i : in std_logic_vector(9 downto 0) -- binary input of signal to be converted
);
end component;
component pwm_sdadc is
port (
clk : in std_logic; -- main clock signal (actually the higher the better)
reset : in std_logic; --
ADC_out : out std_logic_vector(7 downto 0); -- binary input of signal to be converted
ADC_in : in std_logic -- "analog" paddle input pin
);
end component;
-- Implementation of the SID voices (sound channels)
component sid_voice is
port (
clk_1MHz : in std_logic; -- this line drives the oscilator
reset : in std_logic; -- active high signal (i.e. registers are reset when reset=1)
Freq_lo : in std_logic_vector(7 downto 0); --
Freq_hi : in std_logic_vector(7 downto 0); --
Pw_lo : in std_logic_vector(7 downto 0); --
Pw_hi : in std_logic_vector(3 downto 0); --
Control : in std_logic_vector(7 downto 0); --
Att_dec : in std_logic_vector(7 downto 0); --
Sus_Rel : in std_logic_vector(7 downto 0); --
PA_MSB_in : in std_logic; --
PA_MSB_out : out std_logic; --
Osc : out std_logic_vector(7 downto 0); --
Env : out std_logic_vector(7 downto 0); --
voice : out std_logic_vector(11 downto 0) --
);
end component;
component sid_filters is
port (
clk: in std_logic; -- At least 12Mhz
rst: in std_logic;
-- SID registers.
Fc_lo: in std_logic_vector(7 downto 0);
Fc_hi: in std_logic_vector(7 downto 0);
Res_Filt: in std_logic_vector(7 downto 0);
Mode_Vol: in std_logic_vector(7 downto 0);
-- Voices - resampled to 13 bit
voice1: in signed(12 downto 0);
voice2: in signed(12 downto 0);
voice3: in signed(12 downto 0);
--
input_valid: in std_logic;
ext_in: in signed(12 downto 0);
sound: out signed(18 downto 0);
valid: out std_logic
);
end component;
-------------------------------------------------------------------------------
--constant <name>: <type> := <value>;
-- DC offset required to play samples, this is actually a bug of the real 6581,
-- that was converted into an advantage to play samples
constant DC_offset : std_logic_vector(13 downto 0) := "00111111111111";
-------------------------------------------------------------------------------
signal Voice_1_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_1_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_1_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_2_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Osc : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_2_Env : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Freq_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Pw_hi : std_logic_vector(3 downto 0) := (others => '0');
signal Voice_3_Control : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Att_dec : std_logic_vector(7 downto 0) := (others => '0');
signal Voice_3_Sus_Rel : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_lo : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Fc_hi : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Res_Filt : std_logic_vector(7 downto 0) := (others => '0');
signal Filter_Mode_Vol : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotX : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_PotY : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Osc3_Random : std_logic_vector(7 downto 0) := (others => '0');
signal Misc_Env3 : std_logic_vector(7 downto 0) := (others => '0');
signal do_buf : std_logic_vector(7 downto 0) := (others => '0');
signal voice_1 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_2 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_3 : std_logic_vector(11 downto 0) := (others => '0');
signal voice_mixed : std_logic_vector(13 downto 0) := (others => '0');
signal voice_volume : std_logic_vector(35 downto 0) := (others => '0');
signal divide_0 : std_logic_vector(31 downto 0) := (others => '0');
signal voice_1_PA_MSB : std_logic := '0';
signal voice_2_PA_MSB : std_logic := '0';
signal voice_3_PA_MSB : std_logic := '0';
-------------------------------------------------------------------------------
begin
digital_to_analog: pwm_sddac
port map(
clk_i => clk_DAC,
reset => reset,
dac_i => voice_volume(17 downto 8),
dac_o => audio_out
);
paddle_x: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotX,
ADC_in => pot_x
);
paddle_y: pwm_sdadc
port map (
clk => clk_1MHz,
reset => reset,
ADC_out => Misc_PotY,
ADC_in => pot_y
);
sid_voice_1: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_1_Freq_lo,
Freq_hi => Voice_1_Freq_hi,
Pw_lo => Voice_1_Pw_lo,
Pw_hi => Voice_1_Pw_hi,
Control => Voice_1_Control,
Att_dec => Voice_1_Att_dec,
Sus_Rel => Voice_1_Sus_Rel,
PA_MSB_in => voice_3_PA_MSB,
PA_MSB_out => voice_1_PA_MSB,
Osc => Voice_1_Osc,
Env => Voice_1_Env,
voice => voice_1
);
sid_voice_2: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_2_Freq_lo,
Freq_hi => Voice_2_Freq_hi,
Pw_lo => Voice_2_Pw_lo,
Pw_hi => Voice_2_Pw_hi,
Control => Voice_2_Control,
Att_dec => Voice_2_Att_dec,
Sus_Rel => Voice_2_Sus_Rel,
PA_MSB_in => voice_1_PA_MSB,
PA_MSB_out => voice_2_PA_MSB,
Osc => Voice_2_Osc,
Env => Voice_2_Env,
voice => voice_2
);
sid_voice_3: sid_voice
port map(
clk_1MHz => clk_1MHz,
reset => reset,
Freq_lo => Voice_3_Freq_lo,
Freq_hi => Voice_3_Freq_hi,
Pw_lo => Voice_3_Pw_lo,
Pw_hi => Voice_3_Pw_hi,
Control => Voice_3_Control,
Att_dec => Voice_3_Att_dec,
Sus_Rel => Voice_3_Sus_Rel,
PA_MSB_in => voice_2_PA_MSB,
PA_MSB_out => voice_3_PA_MSB,
Osc => Misc_Osc3_Random,
Env => Misc_Env3,
voice => voice_3
);
-------------------------------------------------------------------------------------
do <= do_buf;
-- SID filters
fblk: block
signal voice1_signed: signed(12 downto 0);
signal voice2_signed: signed(12 downto 0);
signal voice3_signed: signed(12 downto 0);
constant ext_in_signed: signed(12 downto 0) := to_signed(0,13);
signal filtered_audio: signed(18 downto 0);
signal tick_q1, tick_q2: std_logic;
signal input_valid: std_logic;
signal unsigned_audio: std_logic_vector(17 downto 0);
signal unsigned_filt: std_logic_vector(18 downto 0);
signal ff1: std_logic;
begin
process (clk_1MHz,reset)
begin
if reset='1' then
ff1<='0';
else
if rising_edge(clk_1MHz) then
ff1<=not ff1;
end if;
end if;
end process;
process(clk32)
begin
if rising_edge(clk32) then
tick_q1 <= ff1;
tick_q2 <= tick_q1;
end if;
end process;
input_valid<='1' when tick_q1 /=tick_q2 else '0';
voice1_signed <= signed(voice_1 & "0") - 4096;
voice2_signed <= signed(voice_2 & "0") - 4096;
voice3_signed <= signed(voice_3 & "0") - 4096;
filters: sid_filters
port map (
clk => clk32,
rst => reset,
-- SID registers.
Fc_lo => Filter_Fc_lo,
Fc_hi => Filter_Fc_hi,
Res_Filt => Filter_Res_Filt,
Mode_Vol => Filter_Mode_Vol,
-- Voices - resampled to 13 bit
voice1 => voice1_signed,
voice2 => voice2_signed,
voice3 => voice3_signed,
--
input_valid => input_valid,
ext_in => ext_in_signed,
sound => filtered_audio,
valid => open
);
unsigned_filt <= std_logic_vector(filtered_audio + "1000000000000000000");
unsigned_audio <= unsigned_filt(18 downto 1);
audio_data <= unsigned_audio;
end block;
-- Register decoding
register_decoder:process(clk32)
begin
if rising_edge(clk32) then
if (reset = '1') then
--------------------------------------- Voice-1
Voice_1_Freq_lo <= (others => '0');
Voice_1_Freq_hi <= (others => '0');
Voice_1_Pw_lo <= (others => '0');
Voice_1_Pw_hi <= (others => '0');
Voice_1_Control <= (others => '0');
Voice_1_Att_dec <= (others => '0');
Voice_1_Sus_Rel <= (others => '0');
--------------------------------------- Voice-2
Voice_2_Freq_lo <= (others => '0');
Voice_2_Freq_hi <= (others => '0');
Voice_2_Pw_lo <= (others => '0');
Voice_2_Pw_hi <= (others => '0');
Voice_2_Control <= (others => '0');
Voice_2_Att_dec <= (others => '0');
Voice_2_Sus_Rel <= (others => '0');
--------------------------------------- Voice-3
Voice_3_Freq_lo <= (others => '0');
Voice_3_Freq_hi <= (others => '0');
Voice_3_Pw_lo <= (others => '0');
Voice_3_Pw_hi <= (others => '0');
Voice_3_Control <= (others => '0');
Voice_3_Att_dec <= (others => '0');
Voice_3_Sus_Rel <= (others => '0');
--------------------------------------- Filter & volume
Filter_Fc_lo <= (others => '0');
Filter_Fc_hi <= (others => '0');
Filter_Res_Filt <= (others => '0');
Filter_Mode_Vol <= (others => '0');
else
Voice_1_Freq_lo <= Voice_1_Freq_lo;
Voice_1_Freq_hi <= Voice_1_Freq_hi;
Voice_1_Pw_lo <= Voice_1_Pw_lo;
Voice_1_Pw_hi <= Voice_1_Pw_hi;
Voice_1_Control <= Voice_1_Control;
Voice_1_Att_dec <= Voice_1_Att_dec;
Voice_1_Sus_Rel <= Voice_1_Sus_Rel;
Voice_2_Freq_lo <= Voice_2_Freq_lo;
Voice_2_Freq_hi <= Voice_2_Freq_hi;
Voice_2_Pw_lo <= Voice_2_Pw_lo;
Voice_2_Pw_hi <= Voice_2_Pw_hi;
Voice_2_Control <= Voice_2_Control;
Voice_2_Att_dec <= Voice_2_Att_dec;
Voice_2_Sus_Rel <= Voice_2_Sus_Rel;
Voice_3_Freq_lo <= Voice_3_Freq_lo;
Voice_3_Freq_hi <= Voice_3_Freq_hi;
Voice_3_Pw_lo <= Voice_3_Pw_lo;
Voice_3_Pw_hi <= Voice_3_Pw_hi;
Voice_3_Control <= Voice_3_Control;
Voice_3_Att_dec <= Voice_3_Att_dec;
Voice_3_Sus_Rel <= Voice_3_Sus_Rel;
Filter_Fc_lo <= Filter_Fc_lo;
Filter_Fc_hi <= Filter_Fc_hi;
Filter_Res_Filt <= Filter_Res_Filt;
Filter_Mode_Vol <= Filter_Mode_Vol;
do_buf <= (others => '0');
if (cs='1') then
if (we='1') then -- Write to SID-register
------------------------
case addr is
-------------------------------------- Voice-1
when "00000" => Voice_1_Freq_lo <= di;
when "00001" => Voice_1_Freq_hi <= di;
when "00010" => Voice_1_Pw_lo <= di;
when "00011" => Voice_1_Pw_hi <= di(3 downto 0);
when "00100" => Voice_1_Control <= di;
when "00101" => Voice_1_Att_dec <= di;
when "00110" => Voice_1_Sus_Rel <= di;
--------------------------------------- Voice-2
when "00111" => Voice_2_Freq_lo <= di;
when "01000" => Voice_2_Freq_hi <= di;
when "01001" => Voice_2_Pw_lo <= di;
when "01010" => Voice_2_Pw_hi <= di(3 downto 0);
when "01011" => Voice_2_Control <= di;
when "01100" => Voice_2_Att_dec <= di;
when "01101" => Voice_2_Sus_Rel <= di;
--------------------------------------- Voice-3
when "01110" => Voice_3_Freq_lo <= di;
when "01111" => Voice_3_Freq_hi <= di;
when "10000" => Voice_3_Pw_lo <= di;
when "10001" => Voice_3_Pw_hi <= di(3 downto 0);
when "10010" => Voice_3_Control <= di;
when "10011" => Voice_3_Att_dec <= di;
when "10100" => Voice_3_Sus_Rel <= di;
--------------------------------------- Filter & volume
when "10101" => Filter_Fc_lo <= di;
when "10110" => Filter_Fc_hi <= di;
when "10111" => Filter_Res_Filt <= di;
when "11000" => Filter_Mode_Vol <= di;
--------------------------------------
when others => null;
end case;
else -- Read from SID-register
-------------------------
--case CONV_INTEGER(addr) is
case addr is
-------------------------------------- Misc
when "11001" => do_buf <= Misc_PotX;
when "11010" => do_buf <= Misc_PotY;
when "11011" => do_buf <= Misc_Osc3_Random;
when "11100" => do_buf <= Misc_Env3;
--------------------------------------
-- when others => null;
when others => do_buf <= (others => '0');
end case;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY parity8 IS
PORT(
byte : IN std_logic_vector(7 downto 0);
paritybit : OUT std_logic
);
END parity8;
ARCHITECTURE behavior OF parity8 IS
BEGIN
paritybit <= byte(7) XOR byte(6) XOR byte(5) XOR byte(4) XOR byte(3) XOR byte(2) XOR byte(1) XOR byte(0);
END behavior;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:52:50 10/26/2009
-- Design Name:
-- Module Name: OZ-3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity OZ-3 is
end OZ-3;
architecture Behavioral of OZ-3 is
begin
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:52:50 10/26/2009
-- Design Name:
-- Module Name: OZ-3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity OZ-3 is
end OZ-3;
architecture Behavioral of OZ-3 is
begin
end Behavioral;
|
entity func7 is
end entity;
architecture test of func7 is
type int_vector is array (natural range <>) of integer;
subtype int_vec_3 is int_vector(0 to 2);
function get_ints(a, b, c : integer) return int_vec_3 is
begin
return int_vec_3'(a, b, c);
end function;
begin
process is
variable v : int_vec_3;
begin
v := get_ints(1, 2, 3);
assert v = (1, 2, 3);
assert get_ints(4, 5, 6) = (4, 5, 6);
wait;
end process;
end architecture;
|
entity func7 is
end entity;
architecture test of func7 is
type int_vector is array (natural range <>) of integer;
subtype int_vec_3 is int_vector(0 to 2);
function get_ints(a, b, c : integer) return int_vec_3 is
begin
return int_vec_3'(a, b, c);
end function;
begin
process is
variable v : int_vec_3;
begin
v := get_ints(1, 2, 3);
assert v = (1, 2, 3);
assert get_ints(4, 5, 6) = (4, 5, 6);
wait;
end process;
end architecture;
|
entity func7 is
end entity;
architecture test of func7 is
type int_vector is array (natural range <>) of integer;
subtype int_vec_3 is int_vector(0 to 2);
function get_ints(a, b, c : integer) return int_vec_3 is
begin
return int_vec_3'(a, b, c);
end function;
begin
process is
variable v : int_vec_3;
begin
v := get_ints(1, 2, 3);
assert v = (1, 2, 3);
assert get_ints(4, 5, 6) = (4, 5, 6);
wait;
end process;
end architecture;
|
entity func7 is
end entity;
architecture test of func7 is
type int_vector is array (natural range <>) of integer;
subtype int_vec_3 is int_vector(0 to 2);
function get_ints(a, b, c : integer) return int_vec_3 is
begin
return int_vec_3'(a, b, c);
end function;
begin
process is
variable v : int_vec_3;
begin
v := get_ints(1, 2, 3);
assert v = (1, 2, 3);
assert get_ints(4, 5, 6) = (4, 5, 6);
wait;
end process;
end architecture;
|
entity func7 is
end entity;
architecture test of func7 is
type int_vector is array (natural range <>) of integer;
subtype int_vec_3 is int_vector(0 to 2);
function get_ints(a, b, c : integer) return int_vec_3 is
begin
return int_vec_3'(a, b, c);
end function;
begin
process is
variable v : int_vec_3;
begin
v := get_ints(1, 2, 3);
assert v = (1, 2, 3);
assert get_ints(4, 5, 6) = (4, 5, 6);
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.qr_pack.all;
entity qr_wrapper_wrapper_stimuli is
port (
clk : in std_logic;
rst_n : in std_logic;
reduced_matrix : out std_logic; --! Divides by two the order of matrices involved
start : out std_logic; --! Starts algorithm, beginning with reading of input ports
request_out : out std_logic; --! Requests output vectors
valid_out : in std_logic; --! '1' if there is an available valid output
ready : in std_logic; --! '1' if the hardware is IDLE (waiting for start or request_out)
in_A_r : out std_logic_vector(N_G*WORD_WIDTH_G - 1 downto 0);
in_A_i : out std_logic_vector(N_G*WORD_WIDTH_G - 1 downto 0)
);
end qr_wrapper_wrapper_stimuli;
architecture behav of qr_wrapper_wrapper_stimuli is
type fsm_type is (IDLE, START_STATE, D0, D1, D2, D3, WAIT_FOR_VALID, REQUEST_OUTPUT, WAIT_FOR_READY);
signal state : fsm_type := IDLE;
signal rand_out_1, rand_out_2 : std_logic_vector(N_G*WORD_WIDTH_G - 1 downto 0);
component lfsr
generic (
width : integer;
seed : integer);
port (
clk : in std_logic;
rand_out : out std_logic_vector(width-1 downto 0));
end component;
begin -- behav
lfsr_1 : lfsr
generic map (
width => N_G*WORD_WIDTH_G,
seed => 24242309)
port map (
clk => clk,
rand_out => rand_out_1);
lfsr_2 : lfsr
generic map (
width => N_G*WORD_WIDTH_G,
seed => 3246236)
port map (
clk => clk,
rand_out => rand_out_2);
reduced_matrix <= '0';
in_A_r <= rand_out_1;
in_A_i <= rand_out_2;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
state <= IDLE;
start <= '0';
request_out <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
case state is
when IDLE =>
if ready = '1' then
state <= START_STATE;
end if;
when START_STATE =>
start <= '1';
state <= D0;
when D0 =>
start <= '0';
state <= D1;
when D1 =>
state <= D2;
when D2 =>
state <= D3;
when D3 =>
state <= WAIT_FOR_VALID;
when WAIT_FOR_VALID =>
if ready = '1' then
state <= REQUEST_OUTPUT;
end if;
when REQUEST_OUTPUT =>
request_out <= '1';
state <= WAIT_FOR_READY;
when WAIT_FOR_READY =>
request_out <= '0';
if ready = '1' then
state <= START_STATE;
end if;
end case;
end if;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.qr_pack.all;
entity qr_wrapper_wrapper_stimuli is
port (
clk : in std_logic;
rst_n : in std_logic;
reduced_matrix : out std_logic; --! Divides by two the order of matrices involved
start : out std_logic; --! Starts algorithm, beginning with reading of input ports
request_out : out std_logic; --! Requests output vectors
valid_out : in std_logic; --! '1' if there is an available valid output
ready : in std_logic; --! '1' if the hardware is IDLE (waiting for start or request_out)
in_A_r : out std_logic_vector(N_G*WORD_WIDTH_G - 1 downto 0);
in_A_i : out std_logic_vector(N_G*WORD_WIDTH_G - 1 downto 0)
);
end qr_wrapper_wrapper_stimuli;
architecture behav of qr_wrapper_wrapper_stimuli is
type fsm_type is (IDLE, START_STATE, D0, D1, D2, D3, WAIT_FOR_VALID, REQUEST_OUTPUT, WAIT_FOR_READY);
signal state : fsm_type := IDLE;
signal rand_out_1, rand_out_2 : std_logic_vector(N_G*WORD_WIDTH_G - 1 downto 0);
component lfsr
generic (
width : integer;
seed : integer);
port (
clk : in std_logic;
rand_out : out std_logic_vector(width-1 downto 0));
end component;
begin -- behav
lfsr_1 : lfsr
generic map (
width => N_G*WORD_WIDTH_G,
seed => 24242309)
port map (
clk => clk,
rand_out => rand_out_1);
lfsr_2 : lfsr
generic map (
width => N_G*WORD_WIDTH_G,
seed => 3246236)
port map (
clk => clk,
rand_out => rand_out_2);
reduced_matrix <= '0';
in_A_r <= rand_out_1;
in_A_i <= rand_out_2;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
state <= IDLE;
start <= '0';
request_out <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
case state is
when IDLE =>
if ready = '1' then
state <= START_STATE;
end if;
when START_STATE =>
start <= '1';
state <= D0;
when D0 =>
start <= '0';
state <= D1;
when D1 =>
state <= D2;
when D2 =>
state <= D3;
when D3 =>
state <= WAIT_FOR_VALID;
when WAIT_FOR_VALID =>
if ready = '1' then
state <= REQUEST_OUTPUT;
end if;
when REQUEST_OUTPUT =>
request_out <= '1';
state <= WAIT_FOR_READY;
when WAIT_FOR_READY =>
request_out <= '0';
if ready = '1' then
state <= START_STATE;
end if;
end case;
end if;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.qr_pack.all;
entity qr_wrapper_wrapper_stimuli is
port (
clk : in std_logic;
rst_n : in std_logic;
reduced_matrix : out std_logic; --! Divides by two the order of matrices involved
start : out std_logic; --! Starts algorithm, beginning with reading of input ports
request_out : out std_logic; --! Requests output vectors
valid_out : in std_logic; --! '1' if there is an available valid output
ready : in std_logic; --! '1' if the hardware is IDLE (waiting for start or request_out)
in_A_r : out std_logic_vector(N_G*WORD_WIDTH_G - 1 downto 0);
in_A_i : out std_logic_vector(N_G*WORD_WIDTH_G - 1 downto 0)
);
end qr_wrapper_wrapper_stimuli;
architecture behav of qr_wrapper_wrapper_stimuli is
type fsm_type is (IDLE, START_STATE, D0, D1, D2, D3, WAIT_FOR_VALID, REQUEST_OUTPUT, WAIT_FOR_READY);
signal state : fsm_type := IDLE;
signal rand_out_1, rand_out_2 : std_logic_vector(N_G*WORD_WIDTH_G - 1 downto 0);
component lfsr
generic (
width : integer;
seed : integer);
port (
clk : in std_logic;
rand_out : out std_logic_vector(width-1 downto 0));
end component;
begin -- behav
lfsr_1 : lfsr
generic map (
width => N_G*WORD_WIDTH_G,
seed => 24242309)
port map (
clk => clk,
rand_out => rand_out_1);
lfsr_2 : lfsr
generic map (
width => N_G*WORD_WIDTH_G,
seed => 3246236)
port map (
clk => clk,
rand_out => rand_out_2);
reduced_matrix <= '0';
in_A_r <= rand_out_1;
in_A_i <= rand_out_2;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
state <= IDLE;
start <= '0';
request_out <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
case state is
when IDLE =>
if ready = '1' then
state <= START_STATE;
end if;
when START_STATE =>
start <= '1';
state <= D0;
when D0 =>
start <= '0';
state <= D1;
when D1 =>
state <= D2;
when D2 =>
state <= D3;
when D3 =>
state <= WAIT_FOR_VALID;
when WAIT_FOR_VALID =>
if ready = '1' then
state <= REQUEST_OUTPUT;
end if;
when REQUEST_OUTPUT =>
request_out <= '1';
state <= WAIT_FOR_READY;
when WAIT_FOR_READY =>
request_out <= '0';
if ready = '1' then
state <= START_STATE;
end if;
end case;
end if;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.qr_pack.all;
entity qr_wrapper_wrapper_stimuli is
port (
clk : in std_logic;
rst_n : in std_logic;
reduced_matrix : out std_logic; --! Divides by two the order of matrices involved
start : out std_logic; --! Starts algorithm, beginning with reading of input ports
request_out : out std_logic; --! Requests output vectors
valid_out : in std_logic; --! '1' if there is an available valid output
ready : in std_logic; --! '1' if the hardware is IDLE (waiting for start or request_out)
in_A_r : out std_logic_vector(N_G*WORD_WIDTH_G - 1 downto 0);
in_A_i : out std_logic_vector(N_G*WORD_WIDTH_G - 1 downto 0)
);
end qr_wrapper_wrapper_stimuli;
architecture behav of qr_wrapper_wrapper_stimuli is
type fsm_type is (IDLE, START_STATE, D0, D1, D2, D3, WAIT_FOR_VALID, REQUEST_OUTPUT, WAIT_FOR_READY);
signal state : fsm_type := IDLE;
signal rand_out_1, rand_out_2 : std_logic_vector(N_G*WORD_WIDTH_G - 1 downto 0);
component lfsr
generic (
width : integer;
seed : integer);
port (
clk : in std_logic;
rand_out : out std_logic_vector(width-1 downto 0));
end component;
begin -- behav
lfsr_1 : lfsr
generic map (
width => N_G*WORD_WIDTH_G,
seed => 24242309)
port map (
clk => clk,
rand_out => rand_out_1);
lfsr_2 : lfsr
generic map (
width => N_G*WORD_WIDTH_G,
seed => 3246236)
port map (
clk => clk,
rand_out => rand_out_2);
reduced_matrix <= '0';
in_A_r <= rand_out_1;
in_A_i <= rand_out_2;
process (clk, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
state <= IDLE;
start <= '0';
request_out <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
case state is
when IDLE =>
if ready = '1' then
state <= START_STATE;
end if;
when START_STATE =>
start <= '1';
state <= D0;
when D0 =>
start <= '0';
state <= D1;
when D1 =>
state <= D2;
when D2 =>
state <= D3;
when D3 =>
state <= WAIT_FOR_VALID;
when WAIT_FOR_VALID =>
if ready = '1' then
state <= REQUEST_OUTPUT;
end if;
when REQUEST_OUTPUT =>
request_out <= '1';
state <= WAIT_FOR_READY;
when WAIT_FOR_READY =>
request_out <= '0';
if ready = '1' then
state <= START_STATE;
end if;
end case;
end if;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
entity block02 is
port (q : out std_logic;
d : std_logic;
clk : std_logic);
end block02;
architecture behav of block02 is
begin
b1 : block
signal s : std_logic;
begin
process (clk) is
begin
if rising_edge (clk) then
s <= d;
end if;
end process;
q <= s;
end block b1;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_254 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_254;
architecture augh of add_254 is
signal carry_inA : std_logic_vector(28 downto 0);
signal carry_inB : std_logic_vector(28 downto 0);
signal carry_res : std_logic_vector(28 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(27 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_254 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_254;
architecture augh of add_254 is
signal carry_inA : std_logic_vector(28 downto 0);
signal carry_inB : std_logic_vector(28 downto 0);
signal carry_res : std_logic_vector(28 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(27 downto 1);
end architecture;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity sand_nov is
port(
clock: in std_logic;
input: in std_logic_vector(10 downto 0);
output: out std_logic_vector(8 downto 0)
);
end sand_nov;
architecture behaviour of sand_nov is
constant st0: std_logic_vector(4 downto 0) := "00111";
constant st1: std_logic_vector(4 downto 0) := "11011";
constant st2: std_logic_vector(4 downto 0) := "11010";
constant st3: std_logic_vector(4 downto 0) := "11000";
constant st4: std_logic_vector(4 downto 0) := "11001";
constant st5: std_logic_vector(4 downto 0) := "00011";
constant st6: std_logic_vector(4 downto 0) := "11100";
constant st7: std_logic_vector(4 downto 0) := "01111";
constant st8: std_logic_vector(4 downto 0) := "00000";
constant st9: std_logic_vector(4 downto 0) := "10111";
constant st10: std_logic_vector(4 downto 0) := "10100";
constant st11: std_logic_vector(4 downto 0) := "01000";
constant st12: std_logic_vector(4 downto 0) := "00100";
constant st13: std_logic_vector(4 downto 0) := "00101";
constant st14: std_logic_vector(4 downto 0) := "11110";
constant st15: std_logic_vector(4 downto 0) := "10011";
constant st16: std_logic_vector(4 downto 0) := "01001";
constant st17: std_logic_vector(4 downto 0) := "00110";
constant st18: std_logic_vector(4 downto 0) := "11101";
constant st19: std_logic_vector(4 downto 0) := "00010";
constant st20: std_logic_vector(4 downto 0) := "11111";
constant st21: std_logic_vector(4 downto 0) := "10000";
constant st22: std_logic_vector(4 downto 0) := "01010";
constant st23: std_logic_vector(4 downto 0) := "10101";
constant st24: std_logic_vector(4 downto 0) := "01011";
constant st25: std_logic_vector(4 downto 0) := "01100";
constant st26: std_logic_vector(4 downto 0) := "10001";
constant st27: std_logic_vector(4 downto 0) := "10110";
constant st28: std_logic_vector(4 downto 0) := "01101";
constant st29: std_logic_vector(4 downto 0) := "10010";
constant st30: std_logic_vector(4 downto 0) := "01110";
constant st31: std_logic_vector(4 downto 0) := "00001";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "---------";
case current_state is
when st0 =>
if std_match(input, "---------0-") then next_state <= st0; output <= "000001---";
elsif std_match(input, "----0----1-") then next_state <= st0; output <= "000001---";
elsif std_match(input, "----1---11-") then next_state <= st5; output <= "011001000";
elsif std_match(input, "----1---01-") then next_state <= st1; output <= "11-001000";
end if;
when st1 =>
if std_match(input, "0000---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0000---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0001---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0001---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0010---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0010---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0011---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0011---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0100---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0100---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0101---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0101---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0110---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0110---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "0111---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "0111---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "1000---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "1000---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "1001---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "1001---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "1010---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "1010---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "1011---0-0-") then next_state <= st1; output <= "0001-0000";
elsif std_match(input, "1011---0-1-") then next_state <= st2; output <= "11-1-0100";
elsif std_match(input, "1100---0---") then next_state <= st4; output <= "1010-0100";
elsif std_match(input, "1101---0---") then next_state <= st3; output <= "0000-0110";
elsif std_match(input, "1111--10---") then next_state <= st0; output <= "11-0---01";
elsif std_match(input, "1111--00---") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "-------1---") then next_state <= st0; output <= "11-0-----";
end if;
when st2 =>
if std_match(input, "-------0-0-") then next_state <= st2; output <= "0000-0000";
elsif std_match(input, "-------0-10") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "----0-00-11") then next_state <= st1; output <= "11-0-1000";
elsif std_match(input, "----1-00-11") then next_state <= st2; output <= "0000-0000";
elsif std_match(input, "------10-11") then next_state <= st0; output <= "11-0---01";
elsif std_match(input, "-------1---") then next_state <= st0; output <= "11-0-----";
end if;
when st3 =>
if std_match(input, "------10--1") then next_state <= st0; output <= "11-0---01";
elsif std_match(input, "-----010--0") then next_state <= st3; output <= "---0-0000";
elsif std_match(input, "-----110--0") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "----1-00--1") then next_state <= st3; output <= "---0-0000";
elsif std_match(input, "----0-00--1") then next_state <= st1; output <= "11-0-1000";
elsif std_match(input, "------00--0") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "-------1---") then next_state <= st0; output <= "11-0-----";
end if;
when st4 =>
if std_match(input, "------10-00") then next_state <= st4; output <= "0000-0000";
elsif std_match(input, "------10-01") then next_state <= st0; output <= "11-0---01";
elsif std_match(input, "------00-00") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "----1-00--1") then next_state <= st4; output <= "---0-0000";
elsif std_match(input, "----0-00--1") then next_state <= st3; output <= "11-0-0000";
elsif std_match(input, "------10-1-") then next_state <= st1; output <= "11-0-0000";
elsif std_match(input, "-------1---") then next_state <= st0; output <= "11-0---00";
end if;
when st5 =>
if std_match(input, "0000-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0000-----1-") then next_state <= st31; output <= "010110100";
elsif std_match(input, "0001-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0001-----1-") then next_state <= st25; output <= "010110100";
elsif std_match(input, "0010-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0010-----1-") then next_state <= st19; output <= "010110100";
elsif std_match(input, "0011-------") then next_state <= st6; output <= "000100100";
elsif std_match(input, "0100-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0100-----1-") then next_state <= st29; output <= "010110100";
elsif std_match(input, "0101-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0101-----1-") then next_state <= st23; output <= "010110100";
elsif std_match(input, "0110-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0110-----1-") then next_state <= st17; output <= "010110100";
elsif std_match(input, "0111-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "0111-----1-") then next_state <= st13; output <= "010110100";
elsif std_match(input, "1000-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "1000-----1-") then next_state <= st27; output <= "010110100";
elsif std_match(input, "1001-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "1001-----1-") then next_state <= st21; output <= "010110100";
elsif std_match(input, "1010-----0-") then next_state <= st5; output <= "000100000";
elsif std_match(input, "1010-----1-") then next_state <= st15; output <= "010110100";
elsif std_match(input, "1011-------") then next_state <= st6; output <= "000100100";
elsif std_match(input, "1100-------") then next_state <= st12; output <= "101100100";
elsif std_match(input, "1101-------") then next_state <= st10; output <= "011100110";
elsif std_match(input, "1111-------") then next_state <= st7; output <= "011100000";
end if;
when st6 =>
if std_match(input, "----------0") then next_state <= st5; output <= "000100000";
elsif std_match(input, "----0-0---1") then next_state <= st5; output <= "000101000";
elsif std_match(input, "----1-0---1") then next_state <= st7; output <= "011101000";
end if;
when st7 =>
if std_match(input, "-----1---1-") then next_state <= st8; output <= "100000000";
elsif std_match(input, "-----0---1-") then next_state <= st0; output <= "10000--01";
elsif std_match(input, "---------0-") then next_state <= st7; output <= "000100000";
end if;
when st8 =>
if std_match(input, "0000-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "00000----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "00001----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0001-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "00010----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "00011----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0010-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "00100----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "00101----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0011-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "00110----1-") then next_state <= st9; output <= "---000100";
elsif std_match(input, "00111----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0100-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "01000----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "01001----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0101-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "01010----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "01011----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0110-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "01100----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "01101----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "0111-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "01110----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "01111----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1000-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "10000----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "10001----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1001-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "10010----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "10011----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1010-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "10100----1-") then next_state <= st5; output <= "011100000";
elsif std_match(input, "10101----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1011-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "10110----1-") then next_state <= st9; output <= "---000100";
elsif std_match(input, "10111----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1100-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "11000----1-") then next_state <= st9; output <= "---000100";
elsif std_match(input, "11001----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1101-----0-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "11010----1-") then next_state <= st9; output <= "---000100";
elsif std_match(input, "11011----1-") then next_state <= st8; output <= "000000000";
elsif std_match(input, "1111-------") then next_state <= st8; output <= "000000000";
end if;
when st9 =>
if std_match(input, "----------1") then next_state <= st8; output <= "001001000";
elsif std_match(input, "----------0") then next_state <= st8; output <= "000000000";
end if;
when st10 =>
if std_match(input, "------1--10") then next_state <= st11; output <= "---000010";
elsif std_match(input, "------1--00") then next_state <= st10; output <= "000100000";
elsif std_match(input, "------1---1") then next_state <= st0; output <= "10000--01";
elsif std_match(input, "------0---0") then next_state <= st5; output <= "100100000";
elsif std_match(input, "----0-0---1") then next_state <= st5; output <= "100101000";
elsif std_match(input, "----1-0---1") then next_state <= st10; output <= "---101000";
end if;
when st11 =>
if std_match(input, "-----0-----") then next_state <= st11; output <= "---000000";
elsif std_match(input, "-----1-----") then next_state <= st5; output <= "011100000";
end if;
when st12 =>
if std_match(input, "------1--10") then next_state <= st5; output <= "001100000";
elsif std_match(input, "------1--00") then next_state <= st12; output <= "000100000";
elsif std_match(input, "------1---1") then next_state <= st7; output <= "01110--00";
elsif std_match(input, "------0---0") then next_state <= st5; output <= "100100000";
elsif std_match(input, "----0-0---1") then next_state <= st5; output <= "100101000";
elsif std_match(input, "----1-0---1") then next_state <= st12; output <= "---101000";
end if;
when st13 =>
if std_match(input, "---------0-") then next_state <= st13; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st14; output <= "001100000";
end if;
when st14 =>
if std_match(input, "---------0-") then next_state <= st14; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st15; output <= "010110000";
end if;
when st15 =>
if std_match(input, "---------0-") then next_state <= st15; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st16; output <= "001100000";
end if;
when st16 =>
if std_match(input, "---------0-") then next_state <= st16; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st17; output <= "010110000";
end if;
when st17 =>
if std_match(input, "---------0-") then next_state <= st17; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st18; output <= "001100000";
end if;
when st18 =>
if std_match(input, "---------0-") then next_state <= st18; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st19; output <= "010110000";
end if;
when st19 =>
if std_match(input, "---------0-") then next_state <= st19; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st20; output <= "001100000";
end if;
when st20 =>
if std_match(input, "---------0-") then next_state <= st20; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st21; output <= "010110000";
end if;
when st21 =>
if std_match(input, "---------0-") then next_state <= st21; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st22; output <= "001100000";
end if;
when st22 =>
if std_match(input, "---------0-") then next_state <= st22; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st23; output <= "010110000";
end if;
when st23 =>
if std_match(input, "---------0-") then next_state <= st23; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st24; output <= "001100000";
end if;
when st24 =>
if std_match(input, "---------0-") then next_state <= st24; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st25; output <= "010110000";
end if;
when st25 =>
if std_match(input, "---------0-") then next_state <= st25; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st26; output <= "001100000";
end if;
when st26 =>
if std_match(input, "---------0-") then next_state <= st26; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st27; output <= "010110000";
end if;
when st27 =>
if std_match(input, "---------0-") then next_state <= st27; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st28; output <= "001100000";
end if;
when st28 =>
if std_match(input, "---------0-") then next_state <= st28; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st29; output <= "010110000";
end if;
when st29 =>
if std_match(input, "---------0-") then next_state <= st29; output <= "000110000";
elsif std_match(input, "---------1-") then next_state <= st30; output <= "001100000";
end if;
when st30 =>
if std_match(input, "---------0-") then next_state <= st30; output <= "000100000";
elsif std_match(input, "---------1-") then next_state <= st31; output <= "010110000";
end if;
when st31 =>
if std_match(input, "---------0-") then next_state <= st31; output <= "000110000";
elsif std_match(input, "---------10") then next_state <= st5; output <= "100100000";
elsif std_match(input, "------1--11") then next_state <= st7; output <= "01110--00";
elsif std_match(input, "----0-0--11") then next_state <= st5; output <= "100101000";
elsif std_match(input, "----1-0--11") then next_state <= st7; output <= "011101000";
end if;
when others => next_state <= "-----"; output <= "---------";
end case;
end process;
end behaviour;
|
---------------------------------------------------------------
-- Title : Package for simulation terminal
-- Project : -
---------------------------------------------------------------
-- File : terminal_pkg.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 22/09/03
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (C) 2001, MEN Mikroelektronik Nuernberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.9 $
--
-- $Log: terminal_pkg.vhd,v $
-- Revision 1.9 2010/08/16 12:57:16 FLenhardt
-- Added an overloaded MTEST which accepts a seed number as an input
--
-- Revision 1.8 2009/01/13 10:57:52 FLenhardt
-- Defined that TGA=2 means configuration access
--
-- Revision 1.7 2008/09/10 17:26:45 MSchindler
-- added flash_mtest_indirect procedure
--
-- Revision 1.6 2007/07/26 07:48:15 FLenhardt
-- Defined usage of TGA
--
-- Revision 1.5 2007/07/18 10:53:34 FLenhardt
-- Fixed bug regarding MTEST printout
--
-- Revision 1.4 2007/07/18 10:28:35 mernst
-- - Changed err to sum up errors instead of setting a specific value
-- - Added dat vector to terminal_in record
--
-- Revision 1.3 2006/08/24 08:52:02 mmiehling
-- changed txt_out to integer
--
-- Revision 1.1 2006/06/23 16:33:04 MMiehling
-- Initial Revision
--
-- Revision 1.2 2006/05/12 10:49:17 MMiehling
-- initialization of iram now with mem_init (back)
-- added testcase 14
--
-- Revision 1.1 2006/05/09 16:51:16 MMiehling
-- Initial Revision
--
-- Revision 1.2 2005/10/27 08:35:35 flenhardt
-- Added IRQ to TERMINAL_IN_TYPE record
--
-- Revision 1.1 2005/08/23 15:21:07 MMiehling
-- Initial Revision
--
-- Revision 1.1 2005/07/01 15:47:38 MMiehling
-- Initial Revision
--
-- Revision 1.2 2005/01/31 16:28:59 mmiehling
-- updated
--
-- Revision 1.1 2004/11/16 12:09:07 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.print_pkg.all;
USE ieee.std_logic_arith.ALL;
PACKAGE terminal_pkg IS
TYPE terminal_in_type IS record
done : boolean; -- edge indicates end of transfer
busy : std_logic; -- indicates status of master
err : natural; -- number of errors occured
irq : std_logic; -- interrupt request
dat : std_logic_vector(31 DOWNTO 0); -- Input data
END record;
TYPE terminal_out_type IS record
adr : std_logic_vector(31 DOWNTO 0); -- address
tga : std_logic_vector(5 DOWNTO 0); -- 0=mem, 1=io, 2=conf
dat : std_logic_vector(31 DOWNTO 0); -- write data
wr : natural; -- 0=read, 1=write, 2=wait for numb cycles
typ : natural; -- 0=b, w=1, l=2
numb : natural; -- number of transactions (1=single, >1=burst)
start : boolean; -- edge starts transfer
txt : integer; -- enables info messages -- 0=quiet, 1=only errors, 2=all
END record;
-- Bus Accesses
PROCEDURE init( SIGNAL terminal_out : OUT terminal_out_type);
PROCEDURE wait_for( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
numb : natural;
woe : boolean
);
PROCEDURE rd32( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
);
PROCEDURE rd16( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
);
PROCEDURE rd8( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
);
PROCEDURE wr32( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
);
PROCEDURE wr16( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
);
PROCEDURE wr8( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
);
PROCEDURE mtest( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
txt_out : integer;
tga : std_logic_vector;
err : INOUT natural
) ;
PROCEDURE mtest( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
txt_out : integer;
tga : std_logic_vector;
seed : natural;
err : INOUT natural
) ;
PROCEDURE flash_mtest_indirect( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
adr_if : std_logic_vector; -- = address of indirect interface
txt_out : integer;
tga : std_logic_vector;
err : OUT natural
) ;
END terminal_pkg;
PACKAGE BODY terminal_pkg IS
----------------------------------------------------------------------------------------------------------
PROCEDURE init( SIGNAL terminal_out : OUT terminal_out_type) IS
BEGIN
terminal_out.adr <= (OTHERS => '0');
terminal_out.tga <= (OTHERS => '0');
terminal_out.dat <= (OTHERS => '0');
terminal_out.wr <= 0;
terminal_out.typ <= 0;
terminal_out.numb <= 0;
terminal_out.txt <= 0;
terminal_out.start <= TRUE;
END PROCEDURE init;
PROCEDURE wait_for( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
numb : natural;
woe : boolean
) IS
BEGIN
terminal_out.wr <= 2;
terminal_out.numb <= numb;
terminal_out.txt <= 0;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
END PROCEDURE;
PROCEDURE rd32( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 0;
terminal_out.typ <= 2;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
err := err + terminal_in.err;
END PROCEDURE;
PROCEDURE rd16( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 0;
terminal_out.typ <= 1;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
err := err + terminal_in.err;
END PROCEDURE;
PROCEDURE rd8( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector;
err : INOUT natural
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 0;
terminal_out.typ <= 0;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
err := err + terminal_in.err;
END PROCEDURE;
PROCEDURE wr32( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 1;
terminal_out.typ <= 2;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
END PROCEDURE;
PROCEDURE wr8( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 1;
terminal_out.typ <= 0;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
END PROCEDURE;
PROCEDURE wr16( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
dat : std_logic_vector;
numb : natural;
txt_out : integer;
woe : boolean;
tga : std_logic_vector
) IS
BEGIN
terminal_out.adr <= adr;
terminal_out.dat <= dat;
terminal_out.tga <= tga;
terminal_out.numb <= numb;
terminal_out.wr <= 1;
terminal_out.typ <= 1;
terminal_out.txt <= txt_out;
terminal_out.start <= NOT terminal_in.done;
IF woe THEN
WAIT on terminal_in.done;
END IF;
END PROCEDURE;
-- This is the legacy MTEST (without seed)
PROCEDURE mtest( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
txt_out : integer;
tga : std_logic_vector;
err : INOUT natural
) IS
BEGIN
mtest(terminal_in, terminal_out, adr, adr_end, typ, numb, txt_out, tga, 0, err);
END PROCEDURE;
-- This is an overloaded MTEST which accepts a seed number as an input,
-- which can be used to generate the pseudo-random data in different ways
PROCEDURE mtest( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
txt_out : integer;
tga : std_logic_vector;
seed : natural;
err : INOUT natural
) IS
VARIABLE loc_err : natural;
VARIABLE loc_adr : std_logic_vector(31 DOWNTO 0);
VARIABLE loc_dat : std_logic_vector(31 DOWNTO 0);
VARIABLE numb_cnt : natural;
BEGIN
loc_adr := adr;
numb_cnt := 0;
loc_err := 0;
loc_dat := adr;
while NOT(numb_cnt = numb) LOOP
CASE typ IS
WHEN 0 => -- long
while NOT (loc_adr = adr_end) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896 + seed;
wr32(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga);
rd32(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga, loc_err);
loc_adr := loc_adr + x"4";
END LOOP;
WHEN 1 => -- word
while NOT (loc_adr = adr_end) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896 + seed;
wr16(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga);
rd16(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga, loc_err);
loc_adr := loc_adr + x"2";
END LOOP;
WHEN 2 => -- byte
while NOT (loc_adr = adr_end) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896 + seed;
wr8(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga);
rd8(terminal_in, terminal_out, loc_adr, loc_dat, 1, txt_out, TRUE, tga, loc_err);
loc_adr := loc_adr + x"1";
END LOOP;
WHEN OTHERS =>
print("ERROR terminal_pkg: typ IS NOT defined!");
END CASE;
numb_cnt := numb_cnt + 1;
END LOOP;
IF loc_err > 0 THEN
print_s_i(" mtest FAIL errors: ", loc_err);
ELSE
print(" mtest PASS");
END IF;
err := err + loc_err;
END PROCEDURE;
PROCEDURE flash_mtest_indirect( SIGNAL terminal_in : IN terminal_in_type;
SIGNAL terminal_out : OUT terminal_out_type;
adr : std_logic_vector;
adr_end : std_logic_vector; -- = end address
typ : natural; -- 0=l, 1=w, 2=b
numb : natural; -- = number of cycles
adr_if : std_logic_vector; -- = address of indirect interface
txt_out : integer;
tga : std_logic_vector;
err : OUT natural
) IS
VARIABLE loc_err : natural;
VARIABLE loc_err2 : natural;
VARIABLE loc_adr : std_logic_vector(31 DOWNTO 0);
VARIABLE loc_dat : std_logic_vector(31 DOWNTO 0);
VARIABLE numb_cnt : natural;
BEGIN
--loc_adr := adr;
numb_cnt := 0;
loc_err := 0;
loc_dat := adr;
while NOT(numb_cnt = numb) LOOP
CASE typ IS
WHEN 0 => -- long
loc_adr := conv_std_logic_vector((conv_integer(adr)/4),32);
print("Flash Address OF the address register will be autoincremented");
print("Writing 32-bit data into Data Register => 32-bit Flash Memory access with indirect addressing");
print("Reading 32-bit-Address Register IN order TO control exact address register content");
while NOT (loc_adr = conv_std_logic_vector((conv_integer(adr_end)/4),32)) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896;
wr32(terminal_in, terminal_out, adr_if + x"0000_0000", loc_adr, 1, txt_out, TRUE, tga);
wr32(terminal_in, terminal_out, adr_if + x"0000_0004", loc_dat(31 DOWNTO 0), 1, txt_out, TRUE, tga);
rd32(terminal_in, terminal_out, adr_if + x"0000_0000", "001" & loc_adr(28 DOWNTO 0), 1, txt_out, TRUE, tga, loc_err2);
IF loc_err2 = 1 THEN
print("ERROR WHEN reading address register: other value expected");
END IF;
loc_adr := loc_adr + x"1";
loc_err := loc_err + loc_err2;
END LOOP;
print("Reading Data Register from Memory using indirect addressing");
loc_adr := conv_std_logic_vector((conv_integer(adr)/4),32);
loc_dat := adr;
while NOT (loc_adr = conv_std_logic_vector((conv_integer(adr_end)/4),32)) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896;
wr32(terminal_in, terminal_out, adr_if + x"0000_0000", loc_adr, 1, txt_out, TRUE, tga);
rd32(terminal_in, terminal_out, adr_if + x"0000_0004", loc_dat(31 DOWNTO 0), 1, txt_out, TRUE, tga, loc_err2);
IF loc_err2 = 1 THEN
print("ERROR WHEN reading data register: value READ from memory isn´t expected value");
END IF;
loc_err := loc_err + loc_err2;
loc_adr := loc_adr + x"1";
END LOOP;
WHEN 1 => -- word
loc_adr := conv_std_logic_vector((conv_integer(adr)/2),32);
print("Flash Address OF the address register will be autoincremented");
print("Writing 16-bit data into Data Register => 16-bit Flash Memory access with indirect addressing");
print("Reading 32-bit-Address Register IN order TO control exact address register content");
while NOT (loc_adr = conv_std_logic_vector((conv_integer(adr_end)/2),32)) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896;
wr32(terminal_in, terminal_out, adr_if + x"0000_0000", loc_adr, 1, txt_out, TRUE, tga);
wr32(terminal_in, terminal_out, adr_if + x"0000_0004", x"0000" & loc_dat(15 DOWNTO 0), 1, txt_out, TRUE, tga);
rd32(terminal_in, terminal_out, adr_if + x"0000_0000", "010" & loc_adr(28 DOWNTO 0), 1, txt_out, TRUE, tga, loc_err2);
IF loc_err2 = 1 THEN
print("ERROR WHEN reading address register: other value expected");
END IF;
loc_adr := loc_adr + x"1";
loc_err := loc_err + loc_err2;
END LOOP;
print("READ AND Check 16-bit-Data from Memory using indirect addressing");
loc_adr := conv_std_logic_vector((conv_integer(adr)/2),32);
loc_dat := adr;
while NOT (loc_adr = conv_std_logic_vector((conv_integer(adr_end)/2),32)) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896;
wr32(terminal_in, terminal_out, adr_if + x"0000_0000", loc_adr, 1, txt_out, TRUE, tga);
rd32(terminal_in, terminal_out, adr_if + x"0000_0004", x"0000" & loc_dat(15 DOWNTO 0), 1, txt_out, TRUE, tga, loc_err2);
IF loc_err2 = 1 THEN
print("ERROR WHEN reading data register: value READ from memory isn´t expected value");
END IF;
loc_err := loc_err + loc_err2;
loc_adr := loc_adr + x"1";
END LOOP;
WHEN 2 => -- byte
loc_adr := adr;
print("Flash Address OF the address register will be autoincremented");
print("Writing 8-bit data into Data Register => 8-bit Flash Memory access with indirect addressing");
print("Reading 32-bit-Address Register IN order TO control exact address register content");
while NOT (loc_adr = adr_end) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896;
wr32(terminal_in, terminal_out, adr_if + x"0000_0000", loc_adr, 1, txt_out, TRUE, tga);
wr32(terminal_in, terminal_out, adr_if + x"0000_0004", x"000000" & loc_dat(7 DOWNTO 0), 1, txt_out, TRUE, tga);
rd32(terminal_in, terminal_out, adr_if + x"0000_0000", "000" & loc_adr(28 DOWNTO 0), 1, txt_out, TRUE, tga, loc_err2);
IF loc_err2 = 1 THEN
print("ERROR WHEN reading address register: other value expected");
END IF;
loc_adr := loc_adr + x"1";
loc_err := loc_err + loc_err2;
END LOOP;
print("READ AND Check 8-bit-Data from Memory using indirect addressing");
loc_adr := adr;
loc_dat := adr;
while NOT (loc_adr = adr_end) LOOP
loc_dat := (loc_dat(15 DOWNTO 0) & loc_dat(31 DOWNTO 16)) + 305419896;
wr32(terminal_in, terminal_out, adr_if + x"0000_0000", loc_adr, 1, txt_out, TRUE, tga);
rd32(terminal_in, terminal_out, adr_if + x"0000_0004", x"000000" & loc_dat(7 DOWNTO 0), 1, txt_out, TRUE, tga, loc_err2);
IF loc_err2 = 1 THEN
print("ERROR WHEN reading data register: value READ from memory isn´t expected value");
END IF;
loc_err := loc_err + loc_err2;
loc_adr := loc_adr + x"1";
END LOOP;
WHEN OTHERS =>
print("ERROR terminal_pkg: typ IS NOT defined!");
END CASE;
numb_cnt := numb_cnt + 1;
END LOOP;
IF loc_err > 0 THEN
print_s_i(" mtest_indirect FAIL errors: ", loc_err);
ELSE
print(" mtest_indirect PASS");
END IF;
err := loc_err;
END PROCEDURE;
--------------------------------------------------------------------------------------------
END; |
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`protect end_protected
|
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Paul Genssler - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity code_loader is
Port (
address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
done : out std_logic;
clk : in std_logic);
end code_loader;
architecture Behavioral of code_loader is
type instr_t is array (0 to 1023) of std_logic_vector(17 downto 0);
signal mem : instr_t;
signal instruction_o : std_logic_vector(17 downto 0);
signal clk_sim : std_logic;
signal inst_sim : std_logic_vector(17 downto 0);
signal addr_sim : std_logic_vector(11 downto 0);
begin
instruction <= instruction_o;
rdl <= '0';
read_inst : process (clk)
begin
if (rising_edge(clk)) then
if (enable = '1') then
instruction_o <= mem(to_integer(unsigned(address)));
else
instruction_o <= instruction_o;
end if;
end if;
end process;
load_mem : process
begin
done <= '0';
clk_sim <= '1';
wait for 50 ps;
clk_sim <= '0';
wait for 50 ps;
for i in 0 to 1023 loop
addr_sim <= std_logic_vector(to_unsigned(i+1, 12));
clk_sim <= '1';
wait for 50 ps;
clk_sim <= '0';
wait for 51 ps;
mem(i) <= inst_sim;
end loop;
done <= '1';
wait;
end process load_mem;
prog_mem : entity work.test_assembler generic map (
C_FAMILY => "V6",
C_RAM_SIZE_KWORDS => 1,
C_JTAG_LOADER_ENABLE => 0)
Port map (
address => addr_sim,
instruction => inst_sim,
enable => '1',
rdl => open,
clk => clk_sim);
end Behavioral;
|
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Paul Genssler - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS is" BASIS,
-- WITHOUT WARRANTIES or CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity code_loader is
Port (
address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
done : out std_logic;
clk : in std_logic);
end code_loader;
architecture Behavioral of code_loader is
type instr_t is array (0 to 1023) of std_logic_vector(17 downto 0);
signal mem : instr_t;
signal instruction_o : std_logic_vector(17 downto 0);
signal clk_sim : std_logic;
signal inst_sim : std_logic_vector(17 downto 0);
signal addr_sim : std_logic_vector(11 downto 0);
begin
instruction <= instruction_o;
rdl <= '0';
read_inst : process (clk)
begin
if (rising_edge(clk)) then
if (enable = '1') then
instruction_o <= mem(to_integer(unsigned(address)));
else
instruction_o <= instruction_o;
end if;
end if;
end process;
load_mem : process
begin
done <= '0';
clk_sim <= '1';
wait for 50 ps;
clk_sim <= '0';
wait for 50 ps;
for i in 0 to 1023 loop
addr_sim <= std_logic_vector(to_unsigned(i+1, 12));
clk_sim <= '1';
wait for 50 ps;
clk_sim <= '0';
wait for 51 ps;
mem(i) <= inst_sim;
end loop;
done <= '1';
wait;
end process load_mem;
prog_mem : entity work.test_assembler generic map (
C_FAMILY => "V6",
C_RAM_SIZE_KWORDS => 1,
C_JTAG_LOADER_ENABLE => 0)
Port map (
address => addr_sim,
instruction => inst_sim,
enable => '1',
rdl => open,
clk => clk_sim);
end Behavioral;
|
library verilog;
use verilog.vl_types.all;
entity SeqEightBitAdder_vlg_check_tst is
port(
LEDR : in vl_logic_vector(8 downto 0);
sampler_rx : in vl_logic
);
end SeqEightBitAdder_vlg_check_tst;
|
--------------------------------------------------------------------------------
-- Title : VME Bustimer
-- Project : A15
--------------------------------------------------------------------------------
-- File : vme_bustimer.vhd
-- Author : michael.miehling@men.de
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 10/02/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- This module handles the resets and the vme bus access time-out counting.
--
--------------------------------------------------------------------------------
-- Hierarchy:
-- wbb2vme
-- vme_ctrl
-- vme_bustimer
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.3 $
--
-- $Log: vme_bustimer.vhd,v $
-- Revision 1.3 2014/04/17 07:35:29 MMiehling
-- added signal prevent_sysrst
--
-- Revision 1.2 2012/08/27 12:57:22 MMiehling
-- changed minimum vme reset time to 1 ms
-- general rework of reset handling
--
-- Revision 1.1 2012/03/29 10:14:50 MMiehling
-- Initial Revision
--
-- Revision 1.13 2006/06/02 15:48:55 MMiehling
-- removed sysfailn_int from fsm to reduce logic (now active when startup_rstn active)
--
-- Revision 1.12 2006/05/18 14:29:03 MMiehling
-- arbitration failures when pci2vme is in slot1 => bugfix in deglitcher
-- corrected time-out counter description
-- changed reset release behaviour
--
-- Revision 1.11 2005/02/04 13:44:12 mmiehling
-- added generic simulation
--
-- Revision 1.10 2004/11/02 11:29:53 mmiehling
-- added registered rstn
--
-- Revision 1.9 2004/07/27 17:15:37 mmiehling
-- changed pci-core to 16z014
-- changed wishbone bus to wb_bus.vhd
-- added clk_trans_wb2wb.vhd
-- improved dma
--
-- Revision 1.8 2004/06/17 13:02:26 MMiehling
-- removed clr_hit and sl_acc_reg
--
-- Revision 1.7 2003/12/17 15:51:43 MMiehling
-- sysfailn must be 1 or 0 because external driver makes z
--
-- Revision 1.6 2003/12/01 10:03:51 MMiehling
-- v2p_rst_intn is open collector now
--
-- Revision 1.5 2003/07/14 08:38:06 MMiehling
-- added sysfailn_int; changed rst_counter
--
-- Revision 1.4 2003/06/24 13:47:06 MMiehling
-- changed vme and cpu reset
--
-- Revision 1.3 2003/06/13 10:06:33 MMiehling
-- changed rst_fsm and slot1 detection
--
-- Revision 1.2 2003/04/22 11:02:58 MMiehling
-- reset does not work
--
-- Revision 1.1 2003/04/01 13:04:41 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
ENTITY vme_bustimer IS
PORT (
clk : IN std_logic; -- global clock
rst : IN std_logic; -- global reset
startup_rst : IN std_logic; -- powerup reset
prevent_sysrst : IN std_logic; -- if "1", sysrst_n_out will not be activated after powerup,
-- if "0", sysrst_n_out will be activated if in slot1 and system reset is active (sysc_bit or rst)
set_sysc : OUT std_logic; -- if set sysc-bit will be set
sysc_bit : IN std_logic; -- 1=slot1 0=slotx
clr_sysr : OUT std_logic; -- if set sysr-bit will be cleared
sysr_bit : IN std_logic; -- 1=system reset
-- connected with Slave Unit
dsain : IN std_logic; -- data strobe a in
dsbin : IN std_logic; -- data strobe b in
bgouten : OUT std_logic; -- enables SGL and bg3out signal
-- bus grant daisy chain is driven through requester in Access VME:
-----------------------------------------------------------------------
-- PINs:
sysfailn : OUT std_logic; -- indicates when A15 is not ready or in reset
sysrstn_in : IN std_logic;
sysrstn_out : OUT std_logic;
v2p_rst : OUT std_logic; -- Reset between VMEbus and Host CPU
bg3n_in : IN std_logic; -- bus grant signal in (if not connected => slot01)
slot01n : OUT std_logic; -- enables V_SYSCLK (16 MHz)
berrn_out : OUT std_logic -- bus error
);
--
END vme_bustimer;
ARCHITECTURE bustimer_arc OF vme_bustimer IS
CONSTANT CONST_10US : std_logic_vector(9 DOWNTO 0):= "1010011011"; -- =667 @ 66MHz => 10,005 us
CONSTANT CONST_200MS : std_logic_vector(14 DOWNTO 0):= "100111000010111"; -- = 19991 @ 10,005us =>
-- counter value for vme rstn => 250ms
SIGNAL btresn : std_logic; -- bus timer reset
SIGNAL cnt : std_logic_vector(12 DOWNTO 0); -- approximately 60 us
SIGNAL sysrstn_out_int : std_logic;
SIGNAL v2p_rst_int : std_logic;
TYPE rst_states IS (IDLE, WAIT_ON_RST, RST_VME, RST_VME2, WAIT_ON_VME, RST_CPU, WAIT_ON_CPU, STARTUP_END);
SIGNAL rst_state : rst_states;
SIGNAL pre_cnt : std_logic_vector(9 DOWNTO 0);
SIGNAL pre_cnt_end : std_logic;
SIGNAL rst_pre_cnt : std_logic;
SIGNAL rst_main_cnt : std_logic;
SIGNAL main_cnt : std_logic_vector(14 DOWNTO 0);
SIGNAL main_cnt_max_sig : std_logic_vector(14 DOWNTO 0);
SIGNAL main_cnt_end : std_logic;
SIGNAL sysrstn_q : std_logic;
SIGNAL sysrstn_qq : std_logic;
SIGNAL sysrstn_qqq : std_logic;
SIGNAL degl_sysrstn : std_logic;
SIGNAL rst_q : std_logic;
SIGNAL rst_qq : std_logic;
SIGNAL rst_qqq : std_logic;
SIGNAL degl_rst : std_logic;
SIGNAL dsain_q : std_logic;
SIGNAL dsbin_q : std_logic;
SIGNAL bg3n_in_q : std_logic;
SIGNAL bg3n_in_qq : std_logic;
SIGNAL pre_cnt_max_sig : std_logic_vector(9 DOWNTO 0);
SIGNAL set_sysc_int : std_logic;
BEGIN
slot01n <= NOT sysc_bit;
sysrstn_out <= sysrstn_out_int;
set_sysc <= set_sysc_int;
sysfailn <= '0' WHEN startup_rst = '1' ELSE '1';
v2p_rst <= v2p_rst_int;
-------------------------------------------------------------------------------
-- Bus Timer. Works only when sysc_bit is set. Generates a bus error after 62 us
-- During normal operation, reset is triggered each
-- time both VMEbus Datastrobes are high.
-------------------------------------------------------------------------------
btresn <= '1' WHEN (dsain_q = '1' AND dsbin_q = '1') ELSE '0';
degl : PROCESS(clk, startup_rst)
BEGIN
IF startup_rst = '1' THEN
sysrstn_q <= '1';
sysrstn_qq <= '1';
sysrstn_qqq <= '1';
degl_sysrstn <= '1';
rst_q <= '0';
rst_qq <= '0';
rst_qqq <= '0';
degl_rst <= '0';
bg3n_in_q <= '1';
bg3n_in_qq <= '1';
ELSIF clk'EVENT AND clk = '1' THEN
bg3n_in_q <= bg3n_in;
bg3n_in_qq <= bg3n_in_q;
sysrstn_q <= sysrstn_in;
sysrstn_qq <= sysrstn_q;
sysrstn_qqq <= sysrstn_qq;
IF sysrstn_q = '0' AND sysrstn_qq = '0' AND sysrstn_qqq = '0' THEN
degl_sysrstn <= '0';
ELSIF sysrstn_q = '1' AND sysrstn_qq = '1' AND sysrstn_qqq = '1' THEN
degl_sysrstn <= '1';
ELSE
degl_sysrstn <= degl_sysrstn;
END IF;
rst_q <= rst;
rst_qq <= rst_q;
rst_qqq <= rst_qq;
IF rst_q = '1' AND rst_qq = '1' AND rst_qqq = '1' THEN
degl_rst <= '1';
ELSIF rst_q = '0' AND rst_qq = '0' AND rst_qqq = '0' THEN
degl_rst <= '0';
END IF;
END IF;
END PROCESS degl;
bustim : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
cnt <= (OTHERS => '0');
berrn_out <= '1';
dsain_q <= '1';
dsbin_q <= '1';
ELSIF clk'event AND clk = '1' THEN
dsain_q <= dsain;
dsbin_q <= dsbin;
IF (btresn = '1') THEN
cnt <= (OTHERS => '0');
ELSIF (dsain_q = '0' OR dsbin_q = '0') AND sysc_bit = '1' THEN -- counter starts with DSA or DSB signal
cnt <= cnt + 1;
END IF;
IF cnt(12) = '1' THEN
berrn_out <= '0';
ELSIF btresn = '1' THEN
berrn_out <= '1';
END IF;
END IF;
END PROCESS bustim;
pre_cnt_max_sig <= CONST_10US;
main_cnt_max_sig <= CONST_200MS;
rst_cnt : PROCESS(clk, startup_rst)
BEGIN
IF startup_rst = '1' THEN
main_cnt <= (OTHERS => '0');
pre_cnt <= (OTHERS => '0');
main_cnt_end <= '0';
pre_cnt_end <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
-- pre counter for counting up to 10 us
IF rst_pre_cnt = '1' THEN
pre_cnt <= (OTHERS => '0');
pre_cnt_end <= '0';
ELSIF pre_cnt = pre_cnt_max_sig THEN
pre_cnt <= (OTHERS => '0');
pre_cnt_end <= '1';
ELSE
pre_cnt <= pre_cnt + 1;
pre_cnt_end <= '0';
END IF;
-- main counter with base of 10 us counts up to 200 ms reset time
IF rst_main_cnt = '1' THEN
main_cnt <= (OTHERS => '0');
main_cnt_end <= '0';
ELSIF main_cnt = main_cnt_max_sig AND pre_cnt_end = '1' THEN
main_cnt <= (OTHERS => '0');
main_cnt_end <= '1';
ELSIF pre_cnt_end = '1' THEN
main_cnt <= main_cnt + 1;
main_cnt_end <= '0';
END IF;
END IF;
END PROCESS rst_cnt;
rst_fsm : PROCESS (clk, startup_rst)
BEGIN
IF startup_rst = '1' THEN
set_sysc_int <= '0';
bgouten <= '0';
sysrstn_out_int <= '0';
v2p_rst_int <= '0';
clr_sysr <= '0';
rst_state <= IDLE;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF set_sysc_int = '1' AND sysc_bit = '1' THEN -- if status reg has stored slot 1 location => clear request to set bit
set_sysc_int <= '0';
ELSIF bg3n_in_qq = '0' AND main_cnt_end = '1' AND rst_state = IDLE THEN -- slot 1 was detected => keep in mind until stored in status reg
set_sysc_int <= '1';
END IF;
CASE rst_state IS
-- wait until powerup reset time has elapsed (16383 * system_clock_period = 250 us @ 66MHz)
WHEN IDLE =>
bgouten <= '0';
sysrstn_out_int <= '0'; -- activate reset to vme-bus
v2p_rst_int <= '0'; -- no reset to cpu
clr_sysr <= '0';
IF main_cnt_end = '1' THEN
rst_state <= STARTUP_END;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
ELSE
rst_state <= IDLE;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
END IF;
-- release vme reset and wait for deactivation of vme- and cpu-reset (minimum 16383 * system_clock_period = 250 us @ 66MHz)
WHEN STARTUP_END =>
bgouten <= '0';
sysrstn_out_int <= '1'; -- no reset to vme-bus
v2p_rst_int <= '0'; -- no reset to cpu
clr_sysr <= '0';
IF main_cnt_end = '1' AND degl_rst = '0' AND degl_sysrstn = '1' THEN -- wait until cpu and vme does not deliver active reset
rst_state <= WAIT_ON_RST;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
ELSE
rst_state <= STARTUP_END;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
END IF;
-- normal operation: wait until either cpu-reset or vme-reset is active
WHEN WAIT_ON_RST =>
bgouten <= '1';
sysrstn_out_int <= '1'; -- no reset to vme-bus
clr_sysr <= '0';
v2p_rst_int <= '0'; -- no reset to cpu
IF (degl_rst = '1' OR sysr_bit = '1') AND sysc_bit = '1' THEN -- in slot 1 and cpu or bit has active reset
rst_state <= RST_VME;
rst_pre_cnt <= '0';
rst_main_cnt <= '1';
ELSIF degl_sysrstn = '0' THEN -- not in slot 1 and vme-bus has active reset
rst_state <= RST_CPU;
rst_pre_cnt <= '1'; -- clear counter in order to set cpu 10 us to reset
rst_main_cnt <= '0';
ELSE
rst_state <= WAIT_ON_RST;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
END IF;
-- set cpu reset active
WHEN RST_CPU =>
bgouten <= '1';
sysrstn_out_int <= '1'; -- no reset to vme-bus
v2p_rst_int <= '1'; -- active reset to cpu
clr_sysr <= '0';
IF pre_cnt_end = '1' THEN -- after 10 us, release cpu reset
rst_state <= WAIT_ON_CPU;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
ELSE
rst_state <= RST_CPU;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
END IF;
-- wait until vme-reset has got deactivated
WHEN WAIT_ON_CPU =>
bgouten <= '1';
sysrstn_out_int <= '1'; -- no reset to vme-bus
v2p_rst_int <= not degl_sysrstn;
clr_sysr <= '0';
IF degl_sysrstn = '1' AND degl_rst = '0' THEN -- wait until vme-bus and cpu reset is inactive
rst_state <= WAIT_ON_RST;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
ELSE
rst_state <= WAIT_ON_CPU;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
END IF;
-- activate vme reset for (16383 * system_clock_period = 250 us @ 66MHz)
WHEN RST_VME =>
bgouten <= '1';
IF prevent_sysrst = '1' THEN
sysrstn_out_int <= '1'; -- no reset
ELSE
sysrstn_out_int <= '0'; -- active reset to vme-bus
END IF;
v2p_rst_int <= '0'; -- no reset to cpu
clr_sysr <= '1';
IF main_cnt_end = '1' THEN -- keep vme-bus reset active for counter time
rst_state <= RST_VME2;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
ELSE
rst_state <= RST_VME;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
END IF;
-- extend active vme reset time for (16383 * system_clock_period = 250 us @ 66MHz) till cpu reset has got deactivated
WHEN RST_VME2 =>
bgouten <= '1';
IF prevent_sysrst = '1' THEN
sysrstn_out_int <= '1'; -- no reset
ELSE
sysrstn_out_int <= '0'; -- active reset to vme-bus
END IF;
v2p_rst_int <= '0'; -- no reset to cpu
clr_sysr <= '1';
IF main_cnt_end = '1' AND degl_rst = '0' THEN -- wait until cpu-reset is inactive
rst_state <= WAIT_ON_VME;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
ELSE
rst_state <= RST_VME2;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
END IF;
-- wait until vme reset has got deactivated
WHEN WAIT_ON_VME =>
bgouten <= '1';
sysrstn_out_int <= '1'; -- no reset to vme-bus
v2p_rst_int <= '0'; -- no reset to cpu
clr_sysr <= '0';
IF degl_sysrstn = '1' THEN -- wait until vme-bus reset is inactive
rst_state <= WAIT_ON_RST;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
ELSE
rst_state <= WAIT_ON_VME;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
END IF;
WHEN OTHERS =>
bgouten <= '0';
sysrstn_out_int <= '1';
v2p_rst_int <= '0';
clr_sysr <= '0';
rst_state <= WAIT_ON_RST;
rst_pre_cnt <= '0';
rst_main_cnt <= '0';
END CASE;
END IF;
END PROCESS rst_fsm;
END bustimer_arc;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- package: testlib
-- file: testlib.vhd
-- author: Marko Isomaki - Aeroflex Gaisler
-- description: package for common vhdl functions for testbenches
------------------------------------------------------------------------------
-- pragma translate_off
library std;
use std.standard.all;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library grlib;
use grlib.stdio.all;
use grlib.stdlib.tost;
-- pragma translate_on
package testlib is
-- pragma translate_off
type octet_vector is array (natural range <>) of std_logic_vector(7 downto 0);
subtype data_vector8 is octet_vector;
type data_vector16 is array (natural range <>) of std_logic_vector(15 downto 0);
type data_vector32 is array (natural range <>) of std_logic_vector(31 downto 0);
type data_vector64 is array (natural range <>) of std_logic_vector(63 downto 0);
type data_vector128 is array (natural range <>) of std_logic_vector(127 downto 0);
type data_vector256 is array (natural range <>) of std_logic_vector(255 downto 0);
type nibble_vector is array (natural range <>) of std_logic_vector(3 downto 0);
subtype data_vector is data_vector32;
-----------------------------------------------------------------------------
-- compare function handling '-'. c is the expected data parameter. If it is
--'-' or 'U' then this bit is not compared. Returns true if the vectors match
-----------------------------------------------------------------------------
function compare(o, c: in std_logic_vector) return boolean;
-----------------------------------------------------------------------------
-- compare function handling '-'
-----------------------------------------------------------------------------
function compare(o, c: in std_ulogic_vector) return boolean;
-----------------------------------------------------------------------------
-- this procedure prints a message to standard output. Also includes the time
-- at which it occurs.
-----------------------------------------------------------------------------
procedure print(
constant comment: in string := "-";
constant severe: in severity_level := note;
constant screen: in boolean := true);
-----------------------------------------------------------------------------
-- synchronisation with respect to clock and with output offset
-----------------------------------------------------------------------------
procedure synchronise(
signal clock: in std_ulogic;
constant offset: in time := 5 ns;
constant enable: in boolean := true);
-----------------------------------------------------------------------------
-- this procedure initialises the test error counters. Used in testbenches
-- with a test variable to check if a subtest has failed and at the end how
-- many subtests have failed. This procedure is called before the first
-- subtest
-----------------------------------------------------------------------------
procedure tinitialise(
variable test: inout boolean;
variable testcount: inout integer);
-----------------------------------------------------------------------------
-- this procedure completes the sub-test. Called at the end of each subtest
-----------------------------------------------------------------------------
procedure tintermediate(
variable test: inout boolean;
variable testcount: inout integer);
-----------------------------------------------------------------------------
-- this procedure completes the test. Called at the end of the complete test
-----------------------------------------------------------------------------
procedure tterminate(
variable test: inout boolean;
variable testcount: inout integer);
-----------------------------------------------------------------------------
-- check std_logic_vector array
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in std_logic_vector;
constant expected: in std_logic_vector;
constant message: in string := "");
-----------------------------------------------------------------------------
-- check std_logic
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in std_logic;
constant expected: in std_logic;
constant message: in string := "");
-----------------------------------------------------------------------------
-- check std_ulogic_vector array
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in std_ulogic_vector;
constant expected: in std_ulogic_vector;
constant message: in string := "");
-----------------------------------------------------------------------------
-- check natural
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in natural;
constant expected: in natural;
constant message: in string := "");
-----------------------------------------------------------------------------
-- check time
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in time;
constant expected: in time;
constant spread: in time;
constant message: in string := "");
-----------------------------------------------------------------------------
-- check boolean
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in boolean;
constant expected: in boolean;
constant message: in string := "");
-----------------------------------------------------------------------------
-- Convert Data_Vector to Octet_Vector
-----------------------------------------------------------------------------
function conv_octet_vector(
constant d: in data_vector)
return octet_vector;
-----------------------------------------------------------------------------
-- Convert Octet_Vector to Data_Vector, with padding
-----------------------------------------------------------------------------
function conv_data_vector(
constant o: in octet_vector)
return data_vector;
procedure compare(
constant data: in octet_vector;
constant cxdata: in octet_vector;
variable tP: inout boolean);
----------------------------------------------------------------------------
-- Read file contents to octet vector
----------------------------------------------------------------------------
--Expects data only in hex with four bytes on each line.
procedure readfile(
constant filename: in string := "";
constant filetype: in integer := 0;
constant size: in integer := 0;
variable dataout: out octet_vector);
--Reads bytes from a file with the format packets are output from ethereal
procedure readfile(
constant filename: in string := "";
constant size: in integer := 0;
variable dataout: out octet_vector);
----------------------------------------------------------------------------
-- Read file contents to data_vector
----------------------------------------------------------------------------
--Expects data only in hex with four bytes on each line.
procedure readfile(
constant filename: in string := "";
constant size: in integer := 0;
variable dataout: out data_vector);
--generates an random integer from 0 to the maximum value specified with max
procedure gen_rand_int(
constant max : in real;
variable seed1 : inout positive;
variable seed2 : inout positive;
variable rand : out integer);
--reverses std_logic_vector
function reverse(din : std_logic_vector) return std_logic_vector;
-- Returns offset to start of valid data for an access of size 'size' in
-- AMBA data vector
function ahb_doff (
constant dw : integer;
constant size : integer; -- access size
constant addr : std_logic_vector(4 downto 0))
return integer;
-- pragma translate_on
end package testlib;
-- pragma translate_off
--============================================================================--
package body testlib is
-----------------------------------------------------------------------------
-- compare function handling '-'
-----------------------------------------------------------------------------
function compare(o, c: in std_logic_vector) return boolean is
variable t: std_logic_vector(o'range) := c;
variable result: boolean;
begin
result := true;
for i in o'range loop
if not (o(i)=t(i) or t(i)='-' or t(i)='U') then
result := false;
end if;
end loop;
return result;
end function compare;
-----------------------------------------------------------------------------
-- compare function handling '-'
-----------------------------------------------------------------------------
function compare(o, c: in std_ulogic_vector) return boolean is
variable t: std_ulogic_vector(o'range) := c;
variable result: boolean;
begin
result := true;
for i in o'range loop
if not (o(i)=t(i) or t(i)='-' or t(i)='U') then
result := false;
end if;
end loop;
return result;
end function compare;
-----------------------------------------------------------------------------
-- this procedure prints a message to standard output
-----------------------------------------------------------------------------
procedure print(
constant comment: in string := "-";
constant severe: in severity_level := note;
constant screen: in boolean := true) is
variable l: line;
begin
if screen then
write(l, now, right, 15);
write(l, " : " & comment);
if severe = warning then
write(l, string'(" # warning, "));
elsif severe = error then
write(l, string'(" # error, "));
elsif severe = failure then
write(l, string'(" # failure, "));
end if;
writeline(output, l);
end if;
end procedure print;
-----------------------------------------------------------------------------
-- synchronisation with respect to clock and with output offset
-----------------------------------------------------------------------------
procedure synchronise(
signal clock: in std_ulogic;
constant offset: in time := 5 ns;
constant enable: in boolean := true) is
begin
if enable then
wait until clock = '1'; -- synchronise
wait for offset; -- output offset delay
end if;
end procedure synchronise;
-----------------------------------------------------------------------------
-- this procedure initialises the test error counters
-----------------------------------------------------------------------------
procedure tinitialise(
variable test: inout boolean;
variable testcount: inout integer) is
begin
--------------------------------------------------------------------------
-- initialise test status
--------------------------------------------------------------------------
test := true; -- reset any errors
testcount := 0;
print("--=========================================================--");
print("*** test initialised ***");
print("--=========================================================--");
end procedure tinitialise;
-----------------------------------------------------------------------------
-- this procedure completes the sub-test
-----------------------------------------------------------------------------
procedure tintermediate(
variable test: inout boolean;
variable testcount: inout integer) is
variable l: line;
begin
--------------------------------------------------------------------------
-- report test status
--------------------------------------------------------------------------
wait for 10 us;
print("--=========================================================--");
if test then
print("*** sub-test completed successfully ***");
if testcount > 0 then
write(l, now, right, 15);
write(l, string'(" : "));
write(l, testcount);
write(l, string'(" sub-test(s) ended with one or more errors."));
writeline(output, l);
end if;
else
print("*** sub-test completed with errors -- # error # -- ***");
testcount := testcount + 1;
test := true;
if testcount > 0 then
write(l, now, right, 15);
write(l, string'(" : "));
write(l, testcount);
write(l, string'(" sub-test(s) ended with one or more errors."));
writeline(output, l);
end if;
end if;
print("--=========================================================--");
end procedure tintermediate;
-----------------------------------------------------------------------------
-- this procedure completes the test
-----------------------------------------------------------------------------
procedure tterminate(
variable test: inout boolean;
variable testcount: inout integer) is
variable l: line;
begin
--------------------------------------------------------------------------
-- end of test
--------------------------------------------------------------------------
wait for 1 ms;
print("--=========================================================--");
if testcount = 0 then
print("*** test completed successfully ***");
else
print("*** test completed with errors -- # error # -- ***");
write(l, now, right, 15);
write(l, string'(" : "));
write(l, testcount);
write(l, string'(" sub-test(s) ended with one or more errors."));
writeline(output, l);
end if;
print("--=========================================================--");
report "---- end of test ----"
severity failure;
wait;
end procedure tterminate;
-----------------------------------------------------------------------------
-- check std_logic_vector array
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in std_logic_vector;
constant expected: in std_logic_vector;
constant message: in string := "") is
variable l: line;
constant padding: std_logic_vector(1 to
(4-(received'length mod 4))) :=
(others => '0');
begin
if not compare(received, expected) then
write(l, now, right, 15);
write(l, string'(" : ") & message & string'(" :"));
write(l, string'(" received: "));
if padding'length > 0 and padding'length < 4 then
hwrite(l, padding & std_logic_vector(received));
else
hwrite(l, std_logic_vector(received));
end if;
write(l, string'(" expected: "));
if padding'length > 0 and padding'length < 4 then
hwrite(l, padding & std_logic_vector(expected));
else
hwrite(l, std_logic_vector(expected));
end if;
write(l, string'(" # error"));
writeline(output, l);
tp := false;
end if;
end procedure check;
-----------------------------------------------------------------------------
-- check std_logic
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in std_logic;
constant expected: in std_logic;
constant message: in string := "") is
variable l: line;
begin
if not (to_x01z(received)=to_x01z(expected)) then
write(l, now, right, 15);
write(l, string'(" : ") & message & string'(" :"));
write(l, string'(" received: "));
write(l, received);
write(l, string'(" expected: "));
write(l, expected);
write(l, string'(" # error"));
writeline(output, l);
tp := false;
end if;
end procedure check;
-----------------------------------------------------------------------------
-- check std_ulogic_vector array
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in std_ulogic_vector;
constant expected: in std_ulogic_vector;
constant message: in string := "") is
variable l: line;
constant padding: std_ulogic_vector(1 to
(4-(received'length mod 4))) :=
(others => '0');
begin
if not compare(received, expected) then
write(l, now, right, 15);
write(l, string'(" : ") & message & string'(" :"));
write(l, string'(" received: "));
if padding'length > 0 and padding'length < 4 then
hwrite(l, std_logic_vector(padding) & std_logic_vector(received));
else
hwrite(l, std_logic_vector(received));
end if;
write(l, string'(" expected: "));
if padding'length > 0 and padding'length < 4 then
hwrite(l, std_logic_vector(padding) & std_logic_vector(expected));
else
hwrite(l, std_logic_vector(expected));
end if;
write(l, string'(" # error"));
writeline(output, l);
tp := false;
end if;
end procedure check;
-----------------------------------------------------------------------------
-- check natural
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in natural;
constant expected: in natural;
constant message: in string := "") is
variable l: line;
begin
if received /= expected then
write(l, now, right, 15);
write(l, string'(" : ") & message & string'(" :"));
write(l, string'(" received: "));
write(l, received);
write(l, string'(" expected: "));
write(l, expected);
write(l, string'(" # error"));
writeline(output, l);
tp := false;
end if;
end procedure check;
-----------------------------------------------------------------------------
-- check time
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in time;
constant expected: in time;
constant spread: in time;
constant message: in string := "") is
variable l: line;
begin
if (received > expected+spread) or
(received < expected-spread) then
write(l, now, right, 15);
write(l, string'(" : ") & message & string'(" :"));
write(l, string'(" received: "));
write(l, received);
write(l, string'(" expected: "));
write(l, expected);
write(l, string'(" # error"));
writeline(output, l);
tp := false;
end if;
end procedure check;
-----------------------------------------------------------------------------
-- check boolean
-----------------------------------------------------------------------------
procedure check(
variable tp: inout boolean;
constant received: in boolean;
constant expected: in boolean;
constant message: in string := "") is
variable l: line;
begin
if received /= expected then
write(l, now, right, 15);
write(l, string'(" : ") & message & string'(" :"));
write(l, string'(" received: "));
write(l, received);
write(l, string'(" expected: "));
write(l, expected);
write(l, string'(" # error"));
writeline(output, l);
tp := false;
end if;
end procedure check;
-----------------------------------------------------------------------------
-- Convert Data_Vector to Octet_Vector
-----------------------------------------------------------------------------
function conv_octet_vector(
constant d: in data_vector)
return octet_vector is
variable o: octet_vector(0 to d'Length*4-1);
begin
for i in o'range loop
o(i) := d(i/4)((3-(i mod 4))*8+7 downto (3-(i mod 4))*8);
end loop;
return o;
end function conv_octet_vector;
-----------------------------------------------------------------------------
-- Convert Octet_Vector to Data_Vector, with padding
-----------------------------------------------------------------------------
function conv_data_vector(
constant o: in octet_vector)
return data_vector is
variable d: data_vector(0 to (1+(o'Length-1)/4)-1);
begin
for i in o'Range loop
d(i/4)((3-(i mod 4))*8+7 downto (3-(i mod 4))*8) := o(i);
end loop;
return d;
end function conv_data_vector;
procedure compare(
constant data: in octet_vector;
constant cxdata: in octet_vector;
variable tp: inout boolean) is
begin
if (data'length /= cxdata'length) then
tp := false;
print("compare error: lengths do not match");
else
for i in data'low to data'low+data'length-1 loop
if not compare(data(i), cxdata(i)) then
tp := false;
print("compare error. index: " & tost(i) & " data: " & tost(data(i)) & " expected: " & tost(cxdata(i)));
end if;
end loop;
end if;
end compare;
function FromChar(C: Character) return Std_Logic_Vector is
variable R: Std_Logic_Vector(0 to 3);
begin
case C is
when '0' => R := "0000";
when '1' => R := "0001";
when '2' => R := "0010";
when '3' => R := "0011";
when '4' => R := "0100";
when '5' => R := "0101";
when '6' => R := "0110";
when '7' => R := "0111";
when '8' => R := "1000";
when '9' => R := "1001";
when 'A' => R := "1010";
when 'B' => R := "1011";
when 'C' => R := "1100";
when 'D' => R := "1101";
when 'E' => R := "1110";
when 'F' => R := "1111";
when 'a' => R := "1010";
when 'b' => R := "1011";
when 'c' => R := "1100";
when 'd' => R := "1101";
when 'e' => R := "1110";
when 'f' => R := "1111";
when others => R := "XXXX";
end case;
return R;
end FromChar;
procedure readfile(
constant filename: in string := "";
constant filetype: in integer := 0;
constant size: in integer := 0;
variable dataout: out octet_vector) is
file readfile: text;
variable l: line;
variable test: boolean := true;
variable count: integer := 0;
variable dtmp: std_logic_vector(31 downto 0);
variable data: octet_vector(0 to size-1);
variable i: integer := 0;
variable good: boolean := true;
variable c: character;
begin
if size /= 0 then
if filename = "" then
print("no file given");
else
if filetype = 0 then
file_open(readfile, filename, read_mode);
while not endfile(readfile) loop
readline(readfile, l);
hread(l, dtmp, test);
if (not test) then
print("illegal data in file");
exit;
end if;
for i in 0 to 3 loop
data(count) := dtmp(31-i*8 downto 24-i*8);
count := count + 1;
if count >= size then
exit;
end if;
end loop;
if count >= size then
exit;
end if;
end loop;
if count < size then
print("not enough data in file");
else
for i in 0 to size-1 loop
dataout(dataout'low+i) := data(i);
end loop;
end if;
else
file_open(readfile, filename, read_mode);
while not endfile(readfile) loop
readline(readfile, L);
while (i < 4) loop
Read(L, C, good);
if not good then
Print("Error in read data");
exit;
end if;
if (C = character'val(32)) or (C = character'val(160)) or (C = HT) then
next;
else
i := i + 1;
end if;
end loop;
i := 0;
while (i < 32) loop
Read(L, C, good);
if not good then
Print("Error in read data");
exit;
end if;
if (C = character'val(32)) or (C = character'val(160)) or (C = HT) then
next;
else
if (i mod 2) = 0 then
data(count)(7 downto 4) := fromchar(C);
else
data(count)(3 downto 0) := fromchar(C);
-- Print(tost(data(count)));
count := count + 1;
if count >= size then
exit;
end if;
end if;
i := i + 1;
end if;
end loop;
i := 0;
end loop;
if count < size then
Print("Not enough data in file");
else
dataout := data;
end if;
end if;
end if;
else
print("size is zero. no data read");
end if;
end procedure;
procedure readfile(
constant filename: in string := "";
constant size: in integer := 0;
variable dataout: out octet_vector) is
begin
readfile(filename, 0, size, dataout);
end procedure;
procedure readfile(
constant filename: in string := "";
constant size: in integer := 0;
variable dataout: out data_vector) is
file readfile: text;
variable l: line;
variable test: boolean := true;
variable count: integer := 0;
variable data: data_vector(0 to size/4);
begin
if size /= 0 then
if filename = "" then
print("no file given");
else
file_open(readfile, filename, read_mode);
while not endfile(readfile) loop
readline(readfile, l);
hread(l, data(count/4), test);
if (not test) then
print("illegal data in file");
exit;
end if;
count := count + 4;
if count >= size then
exit;
end if;
end loop;
if count < size then
print("not enough data in file");
else
if (size mod 4) = 0 then
dataout(dataout'low to dataout'low+data'high-1) :=
data(0 to data'high-1);
else
dataout(dataout'low to dataout'low+data'high) := data(0 to data'high);
end if;
end if;
end if;
else
print("size is zero. no data read");
end if;
end procedure;
procedure gen_rand_int(
constant max : in real;
variable seed1 : inout positive;
variable seed2 : inout positive;
variable rand : out integer) is
variable rand_tmp : real;
begin
uniform(seed1, seed2, rand_tmp);
rand := integer(floor(rand_tmp*max));
end procedure;
function reverse(din : std_logic_vector)
return std_logic_vector is
variable dout: std_logic_vector(din'REVERSE_RANGE);
begin
for i in din'RANGE loop dout(i) := din(i); end loop;
return dout;
end function reverse;
function ahb_doff (
constant dw : integer;
constant size : integer;
constant addr : std_logic_vector(4 downto 0))
return integer is
variable off : integer;
begin -- ahb_doff
if size < 256 and dw = 256 and addr(4) = '0' then off := 128; else off := 0; end if;
if size < 128 and dw >= 128 and addr(3) = '0' then off := off + 64; end if;
if size < 64 and dw >= 64 and addr(2) = '0' then off := off + 32; end if;
if size < 32 and addr(1) = '0' then off := off + 16; end if;
if size < 16 and addr(0) = '0' then off := off + 8; end if;
return off;
end ahb_doff;
end package body ; --=======================================--
-- pragma translate_on
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3185.vhd,v 1.3 2001-10-29 02:12:44 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library std;
use std.TEXTIO.all;
ENTITY c14s03b00x00p42n01i03185ent IS
END c14s03b00x00p42n01i03185ent;
ARCHITECTURE c14s03b00x00p42n01i03185arch OF c14s03b00x00p42n01i03185ent IS
BEGIN
TESTING: PROCESS
file F : TEXT open write_mode is "iofile.02";
variable L : LINE;
BEGIN
--write out to the file
for I in 1 to 100 loop
WRITE (L,integer'(1994));
WRITELINE (F, L);
end loop;
assert FALSE
report "***PASSED TEST: c14s03b00x00p42n01i03185 - This test will write TEXT of integer type into file iofile.02."
severity NOTE;
wait;
END PROCESS TESTING;
END c14s03b00x00p42n01i03185arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3185.vhd,v 1.3 2001-10-29 02:12:44 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library std;
use std.TEXTIO.all;
ENTITY c14s03b00x00p42n01i03185ent IS
END c14s03b00x00p42n01i03185ent;
ARCHITECTURE c14s03b00x00p42n01i03185arch OF c14s03b00x00p42n01i03185ent IS
BEGIN
TESTING: PROCESS
file F : TEXT open write_mode is "iofile.02";
variable L : LINE;
BEGIN
--write out to the file
for I in 1 to 100 loop
WRITE (L,integer'(1994));
WRITELINE (F, L);
end loop;
assert FALSE
report "***PASSED TEST: c14s03b00x00p42n01i03185 - This test will write TEXT of integer type into file iofile.02."
severity NOTE;
wait;
END PROCESS TESTING;
END c14s03b00x00p42n01i03185arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3185.vhd,v 1.3 2001-10-29 02:12:44 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library std;
use std.TEXTIO.all;
ENTITY c14s03b00x00p42n01i03185ent IS
END c14s03b00x00p42n01i03185ent;
ARCHITECTURE c14s03b00x00p42n01i03185arch OF c14s03b00x00p42n01i03185ent IS
BEGIN
TESTING: PROCESS
file F : TEXT open write_mode is "iofile.02";
variable L : LINE;
BEGIN
--write out to the file
for I in 1 to 100 loop
WRITE (L,integer'(1994));
WRITELINE (F, L);
end loop;
assert FALSE
report "***PASSED TEST: c14s03b00x00p42n01i03185 - This test will write TEXT of integer type into file iofile.02."
severity NOTE;
wait;
END PROCESS TESTING;
END c14s03b00x00p42n01i03185arch;
|
component pr_region_alternate_clock_in is
port (
in_clk : in std_logic := 'X'; -- clk
out_clk : out std_logic -- clk
);
end component pr_region_alternate_clock_in;
u0 : component pr_region_alternate_clock_in
port map (
in_clk => CONNECTED_TO_in_clk, -- in_clk.clk
out_clk => CONNECTED_TO_out_clk -- out_clk.clk
);
|
---------------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------------
-- File : switch_fab_1.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 13/08/07
---------------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------------
-- Description :
--!\reqid
--!\upreqid
---------------------------------------------------------------------
--!\hierarchy
--!\endofhierarchy
---------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------------
-- History
---------------------------------------------------------------------
-- $Revision: 1.4 $
--
-- $Log: switch_fab_1.vhd,v $
-- Revision 1.4 2015/06/15 16:39:52 AGeissler
-- R1: In 16z100- version 1.30 the bte signal was removed from the wb_pkg.vhd
-- M1: Adapted switch fabric
-- R2: Clearness
-- M2: Replaced tabs with spaces
--
-- Revision 1.3 2009/07/29 14:05:11 FLenhardt
-- Fixed bug (WB slave strobe had been activated without addressing)
--
-- Revision 1.2 2007/08/13 17:04:22 FWombacher
-- fixed typos
--
-- Revision 1.1 2007/08/13 16:28:20 MMiehling
-- Initial Revision
--
--
---------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.wb_pkg.all;
ENTITY switch_fab_1 IS
GENERIC (
registered : IN boolean
);
PORT (
clk : IN std_logic;
rst : IN std_logic;
-- wb-bus #0
cyc_0 : IN std_logic;
ack_0 : OUT std_logic;
err_0 : OUT std_logic;
wbo_0 : IN wbo_type;
-- wb-bus to slave
wbo_slave : IN wbi_type;
wbi_slave : OUT wbo_type;
wbi_slave_cyc : OUT std_logic
);
END switch_fab_1;
ARCHITECTURE switch_fab_1_arch OF switch_fab_1 IS
SIGNAL wbi_slave_stb : std_logic;
BEGIN
wbi_slave_cyc <= cyc_0;
wbi_slave.stb <= wbi_slave_stb;
ack_0 <= wbo_slave.ack AND wbi_slave_stb;
err_0 <= wbo_slave.err AND wbi_slave_stb;
wbi_slave.dat <= wbo_0.dat;
wbi_slave.adr <= wbo_0.adr;
wbi_slave.sel <= wbo_0.sel;
wbi_slave.we <= wbo_0.we;
wbi_slave.cti <= wbo_0.cti;
wbi_slave.tga <= wbo_0.tga;
PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
wbi_slave_stb <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF cyc_0 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_0.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_0.stb;
ELSIF wbo_slave.ack = '1' AND wbo_0.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_0.stb;
END IF;
ELSE
wbi_slave_stb <= '0';
END IF;
END IF;
END PROCESS;
END switch_fab_1_arch;
|
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: madd - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.all;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pruning_test is
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
cand : in data_type;
closest_cand : in data_type;
bnd_lo : in data_type;
bnd_hi : in data_type;
result : out std_logic;
rdy : out std_logic
);
end pruning_test;
architecture Behavioral of pruning_test is
constant SUB_LATENCY : integer := 2;
constant LAYERS_TREE_ADDER : integer := integer(ceil(log2(real(D))));
constant SCALE_MUL_RESULT : integer := MUL_FRACTIONAL_BITS;
-- latency of the entire unit
constant LATENCY : integer := 2*SUB_LATENCY+MUL_CORE_LATENCY+SUB_LATENCY*LAYERS_TREE_ADDER;
type sub_res_array_type is array(0 to D-1) of std_logic_vector(COORD_BITWIDTH+1-1 downto 0);
type sub_res_array_delay_type is array(0 to SUB_LATENCY-1) of sub_res_array_type;
type mul_res_array_type is array(0 to D-1) of std_logic_vector(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1-1 downto 0);
--type tree_adder_res_array_type is array(0 to LAYERS_TREE_ADDER-1, 0 to D/2-1) of std_logic_vector(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1 downto 0);
type data_delay_type is array(0 to SUB_LATENCY-1) of data_type;
component addorsub
generic (
USE_DSP : boolean := true;
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end component;
component madd
generic (
MUL_LATENCY : integer := 3;
A_BITWIDTH : integer := 16;
B_BITWIDTH : integer := 16;
INCLUDE_ADD : boolean := false;
C_BITWIDTH : integer := 16;
RES_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
a : in std_logic_vector(A_BITWIDTH-1 downto 0);
b : in std_logic_vector(B_BITWIDTH-1 downto 0);
c : in std_logic_vector(C_BITWIDTH-1 downto 0);
res : out std_logic_vector(RES_BITWIDTH-1 downto 0);
rdy : out std_logic
);
end component;
component adder_tree
generic (
NUMBER_OF_INPUTS : integer := 4;
INPUT_BITWIDTH : integer := 16
);
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
sub : in std_logic;
input_string : in std_logic_vector(NUMBER_OF_INPUTS*INPUT_BITWIDTH-1 downto 0);
rdy : out std_logic;
output : out std_logic_vector(INPUT_BITWIDTH+integer(ceil(log2(real(NUMBER_OF_INPUTS))))-1 downto 0)
);
end component;
signal tmp_diff_1 : sub_res_array_type;
signal tmp_diff_1_rdy : std_logic;
signal tmp_input_2 : data_type;
signal tmp_diff_2 : sub_res_array_type;
signal tmp_diff_2_rdy : std_logic;
signal diff_1_delay_line : sub_res_array_delay_type;
signal tmp_diff_1_1 : sub_res_array_type;
signal tmp_mul_1 : mul_res_array_type;
signal tmp_mul_1_rdy : std_logic;
signal tmp_mul_2 : mul_res_array_type;
signal tmp_mul_2_rdy : std_logic;
signal const_0 : std_logic_vector(MUL_BITWIDTH-1 downto 0);
--signal tmp_tree_adder_res_1 : tree_adder_res_array_type;
signal tmp_tree_adder_1_input_string : std_logic_vector(D*(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1)-1 downto 0);
signal tmp_tree_adder_res_1_clean : std_logic_vector(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1 downto 0);
signal tmp_tree_adder_res_1_ext : std_logic_vector(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER+1-1 downto 0);
signal tmp_tree_adder_1_rdy : std_logic;
--signal tmp_tree_adder_res_2 : tree_adder_res_array_type;
signal tmp_tree_adder_2_input_string : std_logic_vector(D*(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1)-1 downto 0);
signal tmp_tree_adder_res_2_clean : std_logic_vector(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER-1 downto 0);
signal tmp_tree_adder_res_2_ext : std_logic_vector(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1+LAYERS_TREE_ADDER+1-1 downto 0);
--signal delay_line_tree_adder : std_logic_vector(0 to SUB_LATENCY*LAYERS_TREE_ADDER-1);
signal bndbox_delay_lo : data_delay_type;
signal bndbox_delay_hi : data_delay_type;
signal closest_cand_delay : data_delay_type;
signal tmp_final_result : std_logic;
begin
G1: for I in 0 to D-1 generate
G_FIRST: if I = 0 generate
addorsub_inst : addorsub
generic map (
USE_DSP => USE_DSP_FOR_ADD,
A_BITWIDTH => COORD_BITWIDTH,
B_BITWIDTH => COORD_BITWIDTH,
RES_BITWIDTH => COORD_BITWIDTH+1
)
port map (
clk => clk,
sclr => sclr,
nd => nd,
sub => '1',
a => cand(I),
b => closest_cand(I),
res => tmp_diff_1(I), -- ccComp
rdy => tmp_diff_1_rdy
);
end generate G_FIRST;
G_OTHER: if I > 0 generate
addorsub_inst : addorsub
generic map (
USE_DSP => USE_DSP_FOR_ADD,
A_BITWIDTH => COORD_BITWIDTH,
B_BITWIDTH => COORD_BITWIDTH,
RES_BITWIDTH => COORD_BITWIDTH+1
)
port map (
clk => clk,
sclr => sclr,
nd => nd,
sub => '1',
a => cand(I),
b => closest_cand(I),
res => tmp_diff_1(I), --ccComp
rdy => open
);
end generate G_OTHER;
end generate G1;
-- delay bndbox
bndbox_delay_proc : process(clk)
begin
if rising_edge(clk) then
bndbox_delay_lo(0) <= bnd_lo;
bndbox_delay_lo(1 to SUB_LATENCY-1) <= bndbox_delay_lo(0 to SUB_LATENCY-2);
bndbox_delay_hi(0) <= bnd_hi;
bndbox_delay_hi(1 to SUB_LATENCY-1) <= bndbox_delay_hi(0 to SUB_LATENCY-2);
closest_cand_delay(0) <= closest_cand;
closest_cand_delay(1 to SUB_LATENCY-1) <= closest_cand_delay(0 to SUB_LATENCY-2);
end if;
end process bndbox_delay_proc;
G2: for I in 0 to D-1 generate
tmp_input_2(I) <= bndbox_delay_hi(SUB_LATENCY-1)(I) WHEN signed(tmp_diff_1(I)) > 0 ELSE bndbox_delay_lo(SUB_LATENCY-1)(I);
G_FIRST: if I = 0 generate
addorsub_inst : addorsub
generic map (
USE_DSP => USE_DSP_FOR_ADD,
A_BITWIDTH => COORD_BITWIDTH,
B_BITWIDTH => COORD_BITWIDTH,
RES_BITWIDTH => COORD_BITWIDTH+1
)
port map (
clk => clk,
sclr => sclr,
nd => tmp_diff_1_rdy,
sub => '1',
a => tmp_input_2(I),
b => closest_cand_delay(SUB_LATENCY-1)(I),
res => tmp_diff_2(I),
rdy => tmp_diff_2_rdy
);
end generate G_FIRST;
G_OTHER: if I > 0 generate
addorsub_inst : addorsub
generic map (
USE_DSP => USE_DSP_FOR_ADD,
A_BITWIDTH => COORD_BITWIDTH,
B_BITWIDTH => COORD_BITWIDTH,
RES_BITWIDTH => COORD_BITWIDTH+1
)
port map (
clk => clk,
sclr => sclr,
nd => tmp_diff_1_rdy,
sub => '1',
a => tmp_input_2(I),
b => closest_cand_delay(SUB_LATENCY-1)(I),
res => tmp_diff_2(I),
rdy => open
);
end generate G_OTHER;
end generate G2;
-- delay tmp_diff_1
diff_1_delay_line_proc : process(clk)
begin
if rising_edge(clk) then
diff_1_delay_line(0) <= tmp_diff_1;
diff_1_delay_line(1 to SUB_LATENCY-1) <= diff_1_delay_line(0 to SUB_LATENCY-2);
end if;
end process diff_1_delay_line_proc;
tmp_diff_1_1 <= diff_1_delay_line(SUB_LATENCY-1);
const_0 <= (others => '0');
G3: for I in 0 to D-1 generate
G_FIRST: if I = 0 generate
madd_inst_1 : madd
generic map(
MUL_LATENCY => MUL_CORE_LATENCY,
A_BITWIDTH => MUL_BITWIDTH,
B_BITWIDTH => MUL_BITWIDTH,
INCLUDE_ADD => false,
C_BITWIDTH => MUL_BITWIDTH,
RES_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1
)
port map (
clk => clk,
sclr => sclr,
nd => tmp_diff_2_rdy,
a => saturate(tmp_diff_1_1(I)),
b => saturate(tmp_diff_1_1(I)),
c => const_0,
res => tmp_mul_1(I),
rdy => tmp_mul_1_rdy
);
madd_inst_2 : madd
generic map(
MUL_LATENCY => MUL_CORE_LATENCY,
A_BITWIDTH => MUL_BITWIDTH,
B_BITWIDTH => MUL_BITWIDTH,
INCLUDE_ADD => false,
C_BITWIDTH => MUL_BITWIDTH,
RES_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1
)
port map (
clk => clk,
sclr => sclr,
nd => tmp_diff_2_rdy,
a => saturate(tmp_diff_2(I)),
b => saturate(tmp_diff_1_1(I)),
c => const_0,
res => tmp_mul_2(I),
rdy => tmp_mul_2_rdy
);
end generate G_FIRST;
G_OTHER: if I > 0 generate
madd_inst_1 : madd
generic map(
MUL_LATENCY => MUL_CORE_LATENCY,
A_BITWIDTH => MUL_BITWIDTH,
B_BITWIDTH => MUL_BITWIDTH,
INCLUDE_ADD => false,
C_BITWIDTH => MUL_BITWIDTH,
RES_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1
)
port map (
clk => clk,
sclr => sclr,
nd => tmp_diff_2_rdy,
a => saturate(tmp_diff_1_1(I)),
b => saturate(tmp_diff_1_1(I)),
c => const_0,
res => tmp_mul_1(I),
rdy => open
);
madd_inst_2 : madd
generic map(
MUL_LATENCY => MUL_CORE_LATENCY,
A_BITWIDTH => MUL_BITWIDTH,
B_BITWIDTH => MUL_BITWIDTH,
INCLUDE_ADD => false,
C_BITWIDTH => MUL_BITWIDTH,
RES_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1
)
port map (
clk => clk,
sclr => sclr,
nd => tmp_diff_2_rdy,
a => saturate(tmp_diff_2(I)),
b => saturate(tmp_diff_1_1(I)),
c => const_0,
res => tmp_mul_2(I),
rdy => open
);
end generate G_OTHER;
end generate G3;
-- adder trees
G4 : for I in 0 to D-1 generate
tmp_tree_adder_1_input_string((I+1)*(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1)-1 downto I*(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1)) <= tmp_mul_1(I);
tmp_tree_adder_2_input_string((I+1)*(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1)-1 downto I*(2*MUL_BITWIDTH-SCALE_MUL_RESULT+1)) <= tmp_mul_2(I);
end generate G4;
adder_tree_inst_1 : adder_tree
generic map (
NUMBER_OF_INPUTS => D,
INPUT_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1
)
port map(
clk => clk,
sclr => sclr,
nd => tmp_mul_1_rdy,
sub => '0',
input_string => tmp_tree_adder_1_input_string,
rdy => tmp_tree_adder_1_rdy,
output => tmp_tree_adder_res_1_clean
);
adder_tree_inst_2 : adder_tree
generic map (
NUMBER_OF_INPUTS => D,
INPUT_BITWIDTH => 2*MUL_BITWIDTH-SCALE_MUL_RESULT+1
)
port map(
clk => clk,
sclr => sclr,
nd => tmp_mul_1_rdy,
sub => '0',
input_string => tmp_tree_adder_2_input_string,
rdy => open,
output => tmp_tree_adder_res_2_clean
);
-- 1*tmp_tree_adder_res_1_clean (always positive)
tmp_tree_adder_res_1_ext <= '0' & tmp_tree_adder_res_1_clean;
-- 2*tmp_tree_adder_res_2_clean
tmp_tree_adder_res_2_ext <= tmp_tree_adder_res_2_clean & '0';
--tmp_final_result <= '1';-- WHEN signed(tmp_tree_adder_res_1_ext) > signed(tmp_tree_adder_res_2_ext) ELSE '0';
--rdy <= delay_line_tree_adder(SUB_LATENCY*LAYERS_TREE_ADDER-1);
rdy <= tmp_tree_adder_1_rdy;
result <= '1' WHEN signed(tmp_tree_adder_res_1_ext) > signed(tmp_tree_adder_res_2_ext) ELSE '0';
end Behavioral;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arbiter is
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR
RTS: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
--err_East_Req_E,
--err_West_Req_W,
--err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
--err_North_Req_E,
--err_East_Req_W,
--err_West_Req_S,
err_South_Req_L,
--err_IDLE_Req_E,
--err_Local_Req_E,
--err_North_Req_W,
--err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
--err_IDLE_Req_W,
--err_Local_Req_W,
--err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
--err_South_Req_E,
--err_IDLE_Req_S,
--err_Local_Req_S,
--err_North_Req_L,
err_East_Req_N,
--err_West_Req_E,
--err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
--err_DCTS_RTS_FF_state_Grant_L,
--err_DCTS_RTS_FF_state_Grant_N,
--err_DCTS_RTS_FF_state_Grant_E,
--err_DCTS_RTS_FF_state_Grant_W,
--err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel : out std_logic
--err_state_local_xbar_sel : out std_logic
);
end;
architecture behavior of Arbiter is
-- next
-- Arbiter router or NI
-- ------------------------------------- ----
-- from LBDR ---> |Req(s) RTS | -----> |DRTS
-- To FIFO <--- |Grant(s) DCTS| <----- |CTS
-- to XBAR <--- |Xbar_sel | |
-- ------------------------------------- ----
--------------------------------------------------------------------------------------------
-- an example of a request/grant + handshake process with next router or NI
--CLK _|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|__
-- Req _____|'''''''''''''''''''''''''''''''''''''''''''|________
-- _________ ___________________ _______ _______ _______ ____
-- TX _________X_______HEADER______X_Body__X_Body__X__Tail_X____
-- Grant _________________________|'''|___|'''|___|'''|____________
-- RTs _________|'''''''''''''''''''|___|'''''''|___|'''''''|____
-- DCTS _________________________|'''|_______|'''|_______|'''|____
-- |<---------clear----------->|
-- | to send |
--------------------------------------------------------------------------------------------
-- TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SUBTYPE STATE_TYPE IS STD_LOGIC_VECTOR (5 downto 0);
CONSTANT IDLE: STATE_TYPE := "000001";
CONSTANT Local: STATE_TYPE := "000010";
CONSTANT North: STATE_TYPE := "000100";
CONSTANT East: STATE_TYPE := "001000";
CONSTANT West: STATE_TYPE := "010000";
CONSTANT South: STATE_TYPE := "100000";
SIGNAL state, state_in, next_state : STATE_TYPE := IDLE;
SIGNAL RTS_FF, RTS_FF_in: std_logic;
signal Grant_N_sig, Grant_E_sig, Grant_W_sig, Grant_S_sig, Grant_L_sig: std_logic;
signal Xbar_sel_sig: std_logic_vector(4 downto 0);
component Arbiter_checkers is
port (
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic;
DCTS: in std_logic;
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L: in std_logic;
Xbar_sel : in std_logic_vector(4 downto 0);
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
next_state_out: in std_logic_vector (5 downto 0);
RTS_FF: in std_logic;
RTS_FF_in: in std_logic;
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
--err_East_Req_E,
--err_West_Req_W,
--err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
--err_North_Req_E,
--err_East_Req_W,
--err_West_Req_S,
err_South_Req_L,
--err_IDLE_Req_E,
--err_Local_Req_E,
--err_North_Req_W,
--err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
--err_IDLE_Req_W,
--err_Local_Req_W,
--err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
--err_South_Req_E,
--err_IDLE_Req_S,
--err_Local_Req_S,
--err_North_Req_L,
err_East_Req_N,
--err_West_Req_E,
--err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
--err_DCTS_RTS_FF_state_Grant_L,
--err_DCTS_RTS_FF_state_Grant_N,
--err_DCTS_RTS_FF_state_Grant_E,
--err_DCTS_RTS_FF_state_Grant_W,
--err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel : out std_logic
--err_state_local_xbar_sel : out std_logic
);
end component;
begin
-- Arbiter checkers instantiation
ARBITERCHECKERS: Arbiter_checkers port map (
Req_N => Req_N,
Req_E => Req_E,
Req_W => Req_W,
Req_S => Req_S,
Req_L => Req_L,
DCTS => DCTS,
Grant_N => Grant_N_sig,
Grant_E => Grant_E_sig,
Grant_W => Grant_W_sig,
Grant_S => Grant_S_sig,
Grant_L => Grant_L_sig,
Xbar_sel=>Xbar_sel_sig,
state => state,
state_in => state_in,
next_state_out => next_state,
RTS_FF => RTS_FF,
RTS_FF_in => RTS_FF_in,
err_state_IDLE_xbar => err_state_IDLE_xbar,
err_state_not_IDLE_xbar => err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in => err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in => err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in => err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state => err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state => err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants => err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants => err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants => err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE => err_Requests_next_state_IDLE,
err_IDLE_Req_L => err_IDLE_Req_L,
err_Local_Req_L => err_Local_Req_L,
err_North_Req_N => err_North_Req_N,
err_IDLE_Req_N => err_IDLE_Req_N,
err_Local_Req_N => err_Local_Req_N,
err_South_Req_L => err_South_Req_L,
err_West_Req_L => err_West_Req_L,
err_South_Req_N => err_South_Req_N,
err_East_Req_L => err_East_Req_L,
err_West_Req_N => err_West_Req_N,
err_East_Req_N => err_East_Req_N,
err_next_state_onehot => err_next_state_onehot,
err_state_in_onehot => err_state_in_onehot,
err_state_north_xbar_sel => err_state_north_xbar_sel,
err_state_east_xbar_sel => err_state_east_xbar_sel,
err_state_west_xbar_sel => err_state_west_xbar_sel,
err_state_south_xbar_sel => err_state_south_xbar_sel
);
-- process for updating the state of arbiter's FSM, also setting RTS based on the state (if Grant is given or not)
process(clk, reset)begin
if reset = '0' then
state<=IDLE;
RTS_FF <= '0';
elsif clk'event and clk = '1' then
-- no grant given yet, it might be that there is no request to
-- arbiter or request is there, but the next router's/NI's FIFO is full
state <= state_in;
RTS_FF <= RTS_FF_in;
end if;
end process;
-- anything below here is pure combinational
RTS <= RTS_FF;
-- Becuase of checkers we did this!
Grant_N <= Grant_N_sig;
Grant_E <= Grant_E_sig;
Grant_W <= Grant_W_sig;
Grant_S <= Grant_S_sig;
Grant_L <= Grant_L_sig;
Xbar_sel <= Xbar_sel_sig;
process(RTS_FF, DCTS, state, next_state)begin
if RTS_FF = '1' and DCTS = '0' then
state_in <= state;
else
state_in <= next_state;
end if;
end process;
process(state, RTS_FF, DCTS)begin
if state = IDLE then
RTS_FF_in <= '0';
-- if there was a grant given to one of the inputs,
-- tell the next router/NI that the output data is valid
else
if RTS_FF = '1' and DCTS = '1' then
RTS_FF_in <= '0';
else
RTS_FF_in <= '1';
end if;
end if ;
end process;
-- sets the grants using round robin
-- the order is L --> N --> E --> W --> S and then back to L
process(state, Req_N, Req_E, Req_W, Req_S, Req_L, DCTS, RTS_FF)begin
Grant_N_sig <= '0';
Grant_E_sig <= '0';
Grant_W_sig <= '0';
Grant_S_sig <= '0';
Grant_L_sig <= '0';
Xbar_sel_sig <= "00000";
case(state) is
when IDLE =>
Xbar_sel_sig <= "00000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
when North =>
Grant_N_sig <= DCTS and RTS_FF ;
Xbar_sel_sig <= "00001";
If Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
else
next_state <= IDLE;
end if;
when East =>
Grant_E_sig <= DCTS and RTS_FF;
Xbar_sel_sig <= "00010";
If Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
else
next_state <= IDLE;
end if;
when West =>
Grant_W_sig <= DCTS and RTS_FF;
Xbar_sel_sig <= "00100";
If Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
else
next_state <= IDLE;
end if;
when South =>
Grant_S_sig <= DCTS and RTS_FF;
Xbar_sel_sig <= "01000";
If Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
else
next_state <= IDLE;
end if;
when others => -- Local
Grant_L_sig <= DCTS and RTS_FF;
Xbar_sel_sig <= "10000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
end case ;
end process;
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arbiter is
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
DCTS: in std_logic; -- Getting the CTS signal from the input FIFO of the next router/NI (for hand-shaking)
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
Xbar_sel : out std_logic_vector(4 downto 0); -- select lines for XBAR
RTS: out std_logic; -- Valid output which is sent to the next router/NI to specify that the data on the output port is valid
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
--err_East_Req_E,
--err_West_Req_W,
--err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
--err_North_Req_E,
--err_East_Req_W,
--err_West_Req_S,
err_South_Req_L,
--err_IDLE_Req_E,
--err_Local_Req_E,
--err_North_Req_W,
--err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
--err_IDLE_Req_W,
--err_Local_Req_W,
--err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
--err_South_Req_E,
--err_IDLE_Req_S,
--err_Local_Req_S,
--err_North_Req_L,
err_East_Req_N,
--err_West_Req_E,
--err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
--err_DCTS_RTS_FF_state_Grant_L,
--err_DCTS_RTS_FF_state_Grant_N,
--err_DCTS_RTS_FF_state_Grant_E,
--err_DCTS_RTS_FF_state_Grant_W,
--err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel : out std_logic
--err_state_local_xbar_sel : out std_logic
);
end;
architecture behavior of Arbiter is
-- next
-- Arbiter router or NI
-- ------------------------------------- ----
-- from LBDR ---> |Req(s) RTS | -----> |DRTS
-- To FIFO <--- |Grant(s) DCTS| <----- |CTS
-- to XBAR <--- |Xbar_sel | |
-- ------------------------------------- ----
--------------------------------------------------------------------------------------------
-- an example of a request/grant + handshake process with next router or NI
--CLK _|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|_|'|__
-- Req _____|'''''''''''''''''''''''''''''''''''''''''''|________
-- _________ ___________________ _______ _______ _______ ____
-- TX _________X_______HEADER______X_Body__X_Body__X__Tail_X____
-- Grant _________________________|'''|___|'''|___|'''|____________
-- RTs _________|'''''''''''''''''''|___|'''''''|___|'''''''|____
-- DCTS _________________________|'''|_______|'''|_______|'''|____
-- |<---------clear----------->|
-- | to send |
--------------------------------------------------------------------------------------------
-- TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local);
SUBTYPE STATE_TYPE IS STD_LOGIC_VECTOR (5 downto 0);
CONSTANT IDLE: STATE_TYPE := "000001";
CONSTANT Local: STATE_TYPE := "000010";
CONSTANT North: STATE_TYPE := "000100";
CONSTANT East: STATE_TYPE := "001000";
CONSTANT West: STATE_TYPE := "010000";
CONSTANT South: STATE_TYPE := "100000";
SIGNAL state, state_in, next_state : STATE_TYPE := IDLE;
SIGNAL RTS_FF, RTS_FF_in: std_logic;
signal Grant_N_sig, Grant_E_sig, Grant_W_sig, Grant_S_sig, Grant_L_sig: std_logic;
signal Xbar_sel_sig: std_logic_vector(4 downto 0);
component Arbiter_checkers is
port (
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic;
DCTS: in std_logic;
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L: in std_logic;
Xbar_sel : in std_logic_vector(4 downto 0);
state: in std_logic_vector (5 downto 0);
state_in: in std_logic_vector (5 downto 0);
next_state_out: in std_logic_vector (5 downto 0);
RTS_FF: in std_logic;
RTS_FF_in: in std_logic;
-- Checker outputs
err_state_IDLE_xbar,
err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE,
err_IDLE_Req_L,
err_Local_Req_L,
err_North_Req_N,
--err_East_Req_E,
--err_West_Req_W,
--err_South_Req_S,
err_IDLE_Req_N,
err_Local_Req_N,
--err_North_Req_E,
--err_East_Req_W,
--err_West_Req_S,
err_South_Req_L,
--err_IDLE_Req_E,
--err_Local_Req_E,
--err_North_Req_W,
--err_East_Req_S,
err_West_Req_L,
err_South_Req_N,
--err_IDLE_Req_W,
--err_Local_Req_W,
--err_North_Req_S,
err_East_Req_L,
err_West_Req_N,
--err_South_Req_E,
--err_IDLE_Req_S,
--err_Local_Req_S,
--err_North_Req_L,
err_East_Req_N,
--err_West_Req_E,
--err_South_Req_W,
err_next_state_onehot,
err_state_in_onehot,
--err_DCTS_RTS_FF_state_Grant_L,
--err_DCTS_RTS_FF_state_Grant_N,
--err_DCTS_RTS_FF_state_Grant_E,
--err_DCTS_RTS_FF_state_Grant_W,
--err_DCTS_RTS_FF_state_Grant_S,
err_state_north_xbar_sel,
err_state_east_xbar_sel,
err_state_west_xbar_sel,
err_state_south_xbar_sel : out std_logic
--err_state_local_xbar_sel : out std_logic
);
end component;
begin
-- Arbiter checkers instantiation
ARBITERCHECKERS: Arbiter_checkers port map (
Req_N => Req_N,
Req_E => Req_E,
Req_W => Req_W,
Req_S => Req_S,
Req_L => Req_L,
DCTS => DCTS,
Grant_N => Grant_N_sig,
Grant_E => Grant_E_sig,
Grant_W => Grant_W_sig,
Grant_S => Grant_S_sig,
Grant_L => Grant_L_sig,
Xbar_sel=>Xbar_sel_sig,
state => state,
state_in => state_in,
next_state_out => next_state,
RTS_FF => RTS_FF,
RTS_FF_in => RTS_FF_in,
err_state_IDLE_xbar => err_state_IDLE_xbar,
err_state_not_IDLE_xbar => err_state_not_IDLE_xbar,
err_state_IDLE_RTS_FF_in => err_state_IDLE_RTS_FF_in,
err_state_not_IDLE_RTS_FF_RTS_FF_in => err_state_not_IDLE_RTS_FF_RTS_FF_in,
err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_DCTS_RTS_FF_RTS_FF_in,
err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in => err_state_not_IDLE_not_DCTS_RTS_FF_RTS_FF_in,
err_RTS_FF_not_DCTS_state_state_in => err_RTS_FF_not_DCTS_state_state_in,
err_not_RTS_FF_state_in_next_state => err_not_RTS_FF_state_in_next_state,
err_RTS_FF_DCTS_state_in_next_state => err_RTS_FF_DCTS_state_in_next_state,
err_not_DCTS_Grants => err_not_DCTS_Grants,
err_DCTS_not_RTS_FF_Grants => err_DCTS_not_RTS_FF_Grants,
err_DCTS_RTS_FF_IDLE_Grants => err_DCTS_RTS_FF_IDLE_Grants,
err_DCTS_RTS_FF_not_IDLE_Grants_onehot => err_DCTS_RTS_FF_not_IDLE_Grants_onehot,
err_Requests_next_state_IDLE => err_Requests_next_state_IDLE,
err_IDLE_Req_L => err_IDLE_Req_L,
err_Local_Req_L => err_Local_Req_L,
err_North_Req_N => err_North_Req_N,
err_IDLE_Req_N => err_IDLE_Req_N,
err_Local_Req_N => err_Local_Req_N,
err_South_Req_L => err_South_Req_L,
err_West_Req_L => err_West_Req_L,
err_South_Req_N => err_South_Req_N,
err_East_Req_L => err_East_Req_L,
err_West_Req_N => err_West_Req_N,
err_East_Req_N => err_East_Req_N,
err_next_state_onehot => err_next_state_onehot,
err_state_in_onehot => err_state_in_onehot,
err_state_north_xbar_sel => err_state_north_xbar_sel,
err_state_east_xbar_sel => err_state_east_xbar_sel,
err_state_west_xbar_sel => err_state_west_xbar_sel,
err_state_south_xbar_sel => err_state_south_xbar_sel
);
-- process for updating the state of arbiter's FSM, also setting RTS based on the state (if Grant is given or not)
process(clk, reset)begin
if reset = '0' then
state<=IDLE;
RTS_FF <= '0';
elsif clk'event and clk = '1' then
-- no grant given yet, it might be that there is no request to
-- arbiter or request is there, but the next router's/NI's FIFO is full
state <= state_in;
RTS_FF <= RTS_FF_in;
end if;
end process;
-- anything below here is pure combinational
RTS <= RTS_FF;
-- Becuase of checkers we did this!
Grant_N <= Grant_N_sig;
Grant_E <= Grant_E_sig;
Grant_W <= Grant_W_sig;
Grant_S <= Grant_S_sig;
Grant_L <= Grant_L_sig;
Xbar_sel <= Xbar_sel_sig;
process(RTS_FF, DCTS, state, next_state)begin
if RTS_FF = '1' and DCTS = '0' then
state_in <= state;
else
state_in <= next_state;
end if;
end process;
process(state, RTS_FF, DCTS)begin
if state = IDLE then
RTS_FF_in <= '0';
-- if there was a grant given to one of the inputs,
-- tell the next router/NI that the output data is valid
else
if RTS_FF = '1' and DCTS = '1' then
RTS_FF_in <= '0';
else
RTS_FF_in <= '1';
end if;
end if ;
end process;
-- sets the grants using round robin
-- the order is L --> N --> E --> W --> S and then back to L
process(state, Req_N, Req_E, Req_W, Req_S, Req_L, DCTS, RTS_FF)begin
Grant_N_sig <= '0';
Grant_E_sig <= '0';
Grant_W_sig <= '0';
Grant_S_sig <= '0';
Grant_L_sig <= '0';
Xbar_sel_sig <= "00000";
case(state) is
when IDLE =>
Xbar_sel_sig <= "00000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
when North =>
Grant_N_sig <= DCTS and RTS_FF ;
Xbar_sel_sig <= "00001";
If Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
else
next_state <= IDLE;
end if;
when East =>
Grant_E_sig <= DCTS and RTS_FF;
Xbar_sel_sig <= "00010";
If Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
else
next_state <= IDLE;
end if;
when West =>
Grant_W_sig <= DCTS and RTS_FF;
Xbar_sel_sig <= "00100";
If Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
else
next_state <= IDLE;
end if;
when South =>
Grant_S_sig <= DCTS and RTS_FF;
Xbar_sel_sig <= "01000";
If Req_S = '1' then
next_state <= South;
elsif Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
else
next_state <= IDLE;
end if;
when others => -- Local
Grant_L_sig <= DCTS and RTS_FF;
Xbar_sel_sig <= "10000";
If Req_L = '1' then
next_state <= Local;
elsif Req_N = '1' then
next_state <= North;
elsif Req_E = '1' then
next_state <= East;
elsif Req_W = '1' then
next_state <= West;
elsif Req_S = '1' then
next_state <= South;
else
next_state <= IDLE;
end if;
end case ;
end process;
end;
|
package b is
generic ( X: natural := 4);
type m is array (natural range <>) of bit_vector (X - 1 downto 0);
end package;
|
package b is
generic ( X: natural := 4);
type m is array (natural range <>) of bit_vector (X - 1 downto 0);
end package;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MAGIC_tb is
end;
architecture testing of MAGIC_tb is
component MAGIC
PORT (
ADDRESS_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN : IN STD_LOGIC;
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
DATA_OUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_B : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_C : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_0 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
C0_STALL : OUT STD_LOGIC;
C1_STALL : OUT STD_LOGIC;
CORE_IDENT : OUT STD_LOGIC
);
end component;
signal ADDRESS_A : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal ADDRESS_B : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal ADDRESS_C : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal ADDRESS_0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal ADDRESS_1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal ADDRESS_W : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal DATA_TO_W : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_EN : STD_LOGIC := '0';
signal CLK : STD_LOGIC := '1';
signal RESET_n : STD_LOGIC := '0';
signal DATA_OUT_A : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal DATA_OUT_B : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal DATA_OUT_C : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal DATA_OUT_0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal DATA_OUT_1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal C0_STALL : STD_LOGIC;
signal C1_STALL : STD_LOGIC;
signal CORE_IDENT : STD_LOGIC;
constant clk_period : time := 10ns;
begin
uut : MAGIC PORT MAP (
ADDRESS_A,
ADDRESS_B,
ADDRESS_C,
ADDRESS_0,
ADDRESS_1,
ADDRESS_W,
DATA_TO_W,
W_EN,
CLK,
RESET_n,
DATA_OUT_A,
DATA_OUT_B,
DATA_OUT_C,
DATA_OUT_0,
DATA_OUT_1,
C0_STALL,
C1_STALL,
CORE_IDENT
);
clk_process : process begin
CLK <= '1';
wait for clk_period/2;
CLK <= '0';
wait for clk_period/2;
end process;
-- id_process : process begin
-- CORE_ID <= '0';
-- wait for clk_period;
-- CORE_ID <= '1';
-- wait for clk_period;
-- end process;
stim_process : process begin
ADDRESS_A <= "00000000000000000000000000000000";
ADDRESS_B <= "00000000000000000000000000000001";
ADDRESS_C <= "00000000000000000000000000000010";
ADDRESS_0 <= "00000000000000000000000000000011";
ADDRESS_1 <= "00000000000000000000000000000100";
ADDRESS_W <= "00000000000000000000000000000000";
DATA_TO_W <= "00000000000000000000000000000000";
wait for clk_period;
RESET_n <= '1';
W_EN <= '1';
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000000001";
DATA_TO_W <= "00000000000000000000000000000001";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000000010";
DATA_TO_W <= "00000000000000000000000000000010";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000000011";
DATA_TO_W <= "00000000000000000000000000000011";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000000100";
DATA_TO_W <= "00000000000000000000000000000100";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000000101";
DATA_TO_W <= "00000000000000000000000000000101";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000000110";
DATA_TO_W <= "00000000000000000000000000000110";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000000111";
DATA_TO_W <= "00000000000000000000000000000111";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000001000";
DATA_TO_W <= "00000000000000000000000000001000";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000001001";
DATA_TO_W <= "00000000000000000000000000001001";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000001010";
DATA_TO_W <= "00000000000000000000000000001010";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000001011";
DATA_TO_W <= "00000000000000000000000000001011";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000001100";
DATA_TO_W <= "00000000000000000000000000001100";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000001101";
DATA_TO_W <= "00000000000000000000000000001101";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000001110";
DATA_TO_W <= "00000000000000000000000000001110";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000011000";
DATA_TO_W <= "00000000000000000000000000011000";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000010000";
DATA_TO_W <= "00000000000000000000000000010000";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000100000";
DATA_TO_W <= "00000000000000000000000000100000";
wait for clk_period;
--------------------------
ADDRESS_A <= "00000000000000000000000000000110";
ADDRESS_B <= "00000000000000000000000000001100";
ADDRESS_C <= "00000000000000000000000000000111";
ADDRESS_0 <= "00000000000000000000000000001000";
ADDRESS_1 <= "00000000000000000000000000001001";
W_EN <= '0';
wait for clk_period;
ADDRESS_A <= "00000000000000000000000000001000";
ADDRESS_B <= "00000000000000000000000000000000";
ADDRESS_C <= "00000000000000000000000000010000";
ADDRESS_0 <= "00000000000000000000000000011000";
ADDRESS_1 <= "00000000000000000000000000100000";
wait for clk_period*3;
ADDRESS_A <= "00000000000000000000000000000000";
ADDRESS_B <= "00000000000000000000000000000001";
ADDRESS_C <= "00000000000000000000000000000010";
ADDRESS_0 <= "00000000000000000000000000000011";
ADDRESS_1 <= "00000000000000000000000000000100";
wait for clk_period*2;
ADDRESS_A <= "00000000000000000000000000000000";
ADDRESS_B <= "00000000000000000000000000000000";
ADDRESS_C <= "00000000000000000000000000000000";
ADDRESS_0 <= "00000000000000000000000000000001";
ADDRESS_1 <= "00000000000000000000000000000010";
wait for clk_period*2;
ADDRESS_A <= "00000000000000000000000000000000";
ADDRESS_B <= "00000000000000000000000000000001";
ADDRESS_C <= "00000000000000000000000000000010";
ADDRESS_0 <= "00000000000000000000000000000011";
ADDRESS_1 <= "00000000000000000000000000000100";
wait;
end process;
end; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MAGIC_tb is
end;
architecture testing of MAGIC_tb is
component MAGIC
PORT (
ADDRESS_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_0 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_TO_W : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
W_EN : IN STD_LOGIC;
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
DATA_OUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_B : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_C : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_0 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
DATA_OUT_1 : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
C0_STALL : OUT STD_LOGIC;
C1_STALL : OUT STD_LOGIC;
CORE_IDENT : OUT STD_LOGIC
);
end component;
signal ADDRESS_A : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal ADDRESS_B : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal ADDRESS_C : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal ADDRESS_0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal ADDRESS_1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal ADDRESS_W : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal DATA_TO_W : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal W_EN : STD_LOGIC := '0';
signal CLK : STD_LOGIC := '1';
signal RESET_n : STD_LOGIC := '0';
signal DATA_OUT_A : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal DATA_OUT_B : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal DATA_OUT_C : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal DATA_OUT_0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal DATA_OUT_1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal C0_STALL : STD_LOGIC;
signal C1_STALL : STD_LOGIC;
signal CORE_IDENT : STD_LOGIC;
constant clk_period : time := 10ns;
begin
uut : MAGIC PORT MAP (
ADDRESS_A,
ADDRESS_B,
ADDRESS_C,
ADDRESS_0,
ADDRESS_1,
ADDRESS_W,
DATA_TO_W,
W_EN,
CLK,
RESET_n,
DATA_OUT_A,
DATA_OUT_B,
DATA_OUT_C,
DATA_OUT_0,
DATA_OUT_1,
C0_STALL,
C1_STALL,
CORE_IDENT
);
clk_process : process begin
CLK <= '1';
wait for clk_period/2;
CLK <= '0';
wait for clk_period/2;
end process;
-- id_process : process begin
-- CORE_ID <= '0';
-- wait for clk_period;
-- CORE_ID <= '1';
-- wait for clk_period;
-- end process;
stim_process : process begin
ADDRESS_A <= "00000000000000000000000000000000";
ADDRESS_B <= "00000000000000000000000000000001";
ADDRESS_C <= "00000000000000000000000000000010";
ADDRESS_0 <= "00000000000000000000000000000011";
ADDRESS_1 <= "00000000000000000000000000000100";
ADDRESS_W <= "00000000000000000000000000000000";
DATA_TO_W <= "00000000000000000000000000000000";
wait for clk_period;
RESET_n <= '1';
W_EN <= '1';
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000000001";
DATA_TO_W <= "00000000000000000000000000000001";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000000010";
DATA_TO_W <= "00000000000000000000000000000010";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000000011";
DATA_TO_W <= "00000000000000000000000000000011";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000000100";
DATA_TO_W <= "00000000000000000000000000000100";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000000101";
DATA_TO_W <= "00000000000000000000000000000101";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000000110";
DATA_TO_W <= "00000000000000000000000000000110";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000000111";
DATA_TO_W <= "00000000000000000000000000000111";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000001000";
DATA_TO_W <= "00000000000000000000000000001000";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000001001";
DATA_TO_W <= "00000000000000000000000000001001";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000001010";
DATA_TO_W <= "00000000000000000000000000001010";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000001011";
DATA_TO_W <= "00000000000000000000000000001011";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000001100";
DATA_TO_W <= "00000000000000000000000000001100";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000001101";
DATA_TO_W <= "00000000000000000000000000001101";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000001110";
DATA_TO_W <= "00000000000000000000000000001110";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000011000";
DATA_TO_W <= "00000000000000000000000000011000";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000010000";
DATA_TO_W <= "00000000000000000000000000010000";
wait for clk_period;
ADDRESS_W <= "00000000000000000000000000100000";
DATA_TO_W <= "00000000000000000000000000100000";
wait for clk_period;
--------------------------
ADDRESS_A <= "00000000000000000000000000000110";
ADDRESS_B <= "00000000000000000000000000001100";
ADDRESS_C <= "00000000000000000000000000000111";
ADDRESS_0 <= "00000000000000000000000000001000";
ADDRESS_1 <= "00000000000000000000000000001001";
W_EN <= '0';
wait for clk_period;
ADDRESS_A <= "00000000000000000000000000001000";
ADDRESS_B <= "00000000000000000000000000000000";
ADDRESS_C <= "00000000000000000000000000010000";
ADDRESS_0 <= "00000000000000000000000000011000";
ADDRESS_1 <= "00000000000000000000000000100000";
wait for clk_period*3;
ADDRESS_A <= "00000000000000000000000000000000";
ADDRESS_B <= "00000000000000000000000000000001";
ADDRESS_C <= "00000000000000000000000000000010";
ADDRESS_0 <= "00000000000000000000000000000011";
ADDRESS_1 <= "00000000000000000000000000000100";
wait for clk_period*2;
ADDRESS_A <= "00000000000000000000000000000000";
ADDRESS_B <= "00000000000000000000000000000000";
ADDRESS_C <= "00000000000000000000000000000000";
ADDRESS_0 <= "00000000000000000000000000000001";
ADDRESS_1 <= "00000000000000000000000000000010";
wait for clk_period*2;
ADDRESS_A <= "00000000000000000000000000000000";
ADDRESS_B <= "00000000000000000000000000000001";
ADDRESS_C <= "00000000000000000000000000000010";
ADDRESS_0 <= "00000000000000000000000000000011";
ADDRESS_1 <= "00000000000000000000000000000100";
wait;
end process;
end; |
-------------------------------------------------------------------------------------------------------------
-- Sign Extender
-- This block performs the sign extension in for the jump address(instruction 25-0)
-------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
-------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------
entity sign_extender is
port (
-- INPUTS
immediate_jump : in std_logic_vector(25 downto 0); -- instructon (25-0)
-- OUTPUTS
extended_jump : out std_logic_vector(31 downto 0) -- sign-extended jump immediate
);
end sign_extender;
-------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------
architecture behavioral of sign_extender is
begin
extended_jump(25 downto 0) <= immediate_jump;
extended_jump(31 downto 26) <= (others => '1') when (immediate_jump(25) = '1') else (others => '0');
end behavioral;
|
-------------------------------------------------------------------------------------------------------------
-- Sign Extender
-- This block performs the sign extension in for the jump address(instruction 25-0)
-------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
-------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------
entity sign_extender is
port (
-- INPUTS
immediate_jump : in std_logic_vector(25 downto 0); -- instructon (25-0)
-- OUTPUTS
extended_jump : out std_logic_vector(31 downto 0) -- sign-extended jump immediate
);
end sign_extender;
-------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------
architecture behavioral of sign_extender is
begin
extended_jump(25 downto 0) <= immediate_jump;
extended_jump(31 downto 26) <= (others => '1') when (immediate_jump(25) = '1') else (others => '0');
end behavioral;
|
-------------------------------------------------------------------------------
-- Bitmap VGA display with 640x480 pixel resolution
-------------------------------------------------------------------------------
-- V 1.1.1 (2015/07/28)
-- Yannick Bornat (yannick.bornat@enseirb-matmeca.fr)
--
-- For more information on this module, refer to module page :
-- http://bornat.vvv.enseirb.fr/wiki/doku.php?id=en202:vga_bitmap
--
-- V1.1.1 :
-- - Comment additions
-- - Code cleanup
-- V1.1.0 :
-- - added capacity above 3bpp
-- - ability to display grayscale pictures
-- - Module works @ 100MHz clock frequency
-- V1.0.1 :
-- - Fixed : image not centered on screen
-- V1.0.0 :
-- - Initial release
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.CONSTANTS.all;
entity VGA_bitmap_640x480 is
generic(grayscale : boolean := false); -- should data be displayed in grayscale
port(clk : in std_logic;
reset : in std_logic;
VGA_hs : out std_logic; -- horisontal vga syncr.
VGA_vs : out std_logic; -- vertical vga syncr.
VGA_red : out std_logic_vector(3 downto 0); -- red output
VGA_green : out std_logic_vector(3 downto 0); -- green output
VGA_blue : out std_logic_vector(3 downto 0); -- blue output
endcalcul : in std_logic;
data_in : in std_logic_vector(bit_per_pixel - 1 downto 0);
data_write : in std_logic;
data_out : out std_logic_vector(bit_per_pixel - 1 downto 0));
end VGA_bitmap_640x480;
architecture Behavioral of VGA_bitmap_640x480 is
-- Graphic RAM type. this object is the content of the displayed image
type GRAM is array (0 to 307199) of std_logic_vector(bit_per_pixel - 1 downto 0);
signal screen : GRAM; -- the memory representation of the image
signal ADDR : unsigned(18 downto 0);
signal h_counter : integer range 0 to 3199:=0; -- counter for H sync. (size depends of frequ because of division)
signal v_counter : integer range 0 to 520 :=0; -- counter for V sync. (base on v_counter, so no frequ issue)
signal TOP_line : boolean := false; -- this signal is true when the current pixel column is visible on the screen
signal TOP_display : boolean := false; -- this signal is true when the current pixel line is visible on the screen
signal pix_read_addr : integer range 0 to 307199:=0; -- the address at which displayed data is read
signal next_pixel : std_logic_vector(bit_per_pixel - 1 downto 0); -- the data coding the value of the pixel to be displayed
begin
ADDRmanagement : process(clk,reset, data_write, endcalcul)
begin
if reset='1' then
ADDR<=(others=>'0'); --to_unsigned(15999, 14);
elsif rising_edge(clk) then
if endcalcul='1' then
ADDR<=(others=>'0');
else
if data_write = '1' then
if ADDR < 307199 then
ADDR<=ADDR+1;
else
ADDR<=(others=>'0');
end if;
end if;
end if;
end if;
end process;
-- This process performs data access (read and write) to the memory
memory_management : process(clk)
begin
if clk'event and clk='1' then
next_pixel <= screen(pix_read_addr);
data_out <= screen(to_integer(ADDR));
if data_write = '1' then
screen(to_integer(ADDR)) <= data_in;
end if;
end if;
end process;
pixel_read_addr : process(clk)
begin
if clk'event and clk='1' then
if reset = '1' or (not TOP_display) then
pix_read_addr <= 0;
elsif TOP_line and (h_counter mod 4)=0 then
pix_read_addr <= pix_read_addr + 1;
end if;
end if;
end process;
-- this process manages the horizontal synchro using the counters
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
VGA_vs <= '0';
TOP_display <= false;
else
case v_counter is
when 0 => VGA_vs <= '0'; -- start of Tpw ( 0 -> 0 + 1)
when 2 => VGA_vs <= '1'; -- start of Tbp ( 2 -> 2 + 28 = 30)
when 31 => TOP_display <= true; -- start of Tdisp ( 31 -> 31 + 479 = 510)
when 511 => TOP_display <= false; -- start of Tfp (511 -> 511 + 9 = 520)
when others => null;
end case;
-- if v_counter = 0 then VGA_vs <= '0'; -- start of Tpw ( 0 -> 0 + 1)
-- elsif v_counter = 2 then VGA_vs <= '1'; -- start of Tbp ( 2 -> 2 + 28 = 30)
-- elsif v_counter = 75 then TOP_display <= true; -- start of Tdisp ( 31 -> 31 + 479 = 510)
-- elsif v_counter = 475 then TOP_display <= false; -- start of Tfp (511 -> 511 + 9 = 520)
-- end if;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk='1' then
if (not TOP_line) or (not TOP_display) then
VGA_red <= "0000";
VGA_green <= "0000";
VGA_blue <= "0000";
else
case bit_per_pixel is
when 1 =>
VGA_red <= (others => next_pixel(0));
VGA_green <= (others => next_pixel(0));
VGA_blue <= (others => next_pixel(0));
when 2 =>
if grayscale then
VGA_blue <= next_pixel & next_pixel;
VGA_green <= next_pixel & next_pixel;
VGA_red <= next_pixel & next_pixel;
else
VGA_red <= (others => (next_pixel(0) and next_pixel(1)));
VGA_green <= (others => (next_pixel(1) and not next_pixel(0)));
VGA_blue <= (others => (next_pixel(0) and not next_pixel(1)));
end if;
when 3 =>
if grayscale then
VGA_blue <= next_pixel & next_pixel(bit_per_pixel - 1);
VGA_green <= next_pixel & next_pixel(bit_per_pixel - 1);
VGA_red <= next_pixel & next_pixel(bit_per_pixel - 1);
else
VGA_red <= (others => next_pixel(2));
VGA_green <= (others => next_pixel(1));
VGA_blue <= (others => next_pixel(0));
end if;
when 4 =>
if grayscale then
VGA_blue <= next_pixel;
VGA_green <= next_pixel;
VGA_red <= next_pixel;
elsif next_pixel="1000" then
VGA_red <= "0100";
VGA_green <= "0100";
VGA_blue <= "0100";
else
VGA_red(2 downto 0) <= (others => (next_pixel(2) and next_pixel(3)));
VGA_green(2 downto 0) <= (others => (next_pixel(1) and next_pixel(3)));
VGA_blue(2 downto 0) <= (others => (next_pixel(0) and next_pixel(3)));
VGA_red(3) <= next_pixel(2);
VGA_green(3) <= next_pixel(1);
VGA_blue(3) <= next_pixel(0);
end if;
when 5 =>
case to_integer(unsigned(next_pixel)) is
when 0 | 3 | 6 | 9 | 12 | 15 | 18 | 21 | 24 => VGA_blue <= "0000";
when 1 | 4 | 7 | 10 | 13 | 16 | 19 | 22 | 25 => VGA_blue <= "1000";
when others => VGA_blue <= "1111";
end case;
case to_integer(unsigned(next_pixel)) is
when 0 | 1 | 2 | 9 | 10 | 11 | 18 | 19 | 20 => VGA_green <= "0000";
when 3 | 4 | 5 | 12 | 13 | 14 | 21 | 22 | 23 => VGA_green <= "1000";
when others => VGA_green <= "1111";
end case;
case to_integer(unsigned(next_pixel)) is
when 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 => VGA_red <= "0000";
when 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 => VGA_red <= "1000";
when others => VGA_red <= "1111";
end case;
when 6 =>
VGA_red <= next_pixel(5 downto 4) & next_pixel(5 downto 4);
VGA_green <= next_pixel(3 downto 2) & next_pixel(3 downto 2);
VGA_blue <= next_pixel(1 downto 0) & next_pixel(1 downto 0);
when 7 =>
VGA_red <= next_pixel(6 downto 5) & next_pixel(6 downto 5);
VGA_green <= next_pixel(4 downto 2) & next_pixel(4);
VGA_blue <= next_pixel(1 downto 0) & next_pixel(1 downto 0);
when 8 =>
VGA_red <= next_pixel(7 downto 5) & next_pixel(7);
VGA_green <= next_pixel(4 downto 2) & next_pixel(4);
VGA_blue <= next_pixel(1 downto 0) & next_pixel(1 downto 0);
when 9 =>
VGA_red <= next_pixel(8 downto 6) & next_pixel(8);
VGA_green <= next_pixel(5 downto 3) & next_pixel(5);
VGA_blue <= next_pixel(2 downto 0) & next_pixel(2);
when 10 =>
VGA_red <= next_pixel(9 downto 7) & next_pixel(9);
VGA_green <= next_pixel(6 downto 3);
VGA_blue <= next_pixel(2 downto 0) & next_pixel(2);
when 11 =>
VGA_red <= next_pixel(10 downto 7);
VGA_green <= next_pixel( 6 downto 3);
VGA_blue <= next_pixel( 2 downto 0) & next_pixel(2);
when 12 =>
VGA_red <= next_pixel(11 downto 8);
VGA_green <= next_pixel( 7 downto 4);
VGA_blue <= next_pixel( 3 downto 0);
when others => NULL;
end case;
end if;
end if;
end process;
-- this process manages the horizontal synchro using the counters
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
VGA_hs <= '0';
TOP_line <= false;
else
case h_counter is
when 2 => VGA_hs <= '0'; -- start of Tpw ( 0 -> 0 + 95) -- +2 because of delay in RAM
when 386 => VGA_hs <= '1'; -- start of Tbp ( 96 -> 96 + 47 = 143) -- 384=96*4 -- -- +2 because of delay in RAM
when 576 => TOP_line <= true; -- start of Tdisp ( 144 -> 144 + 639 = 783) -- 576=144*4
when 3136 => TOP_line <= false; -- start of Tfp ( 784 -> 784 + 15 = 799) -- 3136 = 784*4
when others => null;
end case;
-- if h_counter=2 then VGA_hs <= '0'; -- start of Tpw ( 0 -> 0 + 95) -- +2 because of delay in RAM
-- elsif h_counter=386 then VGA_hs <= '1'; -- start of Tbp ( 96 -> 96 + 47 = 143) -- 384=96*4 -- -- +2 because of delay in RAM
-- elsif h_counter=576 then TOP_line <= true; -- start of Tdisp ( 144 -> 144 + 639 = 783) -- 576=144*4
-- elsif h_counter=3136 then TOP_line <= false; -- start of Tfp ( 784 -> 784 + 15 = 799) -- 3136 = 784*4
-- end if;
end if;
end if;
end process;
-- counter management for synchro
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
h_counter <= 0;
v_counter <= 0;
else
if h_counter = 3199 then
h_counter <= 0;
if v_counter = 520 then
v_counter <= 0;
else
v_counter <= v_counter + 1;
end if;
else
h_counter <= h_counter +1;
end if;
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- Bitmap VGA display with 640x480 pixel resolution
-------------------------------------------------------------------------------
-- V 1.1.1 (2015/07/28)
-- Yannick Bornat (yannick.bornat@enseirb-matmeca.fr)
--
-- For more information on this module, refer to module page :
-- http://bornat.vvv.enseirb.fr/wiki/doku.php?id=en202:vga_bitmap
--
-- V1.1.1 :
-- - Comment additions
-- - Code cleanup
-- V1.1.0 :
-- - added capacity above 3bpp
-- - ability to display grayscale pictures
-- - Module works @ 100MHz clock frequency
-- V1.0.1 :
-- - Fixed : image not centered on screen
-- V1.0.0 :
-- - Initial release
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.CONSTANTS.all;
entity VGA_bitmap_640x480 is
generic(grayscale : boolean := false); -- should data be displayed in grayscale
port(clk : in std_logic;
reset : in std_logic;
VGA_hs : out std_logic; -- horisontal vga syncr.
VGA_vs : out std_logic; -- vertical vga syncr.
VGA_red : out std_logic_vector(3 downto 0); -- red output
VGA_green : out std_logic_vector(3 downto 0); -- green output
VGA_blue : out std_logic_vector(3 downto 0); -- blue output
endcalcul : in std_logic;
data_in : in std_logic_vector(bit_per_pixel - 1 downto 0);
data_write : in std_logic;
data_out : out std_logic_vector(bit_per_pixel - 1 downto 0));
end VGA_bitmap_640x480;
architecture Behavioral of VGA_bitmap_640x480 is
-- Graphic RAM type. this object is the content of the displayed image
type GRAM is array (0 to 307199) of std_logic_vector(bit_per_pixel - 1 downto 0);
signal screen : GRAM; -- the memory representation of the image
signal ADDR : unsigned(18 downto 0);
signal h_counter : integer range 0 to 3199:=0; -- counter for H sync. (size depends of frequ because of division)
signal v_counter : integer range 0 to 520 :=0; -- counter for V sync. (base on v_counter, so no frequ issue)
signal TOP_line : boolean := false; -- this signal is true when the current pixel column is visible on the screen
signal TOP_display : boolean := false; -- this signal is true when the current pixel line is visible on the screen
signal pix_read_addr : integer range 0 to 307199:=0; -- the address at which displayed data is read
signal next_pixel : std_logic_vector(bit_per_pixel - 1 downto 0); -- the data coding the value of the pixel to be displayed
begin
ADDRmanagement : process(clk,reset, data_write, endcalcul)
begin
if reset='1' then
ADDR<=(others=>'0'); --to_unsigned(15999, 14);
elsif rising_edge(clk) then
if endcalcul='1' then
ADDR<=(others=>'0');
else
if data_write = '1' then
if ADDR < 307199 then
ADDR<=ADDR+1;
else
ADDR<=(others=>'0');
end if;
end if;
end if;
end if;
end process;
-- This process performs data access (read and write) to the memory
memory_management : process(clk)
begin
if clk'event and clk='1' then
next_pixel <= screen(pix_read_addr);
data_out <= screen(to_integer(ADDR));
if data_write = '1' then
screen(to_integer(ADDR)) <= data_in;
end if;
end if;
end process;
pixel_read_addr : process(clk)
begin
if clk'event and clk='1' then
if reset = '1' or (not TOP_display) then
pix_read_addr <= 0;
elsif TOP_line and (h_counter mod 4)=0 then
pix_read_addr <= pix_read_addr + 1;
end if;
end if;
end process;
-- this process manages the horizontal synchro using the counters
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
VGA_vs <= '0';
TOP_display <= false;
else
case v_counter is
when 0 => VGA_vs <= '0'; -- start of Tpw ( 0 -> 0 + 1)
when 2 => VGA_vs <= '1'; -- start of Tbp ( 2 -> 2 + 28 = 30)
when 31 => TOP_display <= true; -- start of Tdisp ( 31 -> 31 + 479 = 510)
when 511 => TOP_display <= false; -- start of Tfp (511 -> 511 + 9 = 520)
when others => null;
end case;
-- if v_counter = 0 then VGA_vs <= '0'; -- start of Tpw ( 0 -> 0 + 1)
-- elsif v_counter = 2 then VGA_vs <= '1'; -- start of Tbp ( 2 -> 2 + 28 = 30)
-- elsif v_counter = 75 then TOP_display <= true; -- start of Tdisp ( 31 -> 31 + 479 = 510)
-- elsif v_counter = 475 then TOP_display <= false; -- start of Tfp (511 -> 511 + 9 = 520)
-- end if;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk='1' then
if (not TOP_line) or (not TOP_display) then
VGA_red <= "0000";
VGA_green <= "0000";
VGA_blue <= "0000";
else
case bit_per_pixel is
when 1 =>
VGA_red <= (others => next_pixel(0));
VGA_green <= (others => next_pixel(0));
VGA_blue <= (others => next_pixel(0));
when 2 =>
if grayscale then
VGA_blue <= next_pixel & next_pixel;
VGA_green <= next_pixel & next_pixel;
VGA_red <= next_pixel & next_pixel;
else
VGA_red <= (others => (next_pixel(0) and next_pixel(1)));
VGA_green <= (others => (next_pixel(1) and not next_pixel(0)));
VGA_blue <= (others => (next_pixel(0) and not next_pixel(1)));
end if;
when 3 =>
if grayscale then
VGA_blue <= next_pixel & next_pixel(bit_per_pixel - 1);
VGA_green <= next_pixel & next_pixel(bit_per_pixel - 1);
VGA_red <= next_pixel & next_pixel(bit_per_pixel - 1);
else
VGA_red <= (others => next_pixel(2));
VGA_green <= (others => next_pixel(1));
VGA_blue <= (others => next_pixel(0));
end if;
when 4 =>
if grayscale then
VGA_blue <= next_pixel;
VGA_green <= next_pixel;
VGA_red <= next_pixel;
elsif next_pixel="1000" then
VGA_red <= "0100";
VGA_green <= "0100";
VGA_blue <= "0100";
else
VGA_red(2 downto 0) <= (others => (next_pixel(2) and next_pixel(3)));
VGA_green(2 downto 0) <= (others => (next_pixel(1) and next_pixel(3)));
VGA_blue(2 downto 0) <= (others => (next_pixel(0) and next_pixel(3)));
VGA_red(3) <= next_pixel(2);
VGA_green(3) <= next_pixel(1);
VGA_blue(3) <= next_pixel(0);
end if;
when 5 =>
case to_integer(unsigned(next_pixel)) is
when 0 | 3 | 6 | 9 | 12 | 15 | 18 | 21 | 24 => VGA_blue <= "0000";
when 1 | 4 | 7 | 10 | 13 | 16 | 19 | 22 | 25 => VGA_blue <= "1000";
when others => VGA_blue <= "1111";
end case;
case to_integer(unsigned(next_pixel)) is
when 0 | 1 | 2 | 9 | 10 | 11 | 18 | 19 | 20 => VGA_green <= "0000";
when 3 | 4 | 5 | 12 | 13 | 14 | 21 | 22 | 23 => VGA_green <= "1000";
when others => VGA_green <= "1111";
end case;
case to_integer(unsigned(next_pixel)) is
when 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 => VGA_red <= "0000";
when 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 => VGA_red <= "1000";
when others => VGA_red <= "1111";
end case;
when 6 =>
VGA_red <= next_pixel(5 downto 4) & next_pixel(5 downto 4);
VGA_green <= next_pixel(3 downto 2) & next_pixel(3 downto 2);
VGA_blue <= next_pixel(1 downto 0) & next_pixel(1 downto 0);
when 7 =>
VGA_red <= next_pixel(6 downto 5) & next_pixel(6 downto 5);
VGA_green <= next_pixel(4 downto 2) & next_pixel(4);
VGA_blue <= next_pixel(1 downto 0) & next_pixel(1 downto 0);
when 8 =>
VGA_red <= next_pixel(7 downto 5) & next_pixel(7);
VGA_green <= next_pixel(4 downto 2) & next_pixel(4);
VGA_blue <= next_pixel(1 downto 0) & next_pixel(1 downto 0);
when 9 =>
VGA_red <= next_pixel(8 downto 6) & next_pixel(8);
VGA_green <= next_pixel(5 downto 3) & next_pixel(5);
VGA_blue <= next_pixel(2 downto 0) & next_pixel(2);
when 10 =>
VGA_red <= next_pixel(9 downto 7) & next_pixel(9);
VGA_green <= next_pixel(6 downto 3);
VGA_blue <= next_pixel(2 downto 0) & next_pixel(2);
when 11 =>
VGA_red <= next_pixel(10 downto 7);
VGA_green <= next_pixel( 6 downto 3);
VGA_blue <= next_pixel( 2 downto 0) & next_pixel(2);
when 12 =>
VGA_red <= next_pixel(11 downto 8);
VGA_green <= next_pixel( 7 downto 4);
VGA_blue <= next_pixel( 3 downto 0);
when others => NULL;
end case;
end if;
end if;
end process;
-- this process manages the horizontal synchro using the counters
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
VGA_hs <= '0';
TOP_line <= false;
else
case h_counter is
when 2 => VGA_hs <= '0'; -- start of Tpw ( 0 -> 0 + 95) -- +2 because of delay in RAM
when 386 => VGA_hs <= '1'; -- start of Tbp ( 96 -> 96 + 47 = 143) -- 384=96*4 -- -- +2 because of delay in RAM
when 576 => TOP_line <= true; -- start of Tdisp ( 144 -> 144 + 639 = 783) -- 576=144*4
when 3136 => TOP_line <= false; -- start of Tfp ( 784 -> 784 + 15 = 799) -- 3136 = 784*4
when others => null;
end case;
-- if h_counter=2 then VGA_hs <= '0'; -- start of Tpw ( 0 -> 0 + 95) -- +2 because of delay in RAM
-- elsif h_counter=386 then VGA_hs <= '1'; -- start of Tbp ( 96 -> 96 + 47 = 143) -- 384=96*4 -- -- +2 because of delay in RAM
-- elsif h_counter=576 then TOP_line <= true; -- start of Tdisp ( 144 -> 144 + 639 = 783) -- 576=144*4
-- elsif h_counter=3136 then TOP_line <= false; -- start of Tfp ( 784 -> 784 + 15 = 799) -- 3136 = 784*4
-- end if;
end if;
end if;
end process;
-- counter management for synchro
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
h_counter <= 0;
v_counter <= 0;
else
if h_counter = 3199 then
h_counter <= 0;
if v_counter = 520 then
v_counter <= 0;
else
v_counter <= v_counter + 1;
end if;
else
h_counter <= h_counter +1;
end if;
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:18:02 03/28/2016
-- Design Name:
-- Module Name: ALU_Toplevel - Dataflow
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU_Toplevel is
Port ( RA : in STD_LOGIC_VECTOR (15 downto 0);
RB : in STD_LOGIC_VECTOR (15 downto 0);
OP : in STD_LOGIC_VECTOR (3 downto 0);
CLK : IN STD_LOGIC;
ALU_OUT : out STD_LOGIC_VECTOR (15 downto 0);
SREG : out STD_LOGIC_VECTOR (3 downto 0);
LDST_DAT : out STD_LOGIC_VECTOR (15 downto 0);
LDST_ADR : out STD_LOGIC_VECTOR (15 downto 0));
end ALU_Toplevel;
architecture Structural of ALU_Toplevel is
signal ARITH : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_AR : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal LOGIC : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_LG : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal SHIFT : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_SH : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal LD_MEM : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal WORD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal LDST_ADR_8 : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
begin
LDST_ADR <= X"00" & LDST_ADR_8;
arith_unit: entity work.arith_unit
port map( RA => RA,
RB => RB,
OP => OP(2 downto 0),
AR_OUT => ARITH,
SREG_OUT => SREG_AR);
logical_unit: entity work.logical_unit
port map( RA => RA,
RB => RB,
OP => OP(2 downto 0),
LOG_OUT => LOGIC,
SREG_OUT => SREG_LG);
shift_unit: entity work.shift_unit
port map( RA => RA,
SHIFT => RB(7 downto 0),
OP => OP(3),
SHIFT_OUT => SHIFT,
SREG_OUT => SREG_SH);
word_unit: entity work.word_unit
port map( DATAIN => RA,
IMMAddr => RB(7 downto 0),
CLK => CLK,
OP => OP,
RESULT => WORD_OUT,
DST_ADR => LDST_ADR_8,
STORE_DATA => LDST_DAT);
with OP select
ALU_OUT <=
ARITH when "0000", -- ADD (ARITHMETIC)
ARITH when "0001", -- SUB (ARITHMETIC)
LOGIC when "0010", -- AND (LOGICAL)
LOGIC when "0011", -- OR (LOGICAL)
LOGIC when "0100", -- MOV (LOGICAL)
ARITH when "0101", -- ADDI (ARITHMETIC)
LOGIC when "0110",--, -- ANDI (LOGICAL)
SHIFT when "0111", -- SL (SHIFT)
SHIFT when "1000",--, -- SR (SHIFT)
WORD_OUT when "1001", -- LW (WORD)
RA when "1010", -- SW (WORD)
X"0000" when OTHERS;
with OP select
SREG <=
SREG_AR when "0000", -- ADD (ARITHMETIC)
SREG_AR when "0001", -- SUB (ARITHMETIC)
SREG_LG when "0010", -- AND (LOGICAL)
SREG_LG when "0011", -- OR (LOGICAL)
SREG_LG when "0100", -- MOV (LOGICAL)
SREG_AR when "0101", -- ADDI (ARITHMETIC)
SREG_LG when "0110",--, -- ANDI (LOGICAL)
SREG_SH when "0111", -- SL (SHIFT)
SREG_SH when "1000",--, -- SR (SHIFT)
X"0" when OTHERS;
end Structural;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:18:02 03/28/2016
-- Design Name:
-- Module Name: ALU_Toplevel - Dataflow
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU_Toplevel is
Port ( RA : in STD_LOGIC_VECTOR (15 downto 0);
RB : in STD_LOGIC_VECTOR (15 downto 0);
OP : in STD_LOGIC_VECTOR (3 downto 0);
CLK : IN STD_LOGIC;
ALU_OUT : out STD_LOGIC_VECTOR (15 downto 0);
SREG : out STD_LOGIC_VECTOR (3 downto 0);
LDST_DAT : out STD_LOGIC_VECTOR (15 downto 0);
LDST_ADR : out STD_LOGIC_VECTOR (15 downto 0));
end ALU_Toplevel;
architecture Structural of ALU_Toplevel is
signal ARITH : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_AR : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal LOGIC : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_LG : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal SHIFT : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_SH : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal LD_MEM : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal WORD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal LDST_ADR_8 : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
begin
LDST_ADR <= X"00" & LDST_ADR_8;
arith_unit: entity work.arith_unit
port map( RA => RA,
RB => RB,
OP => OP(2 downto 0),
AR_OUT => ARITH,
SREG_OUT => SREG_AR);
logical_unit: entity work.logical_unit
port map( RA => RA,
RB => RB,
OP => OP(2 downto 0),
LOG_OUT => LOGIC,
SREG_OUT => SREG_LG);
shift_unit: entity work.shift_unit
port map( RA => RA,
SHIFT => RB(7 downto 0),
OP => OP(3),
SHIFT_OUT => SHIFT,
SREG_OUT => SREG_SH);
word_unit: entity work.word_unit
port map( DATAIN => RA,
IMMAddr => RB(7 downto 0),
CLK => CLK,
OP => OP,
RESULT => WORD_OUT,
DST_ADR => LDST_ADR_8,
STORE_DATA => LDST_DAT);
with OP select
ALU_OUT <=
ARITH when "0000", -- ADD (ARITHMETIC)
ARITH when "0001", -- SUB (ARITHMETIC)
LOGIC when "0010", -- AND (LOGICAL)
LOGIC when "0011", -- OR (LOGICAL)
LOGIC when "0100", -- MOV (LOGICAL)
ARITH when "0101", -- ADDI (ARITHMETIC)
LOGIC when "0110",--, -- ANDI (LOGICAL)
SHIFT when "0111", -- SL (SHIFT)
SHIFT when "1000",--, -- SR (SHIFT)
WORD_OUT when "1001", -- LW (WORD)
RA when "1010", -- SW (WORD)
X"0000" when OTHERS;
with OP select
SREG <=
SREG_AR when "0000", -- ADD (ARITHMETIC)
SREG_AR when "0001", -- SUB (ARITHMETIC)
SREG_LG when "0010", -- AND (LOGICAL)
SREG_LG when "0011", -- OR (LOGICAL)
SREG_LG when "0100", -- MOV (LOGICAL)
SREG_AR when "0101", -- ADDI (ARITHMETIC)
SREG_LG when "0110",--, -- ANDI (LOGICAL)
SREG_SH when "0111", -- SL (SHIFT)
SREG_SH when "1000",--, -- SR (SHIFT)
X"0" when OTHERS;
end Structural;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:18:02 03/28/2016
-- Design Name:
-- Module Name: ALU_Toplevel - Dataflow
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU_Toplevel is
Port ( RA : in STD_LOGIC_VECTOR (15 downto 0);
RB : in STD_LOGIC_VECTOR (15 downto 0);
OP : in STD_LOGIC_VECTOR (3 downto 0);
CLK : IN STD_LOGIC;
ALU_OUT : out STD_LOGIC_VECTOR (15 downto 0);
SREG : out STD_LOGIC_VECTOR (3 downto 0);
LDST_DAT : out STD_LOGIC_VECTOR (15 downto 0);
LDST_ADR : out STD_LOGIC_VECTOR (15 downto 0));
end ALU_Toplevel;
architecture Structural of ALU_Toplevel is
signal ARITH : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_AR : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal LOGIC : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_LG : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal SHIFT : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_SH : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal LD_MEM : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal WORD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal LDST_ADR_8 : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
begin
LDST_ADR <= X"00" & LDST_ADR_8;
arith_unit: entity work.arith_unit
port map( RA => RA,
RB => RB,
OP => OP(2 downto 0),
AR_OUT => ARITH,
SREG_OUT => SREG_AR);
logical_unit: entity work.logical_unit
port map( RA => RA,
RB => RB,
OP => OP(2 downto 0),
LOG_OUT => LOGIC,
SREG_OUT => SREG_LG);
shift_unit: entity work.shift_unit
port map( RA => RA,
SHIFT => RB(7 downto 0),
OP => OP(3),
SHIFT_OUT => SHIFT,
SREG_OUT => SREG_SH);
word_unit: entity work.word_unit
port map( DATAIN => RA,
IMMAddr => RB(7 downto 0),
CLK => CLK,
OP => OP,
RESULT => WORD_OUT,
DST_ADR => LDST_ADR_8,
STORE_DATA => LDST_DAT);
with OP select
ALU_OUT <=
ARITH when "0000", -- ADD (ARITHMETIC)
ARITH when "0001", -- SUB (ARITHMETIC)
LOGIC when "0010", -- AND (LOGICAL)
LOGIC when "0011", -- OR (LOGICAL)
LOGIC when "0100", -- MOV (LOGICAL)
ARITH when "0101", -- ADDI (ARITHMETIC)
LOGIC when "0110",--, -- ANDI (LOGICAL)
SHIFT when "0111", -- SL (SHIFT)
SHIFT when "1000",--, -- SR (SHIFT)
WORD_OUT when "1001", -- LW (WORD)
RA when "1010", -- SW (WORD)
X"0000" when OTHERS;
with OP select
SREG <=
SREG_AR when "0000", -- ADD (ARITHMETIC)
SREG_AR when "0001", -- SUB (ARITHMETIC)
SREG_LG when "0010", -- AND (LOGICAL)
SREG_LG when "0011", -- OR (LOGICAL)
SREG_LG when "0100", -- MOV (LOGICAL)
SREG_AR when "0101", -- ADDI (ARITHMETIC)
SREG_LG when "0110",--, -- ANDI (LOGICAL)
SREG_SH when "0111", -- SL (SHIFT)
SREG_SH when "1000",--, -- SR (SHIFT)
X"0" when OTHERS;
end Structural;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:18:02 03/28/2016
-- Design Name:
-- Module Name: ALU_Toplevel - Dataflow
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU_Toplevel is
Port ( RA : in STD_LOGIC_VECTOR (15 downto 0);
RB : in STD_LOGIC_VECTOR (15 downto 0);
OP : in STD_LOGIC_VECTOR (3 downto 0);
CLK : IN STD_LOGIC;
ALU_OUT : out STD_LOGIC_VECTOR (15 downto 0);
SREG : out STD_LOGIC_VECTOR (3 downto 0);
LDST_DAT : out STD_LOGIC_VECTOR (15 downto 0);
LDST_ADR : out STD_LOGIC_VECTOR (15 downto 0));
end ALU_Toplevel;
architecture Structural of ALU_Toplevel is
signal ARITH : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_AR : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal LOGIC : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_LG : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal SHIFT : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_SH : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal LD_MEM : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal WORD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal LDST_ADR_8 : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
begin
LDST_ADR <= X"00" & LDST_ADR_8;
arith_unit: entity work.arith_unit
port map( RA => RA,
RB => RB,
OP => OP(2 downto 0),
AR_OUT => ARITH,
SREG_OUT => SREG_AR);
logical_unit: entity work.logical_unit
port map( RA => RA,
RB => RB,
OP => OP(2 downto 0),
LOG_OUT => LOGIC,
SREG_OUT => SREG_LG);
shift_unit: entity work.shift_unit
port map( RA => RA,
SHIFT => RB(7 downto 0),
OP => OP(3),
SHIFT_OUT => SHIFT,
SREG_OUT => SREG_SH);
word_unit: entity work.word_unit
port map( DATAIN => RA,
IMMAddr => RB(7 downto 0),
CLK => CLK,
OP => OP,
RESULT => WORD_OUT,
DST_ADR => LDST_ADR_8,
STORE_DATA => LDST_DAT);
with OP select
ALU_OUT <=
ARITH when "0000", -- ADD (ARITHMETIC)
ARITH when "0001", -- SUB (ARITHMETIC)
LOGIC when "0010", -- AND (LOGICAL)
LOGIC when "0011", -- OR (LOGICAL)
LOGIC when "0100", -- MOV (LOGICAL)
ARITH when "0101", -- ADDI (ARITHMETIC)
LOGIC when "0110",--, -- ANDI (LOGICAL)
SHIFT when "0111", -- SL (SHIFT)
SHIFT when "1000",--, -- SR (SHIFT)
WORD_OUT when "1001", -- LW (WORD)
RA when "1010", -- SW (WORD)
X"0000" when OTHERS;
with OP select
SREG <=
SREG_AR when "0000", -- ADD (ARITHMETIC)
SREG_AR when "0001", -- SUB (ARITHMETIC)
SREG_LG when "0010", -- AND (LOGICAL)
SREG_LG when "0011", -- OR (LOGICAL)
SREG_LG when "0100", -- MOV (LOGICAL)
SREG_AR when "0101", -- ADDI (ARITHMETIC)
SREG_LG when "0110",--, -- ANDI (LOGICAL)
SREG_SH when "0111", -- SL (SHIFT)
SREG_SH when "1000",--, -- SR (SHIFT)
X"0" when OTHERS;
end Structural;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:18:02 03/28/2016
-- Design Name:
-- Module Name: ALU_Toplevel - Dataflow
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU_Toplevel is
Port ( RA : in STD_LOGIC_VECTOR (15 downto 0);
RB : in STD_LOGIC_VECTOR (15 downto 0);
OP : in STD_LOGIC_VECTOR (3 downto 0);
CLK : IN STD_LOGIC;
ALU_OUT : out STD_LOGIC_VECTOR (15 downto 0);
SREG : out STD_LOGIC_VECTOR (3 downto 0);
LDST_DAT : out STD_LOGIC_VECTOR (15 downto 0);
LDST_ADR : out STD_LOGIC_VECTOR (15 downto 0));
end ALU_Toplevel;
architecture Structural of ALU_Toplevel is
signal ARITH : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_AR : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal LOGIC : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_LG : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal SHIFT : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal SREG_SH : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal LD_MEM : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal WORD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal LDST_ADR_8 : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
begin
LDST_ADR <= X"00" & LDST_ADR_8;
arith_unit: entity work.arith_unit
port map( RA => RA,
RB => RB,
OP => OP(2 downto 0),
AR_OUT => ARITH,
SREG_OUT => SREG_AR);
logical_unit: entity work.logical_unit
port map( RA => RA,
RB => RB,
OP => OP(2 downto 0),
LOG_OUT => LOGIC,
SREG_OUT => SREG_LG);
shift_unit: entity work.shift_unit
port map( RA => RA,
SHIFT => RB(7 downto 0),
OP => OP(3),
SHIFT_OUT => SHIFT,
SREG_OUT => SREG_SH);
word_unit: entity work.word_unit
port map( DATAIN => RA,
IMMAddr => RB(7 downto 0),
CLK => CLK,
OP => OP,
RESULT => WORD_OUT,
DST_ADR => LDST_ADR_8,
STORE_DATA => LDST_DAT);
with OP select
ALU_OUT <=
ARITH when "0000", -- ADD (ARITHMETIC)
ARITH when "0001", -- SUB (ARITHMETIC)
LOGIC when "0010", -- AND (LOGICAL)
LOGIC when "0011", -- OR (LOGICAL)
LOGIC when "0100", -- MOV (LOGICAL)
ARITH when "0101", -- ADDI (ARITHMETIC)
LOGIC when "0110",--, -- ANDI (LOGICAL)
SHIFT when "0111", -- SL (SHIFT)
SHIFT when "1000",--, -- SR (SHIFT)
WORD_OUT when "1001", -- LW (WORD)
RA when "1010", -- SW (WORD)
X"0000" when OTHERS;
with OP select
SREG <=
SREG_AR when "0000", -- ADD (ARITHMETIC)
SREG_AR when "0001", -- SUB (ARITHMETIC)
SREG_LG when "0010", -- AND (LOGICAL)
SREG_LG when "0011", -- OR (LOGICAL)
SREG_LG when "0100", -- MOV (LOGICAL)
SREG_AR when "0101", -- ADDI (ARITHMETIC)
SREG_LG when "0110",--, -- ANDI (LOGICAL)
SREG_SH when "0111", -- SL (SHIFT)
SREG_SH when "1000",--, -- SR (SHIFT)
X"0" when OTHERS;
end Structural;
|
entity tb_var01 is
end tb_var01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_var01 is
signal clk : std_logic;
signal mask : std_logic_vector (3 downto 0);
signal val : std_logic_vector (31 downto 0);
signal res : std_logic_vector (31 downto 0);
begin
dut: entity work.var01
port map (
clk => clk,
mask => mask,
val => val,
res => res);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
mask <= x"f";
val <= x"12_34_56_78";
pulse;
assert res = x"12_34_56_78" report "res=" & to_hstring (res) severity failure;
mask <= x"8";
val <= x"9a_00_00_00";
pulse;
assert res = x"9a_34_56_78" severity failure;
mask <= x"0";
val <= x"00_00_00_00";
pulse;
assert res = x"9a_34_56_78" severity failure;
mask <= x"5";
val <= x"00_bc_00_de";
pulse;
assert res = x"9a_bc_56_de" severity failure;
wait;
end process;
end behav;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.13:54:59)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesaia_alap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14, input15, input16, input17, input18, input19, input20, input21, input22, input23, input24, input25, input26, input27, input28, input29, input30, input31, input32, input33, input34, input35, input36, input37, input38, input39, input40, input41, input42, input43, input44, input45, input46, input47, input48: IN unsigned(0 TO 30);
output1, output2, output3, output4: OUT unsigned(0 TO 31));
END mesaia_alap_entity;
ARCHITECTURE mesaia_alap_description OF mesaia_alap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register7: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register8: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register9: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register10: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register11: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register12: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register13: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register14: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register15: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register16: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register17: unsigned(0 TO 31) := "0000000000000000000000000000000";
SHARED VARIABLE register18: unsigned(0 TO 31) := "0000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
register3 := input3 + 3;
register4 := input4 * 4;
register5 := input5 + 5;
register6 := input6 * 6;
register7 := input7 + 7;
register8 := input8 * 8;
register9 := input9 + 9;
register10 := input10 * 10;
register11 := input11 + 11;
register12 := input12 * 12;
register13 := input13 + 13;
register14 := input14 * 14;
register15 := input15 + 15;
register16 := input16 * 16;
WHEN "00000010" =>
register1 := register2 + register1;
register2 := input17 * 17;
register3 := register4 + register3;
register4 := input18 * 18;
register5 := register6 + register5;
register6 := input19 * 19;
register7 := register8 + register7;
register8 := input20 * 20;
register9 := register10 + register9;
register10 := input21 * 21;
register11 := register12 + register11;
register12 := input22 * 22;
register13 := register14 + register13;
register14 := input23 * 23;
register15 := register16 + register15;
register16 := input24 * 24;
WHEN "00000011" =>
register1 := register2 + register1;
register2 := register4 + register3;
register3 := input25 + 25;
register4 := input26 * 26;
register5 := register6 + register5;
register6 := register8 + register7;
register7 := input27 + 27;
register8 := input28 * 28;
register9 := register10 + register9;
register10 := register12 + register11;
register11 := input29 + 29;
register12 := input30 * 30;
register13 := register14 + register13;
register14 := register16 + register15;
register15 := input31 + 31;
register16 := input32 * 32;
WHEN "00000100" =>
register1 := ((NOT register1) + 1) XOR register1;
register2 := ((NOT register2) + 1) XOR register2;
register3 := register4 + register3;
register4 := input33 * 37;
register5 := ((NOT register5) + 1) XOR register5;
register6 := ((NOT register6) + 1) XOR register6;
register7 := register8 + register7;
register8 := input34 * 42;
register9 := ((NOT register9) + 1) XOR register9;
register10 := ((NOT register10) + 1) XOR register10;
register11 := register12 + register11;
register12 := input35 * 47;
register13 := ((NOT register13) + 1) XOR register13;
register14 := ((NOT register14) + 1) XOR register14;
register15 := register16 + register15;
register16 := input36 * 52;
register17 := input37 + 53;
register18 := input38 * 54;
WHEN "00000101" =>
register1 := register2 - register1;
register2 := register4 + register3;
register3 := input39 + 55;
register4 := input40 * 56;
register5 := register6 - register5;
register6 := register8 + register7;
register7 := input41 + 57;
register8 := input42 * 58;
register9 := register10 - register9;
register10 := register12 + register11;
register11 := input43 + 59;
register12 := input44 * 60;
register13 := register14 - register13;
register14 := register16 + register15;
register15 := register18 + register17;
register16 := input45 * 61;
WHEN "00000110" =>
register1 := register1 * 63;
register2 := ((NOT register2) + 1) XOR register2;
register3 := register4 + register3;
register4 := input46 * 66;
register5 := register5 * 68;
register6 := ((NOT register6) + 1) XOR register6;
register7 := register8 + register7;
register8 := input47 * 71;
register9 := register9 * 73;
register10 := ((NOT register10) + 1) XOR register10;
register11 := register12 + register11;
register12 := input48 * 76;
register13 := register13 * 78;
register14 := ((NOT register14) + 1) XOR register14;
register15 := register16 + register15;
WHEN "00000111" =>
register1 := register2 + register1;
register2 := register4 + register3;
register3 := register6 + register5;
register4 := register8 + register7;
register5 := register10 + register9;
register6 := register12 + register11;
register7 := register14 + register13;
WHEN "00001000" =>
output1 <= register1(0 TO 14) & register15(0 TO 15);
output2 <= register3(0 TO 14) & register2(0 TO 15);
output3 <= register5(0 TO 14) & register4(0 TO 15);
output4 <= register7(0 TO 14) & register6(0 TO 15);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mesaia_alap_description; |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/22/2014
--! Module Name: EPROC_IN4_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
use work.centralRouter_package.all;
--! 8b10b decoder for EPROC_IN4 module
entity EPROC_IN4_DEC8b10b is
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (3 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
busyOut : out std_logic
);
end EPROC_IN4_DEC8b10b;
architecture Behavioral of EPROC_IN4_DEC8b10b is
----------------------------------
----------------------------------
component KcharTest is
port (
clk : in std_logic;
encoded10in : in std_logic_vector (9 downto 0);
KcharCode : out std_logic_vector (1 downto 0)
);
end component KcharTest;
----------------------------------
----------------------------------
signal EDATAbitstreamSREG : std_logic_vector (23 downto 0) := (others=>'0'); -- 24 bit (4 x 5 = 20, plus 4 more)
signal word10bx2_align_array, word10bx2_align_array_r : word10b_2array_4array_type;
signal word10b_array, word10b_array_s : word10b_2array_type;
signal isk_array : isk_2array_type;
signal comma_valid_bits_or, word10bx2_align_rdy_r,
word10b_array_rdy, word10b_array_rdy_s : std_logic;
signal align_select : std_logic_vector (1 downto 0) := (others=>'0');
signal comma_valid_bits : std_logic_vector (3 downto 0);
signal alignment_sreg : std_logic_vector (4 downto 0) := (others=>'0');
begin
-------------------------------------------------------------------------------------------
--live bitstream
-- 24 bit input shift register
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
EDATAbitstreamSREG <= (others => '0');
elsif bitCLK'event and bitCLK = '1' then
EDATAbitstreamSREG <= edataIN & EDATAbitstreamSREG(23 downto 4);
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock0
-- input shift register mapping into 10 bit registers
-------------------------------------------------------------------------------------------
input_map: for I in 0 to 3 generate -- 2 10bit-words per alignment, 4 possible alignments
--word10bx2_align_array(I)(0) <= EDATAbitstreamSREG((I+9) downto (I+0)); -- 1st 10 bit word, alligned to bit I
--word10bx2_align_array(I)(1) <= EDATAbitstreamSREG((I+19) downto (I+10)); -- 2nd 10 bit word, alligned to bit I
word10bx2_align_array(I)(0) <= EDATAbitstreamSREG(I+0)&EDATAbitstreamSREG(I+1)&EDATAbitstreamSREG(I+2)&EDATAbitstreamSREG(I+3)&EDATAbitstreamSREG(I+4)&
EDATAbitstreamSREG(I+5)&EDATAbitstreamSREG(I+6)&EDATAbitstreamSREG(I+7)&EDATAbitstreamSREG(I+8)&EDATAbitstreamSREG(I+9); -- 1st 10 bit word, alligned to bit I
word10bx2_align_array(I)(1) <= EDATAbitstreamSREG(I+10)&EDATAbitstreamSREG(I+11)&EDATAbitstreamSREG(I+12)&EDATAbitstreamSREG(I+13)&EDATAbitstreamSREG(I+14)&
EDATAbitstreamSREG(I+15)&EDATAbitstreamSREG(I+16)&EDATAbitstreamSREG(I+17)&EDATAbitstreamSREG(I+18)&EDATAbitstreamSREG(I+19); -- 2nd 10 bit word, alligned to bit I
end generate input_map;
--
-------------------------------------------------------------------------------------------
--clock0
-- K28.5 comma test
-------------------------------------------------------------------------------------------
comma_test: for I in 0 to 3 generate -- 2 10bit-words per alignment, comma is valid if two first words have comma
comma_valid_bits(I) <= '1' when ((word10bx2_align_array(I)(0) = COMMAp or word10bx2_align_array(I)(0) = COMMAn) and
(word10bx2_align_array(I)(1) = COMMAp or word10bx2_align_array(I)(1) = COMMAn)) else '0';
end generate comma_test;
--
comma_valid_bits_or <= comma_valid_bits(3) or comma_valid_bits(2) or comma_valid_bits(1) or comma_valid_bits(0);
--
-------------------------------------------------------------------------------------------
--clock1
-- alignment selector state
-------------------------------------------------------------------------------------------
process(bitCLK, rst)
begin
if rst = '1' then
alignment_sreg <= "00000";
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
alignment_sreg <= "10000";
else
alignment_sreg <= alignment_sreg(0) & alignment_sreg(4 downto 1);
end if;
end if;
end process;
--
input_reg1: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10bx2_align_array_r <= word10bx2_align_array;
end if;
end process;
--
word10bx2_align_rdy_r <= alignment_sreg(4);
--
process(bitCLK, rst)
begin
if rst = '1' then
align_select <= "00";
elsif bitCLK'event and bitCLK = '1' then
if comma_valid_bits_or = '1' then
align_select(0) <= (not comma_valid_bits(0)) and (
comma_valid_bits(1) or ( (not comma_valid_bits(1)) and (not comma_valid_bits(2)) and (
comma_valid_bits(3)
)));
align_select(1) <= (not comma_valid_bits(0)) and (not comma_valid_bits(1)) and
(comma_valid_bits(2) or comma_valid_bits(3));
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--clock2
-- alignment selected
-------------------------------------------------------------------------------------------
--
input_reg2: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_array_rdy <= word10bx2_align_rdy_r;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case (align_select) is
when "00" => -- bit0 word got comma => align to bit0
word10b_array <= word10bx2_align_array_r(0);
when "01" => -- bit1 word got comma => align to bit1
word10b_array <= word10bx2_align_array_r(1);
when "10" => -- bit2 word got comma => align to bit2
word10b_array <= word10bx2_align_array_r(2);
when "11" => -- bit3 word got comma => align to bit3
word10b_array <= word10bx2_align_array_r(3);
when others =>
end case;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- 8b10b K-characters codes: COMMA/SOC/EOC/DATA
-------------------------------------------------------------------------------------------
KcharTests: for I in 0 to 1 generate
KcharTestn: KcharTest
port map(
clk => bitCLK,
encoded10in => word10b_array(I),
KcharCode => isk_array(I)
);
end generate KcharTests;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
word10b_array_s <= word10b_array;
word10b_array_rdy_s <= word10b_array_rdy;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- 2 words get aligned and ready as 10 bit word (data 8 bit and data code 2 bit)
-------------------------------------------------------------------------------------------
EPROC_IN4_ALIGN_BLOCK_inst: entity work.EPROC_IN4_ALIGN_BLOCK
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst,
bytes => word10b_array_s,
bytes_rdy => word10b_array_rdy_s,
dataOUT => dataOUT,
dataOUTrdy => dataOUTrdy,
busyOut => busyOut
);
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
entity circuito_transmissao is
port(liga : in std_logic;
enviar : in std_logic;
reset : in std_logic;
clock : in std_logic;
CTS : in std_logic;
dado_serial : in std_logic;
envioOk : out std_logic;
DTR : out std_logic;
RTS : out std_logic;
TD : out std_logic;
d_estado : out std_logic_vector(1 downto 0));
end circuito_transmissao;
architecture circuito_transmissao_Arch of circuito_transmissao is
component fluxo_de_dados_transmissao is
port(dado_serial : in std_logic;
enable_transmissao : in std_logic;
TD : out std_logic);
end component;
component unidade_controle_transmissao is
port(liga : in std_logic;
enviar : in std_logic;
reset : in std_logic;
clock : in std_logic;
CTS : in std_logic;
DTR : out std_logic;
RTS : out std_logic;
enable_transmissao : out std_logic;
envioOk : out std_logic;
s_estado : out std_logic_vector(1 downto 0));
end component;
signal s_enable_transmissao : std_logic;
begin
k1 : unidade_controle_transmissao port map (liga, enviar, reset, clock, CTS, DTR, RTS, s_enable_transmissao, envioOk, d_estado);
k2 : fluxo_de_dados_transmissao port map (dado_serial, s_enable_transmissao, TD);
end circuito_transmissao_Arch; |
-- Automatically generated: write_netlist -chip -vhdl -architecture chip-chip_top-a.vhd
architecture chip_top of chip is
component ICP
port (
PAD : in std_logic;
Y : out std_logic
);
end component;
component BU16P
port (
A : in std_logic;
PAD : out std_logic
);
end component;
component ICCK8P
port (
PAD : in std_logic;
Y : out std_logic
);
end component;
component BBC16P
port (
A : in std_logic;
EN : in std_logic;
PAD : inout std_logic;
Y : out std_logic
);
end component;
component BUDD16P
port (
A : in std_logic;
PAD : out std_logic
);
end component;
component ISUP
port (
PAD : in std_logic;
Y : out std_logic
);
end component;
component Core
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Cpu_En_i : in std_logic;
LFXT_Clk_i : in std_logic;
Dbg_En_i : in std_logic;
Dbg_SCL_i : in std_logic;
Dbg_SDA_Out_o : out std_logic;
Dbg_SDA_In_i : in std_logic;
P1_DOut_o : out std_logic_vector(7 downto 0);
P1_En_o : out std_logic_vector(7 downto 0);
P1_DIn_i : in std_logic_vector(7 downto 0);
P2_DOut_o : out std_logic_vector(7 downto 0);
P2_En_o : out std_logic_vector(7 downto 0);
P2_DIn_i : in std_logic_vector(7 downto 0);
UartRxD_i : in std_logic;
UartTxD_o : out std_logic;
SCK_o : out std_logic;
MOSI_o : out std_logic;
MISO_i : in std_logic;
Inputs_i : in std_logic_vector(7 downto 0);
Outputs_o : out std_logic_vector(7 downto 0);
SPIMISO_i : in std_logic;
SPIMOSI_o : out std_logic;
SPISCK_o : out std_logic;
I2CSCL_o : out std_logic;
I2CSDA_i : in std_logic;
I2CSDA_o : out std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(9 downto 0)
);
end component;
signal Reset_n_i_s : std_logic;
signal Clk_i_s : std_logic;
signal Cpu_En_i_s : std_logic;
signal Dbg_En_i_s : std_logic;
signal Dbg_SCL_i_s : std_logic;
signal Dbg_SDA_In_i_s : std_logic;
signal Dbg_SDA_Out_o_s : std_logic;
signal P1_DIn_i_s : std_logic_vector(7 downto 0);
signal P1_DOut_o_s : std_logic_vector(7 downto 0);
signal P1_En_o_s : std_logic_vector(7 downto 0);
signal P1_En_o_s_n : std_logic_vector(7 downto 0);
signal P2_DIn_i_s : std_logic_vector(7 downto 0);
signal P2_DOut_o_s : std_logic_vector(7 downto 0);
signal P2_En_o_s : std_logic_vector(7 downto 0);
signal P2_En_o_s_n : std_logic_vector(7 downto 0);
signal UartRxD_i_s : std_logic;
signal UartTxD_o_s : std_logic;
signal MISO_i_s : std_logic;
signal MOSI_o_s : std_logic;
signal SCK_o_s : std_logic;
signal Inputs_i_s : std_logic_vector(7 downto 0);
signal Outputs_o_s : std_logic_vector(7 downto 0);
signal SPIMISO_i_s : std_logic;
signal SPIMOSI_o_s : std_logic;
signal SPISCK_o_s : std_logic;
signal I2CSCL_o_s : std_logic;
signal I2CSDA_i_s : std_logic;
signal I2CSDA_o_s : std_logic;
signal AdcConvComplete_i_s : std_logic;
signal AdcDoConvert_o_s : std_logic;
signal AdcValue_i_s : std_logic_vector(9 downto 0);
begin
core_1: Core
port map (
Reset_n_i => Reset_n_i_s,
Clk_i => Clk_i_s,
Cpu_En_i => Cpu_En_i_s,
LFXT_Clk_i => '0',
Dbg_En_i => Dbg_En_i_s,
Dbg_SCL_i => Dbg_SCL_i_s,
Dbg_SDA_In_i => Dbg_SDA_In_i_s,
Dbg_SDA_Out_o => Dbg_SDA_Out_o_s,
P1_DIn_i => P1_DIn_i_s,
P1_DOut_o => P1_DOut_o_s,
P1_En_o => P1_En_o_s,
P2_DIn_i => P2_DIn_i_s,
P2_DOut_o => P2_DOut_o_s,
P2_En_o => P2_En_o_s,
UartRxD_i => UartRxD_i_s,
UartTxD_o => UartTxD_o_s,
MISO_i => MISO_i_s,
MOSI_o => MOSI_o_s,
SCK_o => SCK_o_s,
Inputs_i => Inputs_i_s,
Outputs_o => Outputs_o_s,
SPIMISO_i => SPIMISO_i_s,
SPIMOSI_o => SPIMOSI_o_s,
SPISCK_o => SPISCK_o_s,
I2CSCL_o => I2CSCL_o_s,
I2CSDA_i => I2CSDA_i_s,
I2CSDA_o => I2CSDA_o_s,
AdcConvComplete_i => AdcConvComplete_i_s,
AdcDoConvert_o => AdcDoConvert_o_s,
AdcValue_i => AdcValue_i_s
);
PadReset_n_i: ISUP
port map (
PAD => Reset_n_i,
Y => Reset_n_i_s
);
PadClk_i: ICCK8P
port map (
PAD => Clk_i,
Y => Clk_i_s
);
PadCpu_En_i: ICP
port map (
PAD => Cpu_En_i,
Y => Cpu_En_i_s
);
PadDbg_En_i: ICP
port map (
PAD => Dbg_En_i,
Y => Dbg_En_i_s
);
PadDbg_SCL_i: ICP
port map (
PAD => Dbg_SCL_i,
Y => Dbg_SCL_i_s
);
PadDbg_SDA_b: BBC16P
port map (
PAD => Dbg_SDA_b,
Y => Dbg_SDA_In_i_s,
A => '0',
EN => Dbg_SDA_Out_o_s
);
P1_En_o_s_n <= not P1_En_o_s;
PadP1_b_0: BBC16P
port map (
PAD => P1_b(0),
Y => P1_DIn_i_s(0),
A => P1_DOut_o_s(0),
EN => P1_En_o_s_n(0)
);
PadP1_b_1: BBC16P
port map (
PAD => P1_b(1),
Y => P1_DIn_i_s(1),
A => P1_DOut_o_s(1),
EN => P1_En_o_s_n(1)
);
PadP1_b_2: BBC16P
port map (
PAD => P1_b(2),
Y => P1_DIn_i_s(2),
A => P1_DOut_o_s(2),
EN => P1_En_o_s_n(2)
);
PadP1_b_3: BBC16P
port map (
PAD => P1_b(3),
Y => P1_DIn_i_s(3),
A => P1_DOut_o_s(3),
EN => P1_En_o_s_n(3)
);
PadP1_b_4: BBC16P
port map (
PAD => P1_b(4),
Y => P1_DIn_i_s(4),
A => P1_DOut_o_s(4),
EN => P1_En_o_s_n(4)
);
PadP1_b_5: BBC16P
port map (
PAD => P1_b(5),
Y => P1_DIn_i_s(5),
A => P1_DOut_o_s(5),
EN => P1_En_o_s_n(5)
);
PadP1_b_6: BBC16P
port map (
PAD => P1_b(6),
Y => P1_DIn_i_s(6),
A => P1_DOut_o_s(6),
EN => P1_En_o_s_n(6)
);
PadP1_b_7: BBC16P
port map (
PAD => P1_b(7),
Y => P1_DIn_i_s(7),
A => P1_DOut_o_s(7),
EN => P1_En_o_s_n(7)
);
P2_En_o_s_n <= not P2_En_o_s;
PadP2_b_0: BBC16P
port map (
PAD => P2_b(0),
Y => P2_DIn_i_s(0),
A => P2_DOut_o_s(0),
EN => P2_En_o_s_n(0)
);
PadP2_b_1: BBC16P
port map (
PAD => P2_b(1),
Y => P2_DIn_i_s(1),
A => P2_DOut_o_s(1),
EN => P2_En_o_s_n(1)
);
PadP2_b_2: BBC16P
port map (
PAD => P2_b(2),
Y => P2_DIn_i_s(2),
A => P2_DOut_o_s(2),
EN => P2_En_o_s_n(2)
);
PadP2_b_3: BBC16P
port map (
PAD => P2_b(3),
Y => P2_DIn_i_s(3),
A => P2_DOut_o_s(3),
EN => P2_En_o_s_n(3)
);
PadP2_b_4: BBC16P
port map (
PAD => P2_b(4),
Y => P2_DIn_i_s(4),
A => P2_DOut_o_s(4),
EN => P2_En_o_s_n(4)
);
PadP2_b_5: BBC16P
port map (
PAD => P2_b(5),
Y => P2_DIn_i_s(5),
A => P2_DOut_o_s(5),
EN => P2_En_o_s_n(5)
);
PadP2_b_6: BBC16P
port map (
PAD => P2_b(6),
Y => P2_DIn_i_s(6),
A => P2_DOut_o_s(6),
EN => P2_En_o_s_n(6)
);
PadP2_b_7: BBC16P
port map (
PAD => P2_b(7),
Y => P2_DIn_i_s(7),
A => P2_DOut_o_s(7),
EN => P2_En_o_s_n(7)
);
PadUartRxD_i: ICP
port map (
PAD => UartRxD_i,
Y => UartRxD_i_s
);
PadUartTxD_o: BU16P
port map (
PAD => UartTxD_o,
A => UartTxD_o_s
);
PadMISO_i: ICP
port map (
PAD => MISO_i,
Y => MISO_i_s
);
PadMOSI_o: BU16P
port map (
PAD => MOSI_o,
A => MOSI_o_s
);
PadSCK_o: BU16P
port map (
PAD => SCK_o,
A => SCK_o_s
);
PadInputs_i_0: ICP
port map (
PAD => Inputs_i(0),
Y => Inputs_i_s(0)
);
PadInputs_i_1: ICP
port map (
PAD => Inputs_i(1),
Y => Inputs_i_s(1)
);
PadInputs_i_2: ICP
port map (
PAD => Inputs_i(2),
Y => Inputs_i_s(2)
);
PadInputs_i_3: ICP
port map (
PAD => Inputs_i(3),
Y => Inputs_i_s(3)
);
PadInputs_i_4: ICP
port map (
PAD => Inputs_i(4),
Y => Inputs_i_s(4)
);
PadInputs_i_5: ICP
port map (
PAD => Inputs_i(5),
Y => Inputs_i_s(5)
);
PadInputs_i_6: ICP
port map (
PAD => Inputs_i(6),
Y => Inputs_i_s(6)
);
PadInputs_i_7: ICP
port map (
PAD => Inputs_i(7),
Y => Inputs_i_s(7)
);
PadOutputs_o_0: BU16P
port map (
PAD => Outputs_o(0),
A => Outputs_o_s(0)
);
PadOutputs_o_1: BU16P
port map (
PAD => Outputs_o(1),
A => Outputs_o_s(1)
);
PadOutputs_o_2: BU16P
port map (
PAD => Outputs_o(2),
A => Outputs_o_s(2)
);
PadOutputs_o_3: BU16P
port map (
PAD => Outputs_o(3),
A => Outputs_o_s(3)
);
PadOutputs_o_4: BU16P
port map (
PAD => Outputs_o(4),
A => Outputs_o_s(4)
);
PadOutputs_o_5: BU16P
port map (
PAD => Outputs_o(5),
A => Outputs_o_s(5)
);
PadOutputs_o_6: BU16P
port map (
PAD => Outputs_o(6),
A => Outputs_o_s(6)
);
PadOutputs_o_7: BU16P
port map (
PAD => Outputs_o(7),
A => Outputs_o_s(7)
);
PadSPIMISO_i: ICP
port map (
PAD => SPIMISO_i,
Y => SPIMISO_i_s
);
PadSPIMOSI_o: BU16P
port map (
PAD => SPIMOSI_o,
A => SPIMOSI_o_s
);
PadSPISCK_o: BU16P
port map (
PAD => SPISCK_o,
A => SPISCK_o_s
);
PadI2CSCL_b: BUDD16P
port map (
PAD => I2CSCL_b,
A => I2CSCL_o_s
);
PadI2CSDA_b: BBC16P
port map (
PAD => I2CSDA_b,
Y => I2CSDA_i_s,
A => '0',
EN => I2CSDA_o_s
);
PadAdcConvComplete_i: ICP
port map (
PAD => AdcConvComplete_i,
Y => AdcConvComplete_i_s
);
PadAdcDoConvert_o: BU16P
port map (
PAD => AdcDoConvert_o,
A => AdcDoConvert_o_s
);
PadAdcValue_i_0: ICP
port map (
PAD => AdcValue_i(0),
Y => AdcValue_i_s(0)
);
PadAdcValue_i_1: ICP
port map (
PAD => AdcValue_i(1),
Y => AdcValue_i_s(1)
);
PadAdcValue_i_2: ICP
port map (
PAD => AdcValue_i(2),
Y => AdcValue_i_s(2)
);
PadAdcValue_i_3: ICP
port map (
PAD => AdcValue_i(3),
Y => AdcValue_i_s(3)
);
PadAdcValue_i_4: ICP
port map (
PAD => AdcValue_i(4),
Y => AdcValue_i_s(4)
);
PadAdcValue_i_5: ICP
port map (
PAD => AdcValue_i(5),
Y => AdcValue_i_s(5)
);
PadAdcValue_i_6: ICP
port map (
PAD => AdcValue_i(6),
Y => AdcValue_i_s(6)
);
PadAdcValue_i_7: ICP
port map (
PAD => AdcValue_i(7),
Y => AdcValue_i_s(7)
);
PadAdcValue_i_8: ICP
port map (
PAD => AdcValue_i(8),
Y => AdcValue_i_s(8)
);
PadAdcValue_i_9: ICP
port map (
PAD => AdcValue_i(9),
Y => AdcValue_i_s(9)
);
end chip_top;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 71968)
`protect data_block
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qLRavHXkNHJlm4qzX5n+2DVZgLNEF0qeXqTTBJ5dgVqB6Q==
`protect end_protected
|
--741
entity counter741 is
port(clk :in bit;
Qout:out unsigned(3 downto 0));
end entity counter741;
architecture neibu of counter741 is
signal Q:unsigned(3 downto 0);
begin
Qout<=Q;
process(clk)
begin
end process;
end architecture neibu; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:12:12 10/24/2014
-- Design Name:
-- Module Name: SevenSeg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD;
use IEEE.NUMERIC_STD.ALL;
use work.all;
use work.types.all;
use work.topEntity_0;
--library UNISIM;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SevenSeg is
port ( Seg7 : OUT STD_LOGIC_VECTOR(6 downto 0)
; Seg7_AN : OUT STD_LOGIC_VECTOR(3 downto 0)
; Seg7_DP : OUT STD_LOGIC
; Switch : IN STD_LOGIC_VECTOR(7 downto 0)
; Led : OUT STD_LOGIC_VECTOR(7 downto 0)
; clk : IN STD_LOGIC
);
end SevenSeg;
ARCHITECTURE Behavioral OF SevenSeg IS
signal recordish : product2;
signal clkin : STD_LOGIC;
BEGIN
t : entity topEntity_0 PORT MAP (
system1000 => clkin
, system1000_rst => '1'
, topLet_o => recordish
);
clkin <= clk;
Seg7_an <= toSLV(recordish.product2_sel0);
Seg7 <= toSLV(recordish.product2_sel1);
Seg7_DP <= '1';
Led <= Switch;
END Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
entity BitStringValuesEnt is
generic(
C_1 : std_logic := '1';
C_0 : std_logic := '0';
C_1b1 : std_logic_vector := "1";
C_1b0 : std_logic_vector := "0";
C_16b1 : std_logic_vector := X"0000FFFF";
C_32b0 : std_logic_vector := X"00000000";
C_32b1 : std_logic_vector := X"FFFFFFFF";
C_128b1 : std_logic_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
);
port(
ACLK : in std_logic
);
end BitStringValuesEnt;
|
----------------------------------------------------------------------
---- ----
---- Pipelined Aes IP Core ----
---- ----
---- This file is part of the Pipelined AES project ----
---- http://www.opencores.org/cores/aes_pipe/ ----
---- ----
---- Description ----
---- Implementation of AES IP core according to ----
---- FIPS PUB 197 specification document. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Subhasis Das, subhasis256@gmail.com ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2009 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
------------------------------------------------------
-- Project: AESFast
-- Author: Subhasis
-- Last Modified: 25/03/10
-- Email: subhasis256@gmail.com
------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity SBox_module is
Generic ( BYTE_LENGTH : integer := 8 );
Port ( data_out : out STD_LOGIC_VECTOR (BYTE_LENGTH-1 downto 0);
finish : out STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (BYTE_LENGTH-1 downto 0);
start : in STD_LOGIC);
end SBox_module;
architecture RTL of SBox_module is
-----------------------------
----------- TYPES -----------
-----------------------------
type ram_type is array(natural range<>) of std_logic_vector(7 downto 0);
-----------------------------
--------- CONSTANTS ---------
-----------------------------
constant sbox_ram: ram_type(255 downto 0) :=
(
X"16", X"bb", X"54", X"b0", X"0f", X"2d", X"99", X"41", X"68", X"42", X"e6", X"bf", X"0d", X"89", X"a1", X"8c",
X"df", X"28", X"55", X"ce", X"e9", X"87", X"1e", X"9b", X"94", X"8e", X"d9", X"69", X"11", X"98", X"f8", X"e1",
X"9e", X"1d", X"c1", X"86", X"b9", X"57", X"35", X"61", X"0e", X"f6", X"03", X"48", X"66", X"b5", X"3e", X"70",
X"8a", X"8b", X"bd", X"4b", X"1f", X"74", X"dd", X"e8", X"c6", X"b4", X"a6", X"1c", X"2e", X"25", X"78", X"ba",
X"08", X"ae", X"7a", X"65", X"ea", X"f4", X"56", X"6c", X"a9", X"4e", X"d5", X"8d", X"6d", X"37", X"c8", X"e7",
X"79", X"e4", X"95", X"91", X"62", X"ac", X"d3", X"c2", X"5c", X"24", X"06", X"49", X"0a", X"3a", X"32", X"e0",
X"db", X"0b", X"5e", X"de", X"14", X"b8", X"ee", X"46", X"88", X"90", X"2a", X"22", X"dc", X"4f", X"81", X"60",
X"73", X"19", X"5d", X"64", X"3d", X"7e", X"a7", X"c4", X"17", X"44", X"97", X"5f", X"ec", X"13", X"0c", X"cd",
X"d2", X"f3", X"ff", X"10", X"21", X"da", X"b6", X"bc", X"f5", X"38", X"9d", X"92", X"8f", X"40", X"a3", X"51",
X"a8", X"9f", X"3c", X"50", X"7f", X"02", X"f9", X"45", X"85", X"33", X"4d", X"43", X"fb", X"aa", X"ef", X"d0",
X"cf", X"58", X"4c", X"4a", X"39", X"be", X"cb", X"6a", X"5b", X"b1", X"fc", X"20", X"ed", X"00", X"d1", X"53",
X"84", X"2f", X"e3", X"29", X"b3", X"d6", X"3b", X"52", X"a0", X"5a", X"6e", X"1b", X"1a", X"2c", X"83", X"09",
X"75", X"b2", X"27", X"eb", X"e2", X"80", X"12", X"07", X"9a", X"05", X"96", X"18", X"c3", X"23", X"c7", X"04",
X"15", X"31", X"d8", X"71", X"f1", X"e5", X"a5", X"34", X"cc", X"f7", X"3f", X"36", X"26", X"93", X"fd", X"b7",
X"c0", X"72", X"a4", X"9c", X"af", X"a2", X"d4", X"ad", X"f0", X"47", X"59", X"fa", X"7d", X"c9", X"82", X"ca",
X"76", X"ab", X"d7", X"fe", X"2b", X"67", X"01", X"30", X"c5", X"6f", X"6b", X"f2", X"7b", X"77", X"7c", X"63"
);
begin
replace: process(start)
begin
if(rising_edge(start)) then
data_out <= sbox_ram(conv_integer(data_in));
finish <= '1';
end if;
end process replace;
end RTL;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
empty: in std_logic;
grants: in std_logic;
Rxy_in: in std_logic_vector(7 downto 0);
Rxy_reconf: in std_logic_vector(7 downto 0);
ReConf_FF_in: in std_logic;
Rxy: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end Rxy_Reconf_pseudo_checkers;
architecture behavior of Rxy_Reconf_pseudo_checkers is
begin
process(ReConf_FF_out, flit_type, empty, grants, Rxy_in, Rxy_reconf)
begin
if (ReConf_FF_out = '1' and flit_type = "100" and empty = '0' and grants = '1' and Rxy_in /= Rxy_reconf) then
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal <= '1';
else
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, ReConf_FF_in)
begin
if (ReConf_FF_out = '1' and flit_type = "100" and empty = '0' and grants = '1' and ReConf_FF_in = '1') then
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in <= '1';
else
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, Rxy_in, Rxy)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Rxy_in /= Rxy) then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, Reconfig, ReConf_FF_in)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Reconfig = '1' and ReConf_FF_in = '0') then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, Reconfig, ReConf_FF_in, ReConf_FF_out)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Reconfig = '0' and ReConf_FF_in /= ReConf_FF_out) then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal <= '0';
end if;
end process;
end; |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
empty: in std_logic;
grants: in std_logic;
Rxy_in: in std_logic_vector(7 downto 0);
Rxy_reconf: in std_logic_vector(7 downto 0);
ReConf_FF_in: in std_logic;
Rxy: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end Rxy_Reconf_pseudo_checkers;
architecture behavior of Rxy_Reconf_pseudo_checkers is
begin
process(ReConf_FF_out, flit_type, empty, grants, Rxy_in, Rxy_reconf)
begin
if (ReConf_FF_out = '1' and flit_type = "100" and empty = '0' and grants = '1' and Rxy_in /= Rxy_reconf) then
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal <= '1';
else
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, ReConf_FF_in)
begin
if (ReConf_FF_out = '1' and flit_type = "100" and empty = '0' and grants = '1' and ReConf_FF_in = '1') then
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in <= '1';
else
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, Rxy_in, Rxy)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Rxy_in /= Rxy) then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, Reconfig, ReConf_FF_in)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Reconfig = '1' and ReConf_FF_in = '0') then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, Reconfig, ReConf_FF_in, ReConf_FF_out)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Reconfig = '0' and ReConf_FF_in /= ReConf_FF_out) then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal <= '0';
end if;
end process;
end; |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
empty: in std_logic;
grants: in std_logic;
Rxy_in: in std_logic_vector(7 downto 0);
Rxy_reconf: in std_logic_vector(7 downto 0);
ReConf_FF_in: in std_logic;
Rxy: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end Rxy_Reconf_pseudo_checkers;
architecture behavior of Rxy_Reconf_pseudo_checkers is
begin
process(ReConf_FF_out, flit_type, empty, grants, Rxy_in, Rxy_reconf)
begin
if (ReConf_FF_out = '1' and flit_type = "100" and empty = '0' and grants = '1' and Rxy_in /= Rxy_reconf) then
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal <= '1';
else
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, ReConf_FF_in)
begin
if (ReConf_FF_out = '1' and flit_type = "100" and empty = '0' and grants = '1' and ReConf_FF_in = '1') then
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in <= '1';
else
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, Rxy_in, Rxy)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Rxy_in /= Rxy) then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, Reconfig, ReConf_FF_in)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Reconfig = '1' and ReConf_FF_in = '0') then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, Reconfig, ReConf_FF_in, ReConf_FF_out)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Reconfig = '0' and ReConf_FF_in /= ReConf_FF_out) then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal <= '0';
end if;
end process;
end; |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
empty: in std_logic;
grants: in std_logic;
Rxy_in: in std_logic_vector(7 downto 0);
Rxy_reconf: in std_logic_vector(7 downto 0);
ReConf_FF_in: in std_logic;
Rxy: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end Rxy_Reconf_pseudo_checkers;
architecture behavior of Rxy_Reconf_pseudo_checkers is
begin
process(ReConf_FF_out, flit_type, empty, grants, Rxy_in, Rxy_reconf)
begin
if (ReConf_FF_out = '1' and flit_type = "100" and empty = '0' and grants = '1' and Rxy_in /= Rxy_reconf) then
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal <= '1';
else
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, ReConf_FF_in)
begin
if (ReConf_FF_out = '1' and flit_type = "100" and empty = '0' and grants = '1' and ReConf_FF_in = '1') then
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in <= '1';
else
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, Rxy_in, Rxy)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Rxy_in /= Rxy) then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, Reconfig, ReConf_FF_in)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Reconfig = '1' and ReConf_FF_in = '0') then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, Reconfig, ReConf_FF_in, ReConf_FF_out)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Reconfig = '0' and ReConf_FF_in /= ReConf_FF_out) then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal <= '0';
end if;
end process;
end; |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
empty: in std_logic;
grants: in std_logic;
Rxy_in: in std_logic_vector(7 downto 0);
Rxy_reconf: in std_logic_vector(7 downto 0);
ReConf_FF_in: in std_logic;
Rxy: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end Rxy_Reconf_pseudo_checkers;
architecture behavior of Rxy_Reconf_pseudo_checkers is
begin
process(ReConf_FF_out, flit_type, empty, grants, Rxy_in, Rxy_reconf)
begin
if (ReConf_FF_out = '1' and flit_type = "100" and empty = '0' and grants = '1' and Rxy_in /= Rxy_reconf) then
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal <= '1';
else
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, ReConf_FF_in)
begin
if (ReConf_FF_out = '1' and flit_type = "100" and empty = '0' and grants = '1' and ReConf_FF_in = '1') then
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in <= '1';
else
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, Rxy_in, Rxy)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Rxy_in /= Rxy) then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, Reconfig, ReConf_FF_in)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Reconfig = '1' and ReConf_FF_in = '0') then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, Reconfig, ReConf_FF_in, ReConf_FF_out)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Reconfig = '0' and ReConf_FF_in /= ReConf_FF_out) then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal <= '0';
end if;
end process;
end; |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
empty: in std_logic;
grants: in std_logic;
Rxy_in: in std_logic_vector(7 downto 0);
Rxy_reconf: in std_logic_vector(7 downto 0);
ReConf_FF_in: in std_logic;
Rxy: in std_logic_vector(7 downto 0);
Reconfig : in std_logic;
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal,
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in,
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal : out std_logic
);
end Rxy_Reconf_pseudo_checkers;
architecture behavior of Rxy_Reconf_pseudo_checkers is
begin
process(ReConf_FF_out, flit_type, empty, grants, Rxy_in, Rxy_reconf)
begin
if (ReConf_FF_out = '1' and flit_type = "100" and empty = '0' and grants = '1' and Rxy_in /= Rxy_reconf) then
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal <= '1';
else
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_reconf_equal <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, ReConf_FF_in)
begin
if (ReConf_FF_out = '1' and flit_type = "100" and empty = '0' and grants = '1' and ReConf_FF_in = '1') then
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in <= '1';
else
err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, Rxy_in, Rxy)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Rxy_in /= Rxy) then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, Reconfig, ReConf_FF_in)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Reconfig = '1' and ReConf_FF_in = '0') then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_ReConf_FF_in <= '0';
end if;
end process;
process(ReConf_FF_out, flit_type, empty, grants, Reconfig, ReConf_FF_in, ReConf_FF_out)
begin
if ( (ReConf_FF_out = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Reconfig = '0' and ReConf_FF_in /= ReConf_FF_out) then
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal <= '1';
else
err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_ReConf_FF_in_ReConf_FF_out_equal <= '0';
end if;
end process;
end; |
---------------------------------------------------------
-- Routing Mechanism
---------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.PhoenixPackage.all;
use work.TablePackage.all;
entity routingMechanism is
generic(address : regmetadeflit := (others=>'0'));
port(
clock : in std_logic;
reset : in std_logic;
buffCtrl: in buffControl; -- linha correspondente a tabela de roteamento lido do pacote de controle que sera escrita na tabela
ctrl : in std_logic; -- indica se foi lido ou criado de um pacote de controle pelo buffer
operacao: in regflit; -- codigo de controle do pacote de controle (terceiro flit do pacote de controle)
ceT: in std_logic; -- chip enable da tabela de roteamento. Indica que sera escrito na tabela de roteamento
oe : in std_logic;
dest : in reg8;
inputPort : in integer range 0 to (NPORT-1); -- porta de entrada selecionada pelo arbitro para ser chaveada
outputPort : out regNPort; -- indica qual porta de saida o pacote sera encaminhado
find : out RouterControl
);
end routingMechanism;
architecture behavior of routingMechanism is
-- sinais da máquina de estado
type state is (S0,S1,S2,S3,S4);
signal ES, PES : state;
-- sinais da Tabela
signal ce: std_logic := '0';
signal data : std_logic_vector(4 downto 0) := (others=>'0');
signal rowDst, colDst : integer;
type row is array ((NREG-1) downto 0) of integer;
signal rowInf, colInf, rowSup, colSup : row;
signal H : std_logic_vector((NREG-1) downto 0);
-------------New Hardware---------------
signal VertInf, VertSup : regAddr;
signal func : STD_LOGIC_VECTOR(7 downto 0);
signal OP : STD_LOGIC_VECTOR(4 downto 0);
type arrayIP is array ((NREG-1) downto 0) of std_logic_vector(4 downto 0);
signal IP : arrayIP;
signal IP_lido: STD_LOGIC_VECTOR(4 downto 0);
signal i : integer := 0;
signal RAM: memory := TAB(ADDRESS_TO_NUMBER_NOIA(address));
begin
rowDst <= TO_INTEGER(unsigned(dest(7 downto 4))) when ctrl = '0' else 0;
colDst <= TO_INTEGER(unsigned(dest(3 downto 0))) when ctrl = '0' else 0;
cond: for j in 0 to (NREG - 1) generate
rowInf(j) <= TO_INTEGER(unsigned(RAM(j)(20 downto 17))) when ctrl = '0' else 0;
colInf(j) <= TO_INTEGER(unsigned(RAM(j)(16 downto 13))) when ctrl = '0' else 0;
rowSup(j) <= TO_INTEGER(unsigned(RAM(j)(12 downto 9))) when ctrl = '0' else 0;
colSup(j) <= TO_INTEGER(unsigned(RAM(j)(8 downto 5))) when ctrl = '0' else 0;
IP(j) <= RAM(j)(25 downto 21) when ctrl = '0' else (others=>'0');
H(j) <= '1' when rowDst >= rowInf(j) and rowDst <= rowSup(j) and
colDst >= colInf(j) and colDst <= colSup(j) and
IP(j)(inputPort) = '1' and ctrl = '0' else
'0';
end generate;
process(RAM, H, ce, ctrl)
begin
data <= (others=>'Z');
if ce = '1' and ctrl = '0' then
for i in 0 to (NREG-1) loop
if H(i) = '1' then
data <= RAM(i)(4 downto 0);
end if;
end loop;
end if;
end process;
func <= operacao(7 downto 0);
IP_lido <= buffCtrl(0)(4 downto 0);
VertInf <= buffCtrl(1)(7 downto 0);
VertSup <= buffCtrl(2)(7 downto 0);
OP <= buffCtrl(3)(4 downto 0);
process(ceT,ctrl)
begin
if ctrl = '0' then
i <= 0;
elsif ctrl = '1' and ceT = '1' and func = x"01" then
RAM(i)(25 downto 21) <= IP_lido(4 downto 0);
RAM(i)(20 downto 13) <= VertInf(7 downto 0);
RAM(i)(12 downto 5) <= VertSup(7 downto 0);
RAM(i)(4 downto 0) <= OP(4 downto 0);
if (i = NREG-1) then
i <= 0;
else
i <= i + 1;
end if;
end if;
end process;
process(reset,clock)
begin
if reset='1' then
ES<=S0;
elsif clock'event and clock='0' then
ES<=PES;
end if;
end process;
------------------------------------------------------------------------------------------------------
-- PARTE COMBINACIONAL PARA DEFINIR O PROXIMO ESTADO DA MAQUINA
--
-- S0 -> Este estado espera oe = '1' (operation enabled), indicando que ha um pacote que que deve
-- ser roteado.
-- S1 -> Este estado ocorre a leitura na memeria - tabela, a fim de obter as
-- definicoes de uma regiao.
-- S2 -> Este estado verifica se o roteador destino (destRouter) pertence aquela
-- regiao. Caso ele pertenca, o sinal de RM eh ativado e a maquina de estados
-- avanca para o proximo estado, caso contrario retorna para o estado S1 e
-- busca por uma nova regiao.
-- S3 -> Neste estado o switch control eh avisado (find="01") que foi descoberto por
-- qual porta este pacote deve sair. Este estado tambem zera count, valor que
-- aponta qual o proximo endereco deve ser lido na memoria.
-- S4 -> Aguarda oe = '0' e retorna para o estado S0.
process(ES, oe)
begin
case ES is
when S0 => if oe = '1' then PES <= S1; else PES <= S0; end if;
when S1 => PES <= S2;
when S2 => PES <= S3;
when S3 => if oe = '0' then PES <= S0; else PES <= S3; end if;
when others => PES <= S0;
end case;
end process;
------------------------------------------------------------------------------------------------------
-- executa as acoes correspondente ao estado atual da maquina de estados
------------------------------------------------------------------------------------------------------
process(clock)
begin
if(clock'event and clock = '1') then
case ES is
-- Aguarda oe='1'
when S0 =>
find <= invalidRegion;
-- Leitura da tabela
when S1 =>
ce <= '1';
-- Informa que achou a porta de saida para o pacote
when S2 =>
find <= validRegion;
-- Aguarda oe='0'
when S3 =>
ce <= '0';
find <= invalidRegion;
when others =>
find <= portError;
end case;
end if;
end process;
outputPort <= data;
end behavior; |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 14 11:02:39 2017
-- Host : PC4719 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_0_sim_netlist.vhdl
-- Design : vio_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder is
port (
s_drdy_i : out STD_LOGIC;
\wr_en_reg[4]_0\ : out STD_LOGIC;
\wr_en_reg[4]_1\ : out STD_LOGIC;
\wr_en_reg[4]_2\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_do_i : out STD_LOGIC_VECTOR ( 15 downto 0 );
s_rst_o : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
\out\ : in STD_LOGIC;
s_daddr_o : in STD_LOGIC_VECTOR ( 16 downto 0 );
s_dwe_o : in STD_LOGIC;
s_den_o : in STD_LOGIC;
\Bus_Data_out_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder is
signal Hold_probe_in : STD_LOGIC;
signal clear_int : STD_LOGIC;
signal committ_int : STD_LOGIC;
signal \data_info_probe_in__67\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal int_cnt_rst : STD_LOGIC;
signal probe_out_modified : STD_LOGIC_VECTOR ( 15 downto 0 );
signal rd_en_p1 : STD_LOGIC;
signal rd_en_p2 : STD_LOGIC;
signal wr_control_reg : STD_LOGIC;
signal \wr_en[2]_i_1_n_0\ : STD_LOGIC;
signal \wr_en[2]_i_2_n_0\ : STD_LOGIC;
signal \wr_en[4]_i_1_n_0\ : STD_LOGIC;
signal \wr_en[4]_i_6_n_0\ : STD_LOGIC;
signal \^wr_en_reg[4]_0\ : STD_LOGIC;
signal \^wr_en_reg[4]_1\ : STD_LOGIC;
signal \^wr_en_reg[4]_2\ : STD_LOGIC;
signal wr_probe_out_modified : STD_LOGIC;
signal xsdb_addr_2_0_p1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xsdb_addr_2_0_p2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xsdb_addr_8_p1 : STD_LOGIC;
signal xsdb_addr_8_p2 : STD_LOGIC;
signal xsdb_drdy_i_1_n_0 : STD_LOGIC;
signal xsdb_rd : STD_LOGIC;
signal xsdb_wr : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Bus_data_out[12]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \Bus_data_out[13]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \Bus_data_out[14]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \Bus_data_out[15]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \wr_en[2]_i_2\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \wr_en[4]_i_2\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \wr_en[4]_i_6\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of xsdb_drdy_i_1 : label is "soft_lutpair14";
begin
\wr_en_reg[4]_0\ <= \^wr_en_reg[4]_0\;
\wr_en_reg[4]_1\ <= \^wr_en_reg[4]_1\;
\wr_en_reg[4]_2\ <= \^wr_en_reg[4]_2\;
\Bus_data_out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AF00AF000FC000C0"
)
port map (
I0 => \Bus_Data_out_reg[11]\(0),
I1 => probe_out_modified(0),
I2 => xsdb_addr_2_0_p2(2),
I3 => xsdb_addr_2_0_p2(1),
I4 => committ_int,
I5 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(0)
);
\Bus_data_out[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(10),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(10),
O => \data_info_probe_in__67\(10)
);
\Bus_data_out[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(11),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(11),
O => \data_info_probe_in__67\(11)
);
\Bus_data_out[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(12),
I3 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(12)
);
\Bus_data_out[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(13),
I3 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(13)
);
\Bus_data_out[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(14),
I3 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(14)
);
\Bus_data_out[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(15),
I3 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(15)
);
\Bus_data_out[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0000FC0A00000C0"
)
port map (
I0 => \Bus_Data_out_reg[11]\(1),
I1 => probe_out_modified(1),
I2 => xsdb_addr_2_0_p2(2),
I3 => xsdb_addr_2_0_p2(1),
I4 => xsdb_addr_2_0_p2(0),
I5 => clear_int,
O => \data_info_probe_in__67\(1)
);
\Bus_data_out[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A000000F00CFCF"
)
port map (
I0 => \Bus_Data_out_reg[11]\(2),
I1 => probe_out_modified(2),
I2 => xsdb_addr_2_0_p2(2),
I3 => int_cnt_rst,
I4 => xsdb_addr_2_0_p2(1),
I5 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(2)
);
\Bus_data_out[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(3),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(3),
O => \data_info_probe_in__67\(3)
);
\Bus_data_out[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(4),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(4),
O => \data_info_probe_in__67\(4)
);
\Bus_data_out[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(5),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(5),
O => \data_info_probe_in__67\(5)
);
\Bus_data_out[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(6),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(6),
O => \data_info_probe_in__67\(6)
);
\Bus_data_out[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(7),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(7),
O => \data_info_probe_in__67\(7)
);
\Bus_data_out[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(8),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(8),
O => \data_info_probe_in__67\(8)
);
\Bus_data_out[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(9),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(9),
O => \data_info_probe_in__67\(9)
);
\Bus_data_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(0),
Q => s_do_i(0),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(10),
Q => s_do_i(10),
R => xsdb_addr_8_p2
);
\bus_data_out_reg[11]_RnM\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(11),
Q => s_do_i(11),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(12),
Q => s_do_i(12),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(13),
Q => s_do_i(13),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(14),
Q => s_do_i(14),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(15),
Q => s_do_i(15),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(1),
Q => s_do_i(1),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(2),
Q => s_do_i(2),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(3),
Q => s_do_i(3),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(4),
Q => s_do_i(4),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(5),
Q => s_do_i(5),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(6),
Q => s_do_i(6),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(7),
Q => s_do_i(7),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(8),
Q => s_do_i(8),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(9),
Q => s_do_i(9),
R => xsdb_addr_8_p2
);
Hold_probe_in_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(3),
Q => Hold_probe_in,
R => s_rst_o
);
clear_int_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(1),
Q => clear_int,
R => s_rst_o
);
committ_int_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(0),
Q => committ_int,
R => s_rst_o
);
int_cnt_rst_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(2),
Q => int_cnt_rst,
R => s_rst_o
);
\probe_in_reg[3]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => Hold_probe_in,
O => E(0)
);
\probe_out_modified_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(0),
Q => probe_out_modified(0),
R => clear_int
);
\probe_out_modified_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(10),
Q => probe_out_modified(10),
R => clear_int
);
\probe_out_modified_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(11),
Q => probe_out_modified(11),
R => clear_int
);
\probe_out_modified_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(12),
Q => probe_out_modified(12),
R => clear_int
);
\probe_out_modified_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(13),
Q => probe_out_modified(13),
R => clear_int
);
\probe_out_modified_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(14),
Q => probe_out_modified(14),
R => clear_int
);
\probe_out_modified_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(15),
Q => probe_out_modified(15),
R => clear_int
);
\probe_out_modified_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(1),
Q => probe_out_modified(1),
R => clear_int
);
\probe_out_modified_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(2),
Q => probe_out_modified(2),
R => clear_int
);
\probe_out_modified_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(3),
Q => probe_out_modified(3),
R => clear_int
);
\probe_out_modified_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(4),
Q => probe_out_modified(4),
R => clear_int
);
\probe_out_modified_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(5),
Q => probe_out_modified(5),
R => clear_int
);
\probe_out_modified_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(6),
Q => probe_out_modified(6),
R => clear_int
);
\probe_out_modified_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(7),
Q => probe_out_modified(7),
R => clear_int
);
\probe_out_modified_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(8),
Q => probe_out_modified(8),
R => clear_int
);
\probe_out_modified_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(9),
Q => probe_out_modified(9),
R => clear_int
);
rd_en_p1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_den_o,
I1 => s_dwe_o,
O => xsdb_rd
);
rd_en_p1_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_rd,
Q => rd_en_p1,
R => s_rst_o
);
rd_en_p2_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => rd_en_p1,
Q => rd_en_p2,
R => s_rst_o
);
\wr_en[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => xsdb_wr,
I1 => s_daddr_o(2),
I2 => \^wr_en_reg[4]_0\,
I3 => \^wr_en_reg[4]_2\,
I4 => \^wr_en_reg[4]_1\,
I5 => \wr_en[2]_i_2_n_0\,
O => \wr_en[2]_i_1_n_0\
);
\wr_en[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_daddr_o(0),
I1 => s_daddr_o(1),
O => \wr_en[2]_i_2_n_0\
);
\wr_en[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000020000"
)
port map (
I0 => xsdb_wr,
I1 => \^wr_en_reg[4]_0\,
I2 => \^wr_en_reg[4]_2\,
I3 => \^wr_en_reg[4]_1\,
I4 => s_daddr_o(2),
I5 => \wr_en[4]_i_6_n_0\,
O => \wr_en[4]_i_1_n_0\
);
\wr_en[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_den_o,
I1 => s_dwe_o,
O => xsdb_wr
);
\wr_en[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => s_daddr_o(15),
I1 => s_daddr_o(16),
I2 => s_daddr_o(13),
I3 => s_daddr_o(14),
I4 => s_daddr_o(4),
I5 => s_daddr_o(3),
O => \^wr_en_reg[4]_0\
);
\wr_en[4]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_daddr_o(6),
I1 => s_daddr_o(5),
I2 => s_daddr_o(8),
I3 => s_daddr_o(7),
O => \^wr_en_reg[4]_2\
);
\wr_en[4]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_daddr_o(10),
I1 => s_daddr_o(9),
I2 => s_daddr_o(12),
I3 => s_daddr_o(11),
O => \^wr_en_reg[4]_1\
);
\wr_en[4]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_daddr_o(0),
I1 => s_daddr_o(1),
O => \wr_en[4]_i_6_n_0\
);
\wr_en_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \wr_en[2]_i_1_n_0\,
Q => wr_control_reg,
R => '0'
);
\wr_en_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \wr_en[4]_i_1_n_0\,
Q => wr_probe_out_modified,
R => '0'
);
\xsdb_addr_2_0_p1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(0),
Q => xsdb_addr_2_0_p1(0),
R => '0'
);
\xsdb_addr_2_0_p1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(1),
Q => xsdb_addr_2_0_p1(1),
R => '0'
);
\xsdb_addr_2_0_p1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(2),
Q => xsdb_addr_2_0_p1(2),
R => '0'
);
\xsdb_addr_2_0_p2_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_2_0_p1(0),
Q => xsdb_addr_2_0_p2(0),
R => '0'
);
\xsdb_addr_2_0_p2_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_2_0_p1(1),
Q => xsdb_addr_2_0_p2(1),
R => '0'
);
\xsdb_addr_2_0_p2_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_2_0_p1(2),
Q => xsdb_addr_2_0_p2(2),
R => '0'
);
xsdb_addr_8_p1_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(8),
Q => xsdb_addr_8_p1,
R => '0'
);
xsdb_addr_8_p2_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_8_p1,
Q => xsdb_addr_8_p2,
R => '0'
);
xsdb_drdy_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => s_dwe_o,
I1 => s_den_o,
I2 => rd_en_p2,
O => xsdb_drdy_i_1_n_0
);
xsdb_drdy_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_drdy_i_1_n_0,
Q => s_drdy_i,
R => s_rst_o
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one is
port (
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
\out\ : in STD_LOGIC;
\wr_en[4]_i_3\ : in STD_LOGIC;
\wr_en[4]_i_4\ : in STD_LOGIC;
\wr_en[4]_i_5\ : in STD_LOGIC;
s_daddr_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_dwe_o : in STD_LOGIC;
s_den_o : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
s_rst_o : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one is
signal \DECODER_INST/rd_en_int_7\ : STD_LOGIC;
signal Read_int : STD_LOGIC;
signal Read_int_i_2_n_0 : STD_LOGIC;
signal data_int_sync1 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of data_int_sync1 : signal is "true";
signal data_int_sync2 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg of data_int_sync2 : signal is "true";
signal \dn_activity[0]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity[1]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity[2]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity[3]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity_reg_n_0_[0]\ : STD_LOGIC;
signal \dn_activity_reg_n_0_[3]\ : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_9_in : STD_LOGIC;
signal probe_in_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of probe_in_reg : signal is std.standard.true;
signal read_done : STD_LOGIC;
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of read_done : signal is "200";
attribute RTL_MAX_FANOUT : string;
attribute RTL_MAX_FANOUT of read_done : signal is "found";
signal read_done_i_1_n_0 : STD_LOGIC;
signal \up_activity[0]_i_1_n_0\ : STD_LOGIC;
signal \up_activity[1]_i_1_n_0\ : STD_LOGIC;
signal \up_activity[2]_i_1_n_0\ : STD_LOGIC;
signal \up_activity[3]_i_1_n_0\ : STD_LOGIC;
signal \up_activity_reg_n_0_[0]\ : STD_LOGIC;
signal \up_activity_reg_n_0_[1]\ : STD_LOGIC;
signal \up_activity_reg_n_0_[2]\ : STD_LOGIC;
signal \up_activity_reg_n_0_[3]\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \data_int_sync1_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \data_int_sync1_reg[0]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync1_reg[1]\ : label is std.standard.true;
attribute KEEP of \data_int_sync1_reg[1]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync1_reg[2]\ : label is std.standard.true;
attribute KEEP of \data_int_sync1_reg[2]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync1_reg[3]\ : label is std.standard.true;
attribute KEEP of \data_int_sync1_reg[3]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[0]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[0]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[1]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[1]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[2]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[2]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[3]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[3]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[0]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[1]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[2]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[3]\ : label is "yes";
attribute RTL_MAX_FANOUT of read_done_reg : label is "found";
begin
\Bus_Data_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(0),
Q => Q(0),
R => '0'
);
\Bus_Data_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_9_in,
Q => Q(10),
R => '0'
);
\Bus_Data_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \dn_activity_reg_n_0_[3]\,
Q => Q(11),
R => '0'
);
\Bus_Data_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(1),
Q => Q(1),
R => '0'
);
\Bus_Data_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(2),
Q => Q(2),
R => '0'
);
\Bus_Data_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(3),
Q => Q(3),
R => '0'
);
\Bus_Data_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[0]\,
Q => Q(4),
R => '0'
);
\Bus_Data_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[1]\,
Q => Q(5),
R => '0'
);
\Bus_Data_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[2]\,
Q => Q(6),
R => '0'
);
\Bus_Data_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[3]\,
Q => Q(7),
R => '0'
);
\Bus_Data_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \dn_activity_reg_n_0_[0]\,
Q => Q(8),
R => '0'
);
\Bus_Data_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_6_in,
Q => Q(9),
R => '0'
);
Read_int_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => Read_int_i_2_n_0,
I1 => \wr_en[4]_i_3\,
I2 => \wr_en[4]_i_4\,
I3 => \wr_en[4]_i_5\,
O => \DECODER_INST/rd_en_int_7\
);
Read_int_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => s_daddr_o(0),
I1 => s_daddr_o(1),
I2 => s_daddr_o(2),
I3 => s_dwe_o,
I4 => s_den_o,
O => Read_int_i_2_n_0
);
Read_int_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \DECODER_INST/rd_en_int_7\,
Q => Read_int,
R => '0'
);
\data_int_sync1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(0),
Q => data_int_sync1(0),
R => '0'
);
\data_int_sync1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(1),
Q => data_int_sync1(1),
R => '0'
);
\data_int_sync1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(2),
Q => data_int_sync1(2),
R => '0'
);
\data_int_sync1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(3),
Q => data_int_sync1(3),
R => '0'
);
\data_int_sync2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(0),
Q => data_int_sync2(0),
R => '0'
);
\data_int_sync2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(1),
Q => data_int_sync2(1),
R => '0'
);
\data_int_sync2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(2),
Q => data_int_sync2(2),
R => '0'
);
\data_int_sync2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(3),
Q => data_int_sync2(3),
R => '0'
);
\dn_activity[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \dn_activity_reg_n_0_[0]\,
I1 => data_int_sync1(0),
I2 => data_int_sync2(0),
O => \dn_activity[0]_i_1_n_0\
);
\dn_activity[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => p_6_in,
I1 => data_int_sync1(1),
I2 => data_int_sync2(1),
O => \dn_activity[1]_i_1_n_0\
);
\dn_activity[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => p_9_in,
I1 => data_int_sync1(2),
I2 => data_int_sync2(2),
O => \dn_activity[2]_i_1_n_0\
);
\dn_activity[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \dn_activity_reg_n_0_[3]\,
I1 => data_int_sync1(3),
I2 => data_int_sync2(3),
O => \dn_activity[3]_i_1_n_0\
);
\dn_activity_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[0]_i_1_n_0\,
Q => \dn_activity_reg_n_0_[0]\,
R => read_done
);
\dn_activity_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[1]_i_1_n_0\,
Q => p_6_in,
R => read_done
);
\dn_activity_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[2]_i_1_n_0\,
Q => p_9_in,
R => read_done
);
\dn_activity_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[3]_i_1_n_0\,
Q => \dn_activity_reg_n_0_[3]\,
R => read_done
);
\probe_in_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(0),
Q => probe_in_reg(0),
R => '0'
);
\probe_in_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(1),
Q => probe_in_reg(1),
R => '0'
);
\probe_in_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(2),
Q => probe_in_reg(2),
R => '0'
);
\probe_in_reg_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(3),
Q => probe_in_reg(3),
R => '0'
);
read_done_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => Read_int,
I1 => read_done,
I2 => s_rst_o,
O => read_done_i_1_n_0
);
read_done_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => read_done_i_1_n_0,
Q => read_done,
R => '0'
);
\up_activity[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[0]\,
I1 => data_int_sync2(0),
I2 => data_int_sync1(0),
O => \up_activity[0]_i_1_n_0\
);
\up_activity[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[1]\,
I1 => data_int_sync2(1),
I2 => data_int_sync1(1),
O => \up_activity[1]_i_1_n_0\
);
\up_activity[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[2]\,
I1 => data_int_sync2(2),
I2 => data_int_sync1(2),
O => \up_activity[2]_i_1_n_0\
);
\up_activity[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[3]\,
I1 => data_int_sync2(3),
I2 => data_int_sync1(3),
O => \up_activity[3]_i_1_n_0\
);
\up_activity_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[0]_i_1_n_0\,
Q => \up_activity_reg_n_0_[0]\,
R => read_done
);
\up_activity_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[1]_i_1_n_0\,
Q => \up_activity_reg_n_0_[1]\,
R => read_done
);
\up_activity_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[2]_i_1_n_0\,
Q => \up_activity_reg_n_0_[2]\,
R => read_done
);
\up_activity_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[3]_i_1_n_0\,
Q => \up_activity_reg_n_0_[3]\,
R => read_done
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs is
port (
s_rst_o : out STD_LOGIC;
s_dclk_o : out STD_LOGIC;
s_den_o : out STD_LOGIC;
s_dwe_o : out STD_LOGIC;
s_daddr_o : out STD_LOGIC_VECTOR ( 16 downto 0 );
s_di_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
sl_oport_o : out STD_LOGIC_VECTOR ( 16 downto 0 );
s_do_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
sl_iport_i : in STD_LOGIC_VECTOR ( 36 downto 0 );
s_drdy_i : in STD_LOGIC
);
attribute C_BUILD_REVISION : integer;
attribute C_BUILD_REVISION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_CORE_INFO1 : string;
attribute C_CORE_INFO1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 : string;
attribute C_CORE_INFO2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER : integer;
attribute C_CORE_MAJOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 2;
attribute C_CORE_MINOR_VER : integer;
attribute C_CORE_MINOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_CORE_TYPE : integer;
attribute C_CORE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 2;
attribute C_CSE_DRV_VER : integer;
attribute C_CSE_DRV_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 1;
attribute C_MAJOR_VERSION : integer;
attribute C_MAJOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 2013;
attribute C_MINOR_VERSION : integer;
attribute C_MINOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 1;
attribute C_NEXT_SLAVE : integer;
attribute C_NEXT_SLAVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_PIPE_IFACE : integer;
attribute C_PIPE_IFACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_USE_TEST_REG : integer;
attribute C_USE_TEST_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 1;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "kintex7";
attribute C_XSDB_SLAVE_TYPE : integer;
attribute C_XSDB_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 33;
attribute dont_touch : string;
attribute dont_touch of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "true";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs is
signal reg_do : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \reg_do[10]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[10]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[15]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[1]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[2]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[3]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[4]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[5]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[6]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[7]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[8]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[9]_i_1_n_0\ : STD_LOGIC;
signal \reg_do_reg_n_0_[0]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[10]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[11]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[12]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[13]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[14]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[15]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[1]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[2]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[3]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[4]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[5]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[6]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[7]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[8]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[9]\ : STD_LOGIC;
signal reg_drdy : STD_LOGIC;
signal reg_drdy_i_1_n_0 : STD_LOGIC;
signal reg_test : STD_LOGIC_VECTOR ( 15 downto 0 );
signal reg_test0 : STD_LOGIC;
signal s_den_o_INST_0_i_1_n_0 : STD_LOGIC;
signal \^sl_iport_i\ : STD_LOGIC_VECTOR ( 36 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \reg_do[10]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \reg_do[1]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \reg_do[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \reg_do[3]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \reg_do[4]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \reg_do[5]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \reg_do[6]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \reg_do[7]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \sl_oport_o[0]_INST_0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \sl_oport_o[10]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \sl_oport_o[11]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \sl_oport_o[12]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \sl_oport_o[13]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \sl_oport_o[14]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \sl_oport_o[15]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \sl_oport_o[1]_INST_0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \sl_oport_o[2]_INST_0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \sl_oport_o[3]_INST_0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \sl_oport_o[4]_INST_0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \sl_oport_o[5]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \sl_oport_o[6]_INST_0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \sl_oport_o[7]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \sl_oport_o[8]_INST_0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \sl_oport_o[9]_INST_0\ : label is "soft_lutpair8";
begin
\^sl_iport_i\(36 downto 0) <= sl_iport_i(36 downto 0);
s_daddr_o(16 downto 0) <= \^sl_iport_i\(20 downto 4);
s_dclk_o <= \^sl_iport_i\(1);
s_di_o(15 downto 0) <= \^sl_iport_i\(36 downto 21);
s_dwe_o <= \^sl_iport_i\(3);
s_rst_o <= \^sl_iport_i\(0);
\reg_do[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BAAAFFFFAAAAAAAA"
)
port map (
I0 => \reg_do[5]_i_2_n_0\,
I1 => \^sl_iport_i\(4),
I2 => reg_test(0),
I3 => \^sl_iport_i\(6),
I4 => \^sl_iport_i\(5),
I5 => \^sl_iport_i\(8),
O => reg_do(0)
);
\reg_do[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^sl_iport_i\(5),
I1 => \reg_do[8]_i_2_n_0\,
I2 => \^sl_iport_i\(4),
O => \reg_do[10]_i_1_n_0\
);
\reg_do[10]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(10),
O => \reg_do[10]_i_2_n_0\
);
\reg_do[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F7"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
O => \reg_do[15]_i_1_n_0\
);
\reg_do[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20220000"
)
port map (
I0 => \^sl_iport_i\(5),
I1 => \^sl_iport_i\(4),
I2 => reg_test(1),
I3 => \^sl_iport_i\(6),
I4 => \reg_do[1]_i_2_n_0\,
O => reg_do(1)
);
\reg_do[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => \^sl_iport_i\(8),
I1 => \^sl_iport_i\(10),
I2 => \^sl_iport_i\(11),
I3 => \^sl_iport_i\(7),
I4 => \^sl_iport_i\(9),
O => \reg_do[1]_i_2_n_0\
);
\reg_do[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(2),
O => \reg_do[2]_i_1_n_0\
);
\reg_do[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(3),
O => \reg_do[3]_i_1_n_0\
);
\reg_do[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(4),
O => \reg_do[4]_i_1_n_0\
);
\reg_do[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00800044"
)
port map (
I0 => \^sl_iport_i\(6),
I1 => \^sl_iport_i\(8),
I2 => reg_test(5),
I3 => \^sl_iport_i\(4),
I4 => \^sl_iport_i\(5),
I5 => \reg_do[5]_i_2_n_0\,
O => reg_do(5)
);
\reg_do[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFFFFC"
)
port map (
I0 => \^sl_iport_i\(7),
I1 => \^sl_iport_i\(8),
I2 => \^sl_iport_i\(11),
I3 => \^sl_iport_i\(10),
I4 => \^sl_iport_i\(9),
O => \reg_do[5]_i_2_n_0\
);
\reg_do[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(6),
O => \reg_do[6]_i_1_n_0\
);
\reg_do[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(7),
O => \reg_do[7]_i_1_n_0\
);
\reg_do[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F00"
)
port map (
I0 => reg_test(8),
I1 => \^sl_iport_i\(4),
I2 => \^sl_iport_i\(5),
I3 => \reg_do[8]_i_2_n_0\,
O => reg_do(8)
);
\reg_do[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000000000"
)
port map (
I0 => \^sl_iport_i\(9),
I1 => \^sl_iport_i\(7),
I2 => \^sl_iport_i\(11),
I3 => \^sl_iport_i\(10),
I4 => \^sl_iport_i\(8),
I5 => \^sl_iport_i\(6),
O => \reg_do[8]_i_2_n_0\
);
\reg_do[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0C008000"
)
port map (
I0 => reg_test(9),
I1 => \reg_do[1]_i_2_n_0\,
I2 => \^sl_iport_i\(6),
I3 => \^sl_iport_i\(5),
I4 => \^sl_iport_i\(4),
O => \reg_do[9]_i_1_n_0\
);
\reg_do_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(0),
Q => \reg_do_reg_n_0_[0]\,
R => '0'
);
\reg_do_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[10]_i_2_n_0\,
Q => \reg_do_reg_n_0_[10]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(11),
Q => \reg_do_reg_n_0_[11]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(12),
Q => \reg_do_reg_n_0_[12]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(13),
Q => \reg_do_reg_n_0_[13]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(14),
Q => \reg_do_reg_n_0_[14]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(15),
Q => \reg_do_reg_n_0_[15]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(1),
Q => \reg_do_reg_n_0_[1]\,
R => '0'
);
\reg_do_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[2]_i_1_n_0\,
Q => \reg_do_reg_n_0_[2]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[3]_i_1_n_0\,
Q => \reg_do_reg_n_0_[3]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[4]_i_1_n_0\,
Q => \reg_do_reg_n_0_[4]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(5),
Q => \reg_do_reg_n_0_[5]\,
R => '0'
);
\reg_do_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[6]_i_1_n_0\,
Q => \reg_do_reg_n_0_[6]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[7]_i_1_n_0\,
Q => \reg_do_reg_n_0_[7]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(8),
Q => \reg_do_reg_n_0_[8]\,
R => '0'
);
\reg_do_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[9]_i_1_n_0\,
Q => \reg_do_reg_n_0_[9]\,
S => \reg_do[10]_i_1_n_0\
);
reg_drdy_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => \^sl_iport_i\(2),
I1 => s_den_o_INST_0_i_1_n_0,
I2 => \^sl_iport_i\(12),
I3 => \^sl_iport_i\(13),
I4 => \^sl_iport_i\(14),
I5 => \^sl_iport_i\(0),
O => reg_drdy_i_1_n_0
);
reg_drdy_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_drdy_i_1_n_0,
Q => reg_drdy,
R => '0'
);
\reg_test[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^sl_iport_i\(3),
I1 => \^sl_iport_i\(2),
I2 => \^sl_iport_i\(14),
I3 => \^sl_iport_i\(13),
I4 => \^sl_iport_i\(12),
I5 => s_den_o_INST_0_i_1_n_0,
O => reg_test0
);
\reg_test_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(21),
Q => reg_test(0),
R => '0'
);
\reg_test_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(31),
Q => reg_test(10),
R => '0'
);
\reg_test_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(32),
Q => reg_test(11),
R => '0'
);
\reg_test_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(33),
Q => reg_test(12),
R => '0'
);
\reg_test_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(34),
Q => reg_test(13),
R => '0'
);
\reg_test_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(35),
Q => reg_test(14),
R => '0'
);
\reg_test_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(36),
Q => reg_test(15),
R => '0'
);
\reg_test_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(22),
Q => reg_test(1),
R => '0'
);
\reg_test_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(23),
Q => reg_test(2),
R => '0'
);
\reg_test_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(24),
Q => reg_test(3),
R => '0'
);
\reg_test_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(25),
Q => reg_test(4),
R => '0'
);
\reg_test_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(26),
Q => reg_test(5),
R => '0'
);
\reg_test_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(27),
Q => reg_test(6),
R => '0'
);
\reg_test_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(28),
Q => reg_test(7),
R => '0'
);
\reg_test_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(29),
Q => reg_test(8),
R => '0'
);
\reg_test_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(30),
Q => reg_test(9),
R => '0'
);
s_den_o_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"2AAAAAAA"
)
port map (
I0 => \^sl_iport_i\(2),
I1 => \^sl_iport_i\(14),
I2 => \^sl_iport_i\(13),
I3 => \^sl_iport_i\(12),
I4 => s_den_o_INST_0_i_1_n_0,
O => s_den_o
);
s_den_o_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^sl_iport_i\(15),
I1 => \^sl_iport_i\(16),
I2 => \^sl_iport_i\(17),
I3 => \^sl_iport_i\(18),
I4 => \^sl_iport_i\(20),
I5 => \^sl_iport_i\(19),
O => s_den_o_INST_0_i_1_n_0
);
\sl_oport_o[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_drdy_i,
I1 => reg_drdy,
O => sl_oport_o(0)
);
\sl_oport_o[10]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[9]\,
I1 => s_do_i(9),
I2 => reg_drdy,
O => sl_oport_o(10)
);
\sl_oport_o[11]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[10]\,
I1 => s_do_i(10),
I2 => reg_drdy,
O => sl_oport_o(11)
);
\sl_oport_o[12]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[11]\,
I1 => s_do_i(11),
I2 => reg_drdy,
O => sl_oport_o(12)
);
\sl_oport_o[13]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[12]\,
I1 => s_do_i(12),
I2 => reg_drdy,
O => sl_oport_o(13)
);
\sl_oport_o[14]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[13]\,
I1 => s_do_i(13),
I2 => reg_drdy,
O => sl_oport_o(14)
);
\sl_oport_o[15]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[14]\,
I1 => s_do_i(14),
I2 => reg_drdy,
O => sl_oport_o(15)
);
\sl_oport_o[16]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[15]\,
I1 => s_do_i(15),
I2 => reg_drdy,
O => sl_oport_o(16)
);
\sl_oport_o[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[0]\,
I1 => s_do_i(0),
I2 => reg_drdy,
O => sl_oport_o(1)
);
\sl_oport_o[2]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[1]\,
I1 => s_do_i(1),
I2 => reg_drdy,
O => sl_oport_o(2)
);
\sl_oport_o[3]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[2]\,
I1 => s_do_i(2),
I2 => reg_drdy,
O => sl_oport_o(3)
);
\sl_oport_o[4]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[3]\,
I1 => s_do_i(3),
I2 => reg_drdy,
O => sl_oport_o(4)
);
\sl_oport_o[5]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[4]\,
I1 => s_do_i(4),
I2 => reg_drdy,
O => sl_oport_o(5)
);
\sl_oport_o[6]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[5]\,
I1 => s_do_i(5),
I2 => reg_drdy,
O => sl_oport_o(6)
);
\sl_oport_o[7]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[6]\,
I1 => s_do_i(6),
I2 => reg_drdy,
O => sl_oport_o(7)
);
\sl_oport_o[8]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[7]\,
I1 => s_do_i(7),
I2 => reg_drdy,
O => sl_oport_o(8)
);
\sl_oport_o[9]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[8]\,
I1 => s_do_i(8),
I2 => reg_drdy,
O => sl_oport_o(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio is
port (
clk : in STD_LOGIC;
probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in5 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in6 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in7 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in8 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in9 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in10 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in11 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in12 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in13 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in14 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in15 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in16 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in17 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in18 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in19 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in20 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in21 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in22 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in23 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in24 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in25 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in26 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in27 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in28 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in29 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in30 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in31 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in32 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in33 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in34 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in35 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in36 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in37 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in38 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in39 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in40 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in41 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in42 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in43 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in44 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in45 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in46 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in47 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in48 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in49 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in50 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in51 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in52 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in53 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in54 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in55 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in56 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in57 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in58 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in59 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in60 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in61 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in62 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in63 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in64 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in65 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in66 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in67 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in68 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in69 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in70 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in71 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in72 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in73 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in74 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in75 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in76 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in77 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in78 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in79 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in80 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in81 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in82 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in83 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in84 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in85 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in86 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in87 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in88 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in89 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in90 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in91 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in92 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in93 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in94 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in95 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in96 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in97 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in98 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in99 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in100 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in101 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in102 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in103 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in104 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in105 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in106 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in107 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in108 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in109 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in110 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in111 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in112 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in113 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in114 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in115 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in116 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in117 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in118 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in119 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in120 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in121 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in122 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in123 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in124 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in125 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in126 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in127 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in128 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in129 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in130 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in131 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in132 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in133 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in134 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in135 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in136 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in137 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in138 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in139 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in140 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in141 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in142 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in143 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in144 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in145 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in146 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in147 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in148 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in149 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in150 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in151 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in152 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in153 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in154 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in155 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in156 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in157 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in158 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in159 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in160 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in161 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in162 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in163 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in164 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in165 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in166 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in167 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in168 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in169 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in170 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in171 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in172 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in173 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in174 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in175 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in176 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in177 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in178 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in179 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in180 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in181 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in182 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in183 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in184 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in185 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in186 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in187 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in188 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in189 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in190 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in191 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in192 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in193 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in194 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in195 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in196 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in197 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in198 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in199 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in200 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in201 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in202 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in203 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in204 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in205 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in206 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in207 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in208 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in209 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in210 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in211 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in212 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in213 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in214 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in215 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in216 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in217 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in218 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in219 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in220 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in221 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in222 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in223 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in224 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in225 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in226 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in227 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in228 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in229 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in230 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in231 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in232 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in233 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in234 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in235 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in236 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in237 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in238 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in239 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in240 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in241 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in242 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in243 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in244 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in245 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in246 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in247 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in248 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in249 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in250 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in251 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in252 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in253 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in254 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in255 : in STD_LOGIC_VECTOR ( 0 to 0 );
sl_iport0 : in STD_LOGIC_VECTOR ( 36 downto 0 );
sl_oport0 : out STD_LOGIC_VECTOR ( 16 downto 0 );
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out3 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out13 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out15 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out16 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out17 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out18 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out19 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out20 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out21 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out22 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out23 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out24 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out25 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out26 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out27 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out28 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out29 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out30 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out31 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out32 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out33 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out34 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out35 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out36 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out37 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out38 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out39 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out40 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out41 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out42 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out43 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out44 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out45 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out46 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out47 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out48 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out49 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out50 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out51 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out52 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out53 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out54 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out55 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out56 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out57 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out58 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out59 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out60 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out61 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out62 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out63 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out64 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out65 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out66 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out67 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out68 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out69 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out70 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out71 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out72 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out73 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out74 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out75 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out76 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out77 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out78 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out79 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out80 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out81 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out82 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out83 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out84 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out85 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out86 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out87 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out88 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out89 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out90 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out91 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out92 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out93 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out94 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out95 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out96 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out97 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out98 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out99 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out100 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out101 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out102 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out103 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out104 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out105 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out106 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out107 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out108 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out109 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out110 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out111 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out112 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out113 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out114 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out115 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out116 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out117 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out118 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out119 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out120 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out121 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out122 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out123 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out124 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out125 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out126 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out127 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out128 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out129 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out130 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out131 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out132 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out133 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out134 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out135 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out136 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out137 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out138 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out139 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out140 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out141 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out142 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out143 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out144 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out145 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out146 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out147 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out148 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out149 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out150 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out151 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out152 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out153 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out154 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out155 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out156 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out157 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out158 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out159 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out160 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out161 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out162 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out163 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out164 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out165 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out166 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out167 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out168 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out169 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out170 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out171 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out172 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out173 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out174 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out175 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out176 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out177 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out178 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out179 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out180 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out181 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out182 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out183 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out184 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out185 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out186 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out187 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out188 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out189 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out190 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out191 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out192 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out193 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out194 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out195 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out196 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out197 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out198 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out199 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out200 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out201 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out202 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out203 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out204 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out205 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out206 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out207 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out208 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out209 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out210 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out211 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out212 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out213 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out214 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out215 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out216 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out217 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out218 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out219 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out220 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out221 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out222 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out223 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out224 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out225 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out226 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out227 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out228 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out229 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out230 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out231 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out232 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out233 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out234 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out235 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out236 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out237 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out238 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out239 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out240 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out241 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out242 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out243 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out244 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out245 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out246 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out247 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out248 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out249 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out250 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out251 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out252 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out253 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out254 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out255 : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_BUILD_REVISION : integer;
attribute C_BUILD_REVISION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_BUS_ADDR_WIDTH : integer;
attribute C_BUS_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 17;
attribute C_BUS_DATA_WIDTH : integer;
attribute C_BUS_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 16;
attribute C_CORE_INFO1 : string;
attribute C_CORE_INFO1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 : string;
attribute C_CORE_INFO2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER : integer;
attribute C_CORE_MAJOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 2;
attribute C_CORE_MINOR_ALPHA_VER : integer;
attribute C_CORE_MINOR_ALPHA_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 97;
attribute C_CORE_MINOR_VER : integer;
attribute C_CORE_MINOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_CORE_TYPE : integer;
attribute C_CORE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 2;
attribute C_CSE_DRV_VER : integer;
attribute C_CSE_DRV_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_EN_PROBE_IN_ACTIVITY : integer;
attribute C_EN_PROBE_IN_ACTIVITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_EN_SYNCHRONIZATION : integer;
attribute C_EN_SYNCHRONIZATION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_MAJOR_VERSION : integer;
attribute C_MAJOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 2013;
attribute C_MAX_NUM_PROBE : integer;
attribute C_MAX_NUM_PROBE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 256;
attribute C_MAX_WIDTH_PER_PROBE : integer;
attribute C_MAX_WIDTH_PER_PROBE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 256;
attribute C_MINOR_VERSION : integer;
attribute C_MINOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_NEXT_SLAVE : integer;
attribute C_NEXT_SLAVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_NUM_PROBE_IN : integer;
attribute C_NUM_PROBE_IN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 4;
attribute C_NUM_PROBE_OUT : integer;
attribute C_NUM_PROBE_OUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_PIPE_IFACE : integer;
attribute C_PIPE_IFACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_PROBE_IN0_WIDTH : integer;
attribute C_PROBE_IN0_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN100_WIDTH : integer;
attribute C_PROBE_IN100_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN101_WIDTH : integer;
attribute C_PROBE_IN101_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN102_WIDTH : integer;
attribute C_PROBE_IN102_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN103_WIDTH : integer;
attribute C_PROBE_IN103_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN104_WIDTH : integer;
attribute C_PROBE_IN104_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN105_WIDTH : integer;
attribute C_PROBE_IN105_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN106_WIDTH : integer;
attribute C_PROBE_IN106_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN107_WIDTH : integer;
attribute C_PROBE_IN107_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN108_WIDTH : integer;
attribute C_PROBE_IN108_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN109_WIDTH : integer;
attribute C_PROBE_IN109_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN10_WIDTH : integer;
attribute C_PROBE_IN10_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN110_WIDTH : integer;
attribute C_PROBE_IN110_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN111_WIDTH : integer;
attribute C_PROBE_IN111_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN112_WIDTH : integer;
attribute C_PROBE_IN112_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN113_WIDTH : integer;
attribute C_PROBE_IN113_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN114_WIDTH : integer;
attribute C_PROBE_IN114_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN115_WIDTH : integer;
attribute C_PROBE_IN115_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN116_WIDTH : integer;
attribute C_PROBE_IN116_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN117_WIDTH : integer;
attribute C_PROBE_IN117_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN118_WIDTH : integer;
attribute C_PROBE_IN118_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN119_WIDTH : integer;
attribute C_PROBE_IN119_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN11_WIDTH : integer;
attribute C_PROBE_IN11_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN120_WIDTH : integer;
attribute C_PROBE_IN120_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN121_WIDTH : integer;
attribute C_PROBE_IN121_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN122_WIDTH : integer;
attribute C_PROBE_IN122_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN123_WIDTH : integer;
attribute C_PROBE_IN123_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN124_WIDTH : integer;
attribute C_PROBE_IN124_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN125_WIDTH : integer;
attribute C_PROBE_IN125_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN126_WIDTH : integer;
attribute C_PROBE_IN126_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN127_WIDTH : integer;
attribute C_PROBE_IN127_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN128_WIDTH : integer;
attribute C_PROBE_IN128_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN129_WIDTH : integer;
attribute C_PROBE_IN129_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN12_WIDTH : integer;
attribute C_PROBE_IN12_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN130_WIDTH : integer;
attribute C_PROBE_IN130_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN131_WIDTH : integer;
attribute C_PROBE_IN131_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN132_WIDTH : integer;
attribute C_PROBE_IN132_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN133_WIDTH : integer;
attribute C_PROBE_IN133_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN134_WIDTH : integer;
attribute C_PROBE_IN134_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN135_WIDTH : integer;
attribute C_PROBE_IN135_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN136_WIDTH : integer;
attribute C_PROBE_IN136_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN137_WIDTH : integer;
attribute C_PROBE_IN137_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN138_WIDTH : integer;
attribute C_PROBE_IN138_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN139_WIDTH : integer;
attribute C_PROBE_IN139_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN13_WIDTH : integer;
attribute C_PROBE_IN13_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN140_WIDTH : integer;
attribute C_PROBE_IN140_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN141_WIDTH : integer;
attribute C_PROBE_IN141_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN142_WIDTH : integer;
attribute C_PROBE_IN142_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN143_WIDTH : integer;
attribute C_PROBE_IN143_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN144_WIDTH : integer;
attribute C_PROBE_IN144_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN145_WIDTH : integer;
attribute C_PROBE_IN145_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN146_WIDTH : integer;
attribute C_PROBE_IN146_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN147_WIDTH : integer;
attribute C_PROBE_IN147_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN148_WIDTH : integer;
attribute C_PROBE_IN148_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN149_WIDTH : integer;
attribute C_PROBE_IN149_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN14_WIDTH : integer;
attribute C_PROBE_IN14_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN150_WIDTH : integer;
attribute C_PROBE_IN150_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN151_WIDTH : integer;
attribute C_PROBE_IN151_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN152_WIDTH : integer;
attribute C_PROBE_IN152_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN153_WIDTH : integer;
attribute C_PROBE_IN153_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN154_WIDTH : integer;
attribute C_PROBE_IN154_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN155_WIDTH : integer;
attribute C_PROBE_IN155_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN156_WIDTH : integer;
attribute C_PROBE_IN156_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN157_WIDTH : integer;
attribute C_PROBE_IN157_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN158_WIDTH : integer;
attribute C_PROBE_IN158_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN159_WIDTH : integer;
attribute C_PROBE_IN159_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN15_WIDTH : integer;
attribute C_PROBE_IN15_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN160_WIDTH : integer;
attribute C_PROBE_IN160_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN161_WIDTH : integer;
attribute C_PROBE_IN161_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN162_WIDTH : integer;
attribute C_PROBE_IN162_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN163_WIDTH : integer;
attribute C_PROBE_IN163_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN164_WIDTH : integer;
attribute C_PROBE_IN164_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN165_WIDTH : integer;
attribute C_PROBE_IN165_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN166_WIDTH : integer;
attribute C_PROBE_IN166_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN167_WIDTH : integer;
attribute C_PROBE_IN167_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN168_WIDTH : integer;
attribute C_PROBE_IN168_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN169_WIDTH : integer;
attribute C_PROBE_IN169_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN16_WIDTH : integer;
attribute C_PROBE_IN16_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN170_WIDTH : integer;
attribute C_PROBE_IN170_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN171_WIDTH : integer;
attribute C_PROBE_IN171_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN172_WIDTH : integer;
attribute C_PROBE_IN172_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN173_WIDTH : integer;
attribute C_PROBE_IN173_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN174_WIDTH : integer;
attribute C_PROBE_IN174_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN175_WIDTH : integer;
attribute C_PROBE_IN175_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN176_WIDTH : integer;
attribute C_PROBE_IN176_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN177_WIDTH : integer;
attribute C_PROBE_IN177_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN178_WIDTH : integer;
attribute C_PROBE_IN178_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN179_WIDTH : integer;
attribute C_PROBE_IN179_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN17_WIDTH : integer;
attribute C_PROBE_IN17_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN180_WIDTH : integer;
attribute C_PROBE_IN180_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN181_WIDTH : integer;
attribute C_PROBE_IN181_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN182_WIDTH : integer;
attribute C_PROBE_IN182_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN183_WIDTH : integer;
attribute C_PROBE_IN183_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN184_WIDTH : integer;
attribute C_PROBE_IN184_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN185_WIDTH : integer;
attribute C_PROBE_IN185_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN186_WIDTH : integer;
attribute C_PROBE_IN186_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN187_WIDTH : integer;
attribute C_PROBE_IN187_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN188_WIDTH : integer;
attribute C_PROBE_IN188_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN189_WIDTH : integer;
attribute C_PROBE_IN189_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN18_WIDTH : integer;
attribute C_PROBE_IN18_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN190_WIDTH : integer;
attribute C_PROBE_IN190_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN191_WIDTH : integer;
attribute C_PROBE_IN191_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN192_WIDTH : integer;
attribute C_PROBE_IN192_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN193_WIDTH : integer;
attribute C_PROBE_IN193_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN194_WIDTH : integer;
attribute C_PROBE_IN194_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN195_WIDTH : integer;
attribute C_PROBE_IN195_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN196_WIDTH : integer;
attribute C_PROBE_IN196_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN197_WIDTH : integer;
attribute C_PROBE_IN197_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN198_WIDTH : integer;
attribute C_PROBE_IN198_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN199_WIDTH : integer;
attribute C_PROBE_IN199_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN19_WIDTH : integer;
attribute C_PROBE_IN19_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN1_WIDTH : integer;
attribute C_PROBE_IN1_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN200_WIDTH : integer;
attribute C_PROBE_IN200_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN201_WIDTH : integer;
attribute C_PROBE_IN201_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN202_WIDTH : integer;
attribute C_PROBE_IN202_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN203_WIDTH : integer;
attribute C_PROBE_IN203_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN204_WIDTH : integer;
attribute C_PROBE_IN204_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN205_WIDTH : integer;
attribute C_PROBE_IN205_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN206_WIDTH : integer;
attribute C_PROBE_IN206_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN207_WIDTH : integer;
attribute C_PROBE_IN207_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN208_WIDTH : integer;
attribute C_PROBE_IN208_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN209_WIDTH : integer;
attribute C_PROBE_IN209_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN20_WIDTH : integer;
attribute C_PROBE_IN20_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN210_WIDTH : integer;
attribute C_PROBE_IN210_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN211_WIDTH : integer;
attribute C_PROBE_IN211_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN212_WIDTH : integer;
attribute C_PROBE_IN212_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN213_WIDTH : integer;
attribute C_PROBE_IN213_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN214_WIDTH : integer;
attribute C_PROBE_IN214_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN215_WIDTH : integer;
attribute C_PROBE_IN215_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN216_WIDTH : integer;
attribute C_PROBE_IN216_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN217_WIDTH : integer;
attribute C_PROBE_IN217_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN218_WIDTH : integer;
attribute C_PROBE_IN218_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN219_WIDTH : integer;
attribute C_PROBE_IN219_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN21_WIDTH : integer;
attribute C_PROBE_IN21_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN220_WIDTH : integer;
attribute C_PROBE_IN220_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN221_WIDTH : integer;
attribute C_PROBE_IN221_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN222_WIDTH : integer;
attribute C_PROBE_IN222_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN223_WIDTH : integer;
attribute C_PROBE_IN223_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN224_WIDTH : integer;
attribute C_PROBE_IN224_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN225_WIDTH : integer;
attribute C_PROBE_IN225_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN226_WIDTH : integer;
attribute C_PROBE_IN226_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN227_WIDTH : integer;
attribute C_PROBE_IN227_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN228_WIDTH : integer;
attribute C_PROBE_IN228_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN229_WIDTH : integer;
attribute C_PROBE_IN229_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN22_WIDTH : integer;
attribute C_PROBE_IN22_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN230_WIDTH : integer;
attribute C_PROBE_IN230_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN231_WIDTH : integer;
attribute C_PROBE_IN231_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN232_WIDTH : integer;
attribute C_PROBE_IN232_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN233_WIDTH : integer;
attribute C_PROBE_IN233_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN234_WIDTH : integer;
attribute C_PROBE_IN234_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN235_WIDTH : integer;
attribute C_PROBE_IN235_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN236_WIDTH : integer;
attribute C_PROBE_IN236_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN237_WIDTH : integer;
attribute C_PROBE_IN237_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN238_WIDTH : integer;
attribute C_PROBE_IN238_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN239_WIDTH : integer;
attribute C_PROBE_IN239_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN23_WIDTH : integer;
attribute C_PROBE_IN23_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN240_WIDTH : integer;
attribute C_PROBE_IN240_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN241_WIDTH : integer;
attribute C_PROBE_IN241_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN242_WIDTH : integer;
attribute C_PROBE_IN242_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN243_WIDTH : integer;
attribute C_PROBE_IN243_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN244_WIDTH : integer;
attribute C_PROBE_IN244_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN245_WIDTH : integer;
attribute C_PROBE_IN245_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN246_WIDTH : integer;
attribute C_PROBE_IN246_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN247_WIDTH : integer;
attribute C_PROBE_IN247_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN248_WIDTH : integer;
attribute C_PROBE_IN248_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN249_WIDTH : integer;
attribute C_PROBE_IN249_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN24_WIDTH : integer;
attribute C_PROBE_IN24_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN250_WIDTH : integer;
attribute C_PROBE_IN250_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN251_WIDTH : integer;
attribute C_PROBE_IN251_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN252_WIDTH : integer;
attribute C_PROBE_IN252_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN253_WIDTH : integer;
attribute C_PROBE_IN253_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN254_WIDTH : integer;
attribute C_PROBE_IN254_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN255_WIDTH : integer;
attribute C_PROBE_IN255_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN25_WIDTH : integer;
attribute C_PROBE_IN25_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN26_WIDTH : integer;
attribute C_PROBE_IN26_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN27_WIDTH : integer;
attribute C_PROBE_IN27_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN28_WIDTH : integer;
attribute C_PROBE_IN28_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN29_WIDTH : integer;
attribute C_PROBE_IN29_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN2_WIDTH : integer;
attribute C_PROBE_IN2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN30_WIDTH : integer;
attribute C_PROBE_IN30_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN31_WIDTH : integer;
attribute C_PROBE_IN31_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN32_WIDTH : integer;
attribute C_PROBE_IN32_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN33_WIDTH : integer;
attribute C_PROBE_IN33_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN34_WIDTH : integer;
attribute C_PROBE_IN34_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN35_WIDTH : integer;
attribute C_PROBE_IN35_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN36_WIDTH : integer;
attribute C_PROBE_IN36_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN37_WIDTH : integer;
attribute C_PROBE_IN37_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN38_WIDTH : integer;
attribute C_PROBE_IN38_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN39_WIDTH : integer;
attribute C_PROBE_IN39_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN3_WIDTH : integer;
attribute C_PROBE_IN3_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN40_WIDTH : integer;
attribute C_PROBE_IN40_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN41_WIDTH : integer;
attribute C_PROBE_IN41_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN42_WIDTH : integer;
attribute C_PROBE_IN42_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN43_WIDTH : integer;
attribute C_PROBE_IN43_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN44_WIDTH : integer;
attribute C_PROBE_IN44_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN45_WIDTH : integer;
attribute C_PROBE_IN45_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN46_WIDTH : integer;
attribute C_PROBE_IN46_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN47_WIDTH : integer;
attribute C_PROBE_IN47_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN48_WIDTH : integer;
attribute C_PROBE_IN48_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN49_WIDTH : integer;
attribute C_PROBE_IN49_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN4_WIDTH : integer;
attribute C_PROBE_IN4_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN50_WIDTH : integer;
attribute C_PROBE_IN50_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN51_WIDTH : integer;
attribute C_PROBE_IN51_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN52_WIDTH : integer;
attribute C_PROBE_IN52_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN53_WIDTH : integer;
attribute C_PROBE_IN53_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN54_WIDTH : integer;
attribute C_PROBE_IN54_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN55_WIDTH : integer;
attribute C_PROBE_IN55_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN56_WIDTH : integer;
attribute C_PROBE_IN56_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN57_WIDTH : integer;
attribute C_PROBE_IN57_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN58_WIDTH : integer;
attribute C_PROBE_IN58_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN59_WIDTH : integer;
attribute C_PROBE_IN59_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN5_WIDTH : integer;
attribute C_PROBE_IN5_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN60_WIDTH : integer;
attribute C_PROBE_IN60_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN61_WIDTH : integer;
attribute C_PROBE_IN61_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN62_WIDTH : integer;
attribute C_PROBE_IN62_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN63_WIDTH : integer;
attribute C_PROBE_IN63_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN64_WIDTH : integer;
attribute C_PROBE_IN64_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN65_WIDTH : integer;
attribute C_PROBE_IN65_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN66_WIDTH : integer;
attribute C_PROBE_IN66_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN67_WIDTH : integer;
attribute C_PROBE_IN67_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN68_WIDTH : integer;
attribute C_PROBE_IN68_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN69_WIDTH : integer;
attribute C_PROBE_IN69_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN6_WIDTH : integer;
attribute C_PROBE_IN6_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN70_WIDTH : integer;
attribute C_PROBE_IN70_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN71_WIDTH : integer;
attribute C_PROBE_IN71_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN72_WIDTH : integer;
attribute C_PROBE_IN72_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN73_WIDTH : integer;
attribute C_PROBE_IN73_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN74_WIDTH : integer;
attribute C_PROBE_IN74_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN75_WIDTH : integer;
attribute C_PROBE_IN75_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN76_WIDTH : integer;
attribute C_PROBE_IN76_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN77_WIDTH : integer;
attribute C_PROBE_IN77_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN78_WIDTH : integer;
attribute C_PROBE_IN78_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN79_WIDTH : integer;
attribute C_PROBE_IN79_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN7_WIDTH : integer;
attribute C_PROBE_IN7_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN80_WIDTH : integer;
attribute C_PROBE_IN80_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN81_WIDTH : integer;
attribute C_PROBE_IN81_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN82_WIDTH : integer;
attribute C_PROBE_IN82_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN83_WIDTH : integer;
attribute C_PROBE_IN83_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN84_WIDTH : integer;
attribute C_PROBE_IN84_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN85_WIDTH : integer;
attribute C_PROBE_IN85_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN86_WIDTH : integer;
attribute C_PROBE_IN86_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN87_WIDTH : integer;
attribute C_PROBE_IN87_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN88_WIDTH : integer;
attribute C_PROBE_IN88_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN89_WIDTH : integer;
attribute C_PROBE_IN89_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN8_WIDTH : integer;
attribute C_PROBE_IN8_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN90_WIDTH : integer;
attribute C_PROBE_IN90_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN91_WIDTH : integer;
attribute C_PROBE_IN91_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN92_WIDTH : integer;
attribute C_PROBE_IN92_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN93_WIDTH : integer;
attribute C_PROBE_IN93_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN94_WIDTH : integer;
attribute C_PROBE_IN94_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN95_WIDTH : integer;
attribute C_PROBE_IN95_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN96_WIDTH : integer;
attribute C_PROBE_IN96_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN97_WIDTH : integer;
attribute C_PROBE_IN97_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN98_WIDTH : integer;
attribute C_PROBE_IN98_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN99_WIDTH : integer;
attribute C_PROBE_IN99_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN9_WIDTH : integer;
attribute C_PROBE_IN9_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT0_INIT_VAL : string;
attribute C_PROBE_OUT0_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT0_WIDTH : integer;
attribute C_PROBE_OUT0_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT100_INIT_VAL : string;
attribute C_PROBE_OUT100_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT100_WIDTH : integer;
attribute C_PROBE_OUT100_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT101_INIT_VAL : string;
attribute C_PROBE_OUT101_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT101_WIDTH : integer;
attribute C_PROBE_OUT101_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT102_INIT_VAL : string;
attribute C_PROBE_OUT102_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT102_WIDTH : integer;
attribute C_PROBE_OUT102_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT103_INIT_VAL : string;
attribute C_PROBE_OUT103_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT103_WIDTH : integer;
attribute C_PROBE_OUT103_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT104_INIT_VAL : string;
attribute C_PROBE_OUT104_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT104_WIDTH : integer;
attribute C_PROBE_OUT104_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT105_INIT_VAL : string;
attribute C_PROBE_OUT105_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT105_WIDTH : integer;
attribute C_PROBE_OUT105_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT106_INIT_VAL : string;
attribute C_PROBE_OUT106_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT106_WIDTH : integer;
attribute C_PROBE_OUT106_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT107_INIT_VAL : string;
attribute C_PROBE_OUT107_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT107_WIDTH : integer;
attribute C_PROBE_OUT107_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT108_INIT_VAL : string;
attribute C_PROBE_OUT108_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT108_WIDTH : integer;
attribute C_PROBE_OUT108_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT109_INIT_VAL : string;
attribute C_PROBE_OUT109_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT109_WIDTH : integer;
attribute C_PROBE_OUT109_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT10_INIT_VAL : string;
attribute C_PROBE_OUT10_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT10_WIDTH : integer;
attribute C_PROBE_OUT10_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT110_INIT_VAL : string;
attribute C_PROBE_OUT110_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT110_WIDTH : integer;
attribute C_PROBE_OUT110_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT111_INIT_VAL : string;
attribute C_PROBE_OUT111_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT111_WIDTH : integer;
attribute C_PROBE_OUT111_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT112_INIT_VAL : string;
attribute C_PROBE_OUT112_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT112_WIDTH : integer;
attribute C_PROBE_OUT112_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT113_INIT_VAL : string;
attribute C_PROBE_OUT113_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT113_WIDTH : integer;
attribute C_PROBE_OUT113_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT114_INIT_VAL : string;
attribute C_PROBE_OUT114_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT114_WIDTH : integer;
attribute C_PROBE_OUT114_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT115_INIT_VAL : string;
attribute C_PROBE_OUT115_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT115_WIDTH : integer;
attribute C_PROBE_OUT115_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT116_INIT_VAL : string;
attribute C_PROBE_OUT116_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT116_WIDTH : integer;
attribute C_PROBE_OUT116_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT117_INIT_VAL : string;
attribute C_PROBE_OUT117_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT117_WIDTH : integer;
attribute C_PROBE_OUT117_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT118_INIT_VAL : string;
attribute C_PROBE_OUT118_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT118_WIDTH : integer;
attribute C_PROBE_OUT118_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT119_INIT_VAL : string;
attribute C_PROBE_OUT119_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT119_WIDTH : integer;
attribute C_PROBE_OUT119_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT11_INIT_VAL : string;
attribute C_PROBE_OUT11_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT11_WIDTH : integer;
attribute C_PROBE_OUT11_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT120_INIT_VAL : string;
attribute C_PROBE_OUT120_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT120_WIDTH : integer;
attribute C_PROBE_OUT120_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT121_INIT_VAL : string;
attribute C_PROBE_OUT121_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT121_WIDTH : integer;
attribute C_PROBE_OUT121_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT122_INIT_VAL : string;
attribute C_PROBE_OUT122_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT122_WIDTH : integer;
attribute C_PROBE_OUT122_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT123_INIT_VAL : string;
attribute C_PROBE_OUT123_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT123_WIDTH : integer;
attribute C_PROBE_OUT123_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT124_INIT_VAL : string;
attribute C_PROBE_OUT124_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT124_WIDTH : integer;
attribute C_PROBE_OUT124_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT125_INIT_VAL : string;
attribute C_PROBE_OUT125_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT125_WIDTH : integer;
attribute C_PROBE_OUT125_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT126_INIT_VAL : string;
attribute C_PROBE_OUT126_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT126_WIDTH : integer;
attribute C_PROBE_OUT126_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT127_INIT_VAL : string;
attribute C_PROBE_OUT127_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT127_WIDTH : integer;
attribute C_PROBE_OUT127_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT128_INIT_VAL : string;
attribute C_PROBE_OUT128_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT128_WIDTH : integer;
attribute C_PROBE_OUT128_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT129_INIT_VAL : string;
attribute C_PROBE_OUT129_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT129_WIDTH : integer;
attribute C_PROBE_OUT129_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT12_INIT_VAL : string;
attribute C_PROBE_OUT12_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT12_WIDTH : integer;
attribute C_PROBE_OUT12_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT130_INIT_VAL : string;
attribute C_PROBE_OUT130_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT130_WIDTH : integer;
attribute C_PROBE_OUT130_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT131_INIT_VAL : string;
attribute C_PROBE_OUT131_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT131_WIDTH : integer;
attribute C_PROBE_OUT131_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT132_INIT_VAL : string;
attribute C_PROBE_OUT132_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT132_WIDTH : integer;
attribute C_PROBE_OUT132_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT133_INIT_VAL : string;
attribute C_PROBE_OUT133_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT133_WIDTH : integer;
attribute C_PROBE_OUT133_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT134_INIT_VAL : string;
attribute C_PROBE_OUT134_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT134_WIDTH : integer;
attribute C_PROBE_OUT134_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT135_INIT_VAL : string;
attribute C_PROBE_OUT135_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT135_WIDTH : integer;
attribute C_PROBE_OUT135_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT136_INIT_VAL : string;
attribute C_PROBE_OUT136_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT136_WIDTH : integer;
attribute C_PROBE_OUT136_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT137_INIT_VAL : string;
attribute C_PROBE_OUT137_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT137_WIDTH : integer;
attribute C_PROBE_OUT137_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT138_INIT_VAL : string;
attribute C_PROBE_OUT138_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT138_WIDTH : integer;
attribute C_PROBE_OUT138_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT139_INIT_VAL : string;
attribute C_PROBE_OUT139_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT139_WIDTH : integer;
attribute C_PROBE_OUT139_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT13_INIT_VAL : string;
attribute C_PROBE_OUT13_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT13_WIDTH : integer;
attribute C_PROBE_OUT13_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT140_INIT_VAL : string;
attribute C_PROBE_OUT140_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT140_WIDTH : integer;
attribute C_PROBE_OUT140_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT141_INIT_VAL : string;
attribute C_PROBE_OUT141_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT141_WIDTH : integer;
attribute C_PROBE_OUT141_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT142_INIT_VAL : string;
attribute C_PROBE_OUT142_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT142_WIDTH : integer;
attribute C_PROBE_OUT142_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT143_INIT_VAL : string;
attribute C_PROBE_OUT143_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT143_WIDTH : integer;
attribute C_PROBE_OUT143_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT144_INIT_VAL : string;
attribute C_PROBE_OUT144_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT144_WIDTH : integer;
attribute C_PROBE_OUT144_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT145_INIT_VAL : string;
attribute C_PROBE_OUT145_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT145_WIDTH : integer;
attribute C_PROBE_OUT145_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT146_INIT_VAL : string;
attribute C_PROBE_OUT146_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT146_WIDTH : integer;
attribute C_PROBE_OUT146_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT147_INIT_VAL : string;
attribute C_PROBE_OUT147_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT147_WIDTH : integer;
attribute C_PROBE_OUT147_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT148_INIT_VAL : string;
attribute C_PROBE_OUT148_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT148_WIDTH : integer;
attribute C_PROBE_OUT148_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT149_INIT_VAL : string;
attribute C_PROBE_OUT149_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT149_WIDTH : integer;
attribute C_PROBE_OUT149_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT14_INIT_VAL : string;
attribute C_PROBE_OUT14_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT14_WIDTH : integer;
attribute C_PROBE_OUT14_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT150_INIT_VAL : string;
attribute C_PROBE_OUT150_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT150_WIDTH : integer;
attribute C_PROBE_OUT150_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT151_INIT_VAL : string;
attribute C_PROBE_OUT151_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT151_WIDTH : integer;
attribute C_PROBE_OUT151_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT152_INIT_VAL : string;
attribute C_PROBE_OUT152_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT152_WIDTH : integer;
attribute C_PROBE_OUT152_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT153_INIT_VAL : string;
attribute C_PROBE_OUT153_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT153_WIDTH : integer;
attribute C_PROBE_OUT153_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT154_INIT_VAL : string;
attribute C_PROBE_OUT154_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT154_WIDTH : integer;
attribute C_PROBE_OUT154_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT155_INIT_VAL : string;
attribute C_PROBE_OUT155_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT155_WIDTH : integer;
attribute C_PROBE_OUT155_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT156_INIT_VAL : string;
attribute C_PROBE_OUT156_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT156_WIDTH : integer;
attribute C_PROBE_OUT156_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT157_INIT_VAL : string;
attribute C_PROBE_OUT157_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT157_WIDTH : integer;
attribute C_PROBE_OUT157_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT158_INIT_VAL : string;
attribute C_PROBE_OUT158_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT158_WIDTH : integer;
attribute C_PROBE_OUT158_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT159_INIT_VAL : string;
attribute C_PROBE_OUT159_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT159_WIDTH : integer;
attribute C_PROBE_OUT159_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT15_INIT_VAL : string;
attribute C_PROBE_OUT15_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT15_WIDTH : integer;
attribute C_PROBE_OUT15_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT160_INIT_VAL : string;
attribute C_PROBE_OUT160_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT160_WIDTH : integer;
attribute C_PROBE_OUT160_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT161_INIT_VAL : string;
attribute C_PROBE_OUT161_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT161_WIDTH : integer;
attribute C_PROBE_OUT161_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT162_INIT_VAL : string;
attribute C_PROBE_OUT162_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT162_WIDTH : integer;
attribute C_PROBE_OUT162_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT163_INIT_VAL : string;
attribute C_PROBE_OUT163_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT163_WIDTH : integer;
attribute C_PROBE_OUT163_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT164_INIT_VAL : string;
attribute C_PROBE_OUT164_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT164_WIDTH : integer;
attribute C_PROBE_OUT164_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT165_INIT_VAL : string;
attribute C_PROBE_OUT165_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT165_WIDTH : integer;
attribute C_PROBE_OUT165_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT166_INIT_VAL : string;
attribute C_PROBE_OUT166_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT166_WIDTH : integer;
attribute C_PROBE_OUT166_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT167_INIT_VAL : string;
attribute C_PROBE_OUT167_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT167_WIDTH : integer;
attribute C_PROBE_OUT167_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT168_INIT_VAL : string;
attribute C_PROBE_OUT168_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT168_WIDTH : integer;
attribute C_PROBE_OUT168_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT169_INIT_VAL : string;
attribute C_PROBE_OUT169_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT169_WIDTH : integer;
attribute C_PROBE_OUT169_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT16_INIT_VAL : string;
attribute C_PROBE_OUT16_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT16_WIDTH : integer;
attribute C_PROBE_OUT16_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT170_INIT_VAL : string;
attribute C_PROBE_OUT170_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT170_WIDTH : integer;
attribute C_PROBE_OUT170_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT171_INIT_VAL : string;
attribute C_PROBE_OUT171_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT171_WIDTH : integer;
attribute C_PROBE_OUT171_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT172_INIT_VAL : string;
attribute C_PROBE_OUT172_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT172_WIDTH : integer;
attribute C_PROBE_OUT172_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT173_INIT_VAL : string;
attribute C_PROBE_OUT173_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT173_WIDTH : integer;
attribute C_PROBE_OUT173_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT174_INIT_VAL : string;
attribute C_PROBE_OUT174_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT174_WIDTH : integer;
attribute C_PROBE_OUT174_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT175_INIT_VAL : string;
attribute C_PROBE_OUT175_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT175_WIDTH : integer;
attribute C_PROBE_OUT175_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT176_INIT_VAL : string;
attribute C_PROBE_OUT176_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT176_WIDTH : integer;
attribute C_PROBE_OUT176_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT177_INIT_VAL : string;
attribute C_PROBE_OUT177_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT177_WIDTH : integer;
attribute C_PROBE_OUT177_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT178_INIT_VAL : string;
attribute C_PROBE_OUT178_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT178_WIDTH : integer;
attribute C_PROBE_OUT178_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT179_INIT_VAL : string;
attribute C_PROBE_OUT179_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT179_WIDTH : integer;
attribute C_PROBE_OUT179_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT17_INIT_VAL : string;
attribute C_PROBE_OUT17_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT17_WIDTH : integer;
attribute C_PROBE_OUT17_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT180_INIT_VAL : string;
attribute C_PROBE_OUT180_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT180_WIDTH : integer;
attribute C_PROBE_OUT180_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT181_INIT_VAL : string;
attribute C_PROBE_OUT181_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT181_WIDTH : integer;
attribute C_PROBE_OUT181_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT182_INIT_VAL : string;
attribute C_PROBE_OUT182_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT182_WIDTH : integer;
attribute C_PROBE_OUT182_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT183_INIT_VAL : string;
attribute C_PROBE_OUT183_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT183_WIDTH : integer;
attribute C_PROBE_OUT183_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT184_INIT_VAL : string;
attribute C_PROBE_OUT184_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT184_WIDTH : integer;
attribute C_PROBE_OUT184_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT185_INIT_VAL : string;
attribute C_PROBE_OUT185_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT185_WIDTH : integer;
attribute C_PROBE_OUT185_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT186_INIT_VAL : string;
attribute C_PROBE_OUT186_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT186_WIDTH : integer;
attribute C_PROBE_OUT186_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT187_INIT_VAL : string;
attribute C_PROBE_OUT187_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT187_WIDTH : integer;
attribute C_PROBE_OUT187_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT188_INIT_VAL : string;
attribute C_PROBE_OUT188_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT188_WIDTH : integer;
attribute C_PROBE_OUT188_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT189_INIT_VAL : string;
attribute C_PROBE_OUT189_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT189_WIDTH : integer;
attribute C_PROBE_OUT189_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT18_INIT_VAL : string;
attribute C_PROBE_OUT18_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT18_WIDTH : integer;
attribute C_PROBE_OUT18_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT190_INIT_VAL : string;
attribute C_PROBE_OUT190_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT190_WIDTH : integer;
attribute C_PROBE_OUT190_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT191_INIT_VAL : string;
attribute C_PROBE_OUT191_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT191_WIDTH : integer;
attribute C_PROBE_OUT191_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT192_INIT_VAL : string;
attribute C_PROBE_OUT192_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT192_WIDTH : integer;
attribute C_PROBE_OUT192_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT193_INIT_VAL : string;
attribute C_PROBE_OUT193_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT193_WIDTH : integer;
attribute C_PROBE_OUT193_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT194_INIT_VAL : string;
attribute C_PROBE_OUT194_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT194_WIDTH : integer;
attribute C_PROBE_OUT194_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT195_INIT_VAL : string;
attribute C_PROBE_OUT195_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT195_WIDTH : integer;
attribute C_PROBE_OUT195_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT196_INIT_VAL : string;
attribute C_PROBE_OUT196_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT196_WIDTH : integer;
attribute C_PROBE_OUT196_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT197_INIT_VAL : string;
attribute C_PROBE_OUT197_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT197_WIDTH : integer;
attribute C_PROBE_OUT197_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT198_INIT_VAL : string;
attribute C_PROBE_OUT198_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT198_WIDTH : integer;
attribute C_PROBE_OUT198_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT199_INIT_VAL : string;
attribute C_PROBE_OUT199_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT199_WIDTH : integer;
attribute C_PROBE_OUT199_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT19_INIT_VAL : string;
attribute C_PROBE_OUT19_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT19_WIDTH : integer;
attribute C_PROBE_OUT19_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT1_INIT_VAL : string;
attribute C_PROBE_OUT1_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT1_WIDTH : integer;
attribute C_PROBE_OUT1_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT200_INIT_VAL : string;
attribute C_PROBE_OUT200_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT200_WIDTH : integer;
attribute C_PROBE_OUT200_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT201_INIT_VAL : string;
attribute C_PROBE_OUT201_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT201_WIDTH : integer;
attribute C_PROBE_OUT201_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT202_INIT_VAL : string;
attribute C_PROBE_OUT202_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT202_WIDTH : integer;
attribute C_PROBE_OUT202_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT203_INIT_VAL : string;
attribute C_PROBE_OUT203_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT203_WIDTH : integer;
attribute C_PROBE_OUT203_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT204_INIT_VAL : string;
attribute C_PROBE_OUT204_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT204_WIDTH : integer;
attribute C_PROBE_OUT204_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT205_INIT_VAL : string;
attribute C_PROBE_OUT205_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT205_WIDTH : integer;
attribute C_PROBE_OUT205_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT206_INIT_VAL : string;
attribute C_PROBE_OUT206_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT206_WIDTH : integer;
attribute C_PROBE_OUT206_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT207_INIT_VAL : string;
attribute C_PROBE_OUT207_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT207_WIDTH : integer;
attribute C_PROBE_OUT207_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT208_INIT_VAL : string;
attribute C_PROBE_OUT208_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT208_WIDTH : integer;
attribute C_PROBE_OUT208_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT209_INIT_VAL : string;
attribute C_PROBE_OUT209_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT209_WIDTH : integer;
attribute C_PROBE_OUT209_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT20_INIT_VAL : string;
attribute C_PROBE_OUT20_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT20_WIDTH : integer;
attribute C_PROBE_OUT20_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT210_INIT_VAL : string;
attribute C_PROBE_OUT210_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT210_WIDTH : integer;
attribute C_PROBE_OUT210_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT211_INIT_VAL : string;
attribute C_PROBE_OUT211_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT211_WIDTH : integer;
attribute C_PROBE_OUT211_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT212_INIT_VAL : string;
attribute C_PROBE_OUT212_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT212_WIDTH : integer;
attribute C_PROBE_OUT212_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT213_INIT_VAL : string;
attribute C_PROBE_OUT213_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT213_WIDTH : integer;
attribute C_PROBE_OUT213_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT214_INIT_VAL : string;
attribute C_PROBE_OUT214_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT214_WIDTH : integer;
attribute C_PROBE_OUT214_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT215_INIT_VAL : string;
attribute C_PROBE_OUT215_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT215_WIDTH : integer;
attribute C_PROBE_OUT215_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT216_INIT_VAL : string;
attribute C_PROBE_OUT216_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT216_WIDTH : integer;
attribute C_PROBE_OUT216_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT217_INIT_VAL : string;
attribute C_PROBE_OUT217_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT217_WIDTH : integer;
attribute C_PROBE_OUT217_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT218_INIT_VAL : string;
attribute C_PROBE_OUT218_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT218_WIDTH : integer;
attribute C_PROBE_OUT218_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT219_INIT_VAL : string;
attribute C_PROBE_OUT219_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT219_WIDTH : integer;
attribute C_PROBE_OUT219_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT21_INIT_VAL : string;
attribute C_PROBE_OUT21_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT21_WIDTH : integer;
attribute C_PROBE_OUT21_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT220_INIT_VAL : string;
attribute C_PROBE_OUT220_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT220_WIDTH : integer;
attribute C_PROBE_OUT220_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT221_INIT_VAL : string;
attribute C_PROBE_OUT221_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT221_WIDTH : integer;
attribute C_PROBE_OUT221_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT222_INIT_VAL : string;
attribute C_PROBE_OUT222_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT222_WIDTH : integer;
attribute C_PROBE_OUT222_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT223_INIT_VAL : string;
attribute C_PROBE_OUT223_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT223_WIDTH : integer;
attribute C_PROBE_OUT223_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT224_INIT_VAL : string;
attribute C_PROBE_OUT224_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT224_WIDTH : integer;
attribute C_PROBE_OUT224_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT225_INIT_VAL : string;
attribute C_PROBE_OUT225_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT225_WIDTH : integer;
attribute C_PROBE_OUT225_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT226_INIT_VAL : string;
attribute C_PROBE_OUT226_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT226_WIDTH : integer;
attribute C_PROBE_OUT226_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT227_INIT_VAL : string;
attribute C_PROBE_OUT227_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT227_WIDTH : integer;
attribute C_PROBE_OUT227_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT228_INIT_VAL : string;
attribute C_PROBE_OUT228_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT228_WIDTH : integer;
attribute C_PROBE_OUT228_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT229_INIT_VAL : string;
attribute C_PROBE_OUT229_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT229_WIDTH : integer;
attribute C_PROBE_OUT229_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT22_INIT_VAL : string;
attribute C_PROBE_OUT22_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT22_WIDTH : integer;
attribute C_PROBE_OUT22_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT230_INIT_VAL : string;
attribute C_PROBE_OUT230_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT230_WIDTH : integer;
attribute C_PROBE_OUT230_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT231_INIT_VAL : string;
attribute C_PROBE_OUT231_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT231_WIDTH : integer;
attribute C_PROBE_OUT231_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT232_INIT_VAL : string;
attribute C_PROBE_OUT232_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT232_WIDTH : integer;
attribute C_PROBE_OUT232_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT233_INIT_VAL : string;
attribute C_PROBE_OUT233_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT233_WIDTH : integer;
attribute C_PROBE_OUT233_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT234_INIT_VAL : string;
attribute C_PROBE_OUT234_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT234_WIDTH : integer;
attribute C_PROBE_OUT234_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT235_INIT_VAL : string;
attribute C_PROBE_OUT235_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT235_WIDTH : integer;
attribute C_PROBE_OUT235_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT236_INIT_VAL : string;
attribute C_PROBE_OUT236_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT236_WIDTH : integer;
attribute C_PROBE_OUT236_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT237_INIT_VAL : string;
attribute C_PROBE_OUT237_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT237_WIDTH : integer;
attribute C_PROBE_OUT237_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT238_INIT_VAL : string;
attribute C_PROBE_OUT238_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT238_WIDTH : integer;
attribute C_PROBE_OUT238_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT239_INIT_VAL : string;
attribute C_PROBE_OUT239_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT239_WIDTH : integer;
attribute C_PROBE_OUT239_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT23_INIT_VAL : string;
attribute C_PROBE_OUT23_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT23_WIDTH : integer;
attribute C_PROBE_OUT23_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT240_INIT_VAL : string;
attribute C_PROBE_OUT240_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT240_WIDTH : integer;
attribute C_PROBE_OUT240_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT241_INIT_VAL : string;
attribute C_PROBE_OUT241_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT241_WIDTH : integer;
attribute C_PROBE_OUT241_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT242_INIT_VAL : string;
attribute C_PROBE_OUT242_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT242_WIDTH : integer;
attribute C_PROBE_OUT242_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT243_INIT_VAL : string;
attribute C_PROBE_OUT243_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT243_WIDTH : integer;
attribute C_PROBE_OUT243_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT244_INIT_VAL : string;
attribute C_PROBE_OUT244_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT244_WIDTH : integer;
attribute C_PROBE_OUT244_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT245_INIT_VAL : string;
attribute C_PROBE_OUT245_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT245_WIDTH : integer;
attribute C_PROBE_OUT245_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT246_INIT_VAL : string;
attribute C_PROBE_OUT246_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT246_WIDTH : integer;
attribute C_PROBE_OUT246_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT247_INIT_VAL : string;
attribute C_PROBE_OUT247_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT247_WIDTH : integer;
attribute C_PROBE_OUT247_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT248_INIT_VAL : string;
attribute C_PROBE_OUT248_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT248_WIDTH : integer;
attribute C_PROBE_OUT248_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT249_INIT_VAL : string;
attribute C_PROBE_OUT249_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT249_WIDTH : integer;
attribute C_PROBE_OUT249_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT24_INIT_VAL : string;
attribute C_PROBE_OUT24_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT24_WIDTH : integer;
attribute C_PROBE_OUT24_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT250_INIT_VAL : string;
attribute C_PROBE_OUT250_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT250_WIDTH : integer;
attribute C_PROBE_OUT250_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT251_INIT_VAL : string;
attribute C_PROBE_OUT251_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT251_WIDTH : integer;
attribute C_PROBE_OUT251_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT252_INIT_VAL : string;
attribute C_PROBE_OUT252_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT252_WIDTH : integer;
attribute C_PROBE_OUT252_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT253_INIT_VAL : string;
attribute C_PROBE_OUT253_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT253_WIDTH : integer;
attribute C_PROBE_OUT253_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT254_INIT_VAL : string;
attribute C_PROBE_OUT254_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT254_WIDTH : integer;
attribute C_PROBE_OUT254_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT255_INIT_VAL : string;
attribute C_PROBE_OUT255_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT255_WIDTH : integer;
attribute C_PROBE_OUT255_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT25_INIT_VAL : string;
attribute C_PROBE_OUT25_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT25_WIDTH : integer;
attribute C_PROBE_OUT25_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT26_INIT_VAL : string;
attribute C_PROBE_OUT26_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT26_WIDTH : integer;
attribute C_PROBE_OUT26_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT27_INIT_VAL : string;
attribute C_PROBE_OUT27_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT27_WIDTH : integer;
attribute C_PROBE_OUT27_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT28_INIT_VAL : string;
attribute C_PROBE_OUT28_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT28_WIDTH : integer;
attribute C_PROBE_OUT28_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT29_INIT_VAL : string;
attribute C_PROBE_OUT29_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT29_WIDTH : integer;
attribute C_PROBE_OUT29_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT2_INIT_VAL : string;
attribute C_PROBE_OUT2_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT2_WIDTH : integer;
attribute C_PROBE_OUT2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT30_INIT_VAL : string;
attribute C_PROBE_OUT30_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT30_WIDTH : integer;
attribute C_PROBE_OUT30_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT31_INIT_VAL : string;
attribute C_PROBE_OUT31_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT31_WIDTH : integer;
attribute C_PROBE_OUT31_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT32_INIT_VAL : string;
attribute C_PROBE_OUT32_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT32_WIDTH : integer;
attribute C_PROBE_OUT32_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT33_INIT_VAL : string;
attribute C_PROBE_OUT33_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT33_WIDTH : integer;
attribute C_PROBE_OUT33_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT34_INIT_VAL : string;
attribute C_PROBE_OUT34_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT34_WIDTH : integer;
attribute C_PROBE_OUT34_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT35_INIT_VAL : string;
attribute C_PROBE_OUT35_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT35_WIDTH : integer;
attribute C_PROBE_OUT35_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT36_INIT_VAL : string;
attribute C_PROBE_OUT36_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT36_WIDTH : integer;
attribute C_PROBE_OUT36_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT37_INIT_VAL : string;
attribute C_PROBE_OUT37_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT37_WIDTH : integer;
attribute C_PROBE_OUT37_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT38_INIT_VAL : string;
attribute C_PROBE_OUT38_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT38_WIDTH : integer;
attribute C_PROBE_OUT38_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT39_INIT_VAL : string;
attribute C_PROBE_OUT39_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT39_WIDTH : integer;
attribute C_PROBE_OUT39_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT3_INIT_VAL : string;
attribute C_PROBE_OUT3_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT3_WIDTH : integer;
attribute C_PROBE_OUT3_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT40_INIT_VAL : string;
attribute C_PROBE_OUT40_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT40_WIDTH : integer;
attribute C_PROBE_OUT40_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT41_INIT_VAL : string;
attribute C_PROBE_OUT41_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT41_WIDTH : integer;
attribute C_PROBE_OUT41_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT42_INIT_VAL : string;
attribute C_PROBE_OUT42_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT42_WIDTH : integer;
attribute C_PROBE_OUT42_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT43_INIT_VAL : string;
attribute C_PROBE_OUT43_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT43_WIDTH : integer;
attribute C_PROBE_OUT43_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT44_INIT_VAL : string;
attribute C_PROBE_OUT44_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT44_WIDTH : integer;
attribute C_PROBE_OUT44_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT45_INIT_VAL : string;
attribute C_PROBE_OUT45_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT45_WIDTH : integer;
attribute C_PROBE_OUT45_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT46_INIT_VAL : string;
attribute C_PROBE_OUT46_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT46_WIDTH : integer;
attribute C_PROBE_OUT46_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT47_INIT_VAL : string;
attribute C_PROBE_OUT47_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT47_WIDTH : integer;
attribute C_PROBE_OUT47_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT48_INIT_VAL : string;
attribute C_PROBE_OUT48_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT48_WIDTH : integer;
attribute C_PROBE_OUT48_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT49_INIT_VAL : string;
attribute C_PROBE_OUT49_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT49_WIDTH : integer;
attribute C_PROBE_OUT49_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT4_INIT_VAL : string;
attribute C_PROBE_OUT4_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT4_WIDTH : integer;
attribute C_PROBE_OUT4_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT50_INIT_VAL : string;
attribute C_PROBE_OUT50_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT50_WIDTH : integer;
attribute C_PROBE_OUT50_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT51_INIT_VAL : string;
attribute C_PROBE_OUT51_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT51_WIDTH : integer;
attribute C_PROBE_OUT51_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT52_INIT_VAL : string;
attribute C_PROBE_OUT52_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT52_WIDTH : integer;
attribute C_PROBE_OUT52_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT53_INIT_VAL : string;
attribute C_PROBE_OUT53_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT53_WIDTH : integer;
attribute C_PROBE_OUT53_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT54_INIT_VAL : string;
attribute C_PROBE_OUT54_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT54_WIDTH : integer;
attribute C_PROBE_OUT54_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT55_INIT_VAL : string;
attribute C_PROBE_OUT55_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT55_WIDTH : integer;
attribute C_PROBE_OUT55_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT56_INIT_VAL : string;
attribute C_PROBE_OUT56_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT56_WIDTH : integer;
attribute C_PROBE_OUT56_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT57_INIT_VAL : string;
attribute C_PROBE_OUT57_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT57_WIDTH : integer;
attribute C_PROBE_OUT57_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT58_INIT_VAL : string;
attribute C_PROBE_OUT58_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT58_WIDTH : integer;
attribute C_PROBE_OUT58_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT59_INIT_VAL : string;
attribute C_PROBE_OUT59_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT59_WIDTH : integer;
attribute C_PROBE_OUT59_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT5_INIT_VAL : string;
attribute C_PROBE_OUT5_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT5_WIDTH : integer;
attribute C_PROBE_OUT5_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT60_INIT_VAL : string;
attribute C_PROBE_OUT60_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT60_WIDTH : integer;
attribute C_PROBE_OUT60_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT61_INIT_VAL : string;
attribute C_PROBE_OUT61_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT61_WIDTH : integer;
attribute C_PROBE_OUT61_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT62_INIT_VAL : string;
attribute C_PROBE_OUT62_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT62_WIDTH : integer;
attribute C_PROBE_OUT62_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT63_INIT_VAL : string;
attribute C_PROBE_OUT63_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT63_WIDTH : integer;
attribute C_PROBE_OUT63_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT64_INIT_VAL : string;
attribute C_PROBE_OUT64_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT64_WIDTH : integer;
attribute C_PROBE_OUT64_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT65_INIT_VAL : string;
attribute C_PROBE_OUT65_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT65_WIDTH : integer;
attribute C_PROBE_OUT65_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT66_INIT_VAL : string;
attribute C_PROBE_OUT66_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT66_WIDTH : integer;
attribute C_PROBE_OUT66_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT67_INIT_VAL : string;
attribute C_PROBE_OUT67_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT67_WIDTH : integer;
attribute C_PROBE_OUT67_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT68_INIT_VAL : string;
attribute C_PROBE_OUT68_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT68_WIDTH : integer;
attribute C_PROBE_OUT68_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT69_INIT_VAL : string;
attribute C_PROBE_OUT69_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT69_WIDTH : integer;
attribute C_PROBE_OUT69_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT6_INIT_VAL : string;
attribute C_PROBE_OUT6_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT6_WIDTH : integer;
attribute C_PROBE_OUT6_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT70_INIT_VAL : string;
attribute C_PROBE_OUT70_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT70_WIDTH : integer;
attribute C_PROBE_OUT70_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT71_INIT_VAL : string;
attribute C_PROBE_OUT71_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT71_WIDTH : integer;
attribute C_PROBE_OUT71_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT72_INIT_VAL : string;
attribute C_PROBE_OUT72_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT72_WIDTH : integer;
attribute C_PROBE_OUT72_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT73_INIT_VAL : string;
attribute C_PROBE_OUT73_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT73_WIDTH : integer;
attribute C_PROBE_OUT73_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT74_INIT_VAL : string;
attribute C_PROBE_OUT74_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT74_WIDTH : integer;
attribute C_PROBE_OUT74_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT75_INIT_VAL : string;
attribute C_PROBE_OUT75_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT75_WIDTH : integer;
attribute C_PROBE_OUT75_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT76_INIT_VAL : string;
attribute C_PROBE_OUT76_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT76_WIDTH : integer;
attribute C_PROBE_OUT76_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT77_INIT_VAL : string;
attribute C_PROBE_OUT77_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT77_WIDTH : integer;
attribute C_PROBE_OUT77_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT78_INIT_VAL : string;
attribute C_PROBE_OUT78_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT78_WIDTH : integer;
attribute C_PROBE_OUT78_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT79_INIT_VAL : string;
attribute C_PROBE_OUT79_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT79_WIDTH : integer;
attribute C_PROBE_OUT79_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT7_INIT_VAL : string;
attribute C_PROBE_OUT7_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT7_WIDTH : integer;
attribute C_PROBE_OUT7_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT80_INIT_VAL : string;
attribute C_PROBE_OUT80_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT80_WIDTH : integer;
attribute C_PROBE_OUT80_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT81_INIT_VAL : string;
attribute C_PROBE_OUT81_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT81_WIDTH : integer;
attribute C_PROBE_OUT81_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT82_INIT_VAL : string;
attribute C_PROBE_OUT82_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT82_WIDTH : integer;
attribute C_PROBE_OUT82_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT83_INIT_VAL : string;
attribute C_PROBE_OUT83_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT83_WIDTH : integer;
attribute C_PROBE_OUT83_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT84_INIT_VAL : string;
attribute C_PROBE_OUT84_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT84_WIDTH : integer;
attribute C_PROBE_OUT84_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT85_INIT_VAL : string;
attribute C_PROBE_OUT85_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT85_WIDTH : integer;
attribute C_PROBE_OUT85_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT86_INIT_VAL : string;
attribute C_PROBE_OUT86_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT86_WIDTH : integer;
attribute C_PROBE_OUT86_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT87_INIT_VAL : string;
attribute C_PROBE_OUT87_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT87_WIDTH : integer;
attribute C_PROBE_OUT87_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT88_INIT_VAL : string;
attribute C_PROBE_OUT88_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT88_WIDTH : integer;
attribute C_PROBE_OUT88_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT89_INIT_VAL : string;
attribute C_PROBE_OUT89_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT89_WIDTH : integer;
attribute C_PROBE_OUT89_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT8_INIT_VAL : string;
attribute C_PROBE_OUT8_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT8_WIDTH : integer;
attribute C_PROBE_OUT8_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT90_INIT_VAL : string;
attribute C_PROBE_OUT90_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT90_WIDTH : integer;
attribute C_PROBE_OUT90_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT91_INIT_VAL : string;
attribute C_PROBE_OUT91_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT91_WIDTH : integer;
attribute C_PROBE_OUT91_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT92_INIT_VAL : string;
attribute C_PROBE_OUT92_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT92_WIDTH : integer;
attribute C_PROBE_OUT92_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT93_INIT_VAL : string;
attribute C_PROBE_OUT93_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT93_WIDTH : integer;
attribute C_PROBE_OUT93_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT94_INIT_VAL : string;
attribute C_PROBE_OUT94_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT94_WIDTH : integer;
attribute C_PROBE_OUT94_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT95_INIT_VAL : string;
attribute C_PROBE_OUT95_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT95_WIDTH : integer;
attribute C_PROBE_OUT95_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT96_INIT_VAL : string;
attribute C_PROBE_OUT96_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT96_WIDTH : integer;
attribute C_PROBE_OUT96_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT97_INIT_VAL : string;
attribute C_PROBE_OUT97_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT97_WIDTH : integer;
attribute C_PROBE_OUT97_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT98_INIT_VAL : string;
attribute C_PROBE_OUT98_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT98_WIDTH : integer;
attribute C_PROBE_OUT98_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT99_INIT_VAL : string;
attribute C_PROBE_OUT99_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT99_WIDTH : integer;
attribute C_PROBE_OUT99_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT9_INIT_VAL : string;
attribute C_PROBE_OUT9_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT9_WIDTH : integer;
attribute C_PROBE_OUT9_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_USE_TEST_REG : integer;
attribute C_USE_TEST_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "kintex7";
attribute C_XLNX_HW_PROBE_INFO : string;
attribute C_XLNX_HW_PROBE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "DEFAULT";
attribute C_XSDB_SLAVE_TYPE : integer;
attribute C_XSDB_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 33;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "yes";
attribute LC_HIGH_BIT_POS_PROBE_OUT0 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT1 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT10 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT10 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT100 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT100 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT101 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT101 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT102 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT102 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT103 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT103 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT104 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT104 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT105 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT105 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT106 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT106 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT107 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT107 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT108 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT108 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT109 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT109 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT11 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT11 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT110 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT110 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT111 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT111 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT112 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT112 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT113 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT113 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT114 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT114 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT115 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT115 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT116 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT116 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT117 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT117 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT118 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT118 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT119 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT119 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT12 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT12 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT120 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT120 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT121 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT121 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT122 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT122 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT123 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT123 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT124 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT124 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT125 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT125 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT126 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT126 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT127 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT127 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT128 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT128 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT129 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT129 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT13 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT13 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT130 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT130 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT131 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT131 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT132 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT132 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT133 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT133 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT134 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT134 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT135 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT135 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT136 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT136 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT137 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT137 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT138 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT138 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT139 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT139 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT14 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT14 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT140 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT140 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT141 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT141 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT142 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT142 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT143 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT143 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT144 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT144 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT145 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT145 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT146 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT146 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT147 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT147 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT148 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT148 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT149 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT149 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT15 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT15 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT150 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT150 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT151 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT151 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT152 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT152 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT153 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT153 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT154 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT154 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT155 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT155 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT156 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT156 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT157 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT157 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT158 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT158 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT159 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT159 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT16 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT16 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT160 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT160 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT161 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT161 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT162 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT162 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT163 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT163 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT164 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT164 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT165 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT165 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT166 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT166 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT167 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT167 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT168 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT168 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT169 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT169 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT17 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT17 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT170 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT170 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT171 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT171 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT172 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT172 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT173 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT173 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT174 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT174 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT175 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT175 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT176 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT176 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT177 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT177 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT178 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT178 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT179 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT179 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT18 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT18 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT180 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT180 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT181 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT181 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT182 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT182 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT183 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT183 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT184 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT184 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT185 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT185 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT186 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT186 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT187 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT187 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT188 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT188 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT189 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT189 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT19 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT19 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT190 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT190 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT191 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT191 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT192 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT192 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT193 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT193 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT194 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT194 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT195 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT195 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT196 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT196 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT197 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT197 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT198 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT198 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT199 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT199 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT2 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT20 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT20 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT200 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT200 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT201 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT201 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT202 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT202 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT203 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT203 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT204 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT204 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT205 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT205 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT206 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT206 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT207 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT207 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT208 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT208 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT209 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT209 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT21 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT21 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT210 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT210 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT211 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT211 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT212 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT212 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT213 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT213 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT214 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT214 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT215 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT215 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT216 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT216 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT217 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT217 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT218 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT218 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT219 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT219 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT22 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT22 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT220 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT220 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT221 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT221 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT222 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT222 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT223 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT223 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT224 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT224 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT225 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT225 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT226 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT226 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT227 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT227 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT228 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT228 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT229 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT229 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT23 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT23 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT230 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT230 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT231 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT231 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT232 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT232 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT233 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT233 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT234 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT234 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT235 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT235 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT236 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT236 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT237 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT237 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT238 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT238 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT239 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT239 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT24 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT24 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT240 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT240 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT241 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT241 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT242 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT242 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT243 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT243 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT244 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT244 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT245 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT245 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT246 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT246 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT247 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT247 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT248 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT248 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT249 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT249 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT25 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT25 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT250 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT250 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT251 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT251 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT252 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT252 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT253 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT253 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT254 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT254 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT255 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT255 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT26 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT26 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT27 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT27 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT28 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT28 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT29 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT29 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT3 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT30 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT30 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT31 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT31 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT32 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT32 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT33 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT33 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT34 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT34 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT35 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT35 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT36 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT36 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT37 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT37 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT38 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT38 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT39 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT39 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT4 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT40 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT40 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT41 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT41 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT42 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT42 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT43 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT43 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT44 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT44 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT45 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT45 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT46 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT46 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT47 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT47 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT48 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT48 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT49 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT49 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT5 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT5 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT50 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT50 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT51 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT51 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT52 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT52 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT53 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT53 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT54 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT54 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT55 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT55 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT56 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT56 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT57 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT57 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT58 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT58 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT59 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT59 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT6 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT6 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT60 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT60 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT61 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT61 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT62 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT62 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT63 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT63 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT64 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT64 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT65 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT65 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT66 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT66 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT67 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT67 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT68 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT68 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT69 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT69 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT7 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT7 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT70 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT70 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT71 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT71 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT72 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT72 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT73 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT73 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT74 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT74 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT75 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT75 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT76 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT76 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT77 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT77 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT78 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT78 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT79 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT79 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT8 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT8 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT80 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT80 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT81 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT81 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT82 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT82 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT83 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT83 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT84 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT84 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT85 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT85 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT86 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT86 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT87 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT87 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT88 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT88 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT89 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT89 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT9 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT9 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT90 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT90 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT91 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT91 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT92 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT92 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT93 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT93 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT94 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT94 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT95 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT95 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT96 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT96 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT97 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT97 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT98 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT98 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT99 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT99 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100011";
attribute LC_LOW_BIT_POS_PROBE_OUT0 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000000";
attribute LC_LOW_BIT_POS_PROBE_OUT1 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000001";
attribute LC_LOW_BIT_POS_PROBE_OUT10 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT10 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001010";
attribute LC_LOW_BIT_POS_PROBE_OUT100 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT100 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100100";
attribute LC_LOW_BIT_POS_PROBE_OUT101 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT101 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100101";
attribute LC_LOW_BIT_POS_PROBE_OUT102 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT102 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100110";
attribute LC_LOW_BIT_POS_PROBE_OUT103 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT103 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100111";
attribute LC_LOW_BIT_POS_PROBE_OUT104 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT104 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101000";
attribute LC_LOW_BIT_POS_PROBE_OUT105 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT105 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101001";
attribute LC_LOW_BIT_POS_PROBE_OUT106 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT106 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101010";
attribute LC_LOW_BIT_POS_PROBE_OUT107 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT107 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101011";
attribute LC_LOW_BIT_POS_PROBE_OUT108 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT108 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101100";
attribute LC_LOW_BIT_POS_PROBE_OUT109 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT109 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101101";
attribute LC_LOW_BIT_POS_PROBE_OUT11 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT11 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001011";
attribute LC_LOW_BIT_POS_PROBE_OUT110 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT110 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101110";
attribute LC_LOW_BIT_POS_PROBE_OUT111 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT111 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101111";
attribute LC_LOW_BIT_POS_PROBE_OUT112 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT112 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110000";
attribute LC_LOW_BIT_POS_PROBE_OUT113 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT113 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110001";
attribute LC_LOW_BIT_POS_PROBE_OUT114 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT114 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110010";
attribute LC_LOW_BIT_POS_PROBE_OUT115 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT115 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110011";
attribute LC_LOW_BIT_POS_PROBE_OUT116 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT116 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110100";
attribute LC_LOW_BIT_POS_PROBE_OUT117 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT117 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110101";
attribute LC_LOW_BIT_POS_PROBE_OUT118 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT118 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110110";
attribute LC_LOW_BIT_POS_PROBE_OUT119 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT119 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110111";
attribute LC_LOW_BIT_POS_PROBE_OUT12 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT12 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001100";
attribute LC_LOW_BIT_POS_PROBE_OUT120 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT120 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111000";
attribute LC_LOW_BIT_POS_PROBE_OUT121 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT121 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111001";
attribute LC_LOW_BIT_POS_PROBE_OUT122 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT122 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111010";
attribute LC_LOW_BIT_POS_PROBE_OUT123 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT123 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111011";
attribute LC_LOW_BIT_POS_PROBE_OUT124 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT124 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111100";
attribute LC_LOW_BIT_POS_PROBE_OUT125 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT125 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111101";
attribute LC_LOW_BIT_POS_PROBE_OUT126 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT126 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111110";
attribute LC_LOW_BIT_POS_PROBE_OUT127 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT127 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111111";
attribute LC_LOW_BIT_POS_PROBE_OUT128 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT128 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000000";
attribute LC_LOW_BIT_POS_PROBE_OUT129 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT129 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000001";
attribute LC_LOW_BIT_POS_PROBE_OUT13 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT13 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001101";
attribute LC_LOW_BIT_POS_PROBE_OUT130 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT130 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000010";
attribute LC_LOW_BIT_POS_PROBE_OUT131 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT131 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000011";
attribute LC_LOW_BIT_POS_PROBE_OUT132 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT132 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000100";
attribute LC_LOW_BIT_POS_PROBE_OUT133 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT133 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000101";
attribute LC_LOW_BIT_POS_PROBE_OUT134 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT134 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000110";
attribute LC_LOW_BIT_POS_PROBE_OUT135 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT135 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000111";
attribute LC_LOW_BIT_POS_PROBE_OUT136 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT136 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001000";
attribute LC_LOW_BIT_POS_PROBE_OUT137 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT137 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001001";
attribute LC_LOW_BIT_POS_PROBE_OUT138 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT138 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001010";
attribute LC_LOW_BIT_POS_PROBE_OUT139 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT139 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001011";
attribute LC_LOW_BIT_POS_PROBE_OUT14 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT14 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001110";
attribute LC_LOW_BIT_POS_PROBE_OUT140 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT140 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001100";
attribute LC_LOW_BIT_POS_PROBE_OUT141 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT141 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001101";
attribute LC_LOW_BIT_POS_PROBE_OUT142 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT142 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001110";
attribute LC_LOW_BIT_POS_PROBE_OUT143 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT143 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001111";
attribute LC_LOW_BIT_POS_PROBE_OUT144 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT144 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010000";
attribute LC_LOW_BIT_POS_PROBE_OUT145 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT145 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010001";
attribute LC_LOW_BIT_POS_PROBE_OUT146 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT146 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010010";
attribute LC_LOW_BIT_POS_PROBE_OUT147 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT147 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010011";
attribute LC_LOW_BIT_POS_PROBE_OUT148 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT148 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010100";
attribute LC_LOW_BIT_POS_PROBE_OUT149 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT149 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010101";
attribute LC_LOW_BIT_POS_PROBE_OUT15 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT15 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001111";
attribute LC_LOW_BIT_POS_PROBE_OUT150 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT150 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010110";
attribute LC_LOW_BIT_POS_PROBE_OUT151 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT151 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010111";
attribute LC_LOW_BIT_POS_PROBE_OUT152 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT152 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011000";
attribute LC_LOW_BIT_POS_PROBE_OUT153 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT153 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011001";
attribute LC_LOW_BIT_POS_PROBE_OUT154 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT154 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011010";
attribute LC_LOW_BIT_POS_PROBE_OUT155 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT155 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011011";
attribute LC_LOW_BIT_POS_PROBE_OUT156 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT156 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011100";
attribute LC_LOW_BIT_POS_PROBE_OUT157 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT157 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011101";
attribute LC_LOW_BIT_POS_PROBE_OUT158 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT158 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011110";
attribute LC_LOW_BIT_POS_PROBE_OUT159 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT159 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011111";
attribute LC_LOW_BIT_POS_PROBE_OUT16 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT16 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010000";
attribute LC_LOW_BIT_POS_PROBE_OUT160 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT160 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100000";
attribute LC_LOW_BIT_POS_PROBE_OUT161 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT161 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100001";
attribute LC_LOW_BIT_POS_PROBE_OUT162 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT162 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100010";
attribute LC_LOW_BIT_POS_PROBE_OUT163 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT163 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100011";
attribute LC_LOW_BIT_POS_PROBE_OUT164 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT164 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100100";
attribute LC_LOW_BIT_POS_PROBE_OUT165 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT165 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100101";
attribute LC_LOW_BIT_POS_PROBE_OUT166 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT166 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100110";
attribute LC_LOW_BIT_POS_PROBE_OUT167 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT167 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100111";
attribute LC_LOW_BIT_POS_PROBE_OUT168 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT168 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101000";
attribute LC_LOW_BIT_POS_PROBE_OUT169 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT169 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101001";
attribute LC_LOW_BIT_POS_PROBE_OUT17 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT17 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010001";
attribute LC_LOW_BIT_POS_PROBE_OUT170 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT170 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101010";
attribute LC_LOW_BIT_POS_PROBE_OUT171 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT171 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101011";
attribute LC_LOW_BIT_POS_PROBE_OUT172 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT172 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101100";
attribute LC_LOW_BIT_POS_PROBE_OUT173 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT173 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101101";
attribute LC_LOW_BIT_POS_PROBE_OUT174 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT174 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101110";
attribute LC_LOW_BIT_POS_PROBE_OUT175 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT175 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101111";
attribute LC_LOW_BIT_POS_PROBE_OUT176 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT176 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110000";
attribute LC_LOW_BIT_POS_PROBE_OUT177 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT177 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110001";
attribute LC_LOW_BIT_POS_PROBE_OUT178 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT178 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110010";
attribute LC_LOW_BIT_POS_PROBE_OUT179 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT179 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110011";
attribute LC_LOW_BIT_POS_PROBE_OUT18 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT18 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010010";
attribute LC_LOW_BIT_POS_PROBE_OUT180 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT180 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110100";
attribute LC_LOW_BIT_POS_PROBE_OUT181 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT181 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110101";
attribute LC_LOW_BIT_POS_PROBE_OUT182 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT182 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110110";
attribute LC_LOW_BIT_POS_PROBE_OUT183 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT183 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110111";
attribute LC_LOW_BIT_POS_PROBE_OUT184 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT184 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111000";
attribute LC_LOW_BIT_POS_PROBE_OUT185 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT185 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111001";
attribute LC_LOW_BIT_POS_PROBE_OUT186 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT186 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111010";
attribute LC_LOW_BIT_POS_PROBE_OUT187 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT187 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111011";
attribute LC_LOW_BIT_POS_PROBE_OUT188 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT188 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111100";
attribute LC_LOW_BIT_POS_PROBE_OUT189 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT189 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111101";
attribute LC_LOW_BIT_POS_PROBE_OUT19 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT19 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010011";
attribute LC_LOW_BIT_POS_PROBE_OUT190 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT190 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111110";
attribute LC_LOW_BIT_POS_PROBE_OUT191 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT191 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111111";
attribute LC_LOW_BIT_POS_PROBE_OUT192 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT192 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000000";
attribute LC_LOW_BIT_POS_PROBE_OUT193 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT193 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000001";
attribute LC_LOW_BIT_POS_PROBE_OUT194 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT194 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000010";
attribute LC_LOW_BIT_POS_PROBE_OUT195 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT195 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000011";
attribute LC_LOW_BIT_POS_PROBE_OUT196 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT196 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000100";
attribute LC_LOW_BIT_POS_PROBE_OUT197 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT197 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000101";
attribute LC_LOW_BIT_POS_PROBE_OUT198 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT198 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000110";
attribute LC_LOW_BIT_POS_PROBE_OUT199 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT199 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000111";
attribute LC_LOW_BIT_POS_PROBE_OUT2 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000010";
attribute LC_LOW_BIT_POS_PROBE_OUT20 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT20 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010100";
attribute LC_LOW_BIT_POS_PROBE_OUT200 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT200 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001000";
attribute LC_LOW_BIT_POS_PROBE_OUT201 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT201 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001001";
attribute LC_LOW_BIT_POS_PROBE_OUT202 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT202 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001010";
attribute LC_LOW_BIT_POS_PROBE_OUT203 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT203 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001011";
attribute LC_LOW_BIT_POS_PROBE_OUT204 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT204 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001100";
attribute LC_LOW_BIT_POS_PROBE_OUT205 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT205 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001101";
attribute LC_LOW_BIT_POS_PROBE_OUT206 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT206 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001110";
attribute LC_LOW_BIT_POS_PROBE_OUT207 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT207 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001111";
attribute LC_LOW_BIT_POS_PROBE_OUT208 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT208 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010000";
attribute LC_LOW_BIT_POS_PROBE_OUT209 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT209 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010001";
attribute LC_LOW_BIT_POS_PROBE_OUT21 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT21 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010101";
attribute LC_LOW_BIT_POS_PROBE_OUT210 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT210 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010010";
attribute LC_LOW_BIT_POS_PROBE_OUT211 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT211 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010011";
attribute LC_LOW_BIT_POS_PROBE_OUT212 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT212 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010100";
attribute LC_LOW_BIT_POS_PROBE_OUT213 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT213 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010101";
attribute LC_LOW_BIT_POS_PROBE_OUT214 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT214 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010110";
attribute LC_LOW_BIT_POS_PROBE_OUT215 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT215 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010111";
attribute LC_LOW_BIT_POS_PROBE_OUT216 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT216 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011000";
attribute LC_LOW_BIT_POS_PROBE_OUT217 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT217 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011001";
attribute LC_LOW_BIT_POS_PROBE_OUT218 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT218 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011010";
attribute LC_LOW_BIT_POS_PROBE_OUT219 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT219 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011011";
attribute LC_LOW_BIT_POS_PROBE_OUT22 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT22 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010110";
attribute LC_LOW_BIT_POS_PROBE_OUT220 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT220 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011100";
attribute LC_LOW_BIT_POS_PROBE_OUT221 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT221 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011101";
attribute LC_LOW_BIT_POS_PROBE_OUT222 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT222 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011110";
attribute LC_LOW_BIT_POS_PROBE_OUT223 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT223 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011111";
attribute LC_LOW_BIT_POS_PROBE_OUT224 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT224 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100000";
attribute LC_LOW_BIT_POS_PROBE_OUT225 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT225 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100001";
attribute LC_LOW_BIT_POS_PROBE_OUT226 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT226 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100010";
attribute LC_LOW_BIT_POS_PROBE_OUT227 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT227 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100011";
attribute LC_LOW_BIT_POS_PROBE_OUT228 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT228 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100100";
attribute LC_LOW_BIT_POS_PROBE_OUT229 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT229 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100101";
attribute LC_LOW_BIT_POS_PROBE_OUT23 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT23 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010111";
attribute LC_LOW_BIT_POS_PROBE_OUT230 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT230 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100110";
attribute LC_LOW_BIT_POS_PROBE_OUT231 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT231 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100111";
attribute LC_LOW_BIT_POS_PROBE_OUT232 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT232 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101000";
attribute LC_LOW_BIT_POS_PROBE_OUT233 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT233 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101001";
attribute LC_LOW_BIT_POS_PROBE_OUT234 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT234 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101010";
attribute LC_LOW_BIT_POS_PROBE_OUT235 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT235 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101011";
attribute LC_LOW_BIT_POS_PROBE_OUT236 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT236 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101100";
attribute LC_LOW_BIT_POS_PROBE_OUT237 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT237 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101101";
attribute LC_LOW_BIT_POS_PROBE_OUT238 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT238 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101110";
attribute LC_LOW_BIT_POS_PROBE_OUT239 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT239 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101111";
attribute LC_LOW_BIT_POS_PROBE_OUT24 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT24 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011000";
attribute LC_LOW_BIT_POS_PROBE_OUT240 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT240 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110000";
attribute LC_LOW_BIT_POS_PROBE_OUT241 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT241 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110001";
attribute LC_LOW_BIT_POS_PROBE_OUT242 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT242 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110010";
attribute LC_LOW_BIT_POS_PROBE_OUT243 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT243 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110011";
attribute LC_LOW_BIT_POS_PROBE_OUT244 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT244 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110100";
attribute LC_LOW_BIT_POS_PROBE_OUT245 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT245 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110101";
attribute LC_LOW_BIT_POS_PROBE_OUT246 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT246 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110110";
attribute LC_LOW_BIT_POS_PROBE_OUT247 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT247 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110111";
attribute LC_LOW_BIT_POS_PROBE_OUT248 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT248 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111000";
attribute LC_LOW_BIT_POS_PROBE_OUT249 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT249 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111001";
attribute LC_LOW_BIT_POS_PROBE_OUT25 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT25 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011001";
attribute LC_LOW_BIT_POS_PROBE_OUT250 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT250 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111010";
attribute LC_LOW_BIT_POS_PROBE_OUT251 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT251 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111011";
attribute LC_LOW_BIT_POS_PROBE_OUT252 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT252 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111100";
attribute LC_LOW_BIT_POS_PROBE_OUT253 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT253 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111101";
attribute LC_LOW_BIT_POS_PROBE_OUT254 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT254 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111110";
attribute LC_LOW_BIT_POS_PROBE_OUT255 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT255 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111111";
attribute LC_LOW_BIT_POS_PROBE_OUT26 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT26 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011010";
attribute LC_LOW_BIT_POS_PROBE_OUT27 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT27 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011011";
attribute LC_LOW_BIT_POS_PROBE_OUT28 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT28 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011100";
attribute LC_LOW_BIT_POS_PROBE_OUT29 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT29 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011101";
attribute LC_LOW_BIT_POS_PROBE_OUT3 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000011";
attribute LC_LOW_BIT_POS_PROBE_OUT30 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT30 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011110";
attribute LC_LOW_BIT_POS_PROBE_OUT31 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT31 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011111";
attribute LC_LOW_BIT_POS_PROBE_OUT32 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT32 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100000";
attribute LC_LOW_BIT_POS_PROBE_OUT33 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT33 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100001";
attribute LC_LOW_BIT_POS_PROBE_OUT34 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT34 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100010";
attribute LC_LOW_BIT_POS_PROBE_OUT35 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT35 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100011";
attribute LC_LOW_BIT_POS_PROBE_OUT36 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT36 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100100";
attribute LC_LOW_BIT_POS_PROBE_OUT37 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT37 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100101";
attribute LC_LOW_BIT_POS_PROBE_OUT38 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT38 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100110";
attribute LC_LOW_BIT_POS_PROBE_OUT39 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT39 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100111";
attribute LC_LOW_BIT_POS_PROBE_OUT4 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000100";
attribute LC_LOW_BIT_POS_PROBE_OUT40 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT40 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101000";
attribute LC_LOW_BIT_POS_PROBE_OUT41 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT41 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101001";
attribute LC_LOW_BIT_POS_PROBE_OUT42 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT42 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101010";
attribute LC_LOW_BIT_POS_PROBE_OUT43 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT43 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101011";
attribute LC_LOW_BIT_POS_PROBE_OUT44 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT44 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101100";
attribute LC_LOW_BIT_POS_PROBE_OUT45 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT45 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101101";
attribute LC_LOW_BIT_POS_PROBE_OUT46 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT46 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101110";
attribute LC_LOW_BIT_POS_PROBE_OUT47 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT47 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101111";
attribute LC_LOW_BIT_POS_PROBE_OUT48 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT48 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110000";
attribute LC_LOW_BIT_POS_PROBE_OUT49 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT49 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110001";
attribute LC_LOW_BIT_POS_PROBE_OUT5 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT5 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000101";
attribute LC_LOW_BIT_POS_PROBE_OUT50 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT50 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110010";
attribute LC_LOW_BIT_POS_PROBE_OUT51 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT51 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110011";
attribute LC_LOW_BIT_POS_PROBE_OUT52 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT52 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110100";
attribute LC_LOW_BIT_POS_PROBE_OUT53 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT53 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110101";
attribute LC_LOW_BIT_POS_PROBE_OUT54 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT54 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110110";
attribute LC_LOW_BIT_POS_PROBE_OUT55 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT55 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110111";
attribute LC_LOW_BIT_POS_PROBE_OUT56 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT56 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111000";
attribute LC_LOW_BIT_POS_PROBE_OUT57 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT57 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111001";
attribute LC_LOW_BIT_POS_PROBE_OUT58 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT58 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111010";
attribute LC_LOW_BIT_POS_PROBE_OUT59 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT59 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111011";
attribute LC_LOW_BIT_POS_PROBE_OUT6 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT6 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000110";
attribute LC_LOW_BIT_POS_PROBE_OUT60 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT60 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111100";
attribute LC_LOW_BIT_POS_PROBE_OUT61 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT61 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111101";
attribute LC_LOW_BIT_POS_PROBE_OUT62 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT62 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111110";
attribute LC_LOW_BIT_POS_PROBE_OUT63 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT63 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111111";
attribute LC_LOW_BIT_POS_PROBE_OUT64 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT64 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000000";
attribute LC_LOW_BIT_POS_PROBE_OUT65 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT65 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000001";
attribute LC_LOW_BIT_POS_PROBE_OUT66 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT66 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000010";
attribute LC_LOW_BIT_POS_PROBE_OUT67 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT67 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000011";
attribute LC_LOW_BIT_POS_PROBE_OUT68 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT68 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000100";
attribute LC_LOW_BIT_POS_PROBE_OUT69 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT69 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000101";
attribute LC_LOW_BIT_POS_PROBE_OUT7 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT7 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000111";
attribute LC_LOW_BIT_POS_PROBE_OUT70 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT70 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000110";
attribute LC_LOW_BIT_POS_PROBE_OUT71 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT71 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000111";
attribute LC_LOW_BIT_POS_PROBE_OUT72 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT72 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001000";
attribute LC_LOW_BIT_POS_PROBE_OUT73 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT73 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001001";
attribute LC_LOW_BIT_POS_PROBE_OUT74 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT74 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001010";
attribute LC_LOW_BIT_POS_PROBE_OUT75 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT75 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001011";
attribute LC_LOW_BIT_POS_PROBE_OUT76 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT76 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001100";
attribute LC_LOW_BIT_POS_PROBE_OUT77 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT77 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001101";
attribute LC_LOW_BIT_POS_PROBE_OUT78 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT78 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001110";
attribute LC_LOW_BIT_POS_PROBE_OUT79 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT79 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001111";
attribute LC_LOW_BIT_POS_PROBE_OUT8 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT8 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001000";
attribute LC_LOW_BIT_POS_PROBE_OUT80 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT80 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010000";
attribute LC_LOW_BIT_POS_PROBE_OUT81 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT81 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010001";
attribute LC_LOW_BIT_POS_PROBE_OUT82 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT82 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010010";
attribute LC_LOW_BIT_POS_PROBE_OUT83 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT83 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010011";
attribute LC_LOW_BIT_POS_PROBE_OUT84 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT84 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010100";
attribute LC_LOW_BIT_POS_PROBE_OUT85 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT85 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010101";
attribute LC_LOW_BIT_POS_PROBE_OUT86 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT86 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010110";
attribute LC_LOW_BIT_POS_PROBE_OUT87 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT87 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010111";
attribute LC_LOW_BIT_POS_PROBE_OUT88 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT88 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011000";
attribute LC_LOW_BIT_POS_PROBE_OUT89 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT89 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011001";
attribute LC_LOW_BIT_POS_PROBE_OUT9 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT9 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001001";
attribute LC_LOW_BIT_POS_PROBE_OUT90 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT90 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011010";
attribute LC_LOW_BIT_POS_PROBE_OUT91 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT91 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011011";
attribute LC_LOW_BIT_POS_PROBE_OUT92 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT92 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011100";
attribute LC_LOW_BIT_POS_PROBE_OUT93 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT93 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011101";
attribute LC_LOW_BIT_POS_PROBE_OUT94 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT94 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011110";
attribute LC_LOW_BIT_POS_PROBE_OUT95 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT95 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011111";
attribute LC_LOW_BIT_POS_PROBE_OUT96 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT96 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100000";
attribute LC_LOW_BIT_POS_PROBE_OUT97 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT97 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100001";
attribute LC_LOW_BIT_POS_PROBE_OUT98 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT98 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100010";
attribute LC_LOW_BIT_POS_PROBE_OUT99 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT99 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100011";
attribute LC_PROBE_IN_WIDTH_STRING : string;
attribute LC_PROBE_IN_WIDTH_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_INIT_VAL_STRING : string;
attribute LC_PROBE_OUT_INIT_VAL_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_WIDTH_STRING : string;
attribute LC_PROBE_OUT_WIDTH_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_TOTAL_PROBE_IN_WIDTH : integer;
attribute LC_TOTAL_PROBE_IN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 4;
attribute LC_TOTAL_PROBE_OUT_WIDTH : integer;
attribute LC_TOTAL_PROBE_OUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute dont_touch : string;
attribute dont_touch of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "true";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio is
signal \<const0>\ : STD_LOGIC;
signal Bus_Data_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal DECODER_INST_n_1 : STD_LOGIC;
signal DECODER_INST_n_2 : STD_LOGIC;
signal DECODER_INST_n_3 : STD_LOGIC;
signal DECODER_INST_n_4 : STD_LOGIC;
signal bus_addr : STD_LOGIC_VECTOR ( 16 downto 0 );
signal bus_clk : STD_LOGIC;
attribute DONT_TOUCH_boolean : boolean;
attribute DONT_TOUCH_boolean of bus_clk : signal is std.standard.true;
signal \bus_data_int_reg_n_0_[0]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[10]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[11]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[12]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[13]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[14]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[15]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[2]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[3]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[4]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[5]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[6]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[7]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[8]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[9]\ : STD_LOGIC;
signal bus_den : STD_LOGIC;
signal bus_di : STD_LOGIC_VECTOR ( 15 downto 0 );
signal bus_do : STD_LOGIC_VECTOR ( 15 downto 0 );
signal bus_drdy : STD_LOGIC;
signal bus_dwe : STD_LOGIC;
signal bus_rst : STD_LOGIC;
signal p_0_in : STD_LOGIC;
attribute C_BUILD_REVISION of U_XSDB_SLAVE : label is 0;
attribute C_CORE_INFO1 of U_XSDB_SLAVE : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 of U_XSDB_SLAVE : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER of U_XSDB_SLAVE : label is 2;
attribute C_CORE_MINOR_VER of U_XSDB_SLAVE : label is 0;
attribute C_CORE_TYPE of U_XSDB_SLAVE : label is 2;
attribute C_CSE_DRV_VER of U_XSDB_SLAVE : label is 1;
attribute C_MAJOR_VERSION of U_XSDB_SLAVE : label is 2013;
attribute C_MINOR_VERSION of U_XSDB_SLAVE : label is 1;
attribute C_NEXT_SLAVE of U_XSDB_SLAVE : label is 0;
attribute C_PIPE_IFACE of U_XSDB_SLAVE : label is 0;
attribute C_USE_TEST_REG of U_XSDB_SLAVE : label is 1;
attribute C_XDEVICEFAMILY of U_XSDB_SLAVE : label is "kintex7";
attribute C_XSDB_SLAVE_TYPE of U_XSDB_SLAVE : label is 33;
attribute DONT_TOUCH_boolean of U_XSDB_SLAVE : label is std.standard.true;
begin
probe_out0(0) <= \<const0>\;
probe_out1(0) <= \<const0>\;
probe_out10(0) <= \<const0>\;
probe_out100(0) <= \<const0>\;
probe_out101(0) <= \<const0>\;
probe_out102(0) <= \<const0>\;
probe_out103(0) <= \<const0>\;
probe_out104(0) <= \<const0>\;
probe_out105(0) <= \<const0>\;
probe_out106(0) <= \<const0>\;
probe_out107(0) <= \<const0>\;
probe_out108(0) <= \<const0>\;
probe_out109(0) <= \<const0>\;
probe_out11(0) <= \<const0>\;
probe_out110(0) <= \<const0>\;
probe_out111(0) <= \<const0>\;
probe_out112(0) <= \<const0>\;
probe_out113(0) <= \<const0>\;
probe_out114(0) <= \<const0>\;
probe_out115(0) <= \<const0>\;
probe_out116(0) <= \<const0>\;
probe_out117(0) <= \<const0>\;
probe_out118(0) <= \<const0>\;
probe_out119(0) <= \<const0>\;
probe_out12(0) <= \<const0>\;
probe_out120(0) <= \<const0>\;
probe_out121(0) <= \<const0>\;
probe_out122(0) <= \<const0>\;
probe_out123(0) <= \<const0>\;
probe_out124(0) <= \<const0>\;
probe_out125(0) <= \<const0>\;
probe_out126(0) <= \<const0>\;
probe_out127(0) <= \<const0>\;
probe_out128(0) <= \<const0>\;
probe_out129(0) <= \<const0>\;
probe_out13(0) <= \<const0>\;
probe_out130(0) <= \<const0>\;
probe_out131(0) <= \<const0>\;
probe_out132(0) <= \<const0>\;
probe_out133(0) <= \<const0>\;
probe_out134(0) <= \<const0>\;
probe_out135(0) <= \<const0>\;
probe_out136(0) <= \<const0>\;
probe_out137(0) <= \<const0>\;
probe_out138(0) <= \<const0>\;
probe_out139(0) <= \<const0>\;
probe_out14(0) <= \<const0>\;
probe_out140(0) <= \<const0>\;
probe_out141(0) <= \<const0>\;
probe_out142(0) <= \<const0>\;
probe_out143(0) <= \<const0>\;
probe_out144(0) <= \<const0>\;
probe_out145(0) <= \<const0>\;
probe_out146(0) <= \<const0>\;
probe_out147(0) <= \<const0>\;
probe_out148(0) <= \<const0>\;
probe_out149(0) <= \<const0>\;
probe_out15(0) <= \<const0>\;
probe_out150(0) <= \<const0>\;
probe_out151(0) <= \<const0>\;
probe_out152(0) <= \<const0>\;
probe_out153(0) <= \<const0>\;
probe_out154(0) <= \<const0>\;
probe_out155(0) <= \<const0>\;
probe_out156(0) <= \<const0>\;
probe_out157(0) <= \<const0>\;
probe_out158(0) <= \<const0>\;
probe_out159(0) <= \<const0>\;
probe_out16(0) <= \<const0>\;
probe_out160(0) <= \<const0>\;
probe_out161(0) <= \<const0>\;
probe_out162(0) <= \<const0>\;
probe_out163(0) <= \<const0>\;
probe_out164(0) <= \<const0>\;
probe_out165(0) <= \<const0>\;
probe_out166(0) <= \<const0>\;
probe_out167(0) <= \<const0>\;
probe_out168(0) <= \<const0>\;
probe_out169(0) <= \<const0>\;
probe_out17(0) <= \<const0>\;
probe_out170(0) <= \<const0>\;
probe_out171(0) <= \<const0>\;
probe_out172(0) <= \<const0>\;
probe_out173(0) <= \<const0>\;
probe_out174(0) <= \<const0>\;
probe_out175(0) <= \<const0>\;
probe_out176(0) <= \<const0>\;
probe_out177(0) <= \<const0>\;
probe_out178(0) <= \<const0>\;
probe_out179(0) <= \<const0>\;
probe_out18(0) <= \<const0>\;
probe_out180(0) <= \<const0>\;
probe_out181(0) <= \<const0>\;
probe_out182(0) <= \<const0>\;
probe_out183(0) <= \<const0>\;
probe_out184(0) <= \<const0>\;
probe_out185(0) <= \<const0>\;
probe_out186(0) <= \<const0>\;
probe_out187(0) <= \<const0>\;
probe_out188(0) <= \<const0>\;
probe_out189(0) <= \<const0>\;
probe_out19(0) <= \<const0>\;
probe_out190(0) <= \<const0>\;
probe_out191(0) <= \<const0>\;
probe_out192(0) <= \<const0>\;
probe_out193(0) <= \<const0>\;
probe_out194(0) <= \<const0>\;
probe_out195(0) <= \<const0>\;
probe_out196(0) <= \<const0>\;
probe_out197(0) <= \<const0>\;
probe_out198(0) <= \<const0>\;
probe_out199(0) <= \<const0>\;
probe_out2(0) <= \<const0>\;
probe_out20(0) <= \<const0>\;
probe_out200(0) <= \<const0>\;
probe_out201(0) <= \<const0>\;
probe_out202(0) <= \<const0>\;
probe_out203(0) <= \<const0>\;
probe_out204(0) <= \<const0>\;
probe_out205(0) <= \<const0>\;
probe_out206(0) <= \<const0>\;
probe_out207(0) <= \<const0>\;
probe_out208(0) <= \<const0>\;
probe_out209(0) <= \<const0>\;
probe_out21(0) <= \<const0>\;
probe_out210(0) <= \<const0>\;
probe_out211(0) <= \<const0>\;
probe_out212(0) <= \<const0>\;
probe_out213(0) <= \<const0>\;
probe_out214(0) <= \<const0>\;
probe_out215(0) <= \<const0>\;
probe_out216(0) <= \<const0>\;
probe_out217(0) <= \<const0>\;
probe_out218(0) <= \<const0>\;
probe_out219(0) <= \<const0>\;
probe_out22(0) <= \<const0>\;
probe_out220(0) <= \<const0>\;
probe_out221(0) <= \<const0>\;
probe_out222(0) <= \<const0>\;
probe_out223(0) <= \<const0>\;
probe_out224(0) <= \<const0>\;
probe_out225(0) <= \<const0>\;
probe_out226(0) <= \<const0>\;
probe_out227(0) <= \<const0>\;
probe_out228(0) <= \<const0>\;
probe_out229(0) <= \<const0>\;
probe_out23(0) <= \<const0>\;
probe_out230(0) <= \<const0>\;
probe_out231(0) <= \<const0>\;
probe_out232(0) <= \<const0>\;
probe_out233(0) <= \<const0>\;
probe_out234(0) <= \<const0>\;
probe_out235(0) <= \<const0>\;
probe_out236(0) <= \<const0>\;
probe_out237(0) <= \<const0>\;
probe_out238(0) <= \<const0>\;
probe_out239(0) <= \<const0>\;
probe_out24(0) <= \<const0>\;
probe_out240(0) <= \<const0>\;
probe_out241(0) <= \<const0>\;
probe_out242(0) <= \<const0>\;
probe_out243(0) <= \<const0>\;
probe_out244(0) <= \<const0>\;
probe_out245(0) <= \<const0>\;
probe_out246(0) <= \<const0>\;
probe_out247(0) <= \<const0>\;
probe_out248(0) <= \<const0>\;
probe_out249(0) <= \<const0>\;
probe_out25(0) <= \<const0>\;
probe_out250(0) <= \<const0>\;
probe_out251(0) <= \<const0>\;
probe_out252(0) <= \<const0>\;
probe_out253(0) <= \<const0>\;
probe_out254(0) <= \<const0>\;
probe_out255(0) <= \<const0>\;
probe_out26(0) <= \<const0>\;
probe_out27(0) <= \<const0>\;
probe_out28(0) <= \<const0>\;
probe_out29(0) <= \<const0>\;
probe_out3(0) <= \<const0>\;
probe_out30(0) <= \<const0>\;
probe_out31(0) <= \<const0>\;
probe_out32(0) <= \<const0>\;
probe_out33(0) <= \<const0>\;
probe_out34(0) <= \<const0>\;
probe_out35(0) <= \<const0>\;
probe_out36(0) <= \<const0>\;
probe_out37(0) <= \<const0>\;
probe_out38(0) <= \<const0>\;
probe_out39(0) <= \<const0>\;
probe_out4(0) <= \<const0>\;
probe_out40(0) <= \<const0>\;
probe_out41(0) <= \<const0>\;
probe_out42(0) <= \<const0>\;
probe_out43(0) <= \<const0>\;
probe_out44(0) <= \<const0>\;
probe_out45(0) <= \<const0>\;
probe_out46(0) <= \<const0>\;
probe_out47(0) <= \<const0>\;
probe_out48(0) <= \<const0>\;
probe_out49(0) <= \<const0>\;
probe_out5(0) <= \<const0>\;
probe_out50(0) <= \<const0>\;
probe_out51(0) <= \<const0>\;
probe_out52(0) <= \<const0>\;
probe_out53(0) <= \<const0>\;
probe_out54(0) <= \<const0>\;
probe_out55(0) <= \<const0>\;
probe_out56(0) <= \<const0>\;
probe_out57(0) <= \<const0>\;
probe_out58(0) <= \<const0>\;
probe_out59(0) <= \<const0>\;
probe_out6(0) <= \<const0>\;
probe_out60(0) <= \<const0>\;
probe_out61(0) <= \<const0>\;
probe_out62(0) <= \<const0>\;
probe_out63(0) <= \<const0>\;
probe_out64(0) <= \<const0>\;
probe_out65(0) <= \<const0>\;
probe_out66(0) <= \<const0>\;
probe_out67(0) <= \<const0>\;
probe_out68(0) <= \<const0>\;
probe_out69(0) <= \<const0>\;
probe_out7(0) <= \<const0>\;
probe_out70(0) <= \<const0>\;
probe_out71(0) <= \<const0>\;
probe_out72(0) <= \<const0>\;
probe_out73(0) <= \<const0>\;
probe_out74(0) <= \<const0>\;
probe_out75(0) <= \<const0>\;
probe_out76(0) <= \<const0>\;
probe_out77(0) <= \<const0>\;
probe_out78(0) <= \<const0>\;
probe_out79(0) <= \<const0>\;
probe_out8(0) <= \<const0>\;
probe_out80(0) <= \<const0>\;
probe_out81(0) <= \<const0>\;
probe_out82(0) <= \<const0>\;
probe_out83(0) <= \<const0>\;
probe_out84(0) <= \<const0>\;
probe_out85(0) <= \<const0>\;
probe_out86(0) <= \<const0>\;
probe_out87(0) <= \<const0>\;
probe_out88(0) <= \<const0>\;
probe_out89(0) <= \<const0>\;
probe_out9(0) <= \<const0>\;
probe_out90(0) <= \<const0>\;
probe_out91(0) <= \<const0>\;
probe_out92(0) <= \<const0>\;
probe_out93(0) <= \<const0>\;
probe_out94(0) <= \<const0>\;
probe_out95(0) <= \<const0>\;
probe_out96(0) <= \<const0>\;
probe_out97(0) <= \<const0>\;
probe_out98(0) <= \<const0>\;
probe_out99(0) <= \<const0>\;
DECODER_INST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder
port map (
\Bus_Data_out_reg[11]\(11 downto 0) => Bus_Data_out(11 downto 0),
E(0) => DECODER_INST_n_4,
Q(15) => \bus_data_int_reg_n_0_[15]\,
Q(14) => \bus_data_int_reg_n_0_[14]\,
Q(13) => \bus_data_int_reg_n_0_[13]\,
Q(12) => \bus_data_int_reg_n_0_[12]\,
Q(11) => \bus_data_int_reg_n_0_[11]\,
Q(10) => \bus_data_int_reg_n_0_[10]\,
Q(9) => \bus_data_int_reg_n_0_[9]\,
Q(8) => \bus_data_int_reg_n_0_[8]\,
Q(7) => \bus_data_int_reg_n_0_[7]\,
Q(6) => \bus_data_int_reg_n_0_[6]\,
Q(5) => \bus_data_int_reg_n_0_[5]\,
Q(4) => \bus_data_int_reg_n_0_[4]\,
Q(3) => \bus_data_int_reg_n_0_[3]\,
Q(2) => \bus_data_int_reg_n_0_[2]\,
Q(1) => p_0_in,
Q(0) => \bus_data_int_reg_n_0_[0]\,
\out\ => bus_clk,
s_daddr_o(16 downto 0) => bus_addr(16 downto 0),
s_den_o => bus_den,
s_do_i(15 downto 0) => bus_do(15 downto 0),
s_drdy_i => bus_drdy,
s_dwe_o => bus_dwe,
s_rst_o => bus_rst,
\wr_en_reg[4]_0\ => DECODER_INST_n_1,
\wr_en_reg[4]_1\ => DECODER_INST_n_2,
\wr_en_reg[4]_2\ => DECODER_INST_n_3
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
PROBE_IN_INST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one
port map (
D(3) => probe_in3(0),
D(2) => probe_in2(0),
D(1) => probe_in1(0),
D(0) => probe_in0(0),
E(0) => DECODER_INST_n_4,
Q(11 downto 0) => Bus_Data_out(11 downto 0),
clk => clk,
\out\ => bus_clk,
s_daddr_o(2 downto 0) => bus_addr(2 downto 0),
s_den_o => bus_den,
s_dwe_o => bus_dwe,
s_rst_o => bus_rst,
\wr_en[4]_i_3\ => DECODER_INST_n_1,
\wr_en[4]_i_4\ => DECODER_INST_n_3,
\wr_en[4]_i_5\ => DECODER_INST_n_2
);
U_XSDB_SLAVE: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs
port map (
s_daddr_o(16 downto 0) => bus_addr(16 downto 0),
s_dclk_o => bus_clk,
s_den_o => bus_den,
s_di_o(15 downto 0) => bus_di(15 downto 0),
s_do_i(15 downto 0) => bus_do(15 downto 0),
s_drdy_i => bus_drdy,
s_dwe_o => bus_dwe,
s_rst_o => bus_rst,
sl_iport_i(36 downto 0) => sl_iport0(36 downto 0),
sl_oport_o(16 downto 0) => sl_oport0(16 downto 0)
);
\bus_data_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(0),
Q => \bus_data_int_reg_n_0_[0]\,
R => '0'
);
\bus_data_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(10),
Q => \bus_data_int_reg_n_0_[10]\,
R => '0'
);
\bus_data_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(11),
Q => \bus_data_int_reg_n_0_[11]\,
R => '0'
);
\bus_data_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(12),
Q => \bus_data_int_reg_n_0_[12]\,
R => '0'
);
\bus_data_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(13),
Q => \bus_data_int_reg_n_0_[13]\,
R => '0'
);
\bus_data_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(14),
Q => \bus_data_int_reg_n_0_[14]\,
R => '0'
);
\bus_data_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(15),
Q => \bus_data_int_reg_n_0_[15]\,
R => '0'
);
\bus_data_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(1),
Q => p_0_in,
R => '0'
);
\bus_data_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(2),
Q => \bus_data_int_reg_n_0_[2]\,
R => '0'
);
\bus_data_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(3),
Q => \bus_data_int_reg_n_0_[3]\,
R => '0'
);
\bus_data_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(4),
Q => \bus_data_int_reg_n_0_[4]\,
R => '0'
);
\bus_data_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(5),
Q => \bus_data_int_reg_n_0_[5]\,
R => '0'
);
\bus_data_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(6),
Q => \bus_data_int_reg_n_0_[6]\,
R => '0'
);
\bus_data_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(7),
Q => \bus_data_int_reg_n_0_[7]\,
R => '0'
);
\bus_data_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(8),
Q => \bus_data_int_reg_n_0_[8]\,
R => '0'
);
\bus_data_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(9),
Q => \bus_data_int_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clk : in STD_LOGIC;
probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in3 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "vio_0,vio,{}";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "vio,Vivado 2016.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_probe_out0_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out100_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out101_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out102_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out103_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out104_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out105_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out106_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out107_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out108_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out109_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out110_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out111_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out112_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out113_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out114_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out115_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out116_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out117_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out118_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out119_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out120_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out121_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out122_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out123_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out124_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out125_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out126_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out127_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out128_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out129_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out130_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out131_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out132_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out133_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out134_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out135_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out136_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out137_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out138_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out139_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out140_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out141_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out142_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out143_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out144_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out145_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out146_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out147_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out148_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out149_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out150_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out151_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out152_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out153_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out154_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out155_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out156_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out157_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out158_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out159_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out160_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out161_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out162_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out163_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out164_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out165_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out166_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out167_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out168_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out169_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out170_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out171_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out172_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out173_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out174_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out175_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out176_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out177_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out178_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out179_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out180_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out181_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out182_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out183_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out184_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out185_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out186_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out187_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out188_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out189_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out190_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out191_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out192_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out193_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out194_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out195_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out196_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out197_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out198_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out199_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out200_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out201_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out202_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out203_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out204_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out205_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out206_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out207_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out208_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out209_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out210_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out211_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out212_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out213_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out214_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out215_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out216_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out217_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out218_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out219_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out220_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out221_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out222_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out223_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out224_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out225_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out226_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out227_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out228_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out229_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out230_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out231_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out232_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out233_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out234_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out235_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out236_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out237_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out238_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out239_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out240_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out241_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out242_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out243_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out244_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out245_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out246_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out247_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out248_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out249_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out250_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out251_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out252_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out253_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out254_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out255_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out32_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out33_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out34_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out35_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out36_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out37_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out38_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out39_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out40_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out41_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out42_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out43_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out44_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out45_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out46_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out47_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out48_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out49_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out50_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out51_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out52_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out53_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out54_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out55_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out56_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out57_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out58_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out59_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out60_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out61_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out62_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out63_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out64_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out65_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out66_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out67_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out68_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out69_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out70_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out71_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out72_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out73_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out74_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out75_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out76_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out77_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out78_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out79_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out80_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out81_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out82_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out83_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out84_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out85_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out86_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out87_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out88_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out89_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out90_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out91_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out92_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out93_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out94_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out95_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out96_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out97_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out98_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out99_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_sl_oport0_UNCONNECTED : STD_LOGIC_VECTOR ( 16 downto 0 );
attribute C_BUILD_REVISION : integer;
attribute C_BUILD_REVISION of inst : label is 0;
attribute C_BUS_ADDR_WIDTH : integer;
attribute C_BUS_ADDR_WIDTH of inst : label is 17;
attribute C_BUS_DATA_WIDTH : integer;
attribute C_BUS_DATA_WIDTH of inst : label is 16;
attribute C_CORE_INFO1 : string;
attribute C_CORE_INFO1 of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 : string;
attribute C_CORE_INFO2 of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER : integer;
attribute C_CORE_MAJOR_VER of inst : label is 2;
attribute C_CORE_MINOR_ALPHA_VER : integer;
attribute C_CORE_MINOR_ALPHA_VER of inst : label is 97;
attribute C_CORE_MINOR_VER : integer;
attribute C_CORE_MINOR_VER of inst : label is 0;
attribute C_CORE_TYPE : integer;
attribute C_CORE_TYPE of inst : label is 2;
attribute C_CSE_DRV_VER : integer;
attribute C_CSE_DRV_VER of inst : label is 1;
attribute C_EN_PROBE_IN_ACTIVITY : integer;
attribute C_EN_PROBE_IN_ACTIVITY of inst : label is 1;
attribute C_EN_SYNCHRONIZATION : integer;
attribute C_EN_SYNCHRONIZATION of inst : label is 1;
attribute C_MAJOR_VERSION : integer;
attribute C_MAJOR_VERSION of inst : label is 2013;
attribute C_MAX_NUM_PROBE : integer;
attribute C_MAX_NUM_PROBE of inst : label is 256;
attribute C_MAX_WIDTH_PER_PROBE : integer;
attribute C_MAX_WIDTH_PER_PROBE of inst : label is 256;
attribute C_MINOR_VERSION : integer;
attribute C_MINOR_VERSION of inst : label is 1;
attribute C_NEXT_SLAVE : integer;
attribute C_NEXT_SLAVE of inst : label is 0;
attribute C_NUM_PROBE_IN : integer;
attribute C_NUM_PROBE_IN of inst : label is 4;
attribute C_NUM_PROBE_OUT : integer;
attribute C_NUM_PROBE_OUT of inst : label is 0;
attribute C_PIPE_IFACE : integer;
attribute C_PIPE_IFACE of inst : label is 0;
attribute C_PROBE_IN0_WIDTH : integer;
attribute C_PROBE_IN0_WIDTH of inst : label is 1;
attribute C_PROBE_IN100_WIDTH : integer;
attribute C_PROBE_IN100_WIDTH of inst : label is 1;
attribute C_PROBE_IN101_WIDTH : integer;
attribute C_PROBE_IN101_WIDTH of inst : label is 1;
attribute C_PROBE_IN102_WIDTH : integer;
attribute C_PROBE_IN102_WIDTH of inst : label is 1;
attribute C_PROBE_IN103_WIDTH : integer;
attribute C_PROBE_IN103_WIDTH of inst : label is 1;
attribute C_PROBE_IN104_WIDTH : integer;
attribute C_PROBE_IN104_WIDTH of inst : label is 1;
attribute C_PROBE_IN105_WIDTH : integer;
attribute C_PROBE_IN105_WIDTH of inst : label is 1;
attribute C_PROBE_IN106_WIDTH : integer;
attribute C_PROBE_IN106_WIDTH of inst : label is 1;
attribute C_PROBE_IN107_WIDTH : integer;
attribute C_PROBE_IN107_WIDTH of inst : label is 1;
attribute C_PROBE_IN108_WIDTH : integer;
attribute C_PROBE_IN108_WIDTH of inst : label is 1;
attribute C_PROBE_IN109_WIDTH : integer;
attribute C_PROBE_IN109_WIDTH of inst : label is 1;
attribute C_PROBE_IN10_WIDTH : integer;
attribute C_PROBE_IN10_WIDTH of inst : label is 1;
attribute C_PROBE_IN110_WIDTH : integer;
attribute C_PROBE_IN110_WIDTH of inst : label is 1;
attribute C_PROBE_IN111_WIDTH : integer;
attribute C_PROBE_IN111_WIDTH of inst : label is 1;
attribute C_PROBE_IN112_WIDTH : integer;
attribute C_PROBE_IN112_WIDTH of inst : label is 1;
attribute C_PROBE_IN113_WIDTH : integer;
attribute C_PROBE_IN113_WIDTH of inst : label is 1;
attribute C_PROBE_IN114_WIDTH : integer;
attribute C_PROBE_IN114_WIDTH of inst : label is 1;
attribute C_PROBE_IN115_WIDTH : integer;
attribute C_PROBE_IN115_WIDTH of inst : label is 1;
attribute C_PROBE_IN116_WIDTH : integer;
attribute C_PROBE_IN116_WIDTH of inst : label is 1;
attribute C_PROBE_IN117_WIDTH : integer;
attribute C_PROBE_IN117_WIDTH of inst : label is 1;
attribute C_PROBE_IN118_WIDTH : integer;
attribute C_PROBE_IN118_WIDTH of inst : label is 1;
attribute C_PROBE_IN119_WIDTH : integer;
attribute C_PROBE_IN119_WIDTH of inst : label is 1;
attribute C_PROBE_IN11_WIDTH : integer;
attribute C_PROBE_IN11_WIDTH of inst : label is 1;
attribute C_PROBE_IN120_WIDTH : integer;
attribute C_PROBE_IN120_WIDTH of inst : label is 1;
attribute C_PROBE_IN121_WIDTH : integer;
attribute C_PROBE_IN121_WIDTH of inst : label is 1;
attribute C_PROBE_IN122_WIDTH : integer;
attribute C_PROBE_IN122_WIDTH of inst : label is 1;
attribute C_PROBE_IN123_WIDTH : integer;
attribute C_PROBE_IN123_WIDTH of inst : label is 1;
attribute C_PROBE_IN124_WIDTH : integer;
attribute C_PROBE_IN124_WIDTH of inst : label is 1;
attribute C_PROBE_IN125_WIDTH : integer;
attribute C_PROBE_IN125_WIDTH of inst : label is 1;
attribute C_PROBE_IN126_WIDTH : integer;
attribute C_PROBE_IN126_WIDTH of inst : label is 1;
attribute C_PROBE_IN127_WIDTH : integer;
attribute C_PROBE_IN127_WIDTH of inst : label is 1;
attribute C_PROBE_IN128_WIDTH : integer;
attribute C_PROBE_IN128_WIDTH of inst : label is 1;
attribute C_PROBE_IN129_WIDTH : integer;
attribute C_PROBE_IN129_WIDTH of inst : label is 1;
attribute C_PROBE_IN12_WIDTH : integer;
attribute C_PROBE_IN12_WIDTH of inst : label is 1;
attribute C_PROBE_IN130_WIDTH : integer;
attribute C_PROBE_IN130_WIDTH of inst : label is 1;
attribute C_PROBE_IN131_WIDTH : integer;
attribute C_PROBE_IN131_WIDTH of inst : label is 1;
attribute C_PROBE_IN132_WIDTH : integer;
attribute C_PROBE_IN132_WIDTH of inst : label is 1;
attribute C_PROBE_IN133_WIDTH : integer;
attribute C_PROBE_IN133_WIDTH of inst : label is 1;
attribute C_PROBE_IN134_WIDTH : integer;
attribute C_PROBE_IN134_WIDTH of inst : label is 1;
attribute C_PROBE_IN135_WIDTH : integer;
attribute C_PROBE_IN135_WIDTH of inst : label is 1;
attribute C_PROBE_IN136_WIDTH : integer;
attribute C_PROBE_IN136_WIDTH of inst : label is 1;
attribute C_PROBE_IN137_WIDTH : integer;
attribute C_PROBE_IN137_WIDTH of inst : label is 1;
attribute C_PROBE_IN138_WIDTH : integer;
attribute C_PROBE_IN138_WIDTH of inst : label is 1;
attribute C_PROBE_IN139_WIDTH : integer;
attribute C_PROBE_IN139_WIDTH of inst : label is 1;
attribute C_PROBE_IN13_WIDTH : integer;
attribute C_PROBE_IN13_WIDTH of inst : label is 1;
attribute C_PROBE_IN140_WIDTH : integer;
attribute C_PROBE_IN140_WIDTH of inst : label is 1;
attribute C_PROBE_IN141_WIDTH : integer;
attribute C_PROBE_IN141_WIDTH of inst : label is 1;
attribute C_PROBE_IN142_WIDTH : integer;
attribute C_PROBE_IN142_WIDTH of inst : label is 1;
attribute C_PROBE_IN143_WIDTH : integer;
attribute C_PROBE_IN143_WIDTH of inst : label is 1;
attribute C_PROBE_IN144_WIDTH : integer;
attribute C_PROBE_IN144_WIDTH of inst : label is 1;
attribute C_PROBE_IN145_WIDTH : integer;
attribute C_PROBE_IN145_WIDTH of inst : label is 1;
attribute C_PROBE_IN146_WIDTH : integer;
attribute C_PROBE_IN146_WIDTH of inst : label is 1;
attribute C_PROBE_IN147_WIDTH : integer;
attribute C_PROBE_IN147_WIDTH of inst : label is 1;
attribute C_PROBE_IN148_WIDTH : integer;
attribute C_PROBE_IN148_WIDTH of inst : label is 1;
attribute C_PROBE_IN149_WIDTH : integer;
attribute C_PROBE_IN149_WIDTH of inst : label is 1;
attribute C_PROBE_IN14_WIDTH : integer;
attribute C_PROBE_IN14_WIDTH of inst : label is 1;
attribute C_PROBE_IN150_WIDTH : integer;
attribute C_PROBE_IN150_WIDTH of inst : label is 1;
attribute C_PROBE_IN151_WIDTH : integer;
attribute C_PROBE_IN151_WIDTH of inst : label is 1;
attribute C_PROBE_IN152_WIDTH : integer;
attribute C_PROBE_IN152_WIDTH of inst : label is 1;
attribute C_PROBE_IN153_WIDTH : integer;
attribute C_PROBE_IN153_WIDTH of inst : label is 1;
attribute C_PROBE_IN154_WIDTH : integer;
attribute C_PROBE_IN154_WIDTH of inst : label is 1;
attribute C_PROBE_IN155_WIDTH : integer;
attribute C_PROBE_IN155_WIDTH of inst : label is 1;
attribute C_PROBE_IN156_WIDTH : integer;
attribute C_PROBE_IN156_WIDTH of inst : label is 1;
attribute C_PROBE_IN157_WIDTH : integer;
attribute C_PROBE_IN157_WIDTH of inst : label is 1;
attribute C_PROBE_IN158_WIDTH : integer;
attribute C_PROBE_IN158_WIDTH of inst : label is 1;
attribute C_PROBE_IN159_WIDTH : integer;
attribute C_PROBE_IN159_WIDTH of inst : label is 1;
attribute C_PROBE_IN15_WIDTH : integer;
attribute C_PROBE_IN15_WIDTH of inst : label is 1;
attribute C_PROBE_IN160_WIDTH : integer;
attribute C_PROBE_IN160_WIDTH of inst : label is 1;
attribute C_PROBE_IN161_WIDTH : integer;
attribute C_PROBE_IN161_WIDTH of inst : label is 1;
attribute C_PROBE_IN162_WIDTH : integer;
attribute C_PROBE_IN162_WIDTH of inst : label is 1;
attribute C_PROBE_IN163_WIDTH : integer;
attribute C_PROBE_IN163_WIDTH of inst : label is 1;
attribute C_PROBE_IN164_WIDTH : integer;
attribute C_PROBE_IN164_WIDTH of inst : label is 1;
attribute C_PROBE_IN165_WIDTH : integer;
attribute C_PROBE_IN165_WIDTH of inst : label is 1;
attribute C_PROBE_IN166_WIDTH : integer;
attribute C_PROBE_IN166_WIDTH of inst : label is 1;
attribute C_PROBE_IN167_WIDTH : integer;
attribute C_PROBE_IN167_WIDTH of inst : label is 1;
attribute C_PROBE_IN168_WIDTH : integer;
attribute C_PROBE_IN168_WIDTH of inst : label is 1;
attribute C_PROBE_IN169_WIDTH : integer;
attribute C_PROBE_IN169_WIDTH of inst : label is 1;
attribute C_PROBE_IN16_WIDTH : integer;
attribute C_PROBE_IN16_WIDTH of inst : label is 1;
attribute C_PROBE_IN170_WIDTH : integer;
attribute C_PROBE_IN170_WIDTH of inst : label is 1;
attribute C_PROBE_IN171_WIDTH : integer;
attribute C_PROBE_IN171_WIDTH of inst : label is 1;
attribute C_PROBE_IN172_WIDTH : integer;
attribute C_PROBE_IN172_WIDTH of inst : label is 1;
attribute C_PROBE_IN173_WIDTH : integer;
attribute C_PROBE_IN173_WIDTH of inst : label is 1;
attribute C_PROBE_IN174_WIDTH : integer;
attribute C_PROBE_IN174_WIDTH of inst : label is 1;
attribute C_PROBE_IN175_WIDTH : integer;
attribute C_PROBE_IN175_WIDTH of inst : label is 1;
attribute C_PROBE_IN176_WIDTH : integer;
attribute C_PROBE_IN176_WIDTH of inst : label is 1;
attribute C_PROBE_IN177_WIDTH : integer;
attribute C_PROBE_IN177_WIDTH of inst : label is 1;
attribute C_PROBE_IN178_WIDTH : integer;
attribute C_PROBE_IN178_WIDTH of inst : label is 1;
attribute C_PROBE_IN179_WIDTH : integer;
attribute C_PROBE_IN179_WIDTH of inst : label is 1;
attribute C_PROBE_IN17_WIDTH : integer;
attribute C_PROBE_IN17_WIDTH of inst : label is 1;
attribute C_PROBE_IN180_WIDTH : integer;
attribute C_PROBE_IN180_WIDTH of inst : label is 1;
attribute C_PROBE_IN181_WIDTH : integer;
attribute C_PROBE_IN181_WIDTH of inst : label is 1;
attribute C_PROBE_IN182_WIDTH : integer;
attribute C_PROBE_IN182_WIDTH of inst : label is 1;
attribute C_PROBE_IN183_WIDTH : integer;
attribute C_PROBE_IN183_WIDTH of inst : label is 1;
attribute C_PROBE_IN184_WIDTH : integer;
attribute C_PROBE_IN184_WIDTH of inst : label is 1;
attribute C_PROBE_IN185_WIDTH : integer;
attribute C_PROBE_IN185_WIDTH of inst : label is 1;
attribute C_PROBE_IN186_WIDTH : integer;
attribute C_PROBE_IN186_WIDTH of inst : label is 1;
attribute C_PROBE_IN187_WIDTH : integer;
attribute C_PROBE_IN187_WIDTH of inst : label is 1;
attribute C_PROBE_IN188_WIDTH : integer;
attribute C_PROBE_IN188_WIDTH of inst : label is 1;
attribute C_PROBE_IN189_WIDTH : integer;
attribute C_PROBE_IN189_WIDTH of inst : label is 1;
attribute C_PROBE_IN18_WIDTH : integer;
attribute C_PROBE_IN18_WIDTH of inst : label is 1;
attribute C_PROBE_IN190_WIDTH : integer;
attribute C_PROBE_IN190_WIDTH of inst : label is 1;
attribute C_PROBE_IN191_WIDTH : integer;
attribute C_PROBE_IN191_WIDTH of inst : label is 1;
attribute C_PROBE_IN192_WIDTH : integer;
attribute C_PROBE_IN192_WIDTH of inst : label is 1;
attribute C_PROBE_IN193_WIDTH : integer;
attribute C_PROBE_IN193_WIDTH of inst : label is 1;
attribute C_PROBE_IN194_WIDTH : integer;
attribute C_PROBE_IN194_WIDTH of inst : label is 1;
attribute C_PROBE_IN195_WIDTH : integer;
attribute C_PROBE_IN195_WIDTH of inst : label is 1;
attribute C_PROBE_IN196_WIDTH : integer;
attribute C_PROBE_IN196_WIDTH of inst : label is 1;
attribute C_PROBE_IN197_WIDTH : integer;
attribute C_PROBE_IN197_WIDTH of inst : label is 1;
attribute C_PROBE_IN198_WIDTH : integer;
attribute C_PROBE_IN198_WIDTH of inst : label is 1;
attribute C_PROBE_IN199_WIDTH : integer;
attribute C_PROBE_IN199_WIDTH of inst : label is 1;
attribute C_PROBE_IN19_WIDTH : integer;
attribute C_PROBE_IN19_WIDTH of inst : label is 1;
attribute C_PROBE_IN1_WIDTH : integer;
attribute C_PROBE_IN1_WIDTH of inst : label is 1;
attribute C_PROBE_IN200_WIDTH : integer;
attribute C_PROBE_IN200_WIDTH of inst : label is 1;
attribute C_PROBE_IN201_WIDTH : integer;
attribute C_PROBE_IN201_WIDTH of inst : label is 1;
attribute C_PROBE_IN202_WIDTH : integer;
attribute C_PROBE_IN202_WIDTH of inst : label is 1;
attribute C_PROBE_IN203_WIDTH : integer;
attribute C_PROBE_IN203_WIDTH of inst : label is 1;
attribute C_PROBE_IN204_WIDTH : integer;
attribute C_PROBE_IN204_WIDTH of inst : label is 1;
attribute C_PROBE_IN205_WIDTH : integer;
attribute C_PROBE_IN205_WIDTH of inst : label is 1;
attribute C_PROBE_IN206_WIDTH : integer;
attribute C_PROBE_IN206_WIDTH of inst : label is 1;
attribute C_PROBE_IN207_WIDTH : integer;
attribute C_PROBE_IN207_WIDTH of inst : label is 1;
attribute C_PROBE_IN208_WIDTH : integer;
attribute C_PROBE_IN208_WIDTH of inst : label is 1;
attribute C_PROBE_IN209_WIDTH : integer;
attribute C_PROBE_IN209_WIDTH of inst : label is 1;
attribute C_PROBE_IN20_WIDTH : integer;
attribute C_PROBE_IN20_WIDTH of inst : label is 1;
attribute C_PROBE_IN210_WIDTH : integer;
attribute C_PROBE_IN210_WIDTH of inst : label is 1;
attribute C_PROBE_IN211_WIDTH : integer;
attribute C_PROBE_IN211_WIDTH of inst : label is 1;
attribute C_PROBE_IN212_WIDTH : integer;
attribute C_PROBE_IN212_WIDTH of inst : label is 1;
attribute C_PROBE_IN213_WIDTH : integer;
attribute C_PROBE_IN213_WIDTH of inst : label is 1;
attribute C_PROBE_IN214_WIDTH : integer;
attribute C_PROBE_IN214_WIDTH of inst : label is 1;
attribute C_PROBE_IN215_WIDTH : integer;
attribute C_PROBE_IN215_WIDTH of inst : label is 1;
attribute C_PROBE_IN216_WIDTH : integer;
attribute C_PROBE_IN216_WIDTH of inst : label is 1;
attribute C_PROBE_IN217_WIDTH : integer;
attribute C_PROBE_IN217_WIDTH of inst : label is 1;
attribute C_PROBE_IN218_WIDTH : integer;
attribute C_PROBE_IN218_WIDTH of inst : label is 1;
attribute C_PROBE_IN219_WIDTH : integer;
attribute C_PROBE_IN219_WIDTH of inst : label is 1;
attribute C_PROBE_IN21_WIDTH : integer;
attribute C_PROBE_IN21_WIDTH of inst : label is 1;
attribute C_PROBE_IN220_WIDTH : integer;
attribute C_PROBE_IN220_WIDTH of inst : label is 1;
attribute C_PROBE_IN221_WIDTH : integer;
attribute C_PROBE_IN221_WIDTH of inst : label is 1;
attribute C_PROBE_IN222_WIDTH : integer;
attribute C_PROBE_IN222_WIDTH of inst : label is 1;
attribute C_PROBE_IN223_WIDTH : integer;
attribute C_PROBE_IN223_WIDTH of inst : label is 1;
attribute C_PROBE_IN224_WIDTH : integer;
attribute C_PROBE_IN224_WIDTH of inst : label is 1;
attribute C_PROBE_IN225_WIDTH : integer;
attribute C_PROBE_IN225_WIDTH of inst : label is 1;
attribute C_PROBE_IN226_WIDTH : integer;
attribute C_PROBE_IN226_WIDTH of inst : label is 1;
attribute C_PROBE_IN227_WIDTH : integer;
attribute C_PROBE_IN227_WIDTH of inst : label is 1;
attribute C_PROBE_IN228_WIDTH : integer;
attribute C_PROBE_IN228_WIDTH of inst : label is 1;
attribute C_PROBE_IN229_WIDTH : integer;
attribute C_PROBE_IN229_WIDTH of inst : label is 1;
attribute C_PROBE_IN22_WIDTH : integer;
attribute C_PROBE_IN22_WIDTH of inst : label is 1;
attribute C_PROBE_IN230_WIDTH : integer;
attribute C_PROBE_IN230_WIDTH of inst : label is 1;
attribute C_PROBE_IN231_WIDTH : integer;
attribute C_PROBE_IN231_WIDTH of inst : label is 1;
attribute C_PROBE_IN232_WIDTH : integer;
attribute C_PROBE_IN232_WIDTH of inst : label is 1;
attribute C_PROBE_IN233_WIDTH : integer;
attribute C_PROBE_IN233_WIDTH of inst : label is 1;
attribute C_PROBE_IN234_WIDTH : integer;
attribute C_PROBE_IN234_WIDTH of inst : label is 1;
attribute C_PROBE_IN235_WIDTH : integer;
attribute C_PROBE_IN235_WIDTH of inst : label is 1;
attribute C_PROBE_IN236_WIDTH : integer;
attribute C_PROBE_IN236_WIDTH of inst : label is 1;
attribute C_PROBE_IN237_WIDTH : integer;
attribute C_PROBE_IN237_WIDTH of inst : label is 1;
attribute C_PROBE_IN238_WIDTH : integer;
attribute C_PROBE_IN238_WIDTH of inst : label is 1;
attribute C_PROBE_IN239_WIDTH : integer;
attribute C_PROBE_IN239_WIDTH of inst : label is 1;
attribute C_PROBE_IN23_WIDTH : integer;
attribute C_PROBE_IN23_WIDTH of inst : label is 1;
attribute C_PROBE_IN240_WIDTH : integer;
attribute C_PROBE_IN240_WIDTH of inst : label is 1;
attribute C_PROBE_IN241_WIDTH : integer;
attribute C_PROBE_IN241_WIDTH of inst : label is 1;
attribute C_PROBE_IN242_WIDTH : integer;
attribute C_PROBE_IN242_WIDTH of inst : label is 1;
attribute C_PROBE_IN243_WIDTH : integer;
attribute C_PROBE_IN243_WIDTH of inst : label is 1;
attribute C_PROBE_IN244_WIDTH : integer;
attribute C_PROBE_IN244_WIDTH of inst : label is 1;
attribute C_PROBE_IN245_WIDTH : integer;
attribute C_PROBE_IN245_WIDTH of inst : label is 1;
attribute C_PROBE_IN246_WIDTH : integer;
attribute C_PROBE_IN246_WIDTH of inst : label is 1;
attribute C_PROBE_IN247_WIDTH : integer;
attribute C_PROBE_IN247_WIDTH of inst : label is 1;
attribute C_PROBE_IN248_WIDTH : integer;
attribute C_PROBE_IN248_WIDTH of inst : label is 1;
attribute C_PROBE_IN249_WIDTH : integer;
attribute C_PROBE_IN249_WIDTH of inst : label is 1;
attribute C_PROBE_IN24_WIDTH : integer;
attribute C_PROBE_IN24_WIDTH of inst : label is 1;
attribute C_PROBE_IN250_WIDTH : integer;
attribute C_PROBE_IN250_WIDTH of inst : label is 1;
attribute C_PROBE_IN251_WIDTH : integer;
attribute C_PROBE_IN251_WIDTH of inst : label is 1;
attribute C_PROBE_IN252_WIDTH : integer;
attribute C_PROBE_IN252_WIDTH of inst : label is 1;
attribute C_PROBE_IN253_WIDTH : integer;
attribute C_PROBE_IN253_WIDTH of inst : label is 1;
attribute C_PROBE_IN254_WIDTH : integer;
attribute C_PROBE_IN254_WIDTH of inst : label is 1;
attribute C_PROBE_IN255_WIDTH : integer;
attribute C_PROBE_IN255_WIDTH of inst : label is 1;
attribute C_PROBE_IN25_WIDTH : integer;
attribute C_PROBE_IN25_WIDTH of inst : label is 1;
attribute C_PROBE_IN26_WIDTH : integer;
attribute C_PROBE_IN26_WIDTH of inst : label is 1;
attribute C_PROBE_IN27_WIDTH : integer;
attribute C_PROBE_IN27_WIDTH of inst : label is 1;
attribute C_PROBE_IN28_WIDTH : integer;
attribute C_PROBE_IN28_WIDTH of inst : label is 1;
attribute C_PROBE_IN29_WIDTH : integer;
attribute C_PROBE_IN29_WIDTH of inst : label is 1;
attribute C_PROBE_IN2_WIDTH : integer;
attribute C_PROBE_IN2_WIDTH of inst : label is 1;
attribute C_PROBE_IN30_WIDTH : integer;
attribute C_PROBE_IN30_WIDTH of inst : label is 1;
attribute C_PROBE_IN31_WIDTH : integer;
attribute C_PROBE_IN31_WIDTH of inst : label is 1;
attribute C_PROBE_IN32_WIDTH : integer;
attribute C_PROBE_IN32_WIDTH of inst : label is 1;
attribute C_PROBE_IN33_WIDTH : integer;
attribute C_PROBE_IN33_WIDTH of inst : label is 1;
attribute C_PROBE_IN34_WIDTH : integer;
attribute C_PROBE_IN34_WIDTH of inst : label is 1;
attribute C_PROBE_IN35_WIDTH : integer;
attribute C_PROBE_IN35_WIDTH of inst : label is 1;
attribute C_PROBE_IN36_WIDTH : integer;
attribute C_PROBE_IN36_WIDTH of inst : label is 1;
attribute C_PROBE_IN37_WIDTH : integer;
attribute C_PROBE_IN37_WIDTH of inst : label is 1;
attribute C_PROBE_IN38_WIDTH : integer;
attribute C_PROBE_IN38_WIDTH of inst : label is 1;
attribute C_PROBE_IN39_WIDTH : integer;
attribute C_PROBE_IN39_WIDTH of inst : label is 1;
attribute C_PROBE_IN3_WIDTH : integer;
attribute C_PROBE_IN3_WIDTH of inst : label is 1;
attribute C_PROBE_IN40_WIDTH : integer;
attribute C_PROBE_IN40_WIDTH of inst : label is 1;
attribute C_PROBE_IN41_WIDTH : integer;
attribute C_PROBE_IN41_WIDTH of inst : label is 1;
attribute C_PROBE_IN42_WIDTH : integer;
attribute C_PROBE_IN42_WIDTH of inst : label is 1;
attribute C_PROBE_IN43_WIDTH : integer;
attribute C_PROBE_IN43_WIDTH of inst : label is 1;
attribute C_PROBE_IN44_WIDTH : integer;
attribute C_PROBE_IN44_WIDTH of inst : label is 1;
attribute C_PROBE_IN45_WIDTH : integer;
attribute C_PROBE_IN45_WIDTH of inst : label is 1;
attribute C_PROBE_IN46_WIDTH : integer;
attribute C_PROBE_IN46_WIDTH of inst : label is 1;
attribute C_PROBE_IN47_WIDTH : integer;
attribute C_PROBE_IN47_WIDTH of inst : label is 1;
attribute C_PROBE_IN48_WIDTH : integer;
attribute C_PROBE_IN48_WIDTH of inst : label is 1;
attribute C_PROBE_IN49_WIDTH : integer;
attribute C_PROBE_IN49_WIDTH of inst : label is 1;
attribute C_PROBE_IN4_WIDTH : integer;
attribute C_PROBE_IN4_WIDTH of inst : label is 1;
attribute C_PROBE_IN50_WIDTH : integer;
attribute C_PROBE_IN50_WIDTH of inst : label is 1;
attribute C_PROBE_IN51_WIDTH : integer;
attribute C_PROBE_IN51_WIDTH of inst : label is 1;
attribute C_PROBE_IN52_WIDTH : integer;
attribute C_PROBE_IN52_WIDTH of inst : label is 1;
attribute C_PROBE_IN53_WIDTH : integer;
attribute C_PROBE_IN53_WIDTH of inst : label is 1;
attribute C_PROBE_IN54_WIDTH : integer;
attribute C_PROBE_IN54_WIDTH of inst : label is 1;
attribute C_PROBE_IN55_WIDTH : integer;
attribute C_PROBE_IN55_WIDTH of inst : label is 1;
attribute C_PROBE_IN56_WIDTH : integer;
attribute C_PROBE_IN56_WIDTH of inst : label is 1;
attribute C_PROBE_IN57_WIDTH : integer;
attribute C_PROBE_IN57_WIDTH of inst : label is 1;
attribute C_PROBE_IN58_WIDTH : integer;
attribute C_PROBE_IN58_WIDTH of inst : label is 1;
attribute C_PROBE_IN59_WIDTH : integer;
attribute C_PROBE_IN59_WIDTH of inst : label is 1;
attribute C_PROBE_IN5_WIDTH : integer;
attribute C_PROBE_IN5_WIDTH of inst : label is 1;
attribute C_PROBE_IN60_WIDTH : integer;
attribute C_PROBE_IN60_WIDTH of inst : label is 1;
attribute C_PROBE_IN61_WIDTH : integer;
attribute C_PROBE_IN61_WIDTH of inst : label is 1;
attribute C_PROBE_IN62_WIDTH : integer;
attribute C_PROBE_IN62_WIDTH of inst : label is 1;
attribute C_PROBE_IN63_WIDTH : integer;
attribute C_PROBE_IN63_WIDTH of inst : label is 1;
attribute C_PROBE_IN64_WIDTH : integer;
attribute C_PROBE_IN64_WIDTH of inst : label is 1;
attribute C_PROBE_IN65_WIDTH : integer;
attribute C_PROBE_IN65_WIDTH of inst : label is 1;
attribute C_PROBE_IN66_WIDTH : integer;
attribute C_PROBE_IN66_WIDTH of inst : label is 1;
attribute C_PROBE_IN67_WIDTH : integer;
attribute C_PROBE_IN67_WIDTH of inst : label is 1;
attribute C_PROBE_IN68_WIDTH : integer;
attribute C_PROBE_IN68_WIDTH of inst : label is 1;
attribute C_PROBE_IN69_WIDTH : integer;
attribute C_PROBE_IN69_WIDTH of inst : label is 1;
attribute C_PROBE_IN6_WIDTH : integer;
attribute C_PROBE_IN6_WIDTH of inst : label is 1;
attribute C_PROBE_IN70_WIDTH : integer;
attribute C_PROBE_IN70_WIDTH of inst : label is 1;
attribute C_PROBE_IN71_WIDTH : integer;
attribute C_PROBE_IN71_WIDTH of inst : label is 1;
attribute C_PROBE_IN72_WIDTH : integer;
attribute C_PROBE_IN72_WIDTH of inst : label is 1;
attribute C_PROBE_IN73_WIDTH : integer;
attribute C_PROBE_IN73_WIDTH of inst : label is 1;
attribute C_PROBE_IN74_WIDTH : integer;
attribute C_PROBE_IN74_WIDTH of inst : label is 1;
attribute C_PROBE_IN75_WIDTH : integer;
attribute C_PROBE_IN75_WIDTH of inst : label is 1;
attribute C_PROBE_IN76_WIDTH : integer;
attribute C_PROBE_IN76_WIDTH of inst : label is 1;
attribute C_PROBE_IN77_WIDTH : integer;
attribute C_PROBE_IN77_WIDTH of inst : label is 1;
attribute C_PROBE_IN78_WIDTH : integer;
attribute C_PROBE_IN78_WIDTH of inst : label is 1;
attribute C_PROBE_IN79_WIDTH : integer;
attribute C_PROBE_IN79_WIDTH of inst : label is 1;
attribute C_PROBE_IN7_WIDTH : integer;
attribute C_PROBE_IN7_WIDTH of inst : label is 1;
attribute C_PROBE_IN80_WIDTH : integer;
attribute C_PROBE_IN80_WIDTH of inst : label is 1;
attribute C_PROBE_IN81_WIDTH : integer;
attribute C_PROBE_IN81_WIDTH of inst : label is 1;
attribute C_PROBE_IN82_WIDTH : integer;
attribute C_PROBE_IN82_WIDTH of inst : label is 1;
attribute C_PROBE_IN83_WIDTH : integer;
attribute C_PROBE_IN83_WIDTH of inst : label is 1;
attribute C_PROBE_IN84_WIDTH : integer;
attribute C_PROBE_IN84_WIDTH of inst : label is 1;
attribute C_PROBE_IN85_WIDTH : integer;
attribute C_PROBE_IN85_WIDTH of inst : label is 1;
attribute C_PROBE_IN86_WIDTH : integer;
attribute C_PROBE_IN86_WIDTH of inst : label is 1;
attribute C_PROBE_IN87_WIDTH : integer;
attribute C_PROBE_IN87_WIDTH of inst : label is 1;
attribute C_PROBE_IN88_WIDTH : integer;
attribute C_PROBE_IN88_WIDTH of inst : label is 1;
attribute C_PROBE_IN89_WIDTH : integer;
attribute C_PROBE_IN89_WIDTH of inst : label is 1;
attribute C_PROBE_IN8_WIDTH : integer;
attribute C_PROBE_IN8_WIDTH of inst : label is 1;
attribute C_PROBE_IN90_WIDTH : integer;
attribute C_PROBE_IN90_WIDTH of inst : label is 1;
attribute C_PROBE_IN91_WIDTH : integer;
attribute C_PROBE_IN91_WIDTH of inst : label is 1;
attribute C_PROBE_IN92_WIDTH : integer;
attribute C_PROBE_IN92_WIDTH of inst : label is 1;
attribute C_PROBE_IN93_WIDTH : integer;
attribute C_PROBE_IN93_WIDTH of inst : label is 1;
attribute C_PROBE_IN94_WIDTH : integer;
attribute C_PROBE_IN94_WIDTH of inst : label is 1;
attribute C_PROBE_IN95_WIDTH : integer;
attribute C_PROBE_IN95_WIDTH of inst : label is 1;
attribute C_PROBE_IN96_WIDTH : integer;
attribute C_PROBE_IN96_WIDTH of inst : label is 1;
attribute C_PROBE_IN97_WIDTH : integer;
attribute C_PROBE_IN97_WIDTH of inst : label is 1;
attribute C_PROBE_IN98_WIDTH : integer;
attribute C_PROBE_IN98_WIDTH of inst : label is 1;
attribute C_PROBE_IN99_WIDTH : integer;
attribute C_PROBE_IN99_WIDTH of inst : label is 1;
attribute C_PROBE_IN9_WIDTH : integer;
attribute C_PROBE_IN9_WIDTH of inst : label is 1;
attribute C_PROBE_OUT0_INIT_VAL : string;
attribute C_PROBE_OUT0_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT0_WIDTH : integer;
attribute C_PROBE_OUT0_WIDTH of inst : label is 1;
attribute C_PROBE_OUT100_INIT_VAL : string;
attribute C_PROBE_OUT100_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT100_WIDTH : integer;
attribute C_PROBE_OUT100_WIDTH of inst : label is 1;
attribute C_PROBE_OUT101_INIT_VAL : string;
attribute C_PROBE_OUT101_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT101_WIDTH : integer;
attribute C_PROBE_OUT101_WIDTH of inst : label is 1;
attribute C_PROBE_OUT102_INIT_VAL : string;
attribute C_PROBE_OUT102_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT102_WIDTH : integer;
attribute C_PROBE_OUT102_WIDTH of inst : label is 1;
attribute C_PROBE_OUT103_INIT_VAL : string;
attribute C_PROBE_OUT103_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT103_WIDTH : integer;
attribute C_PROBE_OUT103_WIDTH of inst : label is 1;
attribute C_PROBE_OUT104_INIT_VAL : string;
attribute C_PROBE_OUT104_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT104_WIDTH : integer;
attribute C_PROBE_OUT104_WIDTH of inst : label is 1;
attribute C_PROBE_OUT105_INIT_VAL : string;
attribute C_PROBE_OUT105_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT105_WIDTH : integer;
attribute C_PROBE_OUT105_WIDTH of inst : label is 1;
attribute C_PROBE_OUT106_INIT_VAL : string;
attribute C_PROBE_OUT106_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT106_WIDTH : integer;
attribute C_PROBE_OUT106_WIDTH of inst : label is 1;
attribute C_PROBE_OUT107_INIT_VAL : string;
attribute C_PROBE_OUT107_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT107_WIDTH : integer;
attribute C_PROBE_OUT107_WIDTH of inst : label is 1;
attribute C_PROBE_OUT108_INIT_VAL : string;
attribute C_PROBE_OUT108_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT108_WIDTH : integer;
attribute C_PROBE_OUT108_WIDTH of inst : label is 1;
attribute C_PROBE_OUT109_INIT_VAL : string;
attribute C_PROBE_OUT109_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT109_WIDTH : integer;
attribute C_PROBE_OUT109_WIDTH of inst : label is 1;
attribute C_PROBE_OUT10_INIT_VAL : string;
attribute C_PROBE_OUT10_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT10_WIDTH : integer;
attribute C_PROBE_OUT10_WIDTH of inst : label is 1;
attribute C_PROBE_OUT110_INIT_VAL : string;
attribute C_PROBE_OUT110_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT110_WIDTH : integer;
attribute C_PROBE_OUT110_WIDTH of inst : label is 1;
attribute C_PROBE_OUT111_INIT_VAL : string;
attribute C_PROBE_OUT111_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT111_WIDTH : integer;
attribute C_PROBE_OUT111_WIDTH of inst : label is 1;
attribute C_PROBE_OUT112_INIT_VAL : string;
attribute C_PROBE_OUT112_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT112_WIDTH : integer;
attribute C_PROBE_OUT112_WIDTH of inst : label is 1;
attribute C_PROBE_OUT113_INIT_VAL : string;
attribute C_PROBE_OUT113_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT113_WIDTH : integer;
attribute C_PROBE_OUT113_WIDTH of inst : label is 1;
attribute C_PROBE_OUT114_INIT_VAL : string;
attribute C_PROBE_OUT114_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT114_WIDTH : integer;
attribute C_PROBE_OUT114_WIDTH of inst : label is 1;
attribute C_PROBE_OUT115_INIT_VAL : string;
attribute C_PROBE_OUT115_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT115_WIDTH : integer;
attribute C_PROBE_OUT115_WIDTH of inst : label is 1;
attribute C_PROBE_OUT116_INIT_VAL : string;
attribute C_PROBE_OUT116_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT116_WIDTH : integer;
attribute C_PROBE_OUT116_WIDTH of inst : label is 1;
attribute C_PROBE_OUT117_INIT_VAL : string;
attribute C_PROBE_OUT117_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT117_WIDTH : integer;
attribute C_PROBE_OUT117_WIDTH of inst : label is 1;
attribute C_PROBE_OUT118_INIT_VAL : string;
attribute C_PROBE_OUT118_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT118_WIDTH : integer;
attribute C_PROBE_OUT118_WIDTH of inst : label is 1;
attribute C_PROBE_OUT119_INIT_VAL : string;
attribute C_PROBE_OUT119_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT119_WIDTH : integer;
attribute C_PROBE_OUT119_WIDTH of inst : label is 1;
attribute C_PROBE_OUT11_INIT_VAL : string;
attribute C_PROBE_OUT11_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT11_WIDTH : integer;
attribute C_PROBE_OUT11_WIDTH of inst : label is 1;
attribute C_PROBE_OUT120_INIT_VAL : string;
attribute C_PROBE_OUT120_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT120_WIDTH : integer;
attribute C_PROBE_OUT120_WIDTH of inst : label is 1;
attribute C_PROBE_OUT121_INIT_VAL : string;
attribute C_PROBE_OUT121_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT121_WIDTH : integer;
attribute C_PROBE_OUT121_WIDTH of inst : label is 1;
attribute C_PROBE_OUT122_INIT_VAL : string;
attribute C_PROBE_OUT122_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT122_WIDTH : integer;
attribute C_PROBE_OUT122_WIDTH of inst : label is 1;
attribute C_PROBE_OUT123_INIT_VAL : string;
attribute C_PROBE_OUT123_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT123_WIDTH : integer;
attribute C_PROBE_OUT123_WIDTH of inst : label is 1;
attribute C_PROBE_OUT124_INIT_VAL : string;
attribute C_PROBE_OUT124_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT124_WIDTH : integer;
attribute C_PROBE_OUT124_WIDTH of inst : label is 1;
attribute C_PROBE_OUT125_INIT_VAL : string;
attribute C_PROBE_OUT125_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT125_WIDTH : integer;
attribute C_PROBE_OUT125_WIDTH of inst : label is 1;
attribute C_PROBE_OUT126_INIT_VAL : string;
attribute C_PROBE_OUT126_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT126_WIDTH : integer;
attribute C_PROBE_OUT126_WIDTH of inst : label is 1;
attribute C_PROBE_OUT127_INIT_VAL : string;
attribute C_PROBE_OUT127_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT127_WIDTH : integer;
attribute C_PROBE_OUT127_WIDTH of inst : label is 1;
attribute C_PROBE_OUT128_INIT_VAL : string;
attribute C_PROBE_OUT128_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT128_WIDTH : integer;
attribute C_PROBE_OUT128_WIDTH of inst : label is 1;
attribute C_PROBE_OUT129_INIT_VAL : string;
attribute C_PROBE_OUT129_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT129_WIDTH : integer;
attribute C_PROBE_OUT129_WIDTH of inst : label is 1;
attribute C_PROBE_OUT12_INIT_VAL : string;
attribute C_PROBE_OUT12_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT12_WIDTH : integer;
attribute C_PROBE_OUT12_WIDTH of inst : label is 1;
attribute C_PROBE_OUT130_INIT_VAL : string;
attribute C_PROBE_OUT130_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT130_WIDTH : integer;
attribute C_PROBE_OUT130_WIDTH of inst : label is 1;
attribute C_PROBE_OUT131_INIT_VAL : string;
attribute C_PROBE_OUT131_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT131_WIDTH : integer;
attribute C_PROBE_OUT131_WIDTH of inst : label is 1;
attribute C_PROBE_OUT132_INIT_VAL : string;
attribute C_PROBE_OUT132_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT132_WIDTH : integer;
attribute C_PROBE_OUT132_WIDTH of inst : label is 1;
attribute C_PROBE_OUT133_INIT_VAL : string;
attribute C_PROBE_OUT133_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT133_WIDTH : integer;
attribute C_PROBE_OUT133_WIDTH of inst : label is 1;
attribute C_PROBE_OUT134_INIT_VAL : string;
attribute C_PROBE_OUT134_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT134_WIDTH : integer;
attribute C_PROBE_OUT134_WIDTH of inst : label is 1;
attribute C_PROBE_OUT135_INIT_VAL : string;
attribute C_PROBE_OUT135_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT135_WIDTH : integer;
attribute C_PROBE_OUT135_WIDTH of inst : label is 1;
attribute C_PROBE_OUT136_INIT_VAL : string;
attribute C_PROBE_OUT136_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT136_WIDTH : integer;
attribute C_PROBE_OUT136_WIDTH of inst : label is 1;
attribute C_PROBE_OUT137_INIT_VAL : string;
attribute C_PROBE_OUT137_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT137_WIDTH : integer;
attribute C_PROBE_OUT137_WIDTH of inst : label is 1;
attribute C_PROBE_OUT138_INIT_VAL : string;
attribute C_PROBE_OUT138_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT138_WIDTH : integer;
attribute C_PROBE_OUT138_WIDTH of inst : label is 1;
attribute C_PROBE_OUT139_INIT_VAL : string;
attribute C_PROBE_OUT139_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT139_WIDTH : integer;
attribute C_PROBE_OUT139_WIDTH of inst : label is 1;
attribute C_PROBE_OUT13_INIT_VAL : string;
attribute C_PROBE_OUT13_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT13_WIDTH : integer;
attribute C_PROBE_OUT13_WIDTH of inst : label is 1;
attribute C_PROBE_OUT140_INIT_VAL : string;
attribute C_PROBE_OUT140_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT140_WIDTH : integer;
attribute C_PROBE_OUT140_WIDTH of inst : label is 1;
attribute C_PROBE_OUT141_INIT_VAL : string;
attribute C_PROBE_OUT141_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT141_WIDTH : integer;
attribute C_PROBE_OUT141_WIDTH of inst : label is 1;
attribute C_PROBE_OUT142_INIT_VAL : string;
attribute C_PROBE_OUT142_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT142_WIDTH : integer;
attribute C_PROBE_OUT142_WIDTH of inst : label is 1;
attribute C_PROBE_OUT143_INIT_VAL : string;
attribute C_PROBE_OUT143_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT143_WIDTH : integer;
attribute C_PROBE_OUT143_WIDTH of inst : label is 1;
attribute C_PROBE_OUT144_INIT_VAL : string;
attribute C_PROBE_OUT144_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT144_WIDTH : integer;
attribute C_PROBE_OUT144_WIDTH of inst : label is 1;
attribute C_PROBE_OUT145_INIT_VAL : string;
attribute C_PROBE_OUT145_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT145_WIDTH : integer;
attribute C_PROBE_OUT145_WIDTH of inst : label is 1;
attribute C_PROBE_OUT146_INIT_VAL : string;
attribute C_PROBE_OUT146_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT146_WIDTH : integer;
attribute C_PROBE_OUT146_WIDTH of inst : label is 1;
attribute C_PROBE_OUT147_INIT_VAL : string;
attribute C_PROBE_OUT147_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT147_WIDTH : integer;
attribute C_PROBE_OUT147_WIDTH of inst : label is 1;
attribute C_PROBE_OUT148_INIT_VAL : string;
attribute C_PROBE_OUT148_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT148_WIDTH : integer;
attribute C_PROBE_OUT148_WIDTH of inst : label is 1;
attribute C_PROBE_OUT149_INIT_VAL : string;
attribute C_PROBE_OUT149_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT149_WIDTH : integer;
attribute C_PROBE_OUT149_WIDTH of inst : label is 1;
attribute C_PROBE_OUT14_INIT_VAL : string;
attribute C_PROBE_OUT14_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT14_WIDTH : integer;
attribute C_PROBE_OUT14_WIDTH of inst : label is 1;
attribute C_PROBE_OUT150_INIT_VAL : string;
attribute C_PROBE_OUT150_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT150_WIDTH : integer;
attribute C_PROBE_OUT150_WIDTH of inst : label is 1;
attribute C_PROBE_OUT151_INIT_VAL : string;
attribute C_PROBE_OUT151_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT151_WIDTH : integer;
attribute C_PROBE_OUT151_WIDTH of inst : label is 1;
attribute C_PROBE_OUT152_INIT_VAL : string;
attribute C_PROBE_OUT152_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT152_WIDTH : integer;
attribute C_PROBE_OUT152_WIDTH of inst : label is 1;
attribute C_PROBE_OUT153_INIT_VAL : string;
attribute C_PROBE_OUT153_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT153_WIDTH : integer;
attribute C_PROBE_OUT153_WIDTH of inst : label is 1;
attribute C_PROBE_OUT154_INIT_VAL : string;
attribute C_PROBE_OUT154_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT154_WIDTH : integer;
attribute C_PROBE_OUT154_WIDTH of inst : label is 1;
attribute C_PROBE_OUT155_INIT_VAL : string;
attribute C_PROBE_OUT155_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT155_WIDTH : integer;
attribute C_PROBE_OUT155_WIDTH of inst : label is 1;
attribute C_PROBE_OUT156_INIT_VAL : string;
attribute C_PROBE_OUT156_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT156_WIDTH : integer;
attribute C_PROBE_OUT156_WIDTH of inst : label is 1;
attribute C_PROBE_OUT157_INIT_VAL : string;
attribute C_PROBE_OUT157_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT157_WIDTH : integer;
attribute C_PROBE_OUT157_WIDTH of inst : label is 1;
attribute C_PROBE_OUT158_INIT_VAL : string;
attribute C_PROBE_OUT158_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT158_WIDTH : integer;
attribute C_PROBE_OUT158_WIDTH of inst : label is 1;
attribute C_PROBE_OUT159_INIT_VAL : string;
attribute C_PROBE_OUT159_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT159_WIDTH : integer;
attribute C_PROBE_OUT159_WIDTH of inst : label is 1;
attribute C_PROBE_OUT15_INIT_VAL : string;
attribute C_PROBE_OUT15_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT15_WIDTH : integer;
attribute C_PROBE_OUT15_WIDTH of inst : label is 1;
attribute C_PROBE_OUT160_INIT_VAL : string;
attribute C_PROBE_OUT160_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT160_WIDTH : integer;
attribute C_PROBE_OUT160_WIDTH of inst : label is 1;
attribute C_PROBE_OUT161_INIT_VAL : string;
attribute C_PROBE_OUT161_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT161_WIDTH : integer;
attribute C_PROBE_OUT161_WIDTH of inst : label is 1;
attribute C_PROBE_OUT162_INIT_VAL : string;
attribute C_PROBE_OUT162_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT162_WIDTH : integer;
attribute C_PROBE_OUT162_WIDTH of inst : label is 1;
attribute C_PROBE_OUT163_INIT_VAL : string;
attribute C_PROBE_OUT163_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT163_WIDTH : integer;
attribute C_PROBE_OUT163_WIDTH of inst : label is 1;
attribute C_PROBE_OUT164_INIT_VAL : string;
attribute C_PROBE_OUT164_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT164_WIDTH : integer;
attribute C_PROBE_OUT164_WIDTH of inst : label is 1;
attribute C_PROBE_OUT165_INIT_VAL : string;
attribute C_PROBE_OUT165_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT165_WIDTH : integer;
attribute C_PROBE_OUT165_WIDTH of inst : label is 1;
attribute C_PROBE_OUT166_INIT_VAL : string;
attribute C_PROBE_OUT166_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT166_WIDTH : integer;
attribute C_PROBE_OUT166_WIDTH of inst : label is 1;
attribute C_PROBE_OUT167_INIT_VAL : string;
attribute C_PROBE_OUT167_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT167_WIDTH : integer;
attribute C_PROBE_OUT167_WIDTH of inst : label is 1;
attribute C_PROBE_OUT168_INIT_VAL : string;
attribute C_PROBE_OUT168_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT168_WIDTH : integer;
attribute C_PROBE_OUT168_WIDTH of inst : label is 1;
attribute C_PROBE_OUT169_INIT_VAL : string;
attribute C_PROBE_OUT169_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT169_WIDTH : integer;
attribute C_PROBE_OUT169_WIDTH of inst : label is 1;
attribute C_PROBE_OUT16_INIT_VAL : string;
attribute C_PROBE_OUT16_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT16_WIDTH : integer;
attribute C_PROBE_OUT16_WIDTH of inst : label is 1;
attribute C_PROBE_OUT170_INIT_VAL : string;
attribute C_PROBE_OUT170_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT170_WIDTH : integer;
attribute C_PROBE_OUT170_WIDTH of inst : label is 1;
attribute C_PROBE_OUT171_INIT_VAL : string;
attribute C_PROBE_OUT171_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT171_WIDTH : integer;
attribute C_PROBE_OUT171_WIDTH of inst : label is 1;
attribute C_PROBE_OUT172_INIT_VAL : string;
attribute C_PROBE_OUT172_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT172_WIDTH : integer;
attribute C_PROBE_OUT172_WIDTH of inst : label is 1;
attribute C_PROBE_OUT173_INIT_VAL : string;
attribute C_PROBE_OUT173_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT173_WIDTH : integer;
attribute C_PROBE_OUT173_WIDTH of inst : label is 1;
attribute C_PROBE_OUT174_INIT_VAL : string;
attribute C_PROBE_OUT174_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT174_WIDTH : integer;
attribute C_PROBE_OUT174_WIDTH of inst : label is 1;
attribute C_PROBE_OUT175_INIT_VAL : string;
attribute C_PROBE_OUT175_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT175_WIDTH : integer;
attribute C_PROBE_OUT175_WIDTH of inst : label is 1;
attribute C_PROBE_OUT176_INIT_VAL : string;
attribute C_PROBE_OUT176_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT176_WIDTH : integer;
attribute C_PROBE_OUT176_WIDTH of inst : label is 1;
attribute C_PROBE_OUT177_INIT_VAL : string;
attribute C_PROBE_OUT177_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT177_WIDTH : integer;
attribute C_PROBE_OUT177_WIDTH of inst : label is 1;
attribute C_PROBE_OUT178_INIT_VAL : string;
attribute C_PROBE_OUT178_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT178_WIDTH : integer;
attribute C_PROBE_OUT178_WIDTH of inst : label is 1;
attribute C_PROBE_OUT179_INIT_VAL : string;
attribute C_PROBE_OUT179_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT179_WIDTH : integer;
attribute C_PROBE_OUT179_WIDTH of inst : label is 1;
attribute C_PROBE_OUT17_INIT_VAL : string;
attribute C_PROBE_OUT17_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT17_WIDTH : integer;
attribute C_PROBE_OUT17_WIDTH of inst : label is 1;
attribute C_PROBE_OUT180_INIT_VAL : string;
attribute C_PROBE_OUT180_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT180_WIDTH : integer;
attribute C_PROBE_OUT180_WIDTH of inst : label is 1;
attribute C_PROBE_OUT181_INIT_VAL : string;
attribute C_PROBE_OUT181_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT181_WIDTH : integer;
attribute C_PROBE_OUT181_WIDTH of inst : label is 1;
attribute C_PROBE_OUT182_INIT_VAL : string;
attribute C_PROBE_OUT182_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT182_WIDTH : integer;
attribute C_PROBE_OUT182_WIDTH of inst : label is 1;
attribute C_PROBE_OUT183_INIT_VAL : string;
attribute C_PROBE_OUT183_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT183_WIDTH : integer;
attribute C_PROBE_OUT183_WIDTH of inst : label is 1;
attribute C_PROBE_OUT184_INIT_VAL : string;
attribute C_PROBE_OUT184_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT184_WIDTH : integer;
attribute C_PROBE_OUT184_WIDTH of inst : label is 1;
attribute C_PROBE_OUT185_INIT_VAL : string;
attribute C_PROBE_OUT185_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT185_WIDTH : integer;
attribute C_PROBE_OUT185_WIDTH of inst : label is 1;
attribute C_PROBE_OUT186_INIT_VAL : string;
attribute C_PROBE_OUT186_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT186_WIDTH : integer;
attribute C_PROBE_OUT186_WIDTH of inst : label is 1;
attribute C_PROBE_OUT187_INIT_VAL : string;
attribute C_PROBE_OUT187_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT187_WIDTH : integer;
attribute C_PROBE_OUT187_WIDTH of inst : label is 1;
attribute C_PROBE_OUT188_INIT_VAL : string;
attribute C_PROBE_OUT188_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT188_WIDTH : integer;
attribute C_PROBE_OUT188_WIDTH of inst : label is 1;
attribute C_PROBE_OUT189_INIT_VAL : string;
attribute C_PROBE_OUT189_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT189_WIDTH : integer;
attribute C_PROBE_OUT189_WIDTH of inst : label is 1;
attribute C_PROBE_OUT18_INIT_VAL : string;
attribute C_PROBE_OUT18_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT18_WIDTH : integer;
attribute C_PROBE_OUT18_WIDTH of inst : label is 1;
attribute C_PROBE_OUT190_INIT_VAL : string;
attribute C_PROBE_OUT190_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT190_WIDTH : integer;
attribute C_PROBE_OUT190_WIDTH of inst : label is 1;
attribute C_PROBE_OUT191_INIT_VAL : string;
attribute C_PROBE_OUT191_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT191_WIDTH : integer;
attribute C_PROBE_OUT191_WIDTH of inst : label is 1;
attribute C_PROBE_OUT192_INIT_VAL : string;
attribute C_PROBE_OUT192_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT192_WIDTH : integer;
attribute C_PROBE_OUT192_WIDTH of inst : label is 1;
attribute C_PROBE_OUT193_INIT_VAL : string;
attribute C_PROBE_OUT193_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT193_WIDTH : integer;
attribute C_PROBE_OUT193_WIDTH of inst : label is 1;
attribute C_PROBE_OUT194_INIT_VAL : string;
attribute C_PROBE_OUT194_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT194_WIDTH : integer;
attribute C_PROBE_OUT194_WIDTH of inst : label is 1;
attribute C_PROBE_OUT195_INIT_VAL : string;
attribute C_PROBE_OUT195_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT195_WIDTH : integer;
attribute C_PROBE_OUT195_WIDTH of inst : label is 1;
attribute C_PROBE_OUT196_INIT_VAL : string;
attribute C_PROBE_OUT196_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT196_WIDTH : integer;
attribute C_PROBE_OUT196_WIDTH of inst : label is 1;
attribute C_PROBE_OUT197_INIT_VAL : string;
attribute C_PROBE_OUT197_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT197_WIDTH : integer;
attribute C_PROBE_OUT197_WIDTH of inst : label is 1;
attribute C_PROBE_OUT198_INIT_VAL : string;
attribute C_PROBE_OUT198_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT198_WIDTH : integer;
attribute C_PROBE_OUT198_WIDTH of inst : label is 1;
attribute C_PROBE_OUT199_INIT_VAL : string;
attribute C_PROBE_OUT199_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT199_WIDTH : integer;
attribute C_PROBE_OUT199_WIDTH of inst : label is 1;
attribute C_PROBE_OUT19_INIT_VAL : string;
attribute C_PROBE_OUT19_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT19_WIDTH : integer;
attribute C_PROBE_OUT19_WIDTH of inst : label is 1;
attribute C_PROBE_OUT1_INIT_VAL : string;
attribute C_PROBE_OUT1_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT1_WIDTH : integer;
attribute C_PROBE_OUT1_WIDTH of inst : label is 1;
attribute C_PROBE_OUT200_INIT_VAL : string;
attribute C_PROBE_OUT200_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT200_WIDTH : integer;
attribute C_PROBE_OUT200_WIDTH of inst : label is 1;
attribute C_PROBE_OUT201_INIT_VAL : string;
attribute C_PROBE_OUT201_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT201_WIDTH : integer;
attribute C_PROBE_OUT201_WIDTH of inst : label is 1;
attribute C_PROBE_OUT202_INIT_VAL : string;
attribute C_PROBE_OUT202_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT202_WIDTH : integer;
attribute C_PROBE_OUT202_WIDTH of inst : label is 1;
attribute C_PROBE_OUT203_INIT_VAL : string;
attribute C_PROBE_OUT203_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT203_WIDTH : integer;
attribute C_PROBE_OUT203_WIDTH of inst : label is 1;
attribute C_PROBE_OUT204_INIT_VAL : string;
attribute C_PROBE_OUT204_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT204_WIDTH : integer;
attribute C_PROBE_OUT204_WIDTH of inst : label is 1;
attribute C_PROBE_OUT205_INIT_VAL : string;
attribute C_PROBE_OUT205_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT205_WIDTH : integer;
attribute C_PROBE_OUT205_WIDTH of inst : label is 1;
attribute C_PROBE_OUT206_INIT_VAL : string;
attribute C_PROBE_OUT206_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT206_WIDTH : integer;
attribute C_PROBE_OUT206_WIDTH of inst : label is 1;
attribute C_PROBE_OUT207_INIT_VAL : string;
attribute C_PROBE_OUT207_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT207_WIDTH : integer;
attribute C_PROBE_OUT207_WIDTH of inst : label is 1;
attribute C_PROBE_OUT208_INIT_VAL : string;
attribute C_PROBE_OUT208_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT208_WIDTH : integer;
attribute C_PROBE_OUT208_WIDTH of inst : label is 1;
attribute C_PROBE_OUT209_INIT_VAL : string;
attribute C_PROBE_OUT209_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT209_WIDTH : integer;
attribute C_PROBE_OUT209_WIDTH of inst : label is 1;
attribute C_PROBE_OUT20_INIT_VAL : string;
attribute C_PROBE_OUT20_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT20_WIDTH : integer;
attribute C_PROBE_OUT20_WIDTH of inst : label is 1;
attribute C_PROBE_OUT210_INIT_VAL : string;
attribute C_PROBE_OUT210_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT210_WIDTH : integer;
attribute C_PROBE_OUT210_WIDTH of inst : label is 1;
attribute C_PROBE_OUT211_INIT_VAL : string;
attribute C_PROBE_OUT211_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT211_WIDTH : integer;
attribute C_PROBE_OUT211_WIDTH of inst : label is 1;
attribute C_PROBE_OUT212_INIT_VAL : string;
attribute C_PROBE_OUT212_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT212_WIDTH : integer;
attribute C_PROBE_OUT212_WIDTH of inst : label is 1;
attribute C_PROBE_OUT213_INIT_VAL : string;
attribute C_PROBE_OUT213_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT213_WIDTH : integer;
attribute C_PROBE_OUT213_WIDTH of inst : label is 1;
attribute C_PROBE_OUT214_INIT_VAL : string;
attribute C_PROBE_OUT214_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT214_WIDTH : integer;
attribute C_PROBE_OUT214_WIDTH of inst : label is 1;
attribute C_PROBE_OUT215_INIT_VAL : string;
attribute C_PROBE_OUT215_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT215_WIDTH : integer;
attribute C_PROBE_OUT215_WIDTH of inst : label is 1;
attribute C_PROBE_OUT216_INIT_VAL : string;
attribute C_PROBE_OUT216_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT216_WIDTH : integer;
attribute C_PROBE_OUT216_WIDTH of inst : label is 1;
attribute C_PROBE_OUT217_INIT_VAL : string;
attribute C_PROBE_OUT217_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT217_WIDTH : integer;
attribute C_PROBE_OUT217_WIDTH of inst : label is 1;
attribute C_PROBE_OUT218_INIT_VAL : string;
attribute C_PROBE_OUT218_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT218_WIDTH : integer;
attribute C_PROBE_OUT218_WIDTH of inst : label is 1;
attribute C_PROBE_OUT219_INIT_VAL : string;
attribute C_PROBE_OUT219_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT219_WIDTH : integer;
attribute C_PROBE_OUT219_WIDTH of inst : label is 1;
attribute C_PROBE_OUT21_INIT_VAL : string;
attribute C_PROBE_OUT21_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT21_WIDTH : integer;
attribute C_PROBE_OUT21_WIDTH of inst : label is 1;
attribute C_PROBE_OUT220_INIT_VAL : string;
attribute C_PROBE_OUT220_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT220_WIDTH : integer;
attribute C_PROBE_OUT220_WIDTH of inst : label is 1;
attribute C_PROBE_OUT221_INIT_VAL : string;
attribute C_PROBE_OUT221_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT221_WIDTH : integer;
attribute C_PROBE_OUT221_WIDTH of inst : label is 1;
attribute C_PROBE_OUT222_INIT_VAL : string;
attribute C_PROBE_OUT222_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT222_WIDTH : integer;
attribute C_PROBE_OUT222_WIDTH of inst : label is 1;
attribute C_PROBE_OUT223_INIT_VAL : string;
attribute C_PROBE_OUT223_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT223_WIDTH : integer;
attribute C_PROBE_OUT223_WIDTH of inst : label is 1;
attribute C_PROBE_OUT224_INIT_VAL : string;
attribute C_PROBE_OUT224_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT224_WIDTH : integer;
attribute C_PROBE_OUT224_WIDTH of inst : label is 1;
attribute C_PROBE_OUT225_INIT_VAL : string;
attribute C_PROBE_OUT225_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT225_WIDTH : integer;
attribute C_PROBE_OUT225_WIDTH of inst : label is 1;
attribute C_PROBE_OUT226_INIT_VAL : string;
attribute C_PROBE_OUT226_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT226_WIDTH : integer;
attribute C_PROBE_OUT226_WIDTH of inst : label is 1;
attribute C_PROBE_OUT227_INIT_VAL : string;
attribute C_PROBE_OUT227_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT227_WIDTH : integer;
attribute C_PROBE_OUT227_WIDTH of inst : label is 1;
attribute C_PROBE_OUT228_INIT_VAL : string;
attribute C_PROBE_OUT228_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT228_WIDTH : integer;
attribute C_PROBE_OUT228_WIDTH of inst : label is 1;
attribute C_PROBE_OUT229_INIT_VAL : string;
attribute C_PROBE_OUT229_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT229_WIDTH : integer;
attribute C_PROBE_OUT229_WIDTH of inst : label is 1;
attribute C_PROBE_OUT22_INIT_VAL : string;
attribute C_PROBE_OUT22_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT22_WIDTH : integer;
attribute C_PROBE_OUT22_WIDTH of inst : label is 1;
attribute C_PROBE_OUT230_INIT_VAL : string;
attribute C_PROBE_OUT230_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT230_WIDTH : integer;
attribute C_PROBE_OUT230_WIDTH of inst : label is 1;
attribute C_PROBE_OUT231_INIT_VAL : string;
attribute C_PROBE_OUT231_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT231_WIDTH : integer;
attribute C_PROBE_OUT231_WIDTH of inst : label is 1;
attribute C_PROBE_OUT232_INIT_VAL : string;
attribute C_PROBE_OUT232_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT232_WIDTH : integer;
attribute C_PROBE_OUT232_WIDTH of inst : label is 1;
attribute C_PROBE_OUT233_INIT_VAL : string;
attribute C_PROBE_OUT233_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT233_WIDTH : integer;
attribute C_PROBE_OUT233_WIDTH of inst : label is 1;
attribute C_PROBE_OUT234_INIT_VAL : string;
attribute C_PROBE_OUT234_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT234_WIDTH : integer;
attribute C_PROBE_OUT234_WIDTH of inst : label is 1;
attribute C_PROBE_OUT235_INIT_VAL : string;
attribute C_PROBE_OUT235_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT235_WIDTH : integer;
attribute C_PROBE_OUT235_WIDTH of inst : label is 1;
attribute C_PROBE_OUT236_INIT_VAL : string;
attribute C_PROBE_OUT236_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT236_WIDTH : integer;
attribute C_PROBE_OUT236_WIDTH of inst : label is 1;
attribute C_PROBE_OUT237_INIT_VAL : string;
attribute C_PROBE_OUT237_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT237_WIDTH : integer;
attribute C_PROBE_OUT237_WIDTH of inst : label is 1;
attribute C_PROBE_OUT238_INIT_VAL : string;
attribute C_PROBE_OUT238_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT238_WIDTH : integer;
attribute C_PROBE_OUT238_WIDTH of inst : label is 1;
attribute C_PROBE_OUT239_INIT_VAL : string;
attribute C_PROBE_OUT239_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT239_WIDTH : integer;
attribute C_PROBE_OUT239_WIDTH of inst : label is 1;
attribute C_PROBE_OUT23_INIT_VAL : string;
attribute C_PROBE_OUT23_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT23_WIDTH : integer;
attribute C_PROBE_OUT23_WIDTH of inst : label is 1;
attribute C_PROBE_OUT240_INIT_VAL : string;
attribute C_PROBE_OUT240_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT240_WIDTH : integer;
attribute C_PROBE_OUT240_WIDTH of inst : label is 1;
attribute C_PROBE_OUT241_INIT_VAL : string;
attribute C_PROBE_OUT241_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT241_WIDTH : integer;
attribute C_PROBE_OUT241_WIDTH of inst : label is 1;
attribute C_PROBE_OUT242_INIT_VAL : string;
attribute C_PROBE_OUT242_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT242_WIDTH : integer;
attribute C_PROBE_OUT242_WIDTH of inst : label is 1;
attribute C_PROBE_OUT243_INIT_VAL : string;
attribute C_PROBE_OUT243_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT243_WIDTH : integer;
attribute C_PROBE_OUT243_WIDTH of inst : label is 1;
attribute C_PROBE_OUT244_INIT_VAL : string;
attribute C_PROBE_OUT244_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT244_WIDTH : integer;
attribute C_PROBE_OUT244_WIDTH of inst : label is 1;
attribute C_PROBE_OUT245_INIT_VAL : string;
attribute C_PROBE_OUT245_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT245_WIDTH : integer;
attribute C_PROBE_OUT245_WIDTH of inst : label is 1;
attribute C_PROBE_OUT246_INIT_VAL : string;
attribute C_PROBE_OUT246_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT246_WIDTH : integer;
attribute C_PROBE_OUT246_WIDTH of inst : label is 1;
attribute C_PROBE_OUT247_INIT_VAL : string;
attribute C_PROBE_OUT247_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT247_WIDTH : integer;
attribute C_PROBE_OUT247_WIDTH of inst : label is 1;
attribute C_PROBE_OUT248_INIT_VAL : string;
attribute C_PROBE_OUT248_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT248_WIDTH : integer;
attribute C_PROBE_OUT248_WIDTH of inst : label is 1;
attribute C_PROBE_OUT249_INIT_VAL : string;
attribute C_PROBE_OUT249_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT249_WIDTH : integer;
attribute C_PROBE_OUT249_WIDTH of inst : label is 1;
attribute C_PROBE_OUT24_INIT_VAL : string;
attribute C_PROBE_OUT24_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT24_WIDTH : integer;
attribute C_PROBE_OUT24_WIDTH of inst : label is 1;
attribute C_PROBE_OUT250_INIT_VAL : string;
attribute C_PROBE_OUT250_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT250_WIDTH : integer;
attribute C_PROBE_OUT250_WIDTH of inst : label is 1;
attribute C_PROBE_OUT251_INIT_VAL : string;
attribute C_PROBE_OUT251_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT251_WIDTH : integer;
attribute C_PROBE_OUT251_WIDTH of inst : label is 1;
attribute C_PROBE_OUT252_INIT_VAL : string;
attribute C_PROBE_OUT252_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT252_WIDTH : integer;
attribute C_PROBE_OUT252_WIDTH of inst : label is 1;
attribute C_PROBE_OUT253_INIT_VAL : string;
attribute C_PROBE_OUT253_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT253_WIDTH : integer;
attribute C_PROBE_OUT253_WIDTH of inst : label is 1;
attribute C_PROBE_OUT254_INIT_VAL : string;
attribute C_PROBE_OUT254_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT254_WIDTH : integer;
attribute C_PROBE_OUT254_WIDTH of inst : label is 1;
attribute C_PROBE_OUT255_INIT_VAL : string;
attribute C_PROBE_OUT255_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT255_WIDTH : integer;
attribute C_PROBE_OUT255_WIDTH of inst : label is 1;
attribute C_PROBE_OUT25_INIT_VAL : string;
attribute C_PROBE_OUT25_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT25_WIDTH : integer;
attribute C_PROBE_OUT25_WIDTH of inst : label is 1;
attribute C_PROBE_OUT26_INIT_VAL : string;
attribute C_PROBE_OUT26_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT26_WIDTH : integer;
attribute C_PROBE_OUT26_WIDTH of inst : label is 1;
attribute C_PROBE_OUT27_INIT_VAL : string;
attribute C_PROBE_OUT27_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT27_WIDTH : integer;
attribute C_PROBE_OUT27_WIDTH of inst : label is 1;
attribute C_PROBE_OUT28_INIT_VAL : string;
attribute C_PROBE_OUT28_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT28_WIDTH : integer;
attribute C_PROBE_OUT28_WIDTH of inst : label is 1;
attribute C_PROBE_OUT29_INIT_VAL : string;
attribute C_PROBE_OUT29_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT29_WIDTH : integer;
attribute C_PROBE_OUT29_WIDTH of inst : label is 1;
attribute C_PROBE_OUT2_INIT_VAL : string;
attribute C_PROBE_OUT2_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT2_WIDTH : integer;
attribute C_PROBE_OUT2_WIDTH of inst : label is 1;
attribute C_PROBE_OUT30_INIT_VAL : string;
attribute C_PROBE_OUT30_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT30_WIDTH : integer;
attribute C_PROBE_OUT30_WIDTH of inst : label is 1;
attribute C_PROBE_OUT31_INIT_VAL : string;
attribute C_PROBE_OUT31_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT31_WIDTH : integer;
attribute C_PROBE_OUT31_WIDTH of inst : label is 1;
attribute C_PROBE_OUT32_INIT_VAL : string;
attribute C_PROBE_OUT32_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT32_WIDTH : integer;
attribute C_PROBE_OUT32_WIDTH of inst : label is 1;
attribute C_PROBE_OUT33_INIT_VAL : string;
attribute C_PROBE_OUT33_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT33_WIDTH : integer;
attribute C_PROBE_OUT33_WIDTH of inst : label is 1;
attribute C_PROBE_OUT34_INIT_VAL : string;
attribute C_PROBE_OUT34_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT34_WIDTH : integer;
attribute C_PROBE_OUT34_WIDTH of inst : label is 1;
attribute C_PROBE_OUT35_INIT_VAL : string;
attribute C_PROBE_OUT35_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT35_WIDTH : integer;
attribute C_PROBE_OUT35_WIDTH of inst : label is 1;
attribute C_PROBE_OUT36_INIT_VAL : string;
attribute C_PROBE_OUT36_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT36_WIDTH : integer;
attribute C_PROBE_OUT36_WIDTH of inst : label is 1;
attribute C_PROBE_OUT37_INIT_VAL : string;
attribute C_PROBE_OUT37_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT37_WIDTH : integer;
attribute C_PROBE_OUT37_WIDTH of inst : label is 1;
attribute C_PROBE_OUT38_INIT_VAL : string;
attribute C_PROBE_OUT38_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT38_WIDTH : integer;
attribute C_PROBE_OUT38_WIDTH of inst : label is 1;
attribute C_PROBE_OUT39_INIT_VAL : string;
attribute C_PROBE_OUT39_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT39_WIDTH : integer;
attribute C_PROBE_OUT39_WIDTH of inst : label is 1;
attribute C_PROBE_OUT3_INIT_VAL : string;
attribute C_PROBE_OUT3_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT3_WIDTH : integer;
attribute C_PROBE_OUT3_WIDTH of inst : label is 1;
attribute C_PROBE_OUT40_INIT_VAL : string;
attribute C_PROBE_OUT40_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT40_WIDTH : integer;
attribute C_PROBE_OUT40_WIDTH of inst : label is 1;
attribute C_PROBE_OUT41_INIT_VAL : string;
attribute C_PROBE_OUT41_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT41_WIDTH : integer;
attribute C_PROBE_OUT41_WIDTH of inst : label is 1;
attribute C_PROBE_OUT42_INIT_VAL : string;
attribute C_PROBE_OUT42_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT42_WIDTH : integer;
attribute C_PROBE_OUT42_WIDTH of inst : label is 1;
attribute C_PROBE_OUT43_INIT_VAL : string;
attribute C_PROBE_OUT43_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT43_WIDTH : integer;
attribute C_PROBE_OUT43_WIDTH of inst : label is 1;
attribute C_PROBE_OUT44_INIT_VAL : string;
attribute C_PROBE_OUT44_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT44_WIDTH : integer;
attribute C_PROBE_OUT44_WIDTH of inst : label is 1;
attribute C_PROBE_OUT45_INIT_VAL : string;
attribute C_PROBE_OUT45_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT45_WIDTH : integer;
attribute C_PROBE_OUT45_WIDTH of inst : label is 1;
attribute C_PROBE_OUT46_INIT_VAL : string;
attribute C_PROBE_OUT46_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT46_WIDTH : integer;
attribute C_PROBE_OUT46_WIDTH of inst : label is 1;
attribute C_PROBE_OUT47_INIT_VAL : string;
attribute C_PROBE_OUT47_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT47_WIDTH : integer;
attribute C_PROBE_OUT47_WIDTH of inst : label is 1;
attribute C_PROBE_OUT48_INIT_VAL : string;
attribute C_PROBE_OUT48_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT48_WIDTH : integer;
attribute C_PROBE_OUT48_WIDTH of inst : label is 1;
attribute C_PROBE_OUT49_INIT_VAL : string;
attribute C_PROBE_OUT49_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT49_WIDTH : integer;
attribute C_PROBE_OUT49_WIDTH of inst : label is 1;
attribute C_PROBE_OUT4_INIT_VAL : string;
attribute C_PROBE_OUT4_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT4_WIDTH : integer;
attribute C_PROBE_OUT4_WIDTH of inst : label is 1;
attribute C_PROBE_OUT50_INIT_VAL : string;
attribute C_PROBE_OUT50_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT50_WIDTH : integer;
attribute C_PROBE_OUT50_WIDTH of inst : label is 1;
attribute C_PROBE_OUT51_INIT_VAL : string;
attribute C_PROBE_OUT51_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT51_WIDTH : integer;
attribute C_PROBE_OUT51_WIDTH of inst : label is 1;
attribute C_PROBE_OUT52_INIT_VAL : string;
attribute C_PROBE_OUT52_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT52_WIDTH : integer;
attribute C_PROBE_OUT52_WIDTH of inst : label is 1;
attribute C_PROBE_OUT53_INIT_VAL : string;
attribute C_PROBE_OUT53_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT53_WIDTH : integer;
attribute C_PROBE_OUT53_WIDTH of inst : label is 1;
attribute C_PROBE_OUT54_INIT_VAL : string;
attribute C_PROBE_OUT54_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT54_WIDTH : integer;
attribute C_PROBE_OUT54_WIDTH of inst : label is 1;
attribute C_PROBE_OUT55_INIT_VAL : string;
attribute C_PROBE_OUT55_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT55_WIDTH : integer;
attribute C_PROBE_OUT55_WIDTH of inst : label is 1;
attribute C_PROBE_OUT56_INIT_VAL : string;
attribute C_PROBE_OUT56_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT56_WIDTH : integer;
attribute C_PROBE_OUT56_WIDTH of inst : label is 1;
attribute C_PROBE_OUT57_INIT_VAL : string;
attribute C_PROBE_OUT57_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT57_WIDTH : integer;
attribute C_PROBE_OUT57_WIDTH of inst : label is 1;
attribute C_PROBE_OUT58_INIT_VAL : string;
attribute C_PROBE_OUT58_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT58_WIDTH : integer;
attribute C_PROBE_OUT58_WIDTH of inst : label is 1;
attribute C_PROBE_OUT59_INIT_VAL : string;
attribute C_PROBE_OUT59_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT59_WIDTH : integer;
attribute C_PROBE_OUT59_WIDTH of inst : label is 1;
attribute C_PROBE_OUT5_INIT_VAL : string;
attribute C_PROBE_OUT5_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT5_WIDTH : integer;
attribute C_PROBE_OUT5_WIDTH of inst : label is 1;
attribute C_PROBE_OUT60_INIT_VAL : string;
attribute C_PROBE_OUT60_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT60_WIDTH : integer;
attribute C_PROBE_OUT60_WIDTH of inst : label is 1;
attribute C_PROBE_OUT61_INIT_VAL : string;
attribute C_PROBE_OUT61_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT61_WIDTH : integer;
attribute C_PROBE_OUT61_WIDTH of inst : label is 1;
attribute C_PROBE_OUT62_INIT_VAL : string;
attribute C_PROBE_OUT62_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT62_WIDTH : integer;
attribute C_PROBE_OUT62_WIDTH of inst : label is 1;
attribute C_PROBE_OUT63_INIT_VAL : string;
attribute C_PROBE_OUT63_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT63_WIDTH : integer;
attribute C_PROBE_OUT63_WIDTH of inst : label is 1;
attribute C_PROBE_OUT64_INIT_VAL : string;
attribute C_PROBE_OUT64_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT64_WIDTH : integer;
attribute C_PROBE_OUT64_WIDTH of inst : label is 1;
attribute C_PROBE_OUT65_INIT_VAL : string;
attribute C_PROBE_OUT65_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT65_WIDTH : integer;
attribute C_PROBE_OUT65_WIDTH of inst : label is 1;
attribute C_PROBE_OUT66_INIT_VAL : string;
attribute C_PROBE_OUT66_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT66_WIDTH : integer;
attribute C_PROBE_OUT66_WIDTH of inst : label is 1;
attribute C_PROBE_OUT67_INIT_VAL : string;
attribute C_PROBE_OUT67_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT67_WIDTH : integer;
attribute C_PROBE_OUT67_WIDTH of inst : label is 1;
attribute C_PROBE_OUT68_INIT_VAL : string;
attribute C_PROBE_OUT68_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT68_WIDTH : integer;
attribute C_PROBE_OUT68_WIDTH of inst : label is 1;
attribute C_PROBE_OUT69_INIT_VAL : string;
attribute C_PROBE_OUT69_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT69_WIDTH : integer;
attribute C_PROBE_OUT69_WIDTH of inst : label is 1;
attribute C_PROBE_OUT6_INIT_VAL : string;
attribute C_PROBE_OUT6_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT6_WIDTH : integer;
attribute C_PROBE_OUT6_WIDTH of inst : label is 1;
attribute C_PROBE_OUT70_INIT_VAL : string;
attribute C_PROBE_OUT70_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT70_WIDTH : integer;
attribute C_PROBE_OUT70_WIDTH of inst : label is 1;
attribute C_PROBE_OUT71_INIT_VAL : string;
attribute C_PROBE_OUT71_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT71_WIDTH : integer;
attribute C_PROBE_OUT71_WIDTH of inst : label is 1;
attribute C_PROBE_OUT72_INIT_VAL : string;
attribute C_PROBE_OUT72_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT72_WIDTH : integer;
attribute C_PROBE_OUT72_WIDTH of inst : label is 1;
attribute C_PROBE_OUT73_INIT_VAL : string;
attribute C_PROBE_OUT73_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT73_WIDTH : integer;
attribute C_PROBE_OUT73_WIDTH of inst : label is 1;
attribute C_PROBE_OUT74_INIT_VAL : string;
attribute C_PROBE_OUT74_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT74_WIDTH : integer;
attribute C_PROBE_OUT74_WIDTH of inst : label is 1;
attribute C_PROBE_OUT75_INIT_VAL : string;
attribute C_PROBE_OUT75_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT75_WIDTH : integer;
attribute C_PROBE_OUT75_WIDTH of inst : label is 1;
attribute C_PROBE_OUT76_INIT_VAL : string;
attribute C_PROBE_OUT76_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT76_WIDTH : integer;
attribute C_PROBE_OUT76_WIDTH of inst : label is 1;
attribute C_PROBE_OUT77_INIT_VAL : string;
attribute C_PROBE_OUT77_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT77_WIDTH : integer;
attribute C_PROBE_OUT77_WIDTH of inst : label is 1;
attribute C_PROBE_OUT78_INIT_VAL : string;
attribute C_PROBE_OUT78_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT78_WIDTH : integer;
attribute C_PROBE_OUT78_WIDTH of inst : label is 1;
attribute C_PROBE_OUT79_INIT_VAL : string;
attribute C_PROBE_OUT79_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT79_WIDTH : integer;
attribute C_PROBE_OUT79_WIDTH of inst : label is 1;
attribute C_PROBE_OUT7_INIT_VAL : string;
attribute C_PROBE_OUT7_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT7_WIDTH : integer;
attribute C_PROBE_OUT7_WIDTH of inst : label is 1;
attribute C_PROBE_OUT80_INIT_VAL : string;
attribute C_PROBE_OUT80_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT80_WIDTH : integer;
attribute C_PROBE_OUT80_WIDTH of inst : label is 1;
attribute C_PROBE_OUT81_INIT_VAL : string;
attribute C_PROBE_OUT81_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT81_WIDTH : integer;
attribute C_PROBE_OUT81_WIDTH of inst : label is 1;
attribute C_PROBE_OUT82_INIT_VAL : string;
attribute C_PROBE_OUT82_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT82_WIDTH : integer;
attribute C_PROBE_OUT82_WIDTH of inst : label is 1;
attribute C_PROBE_OUT83_INIT_VAL : string;
attribute C_PROBE_OUT83_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT83_WIDTH : integer;
attribute C_PROBE_OUT83_WIDTH of inst : label is 1;
attribute C_PROBE_OUT84_INIT_VAL : string;
attribute C_PROBE_OUT84_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT84_WIDTH : integer;
attribute C_PROBE_OUT84_WIDTH of inst : label is 1;
attribute C_PROBE_OUT85_INIT_VAL : string;
attribute C_PROBE_OUT85_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT85_WIDTH : integer;
attribute C_PROBE_OUT85_WIDTH of inst : label is 1;
attribute C_PROBE_OUT86_INIT_VAL : string;
attribute C_PROBE_OUT86_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT86_WIDTH : integer;
attribute C_PROBE_OUT86_WIDTH of inst : label is 1;
attribute C_PROBE_OUT87_INIT_VAL : string;
attribute C_PROBE_OUT87_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT87_WIDTH : integer;
attribute C_PROBE_OUT87_WIDTH of inst : label is 1;
attribute C_PROBE_OUT88_INIT_VAL : string;
attribute C_PROBE_OUT88_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT88_WIDTH : integer;
attribute C_PROBE_OUT88_WIDTH of inst : label is 1;
attribute C_PROBE_OUT89_INIT_VAL : string;
attribute C_PROBE_OUT89_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT89_WIDTH : integer;
attribute C_PROBE_OUT89_WIDTH of inst : label is 1;
attribute C_PROBE_OUT8_INIT_VAL : string;
attribute C_PROBE_OUT8_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT8_WIDTH : integer;
attribute C_PROBE_OUT8_WIDTH of inst : label is 1;
attribute C_PROBE_OUT90_INIT_VAL : string;
attribute C_PROBE_OUT90_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT90_WIDTH : integer;
attribute C_PROBE_OUT90_WIDTH of inst : label is 1;
attribute C_PROBE_OUT91_INIT_VAL : string;
attribute C_PROBE_OUT91_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT91_WIDTH : integer;
attribute C_PROBE_OUT91_WIDTH of inst : label is 1;
attribute C_PROBE_OUT92_INIT_VAL : string;
attribute C_PROBE_OUT92_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT92_WIDTH : integer;
attribute C_PROBE_OUT92_WIDTH of inst : label is 1;
attribute C_PROBE_OUT93_INIT_VAL : string;
attribute C_PROBE_OUT93_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT93_WIDTH : integer;
attribute C_PROBE_OUT93_WIDTH of inst : label is 1;
attribute C_PROBE_OUT94_INIT_VAL : string;
attribute C_PROBE_OUT94_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT94_WIDTH : integer;
attribute C_PROBE_OUT94_WIDTH of inst : label is 1;
attribute C_PROBE_OUT95_INIT_VAL : string;
attribute C_PROBE_OUT95_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT95_WIDTH : integer;
attribute C_PROBE_OUT95_WIDTH of inst : label is 1;
attribute C_PROBE_OUT96_INIT_VAL : string;
attribute C_PROBE_OUT96_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT96_WIDTH : integer;
attribute C_PROBE_OUT96_WIDTH of inst : label is 1;
attribute C_PROBE_OUT97_INIT_VAL : string;
attribute C_PROBE_OUT97_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT97_WIDTH : integer;
attribute C_PROBE_OUT97_WIDTH of inst : label is 1;
attribute C_PROBE_OUT98_INIT_VAL : string;
attribute C_PROBE_OUT98_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT98_WIDTH : integer;
attribute C_PROBE_OUT98_WIDTH of inst : label is 1;
attribute C_PROBE_OUT99_INIT_VAL : string;
attribute C_PROBE_OUT99_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT99_WIDTH : integer;
attribute C_PROBE_OUT99_WIDTH of inst : label is 1;
attribute C_PROBE_OUT9_INIT_VAL : string;
attribute C_PROBE_OUT9_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT9_WIDTH : integer;
attribute C_PROBE_OUT9_WIDTH of inst : label is 1;
attribute C_USE_TEST_REG : integer;
attribute C_USE_TEST_REG of inst : label is 1;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of inst : label is "kintex7";
attribute C_XLNX_HW_PROBE_INFO : string;
attribute C_XLNX_HW_PROBE_INFO of inst : label is "DEFAULT";
attribute C_XSDB_SLAVE_TYPE : integer;
attribute C_XSDB_SLAVE_TYPE of inst : label is 33;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of inst : label is std.standard.true;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute LC_HIGH_BIT_POS_PROBE_OUT0 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT1 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT10 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT100 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000001100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT101 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000001100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT102 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000001100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT103 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000001100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT104 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000001101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT105 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000001101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT106 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000001101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT107 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000001101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT108 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000001101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT109 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000001101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT11 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT110 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000001101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT111 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000001101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT112 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000001110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT113 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000001110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT114 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000001110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT115 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000001110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT116 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000001110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT117 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000001110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT118 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000001110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT119 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000001110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT12 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT120 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000001111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT121 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000001111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT122 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000001111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT123 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000001111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT124 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000001111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT125 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000001111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT126 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000001111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT127 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000001111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT128 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT129 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT13 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT130 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT131 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT132 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT133 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT134 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT135 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT136 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT137 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT138 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT139 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT14 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT140 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT141 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT142 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT143 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT144 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT145 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT146 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT147 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT148 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT149 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT15 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT150 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT151 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT152 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT153 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT154 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT155 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000010011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT156 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000010011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT157 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000010011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT158 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000010011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT159 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000010011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT16 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT160 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000010100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT161 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000010100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT162 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000010100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT163 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000010100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT164 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000010100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT165 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000010100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT166 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000010100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT167 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000010100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT168 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000010101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT169 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000010101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT17 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT170 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000010101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT171 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000010101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT172 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000010101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT173 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000010101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT174 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000010101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT175 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000010101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT176 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000010110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT177 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000010110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT178 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000010110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT179 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000010110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT18 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT180 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000010110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT181 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000010110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT182 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000010110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT183 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000010110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT184 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000010111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT185 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000010111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT186 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000010111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT187 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000010111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT188 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000010111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT189 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000010111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT19 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT190 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000010111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT191 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000010111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT192 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT193 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT194 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT195 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT196 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT197 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT198 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT199 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT2 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT20 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT200 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT201 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT202 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT203 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT204 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT205 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT206 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT207 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT208 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT209 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT21 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT210 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT211 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT212 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT213 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT214 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT215 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT216 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT217 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT218 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT219 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000011011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT22 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT220 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000011011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT221 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000011011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT222 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000011011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT223 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000011011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT224 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000011100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT225 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000011100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT226 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000011100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT227 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000011100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT228 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000011100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT229 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000011100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT23 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT230 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000011100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT231 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000011100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT232 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000011101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT233 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000011101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT234 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000011101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT235 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000011101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT236 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000011101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT237 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000011101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT238 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000011101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT239 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000011101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT24 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT240 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000011110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT241 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000011110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT242 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000011110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT243 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000011110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT244 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000011110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT245 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000011110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT246 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000011110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT247 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000011110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT248 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000011111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT249 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000011111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT25 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT250 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000011111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT251 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000011111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT252 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000011111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT253 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000011111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT254 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000011111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT255 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000011111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT26 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT27 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000000011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT28 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000000011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT29 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000000011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT3 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT30 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000000011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT31 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000000011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT32 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000000100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT33 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000000100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT34 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000000100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT35 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000000100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT36 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000000100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT37 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000000100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT38 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000000100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT39 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000000100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT4 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT40 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000000101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT41 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000000101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT42 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000000101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT43 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000000101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT44 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000000101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT45 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000000101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT46 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000000101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT47 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000000101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT48 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000000110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT49 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000000110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT5 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT50 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000000110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT51 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000000110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT52 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000000110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT53 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000000110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT54 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000000110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT55 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000000110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT56 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000000111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT57 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000000111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT58 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000000111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT59 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000000111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT6 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT60 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000000111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT61 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000000111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT62 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000000111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT63 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000000111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT64 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT65 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT66 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT67 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT68 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT69 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT7 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT70 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT71 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT72 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT73 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT74 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT75 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT76 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT77 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT78 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT79 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT8 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT80 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT81 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT82 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT83 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT84 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT85 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT86 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT87 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT88 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT89 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT9 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT90 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT91 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000001011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT92 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000001011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT93 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000001011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT94 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000001011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT95 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000001011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT96 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000001100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT97 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000001100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT98 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000001100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT99 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000001100011";
attribute LC_LOW_BIT_POS_PROBE_OUT0 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000000000";
attribute LC_LOW_BIT_POS_PROBE_OUT1 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000001";
attribute LC_LOW_BIT_POS_PROBE_OUT10 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000001010";
attribute LC_LOW_BIT_POS_PROBE_OUT100 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000001100100";
attribute LC_LOW_BIT_POS_PROBE_OUT101 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000001100101";
attribute LC_LOW_BIT_POS_PROBE_OUT102 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000001100110";
attribute LC_LOW_BIT_POS_PROBE_OUT103 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000001100111";
attribute LC_LOW_BIT_POS_PROBE_OUT104 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000001101000";
attribute LC_LOW_BIT_POS_PROBE_OUT105 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000001101001";
attribute LC_LOW_BIT_POS_PROBE_OUT106 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000001101010";
attribute LC_LOW_BIT_POS_PROBE_OUT107 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000001101011";
attribute LC_LOW_BIT_POS_PROBE_OUT108 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000001101100";
attribute LC_LOW_BIT_POS_PROBE_OUT109 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000001101101";
attribute LC_LOW_BIT_POS_PROBE_OUT11 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000001011";
attribute LC_LOW_BIT_POS_PROBE_OUT110 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000001101110";
attribute LC_LOW_BIT_POS_PROBE_OUT111 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000001101111";
attribute LC_LOW_BIT_POS_PROBE_OUT112 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000001110000";
attribute LC_LOW_BIT_POS_PROBE_OUT113 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000001110001";
attribute LC_LOW_BIT_POS_PROBE_OUT114 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000001110010";
attribute LC_LOW_BIT_POS_PROBE_OUT115 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000001110011";
attribute LC_LOW_BIT_POS_PROBE_OUT116 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000001110100";
attribute LC_LOW_BIT_POS_PROBE_OUT117 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000001110101";
attribute LC_LOW_BIT_POS_PROBE_OUT118 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000001110110";
attribute LC_LOW_BIT_POS_PROBE_OUT119 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000001110111";
attribute LC_LOW_BIT_POS_PROBE_OUT12 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000001100";
attribute LC_LOW_BIT_POS_PROBE_OUT120 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000001111000";
attribute LC_LOW_BIT_POS_PROBE_OUT121 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000001111001";
attribute LC_LOW_BIT_POS_PROBE_OUT122 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000001111010";
attribute LC_LOW_BIT_POS_PROBE_OUT123 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000001111011";
attribute LC_LOW_BIT_POS_PROBE_OUT124 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000001111100";
attribute LC_LOW_BIT_POS_PROBE_OUT125 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000001111101";
attribute LC_LOW_BIT_POS_PROBE_OUT126 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000001111110";
attribute LC_LOW_BIT_POS_PROBE_OUT127 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000001111111";
attribute LC_LOW_BIT_POS_PROBE_OUT128 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010000000";
attribute LC_LOW_BIT_POS_PROBE_OUT129 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010000001";
attribute LC_LOW_BIT_POS_PROBE_OUT13 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000001101";
attribute LC_LOW_BIT_POS_PROBE_OUT130 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010000010";
attribute LC_LOW_BIT_POS_PROBE_OUT131 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010000011";
attribute LC_LOW_BIT_POS_PROBE_OUT132 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010000100";
attribute LC_LOW_BIT_POS_PROBE_OUT133 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010000101";
attribute LC_LOW_BIT_POS_PROBE_OUT134 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010000110";
attribute LC_LOW_BIT_POS_PROBE_OUT135 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010000111";
attribute LC_LOW_BIT_POS_PROBE_OUT136 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010001000";
attribute LC_LOW_BIT_POS_PROBE_OUT137 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010001001";
attribute LC_LOW_BIT_POS_PROBE_OUT138 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010001010";
attribute LC_LOW_BIT_POS_PROBE_OUT139 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010001011";
attribute LC_LOW_BIT_POS_PROBE_OUT14 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000001110";
attribute LC_LOW_BIT_POS_PROBE_OUT140 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010001100";
attribute LC_LOW_BIT_POS_PROBE_OUT141 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010001101";
attribute LC_LOW_BIT_POS_PROBE_OUT142 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010001110";
attribute LC_LOW_BIT_POS_PROBE_OUT143 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010001111";
attribute LC_LOW_BIT_POS_PROBE_OUT144 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010010000";
attribute LC_LOW_BIT_POS_PROBE_OUT145 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010010001";
attribute LC_LOW_BIT_POS_PROBE_OUT146 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010010010";
attribute LC_LOW_BIT_POS_PROBE_OUT147 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010010011";
attribute LC_LOW_BIT_POS_PROBE_OUT148 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010010100";
attribute LC_LOW_BIT_POS_PROBE_OUT149 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010010101";
attribute LC_LOW_BIT_POS_PROBE_OUT15 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000001111";
attribute LC_LOW_BIT_POS_PROBE_OUT150 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010010110";
attribute LC_LOW_BIT_POS_PROBE_OUT151 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010010111";
attribute LC_LOW_BIT_POS_PROBE_OUT152 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010011000";
attribute LC_LOW_BIT_POS_PROBE_OUT153 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010011001";
attribute LC_LOW_BIT_POS_PROBE_OUT154 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010011010";
attribute LC_LOW_BIT_POS_PROBE_OUT155 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000010011011";
attribute LC_LOW_BIT_POS_PROBE_OUT156 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000010011100";
attribute LC_LOW_BIT_POS_PROBE_OUT157 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000010011101";
attribute LC_LOW_BIT_POS_PROBE_OUT158 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000010011110";
attribute LC_LOW_BIT_POS_PROBE_OUT159 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000010011111";
attribute LC_LOW_BIT_POS_PROBE_OUT16 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000010000";
attribute LC_LOW_BIT_POS_PROBE_OUT160 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000010100000";
attribute LC_LOW_BIT_POS_PROBE_OUT161 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000010100001";
attribute LC_LOW_BIT_POS_PROBE_OUT162 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000010100010";
attribute LC_LOW_BIT_POS_PROBE_OUT163 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000010100011";
attribute LC_LOW_BIT_POS_PROBE_OUT164 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000010100100";
attribute LC_LOW_BIT_POS_PROBE_OUT165 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000010100101";
attribute LC_LOW_BIT_POS_PROBE_OUT166 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000010100110";
attribute LC_LOW_BIT_POS_PROBE_OUT167 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000010100111";
attribute LC_LOW_BIT_POS_PROBE_OUT168 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000010101000";
attribute LC_LOW_BIT_POS_PROBE_OUT169 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000010101001";
attribute LC_LOW_BIT_POS_PROBE_OUT17 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000010001";
attribute LC_LOW_BIT_POS_PROBE_OUT170 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000010101010";
attribute LC_LOW_BIT_POS_PROBE_OUT171 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000010101011";
attribute LC_LOW_BIT_POS_PROBE_OUT172 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000010101100";
attribute LC_LOW_BIT_POS_PROBE_OUT173 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000010101101";
attribute LC_LOW_BIT_POS_PROBE_OUT174 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000010101110";
attribute LC_LOW_BIT_POS_PROBE_OUT175 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000010101111";
attribute LC_LOW_BIT_POS_PROBE_OUT176 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000010110000";
attribute LC_LOW_BIT_POS_PROBE_OUT177 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000010110001";
attribute LC_LOW_BIT_POS_PROBE_OUT178 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000010110010";
attribute LC_LOW_BIT_POS_PROBE_OUT179 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000010110011";
attribute LC_LOW_BIT_POS_PROBE_OUT18 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000010010";
attribute LC_LOW_BIT_POS_PROBE_OUT180 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000010110100";
attribute LC_LOW_BIT_POS_PROBE_OUT181 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000010110101";
attribute LC_LOW_BIT_POS_PROBE_OUT182 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000010110110";
attribute LC_LOW_BIT_POS_PROBE_OUT183 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000010110111";
attribute LC_LOW_BIT_POS_PROBE_OUT184 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000010111000";
attribute LC_LOW_BIT_POS_PROBE_OUT185 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000010111001";
attribute LC_LOW_BIT_POS_PROBE_OUT186 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000010111010";
attribute LC_LOW_BIT_POS_PROBE_OUT187 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000010111011";
attribute LC_LOW_BIT_POS_PROBE_OUT188 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000010111100";
attribute LC_LOW_BIT_POS_PROBE_OUT189 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000010111101";
attribute LC_LOW_BIT_POS_PROBE_OUT19 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000010011";
attribute LC_LOW_BIT_POS_PROBE_OUT190 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000010111110";
attribute LC_LOW_BIT_POS_PROBE_OUT191 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000010111111";
attribute LC_LOW_BIT_POS_PROBE_OUT192 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011000000";
attribute LC_LOW_BIT_POS_PROBE_OUT193 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011000001";
attribute LC_LOW_BIT_POS_PROBE_OUT194 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011000010";
attribute LC_LOW_BIT_POS_PROBE_OUT195 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011000011";
attribute LC_LOW_BIT_POS_PROBE_OUT196 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011000100";
attribute LC_LOW_BIT_POS_PROBE_OUT197 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011000101";
attribute LC_LOW_BIT_POS_PROBE_OUT198 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011000110";
attribute LC_LOW_BIT_POS_PROBE_OUT199 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011000111";
attribute LC_LOW_BIT_POS_PROBE_OUT2 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000000010";
attribute LC_LOW_BIT_POS_PROBE_OUT20 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000010100";
attribute LC_LOW_BIT_POS_PROBE_OUT200 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011001000";
attribute LC_LOW_BIT_POS_PROBE_OUT201 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011001001";
attribute LC_LOW_BIT_POS_PROBE_OUT202 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011001010";
attribute LC_LOW_BIT_POS_PROBE_OUT203 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011001011";
attribute LC_LOW_BIT_POS_PROBE_OUT204 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011001100";
attribute LC_LOW_BIT_POS_PROBE_OUT205 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011001101";
attribute LC_LOW_BIT_POS_PROBE_OUT206 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011001110";
attribute LC_LOW_BIT_POS_PROBE_OUT207 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011001111";
attribute LC_LOW_BIT_POS_PROBE_OUT208 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011010000";
attribute LC_LOW_BIT_POS_PROBE_OUT209 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011010001";
attribute LC_LOW_BIT_POS_PROBE_OUT21 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000010101";
attribute LC_LOW_BIT_POS_PROBE_OUT210 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011010010";
attribute LC_LOW_BIT_POS_PROBE_OUT211 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011010011";
attribute LC_LOW_BIT_POS_PROBE_OUT212 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011010100";
attribute LC_LOW_BIT_POS_PROBE_OUT213 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011010101";
attribute LC_LOW_BIT_POS_PROBE_OUT214 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011010110";
attribute LC_LOW_BIT_POS_PROBE_OUT215 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011010111";
attribute LC_LOW_BIT_POS_PROBE_OUT216 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011011000";
attribute LC_LOW_BIT_POS_PROBE_OUT217 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011011001";
attribute LC_LOW_BIT_POS_PROBE_OUT218 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011011010";
attribute LC_LOW_BIT_POS_PROBE_OUT219 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000011011011";
attribute LC_LOW_BIT_POS_PROBE_OUT22 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000010110";
attribute LC_LOW_BIT_POS_PROBE_OUT220 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000011011100";
attribute LC_LOW_BIT_POS_PROBE_OUT221 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000011011101";
attribute LC_LOW_BIT_POS_PROBE_OUT222 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000011011110";
attribute LC_LOW_BIT_POS_PROBE_OUT223 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000011011111";
attribute LC_LOW_BIT_POS_PROBE_OUT224 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000011100000";
attribute LC_LOW_BIT_POS_PROBE_OUT225 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000011100001";
attribute LC_LOW_BIT_POS_PROBE_OUT226 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000011100010";
attribute LC_LOW_BIT_POS_PROBE_OUT227 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000011100011";
attribute LC_LOW_BIT_POS_PROBE_OUT228 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000011100100";
attribute LC_LOW_BIT_POS_PROBE_OUT229 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000011100101";
attribute LC_LOW_BIT_POS_PROBE_OUT23 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000010111";
attribute LC_LOW_BIT_POS_PROBE_OUT230 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000011100110";
attribute LC_LOW_BIT_POS_PROBE_OUT231 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000011100111";
attribute LC_LOW_BIT_POS_PROBE_OUT232 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000011101000";
attribute LC_LOW_BIT_POS_PROBE_OUT233 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000011101001";
attribute LC_LOW_BIT_POS_PROBE_OUT234 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000011101010";
attribute LC_LOW_BIT_POS_PROBE_OUT235 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000011101011";
attribute LC_LOW_BIT_POS_PROBE_OUT236 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000011101100";
attribute LC_LOW_BIT_POS_PROBE_OUT237 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000011101101";
attribute LC_LOW_BIT_POS_PROBE_OUT238 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000011101110";
attribute LC_LOW_BIT_POS_PROBE_OUT239 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000011101111";
attribute LC_LOW_BIT_POS_PROBE_OUT24 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000011000";
attribute LC_LOW_BIT_POS_PROBE_OUT240 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000011110000";
attribute LC_LOW_BIT_POS_PROBE_OUT241 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000011110001";
attribute LC_LOW_BIT_POS_PROBE_OUT242 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000011110010";
attribute LC_LOW_BIT_POS_PROBE_OUT243 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000011110011";
attribute LC_LOW_BIT_POS_PROBE_OUT244 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000011110100";
attribute LC_LOW_BIT_POS_PROBE_OUT245 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000011110101";
attribute LC_LOW_BIT_POS_PROBE_OUT246 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000011110110";
attribute LC_LOW_BIT_POS_PROBE_OUT247 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000011110111";
attribute LC_LOW_BIT_POS_PROBE_OUT248 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000011111000";
attribute LC_LOW_BIT_POS_PROBE_OUT249 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000011111001";
attribute LC_LOW_BIT_POS_PROBE_OUT25 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000011001";
attribute LC_LOW_BIT_POS_PROBE_OUT250 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000011111010";
attribute LC_LOW_BIT_POS_PROBE_OUT251 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000011111011";
attribute LC_LOW_BIT_POS_PROBE_OUT252 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000011111100";
attribute LC_LOW_BIT_POS_PROBE_OUT253 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000011111101";
attribute LC_LOW_BIT_POS_PROBE_OUT254 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000011111110";
attribute LC_LOW_BIT_POS_PROBE_OUT255 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000011111111";
attribute LC_LOW_BIT_POS_PROBE_OUT26 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000011010";
attribute LC_LOW_BIT_POS_PROBE_OUT27 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000000011011";
attribute LC_LOW_BIT_POS_PROBE_OUT28 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000000011100";
attribute LC_LOW_BIT_POS_PROBE_OUT29 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000000011101";
attribute LC_LOW_BIT_POS_PROBE_OUT3 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000000011";
attribute LC_LOW_BIT_POS_PROBE_OUT30 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000000011110";
attribute LC_LOW_BIT_POS_PROBE_OUT31 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000000011111";
attribute LC_LOW_BIT_POS_PROBE_OUT32 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000000100000";
attribute LC_LOW_BIT_POS_PROBE_OUT33 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000000100001";
attribute LC_LOW_BIT_POS_PROBE_OUT34 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000000100010";
attribute LC_LOW_BIT_POS_PROBE_OUT35 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000000100011";
attribute LC_LOW_BIT_POS_PROBE_OUT36 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000000100100";
attribute LC_LOW_BIT_POS_PROBE_OUT37 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000000100101";
attribute LC_LOW_BIT_POS_PROBE_OUT38 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000000100110";
attribute LC_LOW_BIT_POS_PROBE_OUT39 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000000100111";
attribute LC_LOW_BIT_POS_PROBE_OUT4 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000000100";
attribute LC_LOW_BIT_POS_PROBE_OUT40 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000000101000";
attribute LC_LOW_BIT_POS_PROBE_OUT41 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000000101001";
attribute LC_LOW_BIT_POS_PROBE_OUT42 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000000101010";
attribute LC_LOW_BIT_POS_PROBE_OUT43 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000000101011";
attribute LC_LOW_BIT_POS_PROBE_OUT44 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000000101100";
attribute LC_LOW_BIT_POS_PROBE_OUT45 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000000101101";
attribute LC_LOW_BIT_POS_PROBE_OUT46 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000000101110";
attribute LC_LOW_BIT_POS_PROBE_OUT47 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000000101111";
attribute LC_LOW_BIT_POS_PROBE_OUT48 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000000110000";
attribute LC_LOW_BIT_POS_PROBE_OUT49 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000000110001";
attribute LC_LOW_BIT_POS_PROBE_OUT5 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000000101";
attribute LC_LOW_BIT_POS_PROBE_OUT50 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000000110010";
attribute LC_LOW_BIT_POS_PROBE_OUT51 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000000110011";
attribute LC_LOW_BIT_POS_PROBE_OUT52 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000000110100";
attribute LC_LOW_BIT_POS_PROBE_OUT53 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000000110101";
attribute LC_LOW_BIT_POS_PROBE_OUT54 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000000110110";
attribute LC_LOW_BIT_POS_PROBE_OUT55 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000000110111";
attribute LC_LOW_BIT_POS_PROBE_OUT56 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000000111000";
attribute LC_LOW_BIT_POS_PROBE_OUT57 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000000111001";
attribute LC_LOW_BIT_POS_PROBE_OUT58 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000000111010";
attribute LC_LOW_BIT_POS_PROBE_OUT59 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000000111011";
attribute LC_LOW_BIT_POS_PROBE_OUT6 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000000110";
attribute LC_LOW_BIT_POS_PROBE_OUT60 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000000111100";
attribute LC_LOW_BIT_POS_PROBE_OUT61 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000000111101";
attribute LC_LOW_BIT_POS_PROBE_OUT62 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000000111110";
attribute LC_LOW_BIT_POS_PROBE_OUT63 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000000111111";
attribute LC_LOW_BIT_POS_PROBE_OUT64 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001000000";
attribute LC_LOW_BIT_POS_PROBE_OUT65 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001000001";
attribute LC_LOW_BIT_POS_PROBE_OUT66 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001000010";
attribute LC_LOW_BIT_POS_PROBE_OUT67 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001000011";
attribute LC_LOW_BIT_POS_PROBE_OUT68 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001000100";
attribute LC_LOW_BIT_POS_PROBE_OUT69 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001000101";
attribute LC_LOW_BIT_POS_PROBE_OUT7 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000000111";
attribute LC_LOW_BIT_POS_PROBE_OUT70 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001000110";
attribute LC_LOW_BIT_POS_PROBE_OUT71 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001000111";
attribute LC_LOW_BIT_POS_PROBE_OUT72 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001001000";
attribute LC_LOW_BIT_POS_PROBE_OUT73 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001001001";
attribute LC_LOW_BIT_POS_PROBE_OUT74 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001001010";
attribute LC_LOW_BIT_POS_PROBE_OUT75 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001001011";
attribute LC_LOW_BIT_POS_PROBE_OUT76 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001001100";
attribute LC_LOW_BIT_POS_PROBE_OUT77 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001001101";
attribute LC_LOW_BIT_POS_PROBE_OUT78 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001001110";
attribute LC_LOW_BIT_POS_PROBE_OUT79 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001001111";
attribute LC_LOW_BIT_POS_PROBE_OUT8 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000001000";
attribute LC_LOW_BIT_POS_PROBE_OUT80 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001010000";
attribute LC_LOW_BIT_POS_PROBE_OUT81 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001010001";
attribute LC_LOW_BIT_POS_PROBE_OUT82 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001010010";
attribute LC_LOW_BIT_POS_PROBE_OUT83 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001010011";
attribute LC_LOW_BIT_POS_PROBE_OUT84 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001010100";
attribute LC_LOW_BIT_POS_PROBE_OUT85 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001010101";
attribute LC_LOW_BIT_POS_PROBE_OUT86 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001010110";
attribute LC_LOW_BIT_POS_PROBE_OUT87 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001010111";
attribute LC_LOW_BIT_POS_PROBE_OUT88 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001011000";
attribute LC_LOW_BIT_POS_PROBE_OUT89 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001011001";
attribute LC_LOW_BIT_POS_PROBE_OUT9 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000001001";
attribute LC_LOW_BIT_POS_PROBE_OUT90 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001011010";
attribute LC_LOW_BIT_POS_PROBE_OUT91 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000001011011";
attribute LC_LOW_BIT_POS_PROBE_OUT92 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000001011100";
attribute LC_LOW_BIT_POS_PROBE_OUT93 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000001011101";
attribute LC_LOW_BIT_POS_PROBE_OUT94 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000001011110";
attribute LC_LOW_BIT_POS_PROBE_OUT95 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000001011111";
attribute LC_LOW_BIT_POS_PROBE_OUT96 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000001100000";
attribute LC_LOW_BIT_POS_PROBE_OUT97 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000001100001";
attribute LC_LOW_BIT_POS_PROBE_OUT98 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000001100010";
attribute LC_LOW_BIT_POS_PROBE_OUT99 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000001100011";
attribute LC_PROBE_IN_WIDTH_STRING : string;
attribute LC_PROBE_IN_WIDTH_STRING of inst : label is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of inst : label is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_INIT_VAL_STRING : string;
attribute LC_PROBE_OUT_INIT_VAL_STRING of inst : label is "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of inst : label is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_WIDTH_STRING : string;
attribute LC_PROBE_OUT_WIDTH_STRING of inst : label is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_TOTAL_PROBE_IN_WIDTH : integer;
attribute LC_TOTAL_PROBE_IN_WIDTH of inst : label is 4;
attribute LC_TOTAL_PROBE_OUT_WIDTH : integer;
attribute LC_TOTAL_PROBE_OUT_WIDTH of inst : label is 0;
attribute syn_noprune : string;
attribute syn_noprune of inst : label is "1";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio
port map (
clk => clk,
probe_in0(0) => probe_in0(0),
probe_in1(0) => probe_in1(0),
probe_in10(0) => '0',
probe_in100(0) => '0',
probe_in101(0) => '0',
probe_in102(0) => '0',
probe_in103(0) => '0',
probe_in104(0) => '0',
probe_in105(0) => '0',
probe_in106(0) => '0',
probe_in107(0) => '0',
probe_in108(0) => '0',
probe_in109(0) => '0',
probe_in11(0) => '0',
probe_in110(0) => '0',
probe_in111(0) => '0',
probe_in112(0) => '0',
probe_in113(0) => '0',
probe_in114(0) => '0',
probe_in115(0) => '0',
probe_in116(0) => '0',
probe_in117(0) => '0',
probe_in118(0) => '0',
probe_in119(0) => '0',
probe_in12(0) => '0',
probe_in120(0) => '0',
probe_in121(0) => '0',
probe_in122(0) => '0',
probe_in123(0) => '0',
probe_in124(0) => '0',
probe_in125(0) => '0',
probe_in126(0) => '0',
probe_in127(0) => '0',
probe_in128(0) => '0',
probe_in129(0) => '0',
probe_in13(0) => '0',
probe_in130(0) => '0',
probe_in131(0) => '0',
probe_in132(0) => '0',
probe_in133(0) => '0',
probe_in134(0) => '0',
probe_in135(0) => '0',
probe_in136(0) => '0',
probe_in137(0) => '0',
probe_in138(0) => '0',
probe_in139(0) => '0',
probe_in14(0) => '0',
probe_in140(0) => '0',
probe_in141(0) => '0',
probe_in142(0) => '0',
probe_in143(0) => '0',
probe_in144(0) => '0',
probe_in145(0) => '0',
probe_in146(0) => '0',
probe_in147(0) => '0',
probe_in148(0) => '0',
probe_in149(0) => '0',
probe_in15(0) => '0',
probe_in150(0) => '0',
probe_in151(0) => '0',
probe_in152(0) => '0',
probe_in153(0) => '0',
probe_in154(0) => '0',
probe_in155(0) => '0',
probe_in156(0) => '0',
probe_in157(0) => '0',
probe_in158(0) => '0',
probe_in159(0) => '0',
probe_in16(0) => '0',
probe_in160(0) => '0',
probe_in161(0) => '0',
probe_in162(0) => '0',
probe_in163(0) => '0',
probe_in164(0) => '0',
probe_in165(0) => '0',
probe_in166(0) => '0',
probe_in167(0) => '0',
probe_in168(0) => '0',
probe_in169(0) => '0',
probe_in17(0) => '0',
probe_in170(0) => '0',
probe_in171(0) => '0',
probe_in172(0) => '0',
probe_in173(0) => '0',
probe_in174(0) => '0',
probe_in175(0) => '0',
probe_in176(0) => '0',
probe_in177(0) => '0',
probe_in178(0) => '0',
probe_in179(0) => '0',
probe_in18(0) => '0',
probe_in180(0) => '0',
probe_in181(0) => '0',
probe_in182(0) => '0',
probe_in183(0) => '0',
probe_in184(0) => '0',
probe_in185(0) => '0',
probe_in186(0) => '0',
probe_in187(0) => '0',
probe_in188(0) => '0',
probe_in189(0) => '0',
probe_in19(0) => '0',
probe_in190(0) => '0',
probe_in191(0) => '0',
probe_in192(0) => '0',
probe_in193(0) => '0',
probe_in194(0) => '0',
probe_in195(0) => '0',
probe_in196(0) => '0',
probe_in197(0) => '0',
probe_in198(0) => '0',
probe_in199(0) => '0',
probe_in2(0) => probe_in2(0),
probe_in20(0) => '0',
probe_in200(0) => '0',
probe_in201(0) => '0',
probe_in202(0) => '0',
probe_in203(0) => '0',
probe_in204(0) => '0',
probe_in205(0) => '0',
probe_in206(0) => '0',
probe_in207(0) => '0',
probe_in208(0) => '0',
probe_in209(0) => '0',
probe_in21(0) => '0',
probe_in210(0) => '0',
probe_in211(0) => '0',
probe_in212(0) => '0',
probe_in213(0) => '0',
probe_in214(0) => '0',
probe_in215(0) => '0',
probe_in216(0) => '0',
probe_in217(0) => '0',
probe_in218(0) => '0',
probe_in219(0) => '0',
probe_in22(0) => '0',
probe_in220(0) => '0',
probe_in221(0) => '0',
probe_in222(0) => '0',
probe_in223(0) => '0',
probe_in224(0) => '0',
probe_in225(0) => '0',
probe_in226(0) => '0',
probe_in227(0) => '0',
probe_in228(0) => '0',
probe_in229(0) => '0',
probe_in23(0) => '0',
probe_in230(0) => '0',
probe_in231(0) => '0',
probe_in232(0) => '0',
probe_in233(0) => '0',
probe_in234(0) => '0',
probe_in235(0) => '0',
probe_in236(0) => '0',
probe_in237(0) => '0',
probe_in238(0) => '0',
probe_in239(0) => '0',
probe_in24(0) => '0',
probe_in240(0) => '0',
probe_in241(0) => '0',
probe_in242(0) => '0',
probe_in243(0) => '0',
probe_in244(0) => '0',
probe_in245(0) => '0',
probe_in246(0) => '0',
probe_in247(0) => '0',
probe_in248(0) => '0',
probe_in249(0) => '0',
probe_in25(0) => '0',
probe_in250(0) => '0',
probe_in251(0) => '0',
probe_in252(0) => '0',
probe_in253(0) => '0',
probe_in254(0) => '0',
probe_in255(0) => '0',
probe_in26(0) => '0',
probe_in27(0) => '0',
probe_in28(0) => '0',
probe_in29(0) => '0',
probe_in3(0) => probe_in3(0),
probe_in30(0) => '0',
probe_in31(0) => '0',
probe_in32(0) => '0',
probe_in33(0) => '0',
probe_in34(0) => '0',
probe_in35(0) => '0',
probe_in36(0) => '0',
probe_in37(0) => '0',
probe_in38(0) => '0',
probe_in39(0) => '0',
probe_in4(0) => '0',
probe_in40(0) => '0',
probe_in41(0) => '0',
probe_in42(0) => '0',
probe_in43(0) => '0',
probe_in44(0) => '0',
probe_in45(0) => '0',
probe_in46(0) => '0',
probe_in47(0) => '0',
probe_in48(0) => '0',
probe_in49(0) => '0',
probe_in5(0) => '0',
probe_in50(0) => '0',
probe_in51(0) => '0',
probe_in52(0) => '0',
probe_in53(0) => '0',
probe_in54(0) => '0',
probe_in55(0) => '0',
probe_in56(0) => '0',
probe_in57(0) => '0',
probe_in58(0) => '0',
probe_in59(0) => '0',
probe_in6(0) => '0',
probe_in60(0) => '0',
probe_in61(0) => '0',
probe_in62(0) => '0',
probe_in63(0) => '0',
probe_in64(0) => '0',
probe_in65(0) => '0',
probe_in66(0) => '0',
probe_in67(0) => '0',
probe_in68(0) => '0',
probe_in69(0) => '0',
probe_in7(0) => '0',
probe_in70(0) => '0',
probe_in71(0) => '0',
probe_in72(0) => '0',
probe_in73(0) => '0',
probe_in74(0) => '0',
probe_in75(0) => '0',
probe_in76(0) => '0',
probe_in77(0) => '0',
probe_in78(0) => '0',
probe_in79(0) => '0',
probe_in8(0) => '0',
probe_in80(0) => '0',
probe_in81(0) => '0',
probe_in82(0) => '0',
probe_in83(0) => '0',
probe_in84(0) => '0',
probe_in85(0) => '0',
probe_in86(0) => '0',
probe_in87(0) => '0',
probe_in88(0) => '0',
probe_in89(0) => '0',
probe_in9(0) => '0',
probe_in90(0) => '0',
probe_in91(0) => '0',
probe_in92(0) => '0',
probe_in93(0) => '0',
probe_in94(0) => '0',
probe_in95(0) => '0',
probe_in96(0) => '0',
probe_in97(0) => '0',
probe_in98(0) => '0',
probe_in99(0) => '0',
probe_out0(0) => NLW_inst_probe_out0_UNCONNECTED(0),
probe_out1(0) => NLW_inst_probe_out1_UNCONNECTED(0),
probe_out10(0) => NLW_inst_probe_out10_UNCONNECTED(0),
probe_out100(0) => NLW_inst_probe_out100_UNCONNECTED(0),
probe_out101(0) => NLW_inst_probe_out101_UNCONNECTED(0),
probe_out102(0) => NLW_inst_probe_out102_UNCONNECTED(0),
probe_out103(0) => NLW_inst_probe_out103_UNCONNECTED(0),
probe_out104(0) => NLW_inst_probe_out104_UNCONNECTED(0),
probe_out105(0) => NLW_inst_probe_out105_UNCONNECTED(0),
probe_out106(0) => NLW_inst_probe_out106_UNCONNECTED(0),
probe_out107(0) => NLW_inst_probe_out107_UNCONNECTED(0),
probe_out108(0) => NLW_inst_probe_out108_UNCONNECTED(0),
probe_out109(0) => NLW_inst_probe_out109_UNCONNECTED(0),
probe_out11(0) => NLW_inst_probe_out11_UNCONNECTED(0),
probe_out110(0) => NLW_inst_probe_out110_UNCONNECTED(0),
probe_out111(0) => NLW_inst_probe_out111_UNCONNECTED(0),
probe_out112(0) => NLW_inst_probe_out112_UNCONNECTED(0),
probe_out113(0) => NLW_inst_probe_out113_UNCONNECTED(0),
probe_out114(0) => NLW_inst_probe_out114_UNCONNECTED(0),
probe_out115(0) => NLW_inst_probe_out115_UNCONNECTED(0),
probe_out116(0) => NLW_inst_probe_out116_UNCONNECTED(0),
probe_out117(0) => NLW_inst_probe_out117_UNCONNECTED(0),
probe_out118(0) => NLW_inst_probe_out118_UNCONNECTED(0),
probe_out119(0) => NLW_inst_probe_out119_UNCONNECTED(0),
probe_out12(0) => NLW_inst_probe_out12_UNCONNECTED(0),
probe_out120(0) => NLW_inst_probe_out120_UNCONNECTED(0),
probe_out121(0) => NLW_inst_probe_out121_UNCONNECTED(0),
probe_out122(0) => NLW_inst_probe_out122_UNCONNECTED(0),
probe_out123(0) => NLW_inst_probe_out123_UNCONNECTED(0),
probe_out124(0) => NLW_inst_probe_out124_UNCONNECTED(0),
probe_out125(0) => NLW_inst_probe_out125_UNCONNECTED(0),
probe_out126(0) => NLW_inst_probe_out126_UNCONNECTED(0),
probe_out127(0) => NLW_inst_probe_out127_UNCONNECTED(0),
probe_out128(0) => NLW_inst_probe_out128_UNCONNECTED(0),
probe_out129(0) => NLW_inst_probe_out129_UNCONNECTED(0),
probe_out13(0) => NLW_inst_probe_out13_UNCONNECTED(0),
probe_out130(0) => NLW_inst_probe_out130_UNCONNECTED(0),
probe_out131(0) => NLW_inst_probe_out131_UNCONNECTED(0),
probe_out132(0) => NLW_inst_probe_out132_UNCONNECTED(0),
probe_out133(0) => NLW_inst_probe_out133_UNCONNECTED(0),
probe_out134(0) => NLW_inst_probe_out134_UNCONNECTED(0),
probe_out135(0) => NLW_inst_probe_out135_UNCONNECTED(0),
probe_out136(0) => NLW_inst_probe_out136_UNCONNECTED(0),
probe_out137(0) => NLW_inst_probe_out137_UNCONNECTED(0),
probe_out138(0) => NLW_inst_probe_out138_UNCONNECTED(0),
probe_out139(0) => NLW_inst_probe_out139_UNCONNECTED(0),
probe_out14(0) => NLW_inst_probe_out14_UNCONNECTED(0),
probe_out140(0) => NLW_inst_probe_out140_UNCONNECTED(0),
probe_out141(0) => NLW_inst_probe_out141_UNCONNECTED(0),
probe_out142(0) => NLW_inst_probe_out142_UNCONNECTED(0),
probe_out143(0) => NLW_inst_probe_out143_UNCONNECTED(0),
probe_out144(0) => NLW_inst_probe_out144_UNCONNECTED(0),
probe_out145(0) => NLW_inst_probe_out145_UNCONNECTED(0),
probe_out146(0) => NLW_inst_probe_out146_UNCONNECTED(0),
probe_out147(0) => NLW_inst_probe_out147_UNCONNECTED(0),
probe_out148(0) => NLW_inst_probe_out148_UNCONNECTED(0),
probe_out149(0) => NLW_inst_probe_out149_UNCONNECTED(0),
probe_out15(0) => NLW_inst_probe_out15_UNCONNECTED(0),
probe_out150(0) => NLW_inst_probe_out150_UNCONNECTED(0),
probe_out151(0) => NLW_inst_probe_out151_UNCONNECTED(0),
probe_out152(0) => NLW_inst_probe_out152_UNCONNECTED(0),
probe_out153(0) => NLW_inst_probe_out153_UNCONNECTED(0),
probe_out154(0) => NLW_inst_probe_out154_UNCONNECTED(0),
probe_out155(0) => NLW_inst_probe_out155_UNCONNECTED(0),
probe_out156(0) => NLW_inst_probe_out156_UNCONNECTED(0),
probe_out157(0) => NLW_inst_probe_out157_UNCONNECTED(0),
probe_out158(0) => NLW_inst_probe_out158_UNCONNECTED(0),
probe_out159(0) => NLW_inst_probe_out159_UNCONNECTED(0),
probe_out16(0) => NLW_inst_probe_out16_UNCONNECTED(0),
probe_out160(0) => NLW_inst_probe_out160_UNCONNECTED(0),
probe_out161(0) => NLW_inst_probe_out161_UNCONNECTED(0),
probe_out162(0) => NLW_inst_probe_out162_UNCONNECTED(0),
probe_out163(0) => NLW_inst_probe_out163_UNCONNECTED(0),
probe_out164(0) => NLW_inst_probe_out164_UNCONNECTED(0),
probe_out165(0) => NLW_inst_probe_out165_UNCONNECTED(0),
probe_out166(0) => NLW_inst_probe_out166_UNCONNECTED(0),
probe_out167(0) => NLW_inst_probe_out167_UNCONNECTED(0),
probe_out168(0) => NLW_inst_probe_out168_UNCONNECTED(0),
probe_out169(0) => NLW_inst_probe_out169_UNCONNECTED(0),
probe_out17(0) => NLW_inst_probe_out17_UNCONNECTED(0),
probe_out170(0) => NLW_inst_probe_out170_UNCONNECTED(0),
probe_out171(0) => NLW_inst_probe_out171_UNCONNECTED(0),
probe_out172(0) => NLW_inst_probe_out172_UNCONNECTED(0),
probe_out173(0) => NLW_inst_probe_out173_UNCONNECTED(0),
probe_out174(0) => NLW_inst_probe_out174_UNCONNECTED(0),
probe_out175(0) => NLW_inst_probe_out175_UNCONNECTED(0),
probe_out176(0) => NLW_inst_probe_out176_UNCONNECTED(0),
probe_out177(0) => NLW_inst_probe_out177_UNCONNECTED(0),
probe_out178(0) => NLW_inst_probe_out178_UNCONNECTED(0),
probe_out179(0) => NLW_inst_probe_out179_UNCONNECTED(0),
probe_out18(0) => NLW_inst_probe_out18_UNCONNECTED(0),
probe_out180(0) => NLW_inst_probe_out180_UNCONNECTED(0),
probe_out181(0) => NLW_inst_probe_out181_UNCONNECTED(0),
probe_out182(0) => NLW_inst_probe_out182_UNCONNECTED(0),
probe_out183(0) => NLW_inst_probe_out183_UNCONNECTED(0),
probe_out184(0) => NLW_inst_probe_out184_UNCONNECTED(0),
probe_out185(0) => NLW_inst_probe_out185_UNCONNECTED(0),
probe_out186(0) => NLW_inst_probe_out186_UNCONNECTED(0),
probe_out187(0) => NLW_inst_probe_out187_UNCONNECTED(0),
probe_out188(0) => NLW_inst_probe_out188_UNCONNECTED(0),
probe_out189(0) => NLW_inst_probe_out189_UNCONNECTED(0),
probe_out19(0) => NLW_inst_probe_out19_UNCONNECTED(0),
probe_out190(0) => NLW_inst_probe_out190_UNCONNECTED(0),
probe_out191(0) => NLW_inst_probe_out191_UNCONNECTED(0),
probe_out192(0) => NLW_inst_probe_out192_UNCONNECTED(0),
probe_out193(0) => NLW_inst_probe_out193_UNCONNECTED(0),
probe_out194(0) => NLW_inst_probe_out194_UNCONNECTED(0),
probe_out195(0) => NLW_inst_probe_out195_UNCONNECTED(0),
probe_out196(0) => NLW_inst_probe_out196_UNCONNECTED(0),
probe_out197(0) => NLW_inst_probe_out197_UNCONNECTED(0),
probe_out198(0) => NLW_inst_probe_out198_UNCONNECTED(0),
probe_out199(0) => NLW_inst_probe_out199_UNCONNECTED(0),
probe_out2(0) => NLW_inst_probe_out2_UNCONNECTED(0),
probe_out20(0) => NLW_inst_probe_out20_UNCONNECTED(0),
probe_out200(0) => NLW_inst_probe_out200_UNCONNECTED(0),
probe_out201(0) => NLW_inst_probe_out201_UNCONNECTED(0),
probe_out202(0) => NLW_inst_probe_out202_UNCONNECTED(0),
probe_out203(0) => NLW_inst_probe_out203_UNCONNECTED(0),
probe_out204(0) => NLW_inst_probe_out204_UNCONNECTED(0),
probe_out205(0) => NLW_inst_probe_out205_UNCONNECTED(0),
probe_out206(0) => NLW_inst_probe_out206_UNCONNECTED(0),
probe_out207(0) => NLW_inst_probe_out207_UNCONNECTED(0),
probe_out208(0) => NLW_inst_probe_out208_UNCONNECTED(0),
probe_out209(0) => NLW_inst_probe_out209_UNCONNECTED(0),
probe_out21(0) => NLW_inst_probe_out21_UNCONNECTED(0),
probe_out210(0) => NLW_inst_probe_out210_UNCONNECTED(0),
probe_out211(0) => NLW_inst_probe_out211_UNCONNECTED(0),
probe_out212(0) => NLW_inst_probe_out212_UNCONNECTED(0),
probe_out213(0) => NLW_inst_probe_out213_UNCONNECTED(0),
probe_out214(0) => NLW_inst_probe_out214_UNCONNECTED(0),
probe_out215(0) => NLW_inst_probe_out215_UNCONNECTED(0),
probe_out216(0) => NLW_inst_probe_out216_UNCONNECTED(0),
probe_out217(0) => NLW_inst_probe_out217_UNCONNECTED(0),
probe_out218(0) => NLW_inst_probe_out218_UNCONNECTED(0),
probe_out219(0) => NLW_inst_probe_out219_UNCONNECTED(0),
probe_out22(0) => NLW_inst_probe_out22_UNCONNECTED(0),
probe_out220(0) => NLW_inst_probe_out220_UNCONNECTED(0),
probe_out221(0) => NLW_inst_probe_out221_UNCONNECTED(0),
probe_out222(0) => NLW_inst_probe_out222_UNCONNECTED(0),
probe_out223(0) => NLW_inst_probe_out223_UNCONNECTED(0),
probe_out224(0) => NLW_inst_probe_out224_UNCONNECTED(0),
probe_out225(0) => NLW_inst_probe_out225_UNCONNECTED(0),
probe_out226(0) => NLW_inst_probe_out226_UNCONNECTED(0),
probe_out227(0) => NLW_inst_probe_out227_UNCONNECTED(0),
probe_out228(0) => NLW_inst_probe_out228_UNCONNECTED(0),
probe_out229(0) => NLW_inst_probe_out229_UNCONNECTED(0),
probe_out23(0) => NLW_inst_probe_out23_UNCONNECTED(0),
probe_out230(0) => NLW_inst_probe_out230_UNCONNECTED(0),
probe_out231(0) => NLW_inst_probe_out231_UNCONNECTED(0),
probe_out232(0) => NLW_inst_probe_out232_UNCONNECTED(0),
probe_out233(0) => NLW_inst_probe_out233_UNCONNECTED(0),
probe_out234(0) => NLW_inst_probe_out234_UNCONNECTED(0),
probe_out235(0) => NLW_inst_probe_out235_UNCONNECTED(0),
probe_out236(0) => NLW_inst_probe_out236_UNCONNECTED(0),
probe_out237(0) => NLW_inst_probe_out237_UNCONNECTED(0),
probe_out238(0) => NLW_inst_probe_out238_UNCONNECTED(0),
probe_out239(0) => NLW_inst_probe_out239_UNCONNECTED(0),
probe_out24(0) => NLW_inst_probe_out24_UNCONNECTED(0),
probe_out240(0) => NLW_inst_probe_out240_UNCONNECTED(0),
probe_out241(0) => NLW_inst_probe_out241_UNCONNECTED(0),
probe_out242(0) => NLW_inst_probe_out242_UNCONNECTED(0),
probe_out243(0) => NLW_inst_probe_out243_UNCONNECTED(0),
probe_out244(0) => NLW_inst_probe_out244_UNCONNECTED(0),
probe_out245(0) => NLW_inst_probe_out245_UNCONNECTED(0),
probe_out246(0) => NLW_inst_probe_out246_UNCONNECTED(0),
probe_out247(0) => NLW_inst_probe_out247_UNCONNECTED(0),
probe_out248(0) => NLW_inst_probe_out248_UNCONNECTED(0),
probe_out249(0) => NLW_inst_probe_out249_UNCONNECTED(0),
probe_out25(0) => NLW_inst_probe_out25_UNCONNECTED(0),
probe_out250(0) => NLW_inst_probe_out250_UNCONNECTED(0),
probe_out251(0) => NLW_inst_probe_out251_UNCONNECTED(0),
probe_out252(0) => NLW_inst_probe_out252_UNCONNECTED(0),
probe_out253(0) => NLW_inst_probe_out253_UNCONNECTED(0),
probe_out254(0) => NLW_inst_probe_out254_UNCONNECTED(0),
probe_out255(0) => NLW_inst_probe_out255_UNCONNECTED(0),
probe_out26(0) => NLW_inst_probe_out26_UNCONNECTED(0),
probe_out27(0) => NLW_inst_probe_out27_UNCONNECTED(0),
probe_out28(0) => NLW_inst_probe_out28_UNCONNECTED(0),
probe_out29(0) => NLW_inst_probe_out29_UNCONNECTED(0),
probe_out3(0) => NLW_inst_probe_out3_UNCONNECTED(0),
probe_out30(0) => NLW_inst_probe_out30_UNCONNECTED(0),
probe_out31(0) => NLW_inst_probe_out31_UNCONNECTED(0),
probe_out32(0) => NLW_inst_probe_out32_UNCONNECTED(0),
probe_out33(0) => NLW_inst_probe_out33_UNCONNECTED(0),
probe_out34(0) => NLW_inst_probe_out34_UNCONNECTED(0),
probe_out35(0) => NLW_inst_probe_out35_UNCONNECTED(0),
probe_out36(0) => NLW_inst_probe_out36_UNCONNECTED(0),
probe_out37(0) => NLW_inst_probe_out37_UNCONNECTED(0),
probe_out38(0) => NLW_inst_probe_out38_UNCONNECTED(0),
probe_out39(0) => NLW_inst_probe_out39_UNCONNECTED(0),
probe_out4(0) => NLW_inst_probe_out4_UNCONNECTED(0),
probe_out40(0) => NLW_inst_probe_out40_UNCONNECTED(0),
probe_out41(0) => NLW_inst_probe_out41_UNCONNECTED(0),
probe_out42(0) => NLW_inst_probe_out42_UNCONNECTED(0),
probe_out43(0) => NLW_inst_probe_out43_UNCONNECTED(0),
probe_out44(0) => NLW_inst_probe_out44_UNCONNECTED(0),
probe_out45(0) => NLW_inst_probe_out45_UNCONNECTED(0),
probe_out46(0) => NLW_inst_probe_out46_UNCONNECTED(0),
probe_out47(0) => NLW_inst_probe_out47_UNCONNECTED(0),
probe_out48(0) => NLW_inst_probe_out48_UNCONNECTED(0),
probe_out49(0) => NLW_inst_probe_out49_UNCONNECTED(0),
probe_out5(0) => NLW_inst_probe_out5_UNCONNECTED(0),
probe_out50(0) => NLW_inst_probe_out50_UNCONNECTED(0),
probe_out51(0) => NLW_inst_probe_out51_UNCONNECTED(0),
probe_out52(0) => NLW_inst_probe_out52_UNCONNECTED(0),
probe_out53(0) => NLW_inst_probe_out53_UNCONNECTED(0),
probe_out54(0) => NLW_inst_probe_out54_UNCONNECTED(0),
probe_out55(0) => NLW_inst_probe_out55_UNCONNECTED(0),
probe_out56(0) => NLW_inst_probe_out56_UNCONNECTED(0),
probe_out57(0) => NLW_inst_probe_out57_UNCONNECTED(0),
probe_out58(0) => NLW_inst_probe_out58_UNCONNECTED(0),
probe_out59(0) => NLW_inst_probe_out59_UNCONNECTED(0),
probe_out6(0) => NLW_inst_probe_out6_UNCONNECTED(0),
probe_out60(0) => NLW_inst_probe_out60_UNCONNECTED(0),
probe_out61(0) => NLW_inst_probe_out61_UNCONNECTED(0),
probe_out62(0) => NLW_inst_probe_out62_UNCONNECTED(0),
probe_out63(0) => NLW_inst_probe_out63_UNCONNECTED(0),
probe_out64(0) => NLW_inst_probe_out64_UNCONNECTED(0),
probe_out65(0) => NLW_inst_probe_out65_UNCONNECTED(0),
probe_out66(0) => NLW_inst_probe_out66_UNCONNECTED(0),
probe_out67(0) => NLW_inst_probe_out67_UNCONNECTED(0),
probe_out68(0) => NLW_inst_probe_out68_UNCONNECTED(0),
probe_out69(0) => NLW_inst_probe_out69_UNCONNECTED(0),
probe_out7(0) => NLW_inst_probe_out7_UNCONNECTED(0),
probe_out70(0) => NLW_inst_probe_out70_UNCONNECTED(0),
probe_out71(0) => NLW_inst_probe_out71_UNCONNECTED(0),
probe_out72(0) => NLW_inst_probe_out72_UNCONNECTED(0),
probe_out73(0) => NLW_inst_probe_out73_UNCONNECTED(0),
probe_out74(0) => NLW_inst_probe_out74_UNCONNECTED(0),
probe_out75(0) => NLW_inst_probe_out75_UNCONNECTED(0),
probe_out76(0) => NLW_inst_probe_out76_UNCONNECTED(0),
probe_out77(0) => NLW_inst_probe_out77_UNCONNECTED(0),
probe_out78(0) => NLW_inst_probe_out78_UNCONNECTED(0),
probe_out79(0) => NLW_inst_probe_out79_UNCONNECTED(0),
probe_out8(0) => NLW_inst_probe_out8_UNCONNECTED(0),
probe_out80(0) => NLW_inst_probe_out80_UNCONNECTED(0),
probe_out81(0) => NLW_inst_probe_out81_UNCONNECTED(0),
probe_out82(0) => NLW_inst_probe_out82_UNCONNECTED(0),
probe_out83(0) => NLW_inst_probe_out83_UNCONNECTED(0),
probe_out84(0) => NLW_inst_probe_out84_UNCONNECTED(0),
probe_out85(0) => NLW_inst_probe_out85_UNCONNECTED(0),
probe_out86(0) => NLW_inst_probe_out86_UNCONNECTED(0),
probe_out87(0) => NLW_inst_probe_out87_UNCONNECTED(0),
probe_out88(0) => NLW_inst_probe_out88_UNCONNECTED(0),
probe_out89(0) => NLW_inst_probe_out89_UNCONNECTED(0),
probe_out9(0) => NLW_inst_probe_out9_UNCONNECTED(0),
probe_out90(0) => NLW_inst_probe_out90_UNCONNECTED(0),
probe_out91(0) => NLW_inst_probe_out91_UNCONNECTED(0),
probe_out92(0) => NLW_inst_probe_out92_UNCONNECTED(0),
probe_out93(0) => NLW_inst_probe_out93_UNCONNECTED(0),
probe_out94(0) => NLW_inst_probe_out94_UNCONNECTED(0),
probe_out95(0) => NLW_inst_probe_out95_UNCONNECTED(0),
probe_out96(0) => NLW_inst_probe_out96_UNCONNECTED(0),
probe_out97(0) => NLW_inst_probe_out97_UNCONNECTED(0),
probe_out98(0) => NLW_inst_probe_out98_UNCONNECTED(0),
probe_out99(0) => NLW_inst_probe_out99_UNCONNECTED(0),
sl_iport0(36 downto 0) => B"0000000000000000000000000000000000000",
sl_oport0(16 downto 0) => NLW_inst_sl_oport0_UNCONNECTED(16 downto 0)
);
end STRUCTURE;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_01_tb_01_03.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity shift_adder is
port ( addend : in integer; augend : in integer;
sum : out integer;
add_control : in bit );
end entity shift_adder;
architecture behavior of shift_adder is
begin
end architecture behavior;
------------------------------------------------------------------------
entity reg is
port ( d : in integer; q : out integer;
en : in bit; reset : in bit );
end entity reg;
architecture behavior of reg is
begin
end architecture behavior;
------------------------------------------------------------------------
entity shift_reg is
port ( d : in integer; q : out bit;
load : in bit; clk : in bit );
end entity shift_reg;
architecture behavior of shift_reg is
begin
end architecture behavior;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_01_tb_01_03.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity shift_adder is
port ( addend : in integer; augend : in integer;
sum : out integer;
add_control : in bit );
end entity shift_adder;
architecture behavior of shift_adder is
begin
end architecture behavior;
------------------------------------------------------------------------
entity reg is
port ( d : in integer; q : out integer;
en : in bit; reset : in bit );
end entity reg;
architecture behavior of reg is
begin
end architecture behavior;
------------------------------------------------------------------------
entity shift_reg is
port ( d : in integer; q : out bit;
load : in bit; clk : in bit );
end entity shift_reg;
architecture behavior of shift_reg is
begin
end architecture behavior;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_01_tb_01_03.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity shift_adder is
port ( addend : in integer; augend : in integer;
sum : out integer;
add_control : in bit );
end entity shift_adder;
architecture behavior of shift_adder is
begin
end architecture behavior;
------------------------------------------------------------------------
entity reg is
port ( d : in integer; q : out integer;
en : in bit; reset : in bit );
end entity reg;
architecture behavior of reg is
begin
end architecture behavior;
------------------------------------------------------------------------
entity shift_reg is
port ( d : in integer; q : out bit;
load : in bit; clk : in bit );
end entity shift_reg;
architecture behavior of shift_reg is
begin
end architecture behavior;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 11-04-2016
-- Module Name: main.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity main is
port (clk, free, reset : in std_logic;
address : in std_logic_vector(3 downto 0);
done : out std_logic;
memory : out std_logic_vector(3 downto 0));
end entity;
architecture rtl of main is
component datapath
port (g, e, l : out std_logic;
clk : in std_logic;
sel_1 : in std_logic;
sel_2 : in std_logic_vector(1 downto 0);
counter_reset : in std_logic;
counter_enable : in std_logic;
rwbar : in std_logic;
load : in std_logic;
counter_done : out std_logic;
input_address : in std_logic_vector(3 downto 0));
end component;
component controller
port (g, e, l : in std_logic;
clk : in std_logic;
reset : in std_logic;
sel_1 : out std_logic;
sel_2 : out std_logic_vector(1 downto 0);
counter_reset : out std_logic;
counter_enable : out std_logic;
load : out std_logic;
counter_done : in std_logic;
free: in std_logic;
done: out std_logic;
rwbar : out std_logic);
end component;
for all:datapath use entity work.datapath;
for all:controller use entity work.controller;
signal g, e, l, sel_1, counter_reset, counter_enable, rwbar, counter_done, load : std_logic;
signal sel_2 : std_logic_vector(1 downto 0);
begin
dp : datapath port map(g, e, l, clk, sel_1, sel_2, counter_reset, counter_enable, rwbar, load, counter_done, address);
cc : controller port map(g, e, l, clk, reset, sel_1, sel_2, counter_reset, counter_enable, load, counter_done, free, done, rwbar);
end architecture;
|
-- NEED RESULT: ARCH00478: Choices in an element association of an aggregate may contain several or no choices passed
-- NEED RESULT: ARCH00478: Element simple name properly disambiguated from simple expressions in aggregate element associations passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00478
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.2 (3)
-- 7.3.2 (4)
-- 7.3.2 (5)
-- 7.3.2 (6)
-- 7.3.2 (8)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00478)
-- ENT00478_Test_Bench(ARCH00478_Test_Bench)
--
-- REVISION HISTORY:
--
-- 6-AUG-1987 - initial revision
-- 5-MAY-1988 -CSW
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00478 of E00000 is
type rec_1 is record
f1 : integer ;
f2 : integer ;
f3 : boolean ;
f4 : real ;
end record ;
type rec_2 is record
f1 : integer ;
end record ;
type arr_1 is array ( integer range <> ) of rec_1 ;
begin
process
constant c_int1 : integer := 1 ;
constant f1 : integer := 3 ;
variable v_int1 : integer := 10 ;
variable v_int2 : integer := 1 ;
variable v_int3 : integer := 5 ;
variable v_bool1 : boolean := true ;
variable v_real1 : real := 3.5 ;
subtype st_arr_1 is arr_1 ( 1 to 4 ) ;
subtype st_arr_2 is arr_1 ( v_int2 to v_int3 ) ;
subtype st_arr_3 is arr_1 ( 2 to 2 ) ;
variable v_arr_1_1, v_arr_1_2 : st_arr_1 ;
variable v_arr_2_1, v_arr_2_2 : st_arr_2 ;
variable v_arr_3_1, v_arr_3_2 : st_arr_3 ;
variable v_rec_1_1, v_rec_1_2 : rec_1 ;
variable v_rec_2_2 : rec_2 ;
variable bool : boolean := true ;
begin
v_rec_1_1 := ( v_int1, v_int2, v_bool1, v_real1 );
v_rec_1_2 := ( f1 | f2 => 3 , f3 => false , f4 => 0.0 ) ;
v_arr_1_1 := ( 1 to 2 | f1 | 4 => v_rec_1_1 ) ;
v_arr_1_2 := ( 1 to 2 | 10 - 6 downto 3 + c_int1 => v_rec_1_2,
others => v_rec_1_1 ) ;
v_arr_2_1 := ( v_rec_1_1, v_rec_1_2, v_rec_1_1, v_rec_1_1, v_rec_1_2 ) ;
v_arr_2_2 := ( 5 downto 1 => v_rec_1_1 ) ;
v_arr_3_1 := ( 2 to 2 => v_rec_1_2 ) ;
v_arr_3_2 := ( others => v_rec_1_1 ) ;
bool := bool and v_rec_1_1.f1 = v_int1 ;
bool := bool and v_rec_1_1.f2 = v_int2 ;
bool := bool and v_rec_1_1.f3 = v_bool1 ;
bool := bool and v_rec_1_1.f4 = v_real1 ;
for i in 1 to 4 loop
bool := bool and v_arr_1_1(i) = v_rec_1_1 ;
end loop ;
bool := bool and v_arr_1_2(1) = v_rec_1_2 ;
bool := bool and v_arr_1_2(2) = v_rec_1_2 ;
bool := bool and v_arr_1_2(3) = v_rec_1_1 ;
bool := bool and v_arr_1_2(4) = v_rec_1_2 ;
bool := bool and v_arr_2_1(1) = v_rec_1_1 ;
bool := bool and v_arr_2_1(2) = v_rec_1_2 ;
bool := bool and v_arr_2_1(3) = v_rec_1_1 ;
bool := bool and v_arr_2_1(4) = v_rec_1_1 ;
bool := bool and v_arr_2_1(5) = v_rec_1_2 ;
for i in 5 downto 1 loop
bool := bool and v_arr_2_2(i) = v_rec_1_1 ;
end loop ;
bool := bool and v_arr_3_1(2) = v_rec_1_2 ;
bool := bool and v_arr_3_2(2) = v_rec_1_1 ;
test_report ( "ARCH00478" ,
"Choices in an element association of an aggregate"
& " may contain several or no choices" ,
bool ) ;
v_rec_2_2 := ( f1 => f1 ) ;
v_arr_1_1 := ( f1 => v_rec_1_2, others => v_rec_1_1 ) ;
test_report ( "ARCH00478" ,
"Element simple name properly disambiguated from simple"
& " expressions in aggregate element associations" ,
v_rec_2_2.f1 = 3 and v_arr_1_1(3) = v_rec_1_2 ) ;
wait ;
end process ;
end ARCH00478 ;
entity ENT00478_Test_Bench is
end ENT00478_Test_Bench ;
architecture ARCH00478_Test_Bench of ENT00478_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00478 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00478_Test_Bench ;
|
---------------------------------------------------------------
-- Title : VME bus slave simmodel
-- Project : A15
---------------------------------------------------------------
-- File : vme_sim_slave.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 02/09/03
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (C) 2001, MEN Mikroelektronik Nuernberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: vme_sim_slave.vhd,v $
-- Revision 1.2 2013/04/18 15:11:16 MMiehling
-- added irq
--
-- Revision 1.1 2012/03/29 10:28:50 MMiehling
-- Initial Revision
--
-- Revision 1.3 2006/05/18 14:31:30 MMiehling
-- correct behaviour of iack
--
-- Revision 1.2 2006/05/15 10:36:23 MMiehling
-- now support of 0x0B, 0x0F, 0x3B, 0x3F => 32Bit Block Transfer
--
-- Revision 1.1 2005/10/28 17:52:18 mmiehling
-- Initial Revision
--
-- Revision 1.2 2004/08/13 15:36:06 mmiehling
-- updated
--
-- Revision 1.1 2004/07/27 17:28:15 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee,work;
USE ieee.std_logic_1164.ALL;
USE work.vme_sim_pack.ALL;
USE ieee.std_logic_unsigned.ALL;
USE std.textio.all;
USE work.print_pkg.all;
ENTITY vme_sim_slave IS
PORT (
sysresin : IN std_logic;
asn_in : IN std_logic;
dsan_in : IN std_logic;
dsbn_in : IN std_logic;
writen_in : IN std_logic;
berrn_in : IN std_logic;
addr : INOUT std_logic_vector(31 DOWNTO 0);
data_in : IN std_logic_vector(31 DOWNTO 0);
am_in : IN std_logic_vector(5 DOWNTO 0);
iackn_in : IN std_logic; -- daisy-chain
iackn : IN std_logic; -- bussignal
irq_out : OUT std_logic_vector(7 DOWNTO 1);
dtackn_out : OUT std_logic;
data_out : OUT std_logic_vector(31 DOWNTO 0);
vb_irq1n : IN std_logic;
vb_irq2n : IN std_logic;
vb_irq3n : IN std_logic;
vb_irq4n : IN std_logic;
vb_irq5n : IN std_logic;
vb_irq6n : IN std_logic;
vb_irq7n : IN std_logic;
vme_slv_in : IN vme_slv_in_type;
vme_slv_out : OUT vme_slv_out_type
);
END vme_sim_slave;
ARCHITECTURE vme_sim_slave_arch OF vme_sim_slave IS
SUBTYPE irq_vec IS std_logic_vector(7 DOWNTO 0);
TYPE irq_id_type IS array (7 DOWNTO 1) OF irq_vec;
SIGNAL sim_slave_active : std_logic;
SIGNAL iackn_in_int : std_logic;
SIGNAL conf_ack : boolean;
BEGIN
iackn_in_int <= '0' WHEN iackn_in = '0' AND (dsan_in = '0' OR dsbn_in = '0') ELSE '1';
vme_slv_out.conf_ack <= conf_ack;
vme_slv_out.irq(1) <= vb_irq1n;
vme_slv_out.irq(2) <= vb_irq2n;
vme_slv_out.irq(3) <= vb_irq3n;
vme_slv_out.irq(4) <= vb_irq4n;
vme_slv_out.irq(5) <= vb_irq5n;
vme_slv_out.irq(6) <= vb_irq6n;
vme_slv_out.irq(7) <= vb_irq7n;
slave : PROCESS
VARIABLE asn_time : time;
VARIABLE zeit : time;
VARIABLE addr_int : std_logic_vector(31 DOWNTO 0);
VARIABLE first_d64_cycle : boolean;
VARIABLE am_int : std_logic_vector(5 DOWNTO 0);
VARIABLE i : integer;
VARIABLE ws, sd : integer;
VARIABLE lin:line;
VARIABLE data : std_logic_vector(31 DOWNTO 0);
VARIABLE check:boolean;
VARIABLE adr_int : std_logic_vector(31 DOWNTO 3);
VARIABLE end_of_acc : std_logic;
VARIABLE mem_head : head_ptr;
VARIABLE allocated : boolean;
VARIABLE irq_id : irq_id_type;
VARIABLE irq : integer;
BEGIN
mem_head := new head'(0,null);
sim_slave_active <= '0';
data_out <= (OTHERS => 'Z');
am_int := (others => '0');
first_d64_cycle := TRUE;
conf_ack <= vme_slv_in.conf_req;
addr <= (OTHERS => 'H');
dtackn_out <= 'H';
irq_out <= (OTHERS => 'H');
irq := 0;
WAIT UNTIL sysresin /= '0'; --ohne EVENT
gen_loop: LOOP -- main loop
data_out <= (OTHERS => 'Z');
IF asn_in /= '0' OR (vme_slv_in.conf_req/= conf_ack) THEN
WAIT until falling_edge(asn_in) OR vme_slv_in.conf_req'event;
END IF;
----------------------------------------------------------------------------------------
-- config access
----------------------------------------------------------------------------------------
IF vme_slv_in.conf_req /= conf_ack THEN
IF vme_slv_in.req_type = 1 THEN
--WRITE
adr_int:=vme_slv_in.adr(31 DOWNTO 3);
wr_data(conv_integer(adr_int), vme_slv_in.wr_dat, "1111", mem_head);
ELSIF vme_slv_in.req_type = 0 THEN
-- read from iram
rd_data(conv_integer(vme_slv_in.adr(31 DOWNTO 3)), data, allocated, mem_head);
vme_slv_out.rd_dat <= data;
ELSIF vme_slv_in.req_type = 2 THEN
-- set irq request
irq_out(vme_slv_in.irq) <= '0';
irq := vme_slv_in.irq;
irq_id(irq) := vme_slv_in.wr_dat(7 DOWNTO 0);
ELSIF vme_slv_in.req_type = 3 THEN
-- request of last address modifier used
vme_slv_out.rd_am <= am_int;
END IF;
conf_ack <= vme_slv_in.conf_req; -- handshake acknowledge
next gen_loop;
END IF;
----------------------------------------------------------------------------------------
-- vme access
----------------------------------------------------------------------------------------
addr_int := addr;
am_int := am_in;
first_d64_cycle := TRUE;
LOOP
asn_time := now;
IF NOT (dsan_in = '0' OR dsbn_in = '0') AND asn_in = '0' THEN
WAIT until (dsan_in = '0' OR dsbn_in = '0' OR asn_in /= '0');
END IF;
IF asn_in /= '0' THEN
exit;
END IF;
-- D64 burst
IF iackn /= '0' AND (
(addr_int(31 DOWNTO 28) = sl_base_A32 AND (am_int(5 DOWNTO 0) = AM_A32_NONPRIV_MBLT OR am_int(5 DOWNTO 0) = AM_A32_SUPER_MBLT)) or
(addr_int(23 DOWNTO 20) = sl_base_A24 AND (am_int(5 DOWNTO 0) = AM_A24_NONPRIV_MBLT OR am_int(5 DOWNTO 0) = AM_A24_SUPER_MBLT))) THEN
sim_slave_active <= '1';
IF writen_in = '1' THEN -- READ
WAIT FOR time_26;
IF first_d64_cycle = FALSE THEN
rd_data(conv_integer(addr_int(11 DOWNTO 2)), data, allocated, mem_head);
addr(31 DOWNTO 24) <= data(31 DOWNTO 24);
addr(23 DOWNTO 16) <= data(23 DOWNTO 16);
addr(15 DOWNTO 8) <= data(15 DOWNTO 8);
addr(7 DOWNTO 0) <= data(7 DOWNTO 0);
rd_data(conv_integer(addr_int(11 DOWNTO 2)+1), data, allocated, mem_head);
data_out(31 DOWNTO 24) <= data(31 DOWNTO 24);
data_out(23 DOWNTO 16) <= data(23 DOWNTO 16);
data_out(15 DOWNTO 8) <= data(15 DOWNTO 8);
data_out(7 DOWNTO 0) <= data(7 DOWNTO 0);
addr_int := addr_int + 8;
END IF;
WAIT FOR time_27;
dtackn_out <= '0';
IF dsan_in = '0' THEN
WAIT until rising_edge(dsan_in);
END IF;
IF dsbn_in = '0' THEN
WAIT until rising_edge(dsbn_in);
END IF;
data_out <= (OTHERS => 'H');
addr <= (OTHERS => 'H');
WAIT FOR 10 ns;
-- WAIT FOR 120 ns; -- extended to simulate slow slave with long dtackn active
dtackn_out <= 'H';
ELSE -- WRITE
IF first_d64_cycle = FALSE THEN
IF NOT (data_in'stable(time_8)) then
print("vme_sim: Data[31:0] was not stable for time(8)!");
ASSERT FALSE REPORT " Timingfehler! " SEVERITY error;
END IF;
IF NOT (addr'stable(time_8)) then
print("vme_sim: Addr[31:0] was not stable for time(8)!");
ASSERT FALSE REPORT " Timingfehler! " SEVERITY error;
END IF;
WAIT FOR time_28;
wr_data(conv_integer(addr_int(11 DOWNTO 2)), addr, "1111", mem_head);
wr_data(conv_integer(addr_int(11 DOWNTO 2)+1), data_in, "1111", mem_head);
addr_int := addr_int + 8;
ELSE
WAIT FOR time_28;
END IF;
dtackn_out <= '0';
IF dsan_in = '0' THEN
WAIT until rising_edge(dsan_in);
END IF;
IF dsbn_in = '0' THEN
WAIT until rising_edge(dsbn_in);
END IF;
WAIT FOR 10 ns;
-- WAIT FOR 120 ns; -- extended to simulate slow slave with long dtackn active
dtackn_out <= 'H';
END IF;
first_d64_cycle := FALSE;
-- all normal accesses
ELSIF iackn /= '0' AND ( (addr_int(15 DOWNTO 12) = sl_base_A16 AND am_int(5 DOWNTO 4) = "10") OR
(addr_int(23 DOWNTO 20) = sl_base_A24 AND am_int(5 DOWNTO 4) = "11") OR
(addr_int(23 DOWNTO 20) = sl_base_CRCSR AND am_int(5 DOWNTO 0) = AM_CRCSR) OR
(addr_int(31 DOWNTO 28) = sl_base_A32 AND am_int(5 DOWNTO 4) = "00") )THEN
sim_slave_active <= '1';
IF writen_in = '1' THEN -- READ
WAIT FOR (time_28 - time_27);
dtackn_out <= '0';
IF (dsbn_in = '0' AND dsan_in = '0' AND addr_int(1 DOWNTO 0) = "01") OR
(dsbn_in = '0' AND dsan_in /= '0' AND addr_int(1 DOWNTO 0) = "01") OR
(dsbn_in /= '0' AND dsan_in = '0' AND addr_int(1 DOWNTO 0) = "01") THEN
rd_data(conv_integer(addr_int(11 DOWNTO 2)), data, allocated, mem_head);
data_out(15 DOWNTO 0) <= data(31 DOWNTO 16);
data_out(31 DOWNTO 16) <= data(15 DOWNTO 0);
ELSE
rd_data(conv_integer(addr_int(11 DOWNTO 2)), data, allocated, mem_head);
data_out <= data;
END IF;
IF dsan_in = '0' THEN
WAIT until rising_edge(dsan_in);
END IF;
IF dsbn_in = '0' THEN
WAIT until rising_edge(dsbn_in);
END IF;
data_out <= (OTHERS => 'H');
WAIT FOR 10 ns;
dtackn_out <= 'H';
ELSE -- WRITE
IF NOT (data_in'stable(time_8)) then
print("vme_sim: Data[31:0] was not stable for time(8)!");
ASSERT FALSE REPORT " Timingfehler! " SEVERITY error;
END IF;
WAIT FOR time_28;
IF addr_int(0) = '1' THEN -- lwordn = '1' => D16
data := data_in(15 DOWNTO 8) & data_in(7 DOWNTO 0) & data_in(15 DOWNTO 8) & data_in(7 DOWNTO 0);
IF dsan_in /= '0' AND dsbn_in = '0' AND addr_int(1) = '0' THEN
wr_data(conv_integer(addr_int(11 DOWNTO 2)), data, "1000", mem_head);
ELSIF dsan_in = '0' AND dsbn_in /= '0' AND addr_int(1) = '0' THEN
wr_data(conv_integer(addr_int(11 DOWNTO 2)), data, "0100", mem_head);
ELSIF dsan_in /= '0' AND dsbn_in = '0' AND addr_int(1) = '1' THEN
wr_data(conv_integer(addr_int(11 DOWNTO 2)), data, "0010", mem_head);
ELSIF dsan_in = '0' AND dsbn_in /= '0' AND addr_int(1) = '1' THEN
wr_data(conv_integer(addr_int(11 DOWNTO 2)), data, "0001", mem_head);
ELSIF dsan_in = '0' AND dsbn_in = '0' AND addr_int(1) = '0' THEN
wr_data(conv_integer(addr_int(11 DOWNTO 2)), data, "1100", mem_head);
ELSIF dsan_in = '0' AND dsbn_in = '0' AND addr_int(1) = '1' THEN
wr_data(conv_integer(addr_int(11 DOWNTO 2)), data, "0011", mem_head);
END IF;
ELSE
data := data_in;
IF dsan_in = '0' AND dsbn_in = '0' AND addr_int(1) = '0' THEN
wr_data(conv_integer(addr_int(11 DOWNTO 2)), data, "1111", mem_head);
END IF;
END IF;
dtackn_out <= '0';
IF dsan_in = '0' THEN
WAIT until rising_edge(dsan_in);
END IF;
IF dsbn_in = '0' THEN
WAIT until rising_edge(dsbn_in);
END IF;
WAIT FOR 10 ns;
dtackn_out <= 'H';
END IF;
-- 0x0B, 0x0F, 0x3B, 0x3F => 32Bit Block Transfer
IF am_int = AM_A32_NONPRIV_BLT OR am_int = AM_A32_SUPER_BLT OR am_int = AM_A24_NONPRIV_BLT OR am_int = AM_A24_SUPER_BLT THEN
IF addr_int(0) = '0' THEN
addr_int := addr_int + 4;
ELSE
addr_int := addr_int + 2;
END IF;
END IF;
-- IACK-Cycle
ELSIF iackn = '0' THEN
IF iackn_in_int = '1' THEN
WAIT until (falling_edge(iackn_in_int) OR rising_edge(asn_in));
IF asn_in /= '0' THEN
exit;
END IF;
END IF;
sim_slave_active <= '1';
IF writen_in = '1' AND dsan_in = '0' AND dsbn_in /= '0' AND addr_int(0) = '1' THEN -- read iack D08
IF ((irq = 1 AND addr_int(3 DOWNTO 1) = "001") OR
(irq = 2 AND addr_int(3 DOWNTO 1) = "010") OR
(irq = 3 AND addr_int(3 DOWNTO 1) = "011") OR
(irq = 4 AND addr_int(3 DOWNTO 1) = "100") OR
(irq = 5 AND addr_int(3 DOWNTO 1) = "101") OR
(irq = 6 AND addr_int(3 DOWNTO 1) = "110") OR
(irq = 7 AND addr_int(3 DOWNTO 1) = "111")) THEN
WAIT FOR time_26;
data_out(7 DOWNTO 0) <= irq_id(irq); -- B(0)
data_out(31 DOWNTO 8) <= (OTHERS => '0');
WAIT FOR time_27;
irq_out <= (OTHERS => 'H');
irq := 0;
dtackn_out <= '0';
IF dsan_in = '0' THEN
WAIT until rising_edge(dsan_in);
END IF;
data_out <= (OTHERS => 'H');
WAIT FOR 10 ns;
dtackn_out <= 'H';
ELSE
WAIT until rising_edge(asn_in);
END IF;
ELSIF writen_in = '1' AND dsan_in = '0' AND dsbn_in = '0' AND addr_int(0) = '1' THEN -- read iack D16
IF ((irq = 1 AND addr_int(3 DOWNTO 1) = "001") OR
(irq = 2 AND addr_int(3 DOWNTO 1) = "010") OR
(irq = 3 AND addr_int(3 DOWNTO 1) = "011") OR
(irq = 4 AND addr_int(3 DOWNTO 1) = "100") OR
(irq = 5 AND addr_int(3 DOWNTO 1) = "101") OR
(irq = 6 AND addr_int(3 DOWNTO 1) = "110") OR
(irq = 7 AND addr_int(3 DOWNTO 1) = "111")) THEN
WAIT FOR time_26;
data_out(7 DOWNTO 0) <= irq_id(irq); -- B(0)
data_out(15 DOWNTO 8) <= irq_id(irq); -- B(0)
data_out(31 DOWNTO 16) <= (OTHERS => '0');
WAIT FOR time_27;
irq_out <= (OTHERS => 'H');
irq := 0;
dtackn_out <= '0';
IF dsan_in = '0' THEN
WAIT until rising_edge(dsan_in);
END IF;
data_out <= (OTHERS => 'H');
WAIT FOR 10 ns;
dtackn_out <= 'H';
ELSE
WAIT until rising_edge(asn_in);
END IF;
ELSIF writen_in = '1' AND dsan_in = '0' AND dsbn_in = '0' AND addr_int(0) = '1' THEN -- read iack D32
IF ((irq = 1 AND addr_int(3 DOWNTO 1) = "001") OR
(irq = 2 AND addr_int(3 DOWNTO 1) = "010") OR
(irq = 3 AND addr_int(3 DOWNTO 1) = "011") OR
(irq = 4 AND addr_int(3 DOWNTO 1) = "100") OR
(irq = 5 AND addr_int(3 DOWNTO 1) = "101") OR
(irq = 6 AND addr_int(3 DOWNTO 1) = "110") OR
(irq = 7 AND addr_int(3 DOWNTO 1) = "111")) THEN
WAIT FOR time_26;
data_out(7 DOWNTO 0) <= irq_id(irq); -- B(0)
data_out(15 DOWNTO 8) <= irq_id(irq); -- B(0)
data_out(23 DOWNTO 16) <= irq_id(irq); -- B(0)
data_out(31 DOWNTO 24) <= irq_id(irq); -- B(0)
WAIT FOR time_27;
irq_out <= (OTHERS => 'H');
irq := 0;
dtackn_out <= '0';
IF dsan_in = '0' THEN
WAIT until rising_edge(dsan_in);
END IF;
data_out <= (OTHERS => 'H');
WAIT FOR 10 ns;
dtackn_out <= 'H';
ELSE
WAIT until rising_edge(asn_in);
END IF;
ELSE
print("vme_sim: For IRQH D08(O) dsan=0, dsbn=1, writen=1, lwordn=1!");
ASSERT FALSE REPORT " Funktionsfehler! " SEVERITY error;
END IF;
ELSE -- if this slave is not addressed
WAIT until rising_edge(asn_in);
END IF;
sim_slave_active <= '0';
END LOOP;
END LOOP;
END PROCESS slave;
END vme_sim_slave_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc965.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p04n01i00965ent IS
END c06s03b00x00p04n01i00965ent;
ARCHITECTURE c06s03b00x00p04n01i00965arch OF c06s03b00x00p04n01i00965ent IS
type Rcd is record
RE1: BOOLEAN;
end record;
BEGIN
TESTING: PROCESS
variable var : Rcd;
BEGIN
var.RE1 := TRUE;
wait for 5 ns;
assert NOT(var.RE1 = TRUE)
report "***PASSED TEST: c06s03b00x00p04n01i00965"
severity NOTE;
assert (var.RE1 = TRUE)
report "***FAILED TEST: c06s03b00x00p04n01i00965 - Selected name should be able to be used to denote an element of a record."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p04n01i00965arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc965.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p04n01i00965ent IS
END c06s03b00x00p04n01i00965ent;
ARCHITECTURE c06s03b00x00p04n01i00965arch OF c06s03b00x00p04n01i00965ent IS
type Rcd is record
RE1: BOOLEAN;
end record;
BEGIN
TESTING: PROCESS
variable var : Rcd;
BEGIN
var.RE1 := TRUE;
wait for 5 ns;
assert NOT(var.RE1 = TRUE)
report "***PASSED TEST: c06s03b00x00p04n01i00965"
severity NOTE;
assert (var.RE1 = TRUE)
report "***FAILED TEST: c06s03b00x00p04n01i00965 - Selected name should be able to be used to denote an element of a record."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p04n01i00965arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc965.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p04n01i00965ent IS
END c06s03b00x00p04n01i00965ent;
ARCHITECTURE c06s03b00x00p04n01i00965arch OF c06s03b00x00p04n01i00965ent IS
type Rcd is record
RE1: BOOLEAN;
end record;
BEGIN
TESTING: PROCESS
variable var : Rcd;
BEGIN
var.RE1 := TRUE;
wait for 5 ns;
assert NOT(var.RE1 = TRUE)
report "***PASSED TEST: c06s03b00x00p04n01i00965"
severity NOTE;
assert (var.RE1 = TRUE)
report "***FAILED TEST: c06s03b00x00p04n01i00965 - Selected name should be able to be used to denote an element of a record."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p04n01i00965arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.file_io_pkg.all;
library std;
use std.textio.all;
entity tb_alu is
end tb_alu;
architecture tb of tb_alu is
signal c_in : std_logic := '0';
signal data_a : std_logic_vector(7 downto 0) := X"00";
signal data_b : std_logic_vector(7 downto 0) := X"00";
signal n_out : std_logic;
signal v_out : std_logic;
signal z_out : std_logic;
signal c_out : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal p_out : std_logic_vector(7 downto 0);
signal operation : std_logic_vector(2 downto 0) := "011"; -- ADC
signal p_reference : std_logic_vector(7 downto 0);
signal n_ref : std_logic;
signal v_ref : std_logic;
signal z_ref : std_logic;
signal c_ref : std_logic;
begin
p_out <= n_out & v_out & "111" & '0' & z_out & c_out;
ref_sum: process -- taken from real 6510
begin
wait for 1 ps;
if operation(2)='0' then -- adc
p_reference <= X"3A"; wait for 1 us;
p_reference <= X"38"; wait for 121 us;
p_reference <= X"F8"; wait for 6 us;
p_reference <= X"B8"; wait for 26 us;
p_reference <= X"B9"; wait for 96 us;
p_reference <= X"39"; wait for 6 us;
-- 01
p_reference <= X"38"; wait for 121 us;
p_reference <= X"F8"; wait for 7 us;
p_reference <= X"B8"; wait for 25 us;
p_reference <= X"B9"; wait for 96 us;
p_reference <= X"39"; wait for 6 us;
p_reference <= X"3B"; wait for 1 us;
else
p_reference <= X"3B"; wait for 1 us;
p_reference <= X"B8"; wait for 127 us;
p_reference <= X"F8"; wait for 1 us;
p_reference <= X"38"; wait for 127 us;
-- 01
p_reference <= X"39"; wait for 1 us;
p_reference <= X"3B"; wait for 1 us;
p_reference <= X"B8"; wait for 126 us;
p_reference <= X"F8"; wait for 2 us;
p_reference <= X"38"; wait for 126 us;
end if;
p_reference <= (others => 'U');
wait;
end process;
n_ref <= p_reference(7);
v_ref <= p_reference(6);
z_ref <= p_reference(1);
c_ref <= p_reference(0);
test: process
variable L : line;
begin
for i in 0 to 3 loop
-- data_a <= conv_std_logic_vector((i mod 10) + (i/10)*16,8);
data_a <= conv_std_logic_vector(i,8);
for j in 0 to 255 loop
data_b <= conv_std_logic_vector(j,8);
c_in <= operation(2);
wait for 500 ns;
-- check flags
assert c_out = c_ref or c_ref = 'U' report "Error in C-flag!" severity error;
assert z_out = z_ref or z_ref = 'U' report "Error in Z-flag!" severity error;
assert v_out = v_ref or v_ref = 'U' report "Error in V-flag!" severity error;
assert n_out = n_ref or n_ref = 'U' report "Error in N-flag!" severity error;
wait for 500 ns;
-- write(L, VecToHex(data_out, 2));
-- write(L, VecToHex(p_out, 2));
-- write(L, ',');
-- c_in <= '1';
-- wait for 1 us;
end loop;
-- writeline(output, L);
end loop;
wait;
end process;
mut: entity work.alu
generic map (true)
port map (
operation => operation,
enable => '1',
n_in => 'U',
v_in => 'U',
z_in => 'U',
c_in => c_in,
d_in => '1',
data_a => data_a,
data_b => data_b,
n_out => n_out,
v_out => v_out,
z_out => z_out,
c_out => c_out,
data_out => data_out );
end tb; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.file_io_pkg.all;
library std;
use std.textio.all;
entity tb_alu is
end tb_alu;
architecture tb of tb_alu is
signal c_in : std_logic := '0';
signal data_a : std_logic_vector(7 downto 0) := X"00";
signal data_b : std_logic_vector(7 downto 0) := X"00";
signal n_out : std_logic;
signal v_out : std_logic;
signal z_out : std_logic;
signal c_out : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal p_out : std_logic_vector(7 downto 0);
signal operation : std_logic_vector(2 downto 0) := "011"; -- ADC
signal p_reference : std_logic_vector(7 downto 0);
signal n_ref : std_logic;
signal v_ref : std_logic;
signal z_ref : std_logic;
signal c_ref : std_logic;
begin
p_out <= n_out & v_out & "111" & '0' & z_out & c_out;
ref_sum: process -- taken from real 6510
begin
wait for 1 ps;
if operation(2)='0' then -- adc
p_reference <= X"3A"; wait for 1 us;
p_reference <= X"38"; wait for 121 us;
p_reference <= X"F8"; wait for 6 us;
p_reference <= X"B8"; wait for 26 us;
p_reference <= X"B9"; wait for 96 us;
p_reference <= X"39"; wait for 6 us;
-- 01
p_reference <= X"38"; wait for 121 us;
p_reference <= X"F8"; wait for 7 us;
p_reference <= X"B8"; wait for 25 us;
p_reference <= X"B9"; wait for 96 us;
p_reference <= X"39"; wait for 6 us;
p_reference <= X"3B"; wait for 1 us;
else
p_reference <= X"3B"; wait for 1 us;
p_reference <= X"B8"; wait for 127 us;
p_reference <= X"F8"; wait for 1 us;
p_reference <= X"38"; wait for 127 us;
-- 01
p_reference <= X"39"; wait for 1 us;
p_reference <= X"3B"; wait for 1 us;
p_reference <= X"B8"; wait for 126 us;
p_reference <= X"F8"; wait for 2 us;
p_reference <= X"38"; wait for 126 us;
end if;
p_reference <= (others => 'U');
wait;
end process;
n_ref <= p_reference(7);
v_ref <= p_reference(6);
z_ref <= p_reference(1);
c_ref <= p_reference(0);
test: process
variable L : line;
begin
for i in 0 to 3 loop
-- data_a <= conv_std_logic_vector((i mod 10) + (i/10)*16,8);
data_a <= conv_std_logic_vector(i,8);
for j in 0 to 255 loop
data_b <= conv_std_logic_vector(j,8);
c_in <= operation(2);
wait for 500 ns;
-- check flags
assert c_out = c_ref or c_ref = 'U' report "Error in C-flag!" severity error;
assert z_out = z_ref or z_ref = 'U' report "Error in Z-flag!" severity error;
assert v_out = v_ref or v_ref = 'U' report "Error in V-flag!" severity error;
assert n_out = n_ref or n_ref = 'U' report "Error in N-flag!" severity error;
wait for 500 ns;
-- write(L, VecToHex(data_out, 2));
-- write(L, VecToHex(p_out, 2));
-- write(L, ',');
-- c_in <= '1';
-- wait for 1 us;
end loop;
-- writeline(output, L);
end loop;
wait;
end process;
mut: entity work.alu
generic map (true)
port map (
operation => operation,
enable => '1',
n_in => 'U',
v_in => 'U',
z_in => 'U',
c_in => c_in,
d_in => '1',
data_a => data_a,
data_b => data_b,
n_out => n_out,
v_out => v_out,
z_out => z_out,
c_out => c_out,
data_out => data_out );
end tb; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.file_io_pkg.all;
library std;
use std.textio.all;
entity tb_alu is
end tb_alu;
architecture tb of tb_alu is
signal c_in : std_logic := '0';
signal data_a : std_logic_vector(7 downto 0) := X"00";
signal data_b : std_logic_vector(7 downto 0) := X"00";
signal n_out : std_logic;
signal v_out : std_logic;
signal z_out : std_logic;
signal c_out : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal p_out : std_logic_vector(7 downto 0);
signal operation : std_logic_vector(2 downto 0) := "011"; -- ADC
signal p_reference : std_logic_vector(7 downto 0);
signal n_ref : std_logic;
signal v_ref : std_logic;
signal z_ref : std_logic;
signal c_ref : std_logic;
begin
p_out <= n_out & v_out & "111" & '0' & z_out & c_out;
ref_sum: process -- taken from real 6510
begin
wait for 1 ps;
if operation(2)='0' then -- adc
p_reference <= X"3A"; wait for 1 us;
p_reference <= X"38"; wait for 121 us;
p_reference <= X"F8"; wait for 6 us;
p_reference <= X"B8"; wait for 26 us;
p_reference <= X"B9"; wait for 96 us;
p_reference <= X"39"; wait for 6 us;
-- 01
p_reference <= X"38"; wait for 121 us;
p_reference <= X"F8"; wait for 7 us;
p_reference <= X"B8"; wait for 25 us;
p_reference <= X"B9"; wait for 96 us;
p_reference <= X"39"; wait for 6 us;
p_reference <= X"3B"; wait for 1 us;
else
p_reference <= X"3B"; wait for 1 us;
p_reference <= X"B8"; wait for 127 us;
p_reference <= X"F8"; wait for 1 us;
p_reference <= X"38"; wait for 127 us;
-- 01
p_reference <= X"39"; wait for 1 us;
p_reference <= X"3B"; wait for 1 us;
p_reference <= X"B8"; wait for 126 us;
p_reference <= X"F8"; wait for 2 us;
p_reference <= X"38"; wait for 126 us;
end if;
p_reference <= (others => 'U');
wait;
end process;
n_ref <= p_reference(7);
v_ref <= p_reference(6);
z_ref <= p_reference(1);
c_ref <= p_reference(0);
test: process
variable L : line;
begin
for i in 0 to 3 loop
-- data_a <= conv_std_logic_vector((i mod 10) + (i/10)*16,8);
data_a <= conv_std_logic_vector(i,8);
for j in 0 to 255 loop
data_b <= conv_std_logic_vector(j,8);
c_in <= operation(2);
wait for 500 ns;
-- check flags
assert c_out = c_ref or c_ref = 'U' report "Error in C-flag!" severity error;
assert z_out = z_ref or z_ref = 'U' report "Error in Z-flag!" severity error;
assert v_out = v_ref or v_ref = 'U' report "Error in V-flag!" severity error;
assert n_out = n_ref or n_ref = 'U' report "Error in N-flag!" severity error;
wait for 500 ns;
-- write(L, VecToHex(data_out, 2));
-- write(L, VecToHex(p_out, 2));
-- write(L, ',');
-- c_in <= '1';
-- wait for 1 us;
end loop;
-- writeline(output, L);
end loop;
wait;
end process;
mut: entity work.alu
generic map (true)
port map (
operation => operation,
enable => '1',
n_in => 'U',
v_in => 'U',
z_in => 'U',
c_in => c_in,
d_in => '1',
data_a => data_a,
data_b => data_b,
n_out => n_out,
v_out => v_out,
z_out => z_out,
c_out => c_out,
data_out => data_out );
end tb; |
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