content stringlengths 1 1.04M ⌀ |
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** CORE ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** CORE ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** CORE ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** CORE ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** CORE ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** CORE ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** CORE ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** CORE ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** CORE ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** CORE ... |
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementatio... |
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementatio... |
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementatio... |
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementatio... |
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementatio... |
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementatio... |
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementatio... |
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementatio... |
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementatio... |
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementatio... |
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementatio... |
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementatio... |
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementatio... |
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY parity8 IS
PORT(
byte : IN std_logic_vector(7 downto 0);
paritybit : OUT std_logic
);
END parity8;
ARCHITECTURE behavior OF parity8 IS
BEGIN
paritybit <= byte(7) XOR byte(6) XOR byte(5) XOR byte(4) XOR byte(3) XOR byte(2) XOR byte(1) XOR... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:52:50 10/26/2009
-- Design Name:
-- Module Name: OZ-3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:52:50 10/26/2009
-- Design Name:
-- Module Name: OZ-3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
... |
entity func7 is
end entity;
architecture test of func7 is
type int_vector is array (natural range <>) of integer;
subtype int_vec_3 is int_vector(0 to 2);
function get_ints(a, b, c : integer) return int_vec_3 is
begin
return int_vec_3'(a, b, c);
end function;
begin
process is
... |
entity func7 is
end entity;
architecture test of func7 is
type int_vector is array (natural range <>) of integer;
subtype int_vec_3 is int_vector(0 to 2);
function get_ints(a, b, c : integer) return int_vec_3 is
begin
return int_vec_3'(a, b, c);
end function;
begin
process is
... |
entity func7 is
end entity;
architecture test of func7 is
type int_vector is array (natural range <>) of integer;
subtype int_vec_3 is int_vector(0 to 2);
function get_ints(a, b, c : integer) return int_vec_3 is
begin
return int_vec_3'(a, b, c);
end function;
begin
process is
... |
entity func7 is
end entity;
architecture test of func7 is
type int_vector is array (natural range <>) of integer;
subtype int_vec_3 is int_vector(0 to 2);
function get_ints(a, b, c : integer) return int_vec_3 is
begin
return int_vec_3'(a, b, c);
end function;
begin
process is
... |
entity func7 is
end entity;
architecture test of func7 is
type int_vector is array (natural range <>) of integer;
subtype int_vec_3 is int_vector(0 to 2);
function get_ints(a, b, c : integer) return int_vec_3 is
begin
return int_vec_3'(a, b, c);
end function;
begin
process is
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.qr_pack.all;
entity qr_wrapper_wrapper_stimuli is
port (
clk : in std_logic;
rst_n : in std_logic;
reduced_matrix : out std_logic; --! Divides by two the order of matrices involved
sta... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.qr_pack.all;
entity qr_wrapper_wrapper_stimuli is
port (
clk : in std_logic;
rst_n : in std_logic;
reduced_matrix : out std_logic; --! Divides by two the order of matrices involved
sta... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.qr_pack.all;
entity qr_wrapper_wrapper_stimuli is
port (
clk : in std_logic;
rst_n : in std_logic;
reduced_matrix : out std_logic; --! Divides by two the order of matrices involved
sta... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.qr_pack.all;
entity qr_wrapper_wrapper_stimuli is
port (
clk : in std_logic;
rst_n : in std_logic;
reduced_matrix : out std_logic; --! Divides by two the order of matrices involved
sta... |
library ieee;
use ieee.std_logic_1164.all;
entity block02 is
port (q : out std_logic;
d : std_logic;
clk : std_logic);
end block02;
architecture behav of block02 is
begin
b1 : block
signal s : std_logic;
begin
process (clk) is
begin
if rising_edge (clk) then
s <= d;
... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_254 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_254;
architecture augh of add_254 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_254 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_254;
architecture augh of add_254 is
signal carry_inA : std_l... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity sand_nov is
port(
clock: in std_logic;
input: in std_logic_vector(10 downto 0);
output: out std_logic_vector(8 downto 0)
);
end sand_nov;
architecture behaviour of sand_nov is
constant st0: std_logic_vector(4 downto 0) := ... |
---------------------------------------------------------------
-- Title : Package for simulation terminal
-- Project : -
---------------------------------------------------------------
-- File : terminal_pkg.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organizati... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ----------------------------... |
-- EMACS settings: -*- tab-width: 4; indent-tabs-mode: t -*-
-- vim: tabstop=4:shiftwidth=4:noexpandtab
-- kate: tab-width 4; replace-tabs off; indent-width 4;
--
-- =============================================================================
-- Authors: Paul Genssler
--
-- Description:
-- ----------------------------... |
library verilog;
use verilog.vl_types.all;
entity SeqEightBitAdder_vlg_check_tst is
port(
LEDR : in vl_logic_vector(8 downto 0);
sampler_rx : in vl_logic
);
end SeqEightBitAdder_vlg_check_tst;
|
--------------------------------------------------------------------------------
-- Title : VME Bustimer
-- Project : A15
--------------------------------------------------------------------------------
-- File : vme_bustimer.vhd
-- Author : michael.miehling@men.de
-- Organization : MEN M... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
component pr_region_alternate_clock_in is
port (
in_clk : in std_logic := 'X'; -- clk
out_clk : out std_logic -- clk
);
end component pr_region_alternate_clock_in;
u0 : component pr_region_alternate_clock_in
port map (
in_clk => CONNECTED_TO_in_clk, -- in_clk.clk
out_clk => CONNECTED_... |
---------------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------------
-- File : switch_fab_1.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : MEN Mikroelekt... |
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: madd - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
-------------------------------------------------------... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arbiter is
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arbiter is
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic; -- From LBDR modules
... |
package b is
generic ( X: natural := 4);
type m is array (natural range <>) of bit_vector (X - 1 downto 0);
end package;
|
package b is
generic ( X: natural := 4);
type m is array (natural range <>) of bit_vector (X - 1 downto 0);
end package;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MAGIC_tb is
end;
architecture testing of MAGIC_tb is
component MAGIC
PORT (
ADDRESS_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADD... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MAGIC_tb is
end;
architecture testing of MAGIC_tb is
component MAGIC
PORT (
ADDRESS_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_B : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADDRESS_C : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ADD... |
-------------------------------------------------------------------------------------------------------------
-- Sign Extender
-- This block performs the sign extension in for the jump address(instruction 25-0)
----------------------------------------------------------------------------------------------------------... |
-------------------------------------------------------------------------------------------------------------
-- Sign Extender
-- This block performs the sign extension in for the jump address(instruction 25-0)
----------------------------------------------------------------------------------------------------------... |
-------------------------------------------------------------------------------
-- Bitmap VGA display with 640x480 pixel resolution
-------------------------------------------------------------------------------
-- V 1.1.1 (2015/07/28)
-- Yannick Bornat (yannick.bornat@enseirb-matmeca.fr)
--
-- For more information on ... |
-------------------------------------------------------------------------------
-- Bitmap VGA display with 640x480 pixel resolution
-------------------------------------------------------------------------------
-- V 1.1.1 (2015/07/28)
-- Yannick Bornat (yannick.bornat@enseirb-matmeca.fr)
--
-- For more information on ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:18:02 03/28/2016
-- Design Name:
-- Module Name: ALU_Toplevel - Dataflow
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:18:02 03/28/2016
-- Design Name:
-- Module Name: ALU_Toplevel - Dataflow
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:18:02 03/28/2016
-- Design Name:
-- Module Name: ALU_Toplevel - Dataflow
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:18:02 03/28/2016
-- Design Name:
-- Module Name: ALU_Toplevel - Dataflow
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:18:02 03/28/2016
-- Design Name:
-- Module Name: ALU_Toplevel - Dataflow
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... |
entity tb_var01 is
end tb_var01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_var01 is
signal clk : std_logic;
signal mask : std_logic_vector (3 downto 0);
signal val : std_logic_vector (31 downto 0);
signal res : std_logic_vector (31 downto 0);
begin
dut: entity work.var01
port m... |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.13:54:59)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mesaia_alap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/22/2014
--! Module Name: EPROC_IN4_DEC8b10b
--! Project Name: FELIX
----------------------------------------------------------------------------------
... |
library ieee;
use ieee.std_logic_1164.all;
entity circuito_transmissao is
port(liga : in std_logic;
enviar : in std_logic;
reset : in std_logic;
clock : in std_logic;
CTS : in std_logic;
dado_serial : in std_logic;
envioOk : out std_logic;
DTR ... |
-- Automatically generated: write_netlist -chip -vhdl -architecture chip-chip_top-a.vhd
architecture chip_top of chip is
component ICP
port (
PAD : in std_logic;
Y : out std_logic
);
end component;
component BU16P
port (
A : in std_logic;
PAD : out std_logic
);
end com... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--741
entity counter741 is
port(clk :in bit;
Qout:out unsigned(3 downto 0));
end entity counter741;
architecture neibu of counter741 is
signal Q:unsigned(3 downto 0);
begin
Qout<=Q;
process(clk)
begin
end process;
end architecture neibu; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:12:12 10/24/2014
-- Design Name:
-- Module Name: SevenSeg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revisi... |
library ieee;
use ieee.std_logic_1164.all;
entity BitStringValuesEnt is
generic(
C_1 : std_logic := '1';
C_0 : std_logic := '0';
C_1b1 : std_logic_vector := "1";
C_1b0 : std_logic_vector := "0";
C_16b1 : std_logic_vector := X"0000FFFF";
... |
----------------------------------------------------------------------
---- ----
---- Pipelined Aes IP Core ----
---- ----
---- This file is part of the Pipeli... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
flit_type: i... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
flit_type: i... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
flit_type: i... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
flit_type: i... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
flit_type: i... |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Rxy_Reconf_pseudo_checkers is
port ( ReConf_FF_out: in std_logic;
flit_type: i... |
---------------------------------------------------------
-- Routing Mechanism
---------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.PhoenixPackage.all;
use work.TablePackage.all;
entity routingMechanism is
generic(address : regmetadefl... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 14 11:02:39 2017
-- Host : PC4719 running 64-bit Service Pack 1... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 11-04-2016
-- Module Name: main.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all... |
-- NEED RESULT: ARCH00478: Choices in an element association of an aggregate may contain several or no choices passed
-- NEED RESULT: ARCH00478: Element simple name properly disambiguated from simple expressions in aggregate element associations passed
-----------------------------------------------------------------... |
---------------------------------------------------------------
-- Title : VME bus slave simmodel
-- Project : A15
---------------------------------------------------------------
-- File : vme_sim_slave.vhd
-- Author : Michael Miehling
-- Email : miehling@men.de
-- Organization : ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.file_io_pkg.all;
library std;
use std.textio.all;
entity tb_alu is
end tb_alu;
architecture tb of tb_alu is
signal c_in : std_logic := '0';
signal data_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.file_io_pkg.all;
library std;
use std.textio.all;
entity tb_alu is
end tb_alu;
architecture tb of tb_alu is
signal c_in : std_logic := '0';
signal data_... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.file_io_pkg.all;
library std;
use std.textio.all;
entity tb_alu is
end tb_alu;
architecture tb of tb_alu is
signal c_in : std_logic := '0';
signal data_... |
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