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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.file_io_pkg.all;
library std;
use std.textio.all;
entity tb_alu is
end tb_alu;
architecture tb of tb_alu is
signal c_in : std_logic := '0';
signal data_a : std_logic_vector(7 downto 0) := X"00";
signal data_b : std_logic_vector(7 downto 0) := X"00";
signal n_out : std_logic;
signal v_out : std_logic;
signal z_out : std_logic;
signal c_out : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal p_out : std_logic_vector(7 downto 0);
signal operation : std_logic_vector(2 downto 0) := "011"; -- ADC
signal p_reference : std_logic_vector(7 downto 0);
signal n_ref : std_logic;
signal v_ref : std_logic;
signal z_ref : std_logic;
signal c_ref : std_logic;
begin
p_out <= n_out & v_out & "111" & '0' & z_out & c_out;
ref_sum: process -- taken from real 6510
begin
wait for 1 ps;
if operation(2)='0' then -- adc
p_reference <= X"3A"; wait for 1 us;
p_reference <= X"38"; wait for 121 us;
p_reference <= X"F8"; wait for 6 us;
p_reference <= X"B8"; wait for 26 us;
p_reference <= X"B9"; wait for 96 us;
p_reference <= X"39"; wait for 6 us;
-- 01
p_reference <= X"38"; wait for 121 us;
p_reference <= X"F8"; wait for 7 us;
p_reference <= X"B8"; wait for 25 us;
p_reference <= X"B9"; wait for 96 us;
p_reference <= X"39"; wait for 6 us;
p_reference <= X"3B"; wait for 1 us;
else
p_reference <= X"3B"; wait for 1 us;
p_reference <= X"B8"; wait for 127 us;
p_reference <= X"F8"; wait for 1 us;
p_reference <= X"38"; wait for 127 us;
-- 01
p_reference <= X"39"; wait for 1 us;
p_reference <= X"3B"; wait for 1 us;
p_reference <= X"B8"; wait for 126 us;
p_reference <= X"F8"; wait for 2 us;
p_reference <= X"38"; wait for 126 us;
end if;
p_reference <= (others => 'U');
wait;
end process;
n_ref <= p_reference(7);
v_ref <= p_reference(6);
z_ref <= p_reference(1);
c_ref <= p_reference(0);
test: process
variable L : line;
begin
for i in 0 to 3 loop
-- data_a <= conv_std_logic_vector((i mod 10) + (i/10)*16,8);
data_a <= conv_std_logic_vector(i,8);
for j in 0 to 255 loop
data_b <= conv_std_logic_vector(j,8);
c_in <= operation(2);
wait for 500 ns;
-- check flags
assert c_out = c_ref or c_ref = 'U' report "Error in C-flag!" severity error;
assert z_out = z_ref or z_ref = 'U' report "Error in Z-flag!" severity error;
assert v_out = v_ref or v_ref = 'U' report "Error in V-flag!" severity error;
assert n_out = n_ref or n_ref = 'U' report "Error in N-flag!" severity error;
wait for 500 ns;
-- write(L, VecToHex(data_out, 2));
-- write(L, VecToHex(p_out, 2));
-- write(L, ',');
-- c_in <= '1';
-- wait for 1 us;
end loop;
-- writeline(output, L);
end loop;
wait;
end process;
mut: entity work.alu
generic map (true)
port map (
operation => operation,
enable => '1',
n_in => 'U',
v_in => 'U',
z_in => 'U',
c_in => c_in,
d_in => '1',
data_a => data_a,
data_b => data_b,
n_out => n_out,
v_out => v_out,
z_out => z_out,
c_out => c_out,
data_out => data_out );
end tb; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.file_io_pkg.all;
library std;
use std.textio.all;
entity tb_alu is
end tb_alu;
architecture tb of tb_alu is
signal c_in : std_logic := '0';
signal data_a : std_logic_vector(7 downto 0) := X"00";
signal data_b : std_logic_vector(7 downto 0) := X"00";
signal n_out : std_logic;
signal v_out : std_logic;
signal z_out : std_logic;
signal c_out : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal p_out : std_logic_vector(7 downto 0);
signal operation : std_logic_vector(2 downto 0) := "011"; -- ADC
signal p_reference : std_logic_vector(7 downto 0);
signal n_ref : std_logic;
signal v_ref : std_logic;
signal z_ref : std_logic;
signal c_ref : std_logic;
begin
p_out <= n_out & v_out & "111" & '0' & z_out & c_out;
ref_sum: process -- taken from real 6510
begin
wait for 1 ps;
if operation(2)='0' then -- adc
p_reference <= X"3A"; wait for 1 us;
p_reference <= X"38"; wait for 121 us;
p_reference <= X"F8"; wait for 6 us;
p_reference <= X"B8"; wait for 26 us;
p_reference <= X"B9"; wait for 96 us;
p_reference <= X"39"; wait for 6 us;
-- 01
p_reference <= X"38"; wait for 121 us;
p_reference <= X"F8"; wait for 7 us;
p_reference <= X"B8"; wait for 25 us;
p_reference <= X"B9"; wait for 96 us;
p_reference <= X"39"; wait for 6 us;
p_reference <= X"3B"; wait for 1 us;
else
p_reference <= X"3B"; wait for 1 us;
p_reference <= X"B8"; wait for 127 us;
p_reference <= X"F8"; wait for 1 us;
p_reference <= X"38"; wait for 127 us;
-- 01
p_reference <= X"39"; wait for 1 us;
p_reference <= X"3B"; wait for 1 us;
p_reference <= X"B8"; wait for 126 us;
p_reference <= X"F8"; wait for 2 us;
p_reference <= X"38"; wait for 126 us;
end if;
p_reference <= (others => 'U');
wait;
end process;
n_ref <= p_reference(7);
v_ref <= p_reference(6);
z_ref <= p_reference(1);
c_ref <= p_reference(0);
test: process
variable L : line;
begin
for i in 0 to 3 loop
-- data_a <= conv_std_logic_vector((i mod 10) + (i/10)*16,8);
data_a <= conv_std_logic_vector(i,8);
for j in 0 to 255 loop
data_b <= conv_std_logic_vector(j,8);
c_in <= operation(2);
wait for 500 ns;
-- check flags
assert c_out = c_ref or c_ref = 'U' report "Error in C-flag!" severity error;
assert z_out = z_ref or z_ref = 'U' report "Error in Z-flag!" severity error;
assert v_out = v_ref or v_ref = 'U' report "Error in V-flag!" severity error;
assert n_out = n_ref or n_ref = 'U' report "Error in N-flag!" severity error;
wait for 500 ns;
-- write(L, VecToHex(data_out, 2));
-- write(L, VecToHex(p_out, 2));
-- write(L, ',');
-- c_in <= '1';
-- wait for 1 us;
end loop;
-- writeline(output, L);
end loop;
wait;
end process;
mut: entity work.alu
generic map (true)
port map (
operation => operation,
enable => '1',
n_in => 'U',
v_in => 'U',
z_in => 'U',
c_in => c_in,
d_in => '1',
data_a => data_a,
data_b => data_b,
n_out => n_out,
v_out => v_out,
z_out => z_out,
c_out => c_out,
data_out => data_out );
end tb; |
entity ent4 is
end entity;
architecture a of ent4 is
begin
main : process
begin
-- wait for 0 ns; -- Comment and it exits with code 1
std.env.stop(0);
wait;
end process;
end architecture;
|
entity ent4 is
end entity;
architecture a of ent4 is
begin
main : process
begin
-- wait for 0 ns; -- Comment and it exits with code 1
std.env.stop(0);
wait;
end process;
end architecture;
|
entity ent4 is
end entity;
architecture a of ent4 is
begin
main : process
begin
-- wait for 0 ns; -- Comment and it exits with code 1
std.env.stop(0);
wait;
end process;
end architecture;
|
-- NEED RESULT: ARCH00403.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00403: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00403: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00403: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00403: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00403
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00403(ARCH00403)
-- ENT00403_Test_Bench(ARCH00403_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00403 is
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
--
end ENT00403 ;
--
--
architecture ARCH00403 of ENT00403 is
subtype chk_time_type is Time ;
signal s_st_arr1_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_arr1_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_arr1_vector_select : select_type := 1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_arr1_vector_cnt is
when 0
=> null ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <=
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_2(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_1(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00403.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr1_vector_select <= transport 2 ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <=
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns ,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ,
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 30 ns ,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_2(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr1_vector_select <= transport 3 ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <=
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_1(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00403" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr1_vector_select <= transport 4 ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <=
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_1(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00403" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr1_vector_select <= transport 5 ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <=
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns ,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ,
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 30 ns ,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_2(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00403" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr1_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr1_vector(highb)(lowb to highb-1) <=
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_1(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_1(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00403" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00403" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr1_vector_savt <= transport Std.Standard.Now ;
chk_st_arr1_vector <= transport s_st_arr1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr1_vector_cnt <= transport s_st_arr1_vector_cnt + 1 ;
wait until (not s_st_arr1_vector(highb)(lowb to highb-1)'Quiet) and
(s_st_arr1_vector_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_arr1_vector_select select
s_st_arr1_vector(highb)(lowb to highb-1) <=
c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns
when 1,
--
c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns ,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ,
c_st_arr1_vector_2(highb)(lowb to highb-1) after 30 ns ,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 40 ns
when 2,
--
c_st_arr1_vector_1(highb)(lowb to highb-1) after 5 ns
when 3,
--
c_st_arr1_vector_1(highb)(lowb to highb-1) after 100 ns
when 4,
--
c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns ,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ,
c_st_arr1_vector_2(highb)(lowb to highb-1) after 30 ns ,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr1_vector_1(highb)(lowb to highb-1) after 40 ns when 6 ;
--
end ARCH00403 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00403_Test_Bench is
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
--
end ENT00403_Test_Bench ;
--
--
architecture ARCH00403_Test_Bench of ENT00403_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_arr1_vector : inout st_arr1_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00403 ( ARCH00403 ) ;
begin
CIS1 : UUT
port map (
s_st_arr1_vector
)
;
end block L1 ;
end ARCH00403_Test_Bench ;
|
component jaxa is
port (
autostart_external_connection_export : out std_logic; -- export
clk_clk : in std_logic := 'X'; -- clk
controlflagsin_external_connection_export : out std_logic_vector(1 downto 0); -- export
controlflagsout_external_connection_export : in std_logic_vector(1 downto 0) := (others => 'X'); -- export
creditcount_external_connection_export : in std_logic_vector(5 downto 0) := (others => 'X'); -- export
errorstatus_external_connection_export : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
linkdisable_external_connection_export : out std_logic; -- export
linkstart_external_connection_export : out std_logic; -- export
linkstatus_external_connection_export : in std_logic_vector(15 downto 0) := (others => 'X'); -- export
memory_mem_a : out std_logic_vector(12 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic := 'X'; -- mem_dqs
memory_mem_dqs_n : inout std_logic := 'X'; -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic; -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
outstandingcount_external_connection_export : in std_logic_vector(5 downto 0) := (others => 'X'); -- export
pll_0_outclk0_clk : out std_logic; -- clk
receiveactivity_external_connection_export : in std_logic := 'X'; -- export
receiveclock_external_connection_export : out std_logic; -- export
receivefifodatacount_external_connection_export : in std_logic := 'X'; -- export
receivefifodataout_external_connection_export : in std_logic_vector(8 downto 0) := (others => 'X'); -- export
receivefifoempty_external_connection_export : in std_logic := 'X'; -- export
receivefifofull_external_connection_export : in std_logic := 'X'; -- export
receivefiforeadenable_external_connection_export : out std_logic; -- export
spacewiredatain_external_connection_export : out std_logic; -- export
spacewiredataout_external_connection_export : in std_logic := 'X'; -- export
spacewirestrobein_external_connection_export : out std_logic; -- export
spacewirestrobeout_external_connection_export : in std_logic := 'X'; -- export
statisticalinformation_0_external_connection_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
statisticalinformation_1_external_connection_export : out std_logic_vector(7 downto 0); -- export
statisticalinformationclear_external_connection_export : out std_logic; -- export
tickin_external_connection_export : out std_logic; -- export
tickout_external_connection_export : in std_logic := 'X'; -- export
timein_external_connection_export : out std_logic_vector(5 downto 0); -- export
timeout_external_connection_export : in std_logic_vector(5 downto 0) := (others => 'X'); -- export
transmitactivity_external_connection_export : in std_logic := 'X'; -- export
transmitclock_external_connection_export : out std_logic; -- export
transmitclockdividevalue_external_connection_export : out std_logic_vector(5 downto 0); -- export
transmitfifodatacount_external_connection_export : in std_logic_vector(5 downto 0) := (others => 'X'); -- export
transmitfifodatain_external_connection_export : out std_logic_vector(8 downto 0); -- export
transmitfifofull_external_connection_export : in std_logic := 'X'; -- export
transmitfifowriteenable_external_connection_export : out std_logic -- export
);
end component jaxa;
u0 : component jaxa
port map (
autostart_external_connection_export => CONNECTED_TO_autostart_external_connection_export, -- autostart_external_connection.export
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
controlflagsin_external_connection_export => CONNECTED_TO_controlflagsin_external_connection_export, -- controlflagsin_external_connection.export
controlflagsout_external_connection_export => CONNECTED_TO_controlflagsout_external_connection_export, -- controlflagsout_external_connection.export
creditcount_external_connection_export => CONNECTED_TO_creditcount_external_connection_export, -- creditcount_external_connection.export
errorstatus_external_connection_export => CONNECTED_TO_errorstatus_external_connection_export, -- errorstatus_external_connection.export
linkdisable_external_connection_export => CONNECTED_TO_linkdisable_external_connection_export, -- linkdisable_external_connection.export
linkstart_external_connection_export => CONNECTED_TO_linkstart_external_connection_export, -- linkstart_external_connection.export
linkstatus_external_connection_export => CONNECTED_TO_linkstatus_external_connection_export, -- linkstatus_external_connection.export
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
outstandingcount_external_connection_export => CONNECTED_TO_outstandingcount_external_connection_export, -- outstandingcount_external_connection.export
pll_0_outclk0_clk => CONNECTED_TO_pll_0_outclk0_clk, -- pll_0_outclk0.clk
receiveactivity_external_connection_export => CONNECTED_TO_receiveactivity_external_connection_export, -- receiveactivity_external_connection.export
receiveclock_external_connection_export => CONNECTED_TO_receiveclock_external_connection_export, -- receiveclock_external_connection.export
receivefifodatacount_external_connection_export => CONNECTED_TO_receivefifodatacount_external_connection_export, -- receivefifodatacount_external_connection.export
receivefifodataout_external_connection_export => CONNECTED_TO_receivefifodataout_external_connection_export, -- receivefifodataout_external_connection.export
receivefifoempty_external_connection_export => CONNECTED_TO_receivefifoempty_external_connection_export, -- receivefifoempty_external_connection.export
receivefifofull_external_connection_export => CONNECTED_TO_receivefifofull_external_connection_export, -- receivefifofull_external_connection.export
receivefiforeadenable_external_connection_export => CONNECTED_TO_receivefiforeadenable_external_connection_export, -- receivefiforeadenable_external_connection.export
spacewiredatain_external_connection_export => CONNECTED_TO_spacewiredatain_external_connection_export, -- spacewiredatain_external_connection.export
spacewiredataout_external_connection_export => CONNECTED_TO_spacewiredataout_external_connection_export, -- spacewiredataout_external_connection.export
spacewirestrobein_external_connection_export => CONNECTED_TO_spacewirestrobein_external_connection_export, -- spacewirestrobein_external_connection.export
spacewirestrobeout_external_connection_export => CONNECTED_TO_spacewirestrobeout_external_connection_export, -- spacewirestrobeout_external_connection.export
statisticalinformation_0_external_connection_export => CONNECTED_TO_statisticalinformation_0_external_connection_export, -- statisticalinformation_0_external_connection.export
statisticalinformation_1_external_connection_export => CONNECTED_TO_statisticalinformation_1_external_connection_export, -- statisticalinformation_1_external_connection.export
statisticalinformationclear_external_connection_export => CONNECTED_TO_statisticalinformationclear_external_connection_export, -- statisticalinformationclear_external_connection.export
tickin_external_connection_export => CONNECTED_TO_tickin_external_connection_export, -- tickin_external_connection.export
tickout_external_connection_export => CONNECTED_TO_tickout_external_connection_export, -- tickout_external_connection.export
timein_external_connection_export => CONNECTED_TO_timein_external_connection_export, -- timein_external_connection.export
timeout_external_connection_export => CONNECTED_TO_timeout_external_connection_export, -- timeout_external_connection.export
transmitactivity_external_connection_export => CONNECTED_TO_transmitactivity_external_connection_export, -- transmitactivity_external_connection.export
transmitclock_external_connection_export => CONNECTED_TO_transmitclock_external_connection_export, -- transmitclock_external_connection.export
transmitclockdividevalue_external_connection_export => CONNECTED_TO_transmitclockdividevalue_external_connection_export, -- transmitclockdividevalue_external_connection.export
transmitfifodatacount_external_connection_export => CONNECTED_TO_transmitfifodatacount_external_connection_export, -- transmitfifodatacount_external_connection.export
transmitfifodatain_external_connection_export => CONNECTED_TO_transmitfifodatain_external_connection_export, -- transmitfifodatain_external_connection.export
transmitfifofull_external_connection_export => CONNECTED_TO_transmitfifofull_external_connection_export, -- transmitfifofull_external_connection.export
transmitfifowriteenable_external_connection_export => CONNECTED_TO_transmitfifowriteenable_external_connection_export -- transmitfifowriteenable_external_connection.export
);
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00519
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 10.3 (1)
-- 10.3 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00519_1(ARCH00519_1)
-- ENT00519(ARCH00519)
-- ENT00519_Test_Bench(ARCH00519_Test_Bench)
--
-- REVISION HISTORY:
--
-- 11-AUG-1987 - initial revision
-- 28-NOV-1989 - (ESL) change files to be of mode out
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00519_1 is
generic ( G : boolean := false ) ;
port ( P : boolean := false ) ;
end ENT00519_1 ;
architecture ARCH00519_1 of ENT00519_1 is
begin
process
begin
test_report ( "ARCH00519" ,
"Declarative region direct visibility test"&
"For Component declaration/instantiation" ,
P and G ) ;
wait ;
end process ;
end ARCH00519_1 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00519 is
generic ( EntGeneric : boolean := false ) ;
port ( EntPort : boolean := false ) ;
function To_Boolean ( p : bit ) return boolean is
begin
case p is
when '0' => return false ;
when '1' => return true ;
end case ;
end To_Boolean ;
subtype EntSubtype is Bit_Vector (1 to 3) ;
type EntType is record
f1 : boolean ;
f2 : EntSubtype ;
end record ;
constant EntCons : EntType := (f1 => EntGeneric,
f2 => EntSubtype'(others => '1')) ;
signal EntSig : EntSubtype := ('0', EntCons.f2(2), '0') ;
alias EntAlias : bit is EntSig(2) ;
type EntFileType is file of boolean ;
file EntFile : EntFileType is out "ct00519.dat";
attribute EntAttr : boolean ;
attribute EntAttr of EntLabel : label is EntCons.f1 ;
procedure EntProc2 (parm1 : boolean) ;
procedure EntProc (parm1 : boolean) is
subtype SubpSubtype is EntSubtype ;
type SubpType is record
f1 : boolean ;
f2 : SubpSubtype ;
end record ;
constant SubpCons : EntType := (f1 => EntGeneric,
f2 => EntCons.f2 ) ;
variable SubpVar : SubpSubtype := SubpCons.f2;
alias SubpAlias : bit is SubpVar(2) ;
file SubpFile : EntFileType is out "ct00519.dat";
attribute EntAttr of SubpLabel : label is EntCons.f1 ;
variable correct : boolean ;
begin
correct := EntGeneric and EntPort and
EntCons.f1 and (EntCons.f2 = EntSubtype'(others => '1')) and
(EntSig(2) = EntAlias) and
EntLabel'EntAttr and
(SubpCons = EntCons) and
(SubpVar(2) = SubpAlias) and
SubpLabel'Entattr ;
test_report ( "ENT00519.EntProc" ,
"Declarative region direct visibility test" ,
correct ) ;
if parm1 then
EntProc (Not parm1) ;
end if ;
SubpLabel : while True loop exit; end loop;
end EntProc ;
begin
EntLabel : process begin wait; end process;
end ENT00519 ;
architecture ARCH00519 of ENT00519 is
component ArchComp
generic ( G : boolean ) ;
port ( P : boolean ) ;
end component ;
for CIS1 : ArchComp use entity WORK.ENT00519_1 ( ARCH00519_1 );
subtype ArchSubtype is EntSubtype ;
type ArchType is record
f1 : boolean ;
f2 : ArchSubtype ;
end record ;
constant ArchCons : ArchType := (f1 => EntGeneric,
f2 => EntCons.f2) ;
signal ArchSig : ArchSubtype := ('0', ArchCons.f2(2), '0') ;
alias ArchAlias : bit is ArchSig(2) ;
file ArchFile : EntFileType is out "ct00519.dat";
constant ArchLabel : integer := 1 ;
attribute EntAttr of ArchLabel : constant is ArchCons.f1 ;
procedure EntProc2 (parm1 : boolean) is
subtype SubpSubtype is EntSubtype ;
type SubpType is record
f1 : boolean ;
f2 : SubpSubtype ;
end record ;
constant SubpCons : EntType := (f1 => EntGeneric,
f2 => EntCons.f2 ) ;
variable SubpVar : SubpSubtype := SubpCons.f2;
alias SubpAlias : bit is SubpVar(2) ;
file SubpFile : EntFileType is out "ct00519.dat";
constant SubpLabel : integer := 1 ;
attribute EntAttr of SubpLabel : Constant is EntCons.f1 ;
variable correct : boolean ;
begin
correct := EntGeneric and EntPort and
EntCons.f1 and (EntCons.f2 = EntSubtype'(others => '1')) and
(EntSig(2) = EntAlias) and
EntLabel'EntAttr and
ArchCons.f1 and (ArchCons.f2 = ArchSubtype'(others => '1')) and
(ArchSig(2) = ArchAlias) and
ArchLabel'EntAttr and
(SubpCons = EntCons) and
(SubpVar(2) = SubpAlias) and
SubpLabel'EntAttr ;
test_report ( "ENT00519.EntProc2" ,
"Declarative region direct visibility test" ,
correct ) ;
if parm1 then
EntProc2 (Not parm1) ;
end if ;
end EntProc2 ;
begin
CIS1 : ArchComp
generic map ( G => True )
port map ( P => To_Boolean (ArchAlias) ) ;
L1 :
block
component BlkComp
generic ( G : boolean ) ;
port ( P : boolean ) ;
end component ;
for CIS1 : ArchComp use entity WORK.ENT00519_1 ( ARCH00519_1 );
for CIS2 : BLKComp use entity WORK.ENT00519_1 ( ARCH00519_1 );
subtype BlkSubtype is EntSubtype ;
type BlkType is record
f1 : boolean ;
f2 : BlkSubtype ;
end record ;
constant BlkCons : BlkType := (f1 => EntGeneric,
f2 => EntCons.f2) ;
signal BlkSig : BlkSubtype := ('0', BlkCons.f2(2), '1');
alias BlkAlias : bit is BlkSig(2) ;
file BlkFile : EntFileType is out "ct00519.dat";
constant BlkLabel : integer := 1 ;
attribute EntAttr of BlkLabel : constant is BlkCons.f1 ;
procedure BlkProc (parm1 : boolean) is
subtype SubpSubtype is EntSubtype ;
type SubpType is record
f1 : boolean ;
f2 : SubpSubtype ;
end record ;
constant SubpCons : EntType := (f1 => EntGeneric,
f2 => EntCons.f2 ) ;
variable SubpVar : SubpSubtype := SubpCons.f2;
alias SubpAlias : bit is SubpVar(2) ;
file SubpFile : EntFileType is out "ct00519.dat";
constant SubpLabel : integer := 1 ;
attribute EntAttr of SubpLabel : Constant is EntCons.f1 ;
variable correct : boolean ;
begin
correct := EntGeneric and EntPort and
EntCons.f1 and (EntCons.f2 = EntSubtype'(others => '1')) and
(EntSig(2) = EntAlias) and
EntLabel'EntAttr and
ArchCons.f1 and (ArchCons.f2 = ArchSubtype'(others => '1'))
and (ArchSig(2) = ArchAlias) and
ArchLabel'EntAttr and
BlkCons.f1 and (BlkCons.f2 = BlkSubtype'(others => '1')) and
(BlkSig(2) = BlkAlias) and
BlkLabel'EntAttr and
(SubpCons = EntCons) and
(SubpVar(2) = SubpAlias) and
SubpLabel'EntAttr ;
test_report ( "ENT00519.BlkProc" ,
"Declarative region direct visibility test" ,
correct ) ;
if parm1 then
BlkProc (Not parm1) ;
end if ;
end BlkProc ;
begin
CIS1 : ArchComp
generic map ( G => True )
port map ( P => To_Boolean (ArchAlias) ) ;
CIS2 : BlkComp
generic map ( G => True )
port map ( P => To_Boolean (BlkAlias) ) ;
process
subtype PcsSubtype is EntSubtype ;
type PcsType is record
f1 : boolean ;
f2 : PcsSubtype ;
end record ;
constant PcsCons : EntType := (f1 => EntGeneric,
f2 => EntCons.f2 ) ;
variable PcsVar : PcsSubtype := PcsCons.f2 ;
alias PcsAlias : bit is PcsVar(2) ;
file PcsFile : EntFileType is out "ct00519.dat";
constant PcsLabel : integer := 1 ;
attribute EntAttr of PcsLabel : Constant is EntCons.f1 ;
variable correct : boolean ;
begin
EntProc (True) ;
EntProc2 (True) ;
BlkProc (True) ;
correct := EntGeneric and EntPort and
EntCons.f1 and (EntCons.f2 = EntSubtype'(others => '1')) and
(EntSig(2) = EntAlias) and
EntLabel'EntAttr and
ArchCons.f1 and (ArchCons.f2 = ArchSubtype'(others => '1'))
and (ArchSig(2) = ArchAlias) and
ArchLabel'EntAttr and
BlkCons.f1 and (BlkCons.f2 = BlkSubtype'(others => '1')) and
(BlkSig(2) = BlkAlias) and
BlkLabel'EntAttr and
(PcsCons = EntCons) and
(PcsVar(2) = PcsAlias) and
PcsLabel'EntAttr ;
test_report ( "ENT00519.Process" ,
"Declarative region direct visibility test" ,
correct ) ;
wait ;
end process ;
end block L1 ;
end ARCH00519 ;
entity ENT00519_Test_Bench is
end ENT00519_Test_Bench ;
architecture ARCH00519_Test_Bench of ENT00519_Test_Bench is
begin
L1:
block
component UUT
generic ( EntGeneric : boolean ) ;
port ( EntPort : boolean ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00519 ( ARCH00519 ) ;
signal Dummy : boolean := True ;
begin
CIS1 : UUT
generic map ( True )
port map ( Dummy ) ;
end block L1 ;
end ARCH00519_Test_Bench ;
|
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) DPR for Xilinx
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-11-17 V0.01 zelenkaj First version
-- 2011-12-06 V0.02 zelenkaj Uses openMAC DPR implementation
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY pdi_dpr IS
GENERIC
(
NUM_WORDS : INTEGER := 1024;
LOG2_NUM_WORDS : INTEGER := 10
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END pdi_dpr;
architecture struct of pdi_dpr is
constant cActivated : std_logic := '1';
begin
abuseMacDpr : entity work.dc_dpr_be
generic map (
gDoInit => true,
WIDTH => data_a'length,
SIZE => NUM_WORDS,
ADDRWIDTH => LOG2_NUM_WORDS
)
port map (
clkA => clock_a, clkB => clock_b,
enA => cActivated, enB => cActivated,
addrA => address_a, addrB => address_b,
diA => data_a, diB => data_b,
doA => q_a, doB => q_b,
weA => wren_a, weB => wren_b,
beA => byteena_a, beB => byteena_b
);
end architecture struct;
|
------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) DPR for Xilinx
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-11-17 V0.01 zelenkaj First version
-- 2011-12-06 V0.02 zelenkaj Uses openMAC DPR implementation
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY pdi_dpr IS
GENERIC
(
NUM_WORDS : INTEGER := 1024;
LOG2_NUM_WORDS : INTEGER := 10
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END pdi_dpr;
architecture struct of pdi_dpr is
constant cActivated : std_logic := '1';
begin
abuseMacDpr : entity work.dc_dpr_be
generic map (
gDoInit => true,
WIDTH => data_a'length,
SIZE => NUM_WORDS,
ADDRWIDTH => LOG2_NUM_WORDS
)
port map (
clkA => clock_a, clkB => clock_b,
enA => cActivated, enB => cActivated,
addrA => address_a, addrB => address_b,
diA => data_a, diB => data_b,
doA => q_a, doB => q_b,
weA => wren_a, weB => wren_b,
beA => byteena_a, beB => byteena_b
);
end architecture struct;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION LOG(LN) - TOP LEVEL ***
--*** ***
--*** FP_LOG.VHD ***
--*** ***
--*** Function: IEEE754 FP LOG() ***
--*** ***
--*** 21/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 21 ***
--***************************************************
ENTITY fp_log IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_log;
ARCHITECTURE rtl OF fp_log IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 19;
signal signinff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signnode : STD_LOGIC;
signal mantissanode : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal zeronode : STD_LOGIC;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
signal infinityinff : STD_LOGIC;
signal infinityff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_ln_core
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
ccsgn : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component fp_lnrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
BEGIN
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
signinff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
maninff <= mantissain;
expinff <= exponentin;
signinff(1) <= signin;
signinff(2) <= signinff(1);
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= maninff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR maninff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= NOT(zeroman(manwidth));
zeroexpinff <= NOT(zeroexp(expwidth));
maxexpinff <= maxexp(expwidth);
-- infinity when exp = zero
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
naninff <= (zeromaninff AND maxexpinff) OR signinff(2);
infinityinff <= zeroexpinff OR maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
infinityff(1) <= infinityinff;
FOR k IN 2 TO coredepth-3 LOOP
infinityff(k) <= infinityff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--***************
--*** LN CORE ***
--***************
lncore: fp_ln_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mantissain,aaexp=>exponentin,
ccman=>mantissanode,ccexp=>exponentnode,ccsgn=>signnode,
zeroout=>zeronode);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_lnrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signln=>signnode,
exponentln=>exponentnode,
mantissaln=>mantissanode,
nanin=>nanff(coredepth-3),
infinityin=>infinityff(coredepth-3),
zeroin=>zeronode,
signout=>signout,
exponentout=>exponentout,
mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION LOG(LN) - TOP LEVEL ***
--*** ***
--*** FP_LOG.VHD ***
--*** ***
--*** Function: IEEE754 FP LOG() ***
--*** ***
--*** 21/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 21 ***
--***************************************************
ENTITY fp_log IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_log;
ARCHITECTURE rtl OF fp_log IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 19;
signal signinff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signnode : STD_LOGIC;
signal mantissanode : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal zeronode : STD_LOGIC;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
signal infinityinff : STD_LOGIC;
signal infinityff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_ln_core
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
ccsgn : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component fp_lnrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
BEGIN
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
signinff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
maninff <= mantissain;
expinff <= exponentin;
signinff(1) <= signin;
signinff(2) <= signinff(1);
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= maninff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR maninff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= NOT(zeroman(manwidth));
zeroexpinff <= NOT(zeroexp(expwidth));
maxexpinff <= maxexp(expwidth);
-- infinity when exp = zero
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
naninff <= (zeromaninff AND maxexpinff) OR signinff(2);
infinityinff <= zeroexpinff OR maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
infinityff(1) <= infinityinff;
FOR k IN 2 TO coredepth-3 LOOP
infinityff(k) <= infinityff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--***************
--*** LN CORE ***
--***************
lncore: fp_ln_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mantissain,aaexp=>exponentin,
ccman=>mantissanode,ccexp=>exponentnode,ccsgn=>signnode,
zeroout=>zeronode);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_lnrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signln=>signnode,
exponentln=>exponentnode,
mantissaln=>mantissanode,
nanin=>nanff(coredepth-3),
infinityin=>infinityff(coredepth-3),
zeroin=>zeronode,
signout=>signout,
exponentout=>exponentout,
mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION LOG(LN) - TOP LEVEL ***
--*** ***
--*** FP_LOG.VHD ***
--*** ***
--*** Function: IEEE754 FP LOG() ***
--*** ***
--*** 21/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 21 ***
--***************************************************
ENTITY fp_log IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_log;
ARCHITECTURE rtl OF fp_log IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 19;
signal signinff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signnode : STD_LOGIC;
signal mantissanode : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal zeronode : STD_LOGIC;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
signal infinityinff : STD_LOGIC;
signal infinityff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_ln_core
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
ccsgn : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component fp_lnrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
BEGIN
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
signinff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
maninff <= mantissain;
expinff <= exponentin;
signinff(1) <= signin;
signinff(2) <= signinff(1);
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= maninff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR maninff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= NOT(zeroman(manwidth));
zeroexpinff <= NOT(zeroexp(expwidth));
maxexpinff <= maxexp(expwidth);
-- infinity when exp = zero
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
naninff <= (zeromaninff AND maxexpinff) OR signinff(2);
infinityinff <= zeroexpinff OR maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
infinityff(1) <= infinityinff;
FOR k IN 2 TO coredepth-3 LOOP
infinityff(k) <= infinityff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--***************
--*** LN CORE ***
--***************
lncore: fp_ln_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mantissain,aaexp=>exponentin,
ccman=>mantissanode,ccexp=>exponentnode,ccsgn=>signnode,
zeroout=>zeronode);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_lnrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signln=>signnode,
exponentln=>exponentnode,
mantissaln=>mantissanode,
nanin=>nanff(coredepth-3),
infinityin=>infinityff(coredepth-3),
zeroin=>zeronode,
signout=>signout,
exponentout=>exponentout,
mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION LOG(LN) - TOP LEVEL ***
--*** ***
--*** FP_LOG.VHD ***
--*** ***
--*** Function: IEEE754 FP LOG() ***
--*** ***
--*** 21/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 21 ***
--***************************************************
ENTITY fp_log IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_log;
ARCHITECTURE rtl OF fp_log IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 19;
signal signinff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signnode : STD_LOGIC;
signal mantissanode : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal zeronode : STD_LOGIC;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
signal infinityinff : STD_LOGIC;
signal infinityff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_ln_core
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
ccsgn : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component fp_lnrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
BEGIN
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
signinff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
maninff <= mantissain;
expinff <= exponentin;
signinff(1) <= signin;
signinff(2) <= signinff(1);
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= maninff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR maninff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= NOT(zeroman(manwidth));
zeroexpinff <= NOT(zeroexp(expwidth));
maxexpinff <= maxexp(expwidth);
-- infinity when exp = zero
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
naninff <= (zeromaninff AND maxexpinff) OR signinff(2);
infinityinff <= zeroexpinff OR maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
infinityff(1) <= infinityinff;
FOR k IN 2 TO coredepth-3 LOOP
infinityff(k) <= infinityff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--***************
--*** LN CORE ***
--***************
lncore: fp_ln_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mantissain,aaexp=>exponentin,
ccman=>mantissanode,ccexp=>exponentnode,ccsgn=>signnode,
zeroout=>zeronode);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_lnrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signln=>signnode,
exponentln=>exponentnode,
mantissaln=>mantissanode,
nanin=>nanff(coredepth-3),
infinityin=>infinityff(coredepth-3),
zeroin=>zeronode,
signout=>signout,
exponentout=>exponentout,
mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION LOG(LN) - TOP LEVEL ***
--*** ***
--*** FP_LOG.VHD ***
--*** ***
--*** Function: IEEE754 FP LOG() ***
--*** ***
--*** 21/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 21 ***
--***************************************************
ENTITY fp_log IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_log;
ARCHITECTURE rtl OF fp_log IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 19;
signal signinff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signnode : STD_LOGIC;
signal mantissanode : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal zeronode : STD_LOGIC;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
signal infinityinff : STD_LOGIC;
signal infinityff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_ln_core
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
ccsgn : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component fp_lnrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
BEGIN
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
signinff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
maninff <= mantissain;
expinff <= exponentin;
signinff(1) <= signin;
signinff(2) <= signinff(1);
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= maninff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR maninff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= NOT(zeroman(manwidth));
zeroexpinff <= NOT(zeroexp(expwidth));
maxexpinff <= maxexp(expwidth);
-- infinity when exp = zero
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
naninff <= (zeromaninff AND maxexpinff) OR signinff(2);
infinityinff <= zeroexpinff OR maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
infinityff(1) <= infinityinff;
FOR k IN 2 TO coredepth-3 LOOP
infinityff(k) <= infinityff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--***************
--*** LN CORE ***
--***************
lncore: fp_ln_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mantissain,aaexp=>exponentin,
ccman=>mantissanode,ccexp=>exponentnode,ccsgn=>signnode,
zeroout=>zeronode);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_lnrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signln=>signnode,
exponentln=>exponentnode,
mantissaln=>mantissanode,
nanin=>nanff(coredepth-3),
infinityin=>infinityff(coredepth-3),
zeroin=>zeronode,
signout=>signout,
exponentout=>exponentout,
mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION LOG(LN) - TOP LEVEL ***
--*** ***
--*** FP_LOG.VHD ***
--*** ***
--*** Function: IEEE754 FP LOG() ***
--*** ***
--*** 21/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 21 ***
--***************************************************
ENTITY fp_log IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_log;
ARCHITECTURE rtl OF fp_log IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 19;
signal signinff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signnode : STD_LOGIC;
signal mantissanode : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal zeronode : STD_LOGIC;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
signal infinityinff : STD_LOGIC;
signal infinityff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_ln_core
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
ccsgn : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component fp_lnrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
BEGIN
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
signinff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
maninff <= mantissain;
expinff <= exponentin;
signinff(1) <= signin;
signinff(2) <= signinff(1);
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= maninff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR maninff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= NOT(zeroman(manwidth));
zeroexpinff <= NOT(zeroexp(expwidth));
maxexpinff <= maxexp(expwidth);
-- infinity when exp = zero
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
naninff <= (zeromaninff AND maxexpinff) OR signinff(2);
infinityinff <= zeroexpinff OR maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
infinityff(1) <= infinityinff;
FOR k IN 2 TO coredepth-3 LOOP
infinityff(k) <= infinityff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--***************
--*** LN CORE ***
--***************
lncore: fp_ln_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mantissain,aaexp=>exponentin,
ccman=>mantissanode,ccexp=>exponentnode,ccsgn=>signnode,
zeroout=>zeronode);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_lnrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signln=>signnode,
exponentln=>exponentnode,
mantissaln=>mantissanode,
nanin=>nanff(coredepth-3),
infinityin=>infinityff(coredepth-3),
zeroin=>zeronode,
signout=>signout,
exponentout=>exponentout,
mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION LOG(LN) - TOP LEVEL ***
--*** ***
--*** FP_LOG.VHD ***
--*** ***
--*** Function: IEEE754 FP LOG() ***
--*** ***
--*** 21/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 21 ***
--***************************************************
ENTITY fp_log IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_log;
ARCHITECTURE rtl OF fp_log IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 19;
signal signinff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signnode : STD_LOGIC;
signal mantissanode : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal zeronode : STD_LOGIC;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
signal infinityinff : STD_LOGIC;
signal infinityff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_ln_core
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
ccsgn : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component fp_lnrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
BEGIN
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
signinff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
maninff <= mantissain;
expinff <= exponentin;
signinff(1) <= signin;
signinff(2) <= signinff(1);
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= maninff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR maninff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= NOT(zeroman(manwidth));
zeroexpinff <= NOT(zeroexp(expwidth));
maxexpinff <= maxexp(expwidth);
-- infinity when exp = zero
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
naninff <= (zeromaninff AND maxexpinff) OR signinff(2);
infinityinff <= zeroexpinff OR maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
infinityff(1) <= infinityinff;
FOR k IN 2 TO coredepth-3 LOOP
infinityff(k) <= infinityff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--***************
--*** LN CORE ***
--***************
lncore: fp_ln_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mantissain,aaexp=>exponentin,
ccman=>mantissanode,ccexp=>exponentnode,ccsgn=>signnode,
zeroout=>zeronode);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_lnrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signln=>signnode,
exponentln=>exponentnode,
mantissaln=>mantissanode,
nanin=>nanff(coredepth-3),
infinityin=>infinityff(coredepth-3),
zeroin=>zeronode,
signout=>signout,
exponentout=>exponentout,
mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION LOG(LN) - TOP LEVEL ***
--*** ***
--*** FP_LOG.VHD ***
--*** ***
--*** Function: IEEE754 FP LOG() ***
--*** ***
--*** 21/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 21 ***
--***************************************************
ENTITY fp_log IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_log;
ARCHITECTURE rtl OF fp_log IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 19;
signal signinff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signnode : STD_LOGIC;
signal mantissanode : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal zeronode : STD_LOGIC;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
signal infinityinff : STD_LOGIC;
signal infinityff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_ln_core
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
ccsgn : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component fp_lnrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
BEGIN
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
signinff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
maninff <= mantissain;
expinff <= exponentin;
signinff(1) <= signin;
signinff(2) <= signinff(1);
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= maninff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR maninff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= NOT(zeroman(manwidth));
zeroexpinff <= NOT(zeroexp(expwidth));
maxexpinff <= maxexp(expwidth);
-- infinity when exp = zero
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
naninff <= (zeromaninff AND maxexpinff) OR signinff(2);
infinityinff <= zeroexpinff OR maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
infinityff(1) <= infinityinff;
FOR k IN 2 TO coredepth-3 LOOP
infinityff(k) <= infinityff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--***************
--*** LN CORE ***
--***************
lncore: fp_ln_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mantissain,aaexp=>exponentin,
ccman=>mantissanode,ccexp=>exponentnode,ccsgn=>signnode,
zeroout=>zeronode);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_lnrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signln=>signnode,
exponentln=>exponentnode,
mantissaln=>mantissanode,
nanin=>nanff(coredepth-3),
infinityin=>infinityff(coredepth-3),
zeroin=>zeronode,
signout=>signout,
exponentout=>exponentout,
mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION LOG(LN) - TOP LEVEL ***
--*** ***
--*** FP_LOG.VHD ***
--*** ***
--*** Function: IEEE754 FP LOG() ***
--*** ***
--*** 21/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 21 ***
--***************************************************
ENTITY fp_log IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_log;
ARCHITECTURE rtl OF fp_log IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 19;
signal signinff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signnode : STD_LOGIC;
signal mantissanode : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal zeronode : STD_LOGIC;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
signal infinityinff : STD_LOGIC;
signal infinityff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_ln_core
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
ccsgn : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component fp_lnrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
BEGIN
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
signinff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
maninff <= mantissain;
expinff <= exponentin;
signinff(1) <= signin;
signinff(2) <= signinff(1);
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= maninff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR maninff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= NOT(zeroman(manwidth));
zeroexpinff <= NOT(zeroexp(expwidth));
maxexpinff <= maxexp(expwidth);
-- infinity when exp = zero
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
naninff <= (zeromaninff AND maxexpinff) OR signinff(2);
infinityinff <= zeroexpinff OR maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
infinityff(1) <= infinityinff;
FOR k IN 2 TO coredepth-3 LOOP
infinityff(k) <= infinityff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--***************
--*** LN CORE ***
--***************
lncore: fp_ln_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mantissain,aaexp=>exponentin,
ccman=>mantissanode,ccexp=>exponentnode,ccsgn=>signnode,
zeroout=>zeronode);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_lnrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signln=>signnode,
exponentln=>exponentnode,
mantissaln=>mantissanode,
nanin=>nanff(coredepth-3),
infinityin=>infinityff(coredepth-3),
zeroin=>zeronode,
signout=>signout,
exponentout=>exponentout,
mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout);
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION LOG(LN) - TOP LEVEL ***
--*** ***
--*** FP_LOG.VHD ***
--*** ***
--*** Function: IEEE754 FP LOG() ***
--*** ***
--*** 21/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 21 ***
--***************************************************
ENTITY fp_log IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_log;
ARCHITECTURE rtl OF fp_log IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 19;
signal signinff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signnode : STD_LOGIC;
signal mantissanode : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal zeronode : STD_LOGIC;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
signal infinityinff : STD_LOGIC;
signal infinityff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_ln_core
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
ccsgn : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component fp_lnrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
BEGIN
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
signinff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
maninff <= mantissain;
expinff <= exponentin;
signinff(1) <= signin;
signinff(2) <= signinff(1);
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= maninff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR maninff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= NOT(zeroman(manwidth));
zeroexpinff <= NOT(zeroexp(expwidth));
maxexpinff <= maxexp(expwidth);
-- infinity when exp = zero
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
naninff <= (zeromaninff AND maxexpinff) OR signinff(2);
infinityinff <= zeroexpinff OR maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
infinityff(1) <= infinityinff;
FOR k IN 2 TO coredepth-3 LOOP
infinityff(k) <= infinityff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--***************
--*** LN CORE ***
--***************
lncore: fp_ln_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mantissain,aaexp=>exponentin,
ccman=>mantissanode,ccexp=>exponentnode,ccsgn=>signnode,
zeroout=>zeronode);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_lnrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signln=>signnode,
exponentln=>exponentnode,
mantissaln=>mantissanode,
nanin=>nanff(coredepth-3),
infinityin=>infinityff(coredepth-3),
zeroin=>zeronode,
signout=>signout,
exponentout=>exponentout,
mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout);
END rtl;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_ok_3_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ok_3_e-c.vhd,v 1.2 2005/07/15 16:20:00 wig Exp $
-- $Date: 2005/07/15 16:20:00 $
-- $Log: inst_ok_3_e-c.vhd,v $
-- Revision 1.2 2005/07/15 16:20:00 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_ok_3_rtl_conf / inst_ok_3_e
--
configuration inst_ok_3_rtl_conf of inst_ok_3_e is
for rtl
-- Generated Configuration
end for;
end inst_ok_3_rtl_conf;
--
-- End of Generated Configuration inst_ok_3_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:51:48 02/20/2013
-- Design Name:
-- Module Name: /home/frank/testproject/Imem_tb.vhd
-- Project Name: testproject
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: imem
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Imem_tb IS
END Imem_tb;
ARCHITECTURE behavior OF Imem_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT imem
PORT(
pc : IN std_logic_vector(31 downto 0);
Instruction : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal pc : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal Instruction : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace clk below with
-- appropriate port name
signal clk : std_logic;
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: imem PORT MAP (
pc => pc,
Instruction => Instruction
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
pc <= X"00000000";
wait for clk_period;
pc <= X"00000004";
wait for clk_period;
pc <= X"00000008";
wait for clk_period;
pc <= X"0000000C";
wait for clk_period;
pc <= X"00000010";
wait for clk_period;
wait;
end process;
END;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_e_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_e_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:41 wig Exp $
-- $Date: 2004/04/06 10:50:41 $
-- $Log: inst_e_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:41 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_e_e
--
architecture rtl of inst_e_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_ea_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_eb_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ec_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ed_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component inst_ee_e --
-- No Generated Generics
-- Generated Generics for Entity inst_ee_e
-- End of Generated Generics for Entity inst_ee_e
-- No Generated Port
end component;
-- ---------
component inst_ef_e --
-- No Generated Generics
-- Generated Generics for Entity inst_ef_e
-- End of Generated Generics for Entity inst_ef_e
-- No Generated Port
end component;
-- ---------
component inst_eg_e --
-- No Generated Generics
-- Generated Generics for Entity inst_eg_e
-- End of Generated Generics for Entity inst_eg_e
-- No Generated Port
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_ea
inst_ea: inst_ea_e
;
-- End of Generated Instance Port Map for inst_ea
-- Generated Instance Port Map for inst_eb
inst_eb: inst_eb_e
;
-- End of Generated Instance Port Map for inst_eb
-- Generated Instance Port Map for inst_ec
inst_ec: inst_ec_e
;
-- End of Generated Instance Port Map for inst_ec
-- Generated Instance Port Map for inst_ed
inst_ed: inst_ed_e
;
-- End of Generated Instance Port Map for inst_ed
-- Generated Instance Port Map for inst_ee
inst_ee: inst_ee_e
;
-- End of Generated Instance Port Map for inst_ee
-- Generated Instance Port Map for inst_ef
inst_ef: inst_ef_e
;
-- End of Generated Instance Port Map for inst_ef
-- Generated Instance Port Map for inst_eg
inst_eg: inst_eg_e
;
-- End of Generated Instance Port Map for inst_eg
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo (orinaudo@gmail.com)
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 1);
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
--type
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
--Which 8KB block
alias block_sel: std_logic_vector(2 downto 0) is address(15 downto 13);
--Address within a 8KB block (without lower two bits)
alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2);
--Block enable with 1 bit per memory block
signal block_enable: std_logic_vector(7 downto 0);
--Block Data Out
signal block_do: mem32_vector(7 downto 0);
--Remember which block was selected
signal block_sel_buf: std_logic_vector(2 downto 0);
begin
block_enable<= "00000001" when (enable='1') and (block_sel="000") else
"00000010" when (enable='1') and (block_sel="001") else
"00000100" when (enable='1') and (block_sel="010") else
"00001000" when (enable='1') and (block_sel="011") else
"00010000" when (enable='1') and (block_sel="100") else
"00100000" when (enable='1') and (block_sel="101") else
"01000000" when (enable='1') and (block_sel="110") else
"10000000" when (enable='1') and (block_sel="111") else
"00000000";
proc_blocksel: process (clk, block_sel) is
begin
if rising_edge(clk) then
block_sel_buf <= block_sel;
end if;
end process;
proc_do: process (block_do, block_sel_buf) is
begin
data_read <= block_do(conv_integer(block_sel_buf));
end process;
-- BLOCKS generation
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000c080400",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000d090501",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000e0a0602",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000f0b0703",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo (orinaudo@gmail.com)
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 1);
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
--type
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
--Which 8KB block
alias block_sel: std_logic_vector(2 downto 0) is address(15 downto 13);
--Address within a 8KB block (without lower two bits)
alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2);
--Block enable with 1 bit per memory block
signal block_enable: std_logic_vector(7 downto 0);
--Block Data Out
signal block_do: mem32_vector(7 downto 0);
--Remember which block was selected
signal block_sel_buf: std_logic_vector(2 downto 0);
begin
block_enable<= "00000001" when (enable='1') and (block_sel="000") else
"00000010" when (enable='1') and (block_sel="001") else
"00000100" when (enable='1') and (block_sel="010") else
"00001000" when (enable='1') and (block_sel="011") else
"00010000" when (enable='1') and (block_sel="100") else
"00100000" when (enable='1') and (block_sel="101") else
"01000000" when (enable='1') and (block_sel="110") else
"10000000" when (enable='1') and (block_sel="111") else
"00000000";
proc_blocksel: process (clk, block_sel) is
begin
if rising_edge(clk) then
block_sel_buf <= block_sel;
end if;
end process;
proc_do: process (block_do, block_sel_buf) is
begin
data_read <= block_do(conv_integer(block_sel_buf));
end process;
-- BLOCKS generation
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000c080400",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000d090501",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000e0a0602",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000f0b0703",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo (orinaudo@gmail.com)
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 1);
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
--type
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
--Which 8KB block
alias block_sel: std_logic_vector(2 downto 0) is address(15 downto 13);
--Address within a 8KB block (without lower two bits)
alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2);
--Block enable with 1 bit per memory block
signal block_enable: std_logic_vector(7 downto 0);
--Block Data Out
signal block_do: mem32_vector(7 downto 0);
--Remember which block was selected
signal block_sel_buf: std_logic_vector(2 downto 0);
begin
block_enable<= "00000001" when (enable='1') and (block_sel="000") else
"00000010" when (enable='1') and (block_sel="001") else
"00000100" when (enable='1') and (block_sel="010") else
"00001000" when (enable='1') and (block_sel="011") else
"00010000" when (enable='1') and (block_sel="100") else
"00100000" when (enable='1') and (block_sel="101") else
"01000000" when (enable='1') and (block_sel="110") else
"10000000" when (enable='1') and (block_sel="111") else
"00000000";
proc_blocksel: process (clk, block_sel) is
begin
if rising_edge(clk) then
block_sel_buf <= block_sel;
end if;
end process;
proc_do: process (block_do, block_sel_buf) is
begin
data_read <= block_do(conv_integer(block_sel_buf));
end process;
-- BLOCKS generation
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000c080400",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000d090501",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000e0a0602",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000f0b0703",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo (orinaudo@gmail.com)
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 1);
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
--type
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
--Which 8KB block
alias block_sel: std_logic_vector(2 downto 0) is address(15 downto 13);
--Address within a 8KB block (without lower two bits)
alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2);
--Block enable with 1 bit per memory block
signal block_enable: std_logic_vector(7 downto 0);
--Block Data Out
signal block_do: mem32_vector(7 downto 0);
--Remember which block was selected
signal block_sel_buf: std_logic_vector(2 downto 0);
begin
block_enable<= "00000001" when (enable='1') and (block_sel="000") else
"00000010" when (enable='1') and (block_sel="001") else
"00000100" when (enable='1') and (block_sel="010") else
"00001000" when (enable='1') and (block_sel="011") else
"00010000" when (enable='1') and (block_sel="100") else
"00100000" when (enable='1') and (block_sel="101") else
"01000000" when (enable='1') and (block_sel="110") else
"10000000" when (enable='1') and (block_sel="111") else
"00000000";
proc_blocksel: process (clk, block_sel) is
begin
if rising_edge(clk) then
block_sel_buf <= block_sel;
end if;
end process;
proc_do: process (block_do, block_sel_buf) is
begin
data_read <= block_do(conv_integer(block_sel_buf));
end process;
-- BLOCKS generation
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000c080400",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000d090501",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000e0a0602",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000f0b0703",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
end; --architecture logic
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2761.vhd,v 1.1.1.1 2001-08-22 18:20:52 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
ENTITY c13s07b00x00p05n01i02761ent IS
END c13s07b00x00p05n01i02761ent;
-- Dale Martin modified this file to make the bit string literal comparisons
-- VHDL '93 compliant, by qualifying them with bit_string_literal'(
ARCHITECTURE c13s07b00x00p05n01i02761arch OF c13s07b00x00p05n01i02761ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( ( bit_vector'(B"01_111_101") = B"0111_1101" )
and ( bit_vector'(O"17_5") = O"1_75")
and ( bit_vector'(X"7D") = X"7_D"))
report "***PASSED TEST: c13s07b00x00p05n01i02761"
severity NOTE;
assert ( ( bit_vector'(B"01_111_101") = B"0111_1101" )
and ( bit_vector'(O"17_5")=O"1_75")
and ( bit_vector'(X"7D")=X"7_D"))
report "***FAILED TEST: c13s07b00x00p05n01i02761 - Underline character should not affect the value of the bit string literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s07b00x00p05n01i02761arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2761.vhd,v 1.1.1.1 2001-08-22 18:20:52 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
ENTITY c13s07b00x00p05n01i02761ent IS
END c13s07b00x00p05n01i02761ent;
-- Dale Martin modified this file to make the bit string literal comparisons
-- VHDL '93 compliant, by qualifying them with bit_string_literal'(
ARCHITECTURE c13s07b00x00p05n01i02761arch OF c13s07b00x00p05n01i02761ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( ( bit_vector'(B"01_111_101") = B"0111_1101" )
and ( bit_vector'(O"17_5") = O"1_75")
and ( bit_vector'(X"7D") = X"7_D"))
report "***PASSED TEST: c13s07b00x00p05n01i02761"
severity NOTE;
assert ( ( bit_vector'(B"01_111_101") = B"0111_1101" )
and ( bit_vector'(O"17_5")=O"1_75")
and ( bit_vector'(X"7D")=X"7_D"))
report "***FAILED TEST: c13s07b00x00p05n01i02761 - Underline character should not affect the value of the bit string literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s07b00x00p05n01i02761arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2761.vhd,v 1.1.1.1 2001-08-22 18:20:52 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
ENTITY c13s07b00x00p05n01i02761ent IS
END c13s07b00x00p05n01i02761ent;
-- Dale Martin modified this file to make the bit string literal comparisons
-- VHDL '93 compliant, by qualifying them with bit_string_literal'(
ARCHITECTURE c13s07b00x00p05n01i02761arch OF c13s07b00x00p05n01i02761ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( ( bit_vector'(B"01_111_101") = B"0111_1101" )
and ( bit_vector'(O"17_5") = O"1_75")
and ( bit_vector'(X"7D") = X"7_D"))
report "***PASSED TEST: c13s07b00x00p05n01i02761"
severity NOTE;
assert ( ( bit_vector'(B"01_111_101") = B"0111_1101" )
and ( bit_vector'(O"17_5")=O"1_75")
and ( bit_vector'(X"7D")=X"7_D"))
report "***FAILED TEST: c13s07b00x00p05n01i02761 - Underline character should not affect the value of the bit string literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s07b00x00p05n01i02761arch;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
architecture abstract of adder is
begin
add_a_b : process (a, b) is
begin
sum <= a + b;
end process add_a_b;
end architecture abstract;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
architecture abstract of adder is
begin
add_a_b : process (a, b) is
begin
sum <= a + b;
end process add_a_b;
end architecture abstract;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
architecture abstract of adder is
begin
add_a_b : process (a, b) is
begin
sum <= a + b;
end process add_a_b;
end architecture abstract;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
entity iec_processor_tb is
end iec_processor_tb;
architecture tb of iec_processor_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal req : t_io_req;
signal resp : t_io_resp;
signal slave_clk_o : std_logic;
signal slave_data_o : std_logic;
signal slave_atn_o : std_logic;
signal srq_o : std_logic;
signal master_clk_o : std_logic;
signal master_data_o : std_logic;
signal master_atn_o : std_logic;
signal iec_clock : std_logic;
signal iec_data : std_logic;
signal iec_atn : std_logic;
signal received : std_logic_vector(7 downto 0);
signal eoi : std_logic;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.iec_processor_io
port map (
clock => clock,
reset => reset,
req => req,
resp => resp,
clk_o => slave_clk_o,
clk_i => iec_clock,
data_o => slave_data_o,
data_i => iec_data,
atn_o => slave_atn_o,
atn_i => iec_atn,
srq_o => srq_o,
srq_i => srq_o );
iec_clock <= '0' when (slave_clk_o='0') or (master_clk_o='0') else 'H';
iec_data <= '0' when (slave_data_o='0') or (master_data_o='0') else 'H';
iec_atn <= '0' when (slave_atn_o='0') or (master_atn_o='0') else 'H';
i_io_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock,
req => req,
resp => resp );
-- i_iec_bfm: entity work.iec_bus_bfm
-- port map (
-- iec_clock => iec_clock,
-- iec_data => iec_data,
-- iec_atn => iec_atn );
process
procedure send_atn_byte(b : std_logic_vector(7 downto 0)) is
begin
master_atn_o <= '0';
wait for 20 us;
master_clk_o <= '0';
wait for 100 us;
master_clk_o <= '1';
if iec_data='0' then
wait until iec_data='H';
end if;
wait for 80 us;
for i in 0 to 7 loop
master_data_o <= b(i);
master_clk_o <= '0';
wait for 60 us;
master_clk_o <= '1';
wait for 60 us;
end loop;
master_data_o <= '1';
master_clk_o <= '0';
wait for 1 us;
if iec_data /= '0' then
wait until iec_data = '0' for 1000 us;
end if;
wait for 20 us;
master_atn_o <= '1';
end procedure;
procedure receive_byte(ret : out std_logic_vector(7 downto 0); eoi : out std_logic) is
variable data : std_logic_vector(7 downto 0);
variable last : std_logic;
begin
last := '0';
master_data_o <= '1'; -- ok, go ahead
wait until iec_clock = '0' for 200 us;
if iec_clock = 'H' then
master_data_o <= '0';
last := '1';
wait for 60 us;
master_data_o <= '1';
if iec_clock /= '0' then
wait until iec_clock = '0';
end if;
end if;
for i in 0 to 7 loop
wait until iec_clock = 'H' for 200 us;
data(i) := iec_data;
end loop;
wait until iec_clock = '0';
master_data_o <= '0'; -- seen it!!
wait for 60 us;
ret := data;
eoi := last;
end procedure;
variable data : std_logic_vector(7 downto 0);
variable last : std_logic;
begin
master_clk_o <= '1';
master_data_o <= '1';
master_atn_o <= '1';
wait for 10 us;
send_atn_byte(X"4A");
send_atn_byte(X"6F");
wait for 50 us;
master_clk_o <= '1'; -- release
master_data_o <= '0'; -- wait, I am not ready!!
wait for 10 us;
wait until iec_clock='H';
wait for 30 us;
receive_byte(data, last);
received <= data;
eoi <= last;
receive_byte(data, last);
received <= data;
eoi <= last;
receive_byte(data, last);
received <= data;
eoi <= last;
wait;
end process;
process
variable io : p_io_bus_bfm_object;
variable stat : std_logic_vector(7 downto 0);
variable data : std_logic_vector(7 downto 0);
begin
wait for 1 us;
bind_io_bus_bfm("io_bfm", io);
while true loop
io_read(io, X"2", stat);
if stat(0)='0' then -- not empty, so data avail
io_read(io, X"6", data);
if stat(7)='1' and data=X"43" then
wait for 400 us;
io_write(io, X"4", X"33");
io_write(io, X"4", X"44");
io_write(io, X"5", X"55"); -- last byte
end if;
end if;
end loop;
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
entity iec_processor_tb is
end iec_processor_tb;
architecture tb of iec_processor_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal req : t_io_req;
signal resp : t_io_resp;
signal slave_clk_o : std_logic;
signal slave_data_o : std_logic;
signal slave_atn_o : std_logic;
signal srq_o : std_logic;
signal master_clk_o : std_logic;
signal master_data_o : std_logic;
signal master_atn_o : std_logic;
signal iec_clock : std_logic;
signal iec_data : std_logic;
signal iec_atn : std_logic;
signal received : std_logic_vector(7 downto 0);
signal eoi : std_logic;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.iec_processor_io
port map (
clock => clock,
reset => reset,
req => req,
resp => resp,
clk_o => slave_clk_o,
clk_i => iec_clock,
data_o => slave_data_o,
data_i => iec_data,
atn_o => slave_atn_o,
atn_i => iec_atn,
srq_o => srq_o,
srq_i => srq_o );
iec_clock <= '0' when (slave_clk_o='0') or (master_clk_o='0') else 'H';
iec_data <= '0' when (slave_data_o='0') or (master_data_o='0') else 'H';
iec_atn <= '0' when (slave_atn_o='0') or (master_atn_o='0') else 'H';
i_io_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock,
req => req,
resp => resp );
-- i_iec_bfm: entity work.iec_bus_bfm
-- port map (
-- iec_clock => iec_clock,
-- iec_data => iec_data,
-- iec_atn => iec_atn );
process
procedure send_atn_byte(b : std_logic_vector(7 downto 0)) is
begin
master_atn_o <= '0';
wait for 20 us;
master_clk_o <= '0';
wait for 100 us;
master_clk_o <= '1';
if iec_data='0' then
wait until iec_data='H';
end if;
wait for 80 us;
for i in 0 to 7 loop
master_data_o <= b(i);
master_clk_o <= '0';
wait for 60 us;
master_clk_o <= '1';
wait for 60 us;
end loop;
master_data_o <= '1';
master_clk_o <= '0';
wait for 1 us;
if iec_data /= '0' then
wait until iec_data = '0' for 1000 us;
end if;
wait for 20 us;
master_atn_o <= '1';
end procedure;
procedure receive_byte(ret : out std_logic_vector(7 downto 0); eoi : out std_logic) is
variable data : std_logic_vector(7 downto 0);
variable last : std_logic;
begin
last := '0';
master_data_o <= '1'; -- ok, go ahead
wait until iec_clock = '0' for 200 us;
if iec_clock = 'H' then
master_data_o <= '0';
last := '1';
wait for 60 us;
master_data_o <= '1';
if iec_clock /= '0' then
wait until iec_clock = '0';
end if;
end if;
for i in 0 to 7 loop
wait until iec_clock = 'H' for 200 us;
data(i) := iec_data;
end loop;
wait until iec_clock = '0';
master_data_o <= '0'; -- seen it!!
wait for 60 us;
ret := data;
eoi := last;
end procedure;
variable data : std_logic_vector(7 downto 0);
variable last : std_logic;
begin
master_clk_o <= '1';
master_data_o <= '1';
master_atn_o <= '1';
wait for 10 us;
send_atn_byte(X"4A");
send_atn_byte(X"6F");
wait for 50 us;
master_clk_o <= '1'; -- release
master_data_o <= '0'; -- wait, I am not ready!!
wait for 10 us;
wait until iec_clock='H';
wait for 30 us;
receive_byte(data, last);
received <= data;
eoi <= last;
receive_byte(data, last);
received <= data;
eoi <= last;
receive_byte(data, last);
received <= data;
eoi <= last;
wait;
end process;
process
variable io : p_io_bus_bfm_object;
variable stat : std_logic_vector(7 downto 0);
variable data : std_logic_vector(7 downto 0);
begin
wait for 1 us;
bind_io_bus_bfm("io_bfm", io);
while true loop
io_read(io, X"2", stat);
if stat(0)='0' then -- not empty, so data avail
io_read(io, X"6", data);
if stat(7)='1' and data=X"43" then
wait for 400 us;
io_write(io, X"4", X"33");
io_write(io, X"4", X"44");
io_write(io, X"5", X"55"); -- last byte
end if;
end if;
end loop;
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
entity iec_processor_tb is
end iec_processor_tb;
architecture tb of iec_processor_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal req : t_io_req;
signal resp : t_io_resp;
signal slave_clk_o : std_logic;
signal slave_data_o : std_logic;
signal slave_atn_o : std_logic;
signal srq_o : std_logic;
signal master_clk_o : std_logic;
signal master_data_o : std_logic;
signal master_atn_o : std_logic;
signal iec_clock : std_logic;
signal iec_data : std_logic;
signal iec_atn : std_logic;
signal received : std_logic_vector(7 downto 0);
signal eoi : std_logic;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.iec_processor_io
port map (
clock => clock,
reset => reset,
req => req,
resp => resp,
clk_o => slave_clk_o,
clk_i => iec_clock,
data_o => slave_data_o,
data_i => iec_data,
atn_o => slave_atn_o,
atn_i => iec_atn,
srq_o => srq_o,
srq_i => srq_o );
iec_clock <= '0' when (slave_clk_o='0') or (master_clk_o='0') else 'H';
iec_data <= '0' when (slave_data_o='0') or (master_data_o='0') else 'H';
iec_atn <= '0' when (slave_atn_o='0') or (master_atn_o='0') else 'H';
i_io_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock,
req => req,
resp => resp );
-- i_iec_bfm: entity work.iec_bus_bfm
-- port map (
-- iec_clock => iec_clock,
-- iec_data => iec_data,
-- iec_atn => iec_atn );
process
procedure send_atn_byte(b : std_logic_vector(7 downto 0)) is
begin
master_atn_o <= '0';
wait for 20 us;
master_clk_o <= '0';
wait for 100 us;
master_clk_o <= '1';
if iec_data='0' then
wait until iec_data='H';
end if;
wait for 80 us;
for i in 0 to 7 loop
master_data_o <= b(i);
master_clk_o <= '0';
wait for 60 us;
master_clk_o <= '1';
wait for 60 us;
end loop;
master_data_o <= '1';
master_clk_o <= '0';
wait for 1 us;
if iec_data /= '0' then
wait until iec_data = '0' for 1000 us;
end if;
wait for 20 us;
master_atn_o <= '1';
end procedure;
procedure receive_byte(ret : out std_logic_vector(7 downto 0); eoi : out std_logic) is
variable data : std_logic_vector(7 downto 0);
variable last : std_logic;
begin
last := '0';
master_data_o <= '1'; -- ok, go ahead
wait until iec_clock = '0' for 200 us;
if iec_clock = 'H' then
master_data_o <= '0';
last := '1';
wait for 60 us;
master_data_o <= '1';
if iec_clock /= '0' then
wait until iec_clock = '0';
end if;
end if;
for i in 0 to 7 loop
wait until iec_clock = 'H' for 200 us;
data(i) := iec_data;
end loop;
wait until iec_clock = '0';
master_data_o <= '0'; -- seen it!!
wait for 60 us;
ret := data;
eoi := last;
end procedure;
variable data : std_logic_vector(7 downto 0);
variable last : std_logic;
begin
master_clk_o <= '1';
master_data_o <= '1';
master_atn_o <= '1';
wait for 10 us;
send_atn_byte(X"4A");
send_atn_byte(X"6F");
wait for 50 us;
master_clk_o <= '1'; -- release
master_data_o <= '0'; -- wait, I am not ready!!
wait for 10 us;
wait until iec_clock='H';
wait for 30 us;
receive_byte(data, last);
received <= data;
eoi <= last;
receive_byte(data, last);
received <= data;
eoi <= last;
receive_byte(data, last);
received <= data;
eoi <= last;
wait;
end process;
process
variable io : p_io_bus_bfm_object;
variable stat : std_logic_vector(7 downto 0);
variable data : std_logic_vector(7 downto 0);
begin
wait for 1 us;
bind_io_bus_bfm("io_bfm", io);
while true loop
io_read(io, X"2", stat);
if stat(0)='0' then -- not empty, so data avail
io_read(io, X"6", data);
if stat(7)='1' and data=X"43" then
wait for 400 us;
io_write(io, X"4", X"33");
io_write(io, X"4", X"44");
io_write(io, X"5", X"55"); -- last byte
end if;
end if;
end loop;
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
entity iec_processor_tb is
end iec_processor_tb;
architecture tb of iec_processor_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal req : t_io_req;
signal resp : t_io_resp;
signal slave_clk_o : std_logic;
signal slave_data_o : std_logic;
signal slave_atn_o : std_logic;
signal srq_o : std_logic;
signal master_clk_o : std_logic;
signal master_data_o : std_logic;
signal master_atn_o : std_logic;
signal iec_clock : std_logic;
signal iec_data : std_logic;
signal iec_atn : std_logic;
signal received : std_logic_vector(7 downto 0);
signal eoi : std_logic;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.iec_processor_io
port map (
clock => clock,
reset => reset,
req => req,
resp => resp,
clk_o => slave_clk_o,
clk_i => iec_clock,
data_o => slave_data_o,
data_i => iec_data,
atn_o => slave_atn_o,
atn_i => iec_atn,
srq_o => srq_o,
srq_i => srq_o );
iec_clock <= '0' when (slave_clk_o='0') or (master_clk_o='0') else 'H';
iec_data <= '0' when (slave_data_o='0') or (master_data_o='0') else 'H';
iec_atn <= '0' when (slave_atn_o='0') or (master_atn_o='0') else 'H';
i_io_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock,
req => req,
resp => resp );
-- i_iec_bfm: entity work.iec_bus_bfm
-- port map (
-- iec_clock => iec_clock,
-- iec_data => iec_data,
-- iec_atn => iec_atn );
process
procedure send_atn_byte(b : std_logic_vector(7 downto 0)) is
begin
master_atn_o <= '0';
wait for 20 us;
master_clk_o <= '0';
wait for 100 us;
master_clk_o <= '1';
if iec_data='0' then
wait until iec_data='H';
end if;
wait for 80 us;
for i in 0 to 7 loop
master_data_o <= b(i);
master_clk_o <= '0';
wait for 60 us;
master_clk_o <= '1';
wait for 60 us;
end loop;
master_data_o <= '1';
master_clk_o <= '0';
wait for 1 us;
if iec_data /= '0' then
wait until iec_data = '0' for 1000 us;
end if;
wait for 20 us;
master_atn_o <= '1';
end procedure;
procedure receive_byte(ret : out std_logic_vector(7 downto 0); eoi : out std_logic) is
variable data : std_logic_vector(7 downto 0);
variable last : std_logic;
begin
last := '0';
master_data_o <= '1'; -- ok, go ahead
wait until iec_clock = '0' for 200 us;
if iec_clock = 'H' then
master_data_o <= '0';
last := '1';
wait for 60 us;
master_data_o <= '1';
if iec_clock /= '0' then
wait until iec_clock = '0';
end if;
end if;
for i in 0 to 7 loop
wait until iec_clock = 'H' for 200 us;
data(i) := iec_data;
end loop;
wait until iec_clock = '0';
master_data_o <= '0'; -- seen it!!
wait for 60 us;
ret := data;
eoi := last;
end procedure;
variable data : std_logic_vector(7 downto 0);
variable last : std_logic;
begin
master_clk_o <= '1';
master_data_o <= '1';
master_atn_o <= '1';
wait for 10 us;
send_atn_byte(X"4A");
send_atn_byte(X"6F");
wait for 50 us;
master_clk_o <= '1'; -- release
master_data_o <= '0'; -- wait, I am not ready!!
wait for 10 us;
wait until iec_clock='H';
wait for 30 us;
receive_byte(data, last);
received <= data;
eoi <= last;
receive_byte(data, last);
received <= data;
eoi <= last;
receive_byte(data, last);
received <= data;
eoi <= last;
wait;
end process;
process
variable io : p_io_bus_bfm_object;
variable stat : std_logic_vector(7 downto 0);
variable data : std_logic_vector(7 downto 0);
begin
wait for 1 us;
bind_io_bus_bfm("io_bfm", io);
while true loop
io_read(io, X"2", stat);
if stat(0)='0' then -- not empty, so data avail
io_read(io, X"6", data);
if stat(7)='1' and data=X"43" then
wait for 400 us;
io_write(io, X"4", X"33");
io_write(io, X"4", X"44");
io_write(io, X"5", X"55"); -- last byte
end if;
end if;
end loop;
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
entity iec_processor_tb is
end iec_processor_tb;
architecture tb of iec_processor_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal req : t_io_req;
signal resp : t_io_resp;
signal slave_clk_o : std_logic;
signal slave_data_o : std_logic;
signal slave_atn_o : std_logic;
signal srq_o : std_logic;
signal master_clk_o : std_logic;
signal master_data_o : std_logic;
signal master_atn_o : std_logic;
signal iec_clock : std_logic;
signal iec_data : std_logic;
signal iec_atn : std_logic;
signal received : std_logic_vector(7 downto 0);
signal eoi : std_logic;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.iec_processor_io
port map (
clock => clock,
reset => reset,
req => req,
resp => resp,
clk_o => slave_clk_o,
clk_i => iec_clock,
data_o => slave_data_o,
data_i => iec_data,
atn_o => slave_atn_o,
atn_i => iec_atn,
srq_o => srq_o,
srq_i => srq_o );
iec_clock <= '0' when (slave_clk_o='0') or (master_clk_o='0') else 'H';
iec_data <= '0' when (slave_data_o='0') or (master_data_o='0') else 'H';
iec_atn <= '0' when (slave_atn_o='0') or (master_atn_o='0') else 'H';
i_io_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock,
req => req,
resp => resp );
-- i_iec_bfm: entity work.iec_bus_bfm
-- port map (
-- iec_clock => iec_clock,
-- iec_data => iec_data,
-- iec_atn => iec_atn );
process
procedure send_atn_byte(b : std_logic_vector(7 downto 0)) is
begin
master_atn_o <= '0';
wait for 20 us;
master_clk_o <= '0';
wait for 100 us;
master_clk_o <= '1';
if iec_data='0' then
wait until iec_data='H';
end if;
wait for 80 us;
for i in 0 to 7 loop
master_data_o <= b(i);
master_clk_o <= '0';
wait for 60 us;
master_clk_o <= '1';
wait for 60 us;
end loop;
master_data_o <= '1';
master_clk_o <= '0';
wait for 1 us;
if iec_data /= '0' then
wait until iec_data = '0' for 1000 us;
end if;
wait for 20 us;
master_atn_o <= '1';
end procedure;
procedure receive_byte(ret : out std_logic_vector(7 downto 0); eoi : out std_logic) is
variable data : std_logic_vector(7 downto 0);
variable last : std_logic;
begin
last := '0';
master_data_o <= '1'; -- ok, go ahead
wait until iec_clock = '0' for 200 us;
if iec_clock = 'H' then
master_data_o <= '0';
last := '1';
wait for 60 us;
master_data_o <= '1';
if iec_clock /= '0' then
wait until iec_clock = '0';
end if;
end if;
for i in 0 to 7 loop
wait until iec_clock = 'H' for 200 us;
data(i) := iec_data;
end loop;
wait until iec_clock = '0';
master_data_o <= '0'; -- seen it!!
wait for 60 us;
ret := data;
eoi := last;
end procedure;
variable data : std_logic_vector(7 downto 0);
variable last : std_logic;
begin
master_clk_o <= '1';
master_data_o <= '1';
master_atn_o <= '1';
wait for 10 us;
send_atn_byte(X"4A");
send_atn_byte(X"6F");
wait for 50 us;
master_clk_o <= '1'; -- release
master_data_o <= '0'; -- wait, I am not ready!!
wait for 10 us;
wait until iec_clock='H';
wait for 30 us;
receive_byte(data, last);
received <= data;
eoi <= last;
receive_byte(data, last);
received <= data;
eoi <= last;
receive_byte(data, last);
received <= data;
eoi <= last;
wait;
end process;
process
variable io : p_io_bus_bfm_object;
variable stat : std_logic_vector(7 downto 0);
variable data : std_logic_vector(7 downto 0);
begin
wait for 1 us;
bind_io_bus_bfm("io_bfm", io);
while true loop
io_read(io, X"2", stat);
if stat(0)='0' then -- not empty, so data avail
io_read(io, X"6", data);
if stat(7)='1' and data=X"43" then
wait for 400 us;
io_write(io, X"4", X"33");
io_write(io, X"4", X"44");
io_write(io, X"5", X"55"); -- last byte
end if;
end if;
end loop;
wait;
end process;
end architecture;
|
--Copyright 2014 by Emmanuel D. Bello <emabello42@gmail.com>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.6
-- \ \ Application :
-- / / Filename : xil_I25VXL
-- /___/ /\ Timestamp : 04/06/2014 00:33:59
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
use work.RetinaParameters.ALL;
entity PairSelector is
port ( clk : in std_logic;
enableIn : in std_logic;
pointSet : in T_POINT_SET;
rst : in std_logic;
enableOut : out std_logic;
point1 : out std_logic_vector(OUT_HORIZ_CONV_BW-1 downto 0);
point2 : out std_logic_vector(OUT_HORIZ_CONV_BW-1 downto 0)
);
end PairSelector;
architecture BEHAVIORAL of PairSelector is
signal s_addr: integer range 0 to 511;
signal s_pointSetAux: T_POINT_SET;
signal s_enableAux: std_logic;
begin
load_points: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
s_pointSetAux <= (others => (others => '0'));
s_enableAux <= '0';
else
if enableIn = '1' then
for i in 0 to 511 loop
s_pointSetAux(i) <= pointSet(i);
end loop;
s_enableAux <= '1';
end if;
end if;
end if;
end process;
select_points: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
s_addr <= 0;
elsif s_enableAux = '1' then
point1 <= std_logic_vector(to_unsigned(ROM_PAIRS(s_addr)(0), point1'length));
point2 <= std_logic_vector(to_unsigned(ROM_PAIRS(s_addr)(1), point2'length));
end if;
enableOut <= s_enableAux;
end if;
end process;
end BEHAVIORAL;
|
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.iec_bus_bfm_pkg.all;
entity tb_cpu_part_1541 is
end tb_cpu_part_1541;
architecture tb of tb_cpu_part_1541 is
signal clock : std_logic := '0';
signal clock_en : std_logic;
signal reset : std_logic;
signal atn_o : std_logic; -- open drain
signal atn_i : std_logic := '1';
signal clk_o : std_logic; -- open drain
signal clk_i : std_logic := '1';
signal data_o : std_logic; -- open drain
signal data_i : std_logic := '1';
signal motor_on : std_logic;
signal mode : std_logic;
signal write_prot_n : std_logic := '1';
signal step : std_logic_vector(1 downto 0);
signal soe : std_logic;
signal rate_ctrl : std_logic_vector(1 downto 0);
signal byte_ready : std_logic := '1';
signal sync : std_logic := '1';
signal drv_rdata : std_logic_vector(7 downto 0) := X"FF";
signal drv_wdata : std_logic_vector(7 downto 0);
signal act_led : std_logic;
signal iec_clock : std_logic;
signal iec_data : std_logic;
signal iec_atn : std_logic;
begin
clock <= not clock after 125 ns;
reset <= '1', '0' after 2 us;
ce: process
begin
clock_en <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
clock_en <= '1';
wait until clock='1';
end process;
mut: entity work.cpu_part_1541
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
-- serial bus pins
atn_o => atn_o, -- open drain
atn_i => atn_i,
clk_o => clk_o, -- open drain
clk_i => clk_i,
data_o => data_o, -- open drain
data_i => data_i,
-- drive pins
power => '1',
drive_select => "00",
motor_on => motor_on,
mode => mode,
write_prot_n => write_prot_n,
step => step,
soe => soe,
rate_ctrl => rate_ctrl,
byte_ready => byte_ready,
sync => sync,
drv_rdata => drv_rdata,
drv_wdata => drv_wdata,
-- other
act_led => act_led );
-- open collector logic
clk_i <= iec_clock and '1';
data_i <= iec_data and '1';
atn_i <= iec_atn and '1';
iec_clock <= '0' when clk_o='0' else 'H';
iec_data <= '0' when data_o='0' else 'H';
iec_atn <= '0' when atn_o='0' else 'H';
iec_bfm: entity work.iec_bus_bfm
port map (
iec_clock => iec_clock,
iec_data => iec_data,
iec_atn => iec_atn );
test: process
variable bfm : p_iec_bus_bfm_object;
variable msg : t_iec_message;
begin
bind_iec_bus_bfm(":tb_cpu_part_1541:iec_bfm:", bfm);
-- wait for 1250 ms; -- unpatched ROM
wait for 30 ms; -- patched ROM
iec_send_atn(bfm, X"48"); -- Drive 8, Talk, I will listen
iec_send_atn(bfm, X"6F"); -- Open channel 15
iec_turnaround(bfm); -- start to listen
iec_get_message(bfm, msg);
iec_print_message(msg);
wait;
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.iec_bus_bfm_pkg.all;
entity tb_cpu_part_1541 is
end tb_cpu_part_1541;
architecture tb of tb_cpu_part_1541 is
signal clock : std_logic := '0';
signal clock_en : std_logic;
signal reset : std_logic;
signal atn_o : std_logic; -- open drain
signal atn_i : std_logic := '1';
signal clk_o : std_logic; -- open drain
signal clk_i : std_logic := '1';
signal data_o : std_logic; -- open drain
signal data_i : std_logic := '1';
signal motor_on : std_logic;
signal mode : std_logic;
signal write_prot_n : std_logic := '1';
signal step : std_logic_vector(1 downto 0);
signal soe : std_logic;
signal rate_ctrl : std_logic_vector(1 downto 0);
signal byte_ready : std_logic := '1';
signal sync : std_logic := '1';
signal drv_rdata : std_logic_vector(7 downto 0) := X"FF";
signal drv_wdata : std_logic_vector(7 downto 0);
signal act_led : std_logic;
signal iec_clock : std_logic;
signal iec_data : std_logic;
signal iec_atn : std_logic;
begin
clock <= not clock after 125 ns;
reset <= '1', '0' after 2 us;
ce: process
begin
clock_en <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
clock_en <= '1';
wait until clock='1';
end process;
mut: entity work.cpu_part_1541
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
-- serial bus pins
atn_o => atn_o, -- open drain
atn_i => atn_i,
clk_o => clk_o, -- open drain
clk_i => clk_i,
data_o => data_o, -- open drain
data_i => data_i,
-- drive pins
power => '1',
drive_select => "00",
motor_on => motor_on,
mode => mode,
write_prot_n => write_prot_n,
step => step,
soe => soe,
rate_ctrl => rate_ctrl,
byte_ready => byte_ready,
sync => sync,
drv_rdata => drv_rdata,
drv_wdata => drv_wdata,
-- other
act_led => act_led );
-- open collector logic
clk_i <= iec_clock and '1';
data_i <= iec_data and '1';
atn_i <= iec_atn and '1';
iec_clock <= '0' when clk_o='0' else 'H';
iec_data <= '0' when data_o='0' else 'H';
iec_atn <= '0' when atn_o='0' else 'H';
iec_bfm: entity work.iec_bus_bfm
port map (
iec_clock => iec_clock,
iec_data => iec_data,
iec_atn => iec_atn );
test: process
variable bfm : p_iec_bus_bfm_object;
variable msg : t_iec_message;
begin
bind_iec_bus_bfm(":tb_cpu_part_1541:iec_bfm:", bfm);
-- wait for 1250 ms; -- unpatched ROM
wait for 30 ms; -- patched ROM
iec_send_atn(bfm, X"48"); -- Drive 8, Talk, I will listen
iec_send_atn(bfm, X"6F"); -- Open channel 15
iec_turnaround(bfm); -- start to listen
iec_get_message(bfm, msg);
iec_print_message(msg);
wait;
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.iec_bus_bfm_pkg.all;
entity tb_cpu_part_1541 is
end tb_cpu_part_1541;
architecture tb of tb_cpu_part_1541 is
signal clock : std_logic := '0';
signal clock_en : std_logic;
signal reset : std_logic;
signal atn_o : std_logic; -- open drain
signal atn_i : std_logic := '1';
signal clk_o : std_logic; -- open drain
signal clk_i : std_logic := '1';
signal data_o : std_logic; -- open drain
signal data_i : std_logic := '1';
signal motor_on : std_logic;
signal mode : std_logic;
signal write_prot_n : std_logic := '1';
signal step : std_logic_vector(1 downto 0);
signal soe : std_logic;
signal rate_ctrl : std_logic_vector(1 downto 0);
signal byte_ready : std_logic := '1';
signal sync : std_logic := '1';
signal drv_rdata : std_logic_vector(7 downto 0) := X"FF";
signal drv_wdata : std_logic_vector(7 downto 0);
signal act_led : std_logic;
signal iec_clock : std_logic;
signal iec_data : std_logic;
signal iec_atn : std_logic;
begin
clock <= not clock after 125 ns;
reset <= '1', '0' after 2 us;
ce: process
begin
clock_en <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
clock_en <= '1';
wait until clock='1';
end process;
mut: entity work.cpu_part_1541
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
-- serial bus pins
atn_o => atn_o, -- open drain
atn_i => atn_i,
clk_o => clk_o, -- open drain
clk_i => clk_i,
data_o => data_o, -- open drain
data_i => data_i,
-- drive pins
power => '1',
drive_select => "00",
motor_on => motor_on,
mode => mode,
write_prot_n => write_prot_n,
step => step,
soe => soe,
rate_ctrl => rate_ctrl,
byte_ready => byte_ready,
sync => sync,
drv_rdata => drv_rdata,
drv_wdata => drv_wdata,
-- other
act_led => act_led );
-- open collector logic
clk_i <= iec_clock and '1';
data_i <= iec_data and '1';
atn_i <= iec_atn and '1';
iec_clock <= '0' when clk_o='0' else 'H';
iec_data <= '0' when data_o='0' else 'H';
iec_atn <= '0' when atn_o='0' else 'H';
iec_bfm: entity work.iec_bus_bfm
port map (
iec_clock => iec_clock,
iec_data => iec_data,
iec_atn => iec_atn );
test: process
variable bfm : p_iec_bus_bfm_object;
variable msg : t_iec_message;
begin
bind_iec_bus_bfm(":tb_cpu_part_1541:iec_bfm:", bfm);
-- wait for 1250 ms; -- unpatched ROM
wait for 30 ms; -- patched ROM
iec_send_atn(bfm, X"48"); -- Drive 8, Talk, I will listen
iec_send_atn(bfm, X"6F"); -- Open channel 15
iec_turnaround(bfm); -- start to listen
iec_get_message(bfm, msg);
iec_print_message(msg);
wait;
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.iec_bus_bfm_pkg.all;
entity tb_cpu_part_1541 is
end tb_cpu_part_1541;
architecture tb of tb_cpu_part_1541 is
signal clock : std_logic := '0';
signal clock_en : std_logic;
signal reset : std_logic;
signal atn_o : std_logic; -- open drain
signal atn_i : std_logic := '1';
signal clk_o : std_logic; -- open drain
signal clk_i : std_logic := '1';
signal data_o : std_logic; -- open drain
signal data_i : std_logic := '1';
signal motor_on : std_logic;
signal mode : std_logic;
signal write_prot_n : std_logic := '1';
signal step : std_logic_vector(1 downto 0);
signal soe : std_logic;
signal rate_ctrl : std_logic_vector(1 downto 0);
signal byte_ready : std_logic := '1';
signal sync : std_logic := '1';
signal drv_rdata : std_logic_vector(7 downto 0) := X"FF";
signal drv_wdata : std_logic_vector(7 downto 0);
signal act_led : std_logic;
signal iec_clock : std_logic;
signal iec_data : std_logic;
signal iec_atn : std_logic;
begin
clock <= not clock after 125 ns;
reset <= '1', '0' after 2 us;
ce: process
begin
clock_en <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
clock_en <= '1';
wait until clock='1';
end process;
mut: entity work.cpu_part_1541
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
-- serial bus pins
atn_o => atn_o, -- open drain
atn_i => atn_i,
clk_o => clk_o, -- open drain
clk_i => clk_i,
data_o => data_o, -- open drain
data_i => data_i,
-- drive pins
power => '1',
drive_select => "00",
motor_on => motor_on,
mode => mode,
write_prot_n => write_prot_n,
step => step,
soe => soe,
rate_ctrl => rate_ctrl,
byte_ready => byte_ready,
sync => sync,
drv_rdata => drv_rdata,
drv_wdata => drv_wdata,
-- other
act_led => act_led );
-- open collector logic
clk_i <= iec_clock and '1';
data_i <= iec_data and '1';
atn_i <= iec_atn and '1';
iec_clock <= '0' when clk_o='0' else 'H';
iec_data <= '0' when data_o='0' else 'H';
iec_atn <= '0' when atn_o='0' else 'H';
iec_bfm: entity work.iec_bus_bfm
port map (
iec_clock => iec_clock,
iec_data => iec_data,
iec_atn => iec_atn );
test: process
variable bfm : p_iec_bus_bfm_object;
variable msg : t_iec_message;
begin
bind_iec_bus_bfm(":tb_cpu_part_1541:iec_bfm:", bfm);
-- wait for 1250 ms; -- unpatched ROM
wait for 30 ms; -- patched ROM
iec_send_atn(bfm, X"48"); -- Drive 8, Talk, I will listen
iec_send_atn(bfm, X"6F"); -- Open channel 15
iec_turnaround(bfm); -- start to listen
iec_get_message(bfm, msg);
iec_print_message(msg);
wait;
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.iec_bus_bfm_pkg.all;
entity tb_cpu_part_1541 is
end tb_cpu_part_1541;
architecture tb of tb_cpu_part_1541 is
signal clock : std_logic := '0';
signal clock_en : std_logic;
signal reset : std_logic;
signal atn_o : std_logic; -- open drain
signal atn_i : std_logic := '1';
signal clk_o : std_logic; -- open drain
signal clk_i : std_logic := '1';
signal data_o : std_logic; -- open drain
signal data_i : std_logic := '1';
signal motor_on : std_logic;
signal mode : std_logic;
signal write_prot_n : std_logic := '1';
signal step : std_logic_vector(1 downto 0);
signal soe : std_logic;
signal rate_ctrl : std_logic_vector(1 downto 0);
signal byte_ready : std_logic := '1';
signal sync : std_logic := '1';
signal drv_rdata : std_logic_vector(7 downto 0) := X"FF";
signal drv_wdata : std_logic_vector(7 downto 0);
signal act_led : std_logic;
signal iec_clock : std_logic;
signal iec_data : std_logic;
signal iec_atn : std_logic;
begin
clock <= not clock after 125 ns;
reset <= '1', '0' after 2 us;
ce: process
begin
clock_en <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
clock_en <= '1';
wait until clock='1';
end process;
mut: entity work.cpu_part_1541
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
-- serial bus pins
atn_o => atn_o, -- open drain
atn_i => atn_i,
clk_o => clk_o, -- open drain
clk_i => clk_i,
data_o => data_o, -- open drain
data_i => data_i,
-- drive pins
power => '1',
drive_select => "00",
motor_on => motor_on,
mode => mode,
write_prot_n => write_prot_n,
step => step,
soe => soe,
rate_ctrl => rate_ctrl,
byte_ready => byte_ready,
sync => sync,
drv_rdata => drv_rdata,
drv_wdata => drv_wdata,
-- other
act_led => act_led );
-- open collector logic
clk_i <= iec_clock and '1';
data_i <= iec_data and '1';
atn_i <= iec_atn and '1';
iec_clock <= '0' when clk_o='0' else 'H';
iec_data <= '0' when data_o='0' else 'H';
iec_atn <= '0' when atn_o='0' else 'H';
iec_bfm: entity work.iec_bus_bfm
port map (
iec_clock => iec_clock,
iec_data => iec_data,
iec_atn => iec_atn );
test: process
variable bfm : p_iec_bus_bfm_object;
variable msg : t_iec_message;
begin
bind_iec_bus_bfm(":tb_cpu_part_1541:iec_bfm:", bfm);
-- wait for 1250 ms; -- unpatched ROM
wait for 30 ms; -- patched ROM
iec_send_atn(bfm, X"48"); -- Drive 8, Talk, I will listen
iec_send_atn(bfm, X"6F"); -- Open channel 15
iec_turnaround(bfm); -- start to listen
iec_get_message(bfm, msg);
iec_print_message(msg);
wait;
end process;
end tb;
|
-- $Id: gen_crc8_tbl.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: gen_crc8_tbl - sim
-- Description: stand-alone program to print crc8 transition table
--
-- Dependencies: comlib/crc8_update (function)
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-17 410 1.1 now numeric_std clean; use function crc8_update
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-07-08 65 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.slvtypes.all;
use work.comlib.all;
entity gen_crc8_tbl is
end gen_crc8_tbl;
architecture sim of gen_crc8_tbl is
begin
process
variable crc : slv8 := (others=>'0');
variable dat : slv8 := (others=>'0');
variable nxt : slv8 := (others=>'0');
variable oline : line;
begin
for i in 0 to 255 loop
crc := (others=>'0');
dat := slv(to_unsigned(i,8));
nxt := crc8_update(crc, dat);
write(oline, to_integer(unsigned(nxt)), right, 4);
if i /= 255 then
write(oline, string'(","));
end if;
if (i mod 8) = 7 then
writeline(output, oline);
end if;
end loop; -- i
wait;
end process;
end sim;
|
-- $Id: gen_crc8_tbl.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: gen_crc8_tbl - sim
-- Description: stand-alone program to print crc8 transition table
--
-- Dependencies: comlib/crc8_update (function)
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-17 410 1.1 now numeric_std clean; use function crc8_update
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-07-08 65 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.slvtypes.all;
use work.comlib.all;
entity gen_crc8_tbl is
end gen_crc8_tbl;
architecture sim of gen_crc8_tbl is
begin
process
variable crc : slv8 := (others=>'0');
variable dat : slv8 := (others=>'0');
variable nxt : slv8 := (others=>'0');
variable oline : line;
begin
for i in 0 to 255 loop
crc := (others=>'0');
dat := slv(to_unsigned(i,8));
nxt := crc8_update(crc, dat);
write(oline, to_integer(unsigned(nxt)), right, 4);
if i /= 255 then
write(oline, string'(","));
end if;
if (i mod 8) = 7 then
writeline(output, oline);
end if;
end loop; -- i
wait;
end process;
end sim;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Fri Sep 22 23:00:45 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_xbar_1_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_xbar_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_sasd is
port (
m_valid_i : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
aa_grant_rnw : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\m_atarget_hot_reg[2]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 34 downto 0 );
\m_atarget_hot_reg[2]_0\ : out STD_LOGIC;
\m_atarget_hot_reg[3]\ : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\m_ready_d_reg[2]\ : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 2 downto 0 );
\m_ready_d_reg[2]_0\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d0 : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_no_arbiter.m_grant_hot_i_reg[0]_0\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_axilite.s_axi_rvalid_i_reg\ : out STD_LOGIC;
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axilite.s_axi_awready_i_reg\ : out STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
aresetn_d : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_atarget_enc_reg[0]\ : in STD_LOGIC;
\gen_axilite.s_axi_bvalid_i_reg\ : in STD_LOGIC;
\m_atarget_hot_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axilite.s_axi_awready_i_reg_0\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg_0 : in STD_LOGIC;
\gen_axilite.s_axi_arready_i_reg\ : in STD_LOGIC;
m_ready_d_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
aa_rready : in STD_LOGIC;
\gen_axilite.s_axi_rvalid_i_reg_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
sr_rvalid : in STD_LOGIC;
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\m_ready_d_reg[2]_1\ : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
mi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
mi_wready : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_sasd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_sasd is
signal \^q\ : STD_LOGIC_VECTOR ( 34 downto 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal aa_grant_any : STD_LOGIC;
signal \^aa_grant_rnw\ : STD_LOGIC;
signal \gen_axilite.s_axi_awready_i_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.grant_rnw_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_grant_hot_i[0]_i_5_n_0\ : STD_LOGIC;
signal \^gen_no_arbiter.m_grant_hot_i_reg[0]_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_1_n_0\ : STD_LOGIC;
signal \m_atarget_hot[3]_i_5_n_0\ : STD_LOGIC;
signal \^m_atarget_hot_reg[2]\ : STD_LOGIC;
signal \^m_atarget_hot_reg[2]_0\ : STD_LOGIC;
signal \^m_atarget_hot_reg[3]\ : STD_LOGIC;
signal \^m_ready_d0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_valid_i\ : STD_LOGIC;
signal m_valid_i_i_2_n_0 : STD_LOGIC;
signal m_valid_i_i_3_n_0 : STD_LOGIC;
signal p_0_in1_in : STD_LOGIC;
signal s_amesg : STD_LOGIC_VECTOR ( 48 downto 1 );
signal \s_arvalid_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \s_arvalid_reg_reg_n_0_[0]\ : STD_LOGIC;
signal s_awvalid_reg : STD_LOGIC;
signal \s_awvalid_reg[0]_i_1_n_0\ : STD_LOGIC;
signal s_ready_i : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axilite.s_axi_awready_i_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_axilite.s_axi_rvalid_i_i_2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_grant_hot_i[0]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_grant_hot_i[0]_i_3\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_grant_hot_i[0]_i_5\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_atarget_hot[0]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_atarget_hot[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_atarget_hot[2]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \m_atarget_hot[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_axi_arvalid[1]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_axi_arvalid[2]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_axi_awvalid[1]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_axi_awvalid[2]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_axi_bready[0]_INST_0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_axi_wvalid[2]_INST_0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \m_ready_d[2]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_ready_d[2]_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \m_ready_d[2]_i_4\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of m_valid_i_i_1 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of m_valid_i_i_3 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \s_arvalid_reg[0]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of s_ready_i_i_1 : label is "soft_lutpair13";
begin
Q(34 downto 0) <= \^q\(34 downto 0);
SR(0) <= \^sr\(0);
aa_grant_rnw <= \^aa_grant_rnw\;
\gen_no_arbiter.m_grant_hot_i_reg[0]_0\ <= \^gen_no_arbiter.m_grant_hot_i_reg[0]_0\;
\m_atarget_hot_reg[2]\ <= \^m_atarget_hot_reg[2]\;
\m_atarget_hot_reg[2]_0\ <= \^m_atarget_hot_reg[2]_0\;
\m_atarget_hot_reg[3]\ <= \^m_atarget_hot_reg[3]\;
m_ready_d0(0) <= \^m_ready_d0\(0);
m_valid_i <= \^m_valid_i\;
\gen_axilite.s_axi_awready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFB00000004"
)
port map (
I0 => \gen_axilite.s_axi_awready_i_i_2_n_0\,
I1 => \m_atarget_hot_reg[3]_0\(3),
I2 => m_ready_d(2),
I3 => \^gen_no_arbiter.m_grant_hot_i_reg[0]_0\,
I4 => mi_bvalid(0),
I5 => mi_wready(0),
O => \gen_axilite.s_axi_awready_i_reg\
);
\gen_axilite.s_axi_awready_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FBFF"
)
port map (
I0 => \^aa_grant_rnw\,
I1 => \^m_valid_i\,
I2 => m_ready_d(1),
I3 => s_axi_wvalid(0),
O => \gen_axilite.s_axi_awready_i_i_2_n_0\
);
\gen_axilite.s_axi_rvalid_i_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => m_ready_d_0(1),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
O => \gen_axilite.s_axi_rvalid_i_reg\
);
\gen_no_arbiter.grant_rnw_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF5300000050"
)
port map (
I0 => s_awvalid_reg,
I1 => s_axi_awvalid(0),
I2 => s_axi_arvalid(0),
I3 => aa_grant_any,
I4 => \^m_valid_i\,
I5 => \^aa_grant_rnw\,
O => \gen_no_arbiter.grant_rnw_i_1_n_0\
);
\gen_no_arbiter.grant_rnw_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.grant_rnw_i_1_n_0\,
Q => \^aa_grant_rnw\,
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(9),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(9),
O => s_amesg(10)
);
\gen_no_arbiter.m_amesg_i[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(10),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(10),
O => s_amesg(11)
);
\gen_no_arbiter.m_amesg_i[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(11),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(11),
O => s_amesg(12)
);
\gen_no_arbiter.m_amesg_i[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(12),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(12),
O => s_amesg(13)
);
\gen_no_arbiter.m_amesg_i[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(13),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(13),
O => s_amesg(14)
);
\gen_no_arbiter.m_amesg_i[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(14),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(14),
O => s_amesg(15)
);
\gen_no_arbiter.m_amesg_i[16]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(15),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(15),
O => s_amesg(16)
);
\gen_no_arbiter.m_amesg_i[17]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(16),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(16),
O => s_amesg(17)
);
\gen_no_arbiter.m_amesg_i[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(17),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(17),
O => s_amesg(18)
);
\gen_no_arbiter.m_amesg_i[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(18),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(18),
O => s_amesg(19)
);
\gen_no_arbiter.m_amesg_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(0),
O => s_amesg(1)
);
\gen_no_arbiter.m_amesg_i[20]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(19),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(19),
O => s_amesg(20)
);
\gen_no_arbiter.m_amesg_i[21]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(20),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(20),
O => s_amesg(21)
);
\gen_no_arbiter.m_amesg_i[22]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(21),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(21),
O => s_amesg(22)
);
\gen_no_arbiter.m_amesg_i[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(22),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(22),
O => s_amesg(23)
);
\gen_no_arbiter.m_amesg_i[24]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(23),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(23),
O => s_amesg(24)
);
\gen_no_arbiter.m_amesg_i[25]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(24),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(24),
O => s_amesg(25)
);
\gen_no_arbiter.m_amesg_i[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(25),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(25),
O => s_amesg(26)
);
\gen_no_arbiter.m_amesg_i[27]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(26),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(26),
O => s_amesg(27)
);
\gen_no_arbiter.m_amesg_i[28]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(27),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(27),
O => s_amesg(28)
);
\gen_no_arbiter.m_amesg_i[29]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(28),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(28),
O => s_amesg(29)
);
\gen_no_arbiter.m_amesg_i[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(1),
O => s_amesg(2)
);
\gen_no_arbiter.m_amesg_i[30]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(29),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(29),
O => s_amesg(30)
);
\gen_no_arbiter.m_amesg_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(30),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(30),
O => s_amesg(31)
);
\gen_no_arbiter.m_amesg_i[32]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn_d,
O => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i[32]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aa_grant_any,
O => p_0_in1_in
);
\gen_no_arbiter.m_amesg_i[32]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(31),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(31),
O => s_amesg(32)
);
\gen_no_arbiter.m_amesg_i[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(2),
O => s_amesg(3)
);
\gen_no_arbiter.m_amesg_i[46]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arprot(0),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awprot(0),
O => s_amesg(46)
);
\gen_no_arbiter.m_amesg_i[47]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arprot(1),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awprot(1),
O => s_amesg(47)
);
\gen_no_arbiter.m_amesg_i[48]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_arprot(2),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awprot(2),
O => s_amesg(48)
);
\gen_no_arbiter.m_amesg_i[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(3),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(3),
O => s_amesg(4)
);
\gen_no_arbiter.m_amesg_i[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(4),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(4),
O => s_amesg(5)
);
\gen_no_arbiter.m_amesg_i[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(5),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(5),
O => s_amesg(6)
);
\gen_no_arbiter.m_amesg_i[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(6),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(6),
O => s_amesg(7)
);
\gen_no_arbiter.m_amesg_i[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(7),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(7),
O => s_amesg(8)
);
\gen_no_arbiter.m_amesg_i[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(8),
I1 => s_axi_arvalid(0),
I2 => s_awvalid_reg,
I3 => s_axi_awaddr(8),
O => s_amesg(9)
);
\gen_no_arbiter.m_amesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(10),
Q => \^q\(9),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(11),
Q => \^q\(10),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(12),
Q => \^q\(11),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(13),
Q => \^q\(12),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(14),
Q => \^q\(13),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(15),
Q => \^q\(14),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(16),
Q => \^q\(15),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(17),
Q => \^q\(16),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(18),
Q => \^q\(17),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(19),
Q => \^q\(18),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(1),
Q => \^q\(0),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(20),
Q => \^q\(19),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(21),
Q => \^q\(20),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(22),
Q => \^q\(21),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(23),
Q => \^q\(22),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(24),
Q => \^q\(23),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(25),
Q => \^q\(24),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(26),
Q => \^q\(25),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(27),
Q => \^q\(26),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(28),
Q => \^q\(27),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(29),
Q => \^q\(28),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(2),
Q => \^q\(1),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(30),
Q => \^q\(29),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(31),
Q => \^q\(30),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(32),
Q => \^q\(31),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(3),
Q => \^q\(2),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(46),
Q => \^q\(32),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(47),
Q => \^q\(33),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(48),
Q => \^q\(34),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(4),
Q => \^q\(3),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(5),
Q => \^q\(4),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(6),
Q => \^q\(5),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(7),
Q => \^q\(6),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(8),
Q => \^q\(7),
R => \^sr\(0)
);
\gen_no_arbiter.m_amesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_0_in1_in,
D => s_amesg(9),
Q => \^q\(8),
R => \^sr\(0)
);
\gen_no_arbiter.m_grant_hot_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000088888088"
)
port map (
I0 => \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\,
I1 => aresetn_d,
I2 => \^gen_no_arbiter.m_grant_hot_i_reg[0]_0\,
I3 => \^m_ready_d0\(0),
I4 => \m_ready_d_reg[2]_1\,
I5 => \gen_no_arbiter.m_grant_hot_i[0]_i_5_n_0\,
O => \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0\
);
\gen_no_arbiter.m_grant_hot_i[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F0FE"
)
port map (
I0 => s_axi_awvalid(0),
I1 => s_axi_arvalid(0),
I2 => aa_grant_any,
I3 => \^m_valid_i\,
O => \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0\
);
\gen_no_arbiter.m_grant_hot_i[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^aa_grant_rnw\,
I1 => \^m_valid_i\,
O => \^gen_no_arbiter.m_grant_hot_i_reg[0]_0\
);
\gen_no_arbiter.m_grant_hot_i[0]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"51000000"
)
port map (
I0 => m_valid_i_reg_0,
I1 => \gen_axilite.s_axi_arready_i_reg\,
I2 => m_ready_d_0(1),
I3 => \^m_valid_i\,
I4 => \^aa_grant_rnw\,
O => \gen_no_arbiter.m_grant_hot_i[0]_i_5_n_0\
);
\gen_no_arbiter.m_grant_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0\,
Q => aa_grant_any,
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3AFA3A0A3AFA3AFA"
)
port map (
I0 => aa_grant_any,
I1 => \gen_no_arbiter.m_valid_i_i_2_n_0\,
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => \m_ready_d_reg[2]_1\,
I5 => \^m_ready_d0\(0),
O => \gen_no_arbiter.m_valid_i_i_1_n_0\
);
\gen_no_arbiter.m_valid_i_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000F0F8"
)
port map (
I0 => \^aa_grant_rnw\,
I1 => \^m_valid_i\,
I2 => m_ready_d_0(1),
I3 => \gen_axilite.s_axi_arready_i_reg\,
I4 => m_valid_i_reg_0,
O => \gen_no_arbiter.m_valid_i_i_2_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1_n_0\,
Q => \^m_valid_i\,
R => \^sr\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^m_valid_i\,
I1 => aa_grant_any,
I2 => aresetn_d,
O => \gen_no_arbiter.s_ready_i[0]_i_1_n_0\
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.s_ready_i[0]_i_1_n_0\,
Q => s_ready_i,
R => '0'
);
\m_atarget_hot[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => \^m_atarget_hot_reg[2]_0\,
I1 => \^q\(16),
I2 => aa_grant_any,
I3 => \^m_atarget_hot_reg[3]\,
O => D(0)
);
\m_atarget_hot[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0400"
)
port map (
I0 => \^m_atarget_hot_reg[3]\,
I1 => \^q\(16),
I2 => \^m_atarget_hot_reg[2]_0\,
I3 => aa_grant_any,
O => D(1)
);
\m_atarget_hot[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0100"
)
port map (
I0 => \^m_atarget_hot_reg[2]\,
I1 => \^q\(16),
I2 => \^m_atarget_hot_reg[2]_0\,
I3 => aa_grant_any,
O => D(2)
);
\m_atarget_hot[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEAA0000"
)
port map (
I0 => \^m_atarget_hot_reg[2]_0\,
I1 => \^q\(16),
I2 => \^m_atarget_hot_reg[2]\,
I3 => \^m_atarget_hot_reg[3]\,
I4 => aa_grant_any,
O => D(3)
);
\m_atarget_hot[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(26),
I1 => \^q\(27),
I2 => \^q\(29),
I3 => \m_atarget_hot[3]_i_5_n_0\,
O => \^m_atarget_hot_reg[2]_0\
);
\m_atarget_hot[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFFFFFFFFF"
)
port map (
I0 => \^q\(20),
I1 => \^q\(24),
I2 => \^q\(21),
I3 => \^q\(22),
I4 => \^q\(23),
I5 => \^q\(25),
O => \^m_atarget_hot_reg[2]\
);
\m_atarget_hot[3]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF7"
)
port map (
I0 => \^q\(21),
I1 => \^q\(24),
I2 => \^q\(20),
I3 => \^q\(23),
I4 => \^q\(22),
I5 => \^q\(25),
O => \^m_atarget_hot_reg[3]\
);
\m_atarget_hot[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEFFFFFFFF"
)
port map (
I0 => \^q\(31),
I1 => \^q\(28),
I2 => \^q\(18),
I3 => \^q\(19),
I4 => \^q\(17),
I5 => \^q\(30),
O => \m_atarget_hot[3]_i_5_n_0\
);
\m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[3]_0\(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(1),
O => m_axi_arvalid(0)
);
\m_axi_arvalid[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[3]_0\(1),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(1),
O => m_axi_arvalid(1)
);
\m_axi_arvalid[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \m_atarget_hot_reg[3]_0\(2),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(1),
O => m_axi_arvalid(2)
);
\m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[3]_0\(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(0)
);
\m_axi_awvalid[1]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[3]_0\(1),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(1)
);
\m_axi_awvalid[2]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \m_atarget_hot_reg[3]_0\(2),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(2),
O => m_axi_awvalid(2)
);
\m_axi_bready[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[3]_0\(0),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(0)
);
\m_axi_bready[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[3]_0\(1),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(1)
);
\m_axi_bready[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => \m_atarget_hot_reg[3]_0\(2),
I1 => m_ready_d(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_bready(0),
O => m_axi_bready(2)
);
\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000800"
)
port map (
I0 => \m_atarget_hot_reg[3]_0\(0),
I1 => s_axi_wvalid(0),
I2 => m_ready_d(1),
I3 => \^m_valid_i\,
I4 => \^aa_grant_rnw\,
O => m_axi_wvalid(0)
);
\m_axi_wvalid[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000800"
)
port map (
I0 => \m_atarget_hot_reg[3]_0\(1),
I1 => s_axi_wvalid(0),
I2 => m_ready_d(1),
I3 => \^m_valid_i\,
I4 => \^aa_grant_rnw\,
O => m_axi_wvalid(1)
);
\m_axi_wvalid[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000800"
)
port map (
I0 => \m_atarget_hot_reg[3]_0\(2),
I1 => s_axi_wvalid(0),
I2 => m_ready_d(1),
I3 => \^m_valid_i\,
I4 => \^aa_grant_rnw\,
O => m_axi_wvalid(2)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0080FFFF"
)
port map (
I0 => s_axi_rready(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d_0(0),
I4 => sr_rvalid,
O => E(0)
);
\m_ready_d[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0F4F0F0"
)
port map (
I0 => \^aa_grant_rnw\,
I1 => \^m_valid_i\,
I2 => m_ready_d(1),
I3 => \gen_axilite.s_axi_awready_i_reg_0\,
I4 => s_axi_wvalid(0),
O => \^m_ready_d0\(0)
);
\m_ready_d[2]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => s_axi_bready(0),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => m_ready_d(0),
O => \m_ready_d_reg[2]_0\
);
\m_ready_d[2]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"4555"
)
port map (
I0 => m_ready_d(2),
I1 => \^aa_grant_rnw\,
I2 => \^m_valid_i\,
I3 => \m_atarget_enc_reg[0]\,
O => \m_ready_d_reg[2]\
);
m_valid_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"A2"
)
port map (
I0 => \aresetn_d_reg[1]\(1),
I1 => m_valid_i_i_2_n_0,
I2 => m_valid_i_i_3_n_0,
O => m_valid_i_reg
);
m_valid_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"8AAAAAAA"
)
port map (
I0 => aa_rready,
I1 => m_ready_d_0(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => \gen_axilite.s_axi_rvalid_i_reg_0\,
O => m_valid_i_i_2_n_0
);
m_valid_i_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"8AAAAAAA"
)
port map (
I0 => sr_rvalid,
I1 => m_ready_d_0(0),
I2 => \^m_valid_i\,
I3 => \^aa_grant_rnw\,
I4 => s_axi_rready(0),
O => m_valid_i_i_3_n_0
);
\s_arvalid_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => s_awvalid_reg,
I1 => s_axi_arvalid(0),
I2 => aresetn_d,
I3 => s_ready_i,
O => \s_arvalid_reg[0]_i_1_n_0\
);
\s_arvalid_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_arvalid_reg[0]_i_1_n_0\,
Q => \s_arvalid_reg_reg_n_0_[0]\,
R => '0'
);
\s_awvalid_reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000D00000"
)
port map (
I0 => s_axi_arvalid(0),
I1 => s_awvalid_reg,
I2 => s_axi_awvalid(0),
I3 => \s_arvalid_reg_reg_n_0_[0]\,
I4 => aresetn_d,
I5 => s_ready_i,
O => \s_awvalid_reg[0]_i_1_n_0\
);
\s_awvalid_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_awvalid_reg[0]_i_1_n_0\,
Q => s_awvalid_reg,
R => '0'
);
\s_axi_arready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_ready_i,
I1 => \^aa_grant_rnw\,
O => s_axi_arready(0)
);
\s_axi_awready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_ready_i,
I1 => \^aa_grant_rnw\,
O => s_axi_awready(0)
);
\s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000400"
)
port map (
I0 => m_ready_d(0),
I1 => \^m_valid_i\,
I2 => \^aa_grant_rnw\,
I3 => aa_grant_any,
I4 => \gen_axilite.s_axi_bvalid_i_reg\,
O => s_axi_bvalid(0)
);
\s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_grant_any,
I1 => sr_rvalid,
O => s_axi_rvalid(0)
);
\s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000200"
)
port map (
I0 => aa_grant_any,
I1 => \gen_axilite.s_axi_awready_i_reg_0\,
I2 => m_ready_d(1),
I3 => \^m_valid_i\,
I4 => \^aa_grant_rnw\,
O => s_axi_wready(0)
);
s_ready_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"A2"
)
port map (
I0 => \aresetn_d_reg[1]\(0),
I1 => m_valid_i_i_3_n_0,
I2 => m_valid_i_i_2_n_0,
O => s_ready_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave is
port (
mi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
mi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_grant_hot_i_reg[0]\ : out STD_LOGIC;
\gen_no_arbiter.m_grant_hot_i_reg[0]_0\ : out STD_LOGIC;
\m_ready_d_reg[2]\ : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\gen_no_arbiter.m_grant_hot_i_reg[0]_1\ : out STD_LOGIC;
\m_ready_d_reg[1]\ : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
\m_atarget_hot_reg[3]\ : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_no_arbiter.grant_rnw_reg\ : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_atarget_hot_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.grant_rnw_reg_0\ : in STD_LOGIC;
\m_ready_d_reg[1]_0\ : in STD_LOGIC;
\m_ready_d_reg[1]_1\ : in STD_LOGIC;
aa_rready : in STD_LOGIC;
aresetn_d : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave is
signal \gen_axilite.s_axi_arready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axilite.s_axi_bvalid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axilite.s_axi_rvalid_i_i_1_n_0\ : STD_LOGIC;
signal \^gen_no_arbiter.m_grant_hot_i_reg[0]_0\ : STD_LOGIC;
signal \^m_ready_d_reg[2]\ : STD_LOGIC;
signal mi_arready : STD_LOGIC_VECTOR ( 3 to 3 );
signal \^mi_bvalid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal mi_rvalid : STD_LOGIC_VECTOR ( 3 to 3 );
signal \^mi_wready\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
\gen_no_arbiter.m_grant_hot_i_reg[0]_0\ <= \^gen_no_arbiter.m_grant_hot_i_reg[0]_0\;
\m_ready_d_reg[2]\ <= \^m_ready_d_reg[2]\;
mi_bvalid(0) <= \^mi_bvalid\(0);
mi_wready(0) <= \^mi_wready\(0);
\gen_axilite.s_axi_arready_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA2A00AA"
)
port map (
I0 => aresetn_d,
I1 => \m_ready_d_reg[1]_1\,
I2 => \m_atarget_hot_reg[3]_0\(0),
I3 => mi_rvalid(3),
I4 => mi_arready(3),
O => \gen_axilite.s_axi_arready_i_i_1_n_0\
);
\gen_axilite.s_axi_arready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axilite.s_axi_arready_i_i_1_n_0\,
Q => mi_arready(3),
R => '0'
);
\gen_axilite.s_axi_awready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_atarget_hot_reg[3]\,
Q => \^mi_wready\(0),
R => SR(0)
);
\gen_axilite.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"77770F00"
)
port map (
I0 => \m_atarget_hot_reg[3]_0\(0),
I1 => \gen_no_arbiter.grant_rnw_reg_0\,
I2 => \m_ready_d_reg[1]_0\,
I3 => \^mi_wready\(0),
I4 => \^mi_bvalid\(0),
O => \gen_axilite.s_axi_bvalid_i_i_1_n_0\
);
\gen_axilite.s_axi_bvalid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axilite.s_axi_bvalid_i_i_1_n_0\,
Q => \^mi_bvalid\(0),
R => SR(0)
);
\gen_axilite.s_axi_rvalid_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FFF8800"
)
port map (
I0 => mi_arready(3),
I1 => \m_ready_d_reg[1]_1\,
I2 => aa_rready,
I3 => \m_atarget_hot_reg[3]_0\(0),
I4 => mi_rvalid(3),
O => \gen_axilite.s_axi_rvalid_i_i_1_n_0\
);
\gen_axilite.s_axi_rvalid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axilite.s_axi_rvalid_i_i_1_n_0\,
Q => mi_rvalid(3),
R => SR(0)
);
\gen_no_arbiter.m_grant_hot_i[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F1F3F1F3F113F1F"
)
port map (
I0 => \^gen_no_arbiter.m_grant_hot_i_reg[0]_0\,
I1 => m_ready_d(1),
I2 => m_ready_d(0),
I3 => \gen_no_arbiter.grant_rnw_reg\,
I4 => s_axi_bready(0),
I5 => \^m_ready_d_reg[2]\,
O => \gen_no_arbiter.m_grant_hot_i_reg[0]\
);
\m_ready_d[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F3300550F33FF55"
)
port map (
I0 => m_axi_arready(0),
I1 => m_axi_arready(2),
I2 => mi_arready(3),
I3 => Q(0),
I4 => Q(1),
I5 => m_axi_arready(1),
O => \m_ready_d_reg[1]\
);
\m_ready_d[2]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFAAF0CC00AAF0CC"
)
port map (
I0 => m_axi_awready(2),
I1 => m_axi_awready(0),
I2 => m_axi_awready(1),
I3 => Q(0),
I4 => Q(1),
I5 => \^mi_wready\(0),
O => \^gen_no_arbiter.m_grant_hot_i_reg[0]_0\
);
m_valid_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"AAFFCCF0AA00CCF0"
)
port map (
I0 => mi_rvalid(3),
I1 => m_axi_rvalid(1),
I2 => m_axi_rvalid(0),
I3 => Q(0),
I4 => Q(1),
I5 => m_axi_rvalid(2),
O => m_valid_i_reg
);
\s_axi_bvalid[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"55000F3355FF0F33"
)
port map (
I0 => \^mi_bvalid\(0),
I1 => m_axi_bvalid(0),
I2 => m_axi_bvalid(2),
I3 => Q(1),
I4 => Q(0),
I5 => m_axi_bvalid(1),
O => \^m_ready_d_reg[2]\
);
\s_axi_wready[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"33000F5533FF0F55"
)
port map (
I0 => m_axi_wready(0),
I1 => \^mi_wready\(0),
I2 => m_axi_wready(2),
I3 => Q(1),
I4 => Q(0),
I5 => m_axi_wready(1),
O => \gen_no_arbiter.m_grant_hot_i_reg[0]_1\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter is
port (
\gen_axilite.s_axi_bvalid_i_reg\ : out STD_LOGIC;
m_ready_d : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : in STD_LOGIC;
aa_grant_rnw : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
m_ready_d0 : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_axilite.s_axi_bvalid_i_reg_0\ : in STD_LOGIC;
\gen_no_arbiter.grant_rnw_reg\ : in STD_LOGIC;
\m_ready_d_reg[2]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[2]_i_1_n_0\ : STD_LOGIC;
begin
m_ready_d(2 downto 0) <= \^m_ready_d\(2 downto 0);
\gen_axilite.s_axi_bvalid_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFDFFFFF"
)
port map (
I0 => s_axi_wvalid(0),
I1 => \^m_ready_d\(1),
I2 => Q(0),
I3 => \^m_ready_d\(2),
I4 => m_valid_i,
I5 => aa_grant_rnw,
O => \gen_axilite.s_axi_bvalid_i_reg\
);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0AAA0A020222020"
)
port map (
I0 => aresetn_d,
I1 => m_ready_d0(0),
I2 => \^m_ready_d\(0),
I3 => \gen_axilite.s_axi_bvalid_i_reg_0\,
I4 => \gen_no_arbiter.grant_rnw_reg\,
I5 => \m_ready_d_reg[2]_0\,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888808000808"
)
port map (
I0 => aresetn_d,
I1 => m_ready_d0(0),
I2 => \^m_ready_d\(0),
I3 => \gen_axilite.s_axi_bvalid_i_reg_0\,
I4 => \gen_no_arbiter.grant_rnw_reg\,
I5 => \m_ready_d_reg[2]_0\,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000002A222A2A"
)
port map (
I0 => aresetn_d,
I1 => m_ready_d0(0),
I2 => \^m_ready_d\(0),
I3 => \gen_axilite.s_axi_bvalid_i_reg_0\,
I4 => \gen_no_arbiter.grant_rnw_reg\,
I5 => \m_ready_d_reg[2]_0\,
O => \m_ready_d[2]_i_1_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
\m_ready_d_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[2]_i_1_n_0\,
Q => \^m_ready_d\(2),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter__parameterized0\ is
port (
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
aresetn_d : in STD_LOGIC;
aa_grant_rnw : in STD_LOGIC;
m_valid_i : in STD_LOGIC;
\gen_axilite.s_axi_arready_i_reg\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter__parameterized0\ : entity is "axi_crossbar_v2_1_14_splitter";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter__parameterized0\ is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
begin
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000AA002A"
)
port map (
I0 => aresetn_d,
I1 => aa_grant_rnw,
I2 => m_valid_i,
I3 => \^m_ready_d\(1),
I4 => \gen_axilite.s_axi_arready_i_reg\,
I5 => m_valid_i_reg,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA00AA8000000000"
)
port map (
I0 => aresetn_d,
I1 => aa_grant_rnw,
I2 => m_valid_i,
I3 => \^m_ready_d\(1),
I4 => \gen_axilite.s_axi_arready_i_reg\,
I5 => m_valid_i_reg,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice is
port (
sr_rvalid : out STD_LOGIC;
aa_rready : out STD_LOGIC;
\m_ready_d_reg[1]\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_valid_i_reg_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
\s_axi_rdata[31]\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_grant_rnw : in STD_LOGIC;
m_valid_i : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 5 downto 0 );
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 95 downto 0 );
\m_atarget_hot_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice is
signal \^aa_rready\ : STD_LOGIC;
signal \m_payload_i[1]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i_reg_n_0_[0]\ : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal skid_buffer : STD_LOGIC_VECTOR ( 34 downto 0 );
signal \skid_buffer[10]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[11]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[12]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[13]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[14]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[15]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[16]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[17]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[18]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[19]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[20]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[21]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[22]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[23]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[24]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[25]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[26]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[27]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[28]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[29]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[30]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[31]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[32]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[33]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[34]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[3]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[4]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[5]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[6]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[7]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[8]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer[9]_i_1_n_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \^sr_rvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_axi_rready[0]_INST_0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_axi_rready[1]_INST_0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_axi_rready[2]_INST_0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \skid_buffer[0]_i_1\ : label is "soft_lutpair31";
begin
aa_rready <= \^aa_rready\;
m_valid_i_reg_0(1 downto 0) <= \^m_valid_i_reg_0\(1 downto 0);
sr_rvalid <= \^sr_rvalid\;
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => '1',
Q => \^m_valid_i_reg_0\(0),
R => SR(0)
);
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \^m_valid_i_reg_0\(0),
Q => \^m_valid_i_reg_0\(1),
R => SR(0)
);
\m_axi_rready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[2]\(0),
O => m_axi_rready(0)
);
\m_axi_rready[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[2]\(1),
O => m_axi_rready(1)
);
\m_axi_rready[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^aa_rready\,
I1 => \m_atarget_hot_reg[2]\(2),
O => m_axi_rready(2)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[10]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[11]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[12]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[13]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[14]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[15]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[16]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[17]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[18]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[19]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \skid_buffer_reg_n_0_[1]\,
I1 => \^aa_rready\,
I2 => \m_payload_i[1]_i_2_n_0\,
O => skid_buffer(1)
);
\m_payload_i[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00550F3300000000"
)
port map (
I0 => m_axi_rresp(4),
I1 => m_axi_rresp(0),
I2 => m_axi_rresp(2),
I3 => Q(0),
I4 => Q(1),
I5 => \^aa_rready\,
O => \m_payload_i[1]_i_2_n_0\
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[20]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[21]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[22]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[23]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[24]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[25]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[26]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[27]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[28]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[29]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"0E"
)
port map (
I0 => \skid_buffer_reg_n_0_[2]\,
I1 => \^aa_rready\,
I2 => \m_payload_i[2]_i_2_n_0\,
O => skid_buffer(2)
);
\m_payload_i[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00220A0000220AAA"
)
port map (
I0 => \^aa_rready\,
I1 => m_axi_rresp(5),
I2 => m_axi_rresp(3),
I3 => Q(0),
I4 => Q(1),
I5 => m_axi_rresp(1),
O => \m_payload_i[2]_i_2_n_0\
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[30]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[31]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[32]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[33]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[34]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[3]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[4]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[5]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[6]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[7]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[8]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \skid_buffer[9]_i_1_n_0\,
I1 => \^aa_rready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \m_payload_i_reg_n_0_[0]\,
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \s_axi_rdata[31]\(9),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \s_axi_rdata[31]\(10),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \s_axi_rdata[31]\(11),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \s_axi_rdata[31]\(12),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \s_axi_rdata[31]\(13),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \s_axi_rdata[31]\(14),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \s_axi_rdata[31]\(15),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \s_axi_rdata[31]\(16),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \s_axi_rdata[31]\(17),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \s_axi_rdata[31]\(18),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \s_axi_rdata[31]\(0),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \s_axi_rdata[31]\(19),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \s_axi_rdata[31]\(20),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \s_axi_rdata[31]\(21),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \s_axi_rdata[31]\(22),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \s_axi_rdata[31]\(23),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \s_axi_rdata[31]\(24),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \s_axi_rdata[31]\(25),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \s_axi_rdata[31]\(26),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \s_axi_rdata[31]\(27),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \s_axi_rdata[31]\(28),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \s_axi_rdata[31]\(1),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \s_axi_rdata[31]\(29),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \s_axi_rdata[31]\(30),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \s_axi_rdata[31]\(31),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \s_axi_rdata[31]\(32),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \s_axi_rdata[31]\(33),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \s_axi_rdata[31]\(2),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \s_axi_rdata[31]\(3),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \s_axi_rdata[31]\(4),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \s_axi_rdata[31]\(5),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \s_axi_rdata[31]\(6),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \s_axi_rdata[31]\(7),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \s_axi_rdata[31]\(8),
R => '0'
);
\m_ready_d[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000007FFFFFFF"
)
port map (
I0 => \^sr_rvalid\,
I1 => \m_payload_i_reg_n_0_[0]\,
I2 => s_axi_rready(0),
I3 => aa_grant_rnw,
I4 => m_valid_i,
I5 => m_ready_d(0),
O => \m_ready_d_reg[1]\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[1]_0\,
Q => \^sr_rvalid\,
R => '0'
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^aa_rready\,
R => '0'
);
\skid_buffer[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^aa_rready\,
I1 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\skid_buffer[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(7),
I1 => m_axi_rdata(39),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(71),
O => \skid_buffer[10]_i_1_n_0\
);
\skid_buffer[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(8),
I1 => m_axi_rdata(40),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(72),
O => \skid_buffer[11]_i_1_n_0\
);
\skid_buffer[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(9),
I1 => m_axi_rdata(41),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(73),
O => \skid_buffer[12]_i_1_n_0\
);
\skid_buffer[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(10),
I1 => m_axi_rdata(42),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(74),
O => \skid_buffer[13]_i_1_n_0\
);
\skid_buffer[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(11),
I1 => m_axi_rdata(43),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(75),
O => \skid_buffer[14]_i_1_n_0\
);
\skid_buffer[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(12),
I1 => m_axi_rdata(44),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(76),
O => \skid_buffer[15]_i_1_n_0\
);
\skid_buffer[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0ACF0AC0"
)
port map (
I0 => m_axi_rdata(45),
I1 => m_axi_rdata(77),
I2 => Q(1),
I3 => Q(0),
I4 => m_axi_rdata(13),
O => \skid_buffer[16]_i_1_n_0\
);
\skid_buffer[17]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(14),
I1 => m_axi_rdata(46),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(78),
O => \skid_buffer[17]_i_1_n_0\
);
\skid_buffer[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(15),
I1 => m_axi_rdata(47),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(79),
O => \skid_buffer[18]_i_1_n_0\
);
\skid_buffer[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(16),
I1 => m_axi_rdata(48),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(80),
O => \skid_buffer[19]_i_1_n_0\
);
\skid_buffer[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(17),
I1 => m_axi_rdata(49),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(81),
O => \skid_buffer[20]_i_1_n_0\
);
\skid_buffer[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(18),
I1 => m_axi_rdata(50),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(82),
O => \skid_buffer[21]_i_1_n_0\
);
\skid_buffer[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(19),
I1 => m_axi_rdata(51),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(83),
O => \skid_buffer[22]_i_1_n_0\
);
\skid_buffer[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(20),
I1 => m_axi_rdata(52),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(84),
O => \skid_buffer[23]_i_1_n_0\
);
\skid_buffer[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(21),
I1 => m_axi_rdata(53),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(85),
O => \skid_buffer[24]_i_1_n_0\
);
\skid_buffer[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(22),
I1 => m_axi_rdata(54),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(86),
O => \skid_buffer[25]_i_1_n_0\
);
\skid_buffer[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(23),
I1 => m_axi_rdata(55),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(87),
O => \skid_buffer[26]_i_1_n_0\
);
\skid_buffer[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0CAF0CA0"
)
port map (
I0 => m_axi_rdata(88),
I1 => m_axi_rdata(56),
I2 => Q(1),
I3 => Q(0),
I4 => m_axi_rdata(24),
O => \skid_buffer[27]_i_1_n_0\
);
\skid_buffer[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(25),
I1 => m_axi_rdata(57),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(89),
O => \skid_buffer[28]_i_1_n_0\
);
\skid_buffer[29]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(26),
I1 => m_axi_rdata(58),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(90),
O => \skid_buffer[29]_i_1_n_0\
);
\skid_buffer[30]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(27),
I1 => m_axi_rdata(59),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(91),
O => \skid_buffer[30]_i_1_n_0\
);
\skid_buffer[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(28),
I1 => m_axi_rdata(60),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(92),
O => \skid_buffer[31]_i_1_n_0\
);
\skid_buffer[32]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(29),
I1 => m_axi_rdata(61),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(93),
O => \skid_buffer[32]_i_1_n_0\
);
\skid_buffer[33]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(30),
I1 => m_axi_rdata(62),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(94),
O => \skid_buffer[33]_i_1_n_0\
);
\skid_buffer[34]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(31),
I1 => m_axi_rdata(63),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(95),
O => \skid_buffer[34]_i_1_n_0\
);
\skid_buffer[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(0),
I1 => m_axi_rdata(32),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(64),
O => \skid_buffer[3]_i_1_n_0\
);
\skid_buffer[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(1),
I1 => m_axi_rdata(33),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(65),
O => \skid_buffer[4]_i_1_n_0\
);
\skid_buffer[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(2),
I1 => m_axi_rdata(66),
I2 => Q(1),
I3 => Q(0),
I4 => m_axi_rdata(34),
O => \skid_buffer[5]_i_1_n_0\
);
\skid_buffer[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(3),
I1 => m_axi_rdata(35),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(67),
O => \skid_buffer[6]_i_1_n_0\
);
\skid_buffer[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(4),
I1 => m_axi_rdata(36),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(68),
O => \skid_buffer[7]_i_1_n_0\
);
\skid_buffer[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(5),
I1 => m_axi_rdata(37),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(69),
O => \skid_buffer[8]_i_1_n_0\
);
\skid_buffer[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCA00CA"
)
port map (
I0 => m_axi_rdata(6),
I1 => m_axi_rdata(38),
I2 => Q(0),
I3 => Q(1),
I4 => m_axi_rdata(70),
O => \skid_buffer[9]_i_1_n_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[10]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[11]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[12]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[13]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[14]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[15]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[16]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[17]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[18]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[19]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[20]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[21]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[22]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[23]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[24]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[25]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[26]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[27]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[28]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[29]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[30]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[31]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[32]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[33]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[34]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[3]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[4]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[5]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[6]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[7]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[8]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^aa_rready\,
D => \skid_buffer[9]_i_1_n_0\,
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar_sasd is
port (
Q : out STD_LOGIC_VECTOR ( 34 downto 0 );
\s_axi_rdata[31]\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 2 downto 0 );
aresetn : in STD_LOGIC;
aclk : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar_sasd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar_sasd is
signal \^q\ : STD_LOGIC_VECTOR ( 34 downto 0 );
signal aa_grant_rnw : STD_LOGIC;
signal aa_rready : STD_LOGIC;
signal addr_arbiter_inst_n_3 : STD_LOGIC;
signal addr_arbiter_inst_n_4 : STD_LOGIC;
signal addr_arbiter_inst_n_43 : STD_LOGIC;
signal addr_arbiter_inst_n_44 : STD_LOGIC;
signal addr_arbiter_inst_n_45 : STD_LOGIC;
signal addr_arbiter_inst_n_46 : STD_LOGIC;
signal addr_arbiter_inst_n_47 : STD_LOGIC;
signal addr_arbiter_inst_n_5 : STD_LOGIC;
signal addr_arbiter_inst_n_52 : STD_LOGIC;
signal addr_arbiter_inst_n_61 : STD_LOGIC;
signal addr_arbiter_inst_n_66 : STD_LOGIC;
signal addr_arbiter_inst_n_7 : STD_LOGIC;
signal addr_arbiter_inst_n_70 : STD_LOGIC;
signal aresetn_d : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_2\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_3\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_4\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_5\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_6\ : STD_LOGIC;
signal \gen_decerr.decerr_slave_inst_n_7\ : STD_LOGIC;
signal m_atarget_enc : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_atarget_enc[0]_i_1_n_0\ : STD_LOGIC;
signal \m_atarget_enc[1]_i_1_n_0\ : STD_LOGIC;
signal m_atarget_hot : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m_atarget_hot0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_ready_d0 : STD_LOGIC_VECTOR ( 1 to 1 );
signal m_ready_d_0 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m_valid_i : STD_LOGIC;
signal mi_bvalid : STD_LOGIC_VECTOR ( 3 to 3 );
signal mi_wready : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_1_in : STD_LOGIC;
signal reg_slice_r_n_2 : STD_LOGIC;
signal reg_slice_r_n_6 : STD_LOGIC;
signal reg_slice_r_n_7 : STD_LOGIC;
signal reset : STD_LOGIC;
signal splitter_aw_n_0 : STD_LOGIC;
signal sr_rvalid : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_atarget_enc[0]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_atarget_enc[1]_i_1\ : label is "soft_lutpair33";
begin
Q(34 downto 0) <= \^q\(34 downto 0);
addr_arbiter_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_sasd
port map (
D(3) => addr_arbiter_inst_n_3,
D(2) => addr_arbiter_inst_n_4,
D(1) => addr_arbiter_inst_n_5,
D(0) => m_atarget_hot0(0),
E(0) => p_1_in,
Q(34 downto 0) => \^q\(34 downto 0),
SR(0) => reset,
aa_grant_rnw => aa_grant_rnw,
aa_rready => aa_rready,
aclk => aclk,
aresetn_d => aresetn_d,
\aresetn_d_reg[1]\(1) => reg_slice_r_n_6,
\aresetn_d_reg[1]\(0) => reg_slice_r_n_7,
\gen_axilite.s_axi_arready_i_reg\ => \gen_decerr.decerr_slave_inst_n_7\,
\gen_axilite.s_axi_awready_i_reg\ => addr_arbiter_inst_n_70,
\gen_axilite.s_axi_awready_i_reg_0\ => \gen_decerr.decerr_slave_inst_n_6\,
\gen_axilite.s_axi_bvalid_i_reg\ => \gen_decerr.decerr_slave_inst_n_4\,
\gen_axilite.s_axi_rvalid_i_reg\ => addr_arbiter_inst_n_66,
\gen_axilite.s_axi_rvalid_i_reg_0\ => \gen_decerr.decerr_slave_inst_n_5\,
\gen_no_arbiter.m_grant_hot_i_reg[0]_0\ => addr_arbiter_inst_n_61,
\m_atarget_enc_reg[0]\ => \gen_decerr.decerr_slave_inst_n_3\,
\m_atarget_hot_reg[2]\ => addr_arbiter_inst_n_7,
\m_atarget_hot_reg[2]_0\ => addr_arbiter_inst_n_43,
\m_atarget_hot_reg[3]\ => addr_arbiter_inst_n_44,
\m_atarget_hot_reg[3]_0\(3 downto 0) => m_atarget_hot(3 downto 0),
m_axi_arvalid(2 downto 0) => m_axi_arvalid(2 downto 0),
m_axi_awvalid(2 downto 0) => m_axi_awvalid(2 downto 0),
m_axi_bready(2 downto 0) => m_axi_bready(2 downto 0),
m_axi_wvalid(2 downto 0) => m_axi_wvalid(2 downto 0),
m_ready_d(2 downto 0) => m_ready_d_0(2 downto 0),
m_ready_d0(0) => m_ready_d0(1),
m_ready_d_0(1 downto 0) => m_ready_d(1 downto 0),
\m_ready_d_reg[2]\ => addr_arbiter_inst_n_47,
\m_ready_d_reg[2]_0\ => addr_arbiter_inst_n_52,
\m_ready_d_reg[2]_1\ => \gen_decerr.decerr_slave_inst_n_2\,
m_valid_i => m_valid_i,
m_valid_i_reg => addr_arbiter_inst_n_46,
m_valid_i_reg_0 => reg_slice_r_n_2,
mi_bvalid(0) => mi_bvalid(3),
mi_wready(0) => mi_wready(3),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
s_ready_i_reg => addr_arbiter_inst_n_45,
sr_rvalid => sr_rvalid
);
aresetn_d_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => aresetn_d,
R => '0'
);
\gen_decerr.decerr_slave_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave
port map (
Q(1 downto 0) => m_atarget_enc(1 downto 0),
SR(0) => reset,
aa_rready => aa_rready,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_no_arbiter.grant_rnw_reg\ => addr_arbiter_inst_n_61,
\gen_no_arbiter.grant_rnw_reg_0\ => addr_arbiter_inst_n_52,
\gen_no_arbiter.m_grant_hot_i_reg[0]\ => \gen_decerr.decerr_slave_inst_n_2\,
\gen_no_arbiter.m_grant_hot_i_reg[0]_0\ => \gen_decerr.decerr_slave_inst_n_3\,
\gen_no_arbiter.m_grant_hot_i_reg[0]_1\ => \gen_decerr.decerr_slave_inst_n_6\,
\m_atarget_hot_reg[3]\ => addr_arbiter_inst_n_70,
\m_atarget_hot_reg[3]_0\(0) => m_atarget_hot(3),
m_axi_arready(2 downto 0) => m_axi_arready(2 downto 0),
m_axi_awready(2 downto 0) => m_axi_awready(2 downto 0),
m_axi_bvalid(2 downto 0) => m_axi_bvalid(2 downto 0),
m_axi_rvalid(2 downto 0) => m_axi_rvalid(2 downto 0),
m_axi_wready(2 downto 0) => m_axi_wready(2 downto 0),
m_ready_d(1) => m_ready_d_0(2),
m_ready_d(0) => m_ready_d_0(0),
\m_ready_d_reg[1]\ => \gen_decerr.decerr_slave_inst_n_7\,
\m_ready_d_reg[1]_0\ => splitter_aw_n_0,
\m_ready_d_reg[1]_1\ => addr_arbiter_inst_n_66,
\m_ready_d_reg[2]\ => \gen_decerr.decerr_slave_inst_n_4\,
m_valid_i_reg => \gen_decerr.decerr_slave_inst_n_5\,
mi_bvalid(0) => mi_bvalid(3),
mi_wready(0) => mi_wready(3),
s_axi_bready(0) => s_axi_bready(0)
);
\m_atarget_enc[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FEEE"
)
port map (
I0 => addr_arbiter_inst_n_43,
I1 => \^q\(16),
I2 => addr_arbiter_inst_n_7,
I3 => addr_arbiter_inst_n_44,
O => \m_atarget_enc[0]_i_1_n_0\
);
\m_atarget_enc[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFAB"
)
port map (
I0 => addr_arbiter_inst_n_43,
I1 => \^q\(16),
I2 => addr_arbiter_inst_n_7,
I3 => addr_arbiter_inst_n_44,
O => \m_atarget_enc[1]_i_1_n_0\
);
\m_atarget_enc_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_atarget_enc[0]_i_1_n_0\,
Q => m_atarget_enc(0),
R => reset
);
\m_atarget_enc_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_atarget_enc[1]_i_1_n_0\,
Q => m_atarget_enc(1),
R => reset
);
\m_atarget_hot_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_atarget_hot0(0),
Q => m_atarget_hot(0),
R => reset
);
\m_atarget_hot_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_5,
Q => m_atarget_hot(1),
R => reset
);
\m_atarget_hot_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_4,
Q => m_atarget_hot(2),
R => reset
);
\m_atarget_hot_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => addr_arbiter_inst_n_3,
Q => m_atarget_hot(3),
R => reset
);
reg_slice_r: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice
port map (
E(0) => p_1_in,
Q(1 downto 0) => m_atarget_enc(1 downto 0),
SR(0) => reset,
aa_grant_rnw => aa_grant_rnw,
aa_rready => aa_rready,
aclk => aclk,
\aresetn_d_reg[0]_0\ => addr_arbiter_inst_n_45,
\aresetn_d_reg[1]_0\ => addr_arbiter_inst_n_46,
\m_atarget_hot_reg[2]\(2 downto 0) => m_atarget_hot(2 downto 0),
m_axi_rdata(95 downto 0) => m_axi_rdata(95 downto 0),
m_axi_rready(2 downto 0) => m_axi_rready(2 downto 0),
m_axi_rresp(5 downto 0) => m_axi_rresp(5 downto 0),
m_ready_d(0) => m_ready_d(0),
\m_ready_d_reg[1]\ => reg_slice_r_n_2,
m_valid_i => m_valid_i,
m_valid_i_reg_0(1) => reg_slice_r_n_6,
m_valid_i_reg_0(0) => reg_slice_r_n_7,
\s_axi_rdata[31]\(33 downto 0) => \s_axi_rdata[31]\(33 downto 0),
s_axi_rready(0) => s_axi_rready(0),
sr_rvalid => sr_rvalid
);
\s_axi_bresp[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCAFFCA0"
)
port map (
I0 => m_axi_bresp(4),
I1 => m_axi_bresp(2),
I2 => m_atarget_enc(1),
I3 => m_atarget_enc(0),
I4 => m_axi_bresp(0),
O => s_axi_bresp(0)
);
\s_axi_bresp[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCAFFCA0"
)
port map (
I0 => m_axi_bresp(5),
I1 => m_axi_bresp(3),
I2 => m_atarget_enc(1),
I3 => m_atarget_enc(0),
I4 => m_axi_bresp(1),
O => s_axi_bresp(1)
);
splitter_ar: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter__parameterized0\
port map (
aa_grant_rnw => aa_grant_rnw,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_axilite.s_axi_arready_i_reg\ => \gen_decerr.decerr_slave_inst_n_7\,
m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
m_valid_i => m_valid_i,
m_valid_i_reg => reg_slice_r_n_2
);
splitter_aw: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter
port map (
Q(0) => m_atarget_hot(3),
aa_grant_rnw => aa_grant_rnw,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_axilite.s_axi_bvalid_i_reg\ => splitter_aw_n_0,
\gen_axilite.s_axi_bvalid_i_reg_0\ => \gen_decerr.decerr_slave_inst_n_4\,
\gen_no_arbiter.grant_rnw_reg\ => addr_arbiter_inst_n_52,
m_ready_d(2 downto 0) => m_ready_d_0(2 downto 0),
m_ready_d0(0) => m_ready_d0(1),
\m_ready_d_reg[2]_0\ => addr_arbiter_inst_n_47,
m_valid_i => m_valid_i,
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_wid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_wuser : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_ruser : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_DEBUG : integer;
attribute C_DEBUG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "96'b000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "192'b000000000000000000000000000000000100001010000000000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 3;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute P_INCR : string;
attribute P_INCR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute P_LOCK : integer;
attribute P_LOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "3'b111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "3'b111";
attribute P_ONES : string;
attribute P_ONES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^m_axi_arprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 95 downto 80 );
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
m_axi_araddr(95 downto 80) <= \^m_axi_awaddr\(95 downto 80);
m_axi_araddr(79 downto 64) <= \^m_axi_araddr\(15 downto 0);
m_axi_araddr(63 downto 48) <= \^m_axi_awaddr\(95 downto 80);
m_axi_araddr(47 downto 32) <= \^m_axi_araddr\(15 downto 0);
m_axi_araddr(31 downto 16) <= \^m_axi_awaddr\(95 downto 80);
m_axi_araddr(15 downto 0) <= \^m_axi_araddr\(15 downto 0);
m_axi_arburst(5) <= \<const0>\;
m_axi_arburst(4) <= \<const0>\;
m_axi_arburst(3) <= \<const0>\;
m_axi_arburst(2) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(11) <= \<const0>\;
m_axi_arcache(10) <= \<const0>\;
m_axi_arcache(9) <= \<const0>\;
m_axi_arcache(8) <= \<const0>\;
m_axi_arcache(7) <= \<const0>\;
m_axi_arcache(6) <= \<const0>\;
m_axi_arcache(5) <= \<const0>\;
m_axi_arcache(4) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(23) <= \<const0>\;
m_axi_arlen(22) <= \<const0>\;
m_axi_arlen(21) <= \<const0>\;
m_axi_arlen(20) <= \<const0>\;
m_axi_arlen(19) <= \<const0>\;
m_axi_arlen(18) <= \<const0>\;
m_axi_arlen(17) <= \<const0>\;
m_axi_arlen(16) <= \<const0>\;
m_axi_arlen(15) <= \<const0>\;
m_axi_arlen(14) <= \<const0>\;
m_axi_arlen(13) <= \<const0>\;
m_axi_arlen(12) <= \<const0>\;
m_axi_arlen(11) <= \<const0>\;
m_axi_arlen(10) <= \<const0>\;
m_axi_arlen(9) <= \<const0>\;
m_axi_arlen(8) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(2) <= \<const0>\;
m_axi_arlock(1) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(8 downto 6) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(5 downto 3) <= \^m_axi_arprot\(2 downto 0);
m_axi_arprot(2 downto 0) <= \^m_axi_arprot\(2 downto 0);
m_axi_arqos(11) <= \<const0>\;
m_axi_arqos(10) <= \<const0>\;
m_axi_arqos(9) <= \<const0>\;
m_axi_arqos(8) <= \<const0>\;
m_axi_arqos(7) <= \<const0>\;
m_axi_arqos(6) <= \<const0>\;
m_axi_arqos(5) <= \<const0>\;
m_axi_arqos(4) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(11) <= \<const0>\;
m_axi_arregion(10) <= \<const0>\;
m_axi_arregion(9) <= \<const0>\;
m_axi_arregion(8) <= \<const0>\;
m_axi_arregion(7) <= \<const0>\;
m_axi_arregion(6) <= \<const0>\;
m_axi_arregion(5) <= \<const0>\;
m_axi_arregion(4) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(8) <= \<const0>\;
m_axi_arsize(7) <= \<const0>\;
m_axi_arsize(6) <= \<const0>\;
m_axi_arsize(5) <= \<const0>\;
m_axi_arsize(4) <= \<const0>\;
m_axi_arsize(3) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(2) <= \<const0>\;
m_axi_aruser(1) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awaddr(95 downto 80) <= \^m_axi_awaddr\(95 downto 80);
m_axi_awaddr(79 downto 64) <= \^m_axi_araddr\(15 downto 0);
m_axi_awaddr(63 downto 48) <= \^m_axi_awaddr\(95 downto 80);
m_axi_awaddr(47 downto 32) <= \^m_axi_araddr\(15 downto 0);
m_axi_awaddr(31 downto 16) <= \^m_axi_awaddr\(95 downto 80);
m_axi_awaddr(15 downto 0) <= \^m_axi_araddr\(15 downto 0);
m_axi_awburst(5) <= \<const0>\;
m_axi_awburst(4) <= \<const0>\;
m_axi_awburst(3) <= \<const0>\;
m_axi_awburst(2) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(11) <= \<const0>\;
m_axi_awcache(10) <= \<const0>\;
m_axi_awcache(9) <= \<const0>\;
m_axi_awcache(8) <= \<const0>\;
m_axi_awcache(7) <= \<const0>\;
m_axi_awcache(6) <= \<const0>\;
m_axi_awcache(5) <= \<const0>\;
m_axi_awcache(4) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(23) <= \<const0>\;
m_axi_awlen(22) <= \<const0>\;
m_axi_awlen(21) <= \<const0>\;
m_axi_awlen(20) <= \<const0>\;
m_axi_awlen(19) <= \<const0>\;
m_axi_awlen(18) <= \<const0>\;
m_axi_awlen(17) <= \<const0>\;
m_axi_awlen(16) <= \<const0>\;
m_axi_awlen(15) <= \<const0>\;
m_axi_awlen(14) <= \<const0>\;
m_axi_awlen(13) <= \<const0>\;
m_axi_awlen(12) <= \<const0>\;
m_axi_awlen(11) <= \<const0>\;
m_axi_awlen(10) <= \<const0>\;
m_axi_awlen(9) <= \<const0>\;
m_axi_awlen(8) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(2) <= \<const0>\;
m_axi_awlock(1) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(8 downto 6) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(5 downto 3) <= \^m_axi_arprot\(2 downto 0);
m_axi_awprot(2 downto 0) <= \^m_axi_arprot\(2 downto 0);
m_axi_awqos(11) <= \<const0>\;
m_axi_awqos(10) <= \<const0>\;
m_axi_awqos(9) <= \<const0>\;
m_axi_awqos(8) <= \<const0>\;
m_axi_awqos(7) <= \<const0>\;
m_axi_awqos(6) <= \<const0>\;
m_axi_awqos(5) <= \<const0>\;
m_axi_awqos(4) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(11) <= \<const0>\;
m_axi_awregion(10) <= \<const0>\;
m_axi_awregion(9) <= \<const0>\;
m_axi_awregion(8) <= \<const0>\;
m_axi_awregion(7) <= \<const0>\;
m_axi_awregion(6) <= \<const0>\;
m_axi_awregion(5) <= \<const0>\;
m_axi_awregion(4) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(8) <= \<const0>\;
m_axi_awsize(7) <= \<const0>\;
m_axi_awsize(6) <= \<const0>\;
m_axi_awsize(5) <= \<const0>\;
m_axi_awsize(4) <= \<const0>\;
m_axi_awsize(3) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(2) <= \<const0>\;
m_axi_awuser(1) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(95 downto 64) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(63 downto 32) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast(2) <= \<const0>\;
m_axi_wlast(1) <= \<const0>\;
m_axi_wlast(0) <= \<const0>\;
m_axi_wstrb(11 downto 8) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(7 downto 4) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(2) <= \<const0>\;
m_axi_wuser(1) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_sasd.crossbar_sasd_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar_sasd
port map (
Q(34 downto 32) => \^m_axi_arprot\(2 downto 0),
Q(31 downto 16) => \^m_axi_awaddr\(95 downto 80),
Q(15 downto 0) => \^m_axi_araddr\(15 downto 0),
aclk => aclk,
aresetn => aresetn,
m_axi_arready(2 downto 0) => m_axi_arready(2 downto 0),
m_axi_arvalid(2 downto 0) => m_axi_arvalid(2 downto 0),
m_axi_awready(2 downto 0) => m_axi_awready(2 downto 0),
m_axi_awvalid(2 downto 0) => m_axi_awvalid(2 downto 0),
m_axi_bready(2 downto 0) => m_axi_bready(2 downto 0),
m_axi_bresp(5 downto 0) => m_axi_bresp(5 downto 0),
m_axi_bvalid(2 downto 0) => m_axi_bvalid(2 downto 0),
m_axi_rdata(95 downto 0) => m_axi_rdata(95 downto 0),
m_axi_rready(2 downto 0) => m_axi_rready(2 downto 0),
m_axi_rresp(5 downto 0) => m_axi_rresp(5 downto 0),
m_axi_rvalid(2 downto 0) => m_axi_rvalid(2 downto 0),
m_axi_wready(2 downto 0) => m_axi_wready(2 downto 0),
m_axi_wvalid(2 downto 0) => m_axi_wvalid(2 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid(0) => s_axi_bvalid(0),
\s_axi_rdata[31]\(33 downto 2) => s_axi_rdata(31 downto 0),
\s_axi_rdata[31]\(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_xbar_1,axi_crossbar_v2_1_14_axi_crossbar,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 23 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_rlast_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 2;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of inst : label is 0;
attribute C_DEBUG : integer;
attribute C_DEBUG of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of inst : label is "96'b000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of inst : label is "192'b000000000000000000000000000000000100001010000000000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of inst : label is "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of inst : label is "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of inst : label is "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of inst : label is "96'b000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of inst : label is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of inst : label is 3;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of inst : label is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of inst : label is 1;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of inst : label is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of inst : label is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of inst : label is 1;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of inst : label is 1;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of inst : label is 0;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of inst : label is 1;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of inst : label is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of inst : label is "zynq";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of inst : label is 8;
attribute P_LOCK : integer;
attribute P_LOCK of inst : label is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of inst : label is "96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of inst : label is "3'b111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "3'b111";
attribute P_ONES : string;
attribute P_ONES of inst : label is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of inst : label is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of inst : label is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of inst : label is "1'b1";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(95 downto 0) => m_axi_araddr(95 downto 0),
m_axi_arburst(5 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(5 downto 0),
m_axi_arcache(11 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(11 downto 0),
m_axi_arid(2 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(2 downto 0),
m_axi_arlen(23 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(23 downto 0),
m_axi_arlock(2 downto 0) => NLW_inst_m_axi_arlock_UNCONNECTED(2 downto 0),
m_axi_arprot(8 downto 0) => m_axi_arprot(8 downto 0),
m_axi_arqos(11 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(11 downto 0),
m_axi_arready(2 downto 0) => m_axi_arready(2 downto 0),
m_axi_arregion(11 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(11 downto 0),
m_axi_arsize(8 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(8 downto 0),
m_axi_aruser(2 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(2 downto 0),
m_axi_arvalid(2 downto 0) => m_axi_arvalid(2 downto 0),
m_axi_awaddr(95 downto 0) => m_axi_awaddr(95 downto 0),
m_axi_awburst(5 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(5 downto 0),
m_axi_awcache(11 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(11 downto 0),
m_axi_awid(2 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(2 downto 0),
m_axi_awlen(23 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(23 downto 0),
m_axi_awlock(2 downto 0) => NLW_inst_m_axi_awlock_UNCONNECTED(2 downto 0),
m_axi_awprot(8 downto 0) => m_axi_awprot(8 downto 0),
m_axi_awqos(11 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(11 downto 0),
m_axi_awready(2 downto 0) => m_axi_awready(2 downto 0),
m_axi_awregion(11 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(11 downto 0),
m_axi_awsize(8 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(8 downto 0),
m_axi_awuser(2 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(2 downto 0),
m_axi_awvalid(2 downto 0) => m_axi_awvalid(2 downto 0),
m_axi_bid(2 downto 0) => B"000",
m_axi_bready(2 downto 0) => m_axi_bready(2 downto 0),
m_axi_bresp(5 downto 0) => m_axi_bresp(5 downto 0),
m_axi_buser(2 downto 0) => B"000",
m_axi_bvalid(2 downto 0) => m_axi_bvalid(2 downto 0),
m_axi_rdata(95 downto 0) => m_axi_rdata(95 downto 0),
m_axi_rid(2 downto 0) => B"000",
m_axi_rlast(2 downto 0) => B"111",
m_axi_rready(2 downto 0) => m_axi_rready(2 downto 0),
m_axi_rresp(5 downto 0) => m_axi_rresp(5 downto 0),
m_axi_ruser(2 downto 0) => B"000",
m_axi_rvalid(2 downto 0) => m_axi_rvalid(2 downto 0),
m_axi_wdata(95 downto 0) => m_axi_wdata(95 downto 0),
m_axi_wid(2 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(2 downto 0),
m_axi_wlast(2 downto 0) => NLW_inst_m_axi_wlast_UNCONNECTED(2 downto 0),
m_axi_wready(2 downto 0) => m_axi_wready(2 downto 0),
m_axi_wstrb(11 downto 0) => m_axi_wstrb(11 downto 0),
m_axi_wuser(2 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(2 downto 0),
m_axi_wvalid(2 downto 0) => m_axi_wvalid(2 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready(0) => s_axi_arready(0),
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready(0) => s_axi_awready(0),
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bid(0) => NLW_inst_s_axi_bid_UNCONNECTED(0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => NLW_inst_s_axi_rid_UNCONNECTED(0),
s_axi_rlast(0) => NLW_inst_s_axi_rlast_UNCONNECTED(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(0) => '0',
s_axi_wlast(0) => '1',
s_axi_wready(0) => s_axi_wready(0),
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
|
entity tb_slice03 is
end tb_slice03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_slice03 is
signal di : std_logic_vector (7 downto 0);
signal do : std_logic_vector (3 downto 0);
begin
dut: entity work.slice03
port map (di, do);
process
begin
di <= x"12";
wait for 1 ns;
assert do = x"1" severity error;
di <= x"e5";
wait for 1 ns;
assert do = x"e" severity error;
wait;
end process;
end behav;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- Simple Digital-Controlled Two-position Switch Model
-- Switch position 1 ('0') or switch position 2 ('1')
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.math_real.all;
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.electrical_systems.ALL;
ENTITY switch_dig_2in is
GENERIC (r_open : RESISTANCE := 1.0e6; -- Open switch resistance
r_closed : RESISTANCE := 0.001; -- Closed switch resistance
trans_time : real := 0.00001); -- Transition time to each position
PORT (sw_state : in std_logic; -- Digital control input
TERMINAL p_in1, p_in2, p_out : ELECTRICAL); -- Analog output
END ENTITY switch_dig_2in;
ARCHITECTURE ideal OF switch_dig_2in IS
SIGNAL r_sig1 : RESISTANCE := r_closed; -- Variable to accept switch resistance
SIGNAL r_sig2 : RESISTANCE := r_open; -- Variable to accept switch resistance
QUANTITY v1 ACROSS i1 THROUGH p_in1 TO p_out; -- V & I for in1 to out
QUANTITY v2 ACROSS i2 THROUGH p_in2 TO p_out; -- V & I for in2 to out
QUANTITY r1 : RESISTANCE; -- Time-varying resistance for in1 to out
QUANTITY r2 : RESISTANCE; -- Time-varying resistance for in2 to out
BEGIN
PROCESS (sw_state) -- Sensitivity to digital control input
BEGIN
IF (sw_state = '0') THEN -- Close sig1, open sig2
r_sig1 <= r_closed;
r_sig2 <= r_open;
ELSIF (sw_state = '1') THEN -- Open sig1, close sig2
r_sig1 <= r_open;
r_sig2 <= r_closed;
END IF;
END PROCESS;
r1 == r_sig1'ramp(trans_time, trans_time); -- Ensure resistance continuity
r2 == r_sig2'ramp(trans_time, trans_time); -- Ensure resistance continuity
v1 == r1*i1; -- Apply Ohm's law to in1
v2 == r2*i2; -- Apply Ohm's law to in2
END ARCHITECTURE ideal;
--
-- Digital clock with 50% duty cycle
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clock IS
GENERIC (
period : time); -- Clock period
PORT (
clk_out : OUT std_logic);
END ENTITY clock;
ARCHITECTURE ideal OF clock IS
BEGIN
-- clock process
process
begin
clk_out <= '0';
wait for period/2;
clk_out <= '1';
wait for period/2;
end process;
END ARCHITECTURE ideal;
--
-- This digital clock allows user to specify the duty cycle using
-- the parameters "on_time" and "off_time"
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
ENTITY clock_duty IS
GENERIC (
on_time : time := 20 us;
off_time : time := 19.98 ms
);
PORT (
clock_out : OUT std_logic := '0');
END ENTITY clock_duty;
ARCHITECTURE ideal OF clock_duty IS
BEGIN
-- clock process
process
begin
clock_out <= '1';
wait for on_time;
clock_out <= '0';
wait for off_time;
end process;
END ARCHITECTURE ideal;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity rc_clk is
port(
clk_100k : out std_logic;
clk_6K : out std_logic;
clk_50 : out std_logic
);
end rc_clk;
architecture rc_clk of rc_clk is
-- Component declarations
-- Signal declarations
begin
-- Signal assignments
-- Component instances
XCMP1 : entity work.clock(ideal)
generic map(
period => 10 us
)
port map(
CLK_OUT => clk_100k
);
XCMP2 : entity work.clock(ideal)
generic map(
period => 150 us
)
port map(
CLK_OUT => clk_6K
);
clk_50Hz : entity work.clock_duty(ideal)
generic map(
on_time => 20 us,
off_time => 19.98 ms
)
port map(
CLOCK_OUT => clk_50
);
end rc_clk;
--
-- This model counts the number of input clock transitions and outputs
-- a '1' when this number equals the value of the user-defined constant 'count'
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity bit_cnt is
generic (
count : integer -- User-defined value to count up to
);
port
(
bit_in : in std_logic ;
clk : in std_logic ;
dly_out : out std_logic
);
end bit_cnt;
architecture behavioral of bit_cnt is
begin
serial_clock : process is
begin
wait until bit_in'event AND (bit_in = '1' OR bit_in = 'H');
FOR i IN 0 to count LOOP -- Loop for 'count' clock transitions
wait until clk'event AND (clk = '1' OR clk = 'H');
END LOOP ;
dly_out <= '1'; -- After count is reached, set output high
wait until bit_in'event AND (bit_in = '0' OR bit_in = 'L');
dly_out <= '0'; -- Reset output to '0' on next clock input
end process serial_clock;
end;
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
LIBRARY IEEE_proposed;
USE IEEE_proposed.electrical_systems.all;
USE IEEE_proposed.mechanical_systems.all;
ENTITY state_mach1 IS
PORT (
a2d_eoc : IN std_logic;
clk_50 : IN std_logic;
clk_100k : IN std_logic;
clk_6k : IN std_logic;
ser_done : IN std_logic;
ch_sel : OUT std_logic;
frm_gen : OUT std_logic;
a2d_oe : OUT std_logic;
a2d_start : OUT std_logic;
p2s_oe : OUT std_logic;
p2s_load : OUT std_logic;
parity_oe : OUT std_logic;
ser_cnt : OUT std_logic;
p2s_clr : OUT std_logic);
END state_mach1;
ARCHITECTURE state_diagram OF state_mach1 IS
ATTRIBUTE ENUM_TYPE_ENCODING: STRING;
TYPE TYP_state_mach1_sm1 IS (V_begin, frm_rd, ser_oe, ch1, data_en, tdm_oe, ch2
, load, ad_ch2, delay);
SIGNAL CS_state_mach1_sm1, NS_state_mach1_sm1 : TYP_state_mach1_sm1;
SIGNAL FB_frm_gen : std_logic;
SIGNAL FB_p2s_load : std_logic;
SIGNAL FB_ch_sel : std_logic;
BEGIN
frm_gen <= FB_frm_gen ;
p2s_load <= FB_p2s_load ;
ch_sel <= FB_ch_sel ;
sm1:
PROCESS (CS_state_mach1_sm1, clk_50, FB_frm_gen, FB_p2s_load, ser_done, a2d_eoc, FB_ch_sel)
BEGIN
CASE CS_state_mach1_sm1 IS
WHEN V_begin =>
FB_frm_gen <= ('1');
a2d_start <= ('0');
a2d_oe <= ('0');
FB_p2s_load <= ('0');
p2s_clr <= ('0');
p2s_oe <= ('0');
FB_ch_sel <= ('0');
parity_oe <= ('0');
ser_cnt <= ('0');
IF ((FB_frm_gen = '1')) THEN
NS_state_mach1_sm1 <= frm_rd;
ELSE
NS_state_mach1_sm1 <= V_begin;
END IF;
WHEN frm_rd =>
FB_p2s_load <= ('1');
IF ((FB_p2s_load = '1')) THEN
NS_state_mach1_sm1 <= ser_oe;
ELSE
NS_state_mach1_sm1 <= frm_rd;
END IF;
WHEN ser_oe =>
p2s_oe <= ('1');
FB_frm_gen <= ('0');
FB_p2s_load <= ('0');
ser_cnt <= ('1');
IF ((ser_done = '1')) THEN
NS_state_mach1_sm1 <= ch1;
ELSE
NS_state_mach1_sm1 <= ser_oe;
END IF;
WHEN ch1 =>
p2s_oe <= ('0');
FB_ch_sel <= ('0');
a2d_start <= ('1');
ser_cnt <= ('0');
IF ((a2d_eoc = '1')) THEN
NS_state_mach1_sm1 <= data_en;
ELSE
NS_state_mach1_sm1 <= ch1;
END IF;
WHEN data_en =>
a2d_start <= ('0');
a2d_oe <= ('1');
parity_oe <= ('1');
NS_state_mach1_sm1 <= load;
WHEN tdm_oe =>
a2d_oe <= ('0');
parity_oe <= ('0');
p2s_oe <= ('1');
FB_p2s_load <= ('0');
ser_cnt <= ('1');
IF (((ser_done = '1') AND (FB_ch_sel = '0'))) THEN
NS_state_mach1_sm1 <= ch2;
ELSE
NS_state_mach1_sm1 <= tdm_oe;
END IF;
WHEN ch2 =>
p2s_oe <= ('0');
ser_cnt <= ('0');
FB_ch_sel <= ('1');
NS_state_mach1_sm1 <= delay;
WHEN load =>
FB_p2s_load <= ('1');
NS_state_mach1_sm1 <= tdm_oe;
WHEN ad_ch2 =>
a2d_start <= ('1');
IF ((a2d_eoc = '1')) THEN
NS_state_mach1_sm1 <= data_en;
ELSE
NS_state_mach1_sm1 <= ad_ch2;
END IF;
WHEN delay =>
NS_state_mach1_sm1 <= ad_ch2;
END CASE;
END PROCESS;
sm1_CTL:
PROCESS (clk_100k, clk_50)
BEGIN
IF (clk_100k'event AND clk_100k='1') THEN
IF (clk_50= '1' ) THEN
CS_state_mach1_sm1 <= V_begin;
ELSE
CS_state_mach1_sm1 <= NS_state_mach1_sm1;
END IF;
END IF;
END PROCESS;
END state_diagram;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sm_cnt is
port(
a2d_eoc : in std_logic;
clk_50 : in std_logic;
clk_100k : in std_logic;
clk_6k : in std_logic;
p2s_load : out std_logic;
p2s_oe : out std_logic;
parity_oe : out std_logic;
a2d_start : out std_logic;
a2d_oe : out std_logic;
frm_gen : out std_logic;
ch_sel : out std_logic;
p2s_clr : out std_logic
);
end sm_cnt;
architecture sm_cnt of sm_cnt is
-- Component declarations
-- Signal declarations
signal serial_cnt : std_logic;
signal XSIG010022 : std_logic;
begin
-- Signal assignments
-- Component instances
bit_cnt1 : entity work.bit_cnt(behavioral)
generic map(
count => 15
)
port map(
bit_in => serial_cnt,
clk => clk_6k,
dly_out => XSIG010022
);
state_mach16 : entity work.state_mach1
port map(
ser_cnt => serial_cnt,
ch_sel => ch_sel,
frm_gen => frm_gen,
a2d_oe => a2d_oe,
a2d_start => a2d_start,
parity_oe => parity_oe,
p2s_oe => p2s_oe,
p2s_load => p2s_load,
p2s_clr => p2s_clr,
clk_6k => clk_6k,
clk_100k => clk_100k,
clk_50 => clk_50,
a2d_eoc => a2d_eoc,
ser_done => XSIG010022
);
end sm_cnt;
--
--This is a VHDL-AMS model of a simple analog to digital converter. The model
--describes the general behavior of A/D converters for system level design and
--verification.
--The format of the digital output is binary coding.
--
--N.B, dout(n-1) is the MSB while dout(0) is the LSB.
--
-- Use IEEE natures and packages
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity a2d_nbit is
generic (
Vmax: REAL := 5.0 ; -- ADC's maximum range
Nbits: INTEGER := 10 ; -- number bits in ADC's output
delay: TIME := 10 us -- ADC's conversion time
);
port (
signal start: in std_logic ; -- Start signal
signal clk: in std_logic ; -- Strobe clock
signal oe: in std_logic ; -- Output enable
terminal ain: ELECTRICAL ; -- ADC's analog input terminal
signal eoc: out std_logic := '0' ; -- End Of Conversion pin
signal dout: out std_logic_vector(0 to (Nbits-1))); -- ADC's digital output signal
end entity a2d_nbit;
architecture sar of a2d_nbit is
type states is (input, convert, output) ; -- Three states of A2D Conversion
constant bit_range : INTEGER := Nbits-1 ; -- Bit range for dtmp and dout
quantity Vin across Iin through ain to electrical_ref; -- ADC's input branch
begin
sa_adc: process
variable thresh: REAL := Vmax ; -- Threshold to test input voltage against
variable Vtmp: REAL := Vin ; -- Snapshot of input voltage when conversion starts
variable dtmp: std_logic_vector(0 to (Nbits-1)); -- Temp. output data
variable status: states := input ; -- Begin with "input" CASE
variable bit_cnt: integer := Nbits -1 ;
begin
CASE status is
when input => -- Read input voltages when start goes high
wait on start until start = '1' or start = 'H' ;
thresh := Vmax ;
Vtmp := Vin ;
eoc <= '0' ;
status := convert ; -- Go to convert state
when convert => -- Begin successive approximation conversion
thresh := thresh / 2.0 ; -- Get value of MSB
wait on clk until clk = '1' OR clk = 'H';
if Vtmp > thresh then
dtmp(bit_cnt) := '1' ;
Vtmp := Vtmp - thresh ;
else
dtmp(bit_cnt) := '0' ;
end if ;
if bit_cnt < 1 then
status := output ; -- Go to output state
end if;
bit_cnt := bit_cnt - 1 ;
when output => -- Wait for output enable, then put data on output pins
eoc <= '1' after delay ;
wait on oe until oe = '1' OR oe = 'H' ;
dout <= dtmp ;
wait on oe until oe = '0' OR oe = 'L' ; -- Hi Z when OE is low
dout <= (others => 'Z') ;
bit_cnt := bit_range ;
status := input ; -- Set up for next conversion
END CASE ;
end process sa_adc ;
Iin == 0.0 ; -- Ideal input draws no current
end architecture sar ;
--
-- Parallel input/serial output shift register
-- With 4 trailing zeros
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity shift_reg is
generic ( td : time := 0 ns);
port
(
bus_in : in std_logic_vector ; -- Input bus
clk : in std_logic ; -- Shift clock
oe : in std_logic ; -- Output enable
ser_out : out std_logic := '0'; -- Output port
load : in std_logic ; -- Parallel input load
clr : in std_logic -- Clear register
);
end entity shift_reg;
architecture behavioral of shift_reg is
begin
control_proc : process
VARIABLE bit_val : std_logic_vector(11 downto 0); -- Default 12-bit input
begin
IF (clr = '1' OR clr = 'H') then
bit_val := "000000000000"; -- Set all input bits to zero
ELSE
wait until load'event AND (load = '1' OR load = 'H');
FOR i IN bus_in'high DOWNTO bus_in'low LOOP
bit_val(i) := bus_in(i) ; -- Transfer input data to variable
END LOOP ;
END IF;
wait until oe'event AND (oe = '1' OR oe = 'H'); -- Shift if output enabled
FOR i IN bit_val'high DOWNTO bit_val'low LOOP
wait until clk'event AND (clk = '1' OR clk = 'H');
ser_out <= bit_val(i) ;
END LOOP ;
FOR i IN 1 TO 4 LOOP -- This loop pads the serial output with 4 zeros
wait until clk'event AND (clk = '1' OR clk = 'H');
ser_out <= '0';
END LOOP;
END process;
end architecture behavioral;
--
-- This model generates a 12-bit data frame synchronization code
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity frame_gen is
port
(
oe : in std_logic := '0';
sync_out : out std_logic_vector (11 downto 0) := "ZZZZZZZZZZZZ");
end entity frame_gen;
architecture simple of frame_gen is
begin
enbl: PROCESS
BEGIN
WAIT ON OE;
IF OE = '1' THEN
sync_out <= "010101010101"; -- Sync code
ELSE
sync_out <= "ZZZZZZZZZZZZ";
END IF;
END PROCESS;
end architecture simple;
--
-- Two input XOR gate
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY xor2 IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
in1, in2 : IN std_logic;
output : OUT std_logic);
END ENTITY xor2;
ARCHITECTURE ideal OF xor2 IS
BEGIN
output <= in1 XOR in2 AFTER delay;
END ARCHITECTURE ideal;
--
-- level_set_tri.vhd
-- If OE = '1' set digital output "level" with parameter "logic_val" (default is 'Z')
-- If OE = '0' set output to high impedance
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY level_set_tri IS
GENERIC (
logic_val : std_logic := 'Z');
PORT (
OE : IN std_logic;
level : OUT std_logic := 'Z');
END ENTITY level_set_tri;
-- Simple architecture
ARCHITECTURE ideal OF level_set_tri IS
BEGIN
oe_ctl: PROCESS
BEGIN
WAIT ON OE;
IF OE = '1' THEN
level <= logic_val;
ELSE
level <= 'Z';
END IF;
END PROCESS;
END ARCHITECTURE ideal;
--
-- Simple Tri-state Buffer with delay time
-- If OE = 1, output = input after delay
-- If OE /= 1, output = Z after delay
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY buffer_tri IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
input : IN std_logic;
OE : IN std_logic;
output : OUT std_logic);
END ENTITY buffer_tri;
ARCHITECTURE ideal OF buffer_tri IS
BEGIN
oe_ctl: PROCESS
BEGIN
WAIT ON OE, input;
IF OE = '1' THEN
output <= input AFTER delay;
ELSE
output <= 'Z' AFTER delay;
END IF;
END PROCESS;
END ARCHITECTURE ideal;
--
-- ideal one bit D/A converter
LIBRARY IEEE_proposed;
USE IEEE_proposed.electrical_systems.ALL;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY d2a_bit IS
GENERIC (vlow : real :=0.0; -- output high voltage
vhigh : real :=5.0); -- output low voltage
PORT (D : IN std_logic; -- digital (std_logic) intout
TERMINAL A : electrical); -- analog (electrical) output
END ENTITY d2a_bit;
ARCHITECTURE ideal OF d2a_bit IS
QUANTITY vout ACROSS iout THROUGH A TO ELECTRICAL_REF;
SIGNAL vin : real := 0.0;
BEGIN
vin <= vhigh WHEN D = '1' ELSE vlow;
-- Use 'RAMP for discontinuous signal
vout == vin'RAMP(1.0e-9);
END ARCHITECTURE ideal;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity parity_gen is
port(
parity : in std_logic_vector(1 to 10);
oe : in std_logic;
parity_out : out std_logic_vector(0 to 11)
);
end parity_gen;
architecture parity_gen of parity_gen is
-- Component declarations
-- Signal declarations
terminal par_bit_gen_a : electrical;
signal XSIG010002 : std_logic;
signal XSIG010003 : std_logic;
signal XSIG010004 : std_logic;
signal XSIG010005 : std_logic;
signal XSIG010006 : std_logic;
signal XSIG010007 : std_logic;
signal XSIG010008 : std_logic;
signal XSIG010009 : std_logic;
signal XSIG010098 : std_logic;
begin
-- Signal assignments
-- Component instances
XCMP1 : entity work.xor2(ideal)
port map(
in1 => parity(1),
in2 => parity(2),
output => XSIG010002
);
XCMP2 : entity work.xor2(ideal)
port map(
in1 => parity(3),
in2 => parity(4),
output => XSIG010003
);
XCMP3 : entity work.xor2(ideal)
port map(
in1 => parity(5),
in2 => parity(6),
output => XSIG010004
);
XCMP4 : entity work.xor2(ideal)
port map(
in1 => parity(7),
in2 => parity(8),
output => XSIG010005
);
XCMP5 : entity work.xor2(ideal)
port map(
in1 => parity(9),
in2 => parity(10),
output => XSIG010008
);
XCMP6 : entity work.xor2(ideal)
port map(
in1 => XSIG010002,
in2 => XSIG010003,
output => XSIG010006
);
XCMP7 : entity work.xor2(ideal)
port map(
in1 => XSIG010004,
in2 => XSIG010005,
output => XSIG010007
);
XCMP8 : entity work.xor2(ideal)
port map(
in1 => XSIG010006,
in2 => XSIG010007,
output => XSIG010009
);
XCMP9 : entity work.xor2(ideal)
port map(
in1 => XSIG010009,
in2 => XSIG010008,
output => XSIG010098
);
XCMP18 : entity work.level_set_tri(ideal)
generic map(
logic_val => '1'
)
port map(
level => parity_out(11),
oe => oe
);
XCMP19 : entity work.buffer_tri(ideal)
port map(
input => parity(1),
output => parity_out(1),
oe => oe
);
XCMP20 : entity work.buffer_tri(ideal)
port map(
input => parity(2),
output => parity_out(2),
oe => oe
);
XCMP21 : entity work.buffer_tri(ideal)
port map(
input => parity(3),
output => parity_out(3),
oe => oe
);
XCMP22 : entity work.buffer_tri(ideal)
port map(
input => parity(4),
output => parity_out(4),
oe => oe
);
XCMP23 : entity work.buffer_tri(ideal)
port map(
input => parity(5),
output => parity_out(5),
oe => oe
);
XCMP24 : entity work.buffer_tri(ideal)
port map(
input => parity(6),
output => parity_out(6),
oe => oe
);
XCMP25 : entity work.buffer_tri(ideal)
port map(
input => parity(7),
output => parity_out(7),
oe => oe
);
XCMP26 : entity work.buffer_tri(ideal)
port map(
input => parity(8),
output => parity_out(8),
oe => oe
);
XCMP27 : entity work.buffer_tri(ideal)
port map(
input => parity(9),
output => parity_out(9),
oe => oe
);
XCMP28 : entity work.buffer_tri(ideal)
port map(
input => parity(10),
output => parity_out(10),
oe => oe
);
XCMP29 : entity work.buffer_tri(ideal)
port map(
input => XSIG010098,
output => parity_out(0),
oe => oe
);
XCMP30 : entity work.d2a_bit(ideal)
port map(
D => XSIG010098,
A => par_bit_gen_a
);
end parity_gen;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity tdm_encoder is
port(
clk : in std_logic;
p2s_oe : in std_logic;
p2s_load : in std_logic;
frm_gen : in std_logic;
parity_oe : in std_logic;
tdm_out : out std_logic;
p2s_clr : in std_logic;
a2d_data : in std_logic_vector(1 to 10)
);
end tdm_encoder;
architecture tdm_encoder of tdm_encoder is
-- Component declarations
-- Signal declarations
signal sync_par : std_logic_vector(0 to 11);
begin
-- Signal assignments
-- Component instances
p2s1 : entity work.shift_reg(behavioral)
port map(
bus_in => sync_par,
clk => clk,
oe => p2s_oe,
ser_out => tdm_out,
load => p2s_load,
clr => p2s_clr
);
sync_gen1 : entity work.frame_gen(simple)
port map(
oe => frm_gen,
sync_out => sync_par
);
par_gen1 : entity work.parity_gen
port map(
parity => a2d_data,
parity_out => sync_par,
oe => parity_oe
);
end tdm_encoder;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity Digitize_Encode is
port(
tdm_out : out std_logic;
terminal ch1_in : electrical;
terminal ch2_in : electrical
);
end Digitize_Encode;
architecture Digitize_Encode of Digitize_Encode is
-- Component declarations
-- Signal declarations
terminal a2d_ana_in : electrical;
signal a2d_oe : std_logic;
signal ch_bus : std_logic_vector(1 to 10);
signal frm_gen_ctl : std_logic;
signal p2s_clr : std_logic;
signal p2s_load : std_logic;
signal p2s_oe : std_logic;
signal par_oe : std_logic;
signal start_a2d1 : std_logic;
signal sw_ctl : std_logic;
signal XSIG010091 : std_logic;
signal XSIG010173 : std_logic;
signal XSIG010180 : std_logic;
signal XSIG010181 : std_logic;
begin
-- Signal assignments
-- Component instances
A_SWITCH1 : entity work.switch_dig_2in(ideal)
port map(
p_in1 => ch1_in,
p_out => a2d_ana_in,
sw_state => sw_ctl,
p_in2 => ch2_in
);
rc_clk2 : entity work.rc_clk
port map(
clk_50 => XSIG010180,
clk_6K => XSIG010173,
clk_100k => XSIG010181
);
sm_xmtr1 : entity work.sm_cnt
port map(
clk_100k => XSIG010181,
a2d_start => start_a2d1,
a2d_eoc => XSIG010091,
p2s_oe => p2s_oe,
p2s_load => p2s_load,
ch_sel => sw_ctl,
frm_gen => frm_gen_ctl,
parity_oe => par_oe,
a2d_oe => a2d_oe,
clk_50 => XSIG010180,
clk_6k => XSIG010173,
p2s_clr => p2s_clr
);
a2d1 : entity work.a2d_nbit(sar)
generic map(
Vmax => 4.8
)
port map(
dout => ch_bus,
ain => a2d_ana_in,
clk => XSIG010181,
start => start_a2d1,
eoc => XSIG010091,
oe => a2d_oe
);
tdm_enc1 : entity work.tdm_encoder
port map(
clk => XSIG010173,
p2s_oe => p2s_oe,
tdm_out => tdm_out,
p2s_load => p2s_load,
a2d_data => ch_bus,
frm_gen => frm_gen_ctl,
parity_oe => par_oe,
p2s_clr => p2s_clr
);
end Digitize_Encode;
--
-- Electrical sinusoidal voltage source (stick.vhd)
LIBRARY IEEE;
USE IEEE.MATH_REAL.ALL;
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
ENTITY stick IS
-- Initialize parameters
GENERIC (
freq : real; -- frequency, [Hertz]
amplitude : real; -- amplitude, [Volt]
phase : real := 0.0; -- initial phase, [Degree]
offset : real := 0.0; -- DC value, [Volt]
df : real := 0.0; -- damping factor, [1/second]
ac_mag : real := 1.0; -- AC magnitude, [Volt]
ac_phase : real := 0.0); -- AC phase, [Degree]
-- Define ports as electrical terminals
PORT (
TERMINAL v_out : ELECTRICAL);
END ENTITY stick;
-- Ideal Architecture
ARCHITECTURE ideal OF stick IS
-- Declare Branch Quantities
QUANTITY v ACROSS i THROUGH v_out TO electrical_ref;
-- Declare Quantity for Phase in radians (calculated below)
QUANTITY phase_rad : real;
-- Declare Quantity in frequency domain for AC analysis
QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
BEGIN
-- Convert phase to radians
phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
IF DOMAIN = QUIESCENT_DOMAIN OR DOMAIN = TIME_DOMAIN USE
v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
ELSE
v == ac_spec; -- used for Frequency (AC) analysis
END USE;
END ARCHITECTURE ideal;
--
-- Two input AND gate
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY and2 IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
in1, in2 : IN std_logic;
output : OUT std_logic);
END ENTITY and2;
ARCHITECTURE ideal OF and2 IS
BEGIN
output <= in1 AND in2 AFTER delay;
END ARCHITECTURE ideal;
--
-- D Flip Flop with reset (negative edge triggered)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY d_latch_n_edge_rst IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
data, clk : IN std_logic;
q : OUT std_logic := '0';
qn : OUT std_logic := '1';
rst : IN std_logic := '0'); -- reset
END ENTITY d_latch_n_edge_rst ;
ARCHITECTURE behav OF d_latch_n_edge_rst IS
BEGIN
data_in : PROCESS(clk, rst) IS
BEGIN
IF clk = '0' AND clk'event AND rst /= '1' THEN
q <= data AFTER delay;
qn <= NOT data AFTER delay;
ELSIF rst = '1' THEN
q <= '0';
qn <= '1';
END IF;
END PROCESS data_in; -- End of process data_in
END ARCHITECTURE behav;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity counter_12 is
port(
cnt : out std_logic_vector(0 to 11);
reset : in std_logic;
enable : in std_logic;
clk : in std_logic
);
end counter_12;
architecture counter_12 of counter_12 is
-- Component declarations
-- Signal declarations
signal cdb2vhdl_tmp_1 : std_logic_vector(0 to 11);
signal XSIG010078 : std_logic;
signal XSIG010081 : std_logic;
signal XSIG010083 : std_logic;
signal XSIG010085 : std_logic;
signal XSIG010087 : std_logic;
signal XSIG010101 : std_logic;
signal XSIG010102 : std_logic;
signal XSIG010103 : std_logic;
signal XSIG010104 : std_logic;
signal XSIG010115 : std_logic;
signal XSIG010116 : std_logic;
signal XSIG010117 : std_logic;
signal XSIG010132 : std_logic;
begin
-- Signal assignments
cnt(0) <= cdb2vhdl_tmp_1(0);
cnt(1) <= cdb2vhdl_tmp_1(1);
cnt(2) <= cdb2vhdl_tmp_1(2);
cnt(3) <= cdb2vhdl_tmp_1(3);
cnt(4) <= cdb2vhdl_tmp_1(4);
cnt(5) <= cdb2vhdl_tmp_1(5);
cnt(6) <= cdb2vhdl_tmp_1(6);
cnt(7) <= cdb2vhdl_tmp_1(7);
cnt(8) <= cdb2vhdl_tmp_1(8);
cnt(9) <= cdb2vhdl_tmp_1(9);
cnt(10) <= cdb2vhdl_tmp_1(10);
cnt(11) <= cdb2vhdl_tmp_1(11);
-- Component instances
XCMP92 : entity work.and2(ideal)
port map(
in1 => clk,
in2 => enable,
output => XSIG010132
);
XCMP93 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => XSIG010132,
DATA => XSIG010078,
QN => XSIG010078,
Q => cdb2vhdl_tmp_1(0),
RST => reset
);
XCMP94 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(0),
DATA => XSIG010081,
QN => XSIG010081,
Q => cdb2vhdl_tmp_1(1),
RST => reset
);
XCMP95 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(1),
DATA => XSIG010083,
QN => XSIG010083,
Q => cdb2vhdl_tmp_1(2),
RST => reset
);
XCMP96 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(2),
DATA => XSIG010085,
QN => XSIG010085,
Q => cdb2vhdl_tmp_1(3),
RST => reset
);
XCMP97 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(3),
DATA => XSIG010087,
QN => XSIG010087,
Q => cdb2vhdl_tmp_1(4),
RST => reset
);
XCMP98 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(4),
DATA => XSIG010101,
QN => XSIG010101,
Q => cdb2vhdl_tmp_1(5),
RST => reset
);
XCMP99 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(5),
DATA => XSIG010102,
QN => XSIG010102,
Q => cdb2vhdl_tmp_1(6),
RST => reset
);
XCMP100 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(6),
DATA => XSIG010103,
QN => XSIG010103,
Q => cdb2vhdl_tmp_1(7),
RST => reset
);
XCMP101 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(7),
DATA => XSIG010104,
QN => XSIG010104,
Q => cdb2vhdl_tmp_1(8),
RST => reset
);
XCMP102 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(8),
DATA => XSIG010115,
QN => XSIG010115,
Q => cdb2vhdl_tmp_1(9),
RST => reset
);
XCMP103 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(9),
DATA => XSIG010116,
QN => XSIG010116,
Q => cdb2vhdl_tmp_1(10),
RST => reset
);
XCMP104 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(10),
DATA => XSIG010117,
QN => XSIG010117,
Q => cdb2vhdl_tmp_1(11),
RST => reset
);
end counter_12;
--
-- ideal one bit A/D converter
LIBRARY IEEE;
USE IEEE.math_real.ALL;
USE IEEE.std_logic_1164.ALL;
LIBRARY IEEE_proposed;
USE IEEE_proposed.electrical_systems.ALL;
ENTITY a2d_bit IS
GENERIC (
thres : real := 2.5); -- Threshold to determine logic output
PORT (
TERMINAL a : electrical; -- analog input
SIGNAL d : OUT std_logic); -- digital (std_logic) output
END ENTITY a2d_bit;
ARCHITECTURE ideal OF a2d_bit IS
QUANTITY vin ACROSS a;
BEGIN -- threshold
-- Process needed to detect threshold crossing and assign output (d)
PROCESS (vin'ABOVE(thres)) IS
BEGIN -- PROCESS
IF vin'ABOVE(thres) THEN
d <= '1';
ELSE
d <= '0';
END IF;
END PROCESS;
END ideal;
-- Digital clock with 50% duty cycle and enable pin
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clock_en IS
GENERIC (
pw : time); -- Clock pulse width
PORT (
enable : IN std_logic ;
clock_out : INOUT std_logic := '0');
END ENTITY clock_en;
ARCHITECTURE ideal OF clock_en IS
BEGIN
-- clock process
process (clock_out, enable) is
begin
if clock_out = '0' AND enable = '1' THEN
clock_out <= '1' after pw, '0' after 2*pw;
end if;
end process;
END ARCHITECTURE ideal;
--
-- Inverter
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY inverter IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
input : IN std_logic;
output : OUT std_logic);
END ENTITY inverter;
ARCHITECTURE ideal OF inverter IS
BEGIN
output <= NOT input AFTER delay;
END ARCHITECTURE ideal;
--
-- Two input OR gate
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY or2 IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
in1, in2 : IN std_logic;
output : OUT std_logic);
END ENTITY or2;
ARCHITECTURE ideal OF or2 IS
BEGIN
output <= in1 OR in2 AFTER delay;
END ARCHITECTURE ideal;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
ENTITY d2a_nbit IS
GENERIC (
vmax : real := 5.0; -- High output
vmin : real := 0.0; -- Low output
high_bit : integer := 9; -- High end of bit range for D/A
low_bit : integer := 0); -- Low end of bit range for D/A
PORT (
SIGNAL bus_in : IN STD_LOGIC_VECTOR; -- variable width vector input
SIGNAL latch : IN STD_LOGIC;
TERMINAL ana_out : electrical); -- analog output
END ENTITY d2a_nbit ;
ARCHITECTURE behavioral OF d2a_nbit IS
SIGNAL sout : real := 0.0;
QUANTITY vout across iout through ana_out TO electrical_ref;
BEGIN -- ARCHITECTURE behavioral
proc : PROCESS
VARIABLE v_sum : real; -- Sum of voltage contribution from each bit
VARIABLE delt_v : real; -- Represents the voltage value of each bit
BEGIN
WAIT UNTIL (latch'event and latch = '1'); -- Begin when latch goes high
v_sum := vmin;
delt_v := vmax - vmin;
FOR i IN high_bit DOWNTO low_bit LOOP -- Perform the conversions
delt_v := delt_v / 2.0;
IF bus_in(i) = '1' OR bus_in(i) = 'H' THEN
v_sum := v_sum + delt_v;
END IF;
END LOOP;
sout <= v_sum;
END PROCESS;
vout == sout'ramp(100.0E-9); -- Ensure continuous transition between levels
END ARCHITECTURE behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity pw2ana is
port(
terminal ana_out : electrical;
terminal pw_in : electrical
);
end pw2ana;
architecture pw2ana of pw2ana is
-- Component declarations
-- Signal declarations
signal bus_servo : std_logic_vector(0 to 11);
signal XSIG010008 : std_logic;
signal XSIG010013 : std_logic;
signal XSIG010019 : std_logic;
signal XSIG010020 : std_logic;
signal XSIG010021 : std_logic;
signal XSIG010022 : std_logic;
begin
-- Signal assignments
-- Component instances
counter_rudder : entity work.counter_12
port map(
enable => XSIG010022,
cnt => bus_servo,
reset => XSIG010021,
clk => XSIG010008
);
XCMP3 : entity work.a2d_bit(ideal)
port map(
D => XSIG010022,
A => pw_in
);
clk_en_rudder : entity work.clock_en(ideal)
generic map(
pw => 500 ns
)
port map(
CLOCK_OUT => XSIG010008,
enable => XSIG010022
);
XCMP5 : entity work.inverter(ideal)
generic map(
delay => 2 us
)
port map(
input => XSIG010022,
output => XSIG010013
);
XCMP8 : entity work.inverter(ideal)
generic map(
delay => 2 us
)
port map(
input => XSIG010020,
output => XSIG010021
);
XCMP9 : entity work.inverter(ideal)
generic map(
delay => 2 us
)
port map(
input => XSIG010022,
output => XSIG010019
);
or_rudder : entity work.or2(ideal)
port map(
in1 => XSIG010022,
in2 => XSIG010019,
output => XSIG010020
);
DA1 : entity work.d2a_nbit(behavioral)
generic map(
vmax => 4.8,
high_bit => 9,
low_bit => 0
)
port map(
bus_in => bus_servo,
ana_out => ana_out,
latch => XSIG010013
);
end pw2ana;
--
-- 12-bit digital comparator model
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity dig_cmp is
port
(
eq : out std_logic := '0';
in1 : in std_logic_vector (0 to 11);
in2 : in std_logic_vector (0 to 11);
latch_in1 : in std_logic := '0'; -- Currently unused
latch_in2 : in std_logic := '0';
cmp : in std_logic := '0';
clk : in std_logic
);
end entity dig_cmp ;
architecture simple of dig_cmp is
begin
compare: PROCESS (latch_in2, cmp, clk) -- Sensitivity list
variable in2_hold : std_logic_vector (0 to 11) := "000000000000";
BEGIN
if latch_in2 = '1' then -- in2 data is latched and stored
in2_hold := in2;
end if;
if cmp = '1' then
if in1 = in2_hold then -- latched in2 checked against current in1
eq <= '0';
else eq <= '1';
end if;
end if;
END PROCESS;
end architecture simple;
-- Set/reset flip flop
-- When S goes high, Q is set high until reset
-- When R goes high, Q is set low until set
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sr_ff is
port
(
S : in std_logic ;
R : in std_logic ;
Q : out std_logic
);
end sr_ff ;
architecture simple of sr_ff is
begin
set_reset: PROCESS(S, R) IS
BEGIN
-- assert S='1' nand R='1' -- Warning if both inputs are high
-- report "S and R are both active. Use with caution"
-- severity warning;
if S'event AND S = '1' then
Q <= '1';
end if;
if R'event AND R = '1' then
Q <= '0';
end if;
END PROCESS set_reset;
end;
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
LIBRARY IEEE_proposed;
USE IEEE_proposed.electrical_systems.all;
USE IEEE_proposed.mechanical_systems.all;
ENTITY state_mach_rcvr IS
PORT (
clk_50 : IN std_logic;
clk_100k : IN std_logic;
ser_done : IN std_logic;
par_det : IN std_logic;
frm_det : IN std_logic;
clk_6k : IN std_logic;
start_pulse : IN std_logic;
dly_done : IN std_logic;
s2p_rst : OUT std_logic;
s2p_en : OUT std_logic;
cnt1_en : OUT std_logic;
cnt1_rst : OUT std_logic;
cmp1_ltch1 : OUT std_logic;
cmp1_ltch2 : OUT std_logic;
cnt2_en : OUT std_logic;
cnt2_rst : OUT std_logic;
cmp2_ltch1 : OUT std_logic;
cmp2_ltch2 : OUT std_logic;
da_latch : OUT std_logic;
ser_cnt : OUT std_logic;
dly_cnt : OUT std_logic;
par_oe : OUT std_logic);
END state_mach_rcvr;
ARCHITECTURE state_diagram OF state_mach_rcvr IS
ATTRIBUTE ENUM_TYPE_ENCODING: STRING;
TYPE TYP_state_mach_rcvr_sm1 IS (V_begin, cnt, ch1, rst1, ch2, rst2, cnt_cmp, rst_cnt
, s_bit, par1, par2);
SIGNAL CS_state_mach_rcvr_sm1, NS_state_mach_rcvr_sm1 : TYP_state_mach_rcvr_sm1;
BEGIN
sm1:
PROCESS (CS_state_mach_rcvr_sm1, clk_50, frm_det, ser_done, start_pulse, dly_done, par_det)
BEGIN
CASE CS_state_mach_rcvr_sm1 IS
WHEN V_begin =>
cnt1_en <= ('0');
cnt1_rst <= ('1');
cmp1_ltch1 <= ('0');
cmp1_ltch2 <= ('0');
cnt2_en <= ('0');
cnt2_rst <= ('1');
cmp2_ltch1 <= ('0');
cmp2_ltch2 <= ('0');
s2p_en <= ('1');
s2p_rst <= ('0');
da_latch <= ('0');
ser_cnt <= ('0');
dly_cnt <= ('0');
par_oe <= ('0');
IF ((frm_det = '1')) THEN
NS_state_mach_rcvr_sm1 <= s_bit;
ELSE
NS_state_mach_rcvr_sm1 <= V_begin;
END IF;
WHEN cnt =>
ser_cnt <= ('1');
cnt1_rst <= ('0');
cnt2_rst <= ('0');
IF ((ser_done = '1')) THEN
NS_state_mach_rcvr_sm1 <= par1;
ELSE
NS_state_mach_rcvr_sm1 <= cnt;
END IF;
WHEN ch1 =>
cmp1_ltch2 <= ('1');
ser_cnt <= ('0');
dly_cnt <= ('1');
IF (((start_pulse = '1') AND (dly_done = '1'))) THEN
NS_state_mach_rcvr_sm1 <= rst1;
ELSE
NS_state_mach_rcvr_sm1 <= ch1;
END IF;
WHEN rst1 =>
cmp1_ltch2 <= ('0');
ser_cnt <= ('1');
dly_cnt <= ('0');
par_oe <= ('0');
IF ((ser_done = '1')) THEN
NS_state_mach_rcvr_sm1 <= par2;
ELSE
NS_state_mach_rcvr_sm1 <= rst1;
END IF;
WHEN ch2 =>
cmp2_ltch2 <= ('1');
ser_cnt <= ('0');
da_latch <= ('1');
NS_state_mach_rcvr_sm1 <= rst2;
WHEN rst2 =>
cmp2_ltch2 <= ('0');
s2p_en <= ('0');
par_oe <= ('0');
da_latch <= ('0');
NS_state_mach_rcvr_sm1 <= cnt_cmp;
WHEN cnt_cmp =>
cnt1_en <= ('1');
cmp1_ltch1 <= ('1');
cnt2_en <= ('1');
cmp2_ltch1 <= ('1');
NS_state_mach_rcvr_sm1 <= rst_cnt;
WHEN rst_cnt =>
cnt1_en <= ('0');
cmp1_ltch1 <= ('0');
cnt2_en <= ('0');
cmp2_ltch1 <= ('0');
NS_state_mach_rcvr_sm1 <= rst_cnt;
WHEN s_bit =>
IF ((start_pulse = '1')) THEN
NS_state_mach_rcvr_sm1 <= cnt;
ELSE
NS_state_mach_rcvr_sm1 <= s_bit;
END IF;
WHEN par1 =>
par_oe <= ('1');
IF ((par_det = '0')) THEN
NS_state_mach_rcvr_sm1 <= ch1;
ELSIF ((par_det = '1')) THEN
NS_state_mach_rcvr_sm1 <= rst1;
ELSE
NS_state_mach_rcvr_sm1 <= par1;
END IF;
WHEN par2 =>
par_oe <= ('1');
IF ((par_det = '0')) THEN
NS_state_mach_rcvr_sm1 <= ch2;
ELSIF ((par_det = '1')) THEN
NS_state_mach_rcvr_sm1 <= rst2;
ELSE
NS_state_mach_rcvr_sm1 <= par2;
END IF;
END CASE;
END PROCESS;
sm1_CTL:
PROCESS (clk_100k, clk_50)
BEGIN
IF (clk_100k'event AND clk_100k='1') THEN
IF (clk_50= '1' ) THEN
CS_state_mach_rcvr_sm1 <= V_begin;
ELSE
CS_state_mach_rcvr_sm1 <= NS_state_mach_rcvr_sm1;
END IF;
END IF;
END PROCESS;
END state_diagram;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sm_cnt_rcvr is
port(
cmp1_ltch1 : out std_logic;
cmp2_ltch1 : out std_logic;
s2p_en : out std_logic;
s2p_rst : out std_logic;
frm_det : in std_logic;
par_det : in std_logic;
clk_100k : in std_logic;
clk_6k : in std_logic;
clk_50 : in std_logic;
start_pulse : in std_logic;
cnt1_en : out std_logic;
cnt1_rst : out std_logic;
cmp1_ltch2 : out std_logic;
cnt2_en : out std_logic;
cnt2_rst : out std_logic;
cmp2_ltch2 : out std_logic;
da_latch : out std_logic;
par_oe : out std_logic
);
end sm_cnt_rcvr;
architecture sm_cnt_rcvr of sm_cnt_rcvr is
-- Component declarations
-- Signal declarations
signal ser_cnt : std_logic;
signal XSIG010002 : std_logic;
signal XSIG010145 : std_logic;
signal XSIG010146 : std_logic;
begin
-- Signal assignments
-- Component instances
bit_cnt3 : entity work.bit_cnt(behavioral)
generic map(
count => 2
)
port map(
bit_in => XSIG010145,
clk => clk_6k,
dly_out => XSIG010146
);
bit_cnt4 : entity work.bit_cnt(behavioral)
generic map(
count => 10
)
port map(
bit_in => ser_cnt,
clk => clk_6k,
dly_out => XSIG010002
);
state_mach_rcvr8 : entity work.state_mach_rcvr
port map(
clk_100k => clk_100k,
clk_50 => clk_50,
s2p_rst => s2p_rst,
s2p_en => s2p_en,
cnt1_en => cnt1_en,
cnt1_rst => cnt1_rst,
cmp1_ltch1 => cmp1_ltch1,
cmp1_ltch2 => cmp1_ltch2,
cnt2_en => cnt2_en,
cnt2_rst => cnt2_rst,
cmp2_ltch1 => cmp2_ltch1,
cmp2_ltch2 => cmp2_ltch2,
da_latch => da_latch,
ser_cnt => ser_cnt,
ser_done => XSIG010002,
par_det => par_det,
frm_det => frm_det,
clk_6k => clk_6k,
start_pulse => start_pulse,
dly_done => XSIG010146,
dly_cnt => XSIG010145,
par_oe => par_oe
);
end sm_cnt_rcvr;
--
-- level_set.vhd
-- Set digital output "level" with parameter "logic_val" (default is '1')
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY level_set IS
GENERIC (
logic_val : std_logic := '1');
PORT (
level : OUT std_logic);
END ENTITY level_set;
-- Simple architecture
ARCHITECTURE ideal OF level_set IS
BEGIN
level <= logic_val;
END ARCHITECTURE ideal;
--
-- Serial to parallel data converter
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity ser2par is
port
(
par_out : inout std_logic_vector(0 to 11) := "ZZZZZZZZZZZZ";
clk : in std_logic ;
load_en : in std_logic ;
ser_in : in std_logic ;
reset : in std_logic
);
begin
end ser2par;
architecture a1 of ser2par is
BEGIN
sr_sm: PROCESS (load_en, clk, reset, ser_in)
BEGIN
if (reset = '1' and load_en = '1') then
par_out <= "000000000000"; -- Reset the parallel data out
elsif (reset = '0' and load_en = '1') then
if (clk'event and clk = '1') then
-- The register will shift when load is enabled
-- and will shift at rising edge of clock
par_out(0) <= ser_in; -- Input data shifts into bit 0
par_out(1) <= par_out(0);
par_out(2) <= par_out(1);
par_out(3) <= par_out(2);
par_out(4) <= par_out(3);
par_out(5) <= par_out(4);
par_out(6) <= par_out(5);
par_out(7) <= par_out(6);
par_out(8) <= par_out(7);
par_out(9) <= par_out(8);
par_out(10) <= par_out(9);
par_out(11) <= par_out(10);
end if;
else
par_out <= "ZZZZZZZZZZZZ"; -- No change in output. Tri-state if load_en = 0.
end if;
END PROCESS;
end;
--
-- This model ouputs a '1' when a specific bit pattern is encountered
-- Otherwise, it outputs a zero
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity frame_det is
port
(
bus_in : in std_logic_vector (0 to 11);
clk : in std_logic;
frm_bit : out std_logic := '0' -- Initialize output to zero
);
end entity frame_det;
architecture simple of frame_det is
begin
enbl: PROCESS (bus_in, clk) -- Sensitivity list
BEGIN
if bus_in = "010101010101" then -- This is the pre-defined bit pattern
if clk'event AND clk = '0' then -- Output updated synchronously
frm_bit <= '1';
end if;
else frm_bit <= '0';
end if;
END PROCESS;
end architecture simple;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity parity_det is
port(
bus_in : in std_logic_vector(0 to 11);
par_bit : out std_logic;
oe : in std_logic
);
end parity_det;
architecture parity_det of parity_det is
-- Component declarations
-- Signal declarations
signal XSIG010010 : std_logic;
signal XSIG010011 : std_logic;
signal XSIG010012 : std_logic;
signal XSIG010013 : std_logic;
signal XSIG010014 : std_logic;
signal XSIG010015 : std_logic;
signal XSIG010016 : std_logic;
signal XSIG010017 : std_logic;
signal XSIG010019 : std_logic;
signal XSIG010057 : std_logic;
begin
-- Signal assignments
-- Component instances
XCMP1 : entity work.xor2(ideal)
port map(
in1 => bus_in(1),
in2 => bus_in(2),
output => XSIG010010
);
XCMP2 : entity work.xor2(ideal)
port map(
in1 => bus_in(3),
in2 => bus_in(4),
output => XSIG010011
);
XCMP3 : entity work.xor2(ideal)
port map(
in1 => bus_in(5),
in2 => bus_in(6),
output => XSIG010012
);
XCMP4 : entity work.xor2(ideal)
port map(
in1 => bus_in(7),
in2 => bus_in(8),
output => XSIG010013
);
XCMP5 : entity work.xor2(ideal)
port map(
in1 => bus_in(9),
in2 => bus_in(10),
output => XSIG010016
);
XCMP6 : entity work.xor2(ideal)
port map(
in1 => XSIG010010,
in2 => XSIG010011,
output => XSIG010014
);
XCMP7 : entity work.xor2(ideal)
port map(
in1 => XSIG010012,
in2 => XSIG010013,
output => XSIG010015
);
XCMP8 : entity work.xor2(ideal)
port map(
in1 => XSIG010014,
in2 => XSIG010015,
output => XSIG010017
);
XCMP9 : entity work.xor2(ideal)
port map(
in1 => XSIG010017,
in2 => XSIG010016,
output => XSIG010019
);
XCMP10 : entity work.xor2(ideal)
port map(
in1 => XSIG010019,
in2 => bus_in(0),
output => XSIG010057
);
XCMP12 : entity work.and2(ideal)
port map(
in1 => oe,
in2 => XSIG010057,
output => par_bit
);
end parity_det;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity TDM_Demux_dbg is
port(
s2p_en : in std_logic;
tdm_in : in std_logic;
clk_6k : in std_logic;
s2p_rst : in std_logic;
par_det : out std_logic;
frm_det : out std_logic;
da_latch : in std_logic;
par_oe : in std_logic;
data_bus : out std_logic_vector(1 to 10);
start_bit : out std_logic
);
end TDM_Demux_dbg;
architecture TDM_Demux_dbg of TDM_Demux_dbg is
-- Component declarations
-- Signal declarations
terminal d2a_out : electrical;
signal rcvr_bus : std_logic_vector(0 to 11);
begin
-- Signal assignments
data_bus(1) <= rcvr_bus(1);
data_bus(2) <= rcvr_bus(2);
data_bus(3) <= rcvr_bus(3);
data_bus(4) <= rcvr_bus(4);
data_bus(5) <= rcvr_bus(5);
data_bus(6) <= rcvr_bus(6);
data_bus(7) <= rcvr_bus(7);
data_bus(8) <= rcvr_bus(8);
data_bus(9) <= rcvr_bus(9);
data_bus(10) <= rcvr_bus(10);
start_bit <= rcvr_bus(0);
-- Component instances
s2p1 : entity work.ser2par(a1)
port map(
par_out => rcvr_bus,
clk => clk_6k,
load_en => s2p_en,
ser_in => tdm_in,
reset => s2p_rst
);
frm_det1 : entity work.frame_det(simple)
port map(
bus_in => rcvr_bus,
frm_bit => frm_det,
clk => clk_6k
);
par_det1 : entity work.parity_det
port map(
bus_in => rcvr_bus,
par_bit => par_det,
oe => par_oe
);
XCMP113 : entity work.d2a_nbit(behavioral)
generic map(
low_bit => 1,
high_bit => 10,
vmax => 4.8
)
port map(
bus_in => rcvr_bus(1 to 10),
ana_out => d2a_out,
latch => da_latch
);
end TDM_Demux_dbg;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity Decode_PW is
port(
bit_stream_in : in std_logic;
terminal ch1_pw : electrical;
terminal ch2_pw : electrical
);
end Decode_PW;
architecture Decode_PW of Decode_PW is
-- Component declarations
-- Signal declarations
signal cmp_bus : std_logic_vector(0 to 11);
signal cnt1 : std_logic_vector(0 to 11);
signal cnt2 : std_logic_vector(0 to 11);
signal rud_clk : std_logic;
signal rud_cmp : std_logic;
signal rud_eq : std_logic;
signal rud_ff_rst : std_logic;
signal rud_ff_set : std_logic;
signal rud_ltch1 : std_logic;
signal rud_ltch2 : std_logic;
signal XSIG010225 : std_logic;
signal XSIG010228 : std_logic;
signal XSIG010229 : std_logic;
signal XSIG010256 : std_logic;
signal XSIG010266 : std_logic;
signal XSIG010267 : std_logic;
signal XSIG010268 : std_logic;
signal XSIG010289 : std_logic;
signal XSIG010315 : std_logic;
signal XSIG010339 : std_logic;
signal XSIG010357 : std_logic;
signal XSIG010371 : std_logic;
signal XSIG010373 : std_logic;
signal XSIG010383 : std_logic;
signal XSIG010384 : std_logic;
signal XSIG010385 : std_logic;
signal XSIG010386 : std_logic;
signal XSIG010390 : std_logic;
signal XSIG010433 : std_logic;
begin
-- Signal assignments
-- Component instances
cntr1 : entity work.counter_12
port map(
enable => XSIG010384,
cnt => cnt1,
reset => XSIG010357,
clk => XSIG010433
);
cntr2 : entity work.counter_12
port map(
enable => rud_cmp,
cnt => cnt2,
reset => XSIG010385,
clk => rud_clk
);
cmp1 : entity work.dig_cmp(simple)
port map(
in1 => cnt1,
eq => XSIG010371,
clk => XSIG010433,
in2 => cmp_bus,
cmp => XSIG010384,
latch_in1 => XSIG010256,
latch_in2 => XSIG010383
);
cmp2 : entity work.dig_cmp(simple)
port map(
in1 => cnt2,
eq => rud_eq,
clk => rud_clk,
in2 => cmp_bus,
cmp => rud_cmp,
latch_in1 => rud_ltch1,
latch_in2 => rud_ltch2
);
clk_1M2 : entity work.clock_en(ideal)
generic map(
pw => 500 ns
)
port map(
CLOCK_OUT => rud_clk,
enable => rud_cmp
);
clk_1M1 : entity work.clock_en(ideal)
generic map(
pw => 500 ns
)
port map(
CLOCK_OUT => XSIG010433,
enable => XSIG010384
);
XCMP134 : entity work.d2a_bit(ideal)
port map(
D => XSIG010371,
A => ch1_pw
);
XCMP135 : entity work.d2a_bit(ideal)
port map(
D => rud_eq,
A => ch2_pw
);
XCMP137 : entity work.SR_FF(simple)
port map(
S => rud_ff_set,
R => rud_ff_rst,
Q => rud_cmp
);
XCMP138 : entity work.inverter(ideal)
port map(
input => rud_eq,
output => rud_ff_rst
);
XCMP139 : entity work.SR_FF(simple)
port map(
S => XSIG010373,
R => XSIG010339,
Q => XSIG010384
);
XCMP140 : entity work.inverter(ideal)
port map(
input => XSIG010371,
output => XSIG010339
);
rc_clk2 : entity work.rc_clk
port map(
clk_50 => XSIG010289,
clk_6K => XSIG010225,
clk_100k => XSIG010315
);
sm_rcvr1 : entity work.sm_cnt_rcvr
port map(
cnt1_en => XSIG010373,
cmp1_ltch1 => XSIG010256,
cnt2_rst => XSIG010385,
clk_100k => XSIG010315,
cnt1_rst => XSIG010357,
cnt2_en => rud_ff_set,
cmp2_ltch1 => rud_ltch1,
frm_det => XSIG010229,
par_det => XSIG010228,
s2p_en => XSIG010266,
s2p_rst => XSIG010267,
clk_6k => XSIG010225,
clk_50 => XSIG010289,
da_latch => XSIG010268,
cmp1_ltch2 => XSIG010383,
cmp2_ltch2 => rud_ltch2,
start_pulse => XSIG010390,
par_oe => XSIG010386
);
XCMP155 : entity work.level_set(ideal)
generic map(
logic_val => '0'
)
port map(
level => cmp_bus(11)
);
XCMP157 : entity work.TDM_Demux_dbg
port map(
data_bus => cmp_bus(0 to 9),
tdm_in => bit_stream_in,
clk_6k => XSIG010225,
s2p_en => XSIG010266,
s2p_rst => XSIG010267,
da_latch => XSIG010268,
frm_det => XSIG010229,
par_det => XSIG010228,
par_oe => XSIG010386,
start_bit => XSIG010390
);
XCMP172 : entity work.level_set(ideal)
generic map(
logic_val => '1'
)
port map(
level => cmp_bus(10)
);
end Decode_PW;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity tb_CS1 is
end tb_CS1;
architecture TB_CS1 of tb_CS1 is
-- Component declarations
-- Signal declarations
terminal rudder : electrical;
terminal rudder_out : electrical;
terminal rudder_servo : electrical;
signal tdm_stream2 : std_logic;
terminal throttle : electrical;
terminal throttle_out : electrical;
terminal throttle_servo : electrical;
begin
-- Signal assignments
-- Component instances
Digitize_Encode1 : entity work.Digitize_Encode
port map(
ch2_in => rudder,
ch1_in => throttle,
tdm_out => tdm_stream2
);
throttle_1 : entity work.stick(ideal)
generic map(
freq => 1.0,
amplitude => 2.397,
phase => 0.0,
offset => 2.397
)
port map(
v_out => throttle
);
rudder_1 : entity work.stick(ideal)
generic map(
offset => 2.397,
phase => 90.0,
amplitude => 2.397,
freq => 1.0
)
port map(
v_out => rudder
);
pw2ana1 : entity work.pw2ana
port map(
ana_out => throttle_out,
pw_in => throttle_servo
);
pw2ana2 : entity work.pw2ana
port map(
ana_out => rudder_out,
pw_in => rudder_servo
);
Decode_PW10 : entity work.Decode_PW
port map(
bit_stream_in => tdm_stream2,
ch2_pw => rudder_servo,
ch1_pw => throttle_servo
);
end TB_CS1;
--
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:28:55 11/19/2013
-- Design Name:
-- Module Name: C:/Users/etingi01/Mips32_948282_19.11.2013/My_16bitAdder_tb_948282.vhd
-- Project Name: Mips32_948282_19.11.2013
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: My_16bitAdder_948282
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY My_16bitAdder_tb_948282 IS
END My_16bitAdder_tb_948282;
ARCHITECTURE behavior OF My_16bitAdder_tb_948282 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT My_16bitAdder_948282
PORT(
A_input : IN std_logic_vector(15 downto 0);
B_input : IN std_logic_vector(15 downto 0);
Sum_out : OUT std_logic_vector(15 downto 0);
Carry_in : IN std_logic;
Carry_out : OUT std_logic
);
END COMPONENT;
--Inputs
signal A_input : std_logic_vector(15 downto 0) := (others => '0');
signal B_input : std_logic_vector(15 downto 0) := (others => '0');
signal Carry_in : std_logic := '0';
--Outputs
signal Sum_out : std_logic_vector(15 downto 0);
signal Carry_out : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: My_16bitAdder_948282 PORT MAP (
A_input => A_input,
B_input => B_input,
Sum_out => Sum_out,
Carry_in => Carry_in,
Carry_out => Carry_out
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
A_input<="0111011101101100";
Carry_in<='1';
B_input<="0000001111100001";
wait;
end process;
END;
|
--RC5 Encryption
--A = A + S[0];
--B = B + S[1];
--for i=1 to 12 do
----A = ((A XOR B) <<< B) + S[2*i];
----B = ((B XOR A) <<< A) + S[2*1+1];
--RC5 Decryption
--for i=12 to 1 do
----B = ((B - S[2×i +1]) >>> A) xor A;
----A = ((A - S[2×i]) >>> B) xor B;
--B = B - S[1];
--A = A - S[0];
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- we will use CONV_INTEGER
USE WORK.RC5_PKG.ALL;
ENTITY rc5 IS
PORT (
clr,clk : IN STD_LOGIC; -- Asynchronous reset and Clock Signal
enc : IN STD_LOGIC; --1 for encryption 0 for decryption
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit input
di_vld : IN STD_LOGIC; -- Valid Input
key_rdy : IN STD_LOGIC;
skey : IN rc5_rom_26;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit output
do_rdy : OUT STD_LOGIC --Output is Ready
);
END rc5;
ARCHITECTURE rtl OF rc5 IS
SIGNAL i_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0); -- round counter
SIGNAL ab_xor : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_rot_left : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_rot_right : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_round : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL a_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register A
SIGNAL ba_xor : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_rot_left : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_rot_right : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_round : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL b_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- register B
-- RC5 state machine has five states: idle, pre_round, round and ready
SIGNAL state : StateType;
BEGIN
WITH enc SELECT
a_round <= din(63 DOWNTO 32) + skey(0) WHEN '1',--A = A + S[0]
a_reg - skey(0) WHEN OTHERS; --A = A - S[0]
WITH enc SELECT
b_round <= din(31 DOWNTO 0) + skey(1) WHEN '1', --B = B + S[1]
b_reg - skey(1) WHEN OTHERS; --B = B - S[1]
WITH enc SELECT --A XOR B
ab_xor<=a_reg XOR b_reg WHEN '1',
a_rot_right XOR ba_xor WHEN OTHERS;
WITH enc SELECT --B XOR A
ba_xor <= b_reg XOR a WHEN '1',
b_rot_right XOR a_reg WHEN OTHERS;
WITH enc SELECT --B XOR A
a <= a_rot_left + skey(CONV_INTEGER(i_cnt & '0')) WHEN '1', --A + S[2*i]
a_reg - skey(CONV_INTEGER(i_cnt & '0')) WHEN OTHERS; -- A - S[2*i]
WITH enc SELECT --B XOR A
b <= b_rot_left + skey(CONV_INTEGER(i_cnt & '1')) WHEN '1', --B + S[2*i+1]
b_reg - skey(CONV_INTEGER(i_cnt & '1')) WHEN OTHERS; --B - S[2*i+1]
ROT_A_LEFT: rotLeft
PORT MAP(din=>ab_xor,amnt=>b_reg(4 DOWNTO 0),dout=>a_rot_left);--A <<< B
ROT_B_LEFT: rotLeft
PORT MAP(din=>ba_xor,amnt=>a(4 DOWNTO 0),dout=>b_rot_left);--B <<< A
ROT_B_RIGHT: rotRight
PORT MAP(din=>b,amnt=>a_reg(4 DOWNTO 0),dout=>b_rot_right);--B >>> A
ROT_A_RIGHT: rotRight
PORT MAP(din=>a,amnt=>ba_xor(4 DOWNTO 0),dout=>a_rot_right);--A >>> B
A_register:
PROCESS(clr, clk) BEGIN
IF(clr='0') THEN
a_reg<=din(63 DOWNTO 32);
ELSIF(rising_edge(clk)) THEN --clk'EVENT AND clk='1' can introduce error
IF(state=ST_PRE_ROUND OR state=ST_POST_ROUND) THEN
a_reg<=a_round;
ELSIF(state=ST_ROUND_OP) THEN
if(enc = '1')then
a_reg<=a;
else
a_reg<=ab_xor;
end if;
END IF;
END IF;
END PROCESS;
B_register:
PROCESS(clr, clk) BEGIN
IF(clr='0') THEN
b_reg<=din(31 DOWNTO 0);
ELSIF(rising_edge(clk)) THEN
IF(state=ST_PRE_ROUND OR state=ST_POST_ROUND) THEN
b_reg<=b_round;
ELSIF(state=ST_ROUND_OP) THEN
if(enc = '1')then
b_reg<=b;
else
b_reg<=ba_xor;
end if;
END IF;
END IF;
END PROCESS;
State_Control:
PROCESS(clr, clk)
BEGIN
IF(clr='0') THEN
state<=ST_IDLE;
ELSIF(rising_edge(clk)) THEN
CASE state IS
WHEN ST_IDLE=> IF(di_vld='1' and key_rdy='1') THEN
IF(enc = '1') THEN
state<=ST_PRE_ROUND;
ELSE
state<=ST_ROUND_OP;
END IF;
END IF;
WHEN ST_PRE_ROUND=> state<=ST_ROUND_OP;--Left because makes sense
WHEN ST_ROUND_OP=> IF(enc = '1') THEN
IF(i_cnt="1100") THEN
state<=ST_READY;
END IF;
ELSE
IF(i_cnt="0001") THEN
state<=ST_POST_ROUND;
END IF;
END IF;
WHEN ST_POST_ROUND=> state<=ST_READY; --Left because makes sense
WHEN ST_READY=> IF(di_vld='1' and key_rdy='1') THEN
state<=ST_IDLE;
END IF;
END CASE;
END IF;
END PROCESS;
round_counter:
PROCESS(clk, enc) BEGIN
IF(clr='0') THEN
i_cnt<="0001";
ELSIF(rising_edge(clk)) THEN
IF (state=ST_ROUND_OP) THEN
if(enc='1')then
IF(i_cnt="1100") THEN
i_cnt<="0001";
ELSE
i_cnt<=i_cnt+'1';
END IF;
else
IF(i_cnt="0001") THEN
i_cnt<="1100";
ELSE
i_cnt<=i_cnt-'1';
END IF;
END IF;
ELSIF(state=ST_PRE_ROUND)THEN
i_cnt<="0001";
ELSIF(state=ST_IDLE OR state = ST_READY)THEN
i_cnt<="1100";
END IF;
END IF;
END PROCESS;
dout<=a_reg & b_reg;
WITH state SELECT
do_rdy<='1' WHEN ST_READY,
'0' WHEN OTHERS;
END rtl;
|
-- $Id: sys_tst_serloop1_n4d.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_serloop1_n4d - syn
-- Description: Tester serial link for nexys4d (serport_1clock case)
--
-- Dependencies: vlib/xlib/s7_cmt_sfs
-- vlib/genlib/clkdivce
-- bpgen/bp_rs232_4line_iob
-- bpgen/sn_humanio
-- tst_serloop_hiomap
-- vlib/serport/serport_1clock
-- tst_serloop
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: viv 2016.2-2022.1; ghdl 0.33-2.0.0
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7a100t-1 409 421 12 0 189
-- 2019-02-02 1108 2018.3 xc7a100t-1 409 456 16 0 200
-- 2019-02-02 1108 2017.2 xc7a100t-1 409 446 16 0 186
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-01-04 838 1.0 Initial version (derived from sys_tst_serloop1_n4)
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_serlooplib.all;
use work.serportlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_serloop1_n4d is -- top level
-- implements nexys4d_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4d switches
I_BTN : in slv5; -- n4d buttons
I_BTNRST_N : in slbit; -- n4d reset button
O_LED : out slv16; -- n4d leds
O_RGBLED0 : out slv3; -- n4d rgb-led 0
O_RGBLED1 : out slv3; -- n4d rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end sys_tst_serloop1_n4d;
architecture syn of sys_tst_serloop1_n4d is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXD : slbit := '0';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv32 := (others=>'0');
signal DSP_DP : slv8 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXHOLD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal SER_MONI : serport_moni_type := serport_moni_init;
begin
GEN_CLKSYS : s7_cmt_sfs -- clock generator -------------------
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => sys_conf_clkdiv_msecdiv)
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
SWIDTH => 16,
BWIDTH => 5,
LWIDTH => 16,
DCWIDTH => 3,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_serloop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
SWI => SWI(7 downto 0),
BTN => BTN(3 downto 0),
LED => LED(7 downto 0),
DSP_DAT => DSP_DAT(15 downto 0),
DSP_DP => DSP_DP(3 downto 0)
);
IOB_RS232 : bp_rs232_4line_iob
port map (
CLK => CLK,
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_CTS_N => I_CTS_N,
O_RTS_N => O_RTS_N
);
SERPORT : serport_1clock
generic map (
CDWIDTH => 12,
CDINIT => sys_conf_uart_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => HIO_CNTL.enaxon,
ENAESC => HIO_CNTL.enaesc,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
MONI => SER_MONI,
RXSD => RXD,
TXSD => TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
TESTER : tst_serloop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
-- show autobauder clock divisor on msb of display
DSP_DAT(31 downto 20) <= SER_MONI.abclkdiv(11 downto 0);
DSP_DAT(19) <= '0';
DSP_DAT(18 downto 16) <= SER_MONI.abclkdiv_f;
DSP_DP(7 downto 4) <= "0010";
-- setup unused outputs in nexys4d
O_RGBLED0 <= (others=>'0');
O_RGBLED1 <= (others=>not I_BTNRST_N);
end syn;
|
-------------------------------------------------------------------------------
-- Title : Cache tags data memory
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : tags_data_mem.vhd
-- Author : Robert Jarzmik <robert.jarzmik@free.fr>
-- Company :
-- Created : 2016-12-15
-- Last update: 2017-01-01
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-12-15 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.cache_defs.all;
-------------------------------------------------------------------------------
entity tags_data_mem is
generic
(
DEBUG : boolean := false
);
port (
clk : in std_logic;
-- Reader
i_re : in std_logic;
i_raddr : in addr_t;
o_tag_found : out boolean;
o_way_found : out natural range 0 to NB_WAYS - 1;
--- Combinational : read_tag_entries(i_raddr)(way)
o_tag_entry : out tag_entry_t;
o_data_valid : out std_logic;
o_way_evict : out natural range 0 to NB_WAYS - 1;
o_evict_dirty : out boolean;
o_evict_tag_entry : out tag_entry_t;
-- Writer
--- i_update_addr will be the one latched when i_prepare_we = 1
--- base data for update will be the one latched from mem_read_data the
--- cycle _after_ i_prepare_we = 1
i_waddr : in addr_t;
i_we : in std_logic;
i_update_way : in natural range 0 to NB_WAYS - 1;
i_wtag_entry : in tag_entry_t;
--- i_way_alloc triggers a new election of the next to evict line
i_evict_compute : in std_logic
);
end entity tags_data_mem;
architecture str of tags_data_mem is
-- Entry anatomy, ie. entry for a given address index
subtype counter_t is natural range 0 to NB_WAYS - 1;
-- Tag Data Memory interface
subtype mem_addr_t is std_logic_vector(INDEX_WIDTH - 1 downto 0);
signal mem_raddr : mem_addr_t := (others => '0');
signal mem_read_data : tag_entry_vector(0 to NB_WAYS - 1) := (others => TAG_ENTRY_EMPTY);
signal mem_bypassed_rdata : tag_entry_vector(0 to NB_WAYS - 1) := (others => TAG_ENTRY_EMPTY);
signal mem_rren : way_selector_t := (others => '0');
signal mem_waddr : mem_addr_t;
signal mem_we : std_logic;
signal mem_wway : natural range 0 to NB_WAYS - 1;
signal mem_wren : way_selector_t := (others => '0');
signal mem_write_data : tag_entry_vector(0 to NB_WAYS - 1) := (others => TAG_ENTRY_EMPTY);
-- Tag Allocate interface
signal evict_rdata : alloc_entry_t := (others => '0');
signal evict_wdata : alloc_entry_t := (others => '0');
signal evict_bypassed_rdata : alloc_entry_t := (others => '0');
signal evict_wren : std_logic := '0';
signal evict_way : natural range 0 to NB_WAYS - 1;
signal mem_read_alloc_counter : alloc_entry_t;
-- Debug signals
-- Latched data for memory read + search
signal searched_addr : addr_t := (others => '0');
signal mem_w_bypass : boolean := false;
signal mem_te : tag_entry_t := TAG_ENTRY_EMPTY;
signal mem_searched_addr : mem_addr_t := (others => '0');
signal mem_way_found : natural range 0 to NB_WAYS - 1;
----------------------------------------------
-- Functions for combinational memory logic --
----------------------------------------------
function get_is_way_found(addr : addr_t;
tev : tag_entry_vector(0 to NB_WAYS - 1))
return boolean is
variable needle : tag_t;
variable way_found : boolean := false;
begin
needle := get_address_tag(addr);
for way in tev'range loop
if tev(way).tag = needle and tev(way).valids /= TAG_ENTRY_EMPTY.valids then
way_found := true;
end if;
end loop;
return way_found;
end function get_is_way_found;
function get_way_found(addr : addr_t;
tev : tag_entry_vector(0 to NB_WAYS - 1))
return natural is
variable needle : tag_t;
variable oway : natural range 0 to NB_WAYS - 1 := 0;
begin
needle := get_address_tag(addr);
for way in tev'range loop
if tev(way).tag = needle and tev(way).valids /= TAG_ENTRY_EMPTY.valids then
oway := way;
end if;
end loop;
return oway;
end function get_way_found;
function get_alloc_counter(ae : alloc_entry_t; step : natural)
return natural is
variable ac : natural;
begin
ac := to_integer(unsigned(ae));
ac := (ac + step) mod NB_WAYS;
return ac;
end function get_alloc_counter;
function get_updated_tag_entry(addr : addr_t;
a : tag_entry_t;
data_in_line : natural range 0 to DATAS_PER_LINE;
valid : std_ulogic;
dirty : std_ulogic;
ctxt : tag_context_t)
return tag_entry_t is
variable te : tag_entry_t;
begin
te.ctxt := ctxt;
te.valids(data_in_line) := valid;
te.dirtys(data_in_line) := dirty;
return te;
end function get_updated_tag_entry;
begin -- architecture str
-- Memories instances
tmem : for i in 0 to NB_WAYS - 1 generate
tdata : entity work.memory_tagmem_internal
generic map (ADDR_WIDTH => INDEX_WIDTH, DEBUG_IDX => i, DEBUG => DEBUG)
port map (clk, mem_raddr, mem_waddr, mem_write_data(i), i_re,
mem_wren(i), mem_read_data(i));
end generate tmem;
evictm : entity work.memory_eviction_internal
generic map (ADDR_WIDTH => INDEX_WIDTH, DEBUG => DEBUG)
port map (clk, mem_raddr, mem_waddr, evict_wdata, i_re,
evict_wren, evict_rdata);
mem_raddr <= std_logic_vector(to_unsigned(get_address_index(i_raddr), mem_raddr'length));
reader : process(clk, i_raddr)
begin
if rising_edge(clk) then
searched_addr <= i_raddr;
mem_searched_addr <= mem_raddr;
end if;
end process reader;
mem_w_bypass <= mem_searched_addr = mem_waddr and mem_we = '1';
gmbypassrdata : for way in mem_bypassed_rdata'range generate
mem_bypassed_rdata(way) <= mem_write_data(way) when mem_w_bypass and way = mem_wway
else mem_read_data(way);
end generate;
evict_bypassed_rdata <= evict_wdata when evict_wren = '1' and mem_waddr = mem_searched_addr else evict_rdata;
-- mem_way_found <= get_way_found(searched_addr, mem_read_data);
mem_way_found <= get_way_found(searched_addr, mem_bypassed_rdata);
mem_te <= mem_bypassed_rdata(mem_way_found);
evict_way <= get_alloc_counter(evict_bypassed_rdata, 0);
o_tag_found <= get_is_way_found(searched_addr, mem_bypassed_rdata);
o_way_found <= mem_way_found;
o_way_evict <= evict_way;
o_data_valid <= data_is_valid(searched_addr, mem_te);
o_tag_entry_mux : entity work.tag_entry_mux
generic map (NB => NB_WAYS)
port map (mem_way_found, mem_bypassed_rdata, o_tag_entry);
o_evict_dirty <= dataline_is_dirty(mem_bypassed_rdata(evict_way));
o_evict_tag_entry_mux : entity work.tag_entry_mux
generic map (NB => NB_WAYS)
port map (evict_way, mem_bypassed_rdata, o_evict_tag_entry);
writer : process(clk, mem_searched_addr, i_we, i_update_way, i_waddr)
begin
if rising_edge(clk) then
mem_waddr <= std_logic_vector(to_unsigned(get_address_index(i_waddr), mem_waddr'length));
mem_we <= i_we;
mem_wway <= i_update_way;
for way in mem_wren'range loop
if i_we = '1' and i_update_way = way then
mem_wren(way) <= '1';
else
mem_wren(way) <= '0';
end if;
end loop;
for way in mem_write_data'range loop
mem_write_data(way) <= i_wtag_entry;
end loop;
end if;
end process writer;
evicter : process(clk, mem_searched_addr, i_evict_compute)
begin
if rising_edge(clk) then
evict_wren <= i_evict_compute;
evict_wdata <=
std_logic_vector(to_unsigned(get_alloc_counter(evict_rdata, 1), evict_wdata'length));
end if;
end process evicter;
end architecture str;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_01_tb_01_01.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity test_bench_01_01 is
end entity test_bench_01_01;
architecture test_reg4_behav of test_bench_01_01 is
signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;
begin
dut : entity work.reg4(behav)
port map ( d0 => d0, d1 => d1, d2 => d2, d3 => d3, en => en, clk => clk,
q0 => q0, q1 => q1, q2 => q2, q3 => q3 );
stimulus : process is
begin
wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("1010"); wait for 20 ns;
en <= '1'; wait for 20 ns;
clk <= '1'; wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("0101"); wait for 20 ns;
clk <= '0'; wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("0000"); wait for 20 ns;
en <= '1'; wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("1111"); wait for 20 ns;
wait;
end process stimulus;
end architecture test_reg4_behav;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_01_tb_01_01.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity test_bench_01_01 is
end entity test_bench_01_01;
architecture test_reg4_behav of test_bench_01_01 is
signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;
begin
dut : entity work.reg4(behav)
port map ( d0 => d0, d1 => d1, d2 => d2, d3 => d3, en => en, clk => clk,
q0 => q0, q1 => q1, q2 => q2, q3 => q3 );
stimulus : process is
begin
wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("1010"); wait for 20 ns;
en <= '1'; wait for 20 ns;
clk <= '1'; wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("0101"); wait for 20 ns;
clk <= '0'; wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("0000"); wait for 20 ns;
en <= '1'; wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("1111"); wait for 20 ns;
wait;
end process stimulus;
end architecture test_reg4_behav;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_01_tb_01_01.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity test_bench_01_01 is
end entity test_bench_01_01;
architecture test_reg4_behav of test_bench_01_01 is
signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;
begin
dut : entity work.reg4(behav)
port map ( d0 => d0, d1 => d1, d2 => d2, d3 => d3, en => en, clk => clk,
q0 => q0, q1 => q1, q2 => q2, q3 => q3 );
stimulus : process is
begin
wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("1010"); wait for 20 ns;
en <= '1'; wait for 20 ns;
clk <= '1'; wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("0101"); wait for 20 ns;
clk <= '0'; wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("0000"); wait for 20 ns;
en <= '1'; wait for 20 ns;
(d0, d1, d2, d3) <= bit_vector'("1111"); wait for 20 ns;
wait;
end process stimulus;
end architecture test_reg4_behav;
|
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`protect end_protected
|
entity psl is
end;
architecture behav of psl is
signal a, b, c : bit;
signal clk : bit;
subtype wf_type is bit_vector (0 to 7);
constant wave_a : wf_type := "10010100";
constant wave_b : wf_type := "01001010";
constant wave_c : wf_type := "00100101";
begin
process
begin
for i in wf_type'range loop
clk <= '0';
wait for 1 ns;
a <= wave_a (i);
b <= wave_b (i);
c <= wave_c (i);
clk <= '1';
wait for 1 ns;
end loop;
wait;
end process;
-- psl default clock is (clk'event and clk = '1');
-- psl a1: assume always a |=> b;
-- psl a2: assume always a -> eventually! c;
-- psl c1: cover {a;b;c};
end behav;
|
--+-------------------------------------------------------------------------------------------------+
--| |
--| File: pcipargen.vhd |
--| |
--| Project: pci32tlite_oc |
--| |
--| Description: PCI Parity Generator. |
--| PCI Target generates PAR in the data phase of a read cycle. The 1's sum on AD, |
--| CBE and PAR is even. |
--| |
--+-------------------------------------------------------------------------------------------------+
--| |
--| Revision history : |
--| Date Version Author Description |
--| 2005-05-13 R00A00 PAU First alfa revision (eng) |
--| |
--| To do: |
--| |
--+-------------------------------------------------------------------------------------------------+
--+-----------------------------------------------------------------+
--| |
--| Copyright (C) 2005 Peio Azkarate, peio@opencores.org |
--| |
--| This source file may be used and distributed without |
--| restriction provided that this copyright statement is not |
--| removed from the file and that any derivative work contains |
--| the original copyright notice and the associated disclaimer. |
--| |
--| This source file is free software; you can redistribute it |
--| and/or modify it under the terms of the GNU Lesser General |
--| Public License as published by the Free Software Foundation; |
--| either version 2.1 of the License, or (at your option) any |
--| later version. |
--| |
--| This source is distributed in the hope that it will be |
--| useful, but WITHOUT ANY WARRANTY; without even the implied |
--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
--| PURPOSE. See the GNU Lesser General Public License for more |
--| details. |
--| |
--| You should have received a copy of the GNU Lesser General |
--| Public License along with this source; if not, download it |
--| from http://www.opencores.org/lgpl.shtml |
--| |
--+-----------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| LIBRARIES |
--+-----------------------------------------------------------------------------+
library ieee;
use ieee.std_logic_1164.all;
--+-----------------------------------------------------------------------------+
--| ENTITY |
--+-----------------------------------------------------------------------------+
entity pcipargen is
port (
clk_i : in std_logic;
pcidatout_i : in std_logic_vector(31 downto 0);
cbe_i : in std_logic_vector(3 downto 0);
parOE_i : in std_logic;
par_o : out std_logic
);
end pcipargen;
architecture rtl of pcipargen is
--+-----------------------------------------------------------------------------+
--| COMPONENTS |
--+-----------------------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| CONSTANTS |
--+-----------------------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| SIGNALS |
--+-----------------------------------------------------------------------------+
signal d : std_logic_vector(31 downto 0);
signal pardat : std_logic;
signal parcbe : std_logic;
signal par : std_logic;
signal par_s : std_logic;
component sync
port (
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end component;
component sync2
port (
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end component;
begin
d <= pcidatout_i;
--+-------------------------------------------------------------------------+
--| building parity |
--+-------------------------------------------------------------------------+
pardat <= d(0) xor d(1) xor d(2) xor d(3) xor d(4) xor d(5) xor d(6) xor d(7) xor
d(8) xor d(9) xor d(10) xor d(11) xor d(12) xor d(13) xor d(14) xor d(15) xor
d(16) xor d(17) xor d(18) xor d(19) xor d(20) xor d(21) xor d(22) xor d(23) xor
d(24) xor d(25) xor d(26) xor d(27) xor d(28) xor d(29) xor d(30) xor d(31);
parcbe <= cbe_i(0) xor cbe_i(1) xor cbe_i(2) xor cbe_i(3);
par <= pardat xor parcbe;
-- u1: sync port map ( clk => clk_i, d => par, q => par_s );
u1: sync2 port map (
clk => clk_i,
d => par,
q => par_s
);
--+-------------------------------------------------------------------------+
--| PAR |
--+-------------------------------------------------------------------------+
par_o <= par_s when ( parOE_i = '1' ) else 'Z';
end rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_misc.all;
use work.types.all;
use work.common.all;
use work.interfaces.all;
use std.textio.all;
entity alu_logic is
port( clk : in std_logic;
reset : in std_logic;
input : in alu_logic_in_if;
output : out alu_logic_out_if);
end entity;
architecture rtl of alu_logic is
component alu is
port( input : in alu_in_if; output : out alu_out_if);
end component;
type state_t is (state_idle, state_register,
state_indirect, state_load_mem,
state_cb_0, state_cb_reg,
state_inc, state_dec,
state_cb_store_reg, state_cb_store_indirect,
state_store_flags,
state_cb_indirect, state_store);
signal alu_in : alu_in_if;
signal alu_out : alu_out_if;
signal state : state_t;
signal temp_flag : byte_t;
signal alu_op : alu_op_t;
begin
alu0 : alu port map(alu_in, alu_out);
alu_in.op <= alu_op;
alu_in.flags <= input.reg.f;
main_proc: process(clk, reset)
variable out_reg : register_t;
begin
if reset = '1' then
state <= state_idle;
output.reg.we <= '0';
output.mem.we <= '0';
elsif rising_edge(clk) then
output.reg.we <= '0';
output.mem.we <= '0';
output.done <= '0';
case state is
when state_idle =>
if input.en = '1' then
output.reg.wsel <= register_a;
if input.op = alu_op_inc then
state <= state_inc;
output.reg.rsel0 <= input.rsel;
output.reg.wsel <= input.rsel;
elsif input.op = alu_op_dec then
state <= state_dec;
output.reg.rsel0 <= input.rsel;
output.reg.wsel <= input.rsel;
elsif input.mode = alu_mode_register then
state <= state_register;
output.reg.rsel0 <= register_a;
output.reg.rsel1 <= input.rsel;
elsif input.mode = alu_mode_immediate then
state <= state_load_mem;
output.mem.address <= std_logic_vector(unsigned(input.reg.pc) + 1);
elsif input.mode = alu_mode_indirect then
state <= state_indirect;
output.reg.rsel0 <= register_hl;
elsif input.mode = alu_mode_cb then
state <= state_cb_0;
output.mem.address <= std_logic_vector(unsigned(input.reg.pc) + 1);
end if;
else
state <= state_idle;
end if;
when state_inc =>
state <= state_store;
alu_in.i0 <= input.reg.d0(LO_BYTE);
alu_in.i1 <= x"01";
alu_op <= alu_op_add;
when state_dec =>
state <= state_store;
alu_in.i0 <= input.reg.d0(LO_BYTE);
alu_in.i1 <= x"01";
alu_op <= alu_op_sub;
when state_register =>
state <= state_store;
alu_op <= input.op;
alu_in.i0 <= input.reg.d0(LO_BYTE);
alu_in.i1 <= input.reg.d1(LO_BYTE);
when state_indirect =>
state <= state_load_mem;
alu_op <= input.op;
output.mem.address <= input.reg.d0;
when state_load_mem =>
state <= state_store;
alu_op <= input.op;
alu_in.i0 <= input.reg.d0(LO_BYTE);
alu_in.i1 <= input.mem.data;
when state_cb_0 =>
case input.mem.data(7 downto 6) is
when "00" => -- logic
alu_op <= l_table(input.mem.data(5 downto 3));
when "01" => -- bit
alu_op <= alu_op_bit;
alu_in.i1 <= "00000" & input.mem.data(5 downto 3);
when "10" => -- set
alu_op <= alu_op_set;
alu_in.i1 <= "00000" & input.mem.data(5 downto 3);
when "11" => -- reset
alu_op <= alu_op_reset;
alu_in.i1 <= "00000" & input.mem.data(5 downto 3);
when others =>
alu_op <= (others => 'U');
end case;
if input.mem.data(2 downto 0) = "110" then -- (HL)
output.mem.address <= input.reg.hl;
state <= state_cb_indirect;
else
out_reg := r_table(input.mem.data(2 downto 0));
output.reg.rsel0 <= out_reg;
state <= state_cb_reg;
end if;
when state_cb_reg =>
alu_in.i0 <= input.reg.d0(LO_BYTE);
if alu_op = alu_op_bit then
state <= state_store_flags;
else
state <= state_cb_store_reg;
end if;
when state_cb_store_reg =>
state <= state_store_flags;
output.reg.we <= '1';
output.reg.wsel <= out_reg;
output.reg.data(LO_BYTE) <= alu_out.q;
when state_cb_indirect =>
alu_in.i0 <= input.mem.data;
if alu_op = alu_op_bit then
state <= state_store_flags;
else
state <= state_cb_store_indirect;
end if;
when state_cb_store_indirect =>
state <= state_store_flags;
output.mem.we <= '1';
output.mem.address <= input.reg.hl;
output.mem.data <= alu_out.q;
when state_store =>
state <= state_store_flags;
output.reg.we <= '1';
output.reg.wsel <= input.rsel;
output.reg.data(LO_BYTE) <= alu_out.q;
when state_store_flags =>
state <= state_idle;
output.done <= '1';
output.reg.we <= '1';
output.reg.wsel <= register_f;
output.reg.data(LO_BYTE) <= alu_out.flags;
end case;
end if;
end process;
end rtl;
|
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 03:32:43 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim
-- d:/github/Digital-Hardware-Modelling/xilinx-vivado/gcd/gcd.srcs/sources_1/bd/gcd_block_design/ip/gcd_block_design_processing_system7_0_2/gcd_block_design_processing_system7_0_2_sim_netlist.vhdl
-- Design : gcd_block_design_processing_system7_0_2
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "clg400";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "gcd_block_design_processing_system7_0_2.hwdef";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "processing_system7_v5_5_processing_system7";
attribute POWER : string;
attribute POWER of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
end gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 1) => B"000000000000000",
IRQF2P(0) => IRQ_F2P(0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 0) => M_AXI_GP1_ARCACHE(3 downto 0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 0) => M_AXI_GP1_AWCACHE(3 downto 0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity gcd_block_design_processing_system7_0_2 is
port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of gcd_block_design_processing_system7_0_2 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of gcd_block_design_processing_system7_0_2 : entity is "gcd_block_design_processing_system7_0_2,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of gcd_block_design_processing_system7_0_2 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of gcd_block_design_processing_system7_0_2 : entity is "processing_system7_v5_5_processing_system7,Vivado 2018.2";
end gcd_block_design_processing_system7_0_2;
architecture STRUCTURE of gcd_block_design_processing_system7_0_2 is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg400";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "gcd_block_design_processing_system7_0_2.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of DDR_CAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N";
attribute X_INTERFACE_INFO of DDR_CKE : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE";
attribute X_INTERFACE_INFO of DDR_CS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N";
attribute X_INTERFACE_INFO of DDR_Clk : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P";
attribute X_INTERFACE_INFO of DDR_Clk_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N";
attribute X_INTERFACE_INFO of DDR_DRSTB : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N";
attribute X_INTERFACE_INFO of DDR_ODT : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT";
attribute X_INTERFACE_INFO of DDR_RAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N";
attribute X_INTERFACE_INFO of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN";
attribute X_INTERFACE_INFO of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP";
attribute X_INTERFACE_INFO of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N";
attribute X_INTERFACE_INFO of FCLK_CLK0 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0";
attribute X_INTERFACE_INFO of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST";
attribute X_INTERFACE_PARAMETER of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of M_AXI_GP0_ACLK : signal is "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK";
attribute X_INTERFACE_PARAMETER of M_AXI_GP0_ACLK : signal is "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_BREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_BVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_RLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST";
attribute X_INTERFACE_INFO of M_AXI_GP0_RREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_RVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_WLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST";
attribute X_INTERFACE_INFO of M_AXI_GP0_WREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_WVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID";
attribute X_INTERFACE_INFO of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK";
attribute X_INTERFACE_INFO of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB";
attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false";
attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB";
attribute X_INTERFACE_INFO of SDIO0_WP : signal is "xilinx.com:interface:sdio:1.0 SDIO_0 WP";
attribute X_INTERFACE_INFO of USB0_VBUS_PWRFAULT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT";
attribute X_INTERFACE_INFO of USB0_VBUS_PWRSELECT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT";
attribute X_INTERFACE_INFO of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR";
attribute X_INTERFACE_INFO of DDR_BankAddr : signal is "xilinx.com:interface:ddrx:1.0 DDR BA";
attribute X_INTERFACE_INFO of DDR_DM : signal is "xilinx.com:interface:ddrx:1.0 DDR DM";
attribute X_INTERFACE_INFO of DDR_DQ : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ";
attribute X_INTERFACE_INFO of DDR_DQS : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P";
attribute X_INTERFACE_PARAMETER of DDR_DQS : signal is "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11";
attribute X_INTERFACE_INFO of DDR_DQS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N";
attribute X_INTERFACE_INFO of IRQ_F2P : signal is "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT";
attribute X_INTERFACE_PARAMETER of IRQ_F2P : signal is "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH, PortWidth 1";
attribute X_INTERFACE_INFO of MIO : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE";
attribute X_INTERFACE_INFO of M_AXI_GP0_BID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID";
attribute X_INTERFACE_INFO of M_AXI_GP0_BRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP";
attribute X_INTERFACE_INFO of M_AXI_GP0_RDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA";
attribute X_INTERFACE_PARAMETER of M_AXI_GP0_RDATA : signal is "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of M_AXI_GP0_RID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID";
attribute X_INTERFACE_INFO of M_AXI_GP0_RRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP";
attribute X_INTERFACE_INFO of M_AXI_GP0_WDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA";
attribute X_INTERFACE_INFO of M_AXI_GP0_WID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID";
attribute X_INTERFACE_INFO of M_AXI_GP0_WSTRB : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB";
attribute X_INTERFACE_INFO of USB0_PORT_INDCTL : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL";
begin
inst: entity work.gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => IRQ_F2P(0),
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => SDIO0_WP,
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
|
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 03:32:43 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim
-- d:/github/Digital-Hardware-Modelling/xilinx-vivado/gcd/gcd.srcs/sources_1/bd/gcd_block_design/ip/gcd_block_design_processing_system7_0_2/gcd_block_design_processing_system7_0_2_sim_netlist.vhdl
-- Design : gcd_block_design_processing_system7_0_2
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "clg400";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "gcd_block_design_processing_system7_0_2.hwdef";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "processing_system7_v5_5_processing_system7";
attribute POWER : string;
attribute POWER of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 : entity is 0;
end gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 1) => B"000000000000000",
IRQF2P(0) => IRQ_F2P(0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 0) => M_AXI_GP1_ARCACHE(3 downto 0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 0) => M_AXI_GP1_AWCACHE(3 downto 0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity gcd_block_design_processing_system7_0_2 is
port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of gcd_block_design_processing_system7_0_2 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of gcd_block_design_processing_system7_0_2 : entity is "gcd_block_design_processing_system7_0_2,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of gcd_block_design_processing_system7_0_2 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of gcd_block_design_processing_system7_0_2 : entity is "processing_system7_v5_5_processing_system7,Vivado 2018.2";
end gcd_block_design_processing_system7_0_2;
architecture STRUCTURE of gcd_block_design_processing_system7_0_2 is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg400";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "gcd_block_design_processing_system7_0_2.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of DDR_CAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N";
attribute X_INTERFACE_INFO of DDR_CKE : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE";
attribute X_INTERFACE_INFO of DDR_CS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N";
attribute X_INTERFACE_INFO of DDR_Clk : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P";
attribute X_INTERFACE_INFO of DDR_Clk_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N";
attribute X_INTERFACE_INFO of DDR_DRSTB : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N";
attribute X_INTERFACE_INFO of DDR_ODT : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT";
attribute X_INTERFACE_INFO of DDR_RAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N";
attribute X_INTERFACE_INFO of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN";
attribute X_INTERFACE_INFO of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP";
attribute X_INTERFACE_INFO of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N";
attribute X_INTERFACE_INFO of FCLK_CLK0 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0";
attribute X_INTERFACE_INFO of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST";
attribute X_INTERFACE_PARAMETER of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of M_AXI_GP0_ACLK : signal is "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK";
attribute X_INTERFACE_PARAMETER of M_AXI_GP0_ACLK : signal is "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_BREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_BVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_RLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST";
attribute X_INTERFACE_INFO of M_AXI_GP0_RREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_RVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_WLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST";
attribute X_INTERFACE_INFO of M_AXI_GP0_WREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_WVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID";
attribute X_INTERFACE_INFO of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK";
attribute X_INTERFACE_INFO of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB";
attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false";
attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB";
attribute X_INTERFACE_INFO of SDIO0_WP : signal is "xilinx.com:interface:sdio:1.0 SDIO_0 WP";
attribute X_INTERFACE_INFO of USB0_VBUS_PWRFAULT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT";
attribute X_INTERFACE_INFO of USB0_VBUS_PWRSELECT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT";
attribute X_INTERFACE_INFO of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR";
attribute X_INTERFACE_INFO of DDR_BankAddr : signal is "xilinx.com:interface:ddrx:1.0 DDR BA";
attribute X_INTERFACE_INFO of DDR_DM : signal is "xilinx.com:interface:ddrx:1.0 DDR DM";
attribute X_INTERFACE_INFO of DDR_DQ : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ";
attribute X_INTERFACE_INFO of DDR_DQS : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P";
attribute X_INTERFACE_PARAMETER of DDR_DQS : signal is "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11";
attribute X_INTERFACE_INFO of DDR_DQS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N";
attribute X_INTERFACE_INFO of IRQ_F2P : signal is "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT";
attribute X_INTERFACE_PARAMETER of IRQ_F2P : signal is "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH, PortWidth 1";
attribute X_INTERFACE_INFO of MIO : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE";
attribute X_INTERFACE_INFO of M_AXI_GP0_BID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID";
attribute X_INTERFACE_INFO of M_AXI_GP0_BRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP";
attribute X_INTERFACE_INFO of M_AXI_GP0_RDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA";
attribute X_INTERFACE_PARAMETER of M_AXI_GP0_RDATA : signal is "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of M_AXI_GP0_RID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID";
attribute X_INTERFACE_INFO of M_AXI_GP0_RRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP";
attribute X_INTERFACE_INFO of M_AXI_GP0_WDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA";
attribute X_INTERFACE_INFO of M_AXI_GP0_WID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID";
attribute X_INTERFACE_INFO of M_AXI_GP0_WSTRB : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB";
attribute X_INTERFACE_INFO of USB0_PORT_INDCTL : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL";
begin
inst: entity work.gcd_block_design_processing_system7_0_2_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => IRQ_F2P(0),
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => SDIO0_WP,
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1533.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p09n02i01533ent IS
END c08s09b00x00p09n02i01533ent;
ARCHITECTURE c08s09b00x00p09n02i01533arch OF c08s09b00x00p09n02i01533ent IS
BEGIN
TESTING: PROCESS
variable i1, i2, i3 : integer := 1;
BEGIN
--
-- Initialize two integer variables so their division yeilds a real
--
i2 := 11;
i3 := 3;
--
-- Loop must have discrete parameters
--
L1: for c in i1 to real(i2) / i3 loop -- parameters must be discrete
null;
end loop L1;
assert FALSE
report "***FAILED TEST: c08s09b00x00p09n02i01533 - Loop parameters must be discrete."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p09n02i01533arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1533.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p09n02i01533ent IS
END c08s09b00x00p09n02i01533ent;
ARCHITECTURE c08s09b00x00p09n02i01533arch OF c08s09b00x00p09n02i01533ent IS
BEGIN
TESTING: PROCESS
variable i1, i2, i3 : integer := 1;
BEGIN
--
-- Initialize two integer variables so their division yeilds a real
--
i2 := 11;
i3 := 3;
--
-- Loop must have discrete parameters
--
L1: for c in i1 to real(i2) / i3 loop -- parameters must be discrete
null;
end loop L1;
assert FALSE
report "***FAILED TEST: c08s09b00x00p09n02i01533 - Loop parameters must be discrete."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p09n02i01533arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1533.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p09n02i01533ent IS
END c08s09b00x00p09n02i01533ent;
ARCHITECTURE c08s09b00x00p09n02i01533arch OF c08s09b00x00p09n02i01533ent IS
BEGIN
TESTING: PROCESS
variable i1, i2, i3 : integer := 1;
BEGIN
--
-- Initialize two integer variables so their division yeilds a real
--
i2 := 11;
i3 := 3;
--
-- Loop must have discrete parameters
--
L1: for c in i1 to real(i2) / i3 loop -- parameters must be discrete
null;
end loop L1;
assert FALSE
report "***FAILED TEST: c08s09b00x00p09n02i01533 - Loop parameters must be discrete."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p09n02i01533arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity s2_box is
port( data_in: in std_logic_vector(0 to 5);
data_out: out std_logic_vector(0 to 3));
end s2_box;
architecture behavior of s2_box is
type s2box is array(0 to 3, 0 to 15) of integer range 0 to 15;
constant box: s2box:=
((15,1,8,14,6,11,3,4,9,7,2,13,12,0,5,10),
(3,13,4,7,15,2,8,14,12,0,1,10,6,9,11,5),
(0,14,7,11,10,4,13,1,5,8,12,6,9,3,2,15),
(13,8,10,1,3,15,4,2,11,6,7,12,0,5,14,9));
begin
process(data_in) is
variable column: integer range 0 to 15;
variable row: integer range 0 to 3;
variable tmp: std_logic_vector(0 to 1); --this variable holds the first and last bit of the input that represents the row. It is usedto cast two separate bits into one vector of size two.
variable data_out_decimal: integer range 0 to 15; --this variable contains the output data in decimal representation
begin
column:=to_integer(unsigned(data_in(1 to 4)));
tmp:=data_in(0)&data_in(5);
row:=to_integer(unsigned(tmp));
data_out_decimal:=box(row,column);
data_out<=std_logic_vector(to_unsigned(data_out_decimal,data_out'length));
end process;
end behavior;
|
--
-- Grain
--
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity grain is
generic (
DEBUG : boolean := false; -- output debug information
FAST : boolean := false -- attempt manual register balancing
);
port (
CLK_I : in std_logic;
CLKEN_I : in std_logic := '1';
ARESET_I : in std_logic;
KEY_I : in std_logic;
IV_I : in std_logic;
INIT_I: in std_logic;
KEYSTREAM_O : out std_logic;
KEYSTREAM_VALID_O : out std_logic
);
end entity;
architecture behav of grain is
type state_t is (IDLE, INIT_KEYIV, INIT_RUN);
signal state : state_t;
signal cnt : unsigned(7 downto 0) := (others => '0');
signal cnt79, cnt63, cnt239 : std_logic := '0';
signal inject_input, set_injected_iv , allow_output : std_logic;
signal add_output : std_logic;
signal output_bit, output_bit_d, allow_output_d : std_logic;
begin
KEYSTREAM_O <= output_bit_d;
KEYSTREAM_VALID_O <= allow_output_d;
slow_design: if FAST = false generate
begin
functions0: entity work.grain_datapath_slow
generic map ( DEBUG => DEBUG )
port map (
CLK_I => CLK_I,
CLKEN_I => CLKEN_I,
ARESET_I => ARESET_I,
KEY_I => KEY_I,
IV_I => IV_I,
INJECT_INPUT_I => inject_input,
PAD_IV_I => set_injected_iv,
ADD_OUTPUT_I => add_output,
H_O => output_bit
);
end generate;
fast_design: if FAST = true generate
begin
functions1: entity work.grain_datapath_fast
generic map ( DEBUG => DEBUG )
port map (
CLK_I => CLK_I,
CLKEN_I => CLKEN_I,
ARESET_I => ARESET_I,
KEY_I => KEY_I,
IV_I => IV_I,
INJECT_INPUT_I => inject_input,
PAD_IV_I => set_injected_iv,
ADD_OUTPUT_I => add_output,
H_O => output_bit
);
end generate;
-- output registers:
-- (in case the "user" forgets this is at
-- his end and kills my fmax)
--
output_reg: process(CLK_I, ARESET_I)
begin
if ARESET_I = '1' then
output_bit_d <= '0';
allow_output_d <= '0';
elsif rising_edge(CLK_I) then
if CLKEN_I = '1' then
output_bit_d <= output_bit;
allow_output_d <= allow_output;
end if;
end if;
end process;
-- the counter:
cnt_proc: process(CLK_I)
begin
if rising_edge(CLK_I) then
if CLKEN_I = '1' then
if state = IDLE then
cnt <= b"0000_0001";
else
cnt <= cnt + 1;
end if;
if cnt = 79 then
cnt79 <= '1';
else
cnt79 <= '0';
end if;
if cnt = 63 then
cnt63 <= '1';
else
cnt63 <= '0';
end if;
if cnt = 239 then
cnt239 <= '1';
else
cnt239 <= '0';
end if;
end if;
end if;
end process;
-- the controller fsm:
ctrl_proc: process(CLK_I, ARESET_I)
begin
if ARESET_I = '1' then
state <= IDLE;
inject_input <= '0';
set_injected_iv <= '0';
add_output <= '0';
allow_output <= '0';
elsif rising_edge(CLK_I) then
if CLKEN_I = '1' then
case state is
when IDLE =>
if INIT_I = '1' then
state <= INIT_KEYIV;
inject_input <= '1';
set_injected_iv <= '0';
allow_output <= '0';
end if;
when INIT_KEYIV =>
if cnt63 = '1' then
set_injected_iv <= '1';
end if;
if cnt79 = '1' then
state <= INIT_RUN;
inject_input <= '0';
add_output <= '1';
end if;
when INIT_RUN =>
if cnt239 = '1' then
state <= IDLE;
add_output <= '0';
allow_output <= '1';
end if;
when others => state <= IDLE;
end case;
end if;
end if;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sram_external is
generic(
ADDRBITS: integer := 19;
DATABITS: integer := 8
);
port(
I_addr: in std_logic_vector(ADDRBITS-1 downto 0);
I_data: in std_logic_vector(DATABITS-1 downto 0);
I_en: in std_logic := '0';
I_we: in std_logic := '0';
O_data: out std_logic_vector(DATABITS-1 downto 0);
IO_external_data: inout std_logic_vector(DATABITS-1 downto 0);
O_external_addr: out std_logic_vector(ADDRBITS-1 downto 0);
O_external_ce: out std_logic := '1';
O_external_oe: out std_logic := '1';
O_external_we: out std_logic := '1'
);
end sram_external;
architecture Behavioral of sram_external is
begin
process(I_we, I_data, IO_external_data)
begin
if I_we = '1' then
IO_external_data <= I_data;
O_data <= I_data;
else
IO_external_data <= (others => 'Z');
O_data <= IO_external_data;
end if;
end process;
-- pass through address
O_external_addr <= I_addr;
-- control signals for external SRAM are active low
O_external_ce <= not I_en;
O_external_we <= not I_we;
O_external_oe <= not (I_en and (not I_we));
end Behavioral; |
package pack is
type rec is record
a, b : integer;
end record;
end package;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
x : in integer;
y : out integer;
r : in rec );
end entity;
architecture test of sub is
begin
y <= x + r.a + r.b;
end architecture;
-------------------------------------------------------------------------------
entity elab21 is
end entity;
use work.pack.all;
architecture test of elab21 is
signal r1, r2 : rec := (0, 0);
begin
sub_i: entity work.sub
port map (
x => r1.a,
y => r1.b,
r => r2 );
process is
begin
r1.a <= 0;
r2 <= (0, 0);
wait for 1 ns;
assert r1.b = 0;
r1.a <= 5;
wait for 1 ns;
assert r1.b = 5;
r2 <= (2, 3);
wait for 1 ns;
assert r1.b = 10;
wait;
end process;
end architecture;
|
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`protect end_protected
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- code from book (in text)
entity nand3 is
port ( a, b, c : in bit; y : out bit );
end entity nand3;
-- end code from book
architecture behavioral of nand3 is
begin
y <= not (a and b and c);
end architecture behavioral;
entity logic_block is
end entity logic_block;
-- code from book
library gate_lib;
architecture ideal of logic_block is
component nand2 is
port ( in1, in2 : in bit; result : out bit );
end component nand2;
for all : nand2
use entity gate_lib.nand3(behavioral)
port map ( a => in1, b => in2, c => '1', y => result );
-- . . . -- other declarations
-- not in book
signal s1, s2, s3 : bit := '0';
begin
gate1 : component nand2
port map ( in1 => s1, in2 => s2, result => s3 );
-- . . . -- other concurrent statements
-- not in book
s1 <= '1' after 20 ns;
s2 <= '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
-- end not in book
end architecture ideal;
-- end code from book
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- code from book (in text)
entity nand3 is
port ( a, b, c : in bit; y : out bit );
end entity nand3;
-- end code from book
architecture behavioral of nand3 is
begin
y <= not (a and b and c);
end architecture behavioral;
entity logic_block is
end entity logic_block;
-- code from book
library gate_lib;
architecture ideal of logic_block is
component nand2 is
port ( in1, in2 : in bit; result : out bit );
end component nand2;
for all : nand2
use entity gate_lib.nand3(behavioral)
port map ( a => in1, b => in2, c => '1', y => result );
-- . . . -- other declarations
-- not in book
signal s1, s2, s3 : bit := '0';
begin
gate1 : component nand2
port map ( in1 => s1, in2 => s2, result => s3 );
-- . . . -- other concurrent statements
-- not in book
s1 <= '1' after 20 ns;
s2 <= '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
-- end not in book
end architecture ideal;
-- end code from book
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- code from book (in text)
entity nand3 is
port ( a, b, c : in bit; y : out bit );
end entity nand3;
-- end code from book
architecture behavioral of nand3 is
begin
y <= not (a and b and c);
end architecture behavioral;
entity logic_block is
end entity logic_block;
-- code from book
library gate_lib;
architecture ideal of logic_block is
component nand2 is
port ( in1, in2 : in bit; result : out bit );
end component nand2;
for all : nand2
use entity gate_lib.nand3(behavioral)
port map ( a => in1, b => in2, c => '1', y => result );
-- . . . -- other declarations
-- not in book
signal s1, s2, s3 : bit := '0';
begin
gate1 : component nand2
port map ( in1 => s1, in2 => s2, result => s3 );
-- . . . -- other concurrent statements
-- not in book
s1 <= '1' after 20 ns;
s2 <= '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
-- end not in book
end architecture ideal;
-- end code from book
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04/05/2017 02:01:44 PM
-- Design Name:
-- Module Name: game_logic - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity game_logic is
port(
clk : in STD_LOGIC;
usb_bt_clk : in STD_LOGIC;
save_button_input : in STD_LOGIC;
keyboard_input : in STD_LOGIC_VECTOR(7 downto 0);
x_pos_input : in STD_LOGIC_VECTOR(7 downto 0);
y_pos_input : in STD_LOGIC_VECTOR(7 downto 0);
usb_bt_input : in STD_LOGIC_VECTOR(7 downto 0);
reset_output : out STD_LOGIC;
screen_size_output : out STD_LOGIC;
pen_width_output : out STD_LOGIC_VECTOR(2 downto 0);
x_pos_output : out STD_LOGIC_VECTOR(7 downto 0);
y_pos_output : out STD_LOGIC_VECTOR(7 downto 0);
tricolor_led_output : out STD_LOGIC_VECTOR(11 downto 0);
usb_bt_output : out STD_LOGIC_VECTOR(15 downto 0);
color_output : out STD_LOGIC_VECTOR(23 downto 0);
ram_we_output : out STD_LOGIC_VECTOR(0 downto 0);
ram_val_output : out STD_LOGIC_VECTOR(11 downto 0);
ram_addr_output : out STD_LOGIC_VECTOR(16 downto 0)
);
end game_logic;
architecture Behavioral of game_logic is
-- Font ROM component
component font_rom is
port(
clk : in STD_LOGIC;
addr : in STD_LOGIC_VECTOR(10 downto 0);
data : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
-- RAM clock divider component
component clock_divider is
generic(count_max : INTEGER := 8); -- FIX THIS?
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
clk_output : out STD_LOGIC
);
end component;
-- System properties
signal pc_connected : STD_LOGIC := '0';
signal screen_size : STD_LOGIC := '0';
signal reset : STD_LOGIC := '0';
signal pen_width : STD_LOGIC_VECTOR(2 downto 0) := "000";
signal ascii_char : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal color : STD_LOGIC_VECTOR(23 downto 0) := x"000000";
--USB/bluetooth control send signals
signal prev_screen_size : STD_LOGIC := '0';
signal prev_save : STD_LOGIC := '0';
signal prev_reset : STD_LOGIC := '0';
signal prev_pen_width : STD_LOGIC_VECTOR(2 downto 0):= "000";
signal prev_ascii_char : STD_LOGIC_VECTOR(7 downto 0):= x"00";
signal prev_x_pos, prev_y_pos : STD_LOGIC_VECTOR(7 downto 0):= x"00";
signal prev_color : STD_LOGIC_VECTOR(23 downto 0):= x"000000";
--USB/Bluetooth control receive signals
signal prev_connections : STD_LOGIC_VECTOR(7 downto 0);
-- Keyboard control signals
signal num_values_input : INTEGER := 0;
signal prev_pc_connected : STD_LOGIC := '0';
signal changing_item : STD_LOGIC_VECTOR(2 downto 0) := "000"; -- [color, pen_width, screen_size]
signal hex_input : STD_LOGIC_VECTOR(3 downto 0) := x"0";
signal temp_hex_input : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal input_values : STD_LOGIC_VECTOR(23 downto 0) := x"000000";
-- Font Rom signals
signal font_rom_addr : UNSIGNED(10 downto 0) := x"00" & "000";
signal font_rom_data : STD_LOGIC_VECTOR(7 downto 0) := x"00";
-- RAM clock divider signals
signal ram_divider_counter : INTEGER := 0;
signal ram_clk : STD_LOGIC := '0';
-- RAM Signals
signal x_pos_int : INTEGER := 0;
signal y_pos_int : INTEGER := 0;
-- RAM fast update signals
signal ram_update_count : INTEGER := 0;
signal ram_update_x_count : INTEGER := 0;
signal ram_update_y_count : INTEGER := 0;
signal ram_update_slow_int : INTEGER := 0;
signal ram_update : STD_LOGIC_VECTOR(2 downto 0) := "000"; -- [pos, sys_text, user_text]
signal ram_update_slow : STD_LOGIC_VECTOR(2 downto 0) := "000";
signal ram_update_pos_slow : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal ram_update_sys_text_slow : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal ram_update_user_text_slow : STD_LOGIC_VECTOR(7 downto 0) := x"00";
-- RAM slow control signals
signal x_addr_count, y_addr_count : INTEGER := 0;
-- RAM reset signals
signal ram_reset : STD_LOGIC := '0';
signal ram_reset_slow : STD_LOGIC := '0';
signal ram_reset_count : UNSIGNED(15 downto 0) := x"0000";
signal prev_ram_resets : STD_LOGIC_VECTOR(7 downto 0) := x"00";
begin
screen_size_output <= screen_size;
pen_width_output <= pen_width;
x_pos_output <= x_pos_input;
y_pos_output <= y_pos_input;
tricolor_led_output <= color(11 downto 0);
color_output <= color;
ram_we_output <= "1";
--ram_we_output <= "0";
reset_output <= reset;
-- Previous signal generation process
process(clk)
begin
prev_pc_connected <= pc_connected;
prev_x_pos <= x_pos_input;
prev_y_pos <= y_pos_input;
prev_color <= color;
prev_ascii_char <= ascii_char;
prev_screen_size <= screen_size;
prev_pen_width <= pen_width;
prev_save <= save_button_input;
prev_reset <= reset;
end process;
-- USB/Bluetooth control process
process(clk, usb_bt_clk, prev_x_pos, prev_y_pos) -- FIX THIS (add update method)
begin
-- Sending Data
if rising_edge(clk) then
if reset /= prev_reset then
usb_bt_output(15 downto 12) <= "1111";
usb_bt_output(1) <= save_button_input;
usb_bt_output(0) <= reset;
elsif prev_x_pos /= x_pos_input then
usb_bt_output(15 downto 14) <= "10";
usb_bt_output(8) <= '0';
usb_bt_output(7 downto 0) <= x_pos_input;
elsif prev_y_pos /= y_pos_input then
usb_bt_output(15 downto 14) <= "10";
usb_bt_output(8) <= '1';
usb_bt_output(7 downto 0) <= y_pos_input;
elsif prev_color /= color then
usb_bt_output(15 downto 12) <= "1100";
usb_bt_output(11 downto 0) <= color(11 downto 0); -- change to 24 bit?
elsif prev_screen_size /= screen_size or prev_pen_width /= pen_width then
usb_bt_output(15 downto 12) <= "1110";
usb_bt_output(3) <= screen_size;
usb_bt_output(2 downto 0) <= pen_width;
elsif prev_ascii_char /= ascii_char then
usb_bt_output(15 downto 12) <= "1101";
usb_bt_output(7 downto 0) <= ascii_char;
elsif prev_save /= save_button_input then
usb_bt_output(15 downto 12) <= "1111";
usb_bt_output(1) <= save_button_input;
usb_bt_output(0) <= reset;
else
usb_bt_output <= x"0000";
end if;
end if;
-- Recieving Data
if rising_edge(usb_bt_clk) then
prev_connections <= prev_connections(6 downto 0) & usb_bt_input(0);
if prev_connections = x"00" then
pc_connected <= '0';
else
pc_connected <= '1';
end if;
end if;
end process;
-- Keyboard control process
hex_input <= temp_hex_input(3 downto 0);
process(clk)
begin
-- Keyboard control
if rising_edge(clk) then
if reset = '0' then
if keyboard_input = x"77" and changing_item = "000" then -- input w and changing color
ascii_char <= x"77";
changing_item <= "100";
num_values_input <= 1;
elsif keyboard_input = x"63" and changing_item = "000" then -- input c and changing pen_width
ascii_char <= x"63";
changing_item <= "010";
num_values_input <= 1;
elsif keyboard_input = x"73" and changing_item = "000" then -- input s and changing screen_size
ascii_char <= x"73";
changing_item <= "001";
num_values_input <= 1;
elsif keyboard_input = x"72" and changing_item = "000" then -- input r
reset <= '1';
color <= x"FFFFFF";
pen_width <= "000";
screen_size <= '0';
elsif keyboard_input = x"71" and changing_item /= "000" then -- input q and exit command
ascii_char <= x"71";
-- FIX THIS
elsif keyboard_input = x"08" and num_values_input = 1 then -- input backspace
ascii_char <= x"08";
num_values_input <= 0;
changing_item <= "000";
elsif changing_item /= "000" then
-- Ascii to hex converter
if (keyboard_input >= x"30" and keyboard_input <= x"39") then
temp_hex_input <= std_logic_vector(unsigned(keyboard_input) - x"30");
elsif (keyboard_input >= x"61" and keyboard_input <= x"66") then
temp_hex_input <= std_logic_vector(unsigned(keyboard_input) - x"57");
else
temp_hex_input <= x"FF";
end if;
-- User keyboard input restrictions
if changing_item = "100" and hex_input <= x"F" then -- Limit color
input_values(((num_values_input * 4)-1) downto ((num_values_input-1) * 4)) <= hex_input;
num_values_input <= num_values_input + 1;
elsif changing_item = "010" and hex_input >= x"1" and hex_input <= x"7" then -- Limit pen_width
input_values(3 downto 0) <= hex_input;
num_values_input <= num_values_input + 1;
elsif changing_item = "001" and hex_input <= x"1" then -- Limit screen_size
input_values(3 downto 0) <= hex_input;
num_values_input <= num_values_input + 1;
end if;
elsif keyboard_input = x"0A" then -- input enter
ascii_char <= x"0A";
if changing_item = "100" and num_values_input = 7 then -- new color
color <= input_values;
changing_item <= "000";
elsif changing_item = "010" and num_values_input = 1 then -- new pen_width
pen_width <= input_values(2 downto 0);
changing_item <= "000";
elsif changing_item = "001" and num_values_input = 1 then -- new screen_size
screen_size <= input_values(0);
changing_item <= "000";
end if;
end if;
end if;
-- Reset handling
if reset = '1' and prev_reset = '1' and ram_reset = '0' then
reset <= '0';
color <= x"000000";
end if;
end if;
end process;
-- Font ROM port map
ram_font_rom : font_rom
port map(
clk => clk,
addr => std_logic_vector(font_rom_addr),
data => font_rom_data
);
-- RAM clock divider port map
ram_clock_divider : clock_divider
generic map(count_max => 2) -- CHANGE VALUE
port map(
clk => clk,
reset => '0',
clk_output => ram_clk
);
x_pos_int <= to_integer(unsigned(x_pos_input));
y_pos_int <= to_integer(unsigned(y_pos_input));
-- RAM control process
process(clk, ram_clk)
begin
-- When to update RAM
if rising_edge(clk) then
-- ram_update_pos_slow <= ram_update_pos_slow(6 downto 0) & ram_update_slow(2);
-- ram_update_pos_slow <= ram_update_pos_slow(6 downto 0) & ram_update_slow(2);
-- ram_update_pos_slow <= ram_update_pos_slow(6 downto 0) & ram_update_slow(2);
if (x_pos_input /= prev_x_pos or y_pos_input /= prev_y_pos) then
ram_update(2) <= '1'; -- pos
ram_update_slow_int <= 1;
elsif ram_update slow = 64
ram_update(2) <= '0';
-- elsif (color /= prev_color or pen_width /= prev_pen_width
-- or pc_connected /= prev_pc_connected) then
-- ram_update(1) <= '1'; -- sys_text
-- elsif (ascii_char /= prev_ascii_char) then
-- ram_update(0) <= '1'; -- user_text
end if;
if ram_update_slow_int = 64 then
ram_update_slow_int <= 0;
elsif ram_update_slow_int > 0 then
ram_update_slow_int <= ram_update_slow_int + 1;
end if;
-- if ram_update_pos_slow = x"00" then
-- ram_update(2) <= '0';
-- end if;
-- if ram_update_sys_text_slow = x"00" then
-- ram_update(1) <= '0';
-- end if;
-- if ram_update_user_text_slow = x"00" then
-- ram_update(0) <= '0';
-- end if;
-- if reset = '1' and ram_reset = '0' then
-- ram_reset <= '1';
-- prev_ram_resets <= prev_ram_resets(6 downto 0) & ram_reset;
-- end if;
--
-- if ram_reset_slow = '0' and prev_ram_resets = x"FF" then
-- ram_reset <= '0';
-- end if;
-- end if;
-- Draw to RAM
--if rising_edge(ram_clk) then
--if rising_edge(clk) then
--if ram_reset = '0' then
if ram_update(2) = '1' then -- pos
--if(true) then
--ram_we_output <= "1";
ram_val_output <= color(23 downto 20) & color(15 downto 12) & color(7 downto 4);
--ram_update_slow(2) <= '1';
--ram_update(2) <= '0';
-- if (y_addr_count < unsigned(pen_width)) and
-- ((y_pos_int + y_addr_count) < 256) and
-- ((y_pos_int + y_addr_count) >= 0) then
-- if (x_addr_count < unsigned(pen_width)) and
-- ((x_pos_int + x_addr_count) < 256) and
-- ((x_pos_int + x_addr_count) >= 0) then
ram_addr_output <= std_logic_vector(to_unsigned( ((x_pos_int+x_addr_count) + ((y_pos_int+y_addr_count) * 256)) , 17));
-- else
-- x_addr_count <= 0;
-- end if;
-- y_addr_count <= y_addr_count + 1;
-- else
-- y_addr_count <= 0;
-- end if;
--elsif prev_x_pos /= x_pos_input and prev_y_pos /= y_pos_input then --Not needed?
--ram_update(1) <= '0';
--ram_we_output <= "0"; --Not needed?
--ram_update(2) <= '0'; --Not needed?
-- elsif ram_update(2 downto 1) = "01" then -- sys_text
-- ram_update_slow(2 downto 1) <= "01";
-- if ram_update_count < 3 then
-- if ram_update_y_count < 16 then
-- if ram_update_x_count < 8 then
-- if ram_update_count = 1 then -- Update color
-- ram_addr_output <= std_logic_vector(to_unsigned(65618 + ram_update_x_count
-- + (ram_update_y_count * 384), 17));
-- ram_val_output <= color(11 downto 0);
-- elsif ram_update_count = 2 then -- Update pen_width
-- ram_addr_output <= std_logic_vector(to_unsigned(65768 + ram_update_x_count
-- + (ram_update_y_count * 384), 17));
-- font_rom_addr <= "000" & (x"30" + unsigned("0000" & pen_width)); -- FIX THIS (concurency)
-- if font_rom_data(ram_update_x_count) = '1' then
-- ram_val_output <= x"000";
-- else
-- ram_val_output <= x"FFF";
-- end if;
-- else -- Update pc_connnection
-- ram_addr_output <= std_logic_vector(to_unsigned(65888 + ram_update_x_count
-- + (ram_update_count * 10)
-- + (ram_update_y_count * 384), 17));
-- font_rom_addr <= "00" & (x"30" + "0000000" & pc_connected); -- FIX THIS (concurency)
-- if font_rom_data(ram_update_x_count) = '1' then
-- ram_val_output <= x"000";
-- else
-- ram_val_output <= x"FFF";
-- end if;
-- end if;
-- ram_update_x_count <= ram_update_x_count + 1;
-- else
-- ram_update_x_count <= 0;
-- end if;
-- ram_update_y_count <= ram_update_x_count + 1;
-- else
-- ram_update_y_count <= 0;
-- end if;
-- ram_update_count <= ram_update_count + 1;
-- else
-- ram_update_slow(1) <= '0';
-- ram_update_count <= 0;
-- end if;
-- elsif ram_update = "001" then -- user_text
-- ram_update_slow <= "001";
-- if ram_update_count < 8 then
-- if ram_update_y_count < 16 then
-- if ram_update_x_count < 8 then
-- ram_addr_output <= std_logic_vector(to_unsigned(66102 + ram_update_x_count
-- + (ram_update_y_count * 384), 17));
-- font_rom_addr <= unsigned("000" & ascii_char); -- FIX THIS (concurency)
-- if font_rom_data(ram_update_x_count) = '1' then
-- ram_val_output <= x"000";
-- else
-- ram_val_output <= x"FFF";
-- end if;
-- ram_update_x_count <= ram_update_x_count + 1;
-- else
-- ram_update_x_count <= 0;
-- end if;
-- ram_update_y_count <= ram_update_x_count + 1;
-- else
-- ram_update_y_count <= 0;
-- end if;
-- ram_update_count <= ram_update_count + 1;
-- else
-- ram_update_slow(0) <= '0';
-- ram_update_count <= 0;
-- end if;
-- else
-- ram_update_slow <= "000";
--end if;
---- else -- ram_reset = 1
---- -- Drawing Screen (sys_text and user_text update automatically)
---- if ram_reset_count < 65536 then
---- ram_reset_slow <= '1';
---- ram_reset_count <= ram_reset_count + 1;
---- ram_addr_output <= "0" & std_logic_vector(ram_reset_count);
---- else
---- ram_reset_slow <= '0';
---- ram_reset_count <= x"0000";
---- end if;
end if;
end if;
end process;
end Behavioral;
|
library verilog;
use verilog.vl_types.all;
entity full_adder_vlg_sample_tst is
port(
a : in vl_logic;
b : in vl_logic;
cin : in vl_logic;
sampler_tx : out vl_logic
);
end full_adder_vlg_sample_tst;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: generic_ddr_phy
-- File: ddr_phy_inferred.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Modified: Magnus Hjorth - Aeroflex Gaisler
-- Description: Generic DDR PHY (simulation only)
------------------------------------------------------------------------------
--###################################################################################
-- Generic DDR1 PHY
--###################################################################################
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
entity generic_ddr_phy_wo_pads is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0; mobile : integer := 0;
abits: integer := 14; nclk: integer := 3; ncs: integer := 2);
port(
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clk0r : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb: in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(nclk-1 downto 0);
moben : in std_logic -- Mobile DDR enable
);
end;
architecture rtl of generic_ddr_phy_wo_pads is
component sim_pll
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
minfreq: integer := 0;
maxfreq: integer := 10000000
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end component;
constant freq_khz: integer := (1000*MHz*clk_mul)/(clk_div);
constant freq_mhz: integer := freq_khz / 1000;
constant td90: time := 250 us * (1.0 / real(freq_khz));
signal vcc, gnd : std_logic; -- VCC and GND
signal clk0, clk90r, clk180r, clk270r : std_ulogic;
signal lockl,vlockl,locked: std_ulogic;
signal dqs90,dqs90n: std_logic_vector(dbits/8-1 downto 0);
signal ckl: std_logic_vector(nclk-1 downto 0);
signal ckel: std_logic_vector(ncs-1 downto 0);
begin
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------------
-- Clock generation (Only for simulation)
-----------------------------------------------------------------------------------
-- Phase shifted clocks
--pragma translate_off
-- To avoid jitter problems when using ddr without sync regs we shift
-- 10 degrees extra.
pll0: sim_pll
generic map (
clkmul => clk_mul,
clkdiv1 => clk_div,
clkphase1 => 0-10+360,
clkdiv2 => clk_div,
clkphase2 => 90-10,
clkdiv3 => clk_div,
clkphase3 => 180-10,
clkdiv4 => clk_div,
clkphase4 => 270-10,
minfreq => MHz*1000,
maxfreq => MHz*1000
)
port map (
i => clk,
o1 => clk0,
o2 => clk90r,
o3 => clk180r,
o4 => clk270r,
lock => lockl,
rst => rst);
--pragma translate_on
-- Clock to DDR controller
clkout <= clk0;
ddr_clk_fb_out <= '0';
-----------------------------------------------------------------------------------
-- Lock delay
-----------------------------------------------------------------------------------
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r, lockl, rst)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*FREQ_MHZ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' or rst='0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-----------------------------------------------------------------------------
-- DQS shifting
-----------------------------------------------------------------------------
-- pragma translate_off
dqs90 <= transport ddr_dqs_in after td90;
dqs90n <= not dqs90;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Data path
-----------------------------------------------------------------------------
-- For mobile SDRAM, force Cke high during reset and reset-delay,
-- For regular SDRAM, force Cke low
-- also disable outgoing clock until we have achieved PLL lock
mobgen: if mobile > 1 generate
ckel <= cke or (cke'range => not locked);
end generate;
nmobgen: if mobile < 2 generate
ckel <= cke and (cke'range => locked);
end generate;
ckl <= ck and (ck'range => lockl);
dp0: ddrphy_datapath
generic map (
regtech => inferred, dbits => dbits, abits => abits,
bankbits => 2, ncs => ncs, nclk => nclk,
resync => 2 )
port map (
clk0 => clk0r,
clk90 => clk90r,
clk180 => clk180r,
clk270 => clk270r,
clkresync => gnd,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_dq_in => ddr_dq_in,
ddr_dq_out => ddr_dq_out,
ddr_dq_oen => ddr_dq_oen,
ddr_dqs_in90 => dqs90,
ddr_dqs_in90n => dqs90n,
ddr_dqs_out => ddr_dqs_out,
ddr_dqs_oen => ddr_dqs_oen,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dm => ddr_dm,
ddr_odt => open,
dqin => dqin,
dqout => dqout,
addr => addr,
ba => ba,
dm => dm,
oen => oen,
rasn => rasn,
casn => casn,
wen => wen,
csn => csn,
cke => ckel,
odt => (others => '0'),
dqs_en => dqs,
dqs_oen => dqsoen,
ddrclk_en => ckl
);
end;
--###################################################################################
-- Generic DDR2 PHY
--###################################################################################
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
entity generic_ddr2_phy_wo_pads is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0;
eightbanks: integer := 0; abits: integer := 14;
cben: integer := 0; chkbits: integer := 8;
nclk: integer := 3; ncs: integer := 2);
port(
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clk0r : in std_ulogic; -- system clock returned
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0); -- ddr odt
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector (2 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(2 downto 0);
odt : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of generic_ddr2_phy_wo_pads is
component sim_pll
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
minfreq: integer := 0;
maxfreq: integer := 10000000
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end component;
constant freq_khz: integer := (1000*MHz*clk_mul)/(clk_div);
constant freq_mhz: integer := freq_khz / 1000;
constant td90: time := 250 us * (1.0 / real(freq_khz));
signal vcc, gnd : std_logic; -- VCC and GND
signal clk0, clk90r, clk180r, clk270r : std_ulogic;
signal lockl,vlockl,locked: std_ulogic;
signal dqs90,dqs90n: std_logic_vector(dbits/8-1 downto 0);
begin
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------------
-- Clock generation (Only for simulation)
-----------------------------------------------------------------------------------
-- Phase shifted clocks
--pragma translate_off
-- To avoid jitter problems when using ddr2 without sync regs we shift
-- 10 degrees extra.
pll0: sim_pll
generic map (
clkmul => clk_mul,
clkdiv1 => clk_div,
clkphase1 => 0-10+360,
clkdiv2 => clk_div,
clkphase2 => 90-10,
clkdiv3 => clk_div,
clkphase3 => 180-10,
clkdiv4 => clk_div,
clkphase4 => 270-10,
minfreq => MHz*1000,
maxfreq => MHz*1000
)
port map (
i => clk,
o1 => clk0,
o2 => clk90r,
o3 => clk180r,
o4 => clk270r,
lock => lockl,
rst => rst);
--pragma translate_on
-- Clock to DDR controller
clkout <= clk0;
ddr_clk_fb_out <= '0';
-----------------------------------------------------------------------------------
-- Lock delay
-----------------------------------------------------------------------------------
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r, lockl)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*FREQ_MHZ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-----------------------------------------------------------------------------
-- DQS shifting
-----------------------------------------------------------------------------
-- pragma translate_off
dqs90 <= transport ddr_dqs_in after td90;
dqs90n <= not dqs90;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Data path
-----------------------------------------------------------------------------
dp0: ddrphy_datapath
generic map (
regtech => inferred, dbits => dbits, abits => abits,
bankbits => 2+EIGHTBANKS, ncs => ncs, nclk => nclk,
resync => 0 )
port map (
clk0 => clk0r,
clk90 => clk90r,
clk180 => clk180r,
clk270 => clk270r,
clkresync => gnd,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_dq_in => ddr_dq_in,
ddr_dq_out => ddr_dq_out,
ddr_dq_oen => ddr_dq_oen,
ddr_dqs_in90 => dqs90,
ddr_dqs_in90n => dqs90n,
ddr_dqs_out => ddr_dqs_out,
ddr_dqs_oen => ddr_dqs_oen,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dm => ddr_dm,
ddr_odt => ddr_odt,
dqin => dqin,
dqout => dqout,
addr => addr,
ba => ba(1+eightbanks downto 0),
dm => dm,
oen => oen,
rasn => rasn,
casn => casn,
wen => wen,
csn => csn,
cke => cke,
odt => odt,
dqs_en => dqs,
dqs_oen => dqsoen,
ddrclk_en => ck(nclk-1 downto 0)
);
end;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 - 2012 Jan Andersson, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
--pragma translate_off
use gaisler.sim.all;
--pragma translate_on
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000 -- frequency of main clock (used for PLLs)
);
port (
cpu_rst_n : in std_ulogic;
clk_fpga_50m : in std_ulogic;
-- DDR SDRAM
ram_a : out std_logic_vector (13 downto 0); -- ddr address
ram_ck_p : out std_logic;
ram_ck_n : out std_logic;
ram_cke : out std_logic;
ram_cs_n : out std_logic;
ram_ws_n : out std_ulogic; -- ddr write enable
ram_ras_n : out std_ulogic; -- ddr ras
ram_cas_n : out std_ulogic; -- ddr cas
ram_dm : out std_logic_vector(1 downto 0); -- ram_udm & ram_ldm
ram_dqs : inout std_logic_vector (1 downto 0); -- ram_udqs & ram_lqds
ram_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ram_d : inout std_logic_vector (15 downto 0); -- ddr data
-- Ethernet PHY
txd : out std_logic_vector(3 downto 0);
rxd : in std_logic_vector(3 downto 0);
tx_clk : in std_logic;
rx_clk : in std_logic;
tx_en : out std_logic;
rx_dv : in std_logic;
eth_crs : in std_logic;
rx_er : in std_logic;
eth_col : in std_logic;
mdio : inout std_logic;
mdc : out std_logic;
eth_reset_n : out std_logic;
-- Temperature sensor
temp_sc : inout std_logic;
temp_cs_n : out std_logic;
temp_sio : inout std_logic;
-- LEDs
f_led : inout std_logic_vector(7 downto 0);
-- User push-button
pbsw_n : in std_logic;
-- Reconfig SW1 and SW2
reconfig_sw : in std_logic_vector(2 downto 1);
-- SD card interface
sd_dat0 : inout std_logic;
sd_dat1 : inout std_logic;
sd_dat2 : inout std_logic;
sd_dat3 : inout std_logic;
sd_cmd : inout std_logic;
sd_clk : inout std_logic;
-- EPCS
epcs_data : in std_ulogic;
epcs_dclk : out std_ulogic;
epcs_csn : out std_ulogic;
epcs_asdi : out std_ulogic
-- Expansion connector on card edge (set as reserved in design's QSF)
--reset_exp_n : out std_logic;
--exp_present : in std_logic;
--p : inout std_logic_vector(64 downto 1)
);
end;
architecture rtl of leon3mp is
constant maxahbm : integer := NCPU+CFG_AHB_JTAG+CFG_GRETH;
constant maxahbs : integer := 6
--pragma translate_off
+1 -- one more in simulation (AHBREP)
--pragma translate_on
;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal clkm, clkml : std_ulogic;
signal lclk, resetn : std_ulogic;
signal clklock, lock : std_ulogic;
signal rstn, rawrstn : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal tck : std_ulogic;
signal tckn : std_ulogic;
signal tms : std_ulogic;
signal tdi : std_ulogic;
signal tdo : std_ulogic;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u0i : uart_in_type;
signal u0o : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal spii2 : spi_in_type;
signal spio2 : spi_out_type;
signal slvsel2 : std_logic_vector(0 downto 0);
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
constant IOAEN : integer := 1;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal dsu_breakn : std_ulogic;
attribute syn_keep : boolean;
attribute syn_keep of clkm : signal is true;
attribute syn_keep of clkml : signal is true;
begin
vcc <= (others => '1'); gnd <= (others => '0');
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
cgi.pllctrl <= "00"; cgi.pllrst <= not rawrstn; cgi.pllref <= '0';
clklock <= cgo.clklock and lock;
clk_pad : clkpad generic map (tech => padtech)
port map (clk_fpga_50m, lclk);
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (
tech => CFG_CLKTECH,
clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV,
sdramen => 0,
freq => freq)
port map (
clkin => lclk,
pciclkin => gnd(0),
clk => clkm,
clkn => open,
clk2x => open,
sdclk => open,
pciclk => open,
cgi => cgi,
cgo => cgo);
reset_pad : inpad generic map (tech => padtech) port map (cpu_rst_n, resetn);
rst0 : rstgen -- reset generator
port map (
rstin => resetn,
clk => clkm,
clklock => clklock,
rstout => rstn,
rstoutraw => rawrstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (
defmast => CFG_DEFMST,
split => CFG_SPLIT,
rrobin => CFG_RROBIN,
ioaddr => CFG_AHBIO,
ioen => IOAEN,
nahbm => maxahbm,
nahbs => maxahbs)
port map (
rst => rstn,
clk => clkm,
msti => ahbmi,
msto => ahbmo,
slvi => ahbsi,
slvo => ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (
hindex => i,
fabtech => fabtech,
memtech => memtech,
nwindows => CFG_NWIN,
dsu => CFG_DSU,
fpu => CFG_FPU,
v8 => CFG_V8,
cp => 0,
mac => CFG_MAC,
pclow => pclow,
notag => CFG_NOTAG,
nwp => CFG_NWP,
icen => CFG_ICEN,
irepl => CFG_IREPL,
isets => CFG_ISETS,
ilinesize => CFG_ILINE,
isetsize => CFG_ISETSZ,
isetlock => CFG_ILOCK,
dcen => CFG_DCEN,
drepl => CFG_DREPL,
dsets => CFG_DSETS,
dlinesize => CFG_DLINE,
dsetsize => CFG_DSETSZ,
dsetlock => CFG_DLOCK,
dsnoop => CFG_DSNOOP,
ilram => CFG_ILRAMEN,
ilramsize => CFG_ILRAMSZ,
ilramstart => CFG_ILRAMADDR,
dlram => CFG_DLRAMEN,
dlramsize => CFG_DLRAMSZ,
dlramstart => CFG_DLRAMADDR,
mmuen => CFG_MMUEN,
itlbnum => CFG_ITLBNUM,
dtlbnum => CFG_DTLBNUM,
tlb_type => CFG_TLB_TYPE,
tlb_rep => CFG_TLB_REP,
lddel => CFG_LDDEL,
disas => disas,
tbuf => CFG_ITBSZ,
pwd => CFG_PWD,
svt => CFG_SVT,
rstaddr => CFG_RSTADDR,
smp => NCPU-1,
cached => CFG_DFIXED,
scantest => CFG_SCAN,
mmupgsz => CFG_MMU_PAGE,
bp => CFG_BP)
port map (
clk => clkm,
rstn => rstn,
ahbi => ahbmi,
ahbo => ahbmo(i),
ahbsi => ahbsi,
ahbso => ahbso,
irqi => irqi(i),
irqo => irqo(i),
dbgi => dbgi(i),
dbgo => dbgo(i));
end generate;
errorn_pad : toutpad generic map (tech => padtech) port map (f_led(6), gnd(0), dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (
hindex => 2,
haddr => 16#900#,
hmask => 16#F00#,
ncpu => NCPU,
tbits => 30,
tech => memtech,
irq => 0,
kbytes => CFG_ATBSZ)
port map (
rst => rstn,
clk => clkm,
ahbmi => ahbmi,
ahbsi => ahbsi,
ahbso => ahbso(2),
dbgi => dbgo,
dbgo => dbgi,
dsui => dsui,
dsuo => dsuo);
dsui.enable <= '1';
dsui.break <= not dsu_breakn; -- Switch polarity
dsubre_pad : inpad generic map (tech => padtech) port map (pbsw_n, dsu_breakn);
dsuact_pad : toutpad generic map (tech => padtech) port map (f_led(7), gnd(0), dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(
rst => rstn,
clk => clkm,
tck => tck,
tms => tms,
tdi => tdi,
tdo => tdo,
ahbi => ahbmi,
ahbo => ahbmo(NCPU+CFG_AHB_UART),
tapo_tck => open,
tapo_tdi => open,
tapo_inst => open,
tapo_rst => open,
tapo_capt => open,
tapo_shft => open,
tapo_upd => open,
tapi_tdo => gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
-- DDR memory controller
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc0 : ddrspa
generic map (
fabtech => fabtech,
memtech => memtech,
hindex => 0,
haddr => 16#400#,
hmask => 16#F00#,
ioaddr => 1,
pwron => CFG_DDRSP_INIT,
MHz => BOARD_FREQ/1000,
rskew => CFG_DDRSP_RSKEW,
clkmul => CFG_DDRSP_FREQ/5,
clkdiv => 10,
ahbfreq => CPU_FREQ/1000,
col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE,
ddrbits => 16,
regoutput => 1,
mobile => 0)
port map (
rst_ddr => rawrstn,
rst_ahb => rstn,
clk_ddr => lclk,
clk_ahb => clkm,
lock => lock,
clkddro => clkml,
clkddri => clkml,
ahbsi => ahbsi,
ahbso => ahbso(0),
ddr_clk => ddr_clkv,
ddr_clkb => ddr_clkbv,
ddr_clk_fb_out => open,
ddr_clk_fb => gnd(0),
ddr_cke => ddr_ckev,
ddr_csb => ddr_csbv,
ddr_web => ram_ws_n,
ddr_rasb => ram_ras_n,
ddr_casb => ram_cas_n,
ddr_dm => ram_dm,
ddr_dqs => ram_dqs,
ddr_ad => ram_a,
ddr_ba => ram_ba,
ddr_dq => ram_d);
end generate;
ram_ck_p <= ddr_clkv(0);
ram_ck_n <= ddr_clkbv(0);
ram_cke <= ddr_ckev(0);
ram_cs_n <= ddr_csbv(0);
ddrsp1 : if (CFG_DDRSP = 0) generate
ahbso(0) <= ahbs_none;
lock <= '1';
ddr_clkv <= (others => '0');
ddr_clkbv <= (others => '0');
ddr_ckev <= (others => '1');
ddr_csbv <= (others => '1');
end generate;
-- SPI Memory Controller
spimc: if CFG_SPIMCTRL /= 0 and CFG_AHBROMEN = 0 generate
spimctrl0 : spimctrl
generic map (
hindex => 4,
hirq => 9,
faddr => 16#000#,
fmask => 16#f00#,
ioaddr => 16#002#,
iomask => 16#fff#,
spliten => CFG_SPLIT,
oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT,
offset => CFG_SPIMCTRL_OFFSET)
port map (
rstn => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(4),
spii => spmi,
spio => spmo);
end generate;
epcs_miso_pad : inpad generic map (tech => padtech)
port map (epcs_data, spmi.miso);
epcs_mosi_pad : outpad generic map (tech => padtech)
port map (epcs_asdi, spmo.mosi);
epcs_sck_pad : outpad generic map (tech => padtech)
port map (epcs_dclk, spmo.sck);
epcs_slvsel0_pad : outpad generic map (tech => padtech)
port map (epcs_csn, spmo.csn);
nospimc : if CFG_SPIMCTRL /= 1 or CFG_AHBROMEN /= 0 generate
spmo <= spimctrl_out_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- AHB/APB bridge
apb0 : apbctrl
generic map (
hindex => 1,
haddr => CFG_APBADDR,
nslaves => 7)
port map (
rst => rstn,
clk => clkm,
ahbi => ahbsi,
ahbo => ahbso(1),
apbi => apbi,
apbo => apbo);
-- 8-bit UART, not connected off-chip, use in loopback with GRMON
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (
pindex => 1,
paddr => 1,
pirq => 2,
console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (
rst => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(1),
uarti => u0i,
uarto => u0o);
end generate;
u0i.rxd <= '0'; u0i.ctsn <= '0'; u0i.extclk <= '0';
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (
pindex => 2,
paddr => 2,
ncpu => NCPU)
port map (
rst => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(2),
irqi => irqo,
irqo => irqi);
end generate;
noirqctrl : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Timer unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (
pindex => 3,
paddr => 3,
pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ,
sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (
rst => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(3),
gpti => gpti,
gpto => open);
end generate;
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
gpti.wdogen <= '0';
notim : if CFG_GPT_ENABLE = 0 generate
apbo(3) <= apb_none;
end generate;
-- GPIO unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(
pindex => 0,
paddr => 0,
imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map(
rst => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(0),
gpioi => gpioi,
gpioo => gpioo);
end generate;
gpio_pads : iopadvv generic map (tech => padtech, width => 6)
port map (f_led(5 downto 0), gpioo.dout(5 downto 0),
gpioo.oen(5 downto 0), gpioi.din(5 downto 0));
gpioi.din(31 downto 6) <= (others => '0');
nogpio : if CFG_GRGPIO_ENABLE = 0 generate
apbo(0) <= apb_none;
end generate;
-- SPI controller connected to temperature sensor
spic: if CFG_SPICTRL_ENABLE /= 0 generate
spi1 : spictrl
generic map (
pindex => 4,
paddr => 4,
pmask => 16#fff#,
pirq => 9,
fdepth => CFG_SPICTRL_FIFO,
slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS,
odmode => CFG_SPICTRL_ODMODE,
automode => CFG_SPICTRL_AM,
aslvsel => CFG_SPICTRL_ASEL,
twen => 1,
maxwlen => CFG_SPICTRL_MAXWLEN,
netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM,
ft => CFG_SPICTRL_FT)
port map (
rstn => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(4),
spii => spii,
spio => spio,
slvsel => slvsel);
end generate spic;
-- MISO signal not used
spii.miso <= '0';
mosi_pad : iopad generic map (tech => padtech)
port map (temp_sio, spio.mosi, spio.mosioen, spii.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (temp_sc, spio.sck, spio.sckoen, spii.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (temp_cs_n, slvsel(0));
spii.spisel <= '1'; -- Master only
nospic : if CFG_SPICTRL_ENABLE = 0 generate
apbo(4) <= apb_none;
spio.misooen <= '1';
spio.mosioen <= '1';
spio.sckoen <= '1';
slvsel <= (others => '1');
end generate;
-- SPI controller connected to SD card slot
spic2: if CFG_SPICTRL_ENABLE /= 0 and CFG_SPICTRL_NUM > 1 generate
spi1 : spictrl
generic map (
pindex => 5,
paddr => 5,
pmask => 16#fff#,
pirq => 11,
fdepth => CFG_SPICTRL_FIFO,
slvselen => 1,
slvselsz => 1,
odmode => CFG_SPICTRL_ODMODE,
automode => CFG_SPICTRL_AM,
aslvsel => CFG_SPICTRL_ASEL,
twen => 0,
maxwlen => CFG_SPICTRL_MAXWLEN,
netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM,
ft => CFG_SPICTRL_FT)
port map (
rstn => rstn,
clk => clkm,
apbi => apbi,
apbo => apbo(5),
spii => spii2,
spio => spio2,
slvsel => slvsel2);
miso_pad : iopad generic map (tech => padtech)
port map (sd_dat0, spio2.miso, spio2.misooen, spii2.miso);
mosi_pad : iopad generic map (tech => padtech)
port map (sd_cmd, spio2.mosi, spio2.mosioen, spii2.mosi);
sck_pad : iopad generic map (tech => padtech)
port map (sd_clk, spio2.sck, spio2.sckoen, spii2.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (sd_dat3, slvsel2(0));
spii2.spisel <= '1'; -- Master only
end generate;
nospic2 : if CFG_SPICTRL_ENABLE = 0 or CFG_SPICTRL_NUM < 2 generate
apbo(5) <= apb_none;
spio2.misooen <= '1';
spio2.mosioen <= '1';
spio2.sckoen <= '1';
slvsel2(0) <= '0';
end generate;
-- SPI Memory Controller
-- Example on how to connect SPI memory controller to SD card. If you want to
-- use this then you need to disable the second SPICTRL core's connections to
-- the same top-level signals above.
--spimc: if false generate
-- spimctrl0 : spimctrl
-- generic map (
-- hindex => 4,
-- hirq => 9,
-- faddr => 16#b00#,
-- fmask => 16#f00#,
-- ioaddr => 16#002#,
-- iomask => 16#fff#,
-- spliten => CFG_SPLIT,
-- oepol => 0,
-- sdcard => CFG_SPIMCTRL_SDCARD,
-- readcmd => CFG_SPIMCTRL_READCMD,
-- dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
-- dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
-- scaler => CFG_SPIMCTRL_SCALER,
-- altscaler => CFG_SPIMCTRL_ASCALER,
-- pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
-- port map (
-- rstn => rstn,
-- clk => clkm,
-- ahbsi => ahbsi,
-- ahbso => ahbso(4),
-- spii => spmi,
-- spio => spmo);
-- miso_pad : inpad generic map (tech => padtech)
-- port map (sd_dat0, spmi.miso);
-- mosi_pad : outpad generic map (tech => padtech)
-- port map (sd_cmd, spmo.mosi);
-- sck_pad : outpad generic map (tech => padtech)
-- port map (sd_clk, spmo.sck);
-- slvsel0_pad : iopad generic map (tech => padtech)
-- port map (sd_dat3, spmo.csn, spmo.cdcsnoen, spmi.cd);
--end generate;
--nospimc : if false generate
-- spmo.mosi <= '0';
-- spmo.mosioen <= '1';
-- spmo.sck <= '0';
-- spmo.csn <= '1';
-- spmo.cdcsnoen <= '1';
-- spmo.errorn <= '0';
-- spmo.ready <= '0';
-- spmo.initialized <= '0';
--end generate;
-- sd_dat1 and sd_dat2 are unused
unuseddat1_pad : iopad generic map (tech => padtech)
port map (sd_dat1, gnd(0), vcc(1), open);
unuseddat2_pad : iopad generic map (tech => padtech)
port map (sd_dat2, gnd(0), vcc(1), open);
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH /= 0 generate -- Gaisler Ethernet MAC
e1 : grethm
generic map(
hindex => CFG_NCPU+CFG_AHB_JTAG,
pindex => 6,
paddr => 6,
pirq => 10,
memtech => memtech,
mdcscaler => CPU_FREQ/(4*1000)-1,
enable_mdio => 1,
fifosize => CFG_ETH_FIFO,
nsync => 1,
edcl => CFG_DSU_ETH,
edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM,
macaddrl => CFG_ETH_ENL,
phyrstadr => 1,
ipaddrh => CFG_ETH_IPM,
ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G)
port map(
rst => rstn,
clk => clkm,
ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_JTAG),
apbi => apbi,
apbo => apbo(6),
ethi => ethi,
etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (rxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (rx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (eth_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (eth_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (txd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (tx_en, etho.tx_en);
emdc_pad : outpad generic map (tech => padtech)
port map (mdc, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (eth_reset_n, rawrstn);
end generate;
noeth : if CFG_GRETH = 0 generate
apbo(6) <= apb_none;
ethi <= eth_in_none;
etho <= eth_out_none;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (
hindex => 3,
haddr => CFG_AHBRODDR,
pipe => CFG_AHBROPIP)
port map (
rst => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(3));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(3) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (
hindex => 5,
haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (
rst => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(5));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(5) <= ahbs_none; end generate;
-----------------------------------------------------------------------
-- AHB Report Module for simulation ----------------------------------
-----------------------------------------------------------------------
--pragma translate_off
test0 : ahbrep generic map (hindex => 6, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(6));
--pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
driveahbm : for i in maxahbm to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
driveahbs : for i in maxahbs to NAHBSLV-1 generate
ahbso(i) <= ahbs_none;
end generate;
driveapb : for i in 7 to NAPBSLV-1 generate
apbo(i) <= apb_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 BeMicro SDK Design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
library IEEE,OSU_AMI05;
use IEEE.std_logic_1164.all;
package CONV_PACK_sniffer_top is
-- define attributes
attribute ENUM_ENCODING : STRING;
end CONV_PACK_sniffer_top;
library IEEE,OSU_AMI05;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_sniffer_top.all;
entity SpiClkDivide_165_3_0_0_DW01_inc_0 is
port( A : in std_logic_vector (8 downto 0); SUM : out std_logic_vector (8
downto 0));
end SpiClkDivide_165_3_0_0_DW01_inc_0;
architecture SYN_rpl of SpiClkDivide_165_3_0_0_DW01_inc_0 is
component XOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component INVX2
port( A : in std_logic; Y : out std_logic);
end component;
component HAX1
port( A, B : in std_logic; YC, YS : out std_logic);
end component;
signal carry_8_port, carry_7_port, carry_6_port, carry_5_port, carry_4_port,
carry_3_port, carry_2_port : std_logic;
begin
U1_1_7 : HAX1 port map( A => A(7), B => carry_7_port, YC => carry_8_port, YS
=> SUM(7));
U1_1_6 : HAX1 port map( A => A(6), B => carry_6_port, YC => carry_7_port, YS
=> SUM(6));
U1_1_5 : HAX1 port map( A => A(5), B => carry_5_port, YC => carry_6_port, YS
=> SUM(5));
U1_1_4 : HAX1 port map( A => A(4), B => carry_4_port, YC => carry_5_port, YS
=> SUM(4));
U1_1_3 : HAX1 port map( A => A(3), B => carry_3_port, YC => carry_4_port, YS
=> SUM(3));
U1_1_2 : HAX1 port map( A => A(2), B => carry_2_port, YC => carry_3_port, YS
=> SUM(2));
U1_1_1 : HAX1 port map( A => A(1), B => A(0), YC => carry_2_port, YS =>
SUM(1));
U1 : INVX2 port map( A => A(0), Y => SUM(0));
U2 : XOR2X1 port map( A => carry_8_port, B => A(8), Y => SUM(8));
end SYN_rpl;
library IEEE,OSU_AMI05;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_sniffer_top.all;
entity sd_control_DW01_inc_0 is
port( A : in std_logic_vector (6 downto 0); SUM : out std_logic_vector (6
downto 0));
end sd_control_DW01_inc_0;
architecture SYN_rpl of sd_control_DW01_inc_0 is
component XOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component INVX2
port( A : in std_logic; Y : out std_logic);
end component;
component HAX1
port( A, B : in std_logic; YC, YS : out std_logic);
end component;
signal carry_6_port, carry_5_port, carry_4_port, carry_3_port, carry_2_port
: std_logic;
begin
U1_1_5 : HAX1 port map( A => A(5), B => carry_5_port, YC => carry_6_port, YS
=> SUM(5));
U1_1_4 : HAX1 port map( A => A(4), B => carry_4_port, YC => carry_5_port, YS
=> SUM(4));
U1_1_3 : HAX1 port map( A => A(3), B => carry_3_port, YC => carry_4_port, YS
=> SUM(3));
U1_1_2 : HAX1 port map( A => A(2), B => carry_2_port, YC => carry_3_port, YS
=> SUM(2));
U1_1_1 : HAX1 port map( A => A(1), B => A(0), YC => carry_2_port, YS =>
SUM(1));
U1 : INVX2 port map( A => A(0), Y => SUM(0));
U2 : XOR2X1 port map( A => carry_6_port, B => A(6), Y => SUM(6));
end SYN_rpl;
library IEEE,OSU_AMI05;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_sniffer_top.all;
entity tristate_2 is
port( lock, interceptorOutput : in std_logic; interceptorInput : out
std_logic; dataLine : inout std_logic);
end tristate_2;
architecture SYN_behavioral of tristate_2 is
component OR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component INVX1
port( A : in std_logic; Y : out std_logic);
end component;
component TBUFX1
port( A, EN : in std_logic; Y : out std_logic);
end component;
signal n1 : std_logic;
begin
dataLine_tri : TBUFX1 port map( A => n1, EN => lock, Y => dataLine);
U1 : INVX1 port map( A => interceptorOutput, Y => n1);
U2 : OR2X1 port map( A => dataLine, B => lock, Y => interceptorInput);
end SYN_behavioral;
library IEEE,OSU_AMI05;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_sniffer_top.all;
entity tristate_1 is
port( lock, interceptorOutput : in std_logic; interceptorInput : out
std_logic; dataLine : inout std_logic);
end tristate_1;
architecture SYN_behavioral of tristate_1 is
component OR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component INVX1
port( A : in std_logic; Y : out std_logic);
end component;
component TBUFX1
port( A, EN : in std_logic; Y : out std_logic);
end component;
signal n1 : std_logic;
begin
dataLine_tri : TBUFX1 port map( A => n1, EN => lock, Y => dataLine);
U1 : INVX1 port map( A => interceptorOutput, Y => n1);
U2 : OR2X1 port map( A => dataLine, B => lock, Y => interceptorInput);
end SYN_behavioral;
library IEEE,OSU_AMI05;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_sniffer_top.all;
entity tristate_0 is
port( lock, interceptorOutput : in std_logic; interceptorInput : out
std_logic; dataLine : inout std_logic);
end tristate_0;
architecture SYN_behavioral of tristate_0 is
component OR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component INVX1
port( A : in std_logic; Y : out std_logic);
end component;
component TBUFX1
port( A, EN : in std_logic; Y : out std_logic);
end component;
signal n1 : std_logic;
begin
dataLine_tri : TBUFX1 port map( A => n1, EN => lock, Y => dataLine);
U1 : INVX1 port map( A => interceptorOutput, Y => n1);
U2 : OR2X1 port map( A => dataLine, B => lock, Y => interceptorInput);
end SYN_behavioral;
library IEEE,OSU_AMI05;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_sniffer_top.all;
entity usbInterceptor is
port( usbClk, rst, intercept, usbDataPlus, usbDataMinus, usbLock, clk, eop :
in std_logic; usbDataPlusOutput, usbDataMinusOutput : out std_logic);
end usbInterceptor;
architecture SYN_behavioral of usbInterceptor is
component INVX1
port( A : in std_logic; Y : out std_logic);
end component;
component NAND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component MUX2X1
port( B, A, S : in std_logic; Y : out std_logic);
end component;
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component NAND3X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component XOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component OR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AOI22X1
port( A, B, C, D : in std_logic; Y : out std_logic);
end component;
component OAI21X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component AOI21X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component OAI22X1
port( A, B, C, D : in std_logic; Y : out std_logic);
end component;
component AND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component INVX2
port( A : in std_logic; Y : out std_logic);
end component;
component HAX1
port( A, B : in std_logic; YC, YS : out std_logic);
end component;
component DFFSR
port( D, CLK, R, S : in std_logic; Q : out std_logic);
end component;
signal usbDataPlusOutput_port, usbDataMinusOutput_port, state_3_port,
state_2_port, state_1_port, state_0_port, cntr_4_port, cntr_3_port,
cntr_2_port, cntr_1_port, cntr_0_port, usbDataPlusSync, usbDataMinusSync,
usbDataPlusSync2, usbDataMinusSync2, usbInt2, usbInt1, n124, n125, n126,
n127, n128, n129, n130, n131, n132, n133, n134, n135, n136, n137, n138,
n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n149, n150,
n151, n152, n153, n155, r118_carry_2_port, r118_carry_3_port,
r118_carry_4_port, r118_SUM_1_port, r118_SUM_2_port, r118_SUM_3_port, n1,
n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32
, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46,
n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61
, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75,
n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90
, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103,
n104, n105, n106, n107, n108, n109, n110, n111, n112, n113, n114, n115,
n116, n117, n118, n119, n120 : std_logic;
begin
usbDataPlusOutput <= usbDataPlusOutput_port;
usbDataMinusOutput <= usbDataMinusOutput_port;
usbInt1_reg : DFFSR port map( D => usbClk, CLK => clk, R => rst, S => n144,
Q => usbInt1);
usbInt2_reg : DFFSR port map( D => usbInt1, CLK => clk, R => rst, S => n143,
Q => usbInt2);
cntr_reg_0_inst : DFFSR port map( D => n147, CLK => clk, R => rst, S => n142
, Q => cntr_0_port);
cntr_reg_4_inst : DFFSR port map( D => n155, CLK => clk, R => rst, S => n141
, Q => cntr_4_port);
state_reg_1_inst : DFFSR port map( D => n151, CLK => clk, R => rst, S =>
n140, Q => state_1_port);
state_reg_0_inst : DFFSR port map( D => n153, CLK => clk, R => rst, S =>
n139, Q => state_0_port);
cntr_reg_1_inst : DFFSR port map( D => n148, CLK => clk, R => rst, S => n138
, Q => cntr_1_port);
cntr_reg_2_inst : DFFSR port map( D => n149, CLK => clk, R => rst, S => n137
, Q => cntr_2_port);
cntr_reg_3_inst : DFFSR port map( D => n150, CLK => clk, R => rst, S => n136
, Q => cntr_3_port);
state_reg_3_inst : DFFSR port map( D => n120, CLK => clk, R => rst, S =>
n135, Q => state_3_port);
state_reg_2_inst : DFFSR port map( D => n152, CLK => clk, R => rst, S =>
n134, Q => state_2_port);
usbDataMinusSync_reg : DFFSR port map( D => n133, CLK => clk, R => rst, S =>
n132, Q => usbDataMinusSync);
usbDataMinusSync2_reg : DFFSR port map( D => n131, CLK => clk, R => rst, S
=> n130, Q => usbDataMinusSync2);
usbDataMinusOutputReg_reg : DFFSR port map( D => n145, CLK => clk, R => rst,
S => n129, Q => usbDataMinusOutput_port);
usbDataPlusSync_reg : DFFSR port map( D => n128, CLK => clk, R => n127, S =>
rst, Q => usbDataPlusSync);
usbDataPlusSync2_reg : DFFSR port map( D => n126, CLK => clk, R => n125, S
=> rst, Q => usbDataPlusSync2);
usbDataPlusOutputReg_reg : DFFSR port map( D => n146, CLK => clk, R => n124,
S => rst, Q => usbDataPlusOutput_port);
n124 <= '1';
n125 <= '1';
n127 <= '1';
n129 <= '1';
n130 <= '1';
n132 <= '1';
n134 <= '1';
n135 <= '1';
n136 <= '1';
n137 <= '1';
n138 <= '1';
n139 <= '1';
n140 <= '1';
n141 <= '1';
n142 <= '1';
n143 <= '1';
n144 <= '1';
r118_U1_1_1 : HAX1 port map( A => cntr_1_port, B => cntr_0_port, YC =>
r118_carry_2_port, YS => r118_SUM_1_port);
r118_U1_1_2 : HAX1 port map( A => cntr_2_port, B => r118_carry_2_port, YC =>
r118_carry_3_port, YS => r118_SUM_2_port);
r118_U1_1_3 : HAX1 port map( A => cntr_3_port, B => r118_carry_3_port, YC =>
r118_carry_4_port, YS => r118_SUM_3_port);
U3 : OAI21X1 port map( A => n78, B => n35, C => n56, Y => n51);
U4 : AOI22X1 port map( A => n47, B => cntr_3_port, C => r118_SUM_3_port, D
=> n11, Y => n1);
U5 : INVX2 port map( A => n1, Y => n150);
U6 : OAI22X1 port map( A => n2, B => n3, C => n4, D => n5, Y => n120);
U7 : INVX1 port map( A => state_3_port, Y => n5);
U8 : MUX2X1 port map( B => n6, A => n7, S => cntr_4_port, Y => n155);
U9 : INVX1 port map( A => n8, Y => n7);
U10 : OAI21X1 port map( A => n9, B => r118_carry_4_port, C => n10, Y => n8);
U11 : NAND2X1 port map( A => r118_carry_4_port, B => n11, Y => n6);
U12 : OAI22X1 port map( A => n4, B => n12, C => n13, D => n3, Y => n153);
U13 : INVX1 port map( A => n14, Y => n13);
U14 : OAI21X1 port map( A => n4, B => n15, C => n16, Y => n152);
U15 : OAI21X1 port map( A => n17, B => n18, C => n19, Y => n16);
U16 : NAND2X1 port map( A => n20, B => n21, Y => n18);
U17 : AND2X1 port map( A => n19, B => n22, Y => n4);
U18 : MUX2X1 port map( B => n23, A => n24, S => n19, Y => n151);
U19 : INVX1 port map( A => n3, Y => n19);
U20 : NAND3X1 port map( A => n25, B => n26, C => n27, Y => n3);
U21 : AOI21X1 port map( A => n28, B => n29, C => n30, Y => n27);
U22 : NOR2X1 port map( A => intercept, B => n31, Y => n30);
U23 : INVX1 port map( A => n32, Y => n26);
U24 : NOR2X1 port map( A => n33, B => n34, Y => n24);
U25 : OAI21X1 port map( A => n35, B => n36, C => n37, Y => n34);
U26 : NAND3X1 port map( A => state_2_port, B => n23, C => n38, Y => n37);
U27 : OR2X1 port map( A => n39, B => n40, Y => n36);
U28 : NAND2X1 port map( A => n41, B => n42, Y => n33);
U29 : OAI21X1 port map( A => n10, B => n43, C => n44, Y => n149);
U30 : NAND2X1 port map( A => r118_SUM_2_port, B => n11, Y => n44);
U31 : OAI21X1 port map( A => n10, B => n45, C => n46, Y => n148);
U32 : NAND2X1 port map( A => r118_SUM_1_port, B => n11, Y => n46);
U33 : INVX1 port map( A => n9, Y => n11);
U34 : MUX2X1 port map( B => n9, A => n10, S => cntr_0_port, Y => n147);
U35 : INVX1 port map( A => n47, Y => n10);
U36 : OAI21X1 port map( A => n48, B => n22, C => n49, Y => n47);
U37 : OAI21X1 port map( A => n40, B => n39, C => n50, Y => n22);
U38 : INVX1 port map( A => cntr_4_port, Y => n39);
U39 : OAI21X1 port map( A => n32, B => n51, C => n49, Y => n9);
U40 : INVX1 port map( A => n52, Y => n49);
U41 : OAI21X1 port map( A => n53, B => n48, C => n25, Y => n52);
U42 : MUX2X1 port map( B => n54, A => n28, S => eop, Y => n25);
U43 : OAI21X1 port map( A => n57, B => n2, C => n53, Y => n32);
U44 : AND2X1 port map( A => n58, B => n59, Y => n53);
U45 : NAND2X1 port map( A => n60, B => n61, Y => n146);
U46 : OAI21X1 port map( A => n62, B => n63, C => n64, Y => n61);
U47 : INVX1 port map( A => n65, Y => n64);
U48 : OAI22X1 port map( A => n56, B => n66, C => usbLock, D => n67, Y => n63
);
U49 : OAI21X1 port map( A => n68, B => n69, C => n70, Y => n62);
U50 : OAI21X1 port map( A => n71, B => n72, C => n73, Y => n70);
U51 : INVX1 port map( A => usbDataPlusOutput_port, Y => n73);
U52 : NOR2X1 port map( A => n74, B => n75, Y => n71);
U53 : INVX1 port map( A => n76, Y => n74);
U54 : OAI21X1 port map( A => n65, B => n77, C => usbDataPlusOutput_port, Y
=> n60);
U55 : OAI22X1 port map( A => eop, B => n67, C => n76, D => n75, Y => n77);
U56 : OAI22X1 port map( A => n78, B => n59, C => n76, D => n55, Y => n65);
U57 : XOR2X1 port map( A => usbDataPlusSync2, B => usbDataPlusSync, Y => n76
);
U58 : OAI21X1 port map( A => n79, B => n80, C => n81, Y => n145);
U59 : OAI21X1 port map( A => n80, B => n82, C => usbDataMinusOutput_port, Y
=> n81);
U60 : OAI21X1 port map( A => n75, B => n83, C => n84, Y => n82);
U61 : NAND3X1 port map( A => n85, B => n86, C => usbLock, Y => n84);
U62 : INVX1 port map( A => n67, Y => n85);
U63 : NOR2X1 port map( A => n87, B => n88, Y => n67);
U64 : OAI21X1 port map( A => usbLock, B => n31, C => n89, Y => n88);
U65 : AOI22X1 port map( A => n90, B => n17, C => n57, D => n91, Y => n89);
U66 : INVX1 port map( A => n92, Y => n90);
U67 : NAND3X1 port map( A => n93, B => n21, C => n94, Y => n87);
U68 : AOI22X1 port map( A => n54, B => n95, C => n96, D => n97, Y => n94);
U69 : INVX1 port map( A => n41, Y => n97);
U70 : INVX1 port map( A => n2, Y => n54);
U71 : OAI21X1 port map( A => n50, B => n14, C => n78, Y => n93);
U72 : NAND3X1 port map( A => n31, B => n41, C => n98, Y => n14);
U73 : NOR2X1 port map( A => n91, B => n17, Y => n98);
U74 : OAI22X1 port map( A => n78, B => n59, C => n55, D => n83, Y => n80);
U75 : OAI21X1 port map( A => cntr_4_port, B => n40, C => n99, Y => n59);
U76 : INVX1 port map( A => n21, Y => n99);
U77 : NAND2X1 port map( A => n38, B => n100, Y => n21);
U78 : XOR2X1 port map( A => state_2_port, B => state_1_port, Y => n100);
U79 : NAND3X1 port map( A => cntr_0_port, B => n45, C => n101, Y => n40);
U80 : NOR2X1 port map( A => cntr_3_port, B => cntr_2_port, Y => n101);
U81 : AOI21X1 port map( A => usbDataMinus, B => n28, C => n102, Y => n79);
U82 : OAI21X1 port map( A => n69, B => n103, C => n104, Y => n102);
U83 : OAI21X1 port map( A => n105, B => n72, C => n106, Y => n104);
U84 : INVX1 port map( A => usbDataMinusOutput_port, Y => n106);
U85 : OAI21X1 port map( A => n58, B => n78, C => n55, Y => n72);
U86 : NAND2X1 port map( A => n48, B => n50, Y => n55);
U87 : INVX1 port map( A => n35, Y => n50);
U88 : NAND2X1 port map( A => n107, B => n38, Y => n35);
U89 : INVX1 port map( A => n108, Y => n58);
U90 : OAI21X1 port map( A => n96, B => n41, C => n109, Y => n108);
U91 : AOI22X1 port map( A => n17, B => n92, C => n91, D => n29, Y => n109);
U92 : INVX1 port map( A => n57, Y => n29);
U93 : NOR2X1 port map( A => n110, B => cntr_2_port, Y => n57);
U94 : INVX1 port map( A => n20, Y => n91);
U95 : NAND3X1 port map( A => n111, B => n23, C => state_2_port, Y => n20);
U96 : INVX1 port map( A => state_1_port, Y => n23);
U97 : NAND3X1 port map( A => n112, B => n45, C => n113, Y => n92);
U98 : NOR2X1 port map( A => cntr_0_port, B => n43, Y => n113);
U99 : INVX1 port map( A => cntr_1_port, Y => n45);
U100 : INVX1 port map( A => n42, Y => n17);
U101 : NAND3X1 port map( A => state_1_port, B => n111, C => state_2_port, Y
=> n42);
U102 : NAND3X1 port map( A => n111, B => n15, C => state_1_port, Y => n41);
U103 : INVX1 port map( A => state_2_port, Y => n15);
U104 : NOR2X1 port map( A => n110, B => n43, Y => n96);
U105 : INVX1 port map( A => cntr_2_port, Y => n43);
U106 : NAND3X1 port map( A => cntr_1_port, B => cntr_0_port, C => n112, Y =>
n110);
U107 : NOR2X1 port map( A => cntr_4_port, B => cntr_3_port, Y => n112);
U108 : NOR2X1 port map( A => n114, B => n75, Y => n105);
U109 : OR2X1 port map( A => n95, B => n2, Y => n75);
U110 : NAND3X1 port map( A => state_2_port, B => state_1_port, C => n38, Y
=> n2);
U111 : NOR2X1 port map( A => n12, B => state_3_port, Y => n38);
U112 : NAND2X1 port map( A => n48, B => n86, Y => n95);
U113 : INVX1 port map( A => eop, Y => n86);
U114 : INVX1 port map( A => n83, Y => n114);
U115 : XOR2X1 port map( A => usbDataMinusSync2, B => usbDataMinusSync, Y =>
n83);
U116 : INVX1 port map( A => usbDataMinusSync, Y => n103);
U117 : NAND3X1 port map( A => n48, B => n115, C => usbLock, Y => n69);
U118 : INVX1 port map( A => n31, Y => n115);
U119 : NAND2X1 port map( A => n107, B => n111, Y => n31);
U120 : NOR2X1 port map( A => state_3_port, B => state_0_port, Y => n111);
U121 : INVX1 port map( A => n56, Y => n28);
U122 : NAND3X1 port map( A => n107, B => n12, C => state_3_port, Y => n56);
U123 : INVX1 port map( A => state_0_port, Y => n12);
U124 : NOR2X1 port map( A => state_2_port, B => state_1_port, Y => n107);
U125 : INVX1 port map( A => n116, Y => n133);
U126 : MUX2X1 port map( B => usbDataMinusSync, A => usbDataMinus, S => n48,
Y => n116);
U127 : INVX1 port map( A => n117, Y => n131);
U128 : MUX2X1 port map( B => usbDataMinusSync2, A => usbDataMinusSync, S =>
n48, Y => n117);
U129 : MUX2X1 port map( B => n68, A => n66, S => n48, Y => n128);
U130 : INVX1 port map( A => usbDataPlus, Y => n66);
U131 : INVX1 port map( A => usbDataPlusSync, Y => n68);
U132 : INVX1 port map( A => n118, Y => n126);
U133 : MUX2X1 port map( B => usbDataPlusSync2, A => usbDataPlusSync, S =>
n48, Y => n118);
U134 : INVX1 port map( A => n78, Y => n48);
U135 : NAND2X1 port map( A => usbInt1, B => n119, Y => n78);
U153 : INVX1 port map( A => usbInt2, Y => n119);
end SYN_behavioral;
library IEEE,OSU_AMI05;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_sniffer_top.all;
entity tristate_3 is
port( lock, interceptorOutput : in std_logic; interceptorInput : out
std_logic; dataLine : inout std_logic);
end tristate_3;
architecture SYN_behavioral of tristate_3 is
component OR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component INVX1
port( A : in std_logic; Y : out std_logic);
end component;
component TBUFX1
port( A, EN : in std_logic; Y : out std_logic);
end component;
signal n1 : std_logic;
begin
dataLine_tri : TBUFX1 port map( A => n1, EN => lock, Y => dataLine);
U1 : INVX1 port map( A => interceptorOutput, Y => n1);
U2 : OR2X1 port map( A => dataLine, B => lock, Y => interceptorInput);
end SYN_behavioral;
library IEEE,OSU_AMI05;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_sniffer_top.all;
entity lockingDetector is
port( endOfPacket, rst, clk : in std_logic; inst : in std_logic_vector (3
downto 0); usbLock, computerLock : out std_logic);
end lockingDetector;
architecture SYN_behavioral of lockingDetector is
component INVX1
port( A : in std_logic; Y : out std_logic);
end component;
component NAND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component MUX2X1
port( B, A, S : in std_logic; Y : out std_logic);
end component;
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component OAI21X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component AOI21X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component XNOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component OR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component DFFSR
port( D, CLK, R, S : in std_logic; Q : out std_logic);
end component;
component DFFPOSX1
port( D, CLK : in std_logic; Q : out std_logic);
end component;
signal state_2_port, state_1_port, state_0_port, lockc, locku, eopIn1,
eopIn2, eopFound, nextState_2_port, nextState_1_port, nextState_0_port,
n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n1, n2, n3,
n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19,
n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34
: std_logic;
begin
eopIn1_reg : DFFSR port map( D => endOfPacket, CLK => clk, R => rst, S =>
n48, Q => eopIn1);
eopIn2_reg : DFFSR port map( D => eopIn1, CLK => clk, R => rst, S => n47, Q
=> eopIn2);
eopFound_reg : DFFPOSX1 port map( D => n46, CLK => clk, Q => eopFound);
state_reg_2_inst : DFFSR port map( D => nextState_2_port, CLK => clk, R =>
rst, S => n45, Q => state_2_port);
state_reg_1_inst : DFFSR port map( D => nextState_1_port, CLK => clk, R =>
rst, S => n44, Q => state_1_port);
state_reg_0_inst : DFFSR port map( D => nextState_0_port, CLK => clk, R =>
rst, S => n43, Q => state_0_port);
locku_reg : DFFSR port map( D => n49, CLK => clk, R => rst, S => n42, Q =>
locku);
usbLock_reg : DFFSR port map( D => locku, CLK => clk, R => rst, S => n41, Q
=> usbLock);
lockc_reg : DFFSR port map( D => n50, CLK => clk, R => n40, S => rst, Q =>
lockc);
computerLock_reg : DFFSR port map( D => lockc, CLK => clk, R => n39, S =>
rst, Q => computerLock);
n39 <= '1';
n40 <= '1';
n41 <= '1';
n42 <= '1';
n43 <= '1';
n44 <= '1';
n45 <= '1';
n47 <= '1';
n48 <= '1';
U3 : OAI21X1 port map( A => n19, B => n9, C => n15, Y => nextState_0_port);
U4 : OAI21X1 port map( A => n1, B => n2, C => n3, Y => nextState_2_port);
U5 : OAI21X1 port map( A => n4, B => n5, C => n6, Y => n3);
U6 : NOR2X1 port map( A => state_1_port, B => state_0_port, Y => n6);
U7 : OR2X1 port map( A => inst(1), B => inst(2), Y => n5);
U8 : XNOR2X1 port map( A => inst(3), B => n7, Y => n4);
U9 : NOR2X1 port map( A => n8, B => n9, Y => n1);
U10 : OAI21X1 port map( A => eopFound, B => n10, C => n11, Y =>
nextState_1_port);
U11 : OAI21X1 port map( A => n12, B => state_1_port, C => n9, Y => n11);
U12 : AOI21X1 port map( A => n13, B => n14, C => state_2_port, Y => n12);
U13 : INVX1 port map( A => inst(1), Y => n14);
U14 : MUX2X1 port map( B => inst(3), A => n7, S => inst(2), Y => n13);
U15 : INVX1 port map( A => inst(0), Y => n7);
U16 : INVX1 port map( A => n16, Y => n10);
U17 : MUX2X1 port map( B => n17, A => n18, S => n8, Y => n15);
U18 : NAND2X1 port map( A => n2, B => n19, Y => n17);
U19 : INVX1 port map( A => n20, Y => n50);
U20 : MUX2X1 port map( B => n21, A => lockc, S => n22, Y => n20);
U21 : OAI21X1 port map( A => state_1_port, B => state_0_port, C => n23, Y =>
n21);
U22 : OAI21X1 port map( A => n2, B => n24, C => n16, Y => n23);
U23 : INVX1 port map( A => lockc, Y => n24);
U24 : MUX2X1 port map( B => n25, A => n26, S => n22, Y => n49);
U25 : OAI21X1 port map( A => eopFound, B => n27, C => n28, Y => n22);
U26 : MUX2X1 port map( B => n29, A => n18, S => n2, Y => n28);
U27 : AOI21X1 port map( A => eopFound, B => n19, C => state_0_port, Y => n29
);
U28 : NOR2X1 port map( A => n16, B => n30, Y => n27);
U29 : INVX1 port map( A => locku, Y => n26);
U30 : AOI21X1 port map( A => n31, B => n16, C => n30, Y => n25);
U31 : OAI21X1 port map( A => state_0_port, B => n19, C => n32, Y => n30);
U32 : INVX1 port map( A => n18, Y => n32);
U33 : NOR2X1 port map( A => n9, B => state_1_port, Y => n18);
U34 : NOR2X1 port map( A => n19, B => n9, Y => n16);
U35 : INVX1 port map( A => state_0_port, Y => n9);
U36 : INVX1 port map( A => state_1_port, Y => n19);
U37 : NOR2X1 port map( A => locku, B => n2, Y => n31);
U38 : INVX1 port map( A => state_2_port, Y => n2);
U39 : MUX2X1 port map( B => n8, A => n33, S => rst, Y => n46);
U40 : NAND2X1 port map( A => eopIn2, B => n34, Y => n33);
U41 : INVX1 port map( A => eopIn1, Y => n34);
U42 : INVX1 port map( A => eopFound, Y => n8);
end SYN_behavioral;
library IEEE,OSU_AMI05;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_sniffer_top.all;
entity computerInterceptor is
port( usbClk, rst, computerDataPlus, computerDataMinus, computerLock, clk,
eop : in std_logic; computerDataPlusOutput, computerDataMinusOutput :
out std_logic);
end computerInterceptor;
architecture SYN_behavioral of computerInterceptor is
component INVX1
port( A : in std_logic; Y : out std_logic);
end component;
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component NAND3X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component OAI21X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component MUX2X1
port( B, A, S : in std_logic; Y : out std_logic);
end component;
component AOI21X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component NAND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component DFFSR
port( D, CLK, R, S : in std_logic; Q : out std_logic);
end component;
signal computerDataPlusOutput_port, computerDataMinusOutput_port,
computerDataPlusSync, computerDataMinusSync, usbInt2, usbInt1, eopInt1,
eopInt2, n1, n2, n3, n4, n5, n6, n7, n8, n24, n25, n9, n10, n11, n12, n13
, n14, n15, n16, n17, n18, n19 : std_logic;
begin
computerDataPlusOutput <= computerDataPlusOutput_port;
computerDataMinusOutput <= computerDataMinusOutput_port;
computerDataPlusSync_reg : DFFSR port map( D => computerDataPlus, CLK => clk
, R => n8, S => rst, Q => computerDataPlusSync);
computerDataMinusSync_reg : DFFSR port map( D => computerDataMinus, CLK =>
clk, R => rst, S => n7, Q => computerDataMinusSync);
usbInt1_reg : DFFSR port map( D => usbClk, CLK => clk, R => n6, S => rst, Q
=> usbInt1);
usbInt2_reg : DFFSR port map( D => usbInt1, CLK => clk, R => rst, S => n5, Q
=> usbInt2);
eopInt1_reg : DFFSR port map( D => eop, CLK => clk, R => rst, S => n4, Q =>
eopInt1);
eopInt2_reg : DFFSR port map( D => eopInt1, CLK => clk, R => rst, S => n3, Q
=> eopInt2);
computerDataPlusOutput_reg : DFFSR port map( D => n25, CLK => clk, R => n2,
S => rst, Q => computerDataPlusOutput_port);
computerDataMinusOutput_reg : DFFSR port map( D => n24, CLK => clk, R => rst
, S => n1, Q => computerDataMinusOutput_port);
n1 <= '1';
n2 <= '1';
n3 <= '1';
n4 <= '1';
n5 <= '1';
n6 <= '1';
n7 <= '1';
n8 <= '1';
U11 : INVX1 port map( A => n9, Y => n25);
U12 : MUX2X1 port map( B => computerDataPlusOutput_port, A => n10, S => n11,
Y => n9);
U13 : NAND2X1 port map( A => n12, B => computerLock, Y => n10);
U14 : AOI21X1 port map( A => computerDataPlusSync, B => n13, C => n14, Y =>
n12);
U15 : INVX1 port map( A => eop, Y => n13);
U16 : MUX2X1 port map( B => n15, A => n16, S => n11, Y => n24);
U17 : OAI21X1 port map( A => usbInt2, B => n17, C => n18, Y => n11);
U18 : INVX1 port map( A => usbInt1, Y => n17);
U19 : NAND3X1 port map( A => computerDataMinusSync, B => computerLock, C =>
n18, Y => n16);
U20 : NOR2X1 port map( A => eop, B => n14, Y => n18);
U21 : NOR2X1 port map( A => n19, B => eopInt1, Y => n14);
U22 : INVX1 port map( A => eopInt2, Y => n19);
U23 : INVX1 port map( A => computerDataMinusOutput_port, Y => n15);
end SYN_behavioral;
library IEEE,OSU_AMI05;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_sniffer_top.all;
entity timer is
port( clk, rst, egde_det, f_egde_det, EOP : in std_logic; data_clk,
shift_en : out std_logic);
end timer;
architecture SYN_FSM of timer is
component INVX1
port( A : in std_logic; Y : out std_logic);
end component;
component NAND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component MUX2X1
port( B, A, S : in std_logic; Y : out std_logic);
end component;
component OR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component XNOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AOI22X1
port( A, B, C, D : in std_logic; Y : out std_logic);
end component;
component XOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AOI21X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component BUFX2
port( A : in std_logic; Y : out std_logic);
end component;
component INVX2
port( A : in std_logic; Y : out std_logic);
end component;
component OAI21X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component NAND3X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component DFFSR
port( D, CLK, R, S : in std_logic; Q : out std_logic);
end component;
signal n28, CS_3_port, CS_2_port, CS_1_port, CS_0_port, NS_3_port, NS_2_port
, NS_1_port, NS_0_port, nxt_shift_en, dclk_nxt, n12, n13, n14, n15, n16,
n17, n1, n2, n3, n5, n6, n7, n8, n9, n10, n11, n18, n19, n20, n21, n22,
n23, n24, n25, n26, n27 : std_logic;
begin
CS_reg_0_inst : DFFSR port map( D => NS_0_port, CLK => clk, R => rst, S =>
n17, Q => CS_0_port);
CS_reg_2_inst : DFFSR port map( D => NS_2_port, CLK => clk, R => rst, S =>
n16, Q => CS_2_port);
CS_reg_3_inst : DFFSR port map( D => NS_3_port, CLK => clk, R => rst, S =>
n15, Q => CS_3_port);
CS_reg_1_inst : DFFSR port map( D => NS_1_port, CLK => clk, R => rst, S =>
n14, Q => CS_1_port);
cur_shift_en_reg : DFFSR port map( D => nxt_shift_en, CLK => clk, R => rst,
S => n13, Q => n28);
dclk_cur_reg : DFFSR port map( D => dclk_nxt, CLK => clk, R => rst, S => n12
, Q => data_clk);
n12 <= '1';
n13 <= '1';
n14 <= '1';
n15 <= '1';
n16 <= '1';
n17 <= '1';
U3 : NAND3X1 port map( A => n7, B => n5, C => n6, Y => n1);
U4 : INVX2 port map( A => n1, Y => nxt_shift_en);
U5 : OAI21X1 port map( A => n24, B => n18, C => n2, Y => n20);
U6 : INVX2 port map( A => n5, Y => n2);
U7 : OAI21X1 port map( A => n24, B => n18, C => CS_0_port, Y => n3);
U8 : INVX2 port map( A => n3, Y => n23);
U9 : BUFX2 port map( A => n28, Y => shift_en);
U10 : AOI21X1 port map( A => n8, B => n5, C => CS_3_port, Y => dclk_nxt);
U11 : XOR2X1 port map( A => n6, B => CS_2_port, Y => n8);
U18 : NOR2X1 port map( A => n9, B => n10, Y => NS_3_port);
U19 : AOI22X1 port map( A => n11, B => n7, C => CS_3_port, D => n18, Y => n9
);
U20 : NOR2X1 port map( A => n10, B => n19, Y => NS_2_port);
U21 : MUX2X1 port map( B => n7, A => n18, S => n11, Y => n19);
U22 : INVX1 port map( A => n6, Y => n11);
U23 : NAND2X1 port map( A => CS_1_port, B => CS_0_port, Y => n6);
U24 : NOR2X1 port map( A => n18, B => CS_3_port, Y => n7);
U25 : NOR2X1 port map( A => n10, B => n20, Y => NS_1_port);
U26 : XNOR2X1 port map( A => CS_0_port, B => CS_1_port, Y => n5);
U27 : OR2X1 port map( A => EOP, B => egde_det, Y => n10);
U28 : MUX2X1 port map( B => n21, A => n22, S => n23, Y => NS_0_port);
U29 : MUX2X1 port map( B => n25, A => f_egde_det, S => n26, Y => n21);
U30 : NOR2X1 port map( A => CS_1_port, B => n27, Y => n26);
U31 : NAND2X1 port map( A => n18, B => n24, Y => n27);
U32 : INVX1 port map( A => CS_3_port, Y => n24);
U33 : INVX1 port map( A => CS_2_port, Y => n18);
U34 : NAND2X1 port map( A => EOP, B => n22, Y => n25);
U35 : INVX1 port map( A => egde_det, Y => n22);
end SYN_FSM;
library IEEE,OSU_AMI05;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_sniffer_top.all;
entity shift_greg is
port( clk, rst, shift_en, data_in : in std_logic; data_out : out
std_logic_vector (7 downto 0); data_ready : out std_logic);
end shift_greg;
architecture SYN_shift of shift_greg is
component OR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component INVX1
port( A : in std_logic; Y : out std_logic);
end component;
component NAND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component MUX2X1
port( B, A, S : in std_logic; Y : out std_logic);
end component;
component XOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component XNOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component DFFSR
port( D, CLK, R, S : in std_logic; Q : out std_logic);
end component;
signal data_out_7_port, data_out_6_port, data_out_5_port, data_out_4_port,
data_out_3_port, data_out_2_port, data_out_1_port, data_out_0_port,
cnt_2_port, cnt_1_port, cnt_0_port, N3, n17, n18, n19, n20, n21, n22, n23
, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37,
n38, n39, n1, n2, n3_port, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13,
n14 : std_logic;
begin
data_out <= ( data_out_7_port, data_out_6_port, data_out_5_port,
data_out_4_port, data_out_3_port, data_out_2_port, data_out_1_port,
data_out_0_port );
cnt_reg_0_inst : DFFSR port map( D => n39, CLK => clk, R => rst, S => n38, Q
=> cnt_0_port);
cnt_reg_1_inst : DFFSR port map( D => n37, CLK => clk, R => rst, S => n36, Q
=> cnt_1_port);
cnt_reg_2_inst : DFFSR port map( D => n35, CLK => clk, R => rst, S => n34, Q
=> cnt_2_port);
pre_val_reg_7_inst : DFFSR port map( D => n33, CLK => clk, R => rst, S =>
n32, Q => data_out_7_port);
pre_val_reg_6_inst : DFFSR port map( D => n31, CLK => clk, R => rst, S =>
n30, Q => data_out_6_port);
pre_val_reg_5_inst : DFFSR port map( D => n29, CLK => clk, R => rst, S =>
n28, Q => data_out_5_port);
pre_val_reg_4_inst : DFFSR port map( D => n27, CLK => clk, R => rst, S =>
n26, Q => data_out_4_port);
pre_val_reg_3_inst : DFFSR port map( D => n25, CLK => clk, R => rst, S =>
n24, Q => data_out_3_port);
pre_val_reg_2_inst : DFFSR port map( D => n23, CLK => clk, R => rst, S =>
n22, Q => data_out_2_port);
pre_val_reg_1_inst : DFFSR port map( D => n21, CLK => clk, R => rst, S =>
n20, Q => data_out_1_port);
pre_val_reg_0_inst : DFFSR port map( D => n19, CLK => clk, R => rst, S =>
n18, Q => data_out_0_port);
cur_data_ready_reg : DFFSR port map( D => N3, CLK => clk, R => rst, S => n17
, Q => data_ready);
n17 <= '1';
n18 <= '1';
n20 <= '1';
n22 <= '1';
n24 <= '1';
n26 <= '1';
n28 <= '1';
n30 <= '1';
n32 <= '1';
n34 <= '1';
n36 <= '1';
n38 <= '1';
U3 : XNOR2X1 port map( A => shift_en, B => n1, Y => n39);
U4 : XNOR2X1 port map( A => cnt_1_port, B => n2, Y => n37);
U5 : XOR2X1 port map( A => cnt_2_port, B => n3_port, Y => n35);
U6 : NOR2X1 port map( A => n4, B => n2, Y => n3_port);
U7 : NAND2X1 port map( A => cnt_0_port, B => shift_en, Y => n2);
U8 : INVX1 port map( A => cnt_1_port, Y => n4);
U9 : INVX1 port map( A => n5, Y => n33);
U10 : MUX2X1 port map( B => data_out_7_port, A => data_in, S => shift_en, Y
=> n5);
U11 : INVX1 port map( A => n6, Y => n31);
U12 : MUX2X1 port map( B => data_out_6_port, A => data_out_7_port, S =>
shift_en, Y => n6);
U13 : INVX1 port map( A => n7, Y => n29);
U14 : MUX2X1 port map( B => data_out_5_port, A => data_out_6_port, S =>
shift_en, Y => n7);
U15 : INVX1 port map( A => n8, Y => n27);
U16 : MUX2X1 port map( B => data_out_4_port, A => data_out_5_port, S =>
shift_en, Y => n8);
U17 : INVX1 port map( A => n9, Y => n25);
U18 : MUX2X1 port map( B => data_out_3_port, A => data_out_4_port, S =>
shift_en, Y => n9);
U19 : INVX1 port map( A => n10, Y => n23);
U20 : MUX2X1 port map( B => data_out_2_port, A => data_out_3_port, S =>
shift_en, Y => n10);
U21 : INVX1 port map( A => n11, Y => n21);
U22 : MUX2X1 port map( B => data_out_1_port, A => data_out_2_port, S =>
shift_en, Y => n11);
U23 : INVX1 port map( A => n12, Y => n19);
U24 : MUX2X1 port map( B => data_out_0_port, A => data_out_1_port, S =>
shift_en, Y => n12);
U25 : NOR2X1 port map( A => n13, B => n14, Y => N3);
U26 : NAND2X1 port map( A => rst, B => n1, Y => n14);
U27 : INVX1 port map( A => cnt_0_port, Y => n1);
U28 : OR2X1 port map( A => cnt_1_port, B => cnt_2_port, Y => n13);
end SYN_shift;
library IEEE,OSU_AMI05;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_sniffer_top.all;
entity NRZIdecode is
port( clk, rst, data0, enable, EOP : in std_logic; data_out : out std_logic
);
end NRZIdecode;
architecture SYN_NRZI of NRZIdecode is
component INVX1
port( A : in std_logic; Y : out std_logic);
end component;
component NAND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component OAI21X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component AND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component MUX2X1
port( B, A, S : in std_logic; Y : out std_logic);
end component;
component DFFSR
port( D, CLK, R, S : in std_logic; Q : out std_logic);
end component;
signal data_out_port, data0_buf0, n8, n9, n10, n12, n1, n2, n3, n4, n5, n6,
n7, n11 : std_logic;
begin
data_out <= data_out_port;
data0_buf0_reg : DFFSR port map( D => n11, CLK => clk, R => n10, S => n12, Q
=> data0_buf0);
data_out_reg : DFFSR port map( D => n9, CLK => clk, R => n8, S => rst, Q =>
data_out_port);
n8 <= '1';
U3 : INVX1 port map( A => n1, Y => n11);
U4 : OAI21X1 port map( A => n2, B => n3, C => n4, Y => n9);
U5 : MUX2X1 port map( B => n5, A => n1, S => n6, Y => n4);
U6 : NOR2X1 port map( A => data0_buf0, B => EOP, Y => n1);
U7 : AND2X1 port map( A => n2, B => data0_buf0, Y => n5);
U8 : INVX1 port map( A => data_out_port, Y => n3);
U9 : INVX1 port map( A => EOP, Y => n2);
U10 : OAI21X1 port map( A => enable, B => n7, C => n10, Y => n12);
U11 : INVX1 port map( A => rst, Y => n7);
U12 : NAND2X1 port map( A => enable, B => n6, Y => n10);
U13 : INVX1 port map( A => data0, Y => n6);
end SYN_NRZI;
library IEEE,OSU_AMI05;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_sniffer_top.all;
entity SEE_det is
port( clk, rst, data0, data1 : in std_logic; EGDE, F_EGDE, EOP : out
std_logic);
end SEE_det;
architecture SYN_SOP_EOP of SEE_det is
component INVX1
port( A : in std_logic; Y : out std_logic);
end component;
component OR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component NAND3X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component OAI21X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component DFFSR
port( D, CLK, R, S : in std_logic; Q : out std_logic);
end component;
signal d1, d2, nxt_EOP, nxt_EGDE, nxt_FEGDE, n1, n2, n3, n4, n5, n6, n7, n8,
n9, n10 : std_logic;
begin
cur_EOP_reg : DFFSR port map( D => nxt_EOP, CLK => clk, R => rst, S => n5, Q
=> EOP);
d1_reg : DFFSR port map( D => data0, CLK => clk, R => n4, S => rst, Q => d1)
;
d2_reg : DFFSR port map( D => d1, CLK => clk, R => n3, S => rst, Q => d2);
cur_EGDE_reg : DFFSR port map( D => nxt_EGDE, CLK => clk, R => rst, S => n2,
Q => EGDE);
cur_FEGDE_reg : DFFSR port map( D => nxt_FEGDE, CLK => clk, R => rst, S =>
n1, Q => F_EGDE);
n1 <= '1';
n2 <= '1';
n3 <= '1';
n4 <= '1';
n5 <= '1';
U8 : INVX1 port map( A => n6, Y => nxt_FEGDE);
U9 : NOR2X1 port map( A => n7, B => n8, Y => nxt_EOP);
U10 : OR2X1 port map( A => data1, B => data0, Y => n8);
U11 : OAI21X1 port map( A => n9, B => n10, C => n6, Y => nxt_EGDE);
U12 : NAND3X1 port map( A => d2, B => n9, C => rst, Y => n6);
U13 : OR2X1 port map( A => n7, B => d2, Y => n10);
U14 : INVX1 port map( A => rst, Y => n7);
U15 : INVX1 port map( A => d1, Y => n9);
end SYN_SOP_EOP;
library IEEE,OSU_AMI05;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_sniffer_top.all;
entity FifoWrite_gregLength4_addrSize2 is
port( clk, resetN, wEnable, fifoFull : in std_logic; wSel : out
std_logic_vector (1 downto 0));
end FifoWrite_gregLength4_addrSize2;
architecture SYN_FifoWrite_arch of FifoWrite_gregLength4_addrSize2 is
component INVX1
port( A : in std_logic; Y : out std_logic);
end component;
component NAND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component XOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component DFFSR
port( D, CLK, R, S : in std_logic; Q : out std_logic);
end component;
signal wSel_1_port, wSel_0_port, n1, n2, n10, n11, n3, n4, n5, n6 :
std_logic;
begin
wSel <= ( wSel_1_port, wSel_0_port );
count_reg_0_inst : DFFSR port map( D => n11, CLK => clk, R => resetN, S =>
n2, Q => wSel_0_port);
count_reg_1_inst : DFFSR port map( D => n10, CLK => clk, R => resetN, S =>
n1, Q => wSel_1_port);
n1 <= '1';
n2 <= '1';
U5 : XOR2X1 port map( A => n3, B => n4, Y => n11);
U6 : XOR2X1 port map( A => wSel_1_port, B => n5, Y => n10);
U7 : NOR2X1 port map( A => n3, B => n4, Y => n5);
U8 : NAND2X1 port map( A => wEnable, B => n6, Y => n4);
U9 : INVX1 port map( A => fifoFull, Y => n6);
U10 : INVX1 port map( A => wSel_0_port, Y => n3);
end SYN_FifoWrite_arch;
library IEEE,OSU_AMI05;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_sniffer_top.all;
entity FifoRead_gregLength4_addrSize2 is
port( clk, resetN, rEnable, fifoEmpty : in std_logic; rSel : out
std_logic_vector (1 downto 0));
end FifoRead_gregLength4_addrSize2;
architecture SYN_FifoRead_arch of FifoRead_gregLength4_addrSize2 is
component INVX1
port( A : in std_logic; Y : out std_logic);
end component;
component NAND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component XOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component DFFSR
port( D, CLK, R, S : in std_logic; Q : out std_logic);
end component;
signal rSel_1_port, rSel_0_port, n1, n2, n10, n11, n3, n4, n5, n6 :
std_logic;
begin
rSel <= ( rSel_1_port, rSel_0_port );
count_reg_0_inst : DFFSR port map( D => n11, CLK => clk, R => resetN, S =>
n2, Q => rSel_0_port);
count_reg_1_inst : DFFSR port map( D => n10, CLK => clk, R => resetN, S =>
n1, Q => rSel_1_port);
n1 <= '1';
n2 <= '1';
U5 : XOR2X1 port map( A => n3, B => n4, Y => n11);
U6 : XOR2X1 port map( A => rSel_1_port, B => n5, Y => n10);
U7 : NOR2X1 port map( A => n3, B => n4, Y => n5);
U8 : NAND2X1 port map( A => rEnable, B => n6, Y => n4);
U9 : INVX1 port map( A => fifoEmpty, Y => n6);
U10 : INVX1 port map( A => rSel_0_port, Y => n3);
end SYN_FifoRead_arch;
library IEEE,OSU_AMI05;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_sniffer_top.all;
entity FifoRam_gregLength4_gregWidth8_addrSize2 is
port( clk, resetN, wEnable : in std_logic; wData : in std_logic_vector (7
downto 0); wSel, rSel : in std_logic_vector (1 downto 0); rData :
out std_logic_vector (7 downto 0); fifoEmpty, fifoFull : out
std_logic);
end FifoRam_gregLength4_gregWidth8_addrSize2;
architecture SYN_FifoRam_arch of FifoRam_gregLength4_gregWidth8_addrSize2 is
component INVX1
port( A : in std_logic; Y : out std_logic);
end component;
component XNOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component NAND3X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component MUX2X1
port( B, A, S : in std_logic; Y : out std_logic);
end component;
component AOI22X1
port( A, B, C, D : in std_logic; Y : out std_logic);
end component;
component NAND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component DFFSR
port( D, CLK, R, S : in std_logic; Q : out std_logic);
end component;
signal fifoFull_port, N4, N7, gregData_3_7_port, gregData_3_6_port,
gregData_3_5_port, gregData_3_4_port, gregData_3_3_port,
gregData_3_2_port, gregData_3_1_port, gregData_3_0_port,
gregData_2_7_port, gregData_2_6_port, gregData_2_5_port,
gregData_2_4_port, gregData_2_3_port, gregData_2_2_port,
gregData_2_1_port, gregData_2_0_port, gregData_1_7_port,
gregData_1_6_port, gregData_1_5_port, gregData_1_4_port,
gregData_1_3_port, gregData_1_2_port, gregData_1_1_port,
gregData_1_0_port, gregData_0_7_port, gregData_0_6_port,
gregData_0_5_port, gregData_0_4_port, gregData_0_3_port,
gregData_0_2_port, gregData_0_1_port, gregData_0_0_port, n77, n79, n81,
n83, n85, n87, n89, n91, n93, n95, n97, n99, n101, n103, n105, n107, n109
, n111, n113, n115, n117, n119, n121, n123, n125, n127, n129, n131, n133,
n135, n137, n139, n141, n142, n1, n2, n3, n4_port, n5, n6, n7_port, n8,
n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23,
n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38
, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52,
n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67
, n68, n69, n70, n71, n72, n73, n74, n75, n76, n78, n80, n82, n84, n86,
n88, n90, n92, n94, n96, n98, n100, n102, n104, n106, n108, n110, n112,
n114, n116, n118, n120 : std_logic;
begin
fifoFull <= fifoFull_port;
fifoEmptyReg_reg : DFFSR port map( D => N4, CLK => clk, R => n142, S =>
resetN, Q => fifoEmpty);
fifoFullReg_reg : DFFSR port map( D => N7, CLK => clk, R => resetN, S =>
n141, Q => fifoFull_port);
gregData_reg_3_7_inst : DFFSR port map( D => n70, CLK => clk, R => resetN, S
=> n139, Q => gregData_3_7_port);
gregData_reg_3_6_inst : DFFSR port map( D => n74, CLK => clk, R => resetN, S
=> n137, Q => gregData_3_6_port);
gregData_reg_3_5_inst : DFFSR port map( D => n80, CLK => clk, R => resetN, S
=> n135, Q => gregData_3_5_port);
gregData_reg_3_4_inst : DFFSR port map( D => n88, CLK => clk, R => resetN, S
=> n133, Q => gregData_3_4_port);
gregData_reg_3_3_inst : DFFSR port map( D => n96, CLK => clk, R => resetN, S
=> n131, Q => gregData_3_3_port);
gregData_reg_3_2_inst : DFFSR port map( D => n104, CLK => clk, R => resetN,
S => n129, Q => gregData_3_2_port);
gregData_reg_3_1_inst : DFFSR port map( D => n112, CLK => clk, R => resetN,
S => n127, Q => gregData_3_1_port);
gregData_reg_3_0_inst : DFFSR port map( D => n120, CLK => clk, R => resetN,
S => n125, Q => gregData_3_0_port);
gregData_reg_2_7_inst : DFFSR port map( D => n69, CLK => clk, R => resetN, S
=> n123, Q => gregData_2_7_port);
gregData_reg_2_6_inst : DFFSR port map( D => n73, CLK => clk, R => resetN, S
=> n121, Q => gregData_2_6_port);
gregData_reg_2_5_inst : DFFSR port map( D => n78, CLK => clk, R => resetN, S
=> n119, Q => gregData_2_5_port);
gregData_reg_2_4_inst : DFFSR port map( D => n86, CLK => clk, R => resetN, S
=> n117, Q => gregData_2_4_port);
gregData_reg_2_3_inst : DFFSR port map( D => n94, CLK => clk, R => resetN, S
=> n115, Q => gregData_2_3_port);
gregData_reg_2_2_inst : DFFSR port map( D => n102, CLK => clk, R => resetN,
S => n113, Q => gregData_2_2_port);
gregData_reg_2_1_inst : DFFSR port map( D => n110, CLK => clk, R => resetN,
S => n111, Q => gregData_2_1_port);
gregData_reg_2_0_inst : DFFSR port map( D => n118, CLK => clk, R => resetN,
S => n109, Q => gregData_2_0_port);
gregData_reg_1_7_inst : DFFSR port map( D => n68, CLK => clk, R => resetN, S
=> n107, Q => gregData_1_7_port);
gregData_reg_1_6_inst : DFFSR port map( D => n72, CLK => clk, R => resetN, S
=> n105, Q => gregData_1_6_port);
gregData_reg_1_5_inst : DFFSR port map( D => n76, CLK => clk, R => resetN, S
=> n103, Q => gregData_1_5_port);
gregData_reg_1_4_inst : DFFSR port map( D => n84, CLK => clk, R => resetN, S
=> n101, Q => gregData_1_4_port);
gregData_reg_1_3_inst : DFFSR port map( D => n92, CLK => clk, R => resetN, S
=> n99, Q => gregData_1_3_port);
gregData_reg_1_2_inst : DFFSR port map( D => n100, CLK => clk, R => resetN,
S => n97, Q => gregData_1_2_port);
gregData_reg_1_1_inst : DFFSR port map( D => n108, CLK => clk, R => resetN,
S => n95, Q => gregData_1_1_port);
gregData_reg_1_0_inst : DFFSR port map( D => n116, CLK => clk, R => resetN,
S => n93, Q => gregData_1_0_port);
gregData_reg_0_7_inst : DFFSR port map( D => n67, CLK => clk, R => resetN, S
=> n91, Q => gregData_0_7_port);
gregData_reg_0_6_inst : DFFSR port map( D => n71, CLK => clk, R => resetN, S
=> n89, Q => gregData_0_6_port);
gregData_reg_0_5_inst : DFFSR port map( D => n75, CLK => clk, R => resetN, S
=> n87, Q => gregData_0_5_port);
gregData_reg_0_4_inst : DFFSR port map( D => n82, CLK => clk, R => resetN, S
=> n85, Q => gregData_0_4_port);
gregData_reg_0_3_inst : DFFSR port map( D => n90, CLK => clk, R => resetN, S
=> n83, Q => gregData_0_3_port);
gregData_reg_0_2_inst : DFFSR port map( D => n98, CLK => clk, R => resetN, S
=> n81, Q => gregData_0_2_port);
gregData_reg_0_1_inst : DFFSR port map( D => n106, CLK => clk, R => resetN,
S => n79, Q => gregData_0_1_port);
gregData_reg_0_0_inst : DFFSR port map( D => n114, CLK => clk, R => resetN,
S => n77, Q => gregData_0_0_port);
n77 <= '1';
n79 <= '1';
n81 <= '1';
n83 <= '1';
n85 <= '1';
n87 <= '1';
n89 <= '1';
n91 <= '1';
n93 <= '1';
n95 <= '1';
n97 <= '1';
n99 <= '1';
n101 <= '1';
n103 <= '1';
n105 <= '1';
n107 <= '1';
n109 <= '1';
n111 <= '1';
n113 <= '1';
n115 <= '1';
n117 <= '1';
n119 <= '1';
n121 <= '1';
n123 <= '1';
n125 <= '1';
n127 <= '1';
n129 <= '1';
n131 <= '1';
n133 <= '1';
n135 <= '1';
n137 <= '1';
n139 <= '1';
n141 <= '1';
n142 <= '1';
U3 : NAND2X1 port map( A => n1, B => n2, Y => rData(7));
U4 : AOI22X1 port map( A => gregData_3_7_port, B => n3, C =>
gregData_2_7_port, D => n4_port, Y => n2);
U5 : AOI22X1 port map( A => gregData_1_7_port, B => n5, C =>
gregData_0_7_port, D => n6, Y => n1);
U6 : NAND2X1 port map( A => n7_port, B => n8, Y => rData(6));
U7 : AOI22X1 port map( A => gregData_3_6_port, B => n3, C =>
gregData_2_6_port, D => n4_port, Y => n8);
U8 : AOI22X1 port map( A => gregData_1_6_port, B => n5, C =>
gregData_0_6_port, D => n6, Y => n7_port);
U9 : NAND2X1 port map( A => n9, B => n10, Y => rData(5));
U10 : AOI22X1 port map( A => gregData_3_5_port, B => n3, C =>
gregData_2_5_port, D => n4_port, Y => n10);
U11 : AOI22X1 port map( A => gregData_1_5_port, B => n5, C =>
gregData_0_5_port, D => n6, Y => n9);
U12 : NAND2X1 port map( A => n11, B => n12, Y => rData(4));
U13 : AOI22X1 port map( A => gregData_3_4_port, B => n3, C =>
gregData_2_4_port, D => n4_port, Y => n12);
U14 : AOI22X1 port map( A => gregData_1_4_port, B => n5, C =>
gregData_0_4_port, D => n6, Y => n11);
U15 : NAND2X1 port map( A => n13, B => n14, Y => rData(3));
U16 : AOI22X1 port map( A => gregData_3_3_port, B => n3, C =>
gregData_2_3_port, D => n4_port, Y => n14);
U17 : AOI22X1 port map( A => gregData_1_3_port, B => n5, C =>
gregData_0_3_port, D => n6, Y => n13);
U18 : NAND2X1 port map( A => n15, B => n16, Y => rData(2));
U19 : AOI22X1 port map( A => gregData_3_2_port, B => n3, C =>
gregData_2_2_port, D => n4_port, Y => n16);
U20 : AOI22X1 port map( A => gregData_1_2_port, B => n5, C =>
gregData_0_2_port, D => n6, Y => n15);
U21 : NAND2X1 port map( A => n17, B => n18, Y => rData(1));
U22 : AOI22X1 port map( A => gregData_3_1_port, B => n3, C =>
gregData_2_1_port, D => n4_port, Y => n18);
U23 : AOI22X1 port map( A => gregData_1_1_port, B => n5, C =>
gregData_0_1_port, D => n6, Y => n17);
U24 : NAND2X1 port map( A => n19, B => n20, Y => rData(0));
U25 : AOI22X1 port map( A => gregData_3_0_port, B => n3, C =>
gregData_2_0_port, D => n4_port, Y => n20);
U26 : NOR2X1 port map( A => n21, B => rSel(0), Y => n4_port);
U27 : NOR2X1 port map( A => n21, B => n22, Y => n3);
U28 : AOI22X1 port map( A => gregData_1_0_port, B => n5, C =>
gregData_0_0_port, D => n6, Y => n19);
U29 : NOR2X1 port map( A => rSel(0), B => rSel(1), Y => n6);
U30 : NOR2X1 port map( A => n22, B => rSel(1), Y => n5);
U31 : INVX1 port map( A => rSel(0), Y => n22);
U32 : INVX1 port map( A => n23, Y => n67);
U33 : MUX2X1 port map( B => wData(7), A => gregData_0_7_port, S => n24, Y =>
n23);
U34 : INVX1 port map( A => n25, Y => n68);
U35 : MUX2X1 port map( B => wData(7), A => gregData_1_7_port, S => n26, Y =>
n25);
U36 : INVX1 port map( A => n27, Y => n69);
U37 : MUX2X1 port map( B => wData(7), A => gregData_2_7_port, S => n28, Y =>
n27);
U38 : INVX1 port map( A => n29, Y => n70);
U39 : MUX2X1 port map( B => wData(7), A => gregData_3_7_port, S => n30, Y =>
n29);
U40 : INVX1 port map( A => n31, Y => n71);
U41 : MUX2X1 port map( B => wData(6), A => gregData_0_6_port, S => n24, Y =>
n31);
U42 : INVX1 port map( A => n32, Y => n72);
U43 : MUX2X1 port map( B => wData(6), A => gregData_1_6_port, S => n26, Y =>
n32);
U44 : INVX1 port map( A => n33, Y => n73);
U45 : MUX2X1 port map( B => wData(6), A => gregData_2_6_port, S => n28, Y =>
n33);
U46 : INVX1 port map( A => n34, Y => n74);
U47 : MUX2X1 port map( B => wData(6), A => gregData_3_6_port, S => n30, Y =>
n34);
U48 : INVX1 port map( A => n35, Y => n75);
U49 : MUX2X1 port map( B => wData(5), A => gregData_0_5_port, S => n24, Y =>
n35);
U50 : INVX1 port map( A => n36, Y => n76);
U51 : MUX2X1 port map( B => wData(5), A => gregData_1_5_port, S => n26, Y =>
n36);
U52 : INVX1 port map( A => n37, Y => n78);
U53 : MUX2X1 port map( B => wData(5), A => gregData_2_5_port, S => n28, Y =>
n37);
U54 : INVX1 port map( A => n38, Y => n80);
U55 : MUX2X1 port map( B => wData(5), A => gregData_3_5_port, S => n30, Y =>
n38);
U56 : INVX1 port map( A => n39, Y => n82);
U57 : MUX2X1 port map( B => wData(4), A => gregData_0_4_port, S => n24, Y =>
n39);
U58 : INVX1 port map( A => n40, Y => n84);
U59 : MUX2X1 port map( B => wData(4), A => gregData_1_4_port, S => n26, Y =>
n40);
U60 : INVX1 port map( A => n41, Y => n86);
U61 : MUX2X1 port map( B => wData(4), A => gregData_2_4_port, S => n28, Y =>
n41);
U62 : INVX1 port map( A => n42, Y => n88);
U63 : MUX2X1 port map( B => wData(4), A => gregData_3_4_port, S => n30, Y =>
n42);
U64 : INVX1 port map( A => n43, Y => n90);
U65 : MUX2X1 port map( B => wData(3), A => gregData_0_3_port, S => n24, Y =>
n43);
U66 : INVX1 port map( A => n44, Y => n92);
U67 : MUX2X1 port map( B => wData(3), A => gregData_1_3_port, S => n26, Y =>
n44);
U68 : INVX1 port map( A => n45, Y => n94);
U69 : MUX2X1 port map( B => wData(3), A => gregData_2_3_port, S => n28, Y =>
n45);
U70 : INVX1 port map( A => n46, Y => n96);
U71 : MUX2X1 port map( B => wData(3), A => gregData_3_3_port, S => n30, Y =>
n46);
U72 : INVX1 port map( A => n47, Y => n98);
U73 : MUX2X1 port map( B => wData(2), A => gregData_0_2_port, S => n24, Y =>
n47);
U74 : INVX1 port map( A => n48, Y => n100);
U75 : MUX2X1 port map( B => wData(2), A => gregData_1_2_port, S => n26, Y =>
n48);
U76 : INVX1 port map( A => n49, Y => n102);
U77 : MUX2X1 port map( B => wData(2), A => gregData_2_2_port, S => n28, Y =>
n49);
U78 : INVX1 port map( A => n50, Y => n104);
U79 : MUX2X1 port map( B => wData(2), A => gregData_3_2_port, S => n30, Y =>
n50);
U80 : INVX1 port map( A => n51, Y => n106);
U81 : MUX2X1 port map( B => wData(1), A => gregData_0_1_port, S => n24, Y =>
n51);
U82 : INVX1 port map( A => n52, Y => n108);
U83 : MUX2X1 port map( B => wData(1), A => gregData_1_1_port, S => n26, Y =>
n52);
U84 : INVX1 port map( A => n53, Y => n110);
U85 : MUX2X1 port map( B => wData(1), A => gregData_2_1_port, S => n28, Y =>
n53);
U86 : INVX1 port map( A => n54, Y => n112);
U87 : MUX2X1 port map( B => wData(1), A => gregData_3_1_port, S => n30, Y =>
n54);
U88 : INVX1 port map( A => n55, Y => n114);
U89 : MUX2X1 port map( B => wData(0), A => gregData_0_0_port, S => n24, Y =>
n55);
U90 : NAND3X1 port map( A => n56, B => n57, C => n58, Y => n24);
U91 : INVX1 port map( A => n59, Y => n116);
U92 : MUX2X1 port map( B => wData(0), A => gregData_1_0_port, S => n26, Y =>
n59);
U93 : NAND3X1 port map( A => n58, B => n57, C => wSel(0), Y => n26);
U94 : INVX1 port map( A => wSel(1), Y => n57);
U95 : INVX1 port map( A => n60, Y => n118);
U96 : MUX2X1 port map( B => wData(0), A => gregData_2_0_port, S => n28, Y =>
n60);
U97 : NAND3X1 port map( A => n58, B => n56, C => wSel(1), Y => n28);
U98 : INVX1 port map( A => n61, Y => n120);
U99 : MUX2X1 port map( B => wData(0), A => gregData_3_0_port, S => n30, Y =>
n61);
U100 : NAND3X1 port map( A => wSel(0), B => n58, C => wSel(1), Y => n30);
U101 : NOR2X1 port map( A => n62, B => fifoFull_port, Y => n58);
U102 : INVX1 port map( A => wEnable, Y => n62);
U103 : NOR2X1 port map( A => n63, B => n64, Y => N7);
U104 : XNOR2X1 port map( A => n56, B => n65, Y => n64);
U105 : XNOR2X1 port map( A => rSel(0), B => wSel(0), Y => n63);
U106 : NOR2X1 port map( A => n65, B => n66, Y => N4);
U107 : XNOR2X1 port map( A => n56, B => rSel(0), Y => n66);
U108 : INVX1 port map( A => wSel(0), Y => n56);
U109 : XNOR2X1 port map( A => n21, B => wSel(1), Y => n65);
U110 : INVX1 port map( A => rSel(1), Y => n21);
end SYN_FifoRam_arch;
library IEEE,OSU_AMI05;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_sniffer_top.all;
entity sd_control is
port( clk, rst, sd_clock, fifo_empty : in std_logic; data_in : in
std_logic_vector (7 downto 0); data_out : out std_logic_vector (7
downto 0); clk_mode, tsr_load, sd_enable, clk_enable, data_read : out
std_logic);
end sd_control;
architecture SYN_sd_arch of sd_control is
component INVX1
port( A : in std_logic; Y : out std_logic);
end component;
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component NAND3X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component NAND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component NOR3X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component OAI21X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component OR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AOI21X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component AOI22X1
port( A, B, C, D : in std_logic; Y : out std_logic);
end component;
component MUX2X1
port( B, A, S : in std_logic; Y : out std_logic);
end component;
component AND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component OAI22X1
port( A, B, C, D : in std_logic; Y : out std_logic);
end component;
component INVX2
port( A : in std_logic; Y : out std_logic);
end component;
component HAX1
port( A, B : in std_logic; YC, YS : out std_logic);
end component;
component sd_control_DW01_inc_0
port( A : in std_logic_vector (6 downto 0); SUM : out std_logic_vector
(6 downto 0));
end component;
component DFFSR
port( D, CLK, R, S : in std_logic; Q : out std_logic);
end component;
signal clk_mode_port, sd_enable_port, sd_3_port, sd_2_port, sd_1_port,
sd_0_port, count1_6_port, count1_5_port, count1_4_port, count1_3_port,
count1_2_port, count1_1_port, count1_0_port, count2_4_port, count2_3_port
, count2_2_port, count2_1_port, count2_0_port, count3_2_port,
count3_1_port, count3_0_port, sd_clock1, sd_clock2, sdc, nextSd_3_port,
nextSd_2_port, nextSd_1_port, nextSd_0_port, nextCount2_4_port,
nextCount2_3_port, nextCount2_2_port, nextCount2_1_port,
nextCount2_0_port, N77, N588, N589, N590, n2, n3, n4, n5, n6, n7, n8, n63
, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76,
n77_port, n78, n79, n80, n81, n82, n83, n84, n313, n314, n315, n316, n317
, n318, n319, n320, n321, n322, r362_carry_2_port, r362_carry_3_port,
r362_carry_4_port, n1, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18,
n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33
, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47,
n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62
, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98,
n99, n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110,
n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122,
n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, n134,
n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, n145, n146,
n147, n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n158,
n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170,
n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182,
n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, n194,
n195, n196, n197, n198, n199, n200, n201, n202, n203, n204, n205, n206,
n207, n208, n209, n210, n211, n212, n213, n214, n215, n216 : std_logic;
begin
clk_mode <= clk_mode_port;
sd_enable <= sd_enable_port;
sd_clock1_reg : DFFSR port map( D => sd_clock, CLK => clk, R => rst, S =>
n84, Q => sd_clock1);
sd_clock2_reg : DFFSR port map( D => sd_clock1, CLK => clk, R => rst, S =>
n83, Q => sd_clock2);
sdc_reg : DFFSR port map( D => N77, CLK => clk, R => rst, S => n82, Q => sdc
);
sd_reg_0_inst : DFFSR port map( D => nextSd_0_port, CLK => clk, R => rst, S
=> n81, Q => sd_0_port);
sd_reg_2_inst : DFFSR port map( D => nextSd_2_port, CLK => clk, R => rst, S
=> n80, Q => sd_2_port);
sd_reg_1_inst : DFFSR port map( D => nextSd_1_port, CLK => clk, R => rst, S
=> n79, Q => sd_1_port);
sd_reg_3_inst : DFFSR port map( D => nextSd_3_port, CLK => clk, R => rst, S
=> n78, Q => sd_3_port);
count1_reg_3_inst : DFFSR port map( D => n318, CLK => clk, R => rst, S =>
n77_port, Q => count1_3_port);
count1_reg_6_inst : DFFSR port map( D => n322, CLK => clk, R => rst, S =>
n76, Q => count1_6_port);
count1_reg_0_inst : DFFSR port map( D => n315, CLK => clk, R => rst, S =>
n75, Q => count1_0_port);
count1_reg_1_inst : DFFSR port map( D => n316, CLK => clk, R => rst, S =>
n74, Q => count1_1_port);
count1_reg_2_inst : DFFSR port map( D => n317, CLK => clk, R => rst, S =>
n73, Q => count1_2_port);
count1_reg_4_inst : DFFSR port map( D => n319, CLK => clk, R => rst, S =>
n72, Q => count1_4_port);
count1_reg_5_inst : DFFSR port map( D => n320, CLK => clk, R => rst, S =>
n71, Q => count1_5_port);
count3_reg_0_inst : DFFSR port map( D => n313, CLK => clk, R => rst, S =>
n70, Q => count3_0_port);
count3_reg_1_inst : DFFSR port map( D => n314, CLK => clk, R => rst, S =>
n69, Q => count3_1_port);
count3_reg_2_inst : DFFSR port map( D => n321, CLK => clk, R => rst, S =>
n68, Q => count3_2_port);
count2_reg_0_inst : DFFSR port map( D => nextCount2_0_port, CLK => clk, R =>
rst, S => n67, Q => count2_0_port);
count2_reg_4_inst : DFFSR port map( D => nextCount2_4_port, CLK => clk, R =>
rst, S => n66, Q => count2_4_port);
count2_reg_3_inst : DFFSR port map( D => nextCount2_3_port, CLK => clk, R =>
rst, S => n65, Q => count2_3_port);
count2_reg_2_inst : DFFSR port map( D => nextCount2_2_port, CLK => clk, R =>
rst, S => n64, Q => count2_2_port);
count2_reg_1_inst : DFFSR port map( D => nextCount2_1_port, CLK => clk, R =>
rst, S => n63, Q => count2_1_port);
n63 <= '1';
n64 <= '1';
n65 <= '1';
n66 <= '1';
n67 <= '1';
n68 <= '1';
n69 <= '1';
n70 <= '1';
n71 <= '1';
n72 <= '1';
n73 <= '1';
n74 <= '1';
n75 <= '1';
n76 <= '1';
n77_port <= '1';
n78 <= '1';
n79 <= '1';
n80 <= '1';
n81 <= '1';
n82 <= '1';
n83 <= '1';
n84 <= '1';
r400 : sd_control_DW01_inc_0 port map( A(6) => count1_6_port, A(5) =>
count1_5_port, A(4) => count1_4_port, A(3) =>
count1_3_port, A(2) => count1_2_port, A(1) =>
count1_1_port, A(0) => count1_0_port, SUM(6) => n2,
SUM(5) => n3, SUM(4) => n4, SUM(3) => n5, SUM(2) =>
n6, SUM(1) => n7, SUM(0) => n8);
r362_U1_1_1 : HAX1 port map( A => count2_1_port, B => count2_0_port, YC =>
r362_carry_2_port, YS => N588);
r362_U1_1_2 : HAX1 port map( A => count2_2_port, B => r362_carry_2_port, YC
=> r362_carry_3_port, YS => N589);
r362_U1_1_3 : HAX1 port map( A => count2_3_port, B => r362_carry_3_port, YC
=> r362_carry_4_port, YS => N590);
U25 : AOI21X1 port map( A => n152, B => n52, C => n48, Y => n55);
U26 : AOI22X1 port map( A => n111, B => count2_4_port, C =>
r362_carry_4_port, D => n103, Y => n1);
U27 : INVX2 port map( A => n1, Y => nextCount2_4_port);
U28 : NAND3X1 port map( A => n9, B => n10, C => n11, Y => tsr_load);
U29 : AOI22X1 port map( A => n12, B => n13, C => n14, D => n15, Y => n11);
U30 : NAND3X1 port map( A => n16, B => n17, C => n18, Y => n15);
U31 : NOR2X1 port map( A => n19, B => n20, Y => n18);
U32 : OAI21X1 port map( A => n21, B => n22, C => n23, Y => n20);
U33 : NAND2X1 port map( A => count3_0_port, B => n24, Y => n22);
U34 : OR2X1 port map( A => n25, B => count3_1_port, Y => n21);
U35 : AOI22X1 port map( A => n26, B => n27, C => n28, D => n29, Y => n16);
U36 : OAI21X1 port map( A => n30, B => n31, C => n32, Y => n13);
U37 : OAI21X1 port map( A => n33, B => n31, C => n34, Y => nextSd_3_port);
U38 : AOI21X1 port map( A => n28, B => n35, C => clk_mode_port, Y => n34);
U39 : INVX1 port map( A => n36, Y => n33);
U40 : NAND3X1 port map( A => n37, B => n38, C => n39, Y => nextSd_2_port);
U41 : NOR2X1 port map( A => n40, B => n19, Y => n39);
U42 : NAND2X1 port map( A => n41, B => n42, Y => n19);
U43 : NAND3X1 port map( A => n43, B => n44, C => n45, Y => n40);
U44 : AOI21X1 port map( A => n46, B => n47, C => n48, Y => n38);
U45 : NOR2X1 port map( A => n49, B => n50, Y => n46);
U46 : INVX1 port map( A => n51, Y => n37);
U47 : OAI22X1 port map( A => n32, B => n52, C => n9, D => n53, Y => n51);
U48 : NAND3X1 port map( A => n54, B => n55, C => n56, Y => nextSd_1_port);
U49 : NOR2X1 port map( A => n57, B => n58, Y => n56);
U50 : OAI22X1 port map( A => n42, B => n59, C => n60, D => n61, Y => n58);
U51 : INVX1 port map( A => n62, Y => n61);
U52 : OAI22X1 port map( A => n17, B => n85, C => n86, D => n53, Y => n57);
U53 : NOR2X1 port map( A => n87, B => n88, Y => n54);
U54 : OR2X1 port map( A => n89, B => n90, Y => nextSd_0_port);
U55 : NAND3X1 port map( A => n91, B => n92, C => n93, Y => n90);
U56 : MUX2X1 port map( B => n94, A => n95, S => n85, Y => n93);
U57 : INVX1 port map( A => n49, Y => n85);
U58 : INVX1 port map( A => n87, Y => n92);
U59 : OAI21X1 port map( A => sdc, B => n9, C => n45, Y => n87);
U60 : INVX1 port map( A => n96, Y => n91);
U61 : MUX2X1 port map( B => n10, A => n97, S => n53, Y => n96);
U62 : NAND3X1 port map( A => n98, B => n60, C => n99, Y => n89);
U63 : AOI22X1 port map( A => n100, B => n59, C => n24, D => n101, Y => n99);
U64 : OAI21X1 port map( A => n102, B => n104, C => n105, Y =>
nextCount2_3_port);
U65 : NAND2X1 port map( A => N590, B => n103, Y => n105);
U66 : OAI21X1 port map( A => n102, B => n106, C => n107, Y =>
nextCount2_2_port);
U67 : NAND2X1 port map( A => N589, B => n103, Y => n107);
U68 : OAI21X1 port map( A => n102, B => n108, C => n109, Y =>
nextCount2_1_port);
U69 : NAND2X1 port map( A => N588, B => n103, Y => n109);
U70 : MUX2X1 port map( B => n110, A => n102, S => count2_0_port, Y =>
nextCount2_0_port);
U71 : INVX1 port map( A => n111, Y => n102);
U72 : OAI21X1 port map( A => n112, B => n113, C => n114, Y => n111);
U73 : INVX1 port map( A => n103, Y => n110);
U74 : OAI21X1 port map( A => n42, B => n115, C => n116, Y => n103);
U75 : NAND3X1 port map( A => n26, B => n27, C => n49, Y => n116);
U76 : OAI21X1 port map( A => n117, B => n118, C => n119, Y => n322);
U77 : NAND2X1 port map( A => n2, B => n120, Y => n119);
U78 : INVX1 port map( A => count1_6_port, Y => n118);
U79 : OAI21X1 port map( A => n121, B => n25, C => n122, Y => n321);
U80 : NAND3X1 port map( A => n123, B => count3_0_port, C => count3_1_port, Y
=> n122);
U81 : INVX1 port map( A => count3_2_port, Y => n25);
U82 : OAI21X1 port map( A => n117, B => n124, C => n125, Y => n320);
U83 : NAND2X1 port map( A => n3, B => n120, Y => n125);
U84 : INVX1 port map( A => count1_5_port, Y => n124);
U85 : OAI21X1 port map( A => n117, B => n126, C => n127, Y => n319);
U86 : NAND2X1 port map( A => n4, B => n120, Y => n127);
U87 : OAI21X1 port map( A => n117, B => n128, C => n129, Y => n318);
U88 : NAND2X1 port map( A => n5, B => n120, Y => n129);
U89 : OAI21X1 port map( A => n117, B => n130, C => n131, Y => n317);
U90 : NAND2X1 port map( A => n6, B => n120, Y => n131);
U91 : OAI21X1 port map( A => n117, B => n132, C => n133, Y => n316);
U92 : NAND2X1 port map( A => n7, B => n120, Y => n133);
U93 : OAI21X1 port map( A => n117, B => n134, C => n135, Y => n315);
U94 : NAND2X1 port map( A => n8, B => n120, Y => n135);
U95 : OAI21X1 port map( A => n62, B => n60, C => n136, Y => n120);
U96 : INVX1 port map( A => n137, Y => n136);
U97 : AOI21X1 port map( A => n44, B => n138, C => n112, Y => n137);
U98 : NOR2X1 port map( A => n139, B => n140, Y => n62);
U99 : NAND3X1 port map( A => count1_3_port, B => count1_2_port, C =>
count1_6_port, Y => n140);
U100 : NAND3X1 port map( A => count1_0_port, B => n132, C => n141, Y => n139
);
U101 : NOR2X1 port map( A => count1_5_port, B => count1_4_port, Y => n141);
U102 : INVX1 port map( A => count1_0_port, Y => n134);
U103 : AND2X1 port map( A => n142, B => n97, Y => n117);
U104 : NAND2X1 port map( A => n143, B => n144, Y => n97);
U105 : OAI21X1 port map( A => n145, B => n146, C => n112, Y => n142);
U106 : NAND3X1 port map( A => n147, B => n148, C => sdc, Y => n112);
U107 : NAND3X1 port map( A => count1_1_port, B => count1_0_port, C =>
count1_2_port, Y => n148);
U108 : OAI21X1 port map( A => n149, B => n49, C => n114, Y => n146);
U109 : AOI21X1 port map( A => n100, B => n150, C => n151, Y => n114);
U110 : AOI21X1 port map( A => n26, B => n49, C => n55, Y => n151);
U111 : NOR2X1 port map( A => n36, B => n31, Y => n48);
U112 : OAI21X1 port map( A => count3_1_port, B => n52, C => n101, Y => n36);
U113 : OR2X1 port map( A => n52, B => n30, Y => n101);
U114 : NAND2X1 port map( A => n152, B => n52, Y => n98);
U115 : NAND2X1 port map( A => sdc, B => n12, Y => n52);
U116 : INVX1 port map( A => n153, Y => n12);
U117 : NOR2X1 port map( A => n154, B => count2_0_port, Y => n26);
U118 : AND2X1 port map( A => n115, B => n59, Y => n150);
U119 : NAND3X1 port map( A => n155, B => n49, C => n156, Y => n59);
U120 : NOR2X1 port map( A => count2_3_port, B => count2_2_port, Y => n156);
U121 : NAND2X1 port map( A => sdc, B => n157, Y => n115);
U122 : NOR2X1 port map( A => n158, B => n159, Y => n149);
U123 : OAI21X1 port map( A => n160, B => n29, C => n161, Y => n145);
U124 : MUX2X1 port map( B => n162, A => n121, S => count3_1_port, Y => n314)
;
U125 : INVX1 port map( A => n163, Y => n121);
U126 : OAI21X1 port map( A => count3_0_port, B => n160, C => n164, Y => n163
);
U127 : NAND2X1 port map( A => n123, B => count3_0_port, Y => n162);
U128 : MUX2X1 port map( B => n45, A => n164, S => count3_0_port, Y => n313);
U129 : AOI21X1 port map( A => n35, B => n28, C => n24, Y => n164);
U130 : INVX1 port map( A => n160, Y => n28);
U131 : INVX1 port map( A => n123, Y => n45);
U132 : NOR2X1 port map( A => n35, B => n160, Y => n123);
U133 : NAND2X1 port map( A => n49, B => n29, Y => n35);
U134 : NOR2X1 port map( A => n53, B => n165, Y => n49);
U135 : INVX1 port map( A => sdc, Y => n53);
U136 : INVX1 port map( A => n10, Y => data_read);
U137 : NAND2X1 port map( A => n166, B => n167, Y => data_out(7));
U138 : AOI22X1 port map( A => n168, B => n165, C => data_in(7), D => n158, Y
=> n166);
U139 : NAND3X1 port map( A => n169, B => n170, C => n171, Y => data_out(6));
U140 : NOR2X1 port map( A => n172, B => n173, Y => n171);
U141 : OAI21X1 port map( A => n14, B => n43, C => n174, Y => n173);
U142 : NAND3X1 port map( A => n160, B => n9, C => n113, Y => n172);
U143 : AOI21X1 port map( A => data_in(6), B => n158, C => n27, Y => n170);
U144 : NOR2X1 port map( A => n175, B => n94, Y => n169);
U145 : NAND2X1 port map( A => n176, B => n41, Y => n94);
U146 : INVX1 port map( A => n88, Y => n176);
U147 : OAI21X1 port map( A => n177, B => n41, C => n23, Y => n88);
U148 : NAND2X1 port map( A => n178, B => n179, Y => data_out(5));
U149 : AOI21X1 port map( A => data_in(5), B => n158, C => n152, Y => n178);
U150 : NAND2X1 port map( A => n180, B => n181, Y => data_out(4));
U151 : AOI21X1 port map( A => data_in(4), B => n158, C => n182, Y => n180);
U152 : NAND2X1 port map( A => n183, B => n181, Y => data_out(3));
U153 : NOR3X1 port map( A => n159, B => n152, C => n184, Y => n181);
U154 : AOI21X1 port map( A => data_in(3), B => n158, C => n185, Y => n183);
U155 : INVX1 port map( A => n174, Y => n185);
U156 : NAND2X1 port map( A => n186, B => n167, Y => data_out(2));
U157 : INVX1 port map( A => n187, Y => n167);
U158 : NAND3X1 port map( A => n32, B => n188, C => n189, Y => n187);
U159 : AOI21X1 port map( A => data_in(2), B => n158, C => n168, Y => n186);
U160 : INVX1 port map( A => n43, Y => n168);
U161 : NAND2X1 port map( A => n190, B => n179, Y => data_out(1));
U162 : INVX1 port map( A => n191, Y => n179);
U163 : NAND3X1 port map( A => n174, B => n43, C => n189, Y => n191);
U164 : NOR2X1 port map( A => n184, B => n192, Y => n189);
U165 : OAI21X1 port map( A => n14, B => n113, C => n193, Y => n192);
U166 : NAND2X1 port map( A => n194, B => n195, Y => n184);
U167 : OAI21X1 port map( A => n30, B => n153, C => n24, Y => n195);
U168 : INVX1 port map( A => n31, Y => n24);
U169 : INVX1 port map( A => n29, Y => n30);
U170 : OAI21X1 port map( A => count3_1_port, B => count3_0_port, C =>
count3_2_port, Y => n29);
U171 : OAI21X1 port map( A => n196, B => n197, C => n182, Y => n174);
U172 : NAND2X1 port map( A => n155, B => n14, Y => n197);
U173 : NOR3X1 port map( A => count2_0_port, B => count2_4_port, C => n108, Y
=> n155);
U174 : NAND2X1 port map( A => n106, B => n104, Y => n196);
U175 : INVX1 port map( A => count2_3_port, Y => n104);
U176 : AOI22X1 port map( A => n152, B => n153, C => data_in(1), D => n158, Y
=> n190);
U177 : NAND3X1 port map( A => n198, B => n194, C => n199, Y => data_out(0));
U178 : AOI21X1 port map( A => n152, B => n153, C => n200, Y => n199);
U179 : NAND2X1 port map( A => n31, B => n188, Y => n200);
U180 : INVX1 port map( A => n182, Y => n188);
U181 : NOR2X1 port map( A => n42, B => n157, Y => n182);
U182 : NAND2X1 port map( A => count2_0_port, B => n157, Y => n153);
U183 : NOR2X1 port map( A => n154, B => n165, Y => n157);
U184 : NAND3X1 port map( A => n108, B => n106, C => n201, Y => n154);
U185 : NOR2X1 port map( A => count2_4_port, B => count2_3_port, Y => n201);
U186 : INVX1 port map( A => count2_2_port, Y => n106);
U187 : INVX1 port map( A => count2_1_port, Y => n108);
U188 : INVX1 port map( A => n32, Y => n152);
U189 : INVX1 port map( A => n175, Y => n194);
U190 : NAND2X1 port map( A => n161, B => n202, Y => n175);
U191 : OAI21X1 port map( A => fifo_empty, B => n165, C => n158, Y => n161);
U192 : AOI21X1 port map( A => data_in(0), B => n158, C => n159, Y => n198);
U193 : NAND3X1 port map( A => n32, B => n44, C => n203, Y => clk_mode_port);
U194 : NOR2X1 port map( A => n47, B => n95, Y => n203);
U195 : INVX1 port map( A => n23, Y => n47);
U196 : OR2X1 port map( A => n204, B => n205, Y => clk_enable);
U197 : OAI21X1 port map( A => n14, B => n44, C => n138, Y => n205);
U198 : NOR3X1 port map( A => n159, B => n100, C => n27, Y => n138);
U199 : NAND2X1 port map( A => n32, B => n31, Y => n27);
U200 : NAND3X1 port map( A => sd_1_port, B => sd_2_port, C => n144, Y => n31
);
U201 : NAND3X1 port map( A => sd_0_port, B => sd_3_port, C => n206, Y => n32
);
U202 : INVX1 port map( A => n42, Y => n100);
U203 : NAND3X1 port map( A => sd_2_port, B => n177, C => n144, Y => n42);
U204 : NAND2X1 port map( A => n193, B => n17, Y => n159);
U205 : INVX1 port map( A => n95, Y => n17);
U206 : NAND2X1 port map( A => n113, B => n43, Y => n95);
U207 : NAND3X1 port map( A => sd_0_port, B => sd_3_port, C => n207, Y => n43
);
U208 : NOR2X1 port map( A => sd_1_port, B => n50, Y => n207);
U209 : INVX1 port map( A => sd_2_port, Y => n50);
U210 : NAND3X1 port map( A => sd_0_port, B => sd_3_port, C => n143, Y =>
n113);
U211 : INVX1 port map( A => n208, Y => n193);
U212 : NAND3X1 port map( A => n41, B => n160, C => n23, Y => n208);
U213 : NAND3X1 port map( A => sd_3_port, B => n209, C => sd_1_port, Y => n23
);
U214 : NAND3X1 port map( A => sd_3_port, B => n209, C => n143, Y => n160);
U215 : NAND3X1 port map( A => n209, B => n210, C => sd_2_port, Y => n41);
U216 : NAND3X1 port map( A => n10, B => n202, C => n9, Y => n204);
U217 : NAND2X1 port map( A => n144, B => n206, Y => n9);
U218 : NOR2X1 port map( A => n209, B => sd_3_port, Y => n144);
U219 : INVX1 port map( A => sd_enable_port, Y => n202);
U220 : NAND2X1 port map( A => n86, B => n60, Y => sd_enable_port);
U221 : NAND3X1 port map( A => n209, B => n210, C => n206, Y => n60);
U222 : NOR2X1 port map( A => n177, B => sd_2_port, Y => n206);
U223 : INVX1 port map( A => sd_1_port, Y => n177);
U224 : INVX1 port map( A => sd_0_port, Y => n209);
U225 : NAND2X1 port map( A => n143, B => n210, Y => n86);
U226 : INVX1 port map( A => sd_3_port, Y => n210);
U227 : NOR2X1 port map( A => sd_1_port, B => sd_2_port, Y => n143);
U228 : NAND3X1 port map( A => n14, B => n211, C => n158, Y => n10);
U229 : INVX1 port map( A => n44, Y => n158);
U230 : NAND3X1 port map( A => sd_3_port, B => sd_2_port, C => n212, Y => n44
);
U231 : NOR2X1 port map( A => sd_1_port, B => sd_0_port, Y => n212);
U232 : INVX1 port map( A => fifo_empty, Y => n211);
U233 : INVX1 port map( A => n165, Y => n14);
U234 : NAND3X1 port map( A => count1_0_port, B => n147, C => n213, Y => n165
);
U235 : NOR2X1 port map( A => n132, B => n130, Y => n213);
U236 : INVX1 port map( A => count1_2_port, Y => n130);
U237 : INVX1 port map( A => count1_1_port, Y => n132);
U238 : INVX1 port map( A => n214, Y => n147);
U239 : NAND3X1 port map( A => n128, B => n126, C => n215, Y => n214);
U240 : NOR2X1 port map( A => count1_6_port, B => count1_5_port, Y => n215);
U241 : INVX1 port map( A => count1_4_port, Y => n126);
U242 : INVX1 port map( A => count1_3_port, Y => n128);
U243 : NOR2X1 port map( A => sd_clock2, B => n216, Y => N77);
U244 : INVX1 port map( A => sd_clock1, Y => n216);
end SYN_sd_arch;
library IEEE,OSU_AMI05;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_sniffer_top.all;
entity interceptor is
port( clk, eop, intercept : in std_logic; inst : in std_logic_vector (3
downto 0); rst, usbclk : in std_logic; dataPlus, dataMinus : out
std_logic; computerMinus, computerPlus, usbMinus, usbPlus : inout
std_logic);
end interceptor;
architecture SYN_struct of interceptor is
component INVX1
port( A : in std_logic; Y : out std_logic);
end component;
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component MUX2X1
port( B, A, S : in std_logic; Y : out std_logic);
end component;
component usbInterceptor
port( usbClk, rst, intercept, usbDataPlus, usbDataMinus, usbLock, clk,
eop : in std_logic; usbDataPlusOutput, usbDataMinusOutput : out
std_logic);
end component;
component tristate_0
port( lock, interceptorOutput : in std_logic; interceptorInput : out
std_logic; dataLine : inout std_logic);
end component;
component tristate_1
port( lock, interceptorOutput : in std_logic; interceptorInput : out
std_logic; dataLine : inout std_logic);
end component;
component tristate_2
port( lock, interceptorOutput : in std_logic; interceptorInput : out
std_logic; dataLine : inout std_logic);
end component;
component tristate_3
port( lock, interceptorOutput : in std_logic; interceptorInput : out
std_logic; dataLine : inout std_logic);
end component;
component lockingDetector
port( endOfPacket, rst, clk : in std_logic; inst : in std_logic_vector
(3 downto 0); usbLock, computerLock : out std_logic);
end component;
component computerInterceptor
port( usbClk, rst, computerDataPlus, computerDataMinus, computerLock, clk
, eop : in std_logic; computerDataPlusOutput,
computerDataMinusOutput : out std_logic);
end component;
signal computerDataMinus, computerDataPlus, computerLock,
computerDataMinusOutput, computerDataPlusOutput, usbLock, usbDataMinus,
usbDataPlusOutput, usbDataPlus, usbDataMinusOutput, n1, n2, n3, n4, n5 :
std_logic;
begin
U_0 : computerInterceptor port map( usbClk => usbclk, rst => rst,
computerDataPlus => computerDataPlus,
computerDataMinus => computerDataMinus, computerLock
=> computerLock, clk => clk, eop => eop,
computerDataPlusOutput => computerDataPlusOutput,
computerDataMinusOutput => computerDataMinusOutput);
U_1 : lockingDetector port map( endOfPacket => eop, rst => rst, clk => clk,
inst(3) => inst(3), inst(2) => inst(2), inst(1) =>
inst(1), inst(0) => inst(0), usbLock => usbLock,
computerLock => computerLock);
U_2 : tristate_3 port map( lock => computerLock, interceptorOutput =>
computerDataMinusOutput, interceptorInput =>
usbDataMinus, dataLine => usbMinus);
U_3 : tristate_2 port map( lock => usbLock, interceptorOutput =>
usbDataPlusOutput, interceptorInput =>
computerDataPlus, dataLine => computerPlus);
U_5 : tristate_1 port map( lock => computerLock, interceptorOutput =>
computerDataPlusOutput, interceptorInput =>
usbDataPlus, dataLine => usbPlus);
U_6 : tristate_0 port map( lock => usbLock, interceptorOutput =>
usbDataMinusOutput, interceptorInput =>
computerDataMinus, dataLine => computerMinus);
U_4 : usbInterceptor port map( usbClk => usbclk, rst => rst, intercept =>
intercept, usbDataPlus => usbDataPlus, usbDataMinus
=> usbDataMinus, usbLock => usbLock, clk => clk, eop
=> eop, usbDataPlusOutput => usbDataPlusOutput,
usbDataMinusOutput => usbDataMinusOutput);
U2 : MUX2X1 port map( B => n1, A => n2, S => usbLock, Y => dataPlus);
U3 : INVX1 port map( A => usbPlus, Y => n2);
U4 : NOR2X1 port map( A => computerPlus, B => n3, Y => n1);
U5 : MUX2X1 port map( B => n4, A => n5, S => usbLock, Y => dataMinus);
U6 : INVX1 port map( A => usbMinus, Y => n5);
U7 : NOR2X1 port map( A => computerMinus, B => n3, Y => n4);
U8 : INVX1 port map( A => computerLock, Y => n3);
end SYN_struct;
library IEEE,OSU_AMI05;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_sniffer_top.all;
entity decoder is
port( clk, rst, data0, data1, halt : in std_logic; data : out
std_logic_vector (1 downto 0); inst : out std_logic_vector (3 downto
0); data_out : out std_logic_vector (7 downto 0); dclk, eopOut : out
std_logic);
end decoder;
architecture SYN_BLK of decoder is
component INVX1
port( A : in std_logic; Y : out std_logic);
end component;
component NAND3X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component XOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component XNOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component OR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component OAI21X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component NAND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component timer
port( clk, rst, egde_det, f_egde_det, EOP : in std_logic; data_clk,
shift_en : out std_logic);
end component;
component shift_greg
port( clk, rst, shift_en, data_in : in std_logic; data_out : out
std_logic_vector (7 downto 0); data_ready : out std_logic);
end component;
component NRZIdecode
port( clk, rst, data0, enable, EOP : in std_logic; data_out : out
std_logic);
end component;
component SEE_det
port( clk, rst, data0, data1 : in std_logic; EGDE, F_EGDE, EOP : out
std_logic);
end component;
component DFFSR
port( D, CLK, R, S : in std_logic; Q : out std_logic);
end component;
signal data_out_7_port, data_out_6_port, data_out_5_port, data_out_4_port,
data_out_3_port, data_out_2_port, data_out_1_port, data_out_0_port,
eopOut_port, CS_3_port, CS_2_port, CS_1_port, CS_0_port, data_ready_0,
data_ready_1, nxt_data_1_port, nxt_inst_3_port, nxt_inst_2_port,
nxt_inst_1_port, nxt_inst_0_port, data_ready, egde, fegde, shift_enable,
act_data, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n67, n68,
n69, n70, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25
, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39,
n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54
, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66 : std_logic;
begin
data_out <= ( data_out_7_port, data_out_6_port, data_out_5_port,
data_out_4_port, data_out_3_port, data_out_2_port, data_out_1_port,
data_out_0_port );
eopOut <= eopOut_port;
data_ready_0_reg : DFFSR port map( D => data_ready, CLK => clk, R => rst, S
=> n12, Q => data_ready_0);
data_ready_1_reg : DFFSR port map( D => data_ready_0, CLK => clk, R => rst,
S => n11, Q => data_ready_1);
CS_reg_0_inst : DFFSR port map( D => n69, CLK => clk, R => rst, S => n10, Q
=> CS_0_port);
CS_reg_1_inst : DFFSR port map( D => n67, CLK => clk, R => rst, S => n9, Q
=> CS_1_port);
CS_reg_2_inst : DFFSR port map( D => n68, CLK => clk, R => rst, S => n8, Q
=> CS_2_port);
CS_reg_3_inst : DFFSR port map( D => n70, CLK => clk, R => rst, S => n7, Q
=> CS_3_port);
cur_data_reg_1_inst : DFFSR port map( D => nxt_data_1_port, CLK => clk, R =>
rst, S => n6, Q => data(1));
cur_data_reg_0_inst : DFFSR port map( D => n66, CLK => clk, R => rst, S =>
n5, Q => data(0));
cur_inst_reg_3_inst : DFFSR port map( D => nxt_inst_3_port, CLK => clk, R =>
rst, S => n4, Q => inst(3));
cur_inst_reg_2_inst : DFFSR port map( D => nxt_inst_2_port, CLK => clk, R =>
rst, S => n3, Q => inst(2));
cur_inst_reg_1_inst : DFFSR port map( D => nxt_inst_1_port, CLK => clk, R =>
rst, S => n2, Q => inst(1));
cur_inst_reg_0_inst : DFFSR port map( D => nxt_inst_0_port, CLK => clk, R =>
rst, S => n1, Q => inst(0));
n1 <= '1';
n2 <= '1';
n3 <= '1';
n4 <= '1';
n5 <= '1';
n6 <= '1';
n7 <= '1';
n8 <= '1';
n9 <= '1';
n10 <= '1';
n11 <= '1';
n12 <= '1';
part2 : SEE_det port map( clk => clk, rst => rst, data0 => data0, data1 =>
data1, EGDE => egde, F_EGDE => fegde, EOP =>
eopOut_port);
part3 : NRZIdecode port map( clk => clk, rst => rst, data0 => data0, enable
=> shift_enable, EOP => eopOut_port, data_out =>
act_data);
part4 : shift_greg port map( clk => clk, rst => rst, shift_en =>
shift_enable, data_in => act_data, data_out(7) =>
data_out_7_port, data_out(6) => data_out_6_port,
data_out(5) => data_out_5_port, data_out(4) =>
data_out_4_port, data_out(3) => data_out_3_port,
data_out(2) => data_out_2_port, data_out(1) =>
data_out_1_port, data_out(0) => data_out_0_port,
data_ready => data_ready);
part5 : timer port map( clk => clk, rst => rst, egde_det => egde, f_egde_det
=> fegde, EOP => eopOut_port, data_clk => dclk,
shift_en => shift_enable);
U15 : NOR2X1 port map( A => n13, B => n14, Y => nxt_inst_3_port);
U16 : AND2X1 port map( A => n15, B => data_out_5_port, Y => nxt_inst_2_port)
;
U17 : NOR2X1 port map( A => n13, B => n16, Y => nxt_inst_0_port);
U18 : INVX1 port map( A => n17, Y => n66);
U19 : OAI21X1 port map( A => n18, B => n19, C => n20, Y => n69);
U20 : NAND3X1 port map( A => n21, B => n22, C => data_ready_0, Y => n20);
U21 : OAI21X1 port map( A => CS_2_port, B => n23, C => n19, Y => n21);
U22 : INVX1 port map( A => n24, Y => n19);
U23 : OAI21X1 port map( A => n25, B => n26, C => n27, Y => n24);
U24 : NOR2X1 port map( A => n70, B => n18, Y => n27);
U25 : AND2X1 port map( A => n28, B => n29, Y => n70);
U26 : OAI21X1 port map( A => n30, B => n31, C => n32, Y => n28);
U27 : NAND3X1 port map( A => CS_3_port, B => CS_0_port, C => n33, Y => n32);
U28 : NOR2X1 port map( A => CS_2_port, B => CS_1_port, Y => n33);
U29 : OAI21X1 port map( A => n34, B => n35, C => data_ready_0, Y => n26);
U30 : NAND2X1 port map( A => n22, B => n29, Y => n25);
U31 : INVX1 port map( A => data_ready_1, Y => n22);
U32 : OR2X1 port map( A => n36, B => n37, Y => n68);
U33 : OAI21X1 port map( A => n38, B => n39, C => n40, Y => n37);
U34 : NAND3X1 port map( A => n15, B => n41, C => n42, Y => n40);
U35 : NOR2X1 port map( A => n43, B => n44, Y => n42);
U36 : INVX1 port map( A => data_out_2_port, Y => n44);
U37 : OAI21X1 port map( A => n45, B => n34, C => n29, Y => n39);
U38 : INVX1 port map( A => n23, Y => n34);
U39 : NAND3X1 port map( A => n46, B => n47, C => n48, Y => n23);
U40 : INVX1 port map( A => n49, Y => n45);
U41 : OR2X1 port map( A => n36, B => n50, Y => n67);
U42 : OAI21X1 port map( A => n51, B => n52, C => n53, Y => n50);
U43 : INVX1 port map( A => n18, Y => n53);
U44 : NOR2X1 port map( A => n54, B => CS_0_port, Y => n18);
U45 : NAND3X1 port map( A => n55, B => n38, C => n56, Y => n52);
U46 : NOR2X1 port map( A => n16, B => n49, Y => n56);
U47 : NAND3X1 port map( A => n46, B => n47, C => CS_0_port, Y => n49);
U48 : INVX1 port map( A => CS_1_port, Y => n46);
U49 : INVX1 port map( A => data_out_7_port, Y => n16);
U50 : NOR2X1 port map( A => data_out_1_port, B => data_out_0_port, Y => n55)
;
U51 : NAND3X1 port map( A => n57, B => n14, C => n58, Y => n51);
U52 : NOR2X1 port map( A => data_out_3_port, B => data_out_2_port, Y => n58)
;
U53 : INVX1 port map( A => data_out_4_port, Y => n14);
U54 : NOR2X1 port map( A => data_out_6_port, B => data_out_5_port, Y => n57)
;
U55 : OAI21X1 port map( A => n59, B => n60, C => n61, Y => n36);
U56 : NAND3X1 port map( A => n29, B => n31, C => n62, Y => n61);
U57 : INVX1 port map( A => n30, Y => n62);
U58 : NOR2X1 port map( A => nxt_data_1_port, B => n35, Y => n30);
U59 : NOR2X1 port map( A => n17, B => CS_0_port, Y => n35);
U60 : NOR2X1 port map( A => n17, B => n48, Y => nxt_data_1_port);
U61 : NAND3X1 port map( A => CS_1_port, B => n47, C => CS_2_port, Y => n17);
U62 : INVX1 port map( A => halt, Y => n31);
U63 : INVX1 port map( A => eopOut_port, Y => n29);
U64 : OR2X1 port map( A => n43, B => data_out_2_port, Y => n60);
U65 : NAND3X1 port map( A => data_out_7_port, B => n63, C => n64, Y => n43);
U66 : NOR2X1 port map( A => data_out_3_port, B => n65, Y => n64);
U67 : XNOR2X1 port map( A => data_out_0_port, B => data_out_4_port, Y => n65
);
U68 : XOR2X1 port map( A => data_out_5_port, B => data_out_1_port, Y => n63)
;
U69 : INVX1 port map( A => nxt_inst_1_port, Y => n59);
U70 : NOR2X1 port map( A => n41, B => n13, Y => nxt_inst_1_port);
U71 : INVX1 port map( A => n15, Y => n13);
U72 : NOR2X1 port map( A => n48, B => n54, Y => n15);
U73 : NAND3X1 port map( A => n38, B => n47, C => CS_1_port, Y => n54);
U74 : INVX1 port map( A => CS_3_port, Y => n47);
U75 : INVX1 port map( A => CS_2_port, Y => n38);
U76 : INVX1 port map( A => CS_0_port, Y => n48);
U77 : INVX1 port map( A => data_out_6_port, Y => n41);
end SYN_BLK;
library IEEE,OSU_AMI05;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_sniffer_top.all;
entity controller is
port( clk, rst, fifo_full : in std_logic; decoder_instruction : in
std_logic_vector (3 downto 0); data_ready : in std_logic_vector (1
downto 0); eop_found, data_read : in std_logic; fifo_read,
fifo_write, intercept : out std_logic);
end controller;
architecture SYN_controller_arch of controller is
component INVX1
port( A : in std_logic; Y : out std_logic);
end component;
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component NAND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component NAND3X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component OAI21X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component MUX2X1
port( B, A, S : in std_logic; Y : out std_logic);
end component;
component AOI21X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component AND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component OAI22X1
port( A, B, C, D : in std_logic; Y : out std_logic);
end component;
component AOI22X1
port( A, B, C, D : in std_logic; Y : out std_logic);
end component;
component OR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component DFFSR
port( D, CLK, R, S : in std_logic; Q : out std_logic);
end component;
component DFFPOSX1
port( D, CLK : in std_logic; Q : out std_logic);
end component;
signal usb_3_port, usb_2_port, usb_1_port, usb_0_port, sd, eopCount_2_port,
eopCount_1_port, eopCount_0_port, writeCount_2_port, writeCount_1_port,
writeCount_0_port, eop1, eop2, dr1, dr2, dr, nextUsb_3_port,
nextUsb_2_port, nextUsb_1_port, nextUsb_0_port, nextSd, eopf, N26, n80,
n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95
, n96, n97, n100, n101, n102, n103, n104, n1, n2, n3, n4, n5, n6, n7, n8,
n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23,
n24, n25, n26_port, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37
, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51,
n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66
, n67, n68, n69, n70, n71, n72, n73, fifo_write_port : std_logic;
begin
fifo_read <= sd;
fifo_write <= fifo_write_port;
eop1_reg : DFFSR port map( D => eop_found, CLK => clk, R => rst, S => n96, Q
=> eop1);
eop2_reg : DFFSR port map( D => eop1, CLK => clk, R => rst, S => n95, Q =>
eop2);
eopf_reg : DFFPOSX1 port map( D => n94, CLK => clk, Q => eopf);
eopCount_reg_0_inst : DFFSR port map( D => n102, CLK => clk, R => rst, S =>
n93, Q => eopCount_0_port);
eopCount_reg_1_inst : DFFSR port map( D => n103, CLK => clk, R => rst, S =>
n92, Q => eopCount_1_port);
eopCount_reg_2_inst : DFFSR port map( D => n104, CLK => clk, R => rst, S =>
n91, Q => eopCount_2_port);
usb_reg_2_inst : DFFSR port map( D => nextUsb_2_port, CLK => clk, R => rst,
S => n90, Q => usb_2_port);
writeCount_reg_2_inst : DFFSR port map( D => n100, CLK => clk, R => rst, S
=> n89, Q => writeCount_2_port);
usb_reg_3_inst : DFFSR port map( D => nextUsb_3_port, CLK => clk, R => rst,
S => n88, Q => usb_3_port);
usb_reg_1_inst : DFFSR port map( D => nextUsb_1_port, CLK => clk, R => rst,
S => n87, Q => usb_1_port);
usb_reg_0_inst : DFFSR port map( D => nextUsb_0_port, CLK => clk, R => rst,
S => n86, Q => usb_0_port);
writeCount_reg_0_inst : DFFSR port map( D => n101, CLK => clk, R => rst, S
=> n85, Q => writeCount_0_port);
writeCount_reg_1_inst : DFFSR port map( D => n97, CLK => clk, R => rst, S =>
n84, Q => writeCount_1_port);
dr1_reg : DFFSR port map( D => data_read, CLK => clk, R => rst, S => n83, Q
=> dr1);
dr2_reg : DFFSR port map( D => dr1, CLK => clk, R => rst, S => n82, Q => dr2
);
dr_reg : DFFSR port map( D => N26, CLK => clk, R => rst, S => n81, Q => dr);
sd_reg : DFFSR port map( D => nextSd, CLK => clk, R => rst, S => n80, Q =>
sd);
n80 <= '1';
n81 <= '1';
n82 <= '1';
n83 <= '1';
n84 <= '1';
n85 <= '1';
n86 <= '1';
n87 <= '1';
n88 <= '1';
n89 <= '1';
n90 <= '1';
n91 <= '1';
n92 <= '1';
n93 <= '1';
n95 <= '1';
n96 <= '1';
U3 : AND2X1 port map( A => n1, B => fifo_write_port, Y => nextUsb_3_port);
U4 : NAND3X1 port map( A => n2, B => n3, C => n4, Y => nextUsb_2_port);
U5 : NOR2X1 port map( A => n5, B => n6, Y => n4);
U6 : AND2X1 port map( A => n7, B => n8, Y => n2);
U7 : NAND3X1 port map( A => n9, B => n8, C => n10, Y => nextUsb_1_port);
U8 : INVX1 port map( A => n11, Y => n10);
U9 : OAI22X1 port map( A => n12, B => n13, C => n14, D => n15, Y => n11);
U10 : NAND3X1 port map( A => n16, B => n17, C => data_ready(0), Y => n9);
U11 : INVX1 port map( A => data_ready(1), Y => n17);
U12 : INVX1 port map( A => n3, Y => n16);
U13 : OR2X1 port map( A => n18, B => n19, Y => nextUsb_0_port);
U14 : OAI21X1 port map( A => data_ready(0), B => n3, C => n20, Y => n19);
U15 : INVX1 port map( A => n6, Y => n20);
U16 : OAI21X1 port map( A => n21, B => n1, C => n22, Y => n6);
U17 : NAND3X1 port map( A => decoder_instruction(1), B =>
decoder_instruction(0), C => n23, Y => n22);
U18 : NOR2X1 port map( A => n12, B => n24, Y => n23);
U19 : OAI21X1 port map( A => n25, B => n26_port, C => n13, Y => n24);
U20 : INVX1 port map( A => decoder_instruction(2), Y => n25);
U21 : OAI21X1 port map( A => n27, B => n28, C => n29, Y => n1);
U22 : NOR2X1 port map( A => fifo_full, B => eop_found, Y => n29);
U23 : NAND2X1 port map( A => writeCount_1_port, B => writeCount_0_port, Y =>
n28);
U24 : INVX1 port map( A => writeCount_2_port, Y => n27);
U25 : OAI21X1 port map( A => n30, B => n14, C => n31, Y => n18);
U26 : AOI22X1 port map( A => n32, B => n33, C => data_ready(1), D => n34, Y
=> n31);
U27 : OAI21X1 port map( A => n35, B => n8, C => n3, Y => n34);
U28 : INVX1 port map( A => data_ready(0), Y => n35);
U29 : NOR2X1 port map( A => n26_port, B => n12, Y => n33);
U30 : NAND3X1 port map( A => n36, B => n37, C => n38, Y => n12);
U31 : INVX1 port map( A => decoder_instruction(3), Y => n26_port);
U32 : NOR2X1 port map( A => n39, B => n40, Y => n32);
U33 : MUX2X1 port map( B => decoder_instruction(1), A => n41, S =>
decoder_instruction(2), Y => n40);
U34 : NOR2X1 port map( A => usb_1_port, B => decoder_instruction(1), Y =>
n41);
U35 : INVX1 port map( A => decoder_instruction(0), Y => n39);
U36 : NAND3X1 port map( A => n36, B => n37, C => n42, Y => n14);
U37 : NOR2X1 port map( A => usb_1_port, B => n38, Y => n42);
U38 : INVX1 port map( A => n15, Y => n30);
U39 : NAND3X1 port map( A => decoder_instruction(0), B =>
decoder_instruction(3), C => n43, Y => n15);
U40 : NOR2X1 port map( A => decoder_instruction(2), B =>
decoder_instruction(1), Y => n43);
U41 : NOR2X1 port map( A => sd, B => n44, Y => nextSd);
U42 : INVX1 port map( A => dr, Y => n44);
U43 : INVX1 port map( A => n7, Y => intercept);
U44 : NAND3X1 port map( A => usb_1_port, B => usb_0_port, C => n45, Y => n7)
;
U45 : NOR2X1 port map( A => usb_3_port, B => usb_2_port, Y => n45);
U46 : MUX2X1 port map( B => n46, A => n47, S => writeCount_1_port, Y => n97)
;
U47 : NAND2X1 port map( A => fifo_write_port, B => writeCount_0_port, Y =>
n46);
U48 : MUX2X1 port map( B => n48, A => n49, S => rst, Y => n94);
U49 : NAND2X1 port map( A => eop1, B => n50, Y => n49);
U50 : INVX1 port map( A => eop2, Y => n50);
U51 : OAI22X1 port map( A => n51, B => n52, C => n53, D => n54, Y => n104);
U52 : INVX1 port map( A => eopCount_2_port, Y => n54);
U53 : MUX2X1 port map( B => n52, A => n53, S => eopCount_1_port, Y => n103);
U54 : INVX1 port map( A => n55, Y => n53);
U55 : OAI21X1 port map( A => eopCount_0_port, B => n56, C => n57, Y => n55);
U56 : NAND3X1 port map( A => n5, B => eopCount_0_port, C => n58, Y => n52);
U57 : MUX2X1 port map( B => n59, A => n57, S => eopCount_0_port, Y => n102);
U58 : INVX1 port map( A => n60, Y => n57);
U59 : OAI21X1 port map( A => n58, B => n56, C => n61, Y => n60);
U60 : NAND2X1 port map( A => n58, B => n5, Y => n59);
U61 : INVX1 port map( A => n56, Y => n5);
U62 : NAND3X1 port map( A => n38, B => n13, C => n62, Y => n56);
U63 : AOI21X1 port map( A => n63, B => eopCount_2_port, C => n64, Y => n62);
U64 : AND2X1 port map( A => n51, B => eopCount_0_port, Y => n63);
U65 : INVX1 port map( A => eopCount_1_port, Y => n51);
U66 : AOI21X1 port map( A => eopCount_2_port, B => eopCount_1_port, C => n48
, Y => n58);
U67 : INVX1 port map( A => eopf, Y => n48);
U68 : MUX2X1 port map( B => n21, A => n65, S => writeCount_0_port, Y => n101
);
U69 : MUX2X1 port map( B => n66, A => n67, S => writeCount_2_port, Y => n100
);
U70 : INVX1 port map( A => n68, Y => n67);
U71 : OAI21X1 port map( A => n21, B => writeCount_1_port, C => n47, Y => n68
);
U72 : INVX1 port map( A => n69, Y => n47);
U73 : OAI21X1 port map( A => writeCount_0_port, B => n21, C => n65, Y => n69
);
U74 : INVX1 port map( A => n70, Y => n65);
U75 : NAND3X1 port map( A => n3, B => n8, C => n61, Y => n70);
U76 : OAI21X1 port map( A => usb_0_port, B => n71, C => usb_3_port, Y => n61
);
U77 : NAND2X1 port map( A => n13, B => n36, Y => n71);
U78 : INVX1 port map( A => usb_2_port, Y => n36);
U79 : NAND3X1 port map( A => n72, B => n38, C => usb_1_port, Y => n8);
U80 : INVX1 port map( A => usb_0_port, Y => n38);
U81 : NAND3X1 port map( A => n72, B => n13, C => usb_0_port, Y => n3);
U82 : INVX1 port map( A => usb_1_port, Y => n13);
U83 : NAND3X1 port map( A => writeCount_1_port, B => writeCount_0_port, C =>
fifo_write_port, Y => n66);
U84 : INVX1 port map( A => n21, Y => fifo_write_port);
U85 : NAND3X1 port map( A => usb_0_port, B => n72, C => usb_1_port, Y => n21
);
U86 : INVX1 port map( A => n64, Y => n72);
U87 : NAND2X1 port map( A => usb_2_port, B => n37, Y => n64);
U88 : INVX1 port map( A => usb_3_port, Y => n37);
U89 : NOR2X1 port map( A => dr2, B => n73, Y => N26);
U90 : INVX1 port map( A => dr1, Y => n73);
end SYN_controller_arch;
library IEEE,OSU_AMI05;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_sniffer_top.all;
entity SpiXmitSR_srWidth8 is
port( clk, resetN, tsrEnable, tsrLoad : in std_logic; tsrData : in
std_logic_vector (7 downto 0); dataOut : out std_logic);
end SpiXmitSR_srWidth8;
architecture SYN_SpiXmitSR_arch of SpiXmitSR_srWidth8 is
component INVX1
port( A : in std_logic; Y : out std_logic);
end component;
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AOI22X1
port( A, B, C, D : in std_logic; Y : out std_logic);
end component;
component OAI21X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component MUX2X1
port( B, A, S : in std_logic; Y : out std_logic);
end component;
component DFFSR
port( D, CLK, R, S : in std_logic; Q : out std_logic);
end component;
signal dataOut_port, tsrDataReg_6_port, tsrDataReg_5_port, tsrDataReg_4_port
, tsrDataReg_3_port, tsrDataReg_2_port, tsrDataReg_1_port,
tsrDataReg_0_port, tsrDummyReg_0_port, load2, load1, load, N2, n23, n24,
n25, n26, n27, n28, n29, n30, n31, n33, n34, n35, n36, n37, n38, n39, n40
, n41, n42, n43, n1, n2_port, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12,
n13, n14, n15, n16, n17, n18, n19, n20, n21, n22 : std_logic;
begin
dataOut <= dataOut_port;
load1_reg : DFFSR port map( D => tsrLoad, CLK => clk, R => resetN, S => n35,
Q => load1);
load2_reg : DFFSR port map( D => load1, CLK => clk, R => resetN, S => n34, Q
=> load2);
load_reg : DFFSR port map( D => N2, CLK => clk, R => resetN, S => n33, Q =>
load);
tsrDummyReg_reg_0_inst : DFFSR port map( D => n22, CLK => clk, R => n31, S
=> resetN, Q => tsrDummyReg_0_port);
tsrDataReg_reg_0_inst : DFFSR port map( D => n43, CLK => clk, R => n30, S =>
resetN, Q => tsrDataReg_0_port);
tsrDataReg_reg_1_inst : DFFSR port map( D => n42, CLK => clk, R => n29, S =>
resetN, Q => tsrDataReg_1_port);
tsrDataReg_reg_2_inst : DFFSR port map( D => n41, CLK => clk, R => n28, S =>
resetN, Q => tsrDataReg_2_port);
tsrDataReg_reg_3_inst : DFFSR port map( D => n40, CLK => clk, R => n27, S =>
resetN, Q => tsrDataReg_3_port);
tsrDataReg_reg_4_inst : DFFSR port map( D => n39, CLK => clk, R => n26, S =>
resetN, Q => tsrDataReg_4_port);
tsrDataReg_reg_5_inst : DFFSR port map( D => n38, CLK => clk, R => n25, S =>
resetN, Q => tsrDataReg_5_port);
tsrDataReg_reg_6_inst : DFFSR port map( D => n37, CLK => clk, R => n24, S =>
resetN, Q => tsrDataReg_6_port);
tsrDataReg_reg_7_inst : DFFSR port map( D => n36, CLK => clk, R => n23, S =>
resetN, Q => dataOut_port);
n23 <= '1';
n24 <= '1';
n25 <= '1';
n26 <= '1';
n27 <= '1';
n28 <= '1';
n29 <= '1';
n30 <= '1';
n31 <= '1';
n33 <= '1';
n34 <= '1';
n35 <= '1';
U3 : INVX1 port map( A => n1, Y => n22);
U4 : MUX2X1 port map( B => tsrDummyReg_0_port, A => tsrData(0), S => load, Y
=> n1);
U5 : OAI21X1 port map( A => n2_port, B => n3, C => n4, Y => n43);
U6 : AOI22X1 port map( A => n5, B => tsrData(0), C => tsrDataReg_0_port, D
=> n6, Y => n4);
U7 : INVX1 port map( A => tsrDummyReg_0_port, Y => n2_port);
U8 : OAI21X1 port map( A => n7, B => n3, C => n8, Y => n42);
U9 : AOI22X1 port map( A => tsrData(1), B => n5, C => tsrDataReg_1_port, D
=> n6, Y => n8);
U10 : INVX1 port map( A => tsrDataReg_0_port, Y => n7);
U11 : OAI21X1 port map( A => n3, B => n9, C => n10, Y => n41);
U12 : AOI22X1 port map( A => tsrData(2), B => n5, C => tsrDataReg_2_port, D
=> n6, Y => n10);
U13 : INVX1 port map( A => tsrDataReg_1_port, Y => n9);
U14 : OAI21X1 port map( A => n3, B => n11, C => n12, Y => n40);
U15 : AOI22X1 port map( A => tsrData(3), B => n5, C => tsrDataReg_3_port, D
=> n6, Y => n12);
U16 : INVX1 port map( A => tsrDataReg_2_port, Y => n11);
U17 : OAI21X1 port map( A => n3, B => n13, C => n14, Y => n39);
U18 : AOI22X1 port map( A => tsrData(4), B => n5, C => tsrDataReg_4_port, D
=> n6, Y => n14);
U19 : INVX1 port map( A => tsrDataReg_3_port, Y => n13);
U20 : OAI21X1 port map( A => n3, B => n15, C => n16, Y => n38);
U21 : AOI22X1 port map( A => tsrData(5), B => n5, C => tsrDataReg_5_port, D
=> n6, Y => n16);
U22 : INVX1 port map( A => tsrDataReg_4_port, Y => n15);
U23 : OAI21X1 port map( A => n3, B => n17, C => n18, Y => n37);
U24 : AOI22X1 port map( A => tsrData(6), B => n5, C => tsrDataReg_6_port, D
=> n6, Y => n18);
U25 : INVX1 port map( A => tsrDataReg_5_port, Y => n17);
U26 : OAI21X1 port map( A => n3, B => n19, C => n20, Y => n36);
U27 : AOI22X1 port map( A => tsrData(7), B => n5, C => dataOut_port, D => n6
, Y => n20);
U28 : NOR2X1 port map( A => n6, B => tsrEnable, Y => n5);
U29 : NOR2X1 port map( A => load, B => tsrEnable, Y => n6);
U30 : INVX1 port map( A => tsrDataReg_6_port, Y => n19);
U31 : INVX1 port map( A => tsrEnable, Y => n3);
U32 : NOR2X1 port map( A => load2, B => n21, Y => N2);
U33 : INVX1 port map( A => load1, Y => n21);
end SYN_SpiXmitSR_arch;
library IEEE,OSU_AMI05;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_sniffer_top.all;
entity SpiClkDivide_165_3_0_0 is
port( clk, resetN, sclEnable, sclSpeed : in std_logic; tsrEnable, scl : out
std_logic);
end SpiClkDivide_165_3_0_0;
architecture SYN_SpiClkDivide_arch of SpiClkDivide_165_3_0_0 is
component INVX1
port( A : in std_logic; Y : out std_logic);
end component;
component NOR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component NAND3X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component OAI21X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component AOI21X1
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component NAND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component AND2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component OR2X1
port( A, B : in std_logic; Y : out std_logic);
end component;
component MUX2X1
port( B, A, S : in std_logic; Y : out std_logic);
end component;
component SpiClkDivide_165_3_0_0_DW01_inc_0
port( A : in std_logic_vector (8 downto 0); SUM : out std_logic_vector
(8 downto 0));
end component;
component DFFSR
port( D, CLK, R, S : in std_logic; Q : out std_logic);
end component;
signal count_8_port, count_7_port, count_6_port, count_5_port, count_4_port,
count_3_port, count_2_port, count_1_port, count_0_port, nextcount_8_port,
nextcount_7_port, nextcount_6_port, nextcount_5_port, nextcount_4_port,
nextcount_3_port, nextcount_2_port, nextcount_1_port, nextcount_0_port,
N32, N33, N34, N35, N36, N37, N38, N39, N40, n24, n25, n26, n27, n28, n29
, n30, n31, n32_port, n33_port, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10,
n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n34_port
, n35_port, n36_port, n37_port, n38_port, n39_port : std_logic;
begin
count_reg_0_inst : DFFSR port map( D => nextcount_0_port, CLK => clk, R =>
resetN, S => n33_port, Q => count_0_port);
count_reg_8_inst : DFFSR port map( D => nextcount_8_port, CLK => clk, R =>
resetN, S => n32_port, Q => count_8_port);
count_reg_7_inst : DFFSR port map( D => nextcount_7_port, CLK => clk, R =>
resetN, S => n31, Q => count_7_port);
count_reg_6_inst : DFFSR port map( D => nextcount_6_port, CLK => clk, R =>
resetN, S => n30, Q => count_6_port);
count_reg_5_inst : DFFSR port map( D => nextcount_5_port, CLK => clk, R =>
resetN, S => n29, Q => count_5_port);
count_reg_4_inst : DFFSR port map( D => nextcount_4_port, CLK => clk, R =>
resetN, S => n28, Q => count_4_port);
count_reg_3_inst : DFFSR port map( D => nextcount_3_port, CLK => clk, R =>
resetN, S => n27, Q => count_3_port);
count_reg_2_inst : DFFSR port map( D => nextcount_2_port, CLK => clk, R =>
resetN, S => n26, Q => count_2_port);
count_reg_1_inst : DFFSR port map( D => nextcount_1_port, CLK => clk, R =>
resetN, S => n25, Q => count_1_port);
sclReg_reg : DFFSR port map( D => n39_port, CLK => clk, R => resetN, S =>
n24, Q => scl);
n24 <= '1';
n25 <= '1';
n26 <= '1';
n27 <= '1';
n28 <= '1';
n29 <= '1';
n30 <= '1';
n31 <= '1';
n32_port <= '1';
n33_port <= '1';
add_96 : SpiClkDivide_165_3_0_0_DW01_inc_0 port map( A(8) => count_8_port,
A(7) => count_7_port, A(6) => count_6_port, A(5) =>
count_5_port, A(4) => count_4_port, A(3) =>
count_3_port, A(2) => count_2_port, A(1) =>
count_1_port, A(0) => count_0_port, SUM(8) => N40,
SUM(7) => N39, SUM(6) => N38, SUM(5) => N37, SUM(4)
=> N36, SUM(3) => N35, SUM(2) => N34, SUM(1) => N33,
SUM(0) => N32);
U8 : MUX2X1 port map( B => n1, A => n2, S => count_0_port, Y => tsrEnable);
U9 : NAND2X1 port map( A => sclSpeed, B => n3, Y => n2);
U10 : OR2X1 port map( A => n4, B => n5, Y => n1);
U11 : NAND3X1 port map( A => count_7_port, B => count_5_port, C => n6, Y =>
n5);
U12 : AND2X1 port map( A => count_1_port, B => count_4_port, Y => n6);
U13 : NAND3X1 port map( A => n7, B => n8, C => n9, Y => n4);
U14 : NOR2X1 port map( A => count_8_port, B => count_6_port, Y => n9);
U20 : AND2X1 port map( A => N40, B => n10, Y => nextcount_8_port);
U21 : AND2X1 port map( A => N39, B => n10, Y => nextcount_7_port);
U22 : AND2X1 port map( A => N38, B => n10, Y => nextcount_6_port);
U23 : AND2X1 port map( A => N37, B => n10, Y => nextcount_5_port);
U24 : AND2X1 port map( A => N36, B => n10, Y => nextcount_4_port);
U25 : AND2X1 port map( A => N35, B => n10, Y => nextcount_3_port);
U26 : AND2X1 port map( A => N34, B => n10, Y => nextcount_2_port);
U27 : AND2X1 port map( A => N33, B => n10, Y => nextcount_1_port);
U28 : AND2X1 port map( A => N32, B => n10, Y => nextcount_0_port);
U29 : OAI21X1 port map( A => n11, B => n12, C => n13, Y => n10);
U30 : INVX1 port map( A => n7, Y => n12);
U31 : AND2X1 port map( A => count_8_port, B => n14, Y => n11);
U32 : OAI21X1 port map( A => n15, B => n16, C => n17, Y => n14);
U33 : INVX1 port map( A => count_7_port, Y => n17);
U34 : OAI21X1 port map( A => count_4_port, B => n18, C => count_5_port, Y =>
n16);
U35 : OAI21X1 port map( A => count_0_port, B => n13, C => n19, Y => n39_port
);
U36 : NAND2X1 port map( A => n20, B => n7, Y => n19);
U37 : NOR2X1 port map( A => n21, B => sclSpeed, Y => n7);
U38 : INVX1 port map( A => sclEnable, Y => n21);
U39 : AOI21X1 port map( A => count_7_port, B => n22, C => count_8_port, Y =>
n20);
U40 : OAI21X1 port map( A => n23, B => n34_port, C => n15, Y => n22);
U41 : OAI21X1 port map( A => count_1_port, B => n18, C => count_4_port, Y =>
n34_port);
U42 : INVX1 port map( A => n8, Y => n18);
U43 : INVX1 port map( A => n3, Y => n13);
U44 : NOR2X1 port map( A => n35_port, B => n36_port, Y => n3);
U45 : NAND3X1 port map( A => sclEnable, B => n8, C => n37_port, Y =>
n36_port);
U46 : NOR2X1 port map( A => count_4_port, B => count_1_port, Y => n37_port);
U47 : NOR2X1 port map( A => count_3_port, B => count_2_port, Y => n8);
U48 : NAND3X1 port map( A => n23, B => n15, C => n38_port, Y => n35_port);
U49 : NOR2X1 port map( A => count_8_port, B => count_7_port, Y => n38_port);
U50 : INVX1 port map( A => count_6_port, Y => n15);
U51 : INVX1 port map( A => count_5_port, Y => n23);
end SYN_SpiClkDivide_arch;
library IEEE,OSU_AMI05;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_sniffer_top.all;
entity FifoTop_gregLength4_gregWidth8_addrSize2 is
port( clk, rEnable, resetN : in std_logic; wData : in std_logic_vector (7
downto 0); wEnable : in std_logic; fifoEmpty, fifoFull : out
std_logic; rData : out std_logic_vector (7 downto 0));
end FifoTop_gregLength4_gregWidth8_addrSize2;
architecture SYN_struct of FifoTop_gregLength4_gregWidth8_addrSize2 is
component FifoWrite_gregLength4_addrSize2
port( clk, resetN, wEnable, fifoFull : in std_logic; wSel : out
std_logic_vector (1 downto 0));
end component;
component FifoRead_gregLength4_addrSize2
port( clk, resetN, rEnable, fifoEmpty : in std_logic; rSel : out
std_logic_vector (1 downto 0));
end component;
component FifoRam_gregLength4_gregWidth8_addrSize2
port( clk, resetN, wEnable : in std_logic; wData : in std_logic_vector
(7 downto 0); wSel, rSel : in std_logic_vector (1 downto 0);
rData : out std_logic_vector (7 downto 0); fifoEmpty, fifoFull :
out std_logic);
end component;
signal fifoEmpty_port, fifoFull_port, rSel_1_port, rSel_0_port, wSel_1_port,
wSel_0_port : std_logic;
begin
fifoEmpty <= fifoEmpty_port;
fifoFull <= fifoFull_port;
U_0 : FifoRam_gregLength4_gregWidth8_addrSize2 port map( clk => clk, resetN
=> resetN, wEnable => wEnable, wData(7) => wData(7),
wData(6) => wData(6), wData(5) => wData(5), wData(4)
=> wData(4), wData(3) => wData(3), wData(2) =>
wData(2), wData(1) => wData(1), wData(0) => wData(0)
, wSel(1) => wSel_1_port, wSel(0) => wSel_0_port,
rSel(1) => rSel_1_port, rSel(0) => rSel_0_port,
rData(7) => rData(7), rData(6) => rData(6), rData(5)
=> rData(5), rData(4) => rData(4), rData(3) =>
rData(3), rData(2) => rData(2), rData(1) => rData(1)
, rData(0) => rData(0), fifoEmpty => fifoEmpty_port,
fifoFull => fifoFull_port);
U_1 : FifoRead_gregLength4_addrSize2 port map( clk => clk, resetN => resetN,
rEnable => rEnable, fifoEmpty => fifoEmpty_port,
rSel(1) => rSel_1_port, rSel(0) => rSel_0_port);
U_2 : FifoWrite_gregLength4_addrSize2 port map( clk => clk, resetN => resetN
, wEnable => wEnable, fifoFull => fifoFull_port,
wSel(1) => wSel_1_port, wSel(0) => wSel_0_port);
end SYN_struct;
library IEEE,OSU_AMI05;
use IEEE.std_logic_1164.all;
use work.CONV_PACK_sniffer_top.all;
entity sniffer_top is
port( clk, rst : in std_logic; dataOut, scl, sd_enable : out std_logic;
dataMinusComputer, dataPlusComputer, dataMinusUsb, dataPlusUsb : inout
std_logic);
end sniffer_top;
architecture SYN_struct of sniffer_top is
component sd_control
port( clk, rst, sd_clock, fifo_empty : in std_logic; data_in : in
std_logic_vector (7 downto 0); data_out : out std_logic_vector (7
downto 0); clk_mode, tsr_load, sd_enable, clk_enable, data_read :
out std_logic);
end component;
component interceptor
port( clk, eop, intercept : in std_logic; inst : in std_logic_vector (3
downto 0); rst, usbclk : in std_logic; dataPlus, dataMinus : out
std_logic; computerMinus, computerPlus, usbMinus, usbPlus : inout
std_logic);
end component;
component decoder
port( clk, rst, data0, data1, halt : in std_logic; data : out
std_logic_vector (1 downto 0); inst : out std_logic_vector (3
downto 0); data_out : out std_logic_vector (7 downto 0); dclk,
eopOut : out std_logic);
end component;
component controller
port( clk, rst, fifo_full : in std_logic; decoder_instruction : in
std_logic_vector (3 downto 0); data_ready : in std_logic_vector (1
downto 0); eop_found, data_read : in std_logic; fifo_read,
fifo_write, intercept : out std_logic);
end component;
component SpiXmitSR_srWidth8
port( clk, resetN, tsrEnable, tsrLoad : in std_logic; tsrData : in
std_logic_vector (7 downto 0); dataOut : out std_logic);
end component;
component SpiClkDivide_165_3_0_0
port( clk, resetN, sclEnable, sclSpeed : in std_logic; tsrEnable, scl :
out std_logic);
end component;
component FifoTop_gregLength4_gregWidth8_addrSize2
port( clk, rEnable, resetN : in std_logic; wData : in std_logic_vector
(7 downto 0); wEnable : in std_logic; fifoEmpty, fifoFull : out
std_logic; rData : out std_logic_vector (7 downto 0));
end component;
signal scl_port, fifo_read, data_out_7_port, data_out_6_port,
data_out_5_port, data_out_4_port, data_out_3_port, data_out_2_port,
data_out_1_port, data_out_0_port, fifo_write, fifoEmpty, fifoFull,
rData_7_port, rData_6_port, rData_5_port, rData_4_port, rData_3_port,
rData_2_port, rData_1_port, rData_0_port, sclEnable, clk_mode, tsrEnable,
dout_7_port, dout_6_port, dout_5_port, dout_4_port, dout_3_port,
dout_2_port, dout_1_port, dout_0_port, tsrLoad, data_read,
data_ready_1_port, data_ready_0_port, inst_3_port, inst_2_port,
inst_1_port, inst_0_port, eop, intercept, dataPlus, dataMinus, dclk :
std_logic;
begin
scl <= scl_port;
U_2 : FifoTop_gregLength4_gregWidth8_addrSize2 port map( clk => clk, rEnable
=> fifo_read, resetN => rst, wData(7) =>
data_out_7_port, wData(6) => data_out_6_port,
wData(5) => data_out_5_port, wData(4) =>
data_out_4_port, wData(3) => data_out_3_port,
wData(2) => data_out_2_port, wData(1) =>
data_out_1_port, wData(0) => data_out_0_port,
wEnable => fifo_write, fifoEmpty => fifoEmpty,
fifoFull => fifoFull, rData(7) => rData_7_port,
rData(6) => rData_6_port, rData(5) => rData_5_port,
rData(4) => rData_4_port, rData(3) => rData_3_port,
rData(2) => rData_2_port, rData(1) => rData_1_port,
rData(0) => rData_0_port);
U_5 : SpiClkDivide_165_3_0_0 port map( clk => clk, resetN => rst, sclEnable
=> sclEnable, sclSpeed => clk_mode, tsrEnable =>
tsrEnable, scl => scl_port);
U_4 : SpiXmitSR_srWidth8 port map( clk => clk, resetN => rst, tsrEnable =>
tsrEnable, tsrLoad => tsrLoad, tsrData(7) =>
dout_7_port, tsrData(6) => dout_6_port, tsrData(5)
=> dout_5_port, tsrData(4) => dout_4_port,
tsrData(3) => dout_3_port, tsrData(2) => dout_2_port
, tsrData(1) => dout_1_port, tsrData(0) =>
dout_0_port, dataOut => dataOut);
U_0 : controller port map( clk => clk, rst => rst, fifo_full => fifoFull,
decoder_instruction(3) => inst_3_port,
decoder_instruction(2) => inst_2_port,
decoder_instruction(1) => inst_1_port,
decoder_instruction(0) => inst_0_port, data_ready(1)
=> data_ready_1_port, data_ready(0) =>
data_ready_0_port, eop_found => eop, data_read =>
data_read, fifo_read => fifo_read, fifo_write =>
fifo_write, intercept => intercept);
U_1 : decoder port map( clk => clk, rst => rst, data0 => dataPlus, data1 =>
dataMinus, halt => intercept, data(1) =>
data_ready_1_port, data(0) => data_ready_0_port,
inst(3) => inst_3_port, inst(2) => inst_2_port,
inst(1) => inst_1_port, inst(0) => inst_0_port,
data_out(7) => data_out_7_port, data_out(6) =>
data_out_6_port, data_out(5) => data_out_5_port,
data_out(4) => data_out_4_port, data_out(3) =>
data_out_3_port, data_out(2) => data_out_2_port,
data_out(1) => data_out_1_port, data_out(0) =>
data_out_0_port, dclk => dclk, eopOut => eop);
U_3 : interceptor port map( clk => clk, eop => eop, intercept => intercept,
inst(3) => inst_3_port, inst(2) => inst_2_port,
inst(1) => inst_1_port, inst(0) => inst_0_port, rst
=> rst, usbclk => dclk, dataPlus => dataPlus,
dataMinus => dataMinus, computerMinus =>
dataMinusComputer, computerPlus => dataPlusComputer,
usbMinus => dataMinusUsb, usbPlus => dataPlusUsb);
U_6 : sd_control port map( clk => clk, rst => rst, sd_clock => scl_port,
fifo_empty => fifoEmpty, data_in(7) => rData_7_port,
data_in(6) => rData_6_port, data_in(5) =>
rData_5_port, data_in(4) => rData_4_port, data_in(3)
=> rData_3_port, data_in(2) => rData_2_port,
data_in(1) => rData_1_port, data_in(0) =>
rData_0_port, data_out(7) => dout_7_port,
data_out(6) => dout_6_port, data_out(5) =>
dout_5_port, data_out(4) => dout_4_port, data_out(3)
=> dout_3_port, data_out(2) => dout_2_port,
data_out(1) => dout_1_port, data_out(0) =>
dout_0_port, clk_mode => clk_mode, tsr_load =>
tsrLoad, sd_enable => sd_enable, clk_enable =>
sclEnable, data_read => data_read);
end SYN_struct;
|
-- Company: Fachhochschule Dortmund
-- Engineer: Javier Reyes
--
-- Create Date: 06/16/2017 04:49:58 PM
-- Design Name: Polynomial Adder Testbench for Convolutional Codes example project
-- Module Name: polyadder_tb - Simulation
-- Project Name: Convolutional Codes example project
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.conf_pkg.all;
entity polyadder_tb is
-- EMPTY
end polyadder_tb;
architecture Behavioral of polyadder_tb is
-- Signals declaration
-- MSB is input of shift register
signal d_in : std_logic_vector(m-1 downto 0);
signal d_out : std_logic_vector(n-1 downto 0);
-- Components declaration
component polyadder
port (add_in : in std_logic_vector(m-1 downto 0);
add_out : out std_logic_vector(n-1 downto 0));
end component;
begin
-- instantiating the components
POLADD : polyadder port map (d_in, d_out);
-- Bit stream generated (emulate output of shift register)
d_in_process : process
begin
-- Initialized as zero
d_in <= std_logic_vector(to_unsigned(0, m));
wait for 2*clk_period;
-- Insert 1, value 1000 = 8
d_in <= std_logic_vector(to_unsigned(8, m));
wait for clk_period;
-- Insert 0, value 0100 = 4
d_in <= std_logic_vector(to_unsigned(4, m));
wait for clk_period;
-- Insert 1, value 1010 = 12
d_in <= std_logic_vector(to_unsigned(10, m));
wait for clk_period;
-- Insert 1, value 1101 = 13
d_in <= std_logic_vector(to_unsigned(13, m));
wait for clk_period;
-- Insert 0, value 0110 = 6 (trail)
d_in <= std_logic_vector(to_unsigned(6, m));
wait for clk_period;
-- Insert 0, value 0011 = 3 (trail)
d_in <= std_logic_vector(to_unsigned(3, m));
wait for clk_period;
-- Insert 0, value 0001 = 1 (trail)
d_in <= std_logic_vector(to_unsigned(1, m));
wait for clk_period;
-- Insert 0, value 0000 = 0 (trail)
d_in <= std_logic_vector(to_unsigned(0, m));
wait for clk_period;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- axi_vdma_lite_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_lite_if.vhd
-- Description: This entity is AXI Lite Interface Module for the AXI DMA
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
library lib_cdc_v1_0;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_vdma_lite_if is
generic(
C_MM2S_IS : integer range 0 to 1 := 1;
-- Include or exclude MM2S channel
-- 0 = exclude mm2s channel
-- 1 = include mm2s channel
C_S2MM_IS : integer range 0 to 1 := 1;
-- Include or exclude S2MM channel
-- 0 = exclude s2mm channel
-- 1 = include s2mm channel
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 1;
-- Specifies the AXI Lite clock is asynchronous
-- 0 = AXI Clocks are Synchronous
-- 1 = AXI Clocks are Asynchronous
C_NUM_CE : integer := 8 ;
C_S_AXI_LITE_ADDR_WIDTH : integer range 9 to 9 := 9 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32
);
port (
----------------------------------------------------------------------- --
-- AXI Lite Control Interface --
----------------------------------------------------------------------- --
s_axi_lite_aclk : in std_logic ; --
s_axi_lite_aresetn : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
mm2s_hrd_resetn : in std_logic ; --
m_axi_s2mm_aclk : in std_logic ; --
s2mm_hrd_resetn : in std_logic ; --
--
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
axi2ip_lite_rdaddr : out std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
-- MM2S Reg Interface signals --
mm2s_axi2ip_wrdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_axi2ip_wrce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
mm2s_ip2axi_rddata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
mm2s_axi2ip_rdaddr : out std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
-- S2MM Reg Interface signals --
s2mm_axi2ip_wrdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_axi2ip_wrce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
s2mm_ip2axi_rddata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
s2mm_axi2ip_rdaddr : out std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
axi2ip_common_region_1_rden : out std_logic ; --
axi2ip_common_region_2_rden : out std_logic ; --
--
--
ip2axi_rddata_common_region : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) --
);
end axi_vdma_lite_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_lite_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Register I/F Address offset
constant ADDR_OFFSET : integer := clog2(C_S_AXI_LITE_DATA_WIDTH/8);
-- Register I/F CE number
constant CE_ADDR_SIZE : integer := clog2(C_NUM_CE);
constant ZERO_VALUE_VECT : std_logic_vector(128 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- AXI Lite slave interface signals
signal awvalid : std_logic := '0';
signal wvalid : std_logic := '0';
signal arvalid : std_logic := '0';
signal awaddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal wdata : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal araddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_ip2axi_rddata_d1 : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal s2mm_ip2axi_rddata_d1 : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal write_response_accepted : std_logic := '0';
signal write_has_started : std_logic := '0';
signal awready_out_i : std_logic := '0';
signal wready_out_i : std_logic := '0';
signal wrce_gen : std_logic_vector(C_NUM_CE-1 downto 0);
signal bvalid_out_i : std_logic := '0';
signal read_data_res_accepted : std_logic := '0';
signal read_has_started_i : std_logic := '0';
signal sig_arvalid_arrived : std_logic := '0';
signal sig_arvalid_arrived_d1 : std_logic := '0';
signal sig_arvalid_arrived_d2 : std_logic := '0';
signal sig_arvalid_arrived_d3 : std_logic := '0';
signal sig_arvalid_arrived_d4 : std_logic := '0';
signal sig_arvalid_detected : std_logic := '0';
signal arready_out_i_cmb : std_logic := '0';
signal arready_out_i : std_logic := '0';
signal arready_out_i_mm2s : std_logic := '0';
signal arready_out_i_s2mm : std_logic := '0';
signal arready_out_i_common : std_logic := '0';
signal rvalid_out_i : std_logic := '0';
----Async_mode
signal wready_out_to_bvalid : std_logic := '0';
signal mm2s_wrce_gen : std_logic_vector(C_NUM_CE-1 downto 0);
signal s2mm_wrce_gen : std_logic_vector(C_NUM_CE-1 downto 0);
signal addr_region_mm2s_rden_cmb : std_logic := '0';
signal addr_region_s2mm_rden_cmb : std_logic := '0';
signal addr_region_1_common_rden_cmb : std_logic := '0';
signal addr_region_2_common_rden_cmb : std_logic := '0';
signal ip2axi_rddata_captured : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
signal ip2axi_rddata_captured_d1 : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
signal ip2axi_rddata_captured_mm2s_cdc_tig : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
signal ip2axi_rddata_captured_s2mm_cdc_tig : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
signal axi2ip_rdaddr_captured : std_logic_vector(7 downto 2) := (others => '0'); --
--signal axi2ip_rdaddr_captured_mm2s_cdc_tig : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
--signal axi2ip_rdaddr_captured_s2mm_cdc_tig : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
signal axi2ip_rdaddr_captured_mm2s_cdc_tig : std_logic_vector(7 downto 2) := (others => '0'); --
signal axi2ip_rdaddr_captured_s2mm_cdc_tig : std_logic_vector(7 downto 2) := (others => '0'); --
signal axi2ip_wraddr_captured : std_logic_vector(7 downto 2) := (others => '0'); --
--signal axi2ip_wraddr_captured_mm2s_cdc_tig : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
--signal axi2ip_wraddr_captured_s2mm_cdc_tig : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
signal axi2ip_wraddr_captured_mm2s_cdc_tig : std_logic_vector(7 downto 2) := (others => '0'); --
signal axi2ip_wraddr_captured_s2mm_cdc_tig : std_logic_vector(7 downto 2) := (others => '0'); --
signal arready_out_i_d1 : std_logic := '0';
signal sig_awvalid_arrived_d1 : std_logic := '0';
signal sig_awvalid_arrived : std_logic := '0';
signal sig_awvalid_detected : std_logic := '0';
signal sig_wvalid_arrived : std_logic := '0';
signal lite_wr_addr_phase_finished_data_phase_started : std_logic := '0';
signal prepare_wrce : std_logic := '0';
signal prepare_wrce_d1 : std_logic := '0';
signal prepare_wrce_pulse_lite : std_logic := '0';
signal prepare_wrce_pulse_lite_d1 : std_logic := '0';
signal prepare_wrce_pulse_lite_d2 : std_logic := '0';
signal prepare_wrce_pulse_lite_d3 : std_logic := '0';
signal prepare_wrce_pulse_lite_d4 : std_logic := '0';
signal prepare_wrce_pulse_lite_d5 : std_logic := '0';
signal prepare_wrce_pulse_lite_d6 : std_logic := '0';
signal prepare_wrce_pulse_mm2s : std_logic := '0';
signal prepare_wrce_pulse_s2mm : std_logic := '0';
signal wready_mm2s : std_logic := '0';
signal wready_s2mm : std_logic := '0';
signal lite_mm2s_wr_done : std_logic := '0';
signal lite_s2mm_wr_done : std_logic := '0';
signal lite_wr_done : std_logic := '0';
signal lite_wr_done_d1 : std_logic := '0';
signal sig_arvalid_arrived_d1_mm2s_rd_lite_domain : std_logic := '0';
signal sig_arvalid_arrived_d1_mm2s : std_logic := '0';
signal sig_arvalid_arrived_d1_s2mm_rd_lite_domain : std_logic := '0';
signal sig_arvalid_arrived_d1_s2mm : std_logic := '0';
signal mm2s_axi2ip_wrdata_cdc_tig : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
signal s2mm_axi2ip_wrdata_cdc_tig : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF ip2axi_rddata_captured_mm2s_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF ip2axi_rddata_captured_s2mm_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF axi2ip_rdaddr_captured_mm2s_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF axi2ip_rdaddr_captured_s2mm_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF axi2ip_wraddr_captured_mm2s_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF axi2ip_wraddr_captured_s2mm_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF mm2s_axi2ip_wrdata_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF s2mm_axi2ip_wrdata_cdc_tig : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
s_axi_lite_awready <= awready_out_i;
s_axi_lite_wready <= wready_out_i;
s_axi_lite_bvalid <= bvalid_out_i;
s_axi_lite_arready <= arready_out_i;
s_axi_lite_rvalid <= rvalid_out_i;
axi2ip_lite_rdaddr(8) <= '0';
axi2ip_lite_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
axi2ip_lite_rdaddr(1) <= '0';
axi2ip_lite_rdaddr(0) <= '0';
mm2s_axi2ip_rdaddr(8) <= '0';
mm2s_axi2ip_rdaddr(1) <= '0';
mm2s_axi2ip_rdaddr(0) <= '0';
s2mm_axi2ip_rdaddr(8) <= '0';
s2mm_axi2ip_rdaddr(1) <= '0';
s2mm_axi2ip_rdaddr(0) <= '0';
s_axi_lite_bresp <= OKAY_RESP;
s_axi_lite_rresp <= OKAY_RESP;
-------------------------------------------------------------------------------------------------
--------------------------- Register AXI4-LITE Control signals ----------------------------------
-------------------------------------------------------------------------------------------------
REG_INPUTS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
awvalid <= '0' ;
wvalid <= '0' ;
arvalid <= '0' ;
awaddr <= (others => '0') ;
wdata <= (others => '0') ;
araddr <= (others => '0') ;
else
awvalid <= s_axi_lite_awvalid ;
wvalid <= s_axi_lite_wvalid ;
arvalid <= s_axi_lite_arvalid ;
awaddr <= s_axi_lite_awaddr ;
wdata <= s_axi_lite_wdata ;
araddr <= s_axi_lite_araddr ;
end if;
end if;
end process REG_INPUTS;
-------------------------------------------------------------------------------
-------------------------------AXI4-LITE WRITE---------------------------------
-------------------------------------------------------------------------------
sig_awvalid_arrived <= awvalid;
sig_wvalid_arrived <= wvalid;
D1_LITE_WR_ADDR_PHASE_DETECT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or write_has_started = '1')then
sig_awvalid_arrived_d1 <= '0';
else
sig_awvalid_arrived_d1 <= sig_awvalid_arrived;
end if;
end if;
end process D1_LITE_WR_ADDR_PHASE_DETECT;
AXI4_LITE_WR_STARTED : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or write_response_accepted = '1')then
write_has_started <= '0';
elsif(sig_awvalid_detected = '1')then
write_has_started <= '1';
end if;
end if;
end process AXI4_LITE_WR_STARTED;
sig_awvalid_detected <= sig_awvalid_arrived and not (sig_awvalid_arrived_d1) and not (write_has_started);
--axi2ip_wraddr_captured <= awaddr when sig_awvalid_detected = '1';
CAPTURE_AWADDR : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_wraddr_captured(7 downto 2) <= (others => '0');
elsif(sig_awvalid_detected = '1')then
axi2ip_wraddr_captured(7 downto 2) <= awaddr(7 downto 2);
end if;
end if;
end process CAPTURE_AWADDR;
GEN_LITE_AWREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
awready_out_i <= '0';
else
awready_out_i <= sig_awvalid_detected;
end if;
end if;
end process GEN_LITE_AWREADY;
GEN_WR_ADDR_PHASE_TO_DATA_PHASE : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or wready_out_i = '1')then
lite_wr_addr_phase_finished_data_phase_started <= '0';
elsif(awready_out_i = '1')then
lite_wr_addr_phase_finished_data_phase_started <= '1';
end if;
end if;
end process GEN_WR_ADDR_PHASE_TO_DATA_PHASE;
--------------------------------------------------------------------------------------------------
--***** SYNC_MODE
--------------------------------------------------------------------------------------------------
GEN_LITE_IS_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
prepare_wrce <= sig_wvalid_arrived and lite_wr_addr_phase_finished_data_phase_started;
GEN_WRCE_PULSE : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
prepare_wrce_d1 <= '0';
else
prepare_wrce_d1 <= prepare_wrce;
end if;
end if;
end process GEN_WRCE_PULSE;
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
AXI4_LITE_WRCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
wrce_gen(j) <= (prepare_wrce and not prepare_wrce_d1) when axi2ip_wraddr_captured
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate AXI4_LITE_WRCE_GEN;
mm2s_axi2ip_wrce <= wrce_gen;
s2mm_axi2ip_wrce <= wrce_gen;
GEN_LITE_WREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
wready_out_i <= '0';
else
wready_out_i <= (prepare_wrce and not prepare_wrce_d1);
end if;
end if;
end process GEN_LITE_WREADY;
wready_out_to_bvalid <= wready_out_i;
-------------------------
--*READ
-------------------------
GEN_LITE_ARREADY_SYNC : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_out_i <= '0';
else
arready_out_i <= sig_arvalid_arrived_d1;
end if;
end if;
end process GEN_LITE_ARREADY_SYNC;
s_axi_lite_rdata <= ip2axi_rddata_captured_d1;
process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
ip2axi_rddata_captured_d1 <= ip2axi_rddata_captured;
end if;
end process ;
ip2axi_rddata_captured <= ip2axi_rddata_common_region when addr_region_1_common_rden_cmb = '1' or addr_region_2_common_rden_cmb = '1'
else mm2s_ip2axi_rddata when addr_region_mm2s_rden_cmb = '1'
else s2mm_ip2axi_rddata;
AXI4_LITE_RRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
rvalid_out_i <= '0';
elsif(rvalid_out_i = '1' and s_axi_lite_rready = '1')then
rvalid_out_i <= '0';
elsif(arready_out_i = '1')then
rvalid_out_i <= '1';
end if;
end if;
end process AXI4_LITE_RRESP_PROCESS;
-------------------------
--*READ
-------------------------
mm2s_axi2ip_wrdata <= wdata;
s2mm_axi2ip_wrdata <= wdata;
mm2s_axi2ip_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
s2mm_axi2ip_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
end generate GEN_LITE_IS_SYNC;
--------------------------------------------------------------------------------------------------
--***** SYNC_MODE
--------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------AXI4-LITE READ----------------------------------
-------------------------------------------------------------------------------
sig_arvalid_arrived <= arvalid;
D1_LITE_RD_DETECT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or read_has_started_i = '1')then
sig_arvalid_arrived_d1 <= '0';
else
sig_arvalid_arrived_d1 <= sig_arvalid_arrived;
end if;
end if;
end process D1_LITE_RD_DETECT;
AXI4_LITE_RD_STARTED : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or read_data_res_accepted = '1')then
read_has_started_i <= '0';
elsif(sig_arvalid_detected = '1')then
read_has_started_i <= '1';
end if;
end if;
end process AXI4_LITE_RD_STARTED;
sig_arvalid_detected <= sig_arvalid_arrived and not (sig_arvalid_arrived_d1) and not (read_has_started_i);
read_data_res_accepted <= rvalid_out_i and s_axi_lite_rready;
CAPTURE_ARADDR : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_rdaddr_captured(7 downto 2) <= (others => '0');
elsif(sig_arvalid_detected = '1')then
axi2ip_rdaddr_captured(7 downto 2) <= araddr(7 downto 2);
end if;
end if;
end process CAPTURE_ARADDR;
-------------------------------------------------------------------------------
-- Decode read_lite_addr MSB to get the region of read access
-------------------------------------------------------------------------------
--*****************************************************************************
-- MM2S_Region_1 (0x00 to 0x1C)
-- MM2S_Region_2 (0x50 to 0x9C)
-- S2MM_Region_1 (0x30 to 0x3C)
-- S2MM_Region_2 (0xA0 to 0xEC)
-- Common_Region_1 (0x20 to 0x2C) (common read only register)
-- Common_Region_2 (0xF0 to 0xFC) (s2mm read-only registers)
--*****************************************************************************
addr_region_1_common_rden_cmb <= ((not axi2ip_rdaddr_captured(7)) and (not axi2ip_rdaddr_captured(6)) and (axi2ip_rdaddr_captured(5)) and (not axi2ip_rdaddr_captured(4)));
addr_region_2_common_rden_cmb <= (axi2ip_rdaddr_captured(7) and axi2ip_rdaddr_captured(6) and axi2ip_rdaddr_captured(5) and axi2ip_rdaddr_captured(4));
--MM2S Region read
addr_region_mm2s_rden_cmb <= (((not axi2ip_rdaddr_captured(6)) and (not axi2ip_rdaddr_captured(5)))
or
((not axi2ip_rdaddr_captured(7)) and (not axi2ip_rdaddr_captured(5)) and (axi2ip_rdaddr_captured(4)))
or
((not axi2ip_rdaddr_captured(7)) and (axi2ip_rdaddr_captured(6)) and (axi2ip_rdaddr_captured(5))))
;
--S2MM Region read
addr_region_s2mm_rden_cmb <= (((axi2ip_rdaddr_captured(7)) and (axi2ip_rdaddr_captured(5)) and (not axi2ip_rdaddr_captured(4)))
or
((not axi2ip_rdaddr_captured(6)) and (axi2ip_rdaddr_captured(5)) and (axi2ip_rdaddr_captured(4)))
or
((axi2ip_rdaddr_captured(6)) and (not axi2ip_rdaddr_captured(5)) and (not axi2ip_rdaddr_captured(4)))
or
((axi2ip_rdaddr_captured(7)) and (axi2ip_rdaddr_captured(6)) and (not axi2ip_rdaddr_captured(5))));
-------------------------------------------------------------------------------
-- Write Response
-------------------------------------------------------------------------------
AXI4_LITE_WRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
bvalid_out_i <= '0';
elsif(bvalid_out_i = '1' and s_axi_lite_bready = '1')then
bvalid_out_i <= '0';
elsif(wready_out_to_bvalid = '1')then
bvalid_out_i <= '1';
end if;
end if;
end process AXI4_LITE_WRESP_PROCESS;
write_response_accepted <= bvalid_out_i and s_axi_lite_bready;
axi2ip_common_region_1_rden <= addr_region_1_common_rden_cmb;
GEN_S2MM_COM_REG2_READ : if C_S2MM_IS = 1 generate
axi2ip_common_region_2_rden <= addr_region_2_common_rden_cmb;
end generate GEN_S2MM_COM_REG2_READ;
GEN_NO_S2MM_COM_REG2_READ : if C_S2MM_IS = 0 generate
axi2ip_common_region_2_rden <= '0';
end generate GEN_NO_S2MM_COM_REG2_READ;
--------------------------------------------------------------------------------------------------
--***** ASYNC_MODE
--------------------------------------------------------------------------------------------------
GEN_LITE_IS_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
--Both channels exist and async mode
GEN_ASYNC_LITE_ACCESS : if C_MM2S_IS = 1 and C_S2MM_IS = 1 generate
prepare_wrce <= sig_wvalid_arrived and lite_wr_addr_phase_finished_data_phase_started;
GEN_WRCE_PULSE : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
prepare_wrce_d1 <= '0';
else
prepare_wrce_d1 <= prepare_wrce;
end if;
end if;
end process GEN_WRCE_PULSE;
prepare_wrce_pulse_lite <= prepare_wrce and not prepare_wrce_d1;
--MM2S
----
---- LITE_WVALID_MM2S_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => s_axi_lite_aclk ,
---- prmry_resetn => s_axi_lite_aresetn ,
---- scndry_aclk => m_axi_mm2s_aclk ,
---- scndry_resetn => mm2s_hrd_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => prepare_wrce_pulse_lite ,
---- scndry_out => prepare_wrce_pulse_mm2s ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
LITE_WVALID_MM2S_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => s_axi_lite_aresetn,
prmry_in => prepare_wrce_pulse_lite,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_mm2s_aclk,
scndry_resetn => mm2s_hrd_resetn,
scndry_out => prepare_wrce_pulse_mm2s,
scndry_vect_out => open
);
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
AXI4_LITE_WRCE_MM2S_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
mm2s_wrce_gen(j) <= prepare_wrce_pulse_mm2s when axi2ip_wraddr_captured_mm2s_cdc_tig
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate AXI4_LITE_WRCE_MM2S_GEN;
mm2s_axi2ip_wrce <= mm2s_wrce_gen;
--S2MM
---- LITE_WVALID_S2MM_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => s_axi_lite_aclk ,
---- prmry_resetn => s_axi_lite_aresetn ,
---- scndry_aclk => m_axi_s2mm_aclk ,
---- scndry_resetn => s2mm_hrd_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => prepare_wrce_pulse_lite ,
---- scndry_out => prepare_wrce_pulse_s2mm ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
LITE_WVALID_S2MM_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => s_axi_lite_aresetn,
prmry_in => prepare_wrce_pulse_lite,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_s2mm_aclk,
scndry_resetn => s2mm_hrd_resetn,
scndry_out => prepare_wrce_pulse_s2mm,
scndry_vect_out => open
);
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
AXI4_LITE_WRCE_S2MM_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
s2mm_wrce_gen(j) <= prepare_wrce_pulse_s2mm when axi2ip_wraddr_captured_s2mm_cdc_tig
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate AXI4_LITE_WRCE_S2MM_GEN;
s2mm_axi2ip_wrce <= s2mm_wrce_gen;
GEN_LITE_WREADY_OUT_D : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
prepare_wrce_pulse_lite_d1 <= prepare_wrce_pulse_lite;
prepare_wrce_pulse_lite_d2 <= prepare_wrce_pulse_lite_d1;
prepare_wrce_pulse_lite_d3 <= prepare_wrce_pulse_lite_d2;
prepare_wrce_pulse_lite_d4 <= prepare_wrce_pulse_lite_d3;
prepare_wrce_pulse_lite_d5 <= prepare_wrce_pulse_lite_d4;
prepare_wrce_pulse_lite_d6 <= prepare_wrce_pulse_lite_d5;
end if;
end process GEN_LITE_WREADY_OUT_D;
GEN_LITE_WREADY_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
wready_out_i <= '0';
else
wready_out_i <= prepare_wrce_pulse_lite_d6;
end if;
end if;
end process GEN_LITE_WREADY_OUT;
wready_out_to_bvalid <= wready_out_i;
-------------------------
--*READ
-------------------------
--MM2S
GEN_LITE_ARREADY_ASYNC_D : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
sig_arvalid_arrived_d2 <= sig_arvalid_arrived_d1;
sig_arvalid_arrived_d3 <= sig_arvalid_arrived_d2;
sig_arvalid_arrived_d4 <= sig_arvalid_arrived_d3;
end if;
end process GEN_LITE_ARREADY_ASYNC_D;
GEN_LITE_ARREADY_ASYNC : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_out_i <= '0';
else
arready_out_i <= sig_arvalid_arrived_d4;
end if;
end if;
end process GEN_LITE_ARREADY_ASYNC;
AXI4_LITE_RRESP_ASYNC_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
rvalid_out_i <= '0';
elsif(rvalid_out_i = '1' and s_axi_lite_rready = '1')then
rvalid_out_i <= '0';
elsif(arready_out_i = '1')then
rvalid_out_i <= '1';
end if;
end if;
end process AXI4_LITE_RRESP_ASYNC_PROCESS;
s_axi_lite_rdata <= ip2axi_rddata_captured_d1;
process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
ip2axi_rddata_captured_d1 <= ip2axi_rddata_captured;
end if;
end process ;
ip2axi_rddata_captured <= ip2axi_rddata_common_region when addr_region_1_common_rden_cmb = '1' or addr_region_2_common_rden_cmb = '1'
else ip2axi_rddata_captured_mm2s_cdc_tig when addr_region_mm2s_rden_cmb = '1'
else ip2axi_rddata_captured_s2mm_cdc_tig;
process(m_axi_mm2s_aclk)
begin
if(m_axi_mm2s_aclk'EVENT and m_axi_mm2s_aclk = '1')then
mm2s_ip2axi_rddata_d1 <= mm2s_ip2axi_rddata;
end if;
end process ;
GEN_LITE_MM2S_RDATA_CROSSING : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
ip2axi_rddata_captured_mm2s_cdc_tig <= mm2s_ip2axi_rddata_d1;
end if;
end process GEN_LITE_MM2S_RDATA_CROSSING;
process(m_axi_s2mm_aclk)
begin
if(m_axi_s2mm_aclk'EVENT and m_axi_s2mm_aclk = '1')then
s2mm_ip2axi_rddata_d1 <= s2mm_ip2axi_rddata;
end if;
end process ;
GEN_LITE_S2MM_RDATA_CROSSING : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
ip2axi_rddata_captured_s2mm_cdc_tig <= s2mm_ip2axi_rddata_d1;
end if;
end process GEN_LITE_S2MM_RDATA_CROSSING;
GEN_LITE_MM2S_WDATA_CROSSING : process(m_axi_mm2s_aclk)
begin
if(m_axi_mm2s_aclk'EVENT and m_axi_mm2s_aclk = '1')then
mm2s_axi2ip_wrdata_cdc_tig <= wdata;
end if;
end process GEN_LITE_MM2S_WDATA_CROSSING;
GEN_LITE_S2MM_WDATA_CROSSING : process(m_axi_s2mm_aclk)
begin
if(m_axi_s2mm_aclk'EVENT and m_axi_s2mm_aclk = '1')then
s2mm_axi2ip_wrdata_cdc_tig <= wdata;
end if;
end process GEN_LITE_S2MM_WDATA_CROSSING;
mm2s_axi2ip_wrdata <= mm2s_axi2ip_wrdata_cdc_tig;
s2mm_axi2ip_wrdata <= s2mm_axi2ip_wrdata_cdc_tig;
GEN_LITE_MM2S_RDADDR_CROSSING : process(m_axi_mm2s_aclk)
begin
if(m_axi_mm2s_aclk'EVENT and m_axi_mm2s_aclk = '1')then
axi2ip_rdaddr_captured_mm2s_cdc_tig(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
end if;
end process GEN_LITE_MM2S_RDADDR_CROSSING;
GEN_LITE_S2MM_RDADDR_CROSSING : process(m_axi_s2mm_aclk)
begin
if(m_axi_s2mm_aclk'EVENT and m_axi_s2mm_aclk = '1')then
axi2ip_rdaddr_captured_s2mm_cdc_tig(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
end if;
end process GEN_LITE_S2MM_RDADDR_CROSSING;
mm2s_axi2ip_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured_mm2s_cdc_tig(7 downto 2);
s2mm_axi2ip_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured_s2mm_cdc_tig(7 downto 2);
GEN_LITE_MM2S_WRADDR_CROSSING : process(m_axi_mm2s_aclk)
begin
if(m_axi_mm2s_aclk'EVENT and m_axi_mm2s_aclk = '1')then
axi2ip_wraddr_captured_mm2s_cdc_tig(7 downto 2) <= axi2ip_wraddr_captured(7 downto 2);
end if;
end process GEN_LITE_MM2S_WRADDR_CROSSING;
GEN_LITE_S2MM_WRADDR_CROSSING : process(m_axi_s2mm_aclk)
begin
if(m_axi_s2mm_aclk'EVENT and m_axi_s2mm_aclk = '1')then
axi2ip_wraddr_captured_s2mm_cdc_tig(7 downto 2) <= axi2ip_wraddr_captured(7 downto 2);
end if;
end process GEN_LITE_S2MM_WRADDR_CROSSING;
end generate GEN_ASYNC_LITE_ACCESS;
--------------------------------------------
--ASYNC_MODE but only single channel enabled
--------------------------------------------
GEN_S2MM_ONLY_ASYNC_LITE_ACCESS : if C_MM2S_IS = 0 and C_S2MM_IS = 1 generate
--Write
prepare_wrce <= sig_wvalid_arrived and lite_wr_addr_phase_finished_data_phase_started;
GEN_WRCE_PULSE : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
prepare_wrce_d1 <= '0';
else
prepare_wrce_d1 <= prepare_wrce;
end if;
end if;
end process GEN_WRCE_PULSE;
prepare_wrce_pulse_lite <= prepare_wrce and not prepare_wrce_d1;
--S2MM
---- LITE_WVALID_S2MM_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => s_axi_lite_aclk ,
---- prmry_resetn => s_axi_lite_aresetn ,
---- scndry_aclk => m_axi_s2mm_aclk ,
---- scndry_resetn => s2mm_hrd_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => prepare_wrce_pulse_lite ,
---- scndry_out => prepare_wrce_pulse_s2mm ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
LITE_WVALID_S2MM_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => s_axi_lite_aresetn,
prmry_in => prepare_wrce_pulse_lite,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_s2mm_aclk,
scndry_resetn => s2mm_hrd_resetn,
scndry_out => prepare_wrce_pulse_s2mm,
scndry_vect_out => open
);
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
AXI4_LITE_WRCE_S2MM_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
s2mm_wrce_gen(j) <= prepare_wrce_pulse_s2mm when axi2ip_wraddr_captured_s2mm_cdc_tig
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate AXI4_LITE_WRCE_S2MM_GEN;
s2mm_axi2ip_wrce <= s2mm_wrce_gen;
GEN_LITE_WREADY_OUT_D : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
prepare_wrce_pulse_lite_d1 <= prepare_wrce_pulse_lite;
prepare_wrce_pulse_lite_d2 <= prepare_wrce_pulse_lite_d1;
prepare_wrce_pulse_lite_d3 <= prepare_wrce_pulse_lite_d2;
prepare_wrce_pulse_lite_d4 <= prepare_wrce_pulse_lite_d3;
prepare_wrce_pulse_lite_d5 <= prepare_wrce_pulse_lite_d4;
prepare_wrce_pulse_lite_d6 <= prepare_wrce_pulse_lite_d5;
end if;
end process GEN_LITE_WREADY_OUT_D;
GEN_LITE_WREADY_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
wready_out_i <= '0';
else
wready_out_i <= prepare_wrce_pulse_lite_d6;
end if;
end if;
end process GEN_LITE_WREADY_OUT;
wready_out_to_bvalid <= wready_out_i;
--Read
--S2MM
GEN_LITE_ARREADY_ASYNC_D : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
sig_arvalid_arrived_d2 <= sig_arvalid_arrived_d1;
sig_arvalid_arrived_d3 <= sig_arvalid_arrived_d2;
sig_arvalid_arrived_d4 <= sig_arvalid_arrived_d3;
end if;
end process GEN_LITE_ARREADY_ASYNC_D;
GEN_LITE_ARREADY_ASYNC : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_out_i <= '0';
else
arready_out_i <= sig_arvalid_arrived_d4;
end if;
end if;
end process GEN_LITE_ARREADY_ASYNC;
AXI4_LITE_RRESP_ASYNC_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
rvalid_out_i <= '0';
elsif(rvalid_out_i = '1' and s_axi_lite_rready = '1')then
rvalid_out_i <= '0';
elsif(arready_out_i = '1')then
rvalid_out_i <= '1';
end if;
end if;
end process AXI4_LITE_RRESP_ASYNC_PROCESS;
s_axi_lite_rdata <= ip2axi_rddata_captured_d1;
process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
ip2axi_rddata_captured_d1 <= ip2axi_rddata_captured;
end if;
end process ;
ip2axi_rddata_captured <= ip2axi_rddata_common_region when addr_region_1_common_rden_cmb = '1' or addr_region_2_common_rden_cmb = '1'
else mm2s_ip2axi_rddata when addr_region_mm2s_rden_cmb = '1'
else ip2axi_rddata_captured_s2mm_cdc_tig;
process(m_axi_s2mm_aclk)
begin
if(m_axi_s2mm_aclk'EVENT and m_axi_s2mm_aclk = '1')then
s2mm_ip2axi_rddata_d1 <= s2mm_ip2axi_rddata;
end if;
end process ;
GEN_LITE_S2MM_RDATA_CROSSING : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
ip2axi_rddata_captured_s2mm_cdc_tig <= s2mm_ip2axi_rddata_d1;
end if;
end process GEN_LITE_S2MM_RDATA_CROSSING;
mm2s_axi2ip_wrdata <= wdata;
GEN_LITE_S2MM_WDATA_CROSSING : process(m_axi_s2mm_aclk)
begin
if(m_axi_s2mm_aclk'EVENT and m_axi_s2mm_aclk = '1')then
s2mm_axi2ip_wrdata_cdc_tig <= wdata;
end if;
end process GEN_LITE_S2MM_WDATA_CROSSING;
s2mm_axi2ip_wrdata <= s2mm_axi2ip_wrdata_cdc_tig;
GEN_LITE_S2MM_RDADDR_CROSSING : process(m_axi_s2mm_aclk)
begin
if(m_axi_s2mm_aclk'EVENT and m_axi_s2mm_aclk = '1')then
axi2ip_rdaddr_captured_s2mm_cdc_tig(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
end if;
end process GEN_LITE_S2MM_RDADDR_CROSSING;
mm2s_axi2ip_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
s2mm_axi2ip_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured_s2mm_cdc_tig(7 downto 2);
GEN_LITE_S2MM_WRADDR_CROSSING : process(m_axi_s2mm_aclk)
begin
if(m_axi_s2mm_aclk'EVENT and m_axi_s2mm_aclk = '1')then
axi2ip_wraddr_captured_s2mm_cdc_tig(7 downto 2) <= axi2ip_wraddr_captured(7 downto 2);
end if;
end process GEN_LITE_S2MM_WRADDR_CROSSING;
mm2s_axi2ip_wrce <= (others => '0');
end generate GEN_S2MM_ONLY_ASYNC_LITE_ACCESS;
GEN_MM2S_ONLY_ASYNC_LITE_ACCESS : if C_MM2S_IS = 1 and C_S2MM_IS = 0 generate
--Write
prepare_wrce <= sig_wvalid_arrived and lite_wr_addr_phase_finished_data_phase_started;
GEN_WRCE_PULSE : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
prepare_wrce_d1 <= '0';
else
prepare_wrce_d1 <= prepare_wrce;
end if;
end if;
end process GEN_WRCE_PULSE;
prepare_wrce_pulse_lite <= prepare_wrce and not prepare_wrce_d1;
--MM2S
---- LITE_WVALID_MM2S_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => s_axi_lite_aclk ,
---- prmry_resetn => s_axi_lite_aresetn ,
---- scndry_aclk => m_axi_mm2s_aclk ,
---- scndry_resetn => mm2s_hrd_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => prepare_wrce_pulse_lite ,
---- scndry_out => prepare_wrce_pulse_mm2s ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
LITE_WVALID_MM2S_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => s_axi_lite_aresetn,
prmry_in => prepare_wrce_pulse_lite,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_mm2s_aclk,
scndry_resetn => mm2s_hrd_resetn,
scndry_out => prepare_wrce_pulse_mm2s,
scndry_vect_out => open
);
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
AXI4_LITE_WRCE_MM2S_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
mm2s_wrce_gen(j) <= prepare_wrce_pulse_mm2s when axi2ip_wraddr_captured_mm2s_cdc_tig
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate AXI4_LITE_WRCE_MM2S_GEN;
mm2s_axi2ip_wrce <= mm2s_wrce_gen;
GEN_LITE_WREADY_OUT_D : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
prepare_wrce_pulse_lite_d1 <= prepare_wrce_pulse_lite;
prepare_wrce_pulse_lite_d2 <= prepare_wrce_pulse_lite_d1;
prepare_wrce_pulse_lite_d3 <= prepare_wrce_pulse_lite_d2;
prepare_wrce_pulse_lite_d4 <= prepare_wrce_pulse_lite_d3;
prepare_wrce_pulse_lite_d5 <= prepare_wrce_pulse_lite_d4;
prepare_wrce_pulse_lite_d6 <= prepare_wrce_pulse_lite_d5;
end if;
end process GEN_LITE_WREADY_OUT_D;
GEN_LITE_WREADY_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
wready_out_i <= '0';
else
wready_out_i <= prepare_wrce_pulse_lite_d6;
end if;
end if;
end process GEN_LITE_WREADY_OUT;
wready_out_to_bvalid <= wready_out_i;
--Read
--MM2S
GEN_LITE_ARREADY_ASYNC_D : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
sig_arvalid_arrived_d2 <= sig_arvalid_arrived_d1;
sig_arvalid_arrived_d3 <= sig_arvalid_arrived_d2;
sig_arvalid_arrived_d4 <= sig_arvalid_arrived_d3;
end if;
end process GEN_LITE_ARREADY_ASYNC_D;
GEN_LITE_ARREADY_ASYNC : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_out_i <= '0';
else
arready_out_i <= sig_arvalid_arrived_d4;
end if;
end if;
end process GEN_LITE_ARREADY_ASYNC;
AXI4_LITE_RRESP_ASYNC_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
rvalid_out_i <= '0';
elsif(rvalid_out_i = '1' and s_axi_lite_rready = '1')then
rvalid_out_i <= '0';
elsif(arready_out_i = '1')then
rvalid_out_i <= '1';
end if;
end if;
end process AXI4_LITE_RRESP_ASYNC_PROCESS;
s_axi_lite_rdata <= ip2axi_rddata_captured_d1;
process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
ip2axi_rddata_captured_d1 <= ip2axi_rddata_captured;
end if;
end process ;
ip2axi_rddata_captured <= ip2axi_rddata_common_region when addr_region_1_common_rden_cmb = '1' or addr_region_2_common_rden_cmb = '1'
else ip2axi_rddata_captured_mm2s_cdc_tig when addr_region_mm2s_rden_cmb = '1'
else s2mm_ip2axi_rddata;
process(m_axi_mm2s_aclk)
begin
if(m_axi_mm2s_aclk'EVENT and m_axi_mm2s_aclk = '1')then
mm2s_ip2axi_rddata_d1 <= mm2s_ip2axi_rddata;
end if;
end process ;
GEN_LITE_MM2S_RDATA_CROSSING : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
ip2axi_rddata_captured_mm2s_cdc_tig <= mm2s_ip2axi_rddata_d1;
end if;
end process GEN_LITE_MM2S_RDATA_CROSSING;
GEN_LITE_MM2S_WDATA_CROSSING : process(m_axi_mm2s_aclk)
begin
if(m_axi_mm2s_aclk'EVENT and m_axi_mm2s_aclk = '1')then
mm2s_axi2ip_wrdata_cdc_tig <= wdata;
end if;
end process GEN_LITE_MM2S_WDATA_CROSSING;
s2mm_axi2ip_wrdata <= wdata;
mm2s_axi2ip_wrdata <= mm2s_axi2ip_wrdata_cdc_tig;
GEN_LITE_MM2S_RDADDR_CROSSING : process(m_axi_mm2s_aclk)
begin
if(m_axi_mm2s_aclk'EVENT and m_axi_mm2s_aclk = '1')then
axi2ip_rdaddr_captured_mm2s_cdc_tig(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
end if;
end process GEN_LITE_MM2S_RDADDR_CROSSING;
mm2s_axi2ip_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured_mm2s_cdc_tig(7 downto 2);
s2mm_axi2ip_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
GEN_LITE_MM2S_WRADDR_CROSSING : process(m_axi_mm2s_aclk)
begin
if(m_axi_mm2s_aclk'EVENT and m_axi_mm2s_aclk = '1')then
axi2ip_wraddr_captured_mm2s_cdc_tig(7 downto 2) <= axi2ip_wraddr_captured(7 downto 2);
end if;
end process GEN_LITE_MM2S_WRADDR_CROSSING;
s2mm_axi2ip_wrce <= (others => '0');
end generate GEN_MM2S_ONLY_ASYNC_LITE_ACCESS;
end generate GEN_LITE_IS_ASYNC;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_lite_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_lite_if.vhd
-- Description: This entity is AXI Lite Interface Module for the AXI DMA
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
library lib_cdc_v1_0;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_vdma_lite_if is
generic(
C_MM2S_IS : integer range 0 to 1 := 1;
-- Include or exclude MM2S channel
-- 0 = exclude mm2s channel
-- 1 = include mm2s channel
C_S2MM_IS : integer range 0 to 1 := 1;
-- Include or exclude S2MM channel
-- 0 = exclude s2mm channel
-- 1 = include s2mm channel
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 1;
-- Specifies the AXI Lite clock is asynchronous
-- 0 = AXI Clocks are Synchronous
-- 1 = AXI Clocks are Asynchronous
C_NUM_CE : integer := 8 ;
C_S_AXI_LITE_ADDR_WIDTH : integer range 9 to 9 := 9 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32
);
port (
----------------------------------------------------------------------- --
-- AXI Lite Control Interface --
----------------------------------------------------------------------- --
s_axi_lite_aclk : in std_logic ; --
s_axi_lite_aresetn : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
mm2s_hrd_resetn : in std_logic ; --
m_axi_s2mm_aclk : in std_logic ; --
s2mm_hrd_resetn : in std_logic ; --
--
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
axi2ip_lite_rdaddr : out std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
-- MM2S Reg Interface signals --
mm2s_axi2ip_wrdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_axi2ip_wrce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
mm2s_ip2axi_rddata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
mm2s_axi2ip_rdaddr : out std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
-- S2MM Reg Interface signals --
s2mm_axi2ip_wrdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_axi2ip_wrce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
s2mm_ip2axi_rddata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
s2mm_axi2ip_rdaddr : out std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
axi2ip_common_region_1_rden : out std_logic ; --
axi2ip_common_region_2_rden : out std_logic ; --
--
--
ip2axi_rddata_common_region : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) --
);
end axi_vdma_lite_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_lite_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Register I/F Address offset
constant ADDR_OFFSET : integer := clog2(C_S_AXI_LITE_DATA_WIDTH/8);
-- Register I/F CE number
constant CE_ADDR_SIZE : integer := clog2(C_NUM_CE);
constant ZERO_VALUE_VECT : std_logic_vector(128 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- AXI Lite slave interface signals
signal awvalid : std_logic := '0';
signal wvalid : std_logic := '0';
signal arvalid : std_logic := '0';
signal awaddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal wdata : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal araddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_ip2axi_rddata_d1 : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal s2mm_ip2axi_rddata_d1 : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal write_response_accepted : std_logic := '0';
signal write_has_started : std_logic := '0';
signal awready_out_i : std_logic := '0';
signal wready_out_i : std_logic := '0';
signal wrce_gen : std_logic_vector(C_NUM_CE-1 downto 0);
signal bvalid_out_i : std_logic := '0';
signal read_data_res_accepted : std_logic := '0';
signal read_has_started_i : std_logic := '0';
signal sig_arvalid_arrived : std_logic := '0';
signal sig_arvalid_arrived_d1 : std_logic := '0';
signal sig_arvalid_arrived_d2 : std_logic := '0';
signal sig_arvalid_arrived_d3 : std_logic := '0';
signal sig_arvalid_arrived_d4 : std_logic := '0';
signal sig_arvalid_detected : std_logic := '0';
signal arready_out_i_cmb : std_logic := '0';
signal arready_out_i : std_logic := '0';
signal arready_out_i_mm2s : std_logic := '0';
signal arready_out_i_s2mm : std_logic := '0';
signal arready_out_i_common : std_logic := '0';
signal rvalid_out_i : std_logic := '0';
----Async_mode
signal wready_out_to_bvalid : std_logic := '0';
signal mm2s_wrce_gen : std_logic_vector(C_NUM_CE-1 downto 0);
signal s2mm_wrce_gen : std_logic_vector(C_NUM_CE-1 downto 0);
signal addr_region_mm2s_rden_cmb : std_logic := '0';
signal addr_region_s2mm_rden_cmb : std_logic := '0';
signal addr_region_1_common_rden_cmb : std_logic := '0';
signal addr_region_2_common_rden_cmb : std_logic := '0';
signal ip2axi_rddata_captured : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
signal ip2axi_rddata_captured_d1 : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
signal ip2axi_rddata_captured_mm2s_cdc_tig : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
signal ip2axi_rddata_captured_s2mm_cdc_tig : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
signal axi2ip_rdaddr_captured : std_logic_vector(7 downto 2) := (others => '0'); --
--signal axi2ip_rdaddr_captured_mm2s_cdc_tig : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
--signal axi2ip_rdaddr_captured_s2mm_cdc_tig : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
signal axi2ip_rdaddr_captured_mm2s_cdc_tig : std_logic_vector(7 downto 2) := (others => '0'); --
signal axi2ip_rdaddr_captured_s2mm_cdc_tig : std_logic_vector(7 downto 2) := (others => '0'); --
signal axi2ip_wraddr_captured : std_logic_vector(7 downto 2) := (others => '0'); --
--signal axi2ip_wraddr_captured_mm2s_cdc_tig : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
--signal axi2ip_wraddr_captured_s2mm_cdc_tig : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
signal axi2ip_wraddr_captured_mm2s_cdc_tig : std_logic_vector(7 downto 2) := (others => '0'); --
signal axi2ip_wraddr_captured_s2mm_cdc_tig : std_logic_vector(7 downto 2) := (others => '0'); --
signal arready_out_i_d1 : std_logic := '0';
signal sig_awvalid_arrived_d1 : std_logic := '0';
signal sig_awvalid_arrived : std_logic := '0';
signal sig_awvalid_detected : std_logic := '0';
signal sig_wvalid_arrived : std_logic := '0';
signal lite_wr_addr_phase_finished_data_phase_started : std_logic := '0';
signal prepare_wrce : std_logic := '0';
signal prepare_wrce_d1 : std_logic := '0';
signal prepare_wrce_pulse_lite : std_logic := '0';
signal prepare_wrce_pulse_lite_d1 : std_logic := '0';
signal prepare_wrce_pulse_lite_d2 : std_logic := '0';
signal prepare_wrce_pulse_lite_d3 : std_logic := '0';
signal prepare_wrce_pulse_lite_d4 : std_logic := '0';
signal prepare_wrce_pulse_lite_d5 : std_logic := '0';
signal prepare_wrce_pulse_lite_d6 : std_logic := '0';
signal prepare_wrce_pulse_mm2s : std_logic := '0';
signal prepare_wrce_pulse_s2mm : std_logic := '0';
signal wready_mm2s : std_logic := '0';
signal wready_s2mm : std_logic := '0';
signal lite_mm2s_wr_done : std_logic := '0';
signal lite_s2mm_wr_done : std_logic := '0';
signal lite_wr_done : std_logic := '0';
signal lite_wr_done_d1 : std_logic := '0';
signal sig_arvalid_arrived_d1_mm2s_rd_lite_domain : std_logic := '0';
signal sig_arvalid_arrived_d1_mm2s : std_logic := '0';
signal sig_arvalid_arrived_d1_s2mm_rd_lite_domain : std_logic := '0';
signal sig_arvalid_arrived_d1_s2mm : std_logic := '0';
signal mm2s_axi2ip_wrdata_cdc_tig : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
signal s2mm_axi2ip_wrdata_cdc_tig : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF ip2axi_rddata_captured_mm2s_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF ip2axi_rddata_captured_s2mm_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF axi2ip_rdaddr_captured_mm2s_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF axi2ip_rdaddr_captured_s2mm_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF axi2ip_wraddr_captured_mm2s_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF axi2ip_wraddr_captured_s2mm_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF mm2s_axi2ip_wrdata_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF s2mm_axi2ip_wrdata_cdc_tig : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
s_axi_lite_awready <= awready_out_i;
s_axi_lite_wready <= wready_out_i;
s_axi_lite_bvalid <= bvalid_out_i;
s_axi_lite_arready <= arready_out_i;
s_axi_lite_rvalid <= rvalid_out_i;
axi2ip_lite_rdaddr(8) <= '0';
axi2ip_lite_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
axi2ip_lite_rdaddr(1) <= '0';
axi2ip_lite_rdaddr(0) <= '0';
mm2s_axi2ip_rdaddr(8) <= '0';
mm2s_axi2ip_rdaddr(1) <= '0';
mm2s_axi2ip_rdaddr(0) <= '0';
s2mm_axi2ip_rdaddr(8) <= '0';
s2mm_axi2ip_rdaddr(1) <= '0';
s2mm_axi2ip_rdaddr(0) <= '0';
s_axi_lite_bresp <= OKAY_RESP;
s_axi_lite_rresp <= OKAY_RESP;
-------------------------------------------------------------------------------------------------
--------------------------- Register AXI4-LITE Control signals ----------------------------------
-------------------------------------------------------------------------------------------------
REG_INPUTS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
awvalid <= '0' ;
wvalid <= '0' ;
arvalid <= '0' ;
awaddr <= (others => '0') ;
wdata <= (others => '0') ;
araddr <= (others => '0') ;
else
awvalid <= s_axi_lite_awvalid ;
wvalid <= s_axi_lite_wvalid ;
arvalid <= s_axi_lite_arvalid ;
awaddr <= s_axi_lite_awaddr ;
wdata <= s_axi_lite_wdata ;
araddr <= s_axi_lite_araddr ;
end if;
end if;
end process REG_INPUTS;
-------------------------------------------------------------------------------
-------------------------------AXI4-LITE WRITE---------------------------------
-------------------------------------------------------------------------------
sig_awvalid_arrived <= awvalid;
sig_wvalid_arrived <= wvalid;
D1_LITE_WR_ADDR_PHASE_DETECT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or write_has_started = '1')then
sig_awvalid_arrived_d1 <= '0';
else
sig_awvalid_arrived_d1 <= sig_awvalid_arrived;
end if;
end if;
end process D1_LITE_WR_ADDR_PHASE_DETECT;
AXI4_LITE_WR_STARTED : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or write_response_accepted = '1')then
write_has_started <= '0';
elsif(sig_awvalid_detected = '1')then
write_has_started <= '1';
end if;
end if;
end process AXI4_LITE_WR_STARTED;
sig_awvalid_detected <= sig_awvalid_arrived and not (sig_awvalid_arrived_d1) and not (write_has_started);
--axi2ip_wraddr_captured <= awaddr when sig_awvalid_detected = '1';
CAPTURE_AWADDR : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_wraddr_captured(7 downto 2) <= (others => '0');
elsif(sig_awvalid_detected = '1')then
axi2ip_wraddr_captured(7 downto 2) <= awaddr(7 downto 2);
end if;
end if;
end process CAPTURE_AWADDR;
GEN_LITE_AWREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
awready_out_i <= '0';
else
awready_out_i <= sig_awvalid_detected;
end if;
end if;
end process GEN_LITE_AWREADY;
GEN_WR_ADDR_PHASE_TO_DATA_PHASE : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or wready_out_i = '1')then
lite_wr_addr_phase_finished_data_phase_started <= '0';
elsif(awready_out_i = '1')then
lite_wr_addr_phase_finished_data_phase_started <= '1';
end if;
end if;
end process GEN_WR_ADDR_PHASE_TO_DATA_PHASE;
--------------------------------------------------------------------------------------------------
--***** SYNC_MODE
--------------------------------------------------------------------------------------------------
GEN_LITE_IS_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
prepare_wrce <= sig_wvalid_arrived and lite_wr_addr_phase_finished_data_phase_started;
GEN_WRCE_PULSE : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
prepare_wrce_d1 <= '0';
else
prepare_wrce_d1 <= prepare_wrce;
end if;
end if;
end process GEN_WRCE_PULSE;
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
AXI4_LITE_WRCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
wrce_gen(j) <= (prepare_wrce and not prepare_wrce_d1) when axi2ip_wraddr_captured
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate AXI4_LITE_WRCE_GEN;
mm2s_axi2ip_wrce <= wrce_gen;
s2mm_axi2ip_wrce <= wrce_gen;
GEN_LITE_WREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
wready_out_i <= '0';
else
wready_out_i <= (prepare_wrce and not prepare_wrce_d1);
end if;
end if;
end process GEN_LITE_WREADY;
wready_out_to_bvalid <= wready_out_i;
-------------------------
--*READ
-------------------------
GEN_LITE_ARREADY_SYNC : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_out_i <= '0';
else
arready_out_i <= sig_arvalid_arrived_d1;
end if;
end if;
end process GEN_LITE_ARREADY_SYNC;
s_axi_lite_rdata <= ip2axi_rddata_captured_d1;
process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
ip2axi_rddata_captured_d1 <= ip2axi_rddata_captured;
end if;
end process ;
ip2axi_rddata_captured <= ip2axi_rddata_common_region when addr_region_1_common_rden_cmb = '1' or addr_region_2_common_rden_cmb = '1'
else mm2s_ip2axi_rddata when addr_region_mm2s_rden_cmb = '1'
else s2mm_ip2axi_rddata;
AXI4_LITE_RRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
rvalid_out_i <= '0';
elsif(rvalid_out_i = '1' and s_axi_lite_rready = '1')then
rvalid_out_i <= '0';
elsif(arready_out_i = '1')then
rvalid_out_i <= '1';
end if;
end if;
end process AXI4_LITE_RRESP_PROCESS;
-------------------------
--*READ
-------------------------
mm2s_axi2ip_wrdata <= wdata;
s2mm_axi2ip_wrdata <= wdata;
mm2s_axi2ip_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
s2mm_axi2ip_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
end generate GEN_LITE_IS_SYNC;
--------------------------------------------------------------------------------------------------
--***** SYNC_MODE
--------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------AXI4-LITE READ----------------------------------
-------------------------------------------------------------------------------
sig_arvalid_arrived <= arvalid;
D1_LITE_RD_DETECT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or read_has_started_i = '1')then
sig_arvalid_arrived_d1 <= '0';
else
sig_arvalid_arrived_d1 <= sig_arvalid_arrived;
end if;
end if;
end process D1_LITE_RD_DETECT;
AXI4_LITE_RD_STARTED : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or read_data_res_accepted = '1')then
read_has_started_i <= '0';
elsif(sig_arvalid_detected = '1')then
read_has_started_i <= '1';
end if;
end if;
end process AXI4_LITE_RD_STARTED;
sig_arvalid_detected <= sig_arvalid_arrived and not (sig_arvalid_arrived_d1) and not (read_has_started_i);
read_data_res_accepted <= rvalid_out_i and s_axi_lite_rready;
CAPTURE_ARADDR : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_rdaddr_captured(7 downto 2) <= (others => '0');
elsif(sig_arvalid_detected = '1')then
axi2ip_rdaddr_captured(7 downto 2) <= araddr(7 downto 2);
end if;
end if;
end process CAPTURE_ARADDR;
-------------------------------------------------------------------------------
-- Decode read_lite_addr MSB to get the region of read access
-------------------------------------------------------------------------------
--*****************************************************************************
-- MM2S_Region_1 (0x00 to 0x1C)
-- MM2S_Region_2 (0x50 to 0x9C)
-- S2MM_Region_1 (0x30 to 0x3C)
-- S2MM_Region_2 (0xA0 to 0xEC)
-- Common_Region_1 (0x20 to 0x2C) (common read only register)
-- Common_Region_2 (0xF0 to 0xFC) (s2mm read-only registers)
--*****************************************************************************
addr_region_1_common_rden_cmb <= ((not axi2ip_rdaddr_captured(7)) and (not axi2ip_rdaddr_captured(6)) and (axi2ip_rdaddr_captured(5)) and (not axi2ip_rdaddr_captured(4)));
addr_region_2_common_rden_cmb <= (axi2ip_rdaddr_captured(7) and axi2ip_rdaddr_captured(6) and axi2ip_rdaddr_captured(5) and axi2ip_rdaddr_captured(4));
--MM2S Region read
addr_region_mm2s_rden_cmb <= (((not axi2ip_rdaddr_captured(6)) and (not axi2ip_rdaddr_captured(5)))
or
((not axi2ip_rdaddr_captured(7)) and (not axi2ip_rdaddr_captured(5)) and (axi2ip_rdaddr_captured(4)))
or
((not axi2ip_rdaddr_captured(7)) and (axi2ip_rdaddr_captured(6)) and (axi2ip_rdaddr_captured(5))))
;
--S2MM Region read
addr_region_s2mm_rden_cmb <= (((axi2ip_rdaddr_captured(7)) and (axi2ip_rdaddr_captured(5)) and (not axi2ip_rdaddr_captured(4)))
or
((not axi2ip_rdaddr_captured(6)) and (axi2ip_rdaddr_captured(5)) and (axi2ip_rdaddr_captured(4)))
or
((axi2ip_rdaddr_captured(6)) and (not axi2ip_rdaddr_captured(5)) and (not axi2ip_rdaddr_captured(4)))
or
((axi2ip_rdaddr_captured(7)) and (axi2ip_rdaddr_captured(6)) and (not axi2ip_rdaddr_captured(5))));
-------------------------------------------------------------------------------
-- Write Response
-------------------------------------------------------------------------------
AXI4_LITE_WRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
bvalid_out_i <= '0';
elsif(bvalid_out_i = '1' and s_axi_lite_bready = '1')then
bvalid_out_i <= '0';
elsif(wready_out_to_bvalid = '1')then
bvalid_out_i <= '1';
end if;
end if;
end process AXI4_LITE_WRESP_PROCESS;
write_response_accepted <= bvalid_out_i and s_axi_lite_bready;
axi2ip_common_region_1_rden <= addr_region_1_common_rden_cmb;
GEN_S2MM_COM_REG2_READ : if C_S2MM_IS = 1 generate
axi2ip_common_region_2_rden <= addr_region_2_common_rden_cmb;
end generate GEN_S2MM_COM_REG2_READ;
GEN_NO_S2MM_COM_REG2_READ : if C_S2MM_IS = 0 generate
axi2ip_common_region_2_rden <= '0';
end generate GEN_NO_S2MM_COM_REG2_READ;
--------------------------------------------------------------------------------------------------
--***** ASYNC_MODE
--------------------------------------------------------------------------------------------------
GEN_LITE_IS_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
--Both channels exist and async mode
GEN_ASYNC_LITE_ACCESS : if C_MM2S_IS = 1 and C_S2MM_IS = 1 generate
prepare_wrce <= sig_wvalid_arrived and lite_wr_addr_phase_finished_data_phase_started;
GEN_WRCE_PULSE : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
prepare_wrce_d1 <= '0';
else
prepare_wrce_d1 <= prepare_wrce;
end if;
end if;
end process GEN_WRCE_PULSE;
prepare_wrce_pulse_lite <= prepare_wrce and not prepare_wrce_d1;
--MM2S
----
---- LITE_WVALID_MM2S_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => s_axi_lite_aclk ,
---- prmry_resetn => s_axi_lite_aresetn ,
---- scndry_aclk => m_axi_mm2s_aclk ,
---- scndry_resetn => mm2s_hrd_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => prepare_wrce_pulse_lite ,
---- scndry_out => prepare_wrce_pulse_mm2s ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
LITE_WVALID_MM2S_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => s_axi_lite_aresetn,
prmry_in => prepare_wrce_pulse_lite,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_mm2s_aclk,
scndry_resetn => mm2s_hrd_resetn,
scndry_out => prepare_wrce_pulse_mm2s,
scndry_vect_out => open
);
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
AXI4_LITE_WRCE_MM2S_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
mm2s_wrce_gen(j) <= prepare_wrce_pulse_mm2s when axi2ip_wraddr_captured_mm2s_cdc_tig
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate AXI4_LITE_WRCE_MM2S_GEN;
mm2s_axi2ip_wrce <= mm2s_wrce_gen;
--S2MM
---- LITE_WVALID_S2MM_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => s_axi_lite_aclk ,
---- prmry_resetn => s_axi_lite_aresetn ,
---- scndry_aclk => m_axi_s2mm_aclk ,
---- scndry_resetn => s2mm_hrd_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => prepare_wrce_pulse_lite ,
---- scndry_out => prepare_wrce_pulse_s2mm ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
LITE_WVALID_S2MM_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => s_axi_lite_aresetn,
prmry_in => prepare_wrce_pulse_lite,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_s2mm_aclk,
scndry_resetn => s2mm_hrd_resetn,
scndry_out => prepare_wrce_pulse_s2mm,
scndry_vect_out => open
);
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
AXI4_LITE_WRCE_S2MM_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
s2mm_wrce_gen(j) <= prepare_wrce_pulse_s2mm when axi2ip_wraddr_captured_s2mm_cdc_tig
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate AXI4_LITE_WRCE_S2MM_GEN;
s2mm_axi2ip_wrce <= s2mm_wrce_gen;
GEN_LITE_WREADY_OUT_D : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
prepare_wrce_pulse_lite_d1 <= prepare_wrce_pulse_lite;
prepare_wrce_pulse_lite_d2 <= prepare_wrce_pulse_lite_d1;
prepare_wrce_pulse_lite_d3 <= prepare_wrce_pulse_lite_d2;
prepare_wrce_pulse_lite_d4 <= prepare_wrce_pulse_lite_d3;
prepare_wrce_pulse_lite_d5 <= prepare_wrce_pulse_lite_d4;
prepare_wrce_pulse_lite_d6 <= prepare_wrce_pulse_lite_d5;
end if;
end process GEN_LITE_WREADY_OUT_D;
GEN_LITE_WREADY_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
wready_out_i <= '0';
else
wready_out_i <= prepare_wrce_pulse_lite_d6;
end if;
end if;
end process GEN_LITE_WREADY_OUT;
wready_out_to_bvalid <= wready_out_i;
-------------------------
--*READ
-------------------------
--MM2S
GEN_LITE_ARREADY_ASYNC_D : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
sig_arvalid_arrived_d2 <= sig_arvalid_arrived_d1;
sig_arvalid_arrived_d3 <= sig_arvalid_arrived_d2;
sig_arvalid_arrived_d4 <= sig_arvalid_arrived_d3;
end if;
end process GEN_LITE_ARREADY_ASYNC_D;
GEN_LITE_ARREADY_ASYNC : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_out_i <= '0';
else
arready_out_i <= sig_arvalid_arrived_d4;
end if;
end if;
end process GEN_LITE_ARREADY_ASYNC;
AXI4_LITE_RRESP_ASYNC_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
rvalid_out_i <= '0';
elsif(rvalid_out_i = '1' and s_axi_lite_rready = '1')then
rvalid_out_i <= '0';
elsif(arready_out_i = '1')then
rvalid_out_i <= '1';
end if;
end if;
end process AXI4_LITE_RRESP_ASYNC_PROCESS;
s_axi_lite_rdata <= ip2axi_rddata_captured_d1;
process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
ip2axi_rddata_captured_d1 <= ip2axi_rddata_captured;
end if;
end process ;
ip2axi_rddata_captured <= ip2axi_rddata_common_region when addr_region_1_common_rden_cmb = '1' or addr_region_2_common_rden_cmb = '1'
else ip2axi_rddata_captured_mm2s_cdc_tig when addr_region_mm2s_rden_cmb = '1'
else ip2axi_rddata_captured_s2mm_cdc_tig;
process(m_axi_mm2s_aclk)
begin
if(m_axi_mm2s_aclk'EVENT and m_axi_mm2s_aclk = '1')then
mm2s_ip2axi_rddata_d1 <= mm2s_ip2axi_rddata;
end if;
end process ;
GEN_LITE_MM2S_RDATA_CROSSING : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
ip2axi_rddata_captured_mm2s_cdc_tig <= mm2s_ip2axi_rddata_d1;
end if;
end process GEN_LITE_MM2S_RDATA_CROSSING;
process(m_axi_s2mm_aclk)
begin
if(m_axi_s2mm_aclk'EVENT and m_axi_s2mm_aclk = '1')then
s2mm_ip2axi_rddata_d1 <= s2mm_ip2axi_rddata;
end if;
end process ;
GEN_LITE_S2MM_RDATA_CROSSING : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
ip2axi_rddata_captured_s2mm_cdc_tig <= s2mm_ip2axi_rddata_d1;
end if;
end process GEN_LITE_S2MM_RDATA_CROSSING;
GEN_LITE_MM2S_WDATA_CROSSING : process(m_axi_mm2s_aclk)
begin
if(m_axi_mm2s_aclk'EVENT and m_axi_mm2s_aclk = '1')then
mm2s_axi2ip_wrdata_cdc_tig <= wdata;
end if;
end process GEN_LITE_MM2S_WDATA_CROSSING;
GEN_LITE_S2MM_WDATA_CROSSING : process(m_axi_s2mm_aclk)
begin
if(m_axi_s2mm_aclk'EVENT and m_axi_s2mm_aclk = '1')then
s2mm_axi2ip_wrdata_cdc_tig <= wdata;
end if;
end process GEN_LITE_S2MM_WDATA_CROSSING;
mm2s_axi2ip_wrdata <= mm2s_axi2ip_wrdata_cdc_tig;
s2mm_axi2ip_wrdata <= s2mm_axi2ip_wrdata_cdc_tig;
GEN_LITE_MM2S_RDADDR_CROSSING : process(m_axi_mm2s_aclk)
begin
if(m_axi_mm2s_aclk'EVENT and m_axi_mm2s_aclk = '1')then
axi2ip_rdaddr_captured_mm2s_cdc_tig(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
end if;
end process GEN_LITE_MM2S_RDADDR_CROSSING;
GEN_LITE_S2MM_RDADDR_CROSSING : process(m_axi_s2mm_aclk)
begin
if(m_axi_s2mm_aclk'EVENT and m_axi_s2mm_aclk = '1')then
axi2ip_rdaddr_captured_s2mm_cdc_tig(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
end if;
end process GEN_LITE_S2MM_RDADDR_CROSSING;
mm2s_axi2ip_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured_mm2s_cdc_tig(7 downto 2);
s2mm_axi2ip_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured_s2mm_cdc_tig(7 downto 2);
GEN_LITE_MM2S_WRADDR_CROSSING : process(m_axi_mm2s_aclk)
begin
if(m_axi_mm2s_aclk'EVENT and m_axi_mm2s_aclk = '1')then
axi2ip_wraddr_captured_mm2s_cdc_tig(7 downto 2) <= axi2ip_wraddr_captured(7 downto 2);
end if;
end process GEN_LITE_MM2S_WRADDR_CROSSING;
GEN_LITE_S2MM_WRADDR_CROSSING : process(m_axi_s2mm_aclk)
begin
if(m_axi_s2mm_aclk'EVENT and m_axi_s2mm_aclk = '1')then
axi2ip_wraddr_captured_s2mm_cdc_tig(7 downto 2) <= axi2ip_wraddr_captured(7 downto 2);
end if;
end process GEN_LITE_S2MM_WRADDR_CROSSING;
end generate GEN_ASYNC_LITE_ACCESS;
--------------------------------------------
--ASYNC_MODE but only single channel enabled
--------------------------------------------
GEN_S2MM_ONLY_ASYNC_LITE_ACCESS : if C_MM2S_IS = 0 and C_S2MM_IS = 1 generate
--Write
prepare_wrce <= sig_wvalid_arrived and lite_wr_addr_phase_finished_data_phase_started;
GEN_WRCE_PULSE : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
prepare_wrce_d1 <= '0';
else
prepare_wrce_d1 <= prepare_wrce;
end if;
end if;
end process GEN_WRCE_PULSE;
prepare_wrce_pulse_lite <= prepare_wrce and not prepare_wrce_d1;
--S2MM
---- LITE_WVALID_S2MM_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => s_axi_lite_aclk ,
---- prmry_resetn => s_axi_lite_aresetn ,
---- scndry_aclk => m_axi_s2mm_aclk ,
---- scndry_resetn => s2mm_hrd_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => prepare_wrce_pulse_lite ,
---- scndry_out => prepare_wrce_pulse_s2mm ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
LITE_WVALID_S2MM_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => s_axi_lite_aresetn,
prmry_in => prepare_wrce_pulse_lite,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_s2mm_aclk,
scndry_resetn => s2mm_hrd_resetn,
scndry_out => prepare_wrce_pulse_s2mm,
scndry_vect_out => open
);
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
AXI4_LITE_WRCE_S2MM_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
s2mm_wrce_gen(j) <= prepare_wrce_pulse_s2mm when axi2ip_wraddr_captured_s2mm_cdc_tig
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate AXI4_LITE_WRCE_S2MM_GEN;
s2mm_axi2ip_wrce <= s2mm_wrce_gen;
GEN_LITE_WREADY_OUT_D : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
prepare_wrce_pulse_lite_d1 <= prepare_wrce_pulse_lite;
prepare_wrce_pulse_lite_d2 <= prepare_wrce_pulse_lite_d1;
prepare_wrce_pulse_lite_d3 <= prepare_wrce_pulse_lite_d2;
prepare_wrce_pulse_lite_d4 <= prepare_wrce_pulse_lite_d3;
prepare_wrce_pulse_lite_d5 <= prepare_wrce_pulse_lite_d4;
prepare_wrce_pulse_lite_d6 <= prepare_wrce_pulse_lite_d5;
end if;
end process GEN_LITE_WREADY_OUT_D;
GEN_LITE_WREADY_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
wready_out_i <= '0';
else
wready_out_i <= prepare_wrce_pulse_lite_d6;
end if;
end if;
end process GEN_LITE_WREADY_OUT;
wready_out_to_bvalid <= wready_out_i;
--Read
--S2MM
GEN_LITE_ARREADY_ASYNC_D : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
sig_arvalid_arrived_d2 <= sig_arvalid_arrived_d1;
sig_arvalid_arrived_d3 <= sig_arvalid_arrived_d2;
sig_arvalid_arrived_d4 <= sig_arvalid_arrived_d3;
end if;
end process GEN_LITE_ARREADY_ASYNC_D;
GEN_LITE_ARREADY_ASYNC : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_out_i <= '0';
else
arready_out_i <= sig_arvalid_arrived_d4;
end if;
end if;
end process GEN_LITE_ARREADY_ASYNC;
AXI4_LITE_RRESP_ASYNC_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
rvalid_out_i <= '0';
elsif(rvalid_out_i = '1' and s_axi_lite_rready = '1')then
rvalid_out_i <= '0';
elsif(arready_out_i = '1')then
rvalid_out_i <= '1';
end if;
end if;
end process AXI4_LITE_RRESP_ASYNC_PROCESS;
s_axi_lite_rdata <= ip2axi_rddata_captured_d1;
process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
ip2axi_rddata_captured_d1 <= ip2axi_rddata_captured;
end if;
end process ;
ip2axi_rddata_captured <= ip2axi_rddata_common_region when addr_region_1_common_rden_cmb = '1' or addr_region_2_common_rden_cmb = '1'
else mm2s_ip2axi_rddata when addr_region_mm2s_rden_cmb = '1'
else ip2axi_rddata_captured_s2mm_cdc_tig;
process(m_axi_s2mm_aclk)
begin
if(m_axi_s2mm_aclk'EVENT and m_axi_s2mm_aclk = '1')then
s2mm_ip2axi_rddata_d1 <= s2mm_ip2axi_rddata;
end if;
end process ;
GEN_LITE_S2MM_RDATA_CROSSING : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
ip2axi_rddata_captured_s2mm_cdc_tig <= s2mm_ip2axi_rddata_d1;
end if;
end process GEN_LITE_S2MM_RDATA_CROSSING;
mm2s_axi2ip_wrdata <= wdata;
GEN_LITE_S2MM_WDATA_CROSSING : process(m_axi_s2mm_aclk)
begin
if(m_axi_s2mm_aclk'EVENT and m_axi_s2mm_aclk = '1')then
s2mm_axi2ip_wrdata_cdc_tig <= wdata;
end if;
end process GEN_LITE_S2MM_WDATA_CROSSING;
s2mm_axi2ip_wrdata <= s2mm_axi2ip_wrdata_cdc_tig;
GEN_LITE_S2MM_RDADDR_CROSSING : process(m_axi_s2mm_aclk)
begin
if(m_axi_s2mm_aclk'EVENT and m_axi_s2mm_aclk = '1')then
axi2ip_rdaddr_captured_s2mm_cdc_tig(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
end if;
end process GEN_LITE_S2MM_RDADDR_CROSSING;
mm2s_axi2ip_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
s2mm_axi2ip_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured_s2mm_cdc_tig(7 downto 2);
GEN_LITE_S2MM_WRADDR_CROSSING : process(m_axi_s2mm_aclk)
begin
if(m_axi_s2mm_aclk'EVENT and m_axi_s2mm_aclk = '1')then
axi2ip_wraddr_captured_s2mm_cdc_tig(7 downto 2) <= axi2ip_wraddr_captured(7 downto 2);
end if;
end process GEN_LITE_S2MM_WRADDR_CROSSING;
mm2s_axi2ip_wrce <= (others => '0');
end generate GEN_S2MM_ONLY_ASYNC_LITE_ACCESS;
GEN_MM2S_ONLY_ASYNC_LITE_ACCESS : if C_MM2S_IS = 1 and C_S2MM_IS = 0 generate
--Write
prepare_wrce <= sig_wvalid_arrived and lite_wr_addr_phase_finished_data_phase_started;
GEN_WRCE_PULSE : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
prepare_wrce_d1 <= '0';
else
prepare_wrce_d1 <= prepare_wrce;
end if;
end if;
end process GEN_WRCE_PULSE;
prepare_wrce_pulse_lite <= prepare_wrce and not prepare_wrce_d1;
--MM2S
---- LITE_WVALID_MM2S_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => s_axi_lite_aclk ,
---- prmry_resetn => s_axi_lite_aresetn ,
---- scndry_aclk => m_axi_mm2s_aclk ,
---- scndry_resetn => mm2s_hrd_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => prepare_wrce_pulse_lite ,
---- scndry_out => prepare_wrce_pulse_mm2s ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
LITE_WVALID_MM2S_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => s_axi_lite_aresetn,
prmry_in => prepare_wrce_pulse_lite,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_mm2s_aclk,
scndry_resetn => mm2s_hrd_resetn,
scndry_out => prepare_wrce_pulse_mm2s,
scndry_vect_out => open
);
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
AXI4_LITE_WRCE_MM2S_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
mm2s_wrce_gen(j) <= prepare_wrce_pulse_mm2s when axi2ip_wraddr_captured_mm2s_cdc_tig
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate AXI4_LITE_WRCE_MM2S_GEN;
mm2s_axi2ip_wrce <= mm2s_wrce_gen;
GEN_LITE_WREADY_OUT_D : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
prepare_wrce_pulse_lite_d1 <= prepare_wrce_pulse_lite;
prepare_wrce_pulse_lite_d2 <= prepare_wrce_pulse_lite_d1;
prepare_wrce_pulse_lite_d3 <= prepare_wrce_pulse_lite_d2;
prepare_wrce_pulse_lite_d4 <= prepare_wrce_pulse_lite_d3;
prepare_wrce_pulse_lite_d5 <= prepare_wrce_pulse_lite_d4;
prepare_wrce_pulse_lite_d6 <= prepare_wrce_pulse_lite_d5;
end if;
end process GEN_LITE_WREADY_OUT_D;
GEN_LITE_WREADY_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
wready_out_i <= '0';
else
wready_out_i <= prepare_wrce_pulse_lite_d6;
end if;
end if;
end process GEN_LITE_WREADY_OUT;
wready_out_to_bvalid <= wready_out_i;
--Read
--MM2S
GEN_LITE_ARREADY_ASYNC_D : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
sig_arvalid_arrived_d2 <= sig_arvalid_arrived_d1;
sig_arvalid_arrived_d3 <= sig_arvalid_arrived_d2;
sig_arvalid_arrived_d4 <= sig_arvalid_arrived_d3;
end if;
end process GEN_LITE_ARREADY_ASYNC_D;
GEN_LITE_ARREADY_ASYNC : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_out_i <= '0';
else
arready_out_i <= sig_arvalid_arrived_d4;
end if;
end if;
end process GEN_LITE_ARREADY_ASYNC;
AXI4_LITE_RRESP_ASYNC_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
rvalid_out_i <= '0';
elsif(rvalid_out_i = '1' and s_axi_lite_rready = '1')then
rvalid_out_i <= '0';
elsif(arready_out_i = '1')then
rvalid_out_i <= '1';
end if;
end if;
end process AXI4_LITE_RRESP_ASYNC_PROCESS;
s_axi_lite_rdata <= ip2axi_rddata_captured_d1;
process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
ip2axi_rddata_captured_d1 <= ip2axi_rddata_captured;
end if;
end process ;
ip2axi_rddata_captured <= ip2axi_rddata_common_region when addr_region_1_common_rden_cmb = '1' or addr_region_2_common_rden_cmb = '1'
else ip2axi_rddata_captured_mm2s_cdc_tig when addr_region_mm2s_rden_cmb = '1'
else s2mm_ip2axi_rddata;
process(m_axi_mm2s_aclk)
begin
if(m_axi_mm2s_aclk'EVENT and m_axi_mm2s_aclk = '1')then
mm2s_ip2axi_rddata_d1 <= mm2s_ip2axi_rddata;
end if;
end process ;
GEN_LITE_MM2S_RDATA_CROSSING : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
ip2axi_rddata_captured_mm2s_cdc_tig <= mm2s_ip2axi_rddata_d1;
end if;
end process GEN_LITE_MM2S_RDATA_CROSSING;
GEN_LITE_MM2S_WDATA_CROSSING : process(m_axi_mm2s_aclk)
begin
if(m_axi_mm2s_aclk'EVENT and m_axi_mm2s_aclk = '1')then
mm2s_axi2ip_wrdata_cdc_tig <= wdata;
end if;
end process GEN_LITE_MM2S_WDATA_CROSSING;
s2mm_axi2ip_wrdata <= wdata;
mm2s_axi2ip_wrdata <= mm2s_axi2ip_wrdata_cdc_tig;
GEN_LITE_MM2S_RDADDR_CROSSING : process(m_axi_mm2s_aclk)
begin
if(m_axi_mm2s_aclk'EVENT and m_axi_mm2s_aclk = '1')then
axi2ip_rdaddr_captured_mm2s_cdc_tig(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
end if;
end process GEN_LITE_MM2S_RDADDR_CROSSING;
mm2s_axi2ip_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured_mm2s_cdc_tig(7 downto 2);
s2mm_axi2ip_rdaddr(7 downto 2) <= axi2ip_rdaddr_captured(7 downto 2);
GEN_LITE_MM2S_WRADDR_CROSSING : process(m_axi_mm2s_aclk)
begin
if(m_axi_mm2s_aclk'EVENT and m_axi_mm2s_aclk = '1')then
axi2ip_wraddr_captured_mm2s_cdc_tig(7 downto 2) <= axi2ip_wraddr_captured(7 downto 2);
end if;
end process GEN_LITE_MM2S_WRADDR_CROSSING;
s2mm_axi2ip_wrce <= (others => '0');
end generate GEN_MM2S_ONLY_ASYNC_LITE_ACCESS;
end generate GEN_LITE_IS_ASYNC;
end implementation;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 17/08/2015
--! Module Name: FIFO2Elink
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
--! Use standard library
library work, ieee, std;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.all;
use work.centralRouter_package.all;
use work.elinkInterface_package.all;
use ieee.std_logic_textio.all;
use std.textio.all;
--! consists of 1 E-path
entity elinkInterface_top is
port (
clk_200_in_n : in std_logic;
clk_200_in_p : in std_logic;
sys_reset_n : in std_logic;
rst_sw : in std_logic;
locked : out std_logic;
clk40_out : out std_logic;
rst_state : out std_logic;
------
emu_ena : in std_logic;
--
edata_clk : out std_logic;
edata : out std_logic_vector (15 downto 0);
edata_rdy : out std_logic
------
);
end elinkInterface_top;
architecture Behavioral of elinkInterface_top is
----------------------------------
----------------------------------
component CR_CLKs
port
(-- Clock in ports
clk200_in_p : in std_logic;
clk200_in_n : in std_logic;
-- Clock out ports
clk40 : out std_logic;
clk80 : out std_logic;
clk160 : out std_logic;
clk320 : out std_logic;
clk240 : out std_logic;
-- Status and control signals
resetn : in std_logic;
locked : out std_logic
);
end component;
ATTRIBUTE SYN_BLACK_BOX : BOOLEAN;
ATTRIBUTE SYN_BLACK_BOX OF CR_CLKs : COMPONENT IS TRUE;
ATTRIBUTE BLACK_BOX_PAD_PIN : STRING;
ATTRIBUTE BLACK_BOX_PAD_PIN OF CR_CLKs : COMPONENT IS "clk200_in_p,clk200_in_n,clk40,clk80,clk160,clk320,resetn,locked";
----------------------------------
----------------------------------
constant block_size : std_logic_vector(8 downto 0) := (others=>'1'); -- block is 1Kbyte
signal block_word_count : std_logic_vector(8 downto 0) := (others=>'0');
signal packet_counter : std_logic_vector(7 downto 0) := (others=>'0');
signal count : std_logic_vector(7 downto 0) := (others=>'0');
signal packet_data : std_logic_vector(15 downto 0);
signal clk40, clk80, clk160, clk320, clk240 : std_logic;
signal startup_case : std_logic := '1';
signal efifoRe,send_sop,edata_rdy_r : std_logic := '0';
signal rst,fifo_flush,data_on_elink,efifoWe,efifoPfull,efifoHF,send_eop,emu_ena_s,block_done : std_logic;
signal efifoDin : std_logic_vector(17 downto 0) := (others=>'0');
signal efifoDout : std_logic_vector(15 downto 0);
begin
--------------------------------------------------------------------
-- clocks
--------------------------------------------------------------------
clk0: CR_CLKs
port map (
-- Clock in ports
clk200_in_p => clk_200_in_p,
clk200_in_n => clk_200_in_n,
-- Clock out ports
clk40 => clk40,
clk80 => clk80,
clk160 => clk160,
clk320 => clk320,
clk240 => clk240,
-- Status and control signals
resetn => sys_reset_n,
locked => locked
);
--
clk40_out <= clk40;
--
--------------------------------------------------------------------
-- reset and fifo flush sequence
--------------------------------------------------------------------
rst0: entity work.CRresetManager
port map (
clk40 => clk40,
rst_soft => rst_sw,
cr_rst => rst,
cr_fifo_flush => fifo_flush
);
--
rst_state <= rst;
--
--------------------------------------------------------------------
-- user data source: counter @ clk160
--------------------------------------------------------------------
send_eop <= '1' when (count = packet_size) else '0';
--
process(clk160)
begin
if rising_edge(clk160) then
send_sop <= send_eop; -- nex clock after eop is sent
if emu_ena = '1' then
startup_case <= '0';
end if;
if send_eop = '1' then
packet_counter <= packet_counter + 1;
end if;
end if;
end process;
--
emu_ena_s <= emu_ena and not (send_eop or send_sop or startup_case);
--
process(clk160)
begin
if rising_edge(clk160) then
if efifoPfull = '0' then -- only when not full
if emu_ena_s = '1' then -- when data emulator is enabled in simulation module
count <= count + 1;
else
count <= (others=>'0');
end if;
end if;
end if;
end process;
--
process(clk160)
begin
if rising_edge(clk160) then
if efifoPfull = '1' or emu_ena = '0' then
efifoWe <= '0';
efifoDin <= "11" & x"0000";
else
efifoWe <= '1';
if send_sop = '1' or startup_case = '1' then
efifoDin <= "10" & x"0000";
elsif send_eop = '1' then
efifoDin <= "01" & x"0000";
else
efifoDin <= "00" & packet_data;
end if;
end if;
end if;
end process;
--
--packet_data <= packet_counter & count;
--packet_data <= "11111111" & count;
--packet_data <= (others=>'1');
--packet_data <= x"fc" & x"fd";
--packet_data <= x"7e" & x"f" & count(3 downto 0);
packet_data <= x"fe" & x"f" & count(3 downto 0);
--
--------------------------------------------------------------------
-- elink transmitter
--------------------------------------------------------------------
elink_tx: entity work.FIFO2Elink
generic map (
OutputDataRate => elinkRate,
elinkEncoding => elinkEncoding
)
port map (
clk40 => clk40,
clk80 => clk80,
clk160 => clk160,
rst => rst,
fifo_flush => fifo_flush,
------
efifoDin => efifoDin, -- [data_code,2bit][data,16bit]
efifoWe => efifoWe,
efifoPfull => efifoPfull,
efifoWclk => clk160,
------
DATA1bitOUT => data_on_elink
------
);
--------------------------------------------------------------------
-- elink receiver
--------------------------------------------------------------------
elink_rx: entity work.Elink2FIFO
generic map (
InputDataRate => elinkRate,
elinkEncoding => elinkEncoding
)
port map (
clk40 => clk40,
clk80 => clk80,
clk160 => clk160,
rst => rst,
fifo_flush => fifo_flush,
------
DATA1bitIN => data_on_elink,
------
efifoRclk => clk160,
efifoRe => efifoRe,
efifoHF => efifoHF, -- half-full flag: 1 KByte block is ready to be read
efifoDout => efifoDout
------
);
--------------------------------------------------------------------
-- user data acquisition
--------------------------------------------------------------------
block_re_latch: process(clk160)
begin
if rising_edge(clk160) then
if block_done = '1' or rst = '1' then
efifoRe <= '0';
elsif efifoHF = '1' then -- one 1Kbyte block is ready
efifoRe <= '1';
end if;
end if;
end process;
--
block_done <= '1' when (block_word_count = block_size) else '0';
--
block_word_counter: process(clk160)
begin
if rising_edge(clk160) then
if efifoRe = '1' and block_done = '0' then
block_word_count <= block_word_count + 1;
else
block_word_count <= (others=>'0');
end if;
end if;
end process;
--
edata_rdy0: process(clk160)
begin
if rising_edge(clk160) then
edata_rdy_r <= efifoRe;
end if;
end process;
--
edata_clk <= clk160;
edata_rdy <= edata_rdy_r;
edata <= efifoDout;
--
end Behavioral;
|
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