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// See LICENSE.SiFive for license details.
package freechips.rocketchip.examples
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.amba.ahb.HasAHBControlRegMap
import freechips.rocketchip.amba.axi4.HasAXI4ControlRegMap
import freechips... | rocket-chip/src/main/scala/examples/ExampleDevice.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.125 | false | false | 2,630 | -1 |
package freechips.rocketchip.rocket
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.prci.{SynchronousCrossing, AsynchronousCrossing, RationalCrossing, ClockCrossingType}
import freechips.rocketchip.subsystem.{TilesLocated, NumTil... | rocket-chip/src/main/scala/rocket/Configs.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.02 | false | false | 14,650 | -1 |
// See LICENSE for license details.
package freechips.rocketchip.regmapper
import chisel3._
import freechips.rocketchip.util.{AsyncResetRegVec, SimpleRegIO}
object DescribedReg {
import freechips.rocketchip.regmapper.RegFieldAccessType._
import freechips.rocketchip.regmapper.RegFieldWrType._
import freechips.ro... | rocket-chip/src/main/scala/regmapper/DescribedReg.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.024 | false | false | 1,524 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.prci
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.resources.FixedClockResource
case class ClockG... | rocket-chip/src/main/scala/prci/ClockGroup.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.01 | false | false | 4,460 | -1 |
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{PriorityEncoder, Valid, log2Up}
/** Timer with a statically-specified period.
* Can take multiple inflight start-stop events with ID
* Will continue to c... | rocket-chip/src/main/scala/util/Timer.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.132 | false | false | 2,614 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import scala.language.implicitConversions
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{BufferParams}
package object prci
{
type ClockInwardNode = InwardNodeHandle[ClockSourceParameters, ClockSinkParameters... | rocket-chip/src/main/scala/prci/package.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.059 | false | false | 1,165 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axi4
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Parameters, Field}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.nodes.{SimpleNodeImp, RenderedEdge, OutwardN... | rocket-chip/src/main/scala/amba/axi4/Nodes.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.01 | false | false | 7,181 | -1 |
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Cat,log2Up}
import org.chipsalliance.cde.config.Parameters
class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module
{
val io = IO(new Bundl... | rocket-chip/src/main/scala/rocket/HellaCacheArbiter.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.026 | false | false | 3,049 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.nodes.{SimpleNodeHandle, OutwardNodeHandle, InwardNodeHandle}
import freechips.rocketchip.prci.{HasClockDomainCrossing, HasResetDomainCrossing}
/**
* Provide b... | rocket-chip/src/main/scala/amba/axi4/package.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.154 | false | false | 1,746 | -1 |
package freechips.rocketchip.resources
import freechips.rocketchip.diplomacy.{AddressRange}
case class AddressMapEntry(range: AddressRange, permissions: ResourcePermissions, names: Seq[String]) {
val ResourcePermissions(r, w, x, c, a) = permissions
def toString(aw: Int) = s"\t%${aw}x - %${aw}x %c%c%c%c%c %s".for... | rocket-chip/src/main/scala/resources/AddressMapEntry.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0 | false | false | 720 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{
AddressDecoder, AddressSet, Buffer... | rocket-chip/src/main/scala/tilelink/Parameters.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.069 | false | false | 64,309 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import scala.language.implicitConversions
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of me... | rocket-chip/src/main/scala/diplomacy/Parameters.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.094 | false | false | 11,844 | -1 |
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.subsystem
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.devices.debug.{DebugModuleKey, DefaultDebugModulePara... | rocket-chip/src/main/scala/subsystem/Litex.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.044 | false | false | 2,056 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
/** Using e.g. Random.nextInt makes your hardware generation non-repoducible,
* which is almost certainly undesirable. Use LCG to increment random numbers in HW,
* or use this SeededRandom.fromSeed to make reproducible Scala PRNGs.
*/
... | rocket-chip/src/main/scala/util/SeededRandom.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.556 | false | false | 387 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axi4
import chisel3._
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp, SimpleLazyModule}
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.di... | rocket-chip/src/main/scala/amba/axi4/Test.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.007 | false | false | 6,162 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axi4
import chisel3._
import chisel3.util.{log2Ceil, Cat}
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
import freechips.rocketchip.diplomacy.IdRange
import freech... | rocket-chip/src/main/scala/amba/axi4/IdIndexer.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.153 | false | false | 4,225 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.AsyncBundle
// READ the comments in the TLIsolation object before you instantiate this module
clas... | rocket-chip/src/main/scala/tilelink/Isolation.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.029 | false | false | 2,706 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.DataToAugmentedData
trait Pattern {
def address: BigInt
def size: Int
... | rocket-chip/src/main/scala/tilelink/PatternPusher.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.038 | false | false | 2,855 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import scala.language.dynamics
import scala.collection.mutable.Map
class Location[T](val name: String) extends Dynamic {
def selectDynamic[A](portname: String): Location[A] = new Location[A](s"${name}_${portname}")
def applyDynamic[A](p... | rocket-chip/src/main/scala/util/Location.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.133 | false | false | 1,602 | -1 |
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import freechips.rocketchip.util.property.cover
abstract class ReplacementPolicy {
def nBits: Int
def perSet: Boolean
... | rocket-chip/src/main/scala/util/Replacement.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.111 | false | false | 40,873 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, BufferParams}
import freechips.rocketchip.tilelink.{HasTLBusParams, TLBuffer, TLCacheCork, ... | rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.036 | false | false | 2,205 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
class MultiLaneQueue[T <: Data](gen: T, val lanes: Int, val rows: Int, val flow: Boolean = false, storage: LanePositionedQueue = FloppedLanePositionedQueue) extends Module {
val laneBits1 = log2Ceil(... | rocket-chip/src/main/scala/util/MultiLaneQueue.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.027 | false | false | 2,867 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{Decoupled, DecoupledIO}
// A Repeater passes its input to its output, unless repeat is asserted.
// When repeat is asserted, the Repeater copies the input and repeats it next cycle.
class Repeater[T <: ... | rocket-chip/src/main/scala/util/Repeater.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.118 | false | false | 1,224 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.amba.axi4.{
AX... | rocket-chip/src/main/scala/subsystem/Ports.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.075 | false | false | 9,433 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
class Atomics(params: TLBundleParameters) extends Module
{
val io = IO(new Bundle {
val write = Flipped(Bool()) // ignore opcode
val a = Flipped(new TLBundleA(params))
val d... | rocket-chip/src/main/scala/tilelink/Atomics.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.094 | false | false | 1,971 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.regmapper
import chisel3._
import chisel3.util.{Decoupled, Irrevocable}
import freechips.rocketchip.util.{AsyncQueue,AsyncQueueParams,AsyncResetRegVec}
// A very simple flow control state machine, run in the specified clock domain
class BusyReg... | rocket-chip/src/main/scala/regmapper/RegisterCrossing.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.208 | false | false | 8,232 | -1 |
package freechips.rocketchip
package object resources {
type PropertyOption = Option[(String, Seq[ResourceValue])]
type PropertyMap = Iterable[(String, Seq[ResourceValue])]
implicit class BigIntHexContext(private val sc: StringContext) extends AnyVal {
def x(args: Any*): BigInt = {
val orig = sc.s(arg... | rocket-chip/src/main/scala/resources/package.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0 | false | false | 848 | -1 |
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.constants.MemoryOpConstants
import freechips.rocketchip.util._
object ClientStates {
val width = 2
def Nothing =... | rocket-chip/src/main/scala/tilelink/Metadata.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.185 | false | false | 6,232 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.apb
import chisel3.util.{isPow2, log2Up}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.BaseNode
import freechips.rocketchip.diplomacy.{AddressSet, RegionType... | rocket-chip/src/main/scala/amba/apb/Parameters.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.032 | false | false | 3,544 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import scala.language.implicitConversions
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.resources.Resource
// A potentially empty... | rocket-chip/src/main/scala/interrupts/Parameters.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.074 | false | false | 2,063 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba
import org.chipsalliance.diplomacy.nodes.{InwardNodeHandle, OutwardNodeHandle, NodeHandle}
package object axis
{
type AXISInwardNode = InwardNodeHandle[AXISMasterPortParameters, AXISSlavePortParameters, AXISEdgeParameters, AXISBundle]
t... | rocket-chip/src/main/scala/amba/axis/package.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.111 | false | false | 640 | -1 |
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends... | rocket-chip/src/main/scala/util/Misc.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.035 | false | false | 6,955 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axis
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
sealed trait AXISKey
case object AXISLast extends ControlKey[Bool]("last") with AXISKey
case object AXISId extends ControlKey[UInt]("id") with AXISKey
case ob... | rocket-chip/src/main/scala/amba/axis/Bundles.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.024 | false | false | 2,533 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axi4
import chisel3._
case class AXI4MonitorArgs(edge: AXI4EdgeParameters)
abstract class AXI4MonitorBase(args: AXI4MonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new AXI4Bundle(args.edge.bundle))
})
def l... | rocket-chip/src/main/scala/amba/axi4/Monitor.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.083 | false | false | 432 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.regmapper
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet}
import f... | rocket-chip/src/main/scala/regmapper/RegisterRouter.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.146 | false | false | 2,248 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.ahb
import chisel3._
object AHBParameters
{
// These are all fixed by the AHB standard:
val transBits = 2
val burstBits = 3
val protBits = 4
val sizeBits = 3 // 8*2^s
val userBits = 3
val hrespBits = 2 // AHB full
def ... | rocket-chip/src/main/scala/amba/ahb/Protocol.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.083 | false | false | 1,556 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet}
import freechips.rocketchip.resources.{SimpleDevice... | rocket-chip/src/main/scala/devices/tilelink/PhysicalFilter.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.25 | false | false | 14,537 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.ahb
import chisel3._
import chisel3.util.Mux1H
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
import freechips.rocketchip.diplomacy.AddressDecoder
import freechips.r... | rocket-chip/src/main/scala/amba/ahb/Xbar.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.024 | false | false | 3,481 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
class IDPool(numIds: Int, lateValid: Boolean = false, revocableSelect: Boolean = false) extends Module {
require (numIds > 0)
val idWidth = log2Up(numIds)
val io = IO(new Bundle {
val free =... | rocket-chip/src/main/scala/util/IDPool.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.136 | false | false | 1,792 | -1 |
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.subsystem.CacheBlockBytes
import freechips.rocketchip.tile.HasCoreParameters
imp... | rocket-chip/src/main/scala/rocket/BTB.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.083 | false | false | 12,837 | -1 |
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch}
impo... | rocket-chip/src/main/scala/rocket/PTW.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.227 | false | false | 32,867 | -1 |
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.{DontCare, WireInit, withClock, withReset}
import chisel3.experimental.SourceInfo
import chisel3.experimental.dataview._
import org.chipsallia... | rocket-chip/src/main/scala/tile/FPU.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.035 | false | false | 42,565 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.AddressSet
class Addr... | rocket-chip/src/main/scala/tilelink/AddressAdjuster.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.127 | false | false | 21,252 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
import freec... | rocket-chip/src/main/scala/tilelink/RegisterRouter.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.171 | false | false | 6,368 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.debug
import chisel3._
import chisel3.experimental._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.node... | rocket-chip/src/main/scala/devices/debug/Custom.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.107 | false | false | 3,550 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
class ExpandedInstruction extends Bundle {
val bits = UInt(32.W)
val rd = UInt... | rocket-chip/src/main/scala/rocket/RVC.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.005 | false | false | 8,226 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
// If you know two clocks are related with an N:M relationship, you
// can cross the clock domains with lower latency than an AsyncQueue.
// This crossing adds 1 cycle in the target clock domain.
// A... | rocket-chip/src/main/scala/util/RationalCrossing.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.176 | false | false | 5,295 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressRange}
import freechips.rocketchip.resources.{
BindingScope, ... | rocket-chip/src/main/scala/subsystem/BaseSubsystem.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.118 | false | false | 7,497 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.groundtest
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.AddressSet
import freechips.rocketchip.interrupts._
import freechips.rocketchip.tile.{NMI}
... | rocket-chip/src/main/scala/groundtest/GroundTestSubsystem.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.075 | false | false | 2,070 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.AddressSet
/* Address inside the 'local' sp... | rocket-chip/src/main/scala/tilelink/RegionReplication.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.13 | false | false | 2,593 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
import freechips.rocketchip.resour... | rocket-chip/src/main/scala/rocket/ScratchpadSlavePort.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.07 | false | false | 5,563 | -1 |
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// this bundle is used to expose some internal core signals
// to verification monitors which sample instruction commits
class CoreMonitorBundle(val xLen: Int, val fLen: Int) ext... | rocket-chip/src/main/scala/util/CoreMonitor.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.172 | false | false | 1,103 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
class MultiPortQueue[T <: Data](gen: T, val enq_lanes: Int, val deq_lanes: Int, val lanes: Int, val rows: Int, val flow: Boolean = false, storage: LanePositionedQueue = FloppedLanePositionedQueue) exte... | rocket-chip/src/main/scala/util/MultiPortQueue.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.073 | false | false | 4,475 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.am... | rocket-chip/src/main/scala/tilelink/ToAHB.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.081 | false | false | 12,018 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.bundlebridge._
case object IncludePSDTest extends Field[Boolean](false)
case object PSDTestModeBroadcastKey exte... | rocket-chip/src/main/scala/util/PSDTestMode.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.105 | false | false | 652 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.reflect.DataMirror
import scala.collection.immutable.SeqMap
import scala.collection.immutable.HashMap
/* BundleMaps include IOs for every BundleField they are constructed with.
* A given BundleField in a Bun... | rocket-chip/src/main/scala/util/BundleMap.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.319 | false | false | 6,445 | -1 |
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.system
import scala.collection.mutable.LinkedHashSet
abstract class RocketTestSuite {
val dir: String
val makeTargetName: String
val names: LinkedHashSet[String]
val envName: String
def kind... | rocket-chip/src/main/scala/system/RocketTestSuite.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.013 | false | false | 11,678 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
// Use AddressSet instead -- this is just for pretty printing
case class AddressRange(base: BigInt, size: BigInt) extends Ordered[AddressRange]
{
val end = base + size
require (base >= 0, s"AddressRange base must be positive, got:... | rocket-chip/src/main/scala/diplomacy/AddressRange.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.096 | false | false | 2,116 | -1 |
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket.constants
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
trait ScalarOpConstants {
val SZ_BR = 3
def BR_X = BitPat("b???")
def BR_EQ = 0.U(3.W)
def BR_NE = 1.U(3.W)
def BR_J = 2.U(3.W)
de... | rocket-chip/src/main/scala/rocket/Consts.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.012 | false | false | 2,917 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.unittest
import chisel3._
import freechips.rocketchip.amba.ahb._
import freechips.rocketchip.amba.apb._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem.{BaseSubsystemConfig}
impo... | rocket-chip/src/main/scala/unittest/Configs.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.03 | false | false | 9,726 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
object CRC
{
// A divisor is interpretted using an explicit+1 CRC notation where bit 0 is required to be one.
// For example, a divisor of 0x1d5 is interpretted to be x^8 + x^7 + x^6 + x^4 + x^2 + ... | rocket-chip/src/main/scala/util/CRC.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.312 | false | false | 1,361 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance... | rocket-chip/src/main/scala/tilelink/BusWrapper.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.096 | false | false | 14,317 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet}
import freechips.rocketchip.resources.{Resource, Si... | rocket-chip/src/main/scala/devices/tilelink/CLINT.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.122 | false | false | 4,345 | -1 |
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.withClock
import chisel3.util.HasBlackBoxResource
/** This black-boxes a Clock Divider by 2.
* The output clock is phase-aligned to the input clock.
* If you use this in synthesis, make sure your sdc
... | rocket-chip/src/main/scala/util/ClockDivider.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.245 | false | false | 1,636 | -1 |
package freechips.rocketchip.subsystem
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.devices.debug.{TLDebugModule}
import org.chipsalliance.diplomacy.FlipRender... | rocket-chip/src/main/scala/subsystem/Cluster.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.014 | false | false | 11,139 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{Counter, RegEnable}
/** Blocks transactions until the cycle after reset. */
object BlockDuringReset
{
private def outOfReset(stretchCycles: Int): Bool = stretchCycles match {
case 0 => RegNext(tru... | rocket-chip/src/main/scala/util/BlockDuringReset.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.133 | false | false | 558 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.ahb
import chisel3._
import chisel3.util.{log2Up, log2Ceil, Decoupled}
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.nodes.{SinkNode}
import freechips.rocketch... | rocket-chip/src/main/scala/amba/ahb/RegisterRouter.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.108 | false | false | 3,430 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
// To mix this trait, you must supply:
// override def canEqual(that: Any): Boolean = that.isInstanceOf[YourClass]
// override def productPrefix: String = "YourClass"
// def productArity: Int = # of fields
// def productElement(n: In... | rocket-chip/src/main/scala/util/SimpleProduct.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.286 | false | false | 1,311 | -1 |
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.diplomacy.lazymodule._
object IOHelper {
def forNonSynchronous[T <: Data](gen: => T, xs: Seq[ClockCrossingType], prefix: String): Seq[Option[ModuleVal... | rocket-chip/src/main/scala/prci/IOHelper.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.125 | false | false | 669 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet}
import freechips.rocketchip.prci.{CreditedCrossing}
import ... | rocket-chip/src/main/scala/tilelink/Credited.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.019 | false | false | 5,214 | -1 |
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{BitPat, Fill, Cat, Reverse, PriorityEncoderOH, PopCount, MuxLookup}
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile.CoreModu... | rocket-chip/src/main/scala/rocket/ALU.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.07 | false | false | 5,735 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{CRC, UIntToOH1}
import freechips.rocketchip.util.DataToAugmentedData
// We... | rocket-chip/src/main/scala/tilelink/RAMModel.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.105 | false | false | 15,990 | -1 |
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) {
val size = Wire(UInt(log2Up(log2Up(maxSi... | rocket-chip/src/main/scala/rocket/AMOALU.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.044 | false | false | 3,591 | -1 |
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.groundtest
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.resourc... | rocket-chip/src/main/scala/groundtest/Tile.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.036 | false | false | 2,085 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.BlockDuringReset
/** BlockDuringReset ensures that no channel admits to be ready or valid while re... | rocket-chip/src/main/scala/tilelink/BlockDuringReset.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.053 | false | false | 1,502 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{RegionType, AddressSet, TransferSizes}
import freechips.rocketc... | rocket-chip/src/main/scala/devices/tilelink/MaskROM.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.045 | false | false | 2,966 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util.isPow2
import org.chipsalliance.cde.config._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util._
case object MaxHartIdBits extends Field[Int]
// These parameters can be varied per-co... | rocket-chip/src/main/scala/tile/Core.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.035 | false | false | 5,240 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
import freechips.rocketc... | rocket-chip/src/main/scala/devices/tilelink/TestRAM.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.083 | false | false | 3,531 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet}
import freechips.rocketchip.resources.{SimpleDevice}
import freechips.roc... | rocket-chip/src/main/scala/devices/tilelink/BusBlocker.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.296 | false | false | 3,654 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.debug
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.amba.apb.{APBFanout, APBToTL}
import freechips.rocketchip.devices.debug.syst... | rocket-chip/src/main/scala/devices/debug/Debug.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.223 | false | false | 93,790 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axi4
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule.{LazyScope}
import freechips.rocketchip.prci.{ResetCrossingType, NoResetCrossing, StretchedResetCrossing, CrossingType, ClockCrossingType, NoC... | rocket-chip/src/main/scala/amba/axi4/CrossingHelper.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.014 | false | false | 3,542 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b... | rocket-chip/src/main/scala/tilelink/Buffer.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.013 | false | false | 3,081 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba
import org.chipsalliance.diplomacy.nodes.{InwardNodeHandle, OutwardNodeHandle, SimpleNodeHandle}
package object apb
{
type APBOutwardNode = OutwardNodeHandle[APBMasterPortParameters, APBSlavePortParameters, APBEdgeParameters, APBBundle]
... | rocket-chip/src/main/scala/amba/apb/package.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.111 | false | false | 553 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.rocket.{DCacheErrors, ICacheErrors}
import freechips.rocketchip.diplomacy.{Ad... | rocket-chip/src/main/scala/tile/BusErrorUnit.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.017 | false | false | 5,784 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBund... | rocket-chip/src/main/scala/tilelink/Bundles.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.103 | false | false | 12,443 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.devices.tilelink.{
BuiltInDevices, BuiltInZeroDeviceParams, BuiltInErrorDeviceParams, HasBuiltInDeviceParams
}
import f... | rocket-chip/src/main/scala/subsystem/SystemBus.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.022 | false | false | 2,063 | -1 |
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.groundtest
import org.chipsalliance.cde.config._
import freechips.rocketchip.devices.tilelink.{CLINTKey, PLICKey}
import freechips.rocketchip.devices.debug.{DebugModuleKey}
import freechips.rocketchip... | rocket-chip/src/main/scala/groundtest/Configs.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.063 | false | false | 2,228 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axi4
import chisel3._
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
import freechips.rocketchip.diplomacy.{AddressSet}
import freechips.rocketchip.prci.{CreditedCr... | rocket-chip/src/main/scala/amba/axi4/Credited.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.019 | false | false | 5,318 | -1 |
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
import Instructions._
import CustomInstructions._
import ALU._
abstract ... | rocket-chip/src/main/scala/rocket/IDecode.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.02 | false | false | 42,119 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axi4
import chisel3._
object AXI4Parameters
{
// These are all fixed by the AXI4 standard:
val lenBits = 8
val sizeBits = 3
val burstBits = 2
val lockBits = 1
val cacheBits = 4
val protBits = 3
val qosBits = 4
val r... | rocket-chip/src/main/scala/amba/axi4/Protocol.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.069 | false | false | 884 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.groundtest
import chisel3._
import chisel3.util._
import freechips.rocketchip.util.ValidMux
class GroundTestStatus extends Bundle {
val timeout = Valid(UInt(4.W))
val error = Valid(UInt(4.W))
}
object DebugCombiner {
def apply(debugs: Seq... | rocket-chip/src/main/scala/groundtest/Status.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.059 | false | false | 519 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axi4
import chisel3._
import chisel3.util.{Queue, QueueIO, UIntToOH}
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
import freechips.rocketchip.util.BundleMap
/** ... | rocket-chip/src/main/scala/amba/axi4/UserYanker.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.091 | false | false | 4,721 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
/** Implements the same interface as chisel3.util.Queue, but uses a shift
* register internally. It is less energy efficient whenever the queue
* has more than one entry populated, but is faster o... | rocket-chip/src/main/scala/util/ShiftQueue.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.096 | false | false | 2,043 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.ahb
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes... | rocket-chip/src/main/scala/amba/ahb/SRAM.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.22 | false | false | 4,854 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import freechips.rocketchip.util.{ControlKey, DataKey, BundleField}
package object amba {
class AMBAProtBundle extends Bundle {
val bufferable = Bool() // writeback caching ok?
val modifiable = Bool() // legal to read... | rocket-chip/src/main/scala/amba/package.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.071 | false | false | 1,237 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.unittest
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
abstract class LazyUnitTest(implicit p: Parameters) extends LazyModule
{ self =>
protected def finished: Bool
lazy val module =... | rocket-chip/src/main/scala/unittest/TestGenerator.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.067 | false | false | 1,135 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import scala.language.implicitConversions
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.AddressSet
import freechips.rocketchip.util.UIntToO... | rocket-chip/src/main/scala/tilelink/ErrorEvaluator.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.132 | false | false | 3,441 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
object ReduceOthers {
// Given a list of bools, create this output:
// out[i] = AND[j=0..out.size, j!=i] in[j]
def apply(x: Seq[Bool]): Seq[Bool] = {
val (literals, variables) = x.partition(_.isLit)
val fal... | rocket-chip/src/main/scala/util/ReduceOthers.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.078 | false | false | 1,504 | -1 |
// See LICENSE.jtag for license details.
package freechips.rocketchip.jtag
import chisel3._
class JTAGIdcodeBundle extends Bundle {
val version = UInt(4.W)
val partNumber = UInt(16.W)
val mfrId = UInt(11.W)
val always1 = UInt(1.W)
}
object JtagIdcode {
/** Generates a JTAG IDCODE as a 32-bit integer, usin... | rocket-chip/src/main/scala/jtag/JtagUtils.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.261 | false | false | 899 | -1 |
// See LICENSE.SiFive for license details.
package freechips.rocketchip.prci
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
trait HasResetDomainCrossing extends HasDomainCrossing { this: LazyModule =>
type DomainCrossingType = ResetCrossingType
}
sealed trait ResetCrossingTyp... | rocket-chip/src/main/scala/prci/ResetCrossingType.scala | arch_code | rocket-chip | rocket-chip/src/main | BSD-3-Clause OR Apache-2.0 | BSD-3-Clause OR Apache-2.0 | ece7b9ad544b07df39cd13b6fd7236562a26355d | other | false | 0.053 | false | false | 746 | -1 |
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