Unnamed: 0 int64 0 350k | level_0 int64 0 351k | ApplicationNumber int64 9.75M 96.1M | ArtUnit int64 1.6k 3.99k | Abstract stringlengths 1 8.37k | Claims stringlengths 3 292k | abstract-claims stringlengths 68 293k | TechCenter int64 1.6k 3.9k |
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11,400 | 11,400 | 15,040,236 | 2,859 | Some aspects provide for a multicopter that includes a frame and a charging unit receiver configured to receive a portion of a charging unit. In some aspects, a perimeter of a cross-section of the proximal portion of the charging unit receiver may be shorter than a perimeter of a cross-section of the distal portion of the charging unit receiver. In some aspects, a perimeter of a cross-section of the distal portion of the charging unit receiver may be shorter than a perimeter of a cross-section of the proximal portion of the charging unit receiver. Some aspects provide for a charging unit that includes a frame and a multicopter receiver configured to receive a portion of the multicopter. In some aspects, a perimeter of a cross-section of the distal portion of the multicopter receiver may be shorter than a perimeter of a cross-section of the proximal portion of the multicopter receiver. | 1. A multicopter comprising:
a frame; and a charging unit receiver coupled to the frame and configured to receive a portion of a charging unit, wherein the charging unit receiver comprises a distal portion and a proximal portion, and wherein a perimeter of a cross-section of the proximal portion of the charging unit receiver is shorter than a perimeter of a cross-section of the distal portion of the charging unit receiver. 2. The multicopter of claim 1, wherein the charging unit receiver further comprises one or more edges configured to guide the portion of the charging unit from the distal portion of the charging unit receiver to the proximal portion of the charging unit receiver. 3. The multicopter of claim 2, wherein the one or more edges comprise one or more sloped edges. 4. The multicopter of claim 3, wherein the one or more sloped edges comprise a uniform slope. 5. The multicopter of claim 3, wherein the one or more sloped edges comprise a first edge portion and a second edge portion, wherein a slope of the first edge portion differs from a slope of the second edge portion. 6. The multicopter of claim 3, wherein the one or more sloped edges comprise a uniform length. 7. The multicopter of claim 3, wherein the one or more sloped edges comprise a first edge portion and a second edge portion, wherein a length of the first edge portion differs from a length of the second edge portion. 8. The multicopter of claim 1, wherein the charging unit receiver comprises a component configured for charging of the multicopter by the charging unit. 9. The multicopter of claim 8, wherein the component comprises one or more charging coils configured for inductive charging of the multicopter by the charging unit. 10. The multicopter of claim 1, further comprising one or more securing mechanisms configured to secure the multicopter to the charging unit. 11. The multicopter of claim 1, wherein the charging unit receiver is integrated with the frame. 12. A charging unit for a multicopter, the charging unit comprising:
a frame; and a multicopter receiver coupled to the frame and configured to receive a portion of the multicopter, wherein the multicopter receiver comprises a distal portion and a proximal portion, and wherein a perimeter of a cross-section of the distal portion of the multicopter receiver is shorter than a perimeter of a cross-section of the proximal portion of the multicopter receiver. 13. The charging unit of claim 12, wherein the multicopter receiver further comprises one or more edges configured to guide the portion of the multicopter from the distal portion of the multicopter receiver to the proximal portion of the multicopter receiver. 14. The charging unit of claim 13, wherein the one or more edges comprise one or more sloped edges. 15. The charging unit of claim 14, wherein the one or more sloped edges comprise a uniform slope. 16. The charging unit of claim 14, wherein the one or more sloped edges comprise a first edge portion and a second edge portion, wherein a slope of the first edge portion differs from a slope of the second edge portion. 17. The charging unit of claim 14, wherein the one or more sloped edges comprise a uniform length. 18. The charging unit of claim 14, wherein the one or more sloped edges comprise a first edge portion and a second edge portion, wherein a length of the first edge portion differs from a length of the second edge portion. 19. The charging unit of claim 12, further comprising a component configured for charging the multicopter. 20. The charging unit of claim 19, wherein the component comprises one or more charging coils configured for inductive charging of the multicopter. 21. The charging unit of claim 12, further comprising one or more securing mechanisms configured to secure the multicopter to the charging unit. 22. The multicopter of claim 12, wherein the multicopter receiver is integrated with the frame. 23. A multicopter comprising:
a frame; and a charging unit receiver coupled to the frame and configured to be receivable into a portion of a charging unit, wherein the charging unit receiver comprises a distal portion and a proximal portion, and wherein a perimeter of a cross-section of the distal portion of the charging unit receiver is shorter than a perimeter of a cross-section of the proximal portion of the charging unit receiver. 24. The multicopter of claim 23, wherein the charging unit receiver further comprises one or more edges configured to guide the portion of the charging unit from the distal portion of the charging unit receiver to the proximal portion of the charging unit receiver. 25. The multicopter of claim 24, wherein the one or more edges comprise one or more sloped edges. 26. The multicopter of claim 25, wherein the one or more sloped edges comprise a uniform slope, and wherein the one or more sloped edges comprise a uniform length. 27. The multicopter of claim 25, wherein the one or more sloped edges comprise a first edge portion and a second edge portion, wherein a slope of the first edge portion differs from a slope of the second edge portion. 28. The multicopter of claim 25, wherein the one or more sloped edges comprise a first edge portion and a second edge portion, wherein a length of the first edge portion differs from a length of the second edge portion. 29. The multicopter of claim 23, wherein the charging unit receiver comprises a component configured for charging the multicopter by the charging unit. 30. The multicopter of claim 23, wherein the charging unit receiver is integrated with the frame. | Some aspects provide for a multicopter that includes a frame and a charging unit receiver configured to receive a portion of a charging unit. In some aspects, a perimeter of a cross-section of the proximal portion of the charging unit receiver may be shorter than a perimeter of a cross-section of the distal portion of the charging unit receiver. In some aspects, a perimeter of a cross-section of the distal portion of the charging unit receiver may be shorter than a perimeter of a cross-section of the proximal portion of the charging unit receiver. Some aspects provide for a charging unit that includes a frame and a multicopter receiver configured to receive a portion of the multicopter. In some aspects, a perimeter of a cross-section of the distal portion of the multicopter receiver may be shorter than a perimeter of a cross-section of the proximal portion of the multicopter receiver.1. A multicopter comprising:
a frame; and a charging unit receiver coupled to the frame and configured to receive a portion of a charging unit, wherein the charging unit receiver comprises a distal portion and a proximal portion, and wherein a perimeter of a cross-section of the proximal portion of the charging unit receiver is shorter than a perimeter of a cross-section of the distal portion of the charging unit receiver. 2. The multicopter of claim 1, wherein the charging unit receiver further comprises one or more edges configured to guide the portion of the charging unit from the distal portion of the charging unit receiver to the proximal portion of the charging unit receiver. 3. The multicopter of claim 2, wherein the one or more edges comprise one or more sloped edges. 4. The multicopter of claim 3, wherein the one or more sloped edges comprise a uniform slope. 5. The multicopter of claim 3, wherein the one or more sloped edges comprise a first edge portion and a second edge portion, wherein a slope of the first edge portion differs from a slope of the second edge portion. 6. The multicopter of claim 3, wherein the one or more sloped edges comprise a uniform length. 7. The multicopter of claim 3, wherein the one or more sloped edges comprise a first edge portion and a second edge portion, wherein a length of the first edge portion differs from a length of the second edge portion. 8. The multicopter of claim 1, wherein the charging unit receiver comprises a component configured for charging of the multicopter by the charging unit. 9. The multicopter of claim 8, wherein the component comprises one or more charging coils configured for inductive charging of the multicopter by the charging unit. 10. The multicopter of claim 1, further comprising one or more securing mechanisms configured to secure the multicopter to the charging unit. 11. The multicopter of claim 1, wherein the charging unit receiver is integrated with the frame. 12. A charging unit for a multicopter, the charging unit comprising:
a frame; and a multicopter receiver coupled to the frame and configured to receive a portion of the multicopter, wherein the multicopter receiver comprises a distal portion and a proximal portion, and wherein a perimeter of a cross-section of the distal portion of the multicopter receiver is shorter than a perimeter of a cross-section of the proximal portion of the multicopter receiver. 13. The charging unit of claim 12, wherein the multicopter receiver further comprises one or more edges configured to guide the portion of the multicopter from the distal portion of the multicopter receiver to the proximal portion of the multicopter receiver. 14. The charging unit of claim 13, wherein the one or more edges comprise one or more sloped edges. 15. The charging unit of claim 14, wherein the one or more sloped edges comprise a uniform slope. 16. The charging unit of claim 14, wherein the one or more sloped edges comprise a first edge portion and a second edge portion, wherein a slope of the first edge portion differs from a slope of the second edge portion. 17. The charging unit of claim 14, wherein the one or more sloped edges comprise a uniform length. 18. The charging unit of claim 14, wherein the one or more sloped edges comprise a first edge portion and a second edge portion, wherein a length of the first edge portion differs from a length of the second edge portion. 19. The charging unit of claim 12, further comprising a component configured for charging the multicopter. 20. The charging unit of claim 19, wherein the component comprises one or more charging coils configured for inductive charging of the multicopter. 21. The charging unit of claim 12, further comprising one or more securing mechanisms configured to secure the multicopter to the charging unit. 22. The multicopter of claim 12, wherein the multicopter receiver is integrated with the frame. 23. A multicopter comprising:
a frame; and a charging unit receiver coupled to the frame and configured to be receivable into a portion of a charging unit, wherein the charging unit receiver comprises a distal portion and a proximal portion, and wherein a perimeter of a cross-section of the distal portion of the charging unit receiver is shorter than a perimeter of a cross-section of the proximal portion of the charging unit receiver. 24. The multicopter of claim 23, wherein the charging unit receiver further comprises one or more edges configured to guide the portion of the charging unit from the distal portion of the charging unit receiver to the proximal portion of the charging unit receiver. 25. The multicopter of claim 24, wherein the one or more edges comprise one or more sloped edges. 26. The multicopter of claim 25, wherein the one or more sloped edges comprise a uniform slope, and wherein the one or more sloped edges comprise a uniform length. 27. The multicopter of claim 25, wherein the one or more sloped edges comprise a first edge portion and a second edge portion, wherein a slope of the first edge portion differs from a slope of the second edge portion. 28. The multicopter of claim 25, wherein the one or more sloped edges comprise a first edge portion and a second edge portion, wherein a length of the first edge portion differs from a length of the second edge portion. 29. The multicopter of claim 23, wherein the charging unit receiver comprises a component configured for charging the multicopter by the charging unit. 30. The multicopter of claim 23, wherein the charging unit receiver is integrated with the frame. | 2,800 |
11,401 | 11,401 | 14,456,805 | 2,842 | A flip-flop element is configured to gate the clock inversions within a master-slave flip-flop element. The flip-flop element reduces the number of circuit elements within the flip-flop element by collapsing elements with common functionality into a single circuit element. Further, by making the actions of judiciously selected circuit elements conditional upon the state of the input data, the flip-flop element circuit reduces the number of internal transitions. In this manner, by reducing the number of circuit elements as well as the number of transitions, the flip-flop element achieves substantial reduction in overall system power consumption, resulting in a more efficient system. | 1. A circuit element configured to perform a data capture operation, the circuit element comprising:
a first latch element configured to:
receive a first data signal that has a first logic state,
invert the first logic state to generate a first inverted logic state, and
receive a first clock signal; and
a first logic element coupled to the first latch element and configured to:
invert the first clock signal to generate a first inverted clock signal, and
transmit the first inverted clock signal to the first latch element, wherein the first latch element, in response to the first inverted clock signal, inverts the first data signal to generate a first inverted data signal. 2. The circuit element of claim 1 wherein the first latch element comprises:
a first inverter pair configured to receive the first data signal;
a first switching element coupled between the first inverter pair and a supply voltage;
a second switching element coupled between the first inverter pair and a grounding path;
a second inverter pair coupled to the first inverter pair;
a third switching element coupled between the second inverter pair and the supply voltage;
a first inverter coupled between the first inverter pair and the second inverter pair; and
a fourth switching element coupled between the second inverter pair and the grounding path. 3. The circuit element of claim 2, wherein the first latch element further comprises a fourth switching element coupled between the second inverter pair and the grounding path. 4. The circuit element of claim 1, wherein the first logic element comprises:
a first inverter pair coupled to the first latch element; a first switching element coupled between the first inverter pair and a supply voltage; and a second switching element coupled between the first inverter pair and a grounding path. 5. The circuit element of claim 4, wherein the first logic element comprises a negated AND (NAND) gate. 6. The circuit element of claim 4, wherein the first logic element further comprises a third switching element coupled between the first switching element and the first inverter pair. 7. The circuit element of claim 6, wherein the logic element comprises an AND-OR-INVERT gate. 8. The circuit element of claim 1, further comprising:
a second latch element configured to:
receive the first inverted data signal from the first logic element,
invert the first inverted data signal to generate a second data signal that has the first logic state,
receive the first clock signal,
receive the first inverted clock signal, and
output the second data signal in response to the first inverted clock signal. 9. The circuit element of claim 8, wherein the second latch element comprises:
a first switching element coupled to the first latch element; a second switching element coupled between the first switching element and a grounding path; a third switching element coupled between the first switching element and a supply voltage; a first inverter pair coupled to the first switching element; a first inverter coupled to the first inverter pair; and a second inverter coupled to the first inverter pair. 10. The circuit element of claim 9, wherein the second latch element further comprises a fourth switching element coupled between the second inverter pair and the supply voltage. 11. The circuit element of claim 4, wherein the first logic element is further configured to couple an inversion of the first data signal to the first switching element. 12. A flip-flop element configured to perform a data capture operation, the flip-flop element comprising:
a first latch element configured to:
receive a first data signal that has a first logic state,
invert the first logic state to generate a first inverted logic state, and
receive a first clock signal; and
a first logic element coupled to the first latch element and configured to:
invert the first clock signal to generate a first inverted clock signal, and
transmit the first inverted clock signal to the first latch element, wherein the first latch element, in response to the first inverted clock signal, inverts the first data signal to generate a first inverted data signal. 13. The flip-flop element of claim 12, wherein the first latch element comprises:
a first inverter pair configured to receive the first data signal; a first switching element coupled between the first inverter pair and a supply voltage; a second switching element coupled between the first inverter pair and a grounding path; a second inverter pair coupled to the first inverter pair; a third switching element coupled between the second inverter pair and a supply voltage; a first inverter coupled between the first inverter pair and the second inverter pair; and a fourth switching element coupled between the second inverter pair and the grounding path. 14. The flip-flop element of claim 12, wherein the first logic element comprises:
a first inverter pair coupled to the first latch element; a first switching element coupled between the first inverter pair and a supply voltage; and a second switching element coupled between the first inverter pair and a grounding path. 15. The flip-flop element of claim 12, further comprising:
a second latch element configured to:
receive the first inverted data signal from the first latch element,
invert the first inverted data signal to generate a second data signal that has the first logic state,
receive the first clock signal,
receive the first inverted clock signal, and
output the second data signal in response to the first inverted clock signal. 16. The flip-flop element of claim 15, wherein the second latch element comprises:
a first switching element coupled to the first latch element; a second switching element coupled between the first switching element and a grounding path; a third switching element coupled between the first switching element and a supply voltage; a first inverter pair coupled to the first switching element; a first inverter coupled to the first inverter pair; and a second inverter coupled to the first inverter pair. 17. A subsystem configured to perform a data capture operation, comprising:
a flip-flop element, configured to:
receive a first data signal that has a first logic state,
invert the first logic state to generate a first inverted logic state,
receive a first clock signal,
invert the first data signal to produce a first inverted data signal,
invert the first inverted data signal to generate a second data signal that has the first logic state, and
output the second data signal in response to the first inverted clock signal. 18. The subsystem of claim 17, wherein the flip-flop element includes a first latch element configured to:
receive the first data signal; invert the first logic state to generate the first inverted logic state; receive the first clock signal; and invert the first clock signal to generate the first inverted clock signal. 19. The subsystem of claim 18, wherein the flip-flop element includes a first logic element configured to:
gate off the first inverted clock signal with the first inverted logic state to generate the first inverted clock signal; and transmit the second clock signal to the first latch element, wherein the first latch element, in response to the first inverted clock signal, inverts the first data signal to generate a first inverted data signal. 20. The subsystem of claim 19, wherein the flip-flop element includes a second latch element configured to:
receive the first inverted data signal from the first latch element; invert the first inverted data signal to generate the second data signal; receive the first clock signal; receive the first inverted clock signal; and output the second data signal in response to the first inverted clock signal. | A flip-flop element is configured to gate the clock inversions within a master-slave flip-flop element. The flip-flop element reduces the number of circuit elements within the flip-flop element by collapsing elements with common functionality into a single circuit element. Further, by making the actions of judiciously selected circuit elements conditional upon the state of the input data, the flip-flop element circuit reduces the number of internal transitions. In this manner, by reducing the number of circuit elements as well as the number of transitions, the flip-flop element achieves substantial reduction in overall system power consumption, resulting in a more efficient system.1. A circuit element configured to perform a data capture operation, the circuit element comprising:
a first latch element configured to:
receive a first data signal that has a first logic state,
invert the first logic state to generate a first inverted logic state, and
receive a first clock signal; and
a first logic element coupled to the first latch element and configured to:
invert the first clock signal to generate a first inverted clock signal, and
transmit the first inverted clock signal to the first latch element, wherein the first latch element, in response to the first inverted clock signal, inverts the first data signal to generate a first inverted data signal. 2. The circuit element of claim 1 wherein the first latch element comprises:
a first inverter pair configured to receive the first data signal;
a first switching element coupled between the first inverter pair and a supply voltage;
a second switching element coupled between the first inverter pair and a grounding path;
a second inverter pair coupled to the first inverter pair;
a third switching element coupled between the second inverter pair and the supply voltage;
a first inverter coupled between the first inverter pair and the second inverter pair; and
a fourth switching element coupled between the second inverter pair and the grounding path. 3. The circuit element of claim 2, wherein the first latch element further comprises a fourth switching element coupled between the second inverter pair and the grounding path. 4. The circuit element of claim 1, wherein the first logic element comprises:
a first inverter pair coupled to the first latch element; a first switching element coupled between the first inverter pair and a supply voltage; and a second switching element coupled between the first inverter pair and a grounding path. 5. The circuit element of claim 4, wherein the first logic element comprises a negated AND (NAND) gate. 6. The circuit element of claim 4, wherein the first logic element further comprises a third switching element coupled between the first switching element and the first inverter pair. 7. The circuit element of claim 6, wherein the logic element comprises an AND-OR-INVERT gate. 8. The circuit element of claim 1, further comprising:
a second latch element configured to:
receive the first inverted data signal from the first logic element,
invert the first inverted data signal to generate a second data signal that has the first logic state,
receive the first clock signal,
receive the first inverted clock signal, and
output the second data signal in response to the first inverted clock signal. 9. The circuit element of claim 8, wherein the second latch element comprises:
a first switching element coupled to the first latch element; a second switching element coupled between the first switching element and a grounding path; a third switching element coupled between the first switching element and a supply voltage; a first inverter pair coupled to the first switching element; a first inverter coupled to the first inverter pair; and a second inverter coupled to the first inverter pair. 10. The circuit element of claim 9, wherein the second latch element further comprises a fourth switching element coupled between the second inverter pair and the supply voltage. 11. The circuit element of claim 4, wherein the first logic element is further configured to couple an inversion of the first data signal to the first switching element. 12. A flip-flop element configured to perform a data capture operation, the flip-flop element comprising:
a first latch element configured to:
receive a first data signal that has a first logic state,
invert the first logic state to generate a first inverted logic state, and
receive a first clock signal; and
a first logic element coupled to the first latch element and configured to:
invert the first clock signal to generate a first inverted clock signal, and
transmit the first inverted clock signal to the first latch element, wherein the first latch element, in response to the first inverted clock signal, inverts the first data signal to generate a first inverted data signal. 13. The flip-flop element of claim 12, wherein the first latch element comprises:
a first inverter pair configured to receive the first data signal; a first switching element coupled between the first inverter pair and a supply voltage; a second switching element coupled between the first inverter pair and a grounding path; a second inverter pair coupled to the first inverter pair; a third switching element coupled between the second inverter pair and a supply voltage; a first inverter coupled between the first inverter pair and the second inverter pair; and a fourth switching element coupled between the second inverter pair and the grounding path. 14. The flip-flop element of claim 12, wherein the first logic element comprises:
a first inverter pair coupled to the first latch element; a first switching element coupled between the first inverter pair and a supply voltage; and a second switching element coupled between the first inverter pair and a grounding path. 15. The flip-flop element of claim 12, further comprising:
a second latch element configured to:
receive the first inverted data signal from the first latch element,
invert the first inverted data signal to generate a second data signal that has the first logic state,
receive the first clock signal,
receive the first inverted clock signal, and
output the second data signal in response to the first inverted clock signal. 16. The flip-flop element of claim 15, wherein the second latch element comprises:
a first switching element coupled to the first latch element; a second switching element coupled between the first switching element and a grounding path; a third switching element coupled between the first switching element and a supply voltage; a first inverter pair coupled to the first switching element; a first inverter coupled to the first inverter pair; and a second inverter coupled to the first inverter pair. 17. A subsystem configured to perform a data capture operation, comprising:
a flip-flop element, configured to:
receive a first data signal that has a first logic state,
invert the first logic state to generate a first inverted logic state,
receive a first clock signal,
invert the first data signal to produce a first inverted data signal,
invert the first inverted data signal to generate a second data signal that has the first logic state, and
output the second data signal in response to the first inverted clock signal. 18. The subsystem of claim 17, wherein the flip-flop element includes a first latch element configured to:
receive the first data signal; invert the first logic state to generate the first inverted logic state; receive the first clock signal; and invert the first clock signal to generate the first inverted clock signal. 19. The subsystem of claim 18, wherein the flip-flop element includes a first logic element configured to:
gate off the first inverted clock signal with the first inverted logic state to generate the first inverted clock signal; and transmit the second clock signal to the first latch element, wherein the first latch element, in response to the first inverted clock signal, inverts the first data signal to generate a first inverted data signal. 20. The subsystem of claim 19, wherein the flip-flop element includes a second latch element configured to:
receive the first inverted data signal from the first latch element; invert the first inverted data signal to generate the second data signal; receive the first clock signal; receive the first inverted clock signal; and output the second data signal in response to the first inverted clock signal. | 2,800 |
11,402 | 11,402 | 14,806,928 | 2,883 | A method for forming optoelectronic modules connectable to optical fibers is provided which comprises forming a compound substrate comprising a substrate having a two-dimensional array of optoelectronic devices and further comprising a cover layer having a two-dimensional array of fiber end-piece mounting structures. The cover layer is arranged in an aligned position in relation to the substrate, thereby bringing all fiber end-piece mounting structures in alignment to all optoelectronic devices simultaneously. The compound substrate is singulated into pieces, thereby forming a plurality of optoelectronic modules each comprising at least one optoelectronic device covered by an aligned fiber end-piece mounting block connectable to end-pieces of at least one optical fiber in a position automatically self-aligned. | 1. A method for forming optoelectronic modules connectable to optical fibers, wherein the method at least comprises:
a) forming a compound substrate:
the compound substrate comprising a substrate having a plurality of optoelectronic devices constituting a two-dimensional first array in which the optoelectronic devices are lined up along two lateral directions;
the compound substrate further comprising a cover layer on a side of the substrate, the cover layer having a plurality of fiber end-piece mounting structures for mounting fiber end-pieces, the fiber end-piece mounting structures constituting a two-dimensional second array in which the fiber end-piece mounting structures are lined up along the two lateral directions;
wherein forming the compound substrate comprises arranging the cover layer and/or the plurality of fiber end-piece mounting structures in an aligned position in relation to the substrate and/or in relation to the plurality of optoelectronic devices, thereby bringing all fiber end-piece mounting structures in alignment to all optoelectronic devices simultaneously; and
b) singulating the compound substrate into pieces, thereby forming a plurality of optoelectronic modules each comprising at least one optoelectronic device covered by an aligned fiber end-piece mounting block shaped to receive at least one fiber end-piece of at least one respective optical fiber in a position self-aligned to the at least one optoelectronic device. 2. The method of claim 1, wherein the substrate comprising the plurality of optoelectronic devices is a semiconductor wafer made of silicon, indium phosphide or another semiconductor material or semiconductor material composition, or is a glass wafer, a quartz wafer, or a ceramic wafer. 3. The method of claim 1, wherein the cover layer is a further substrate and wherein the compound substrate includes bonding the substrate and the further substrate onto one another in an aligned position relative to each other. 4. The method of claim 3, wherein at least one of the substrate and the further substrate is made of a semiconductor material, such as silicon or indium phosphide, for instance, of ceramics, of glass, of quartz or of a synthetic material, such as a polymer, and wherein the fiber end-piece mounting structures are formed in the further substrate prior to bonding both substrates onto one another. 5. The method of claim 3, wherein the fiber end-piece mounting structures are formed in at least one surface of the substrate or of the further substrate by means of UV imprint lithography, reactive ion etching, injection molding, and/or another technique of semiconductor manufacturing or of micro-electro-mechanical system manufacturing, thereby forming the fiber end-piece mounting structures in an exposed portion of the substrate or in the further substrate. 6. The method of claim 1, wherein the cover layer is formed by depositing a cover material onto the substrate comprising the optoelectronic devices and wherein an exposed surface of the cover layer thus deposited is patterned subsequently, thereby forming a plurality of aligned fiber end-piece mounting structures in the cover layer in positions aligned to the optoelectronic devices. 7. The method of claim 1, wherein injection molding, UV imprint lithography, reactive ion etching and/or another technique of semiconductor manufacturing or micro-electro-mechanical system manufacturing is applied for patterning an exposed surface of the cover layer to form the plurality of fiber end-piece mounting structures. 8. The method of claim 1, wherein for each optoelectronic device an associated fiber end-piece mounting structure is formed which at least comprises a surface portion shaped to receive a fiber end-piece free of play and/or shaped to insert a fiber end-piece in a position fixed in two or three directions. 9. The method of claim 8, wherein each fiber end-piece mounting structure comprises a groove for attaching an optical fiber with its axial extension oriented in parallel to a main surface of the cover layer or with its axial extension oriented at an angle to a main surface of the cover layer. 10. The method of claim 9, wherein each fiber end-piece mounting structure comprises an end stop surface for defining a maximum length of a fiber end-piece to be inserted in the groove, wherein the end stop surface is defining the lateral end of the groove or is located at a distance from the groove, for instance behind a widened recess wider than the groove. 11. The method of claim 1, wherein each fiber end-piece mounting structure is formed so as to comprise a slanted surface which is slanted such as to reflect a beam of electromagnetic radiation from an optical fiber onto the optoelectronic device or vice versa. 12. The method of claim 11, wherein the reflective surface is covered with a reflective coating or is slanted at an angle suitable for reflecting a beam of electromagnetic radiation due to total internal reflection. 13. The method of claim 1, wherein the method further comprises either mounting an additional protective cover substrate onto a surface of the substrate of the cover layer, or of the further substrate before singulating the compound substrate thus obtained, or mounting protective cover elements on at least some of the optoelectronic modules after singulating the compound substrate. 14. A compound substrate at least comprising a substrate having a plurality of optoelectronic devices constituting a two-dimensional first array in which the optoelectronic devices are lined up along two lateral directions:
the compound substrate further comprising a cover layer on one side of the substrate, the cover layer having a plurality of fiber end-piece mounting structures for mounting fiber end-pieces, the fiber end-piece mounting structures constituting a two-dimensional second array in which the fiber end-piece mounting structures are lined up along the two lateral directions, the fiber end-piece mounting structures being shaped to receive at least one fiber end-piece of at least one respective optical fiber; wherein the fiber end-piece mounting structures of the second array are aligned to the optoelectronic devices of the first array so as to enable self-aligned mounting of fiber end-pieces via the fiber end-piece mounting structures to the optoelectronic devices. 15. An optoelectronic module connectable to at least one optical fiber, the optoelectronic module comprising a piece of a first substrate comprising at least one optoelectronic device, and further comprising a fiber end-piece mounting block arranged at the piece of the first substrate, the fiber end-piece mounting block being shaped to receive at least one fiber end-piece in a mounting position self-aligned in relation to the optoelectronic device, wherein the optoelectronic module is confined by surfaces along which at least some of the sidewalls of the fiber end-piece mounting block are flush with at least some of the sidewalls of the piece of the first substrate comprising the at least one optoelectronic device. | A method for forming optoelectronic modules connectable to optical fibers is provided which comprises forming a compound substrate comprising a substrate having a two-dimensional array of optoelectronic devices and further comprising a cover layer having a two-dimensional array of fiber end-piece mounting structures. The cover layer is arranged in an aligned position in relation to the substrate, thereby bringing all fiber end-piece mounting structures in alignment to all optoelectronic devices simultaneously. The compound substrate is singulated into pieces, thereby forming a plurality of optoelectronic modules each comprising at least one optoelectronic device covered by an aligned fiber end-piece mounting block connectable to end-pieces of at least one optical fiber in a position automatically self-aligned.1. A method for forming optoelectronic modules connectable to optical fibers, wherein the method at least comprises:
a) forming a compound substrate:
the compound substrate comprising a substrate having a plurality of optoelectronic devices constituting a two-dimensional first array in which the optoelectronic devices are lined up along two lateral directions;
the compound substrate further comprising a cover layer on a side of the substrate, the cover layer having a plurality of fiber end-piece mounting structures for mounting fiber end-pieces, the fiber end-piece mounting structures constituting a two-dimensional second array in which the fiber end-piece mounting structures are lined up along the two lateral directions;
wherein forming the compound substrate comprises arranging the cover layer and/or the plurality of fiber end-piece mounting structures in an aligned position in relation to the substrate and/or in relation to the plurality of optoelectronic devices, thereby bringing all fiber end-piece mounting structures in alignment to all optoelectronic devices simultaneously; and
b) singulating the compound substrate into pieces, thereby forming a plurality of optoelectronic modules each comprising at least one optoelectronic device covered by an aligned fiber end-piece mounting block shaped to receive at least one fiber end-piece of at least one respective optical fiber in a position self-aligned to the at least one optoelectronic device. 2. The method of claim 1, wherein the substrate comprising the plurality of optoelectronic devices is a semiconductor wafer made of silicon, indium phosphide or another semiconductor material or semiconductor material composition, or is a glass wafer, a quartz wafer, or a ceramic wafer. 3. The method of claim 1, wherein the cover layer is a further substrate and wherein the compound substrate includes bonding the substrate and the further substrate onto one another in an aligned position relative to each other. 4. The method of claim 3, wherein at least one of the substrate and the further substrate is made of a semiconductor material, such as silicon or indium phosphide, for instance, of ceramics, of glass, of quartz or of a synthetic material, such as a polymer, and wherein the fiber end-piece mounting structures are formed in the further substrate prior to bonding both substrates onto one another. 5. The method of claim 3, wherein the fiber end-piece mounting structures are formed in at least one surface of the substrate or of the further substrate by means of UV imprint lithography, reactive ion etching, injection molding, and/or another technique of semiconductor manufacturing or of micro-electro-mechanical system manufacturing, thereby forming the fiber end-piece mounting structures in an exposed portion of the substrate or in the further substrate. 6. The method of claim 1, wherein the cover layer is formed by depositing a cover material onto the substrate comprising the optoelectronic devices and wherein an exposed surface of the cover layer thus deposited is patterned subsequently, thereby forming a plurality of aligned fiber end-piece mounting structures in the cover layer in positions aligned to the optoelectronic devices. 7. The method of claim 1, wherein injection molding, UV imprint lithography, reactive ion etching and/or another technique of semiconductor manufacturing or micro-electro-mechanical system manufacturing is applied for patterning an exposed surface of the cover layer to form the plurality of fiber end-piece mounting structures. 8. The method of claim 1, wherein for each optoelectronic device an associated fiber end-piece mounting structure is formed which at least comprises a surface portion shaped to receive a fiber end-piece free of play and/or shaped to insert a fiber end-piece in a position fixed in two or three directions. 9. The method of claim 8, wherein each fiber end-piece mounting structure comprises a groove for attaching an optical fiber with its axial extension oriented in parallel to a main surface of the cover layer or with its axial extension oriented at an angle to a main surface of the cover layer. 10. The method of claim 9, wherein each fiber end-piece mounting structure comprises an end stop surface for defining a maximum length of a fiber end-piece to be inserted in the groove, wherein the end stop surface is defining the lateral end of the groove or is located at a distance from the groove, for instance behind a widened recess wider than the groove. 11. The method of claim 1, wherein each fiber end-piece mounting structure is formed so as to comprise a slanted surface which is slanted such as to reflect a beam of electromagnetic radiation from an optical fiber onto the optoelectronic device or vice versa. 12. The method of claim 11, wherein the reflective surface is covered with a reflective coating or is slanted at an angle suitable for reflecting a beam of electromagnetic radiation due to total internal reflection. 13. The method of claim 1, wherein the method further comprises either mounting an additional protective cover substrate onto a surface of the substrate of the cover layer, or of the further substrate before singulating the compound substrate thus obtained, or mounting protective cover elements on at least some of the optoelectronic modules after singulating the compound substrate. 14. A compound substrate at least comprising a substrate having a plurality of optoelectronic devices constituting a two-dimensional first array in which the optoelectronic devices are lined up along two lateral directions:
the compound substrate further comprising a cover layer on one side of the substrate, the cover layer having a plurality of fiber end-piece mounting structures for mounting fiber end-pieces, the fiber end-piece mounting structures constituting a two-dimensional second array in which the fiber end-piece mounting structures are lined up along the two lateral directions, the fiber end-piece mounting structures being shaped to receive at least one fiber end-piece of at least one respective optical fiber; wherein the fiber end-piece mounting structures of the second array are aligned to the optoelectronic devices of the first array so as to enable self-aligned mounting of fiber end-pieces via the fiber end-piece mounting structures to the optoelectronic devices. 15. An optoelectronic module connectable to at least one optical fiber, the optoelectronic module comprising a piece of a first substrate comprising at least one optoelectronic device, and further comprising a fiber end-piece mounting block arranged at the piece of the first substrate, the fiber end-piece mounting block being shaped to receive at least one fiber end-piece in a mounting position self-aligned in relation to the optoelectronic device, wherein the optoelectronic module is confined by surfaces along which at least some of the sidewalls of the fiber end-piece mounting block are flush with at least some of the sidewalls of the piece of the first substrate comprising the at least one optoelectronic device. | 2,800 |
11,403 | 11,403 | 15,203,692 | 2,899 | Several embodiments of the present technology are described with reference to a semiconductor die assembly and processes for manufacturing the assembly. In some embodiments of the present technology, a semiconductor die assembly includes a stack of semiconductor dies attached to a thermal transfer structure (also known as a “heat spreader,” “lid,” or “thermal lid”). The thermal transfer structure conducts heat away from the stack of semiconductor dies. Additionally, the assembly can include molded walls fabricated with molding material to support the thermal transfer structure. | 1. A semiconductor die assembly, comprising:
a support substrate; a first semiconductor die on the support substrate; a plurality of second semiconductor dies arranged in a stack on the first semiconductor die; a molded wall made from a molded material, wherein the molded wall has substantially vertical surfaces defining a cavity spaced apart from the stack of second semiconductor dies and a portion of the molded wall is on the support substrate spaced laterally apart from the first semiconductor die; and a thermal transfer structure (TTS) attached to the molded wall. 2. The semiconductor die assembly of claim 1, further comprising a plurality of capacitors on the support substrate, wherein the plurality of capacitors are operatively coupled to the stack, and wherein the molded wall has a recessed surface molded around the capacitor. 3. The semiconductor die assembly of claim 1 wherein the TTS further comprises a first portion extending in a first direction and a second portion extending in a second direction, wherein the first and second directions are different, and wherein the second portion is directly coupled to the first semiconductor die via an adhesive. 4. The semiconductor die assembly of claim 1 wherein the TTS comprises at least one of copper, nickel, or both. 5. The semiconductor die assembly of claim 1, further comprising an underfill material disposed between the molded wall and the stack and between the plurality of second semiconductor dies arranged in the stack. 6. The semiconductor die assembly of claim 3 wherein the first semiconductor die is a logic die that extends at least partially beyond other semiconductor dies and is attached to the support substrate and operatively coupled to a capacitor. 7. A semiconductor die assembly, comprising:
a support substrate; a first semiconductor die on the support substrate; a stack of second semiconductor dies on the first semiconductor die, wherein the second semiconductor dies have different functionality than the first semiconductor die; a molded material formed on the substrate and having substantially vertical surfaces defining a cavity, wherein the stack of second semiconductor dies is received in the cavity and spaced apart from the molded material; a thermal transfer lid having a first portion attached to the molded material and a second portion extending from the first portion, wherein the second portion of the thermal transfer lid is attached to the first semiconductor die. 8. The semiconductor die assembly of claim 7 wherein the molded wall covers an electronic component operatively coupled to the first semiconductor die in the stack. 9. The semiconductor die assembly of claim 7 wherein the molded wall further comprises at least one of an organic resin, nonorganic resin, epoxy, or a combination thereof. 10. The semiconductor die assembly of claim 7 wherein the thermal transfer lid comprises at least one of copper, nickel, or a combination thereof. 11. The semiconductor die assembly of claim 7, wherein the second portion of the thermal transfer lid is attached to a peripheral region of the first die located on the bottom of the stack, and wherein the peripheral region extends beyond the second semiconductor dies in the stack. 12. The semiconductor die assembly of claim 7 wherein the stack includes a logic die that extends at least partially beyond other semiconductor dies and is attached to the support substrate and operatively coupled to a capacitor, wherein the capacitor is operatively coupled to the support substrate. 13. The semiconductor die assembly of claim 7 wherein the thermal transfer lid has a plurality of passages. 14. The semiconductor die assembly of claim 7 wherein the stack comprises at least eight dies. 15. A method of manufacturing a semiconductor die assembly, the method comprising:
molding a material onto a support substrate and over a plurality of capacitors on the support substrate, wherein the molding material has cavity; after molding the material onto the support substrate, attaching a first die to the support substrate; positioning a plurality of semiconductor dies arranged in a stack over the first die, wherein at least the stack of second dies is within the cavity defined by the molding material; and attaching a thermal lid to the molding material. 16. The method of claim 15, further comprising disposing thermal interface material to a surface of the stack. 17. The method of claim 15, further comprising disposing underfill material between the two molded walls and the stack. 18. The method of claim 15, further comprising positioning a plurality of capacitors on a support substrate and reflowing the semiconductor die assembly after positioning the plurality of capacitors on the support substrate. 19. The method of claim 15, wherein attaching the thermal lid to the stack further comprises attaching a first portion of the thermal lid to a top of the stack and a second portion of the thermal lid to a peripheral region of the first die. 20. The method of claim 15, wherein positioning the plurality of semiconductor dies arranged in a stack over the first die the stack comprises positioning at least eight dies. | Several embodiments of the present technology are described with reference to a semiconductor die assembly and processes for manufacturing the assembly. In some embodiments of the present technology, a semiconductor die assembly includes a stack of semiconductor dies attached to a thermal transfer structure (also known as a “heat spreader,” “lid,” or “thermal lid”). The thermal transfer structure conducts heat away from the stack of semiconductor dies. Additionally, the assembly can include molded walls fabricated with molding material to support the thermal transfer structure.1. A semiconductor die assembly, comprising:
a support substrate; a first semiconductor die on the support substrate; a plurality of second semiconductor dies arranged in a stack on the first semiconductor die; a molded wall made from a molded material, wherein the molded wall has substantially vertical surfaces defining a cavity spaced apart from the stack of second semiconductor dies and a portion of the molded wall is on the support substrate spaced laterally apart from the first semiconductor die; and a thermal transfer structure (TTS) attached to the molded wall. 2. The semiconductor die assembly of claim 1, further comprising a plurality of capacitors on the support substrate, wherein the plurality of capacitors are operatively coupled to the stack, and wherein the molded wall has a recessed surface molded around the capacitor. 3. The semiconductor die assembly of claim 1 wherein the TTS further comprises a first portion extending in a first direction and a second portion extending in a second direction, wherein the first and second directions are different, and wherein the second portion is directly coupled to the first semiconductor die via an adhesive. 4. The semiconductor die assembly of claim 1 wherein the TTS comprises at least one of copper, nickel, or both. 5. The semiconductor die assembly of claim 1, further comprising an underfill material disposed between the molded wall and the stack and between the plurality of second semiconductor dies arranged in the stack. 6. The semiconductor die assembly of claim 3 wherein the first semiconductor die is a logic die that extends at least partially beyond other semiconductor dies and is attached to the support substrate and operatively coupled to a capacitor. 7. A semiconductor die assembly, comprising:
a support substrate; a first semiconductor die on the support substrate; a stack of second semiconductor dies on the first semiconductor die, wherein the second semiconductor dies have different functionality than the first semiconductor die; a molded material formed on the substrate and having substantially vertical surfaces defining a cavity, wherein the stack of second semiconductor dies is received in the cavity and spaced apart from the molded material; a thermal transfer lid having a first portion attached to the molded material and a second portion extending from the first portion, wherein the second portion of the thermal transfer lid is attached to the first semiconductor die. 8. The semiconductor die assembly of claim 7 wherein the molded wall covers an electronic component operatively coupled to the first semiconductor die in the stack. 9. The semiconductor die assembly of claim 7 wherein the molded wall further comprises at least one of an organic resin, nonorganic resin, epoxy, or a combination thereof. 10. The semiconductor die assembly of claim 7 wherein the thermal transfer lid comprises at least one of copper, nickel, or a combination thereof. 11. The semiconductor die assembly of claim 7, wherein the second portion of the thermal transfer lid is attached to a peripheral region of the first die located on the bottom of the stack, and wherein the peripheral region extends beyond the second semiconductor dies in the stack. 12. The semiconductor die assembly of claim 7 wherein the stack includes a logic die that extends at least partially beyond other semiconductor dies and is attached to the support substrate and operatively coupled to a capacitor, wherein the capacitor is operatively coupled to the support substrate. 13. The semiconductor die assembly of claim 7 wherein the thermal transfer lid has a plurality of passages. 14. The semiconductor die assembly of claim 7 wherein the stack comprises at least eight dies. 15. A method of manufacturing a semiconductor die assembly, the method comprising:
molding a material onto a support substrate and over a plurality of capacitors on the support substrate, wherein the molding material has cavity; after molding the material onto the support substrate, attaching a first die to the support substrate; positioning a plurality of semiconductor dies arranged in a stack over the first die, wherein at least the stack of second dies is within the cavity defined by the molding material; and attaching a thermal lid to the molding material. 16. The method of claim 15, further comprising disposing thermal interface material to a surface of the stack. 17. The method of claim 15, further comprising disposing underfill material between the two molded walls and the stack. 18. The method of claim 15, further comprising positioning a plurality of capacitors on a support substrate and reflowing the semiconductor die assembly after positioning the plurality of capacitors on the support substrate. 19. The method of claim 15, wherein attaching the thermal lid to the stack further comprises attaching a first portion of the thermal lid to a top of the stack and a second portion of the thermal lid to a peripheral region of the first die. 20. The method of claim 15, wherein positioning the plurality of semiconductor dies arranged in a stack over the first die the stack comprises positioning at least eight dies. | 2,800 |
11,404 | 11,404 | 15,028,153 | 2,844 | Disclosed is an attachable apparatus ( 100 ) and related methods for controlling one or more properties of light emitted by a light source. In various embodiments, the attachable lighting control apparatus may be secured to a surface ( 632 ), which in some instances may be on or near the light source ( 630 ). In various embodiments, a placement sensor ( 218 ) may detect that the attachable lighting control apparatus has been secured to the surface, and may activate the attachable lighting control apparatus. Activation may cause the attachable lighting control apparatus to, automatically or in response to one or more additional events, commission itself to control one or more properties of light emitted by the light source. In various embodiments, the attachable lighting control apparatus may generate and transmit to the light source a lighting instruction based on touch input received at one or more touch-sensitive sensors ( 216 ) of the attachable lighting control apparatus. | 1. An attachable lighting control apparatus, comprising:
one or more touch pads; a placement sensor to detect that the attachable lighting control apparatus is secured to a surface; a microcontroller configured to generate, based on touch input received at the one or more touch pads, a lighting instruction to cause the light source to emit light having one or more lighting properties; and a communication interface configured to wirelessly transmit the lighting instruction to the light source, wherein the microcontroller is further configured to transition the attachable lighting control apparatus from a first state in which the apparatus consumes a first amount of power to a second state in which the apparatus consumes a second amount of power that is greater than the first amount of power, in response to detection by the placement sensor that the apparatus is secured to a surface. 2. The attachable lighting control apparatus of claim 1, further comprising a battery to power the one or more touch pads, the microcontroller and the communication interface. 3. The attachable lighting control apparatus of claim 2, further comprising a photovoltaic cell to recharge the battery. 4. The attachable lighting control apparatus of claim 2, wherein the battery is an at least partially transparent lithium ion battery. 5. The attachable lighting control apparatus of claim 1, further comprising adhesive material to create an adhesive bond between the attachable lighting control apparatus and the surface. 6. The attachable lighting control apparatus of claim 1, further comprising a magnetic element to create a magnetic bond between the attachable lighting control apparatus and the surface. 7. The attachable lighting control apparatus of claim 1, further comprising a suction portion to create a suction-based bond between the attachable lighting control apparatus and the surface. 8. (canceled) 9. The attachable lighting control apparatus of claim 1, wherein the placement sensor comprises two or more electrodes configured to detect a change in resistance associated with the attachable lighting control apparatus. 10. (canceled) 11. The attachable lighting control apparatus of claim 1, wherein the placement sensor comprises an accelerometer to detect an orientation of the attachable lighting control apparatus, and the microcontroller is configured to perform the transition in response to a determination, based on output of the accelerometer, that the attachable lighting control device has remained stable for greater than a predetermined time interval. 12. The attachable lighting control apparatus of claim 1, wherein the microcontroller is configured to perform the transition responsive to detection of user contact with the one or more touch pads. 13. (canceled) 14. The attachable lighting control apparatus of claim 1, further comprising a commissioning module configured to establish two-way wireless communication with the light source. 15. The attachable lighting control apparatus of claim 14, further comprising a coded light sensor, wherein the commissioning module is configured to extract an identifier associated with the light source from a coded light signal received at the coded light sensor from the light source, and the microcontroller is configured to further base generation of the lighting instruction at least in part on the extracted identifier. 16. (canceled) 17. The attachable lighting control apparatus of claim 1, wherein the one or more touch pads comprise two or more concentric, ring-shaped touch pads, wherein the microcontroller is configured to generate the lighting instruction to cause the light source to emit light having first and second properties based on touch input received at first and second touch pads, respectively, of the two or more concentric, ring-shaped touch pads. 18. (canceled) 19. A method of commandeering and controlling a light source, comprising:
securing an attachable lighting control apparatus to a surface on or near the light source; initiating commissioning of the attachable lighting control apparatus for wireless control of one or more properties of light emitted by the light source; and providing touch input at one or more touch-sensitive sensors of the attachable lighting control apparatus to cause the attachable lighting control apparatus to generate, based on the touch input, a lighting instruction for wireless transmission to the light source, the lighting instruction to cause the light source to emit light having one or more lighting properties, wherein the initiating comprises exposing a coded light sensor of the attachable lighting control apparatus to a coded light signal emitted by the light source, to enable the apparatus to extract an identifier associated with the light source from the coded light signal. 20. The method of claim 19, further comprising exposing a photovoltaic cell to light from the light source to recharge a battery of the attachable lighting control apparatus. 21. (canceled) 22. The method of claim 19, wherein the initiating comprises removing a peelable cover from an adhesive surface of the attachable lighting control apparatus. 23. The method of claim 19, wherein the securing comprises creating suction between an adhesive surface of the attachable lighting control apparatus and the surface on or near the light source. 24. The method of claim 19, wherein the initiating comprises changing a resistance between two or more electrodes of the attachable lighting control apparatus. 25. (canceled) 26. (canceled) 27. An attachable lighting control apparatus adapted to be secured to a surface on or near a light source, comprising:
one or more touch-sensitive sensors; an adhesive surface to secure the attachable lighting control apparatus to the surface on or near the light source; a peelable cover that is removable to expose the adhesive surface and activate the attachable lighting control apparatus; a commissioning module to, on activation, establish two-way wireless communication with the light source; a microcontroller coupled to the one or more touch-sensitive sensors and configured to generate, based on touch input received at the one or more touch-sensitive sensors, a lighting instruction to cause the light source to emit light having one or more lighting properties; a communication interface coupled to the microcontroller and configured to wirelessly transmit the lighting instruction to the light source; a battery to power the one or more touch-sensitive sensors, the commissioning module, the microcontroller and the communication interface; and a photovoltaic cell to recharge the battery. 28. The attachable lighting control apparatus of claim 27, wherein prior to its removal, the peelable cover creates a separation between the battery and the microcontroller, such that removal of the peelable cover removes the separation to cause activation of the attachable lighting control apparatus. | Disclosed is an attachable apparatus ( 100 ) and related methods for controlling one or more properties of light emitted by a light source. In various embodiments, the attachable lighting control apparatus may be secured to a surface ( 632 ), which in some instances may be on or near the light source ( 630 ). In various embodiments, a placement sensor ( 218 ) may detect that the attachable lighting control apparatus has been secured to the surface, and may activate the attachable lighting control apparatus. Activation may cause the attachable lighting control apparatus to, automatically or in response to one or more additional events, commission itself to control one or more properties of light emitted by the light source. In various embodiments, the attachable lighting control apparatus may generate and transmit to the light source a lighting instruction based on touch input received at one or more touch-sensitive sensors ( 216 ) of the attachable lighting control apparatus.1. An attachable lighting control apparatus, comprising:
one or more touch pads; a placement sensor to detect that the attachable lighting control apparatus is secured to a surface; a microcontroller configured to generate, based on touch input received at the one or more touch pads, a lighting instruction to cause the light source to emit light having one or more lighting properties; and a communication interface configured to wirelessly transmit the lighting instruction to the light source, wherein the microcontroller is further configured to transition the attachable lighting control apparatus from a first state in which the apparatus consumes a first amount of power to a second state in which the apparatus consumes a second amount of power that is greater than the first amount of power, in response to detection by the placement sensor that the apparatus is secured to a surface. 2. The attachable lighting control apparatus of claim 1, further comprising a battery to power the one or more touch pads, the microcontroller and the communication interface. 3. The attachable lighting control apparatus of claim 2, further comprising a photovoltaic cell to recharge the battery. 4. The attachable lighting control apparatus of claim 2, wherein the battery is an at least partially transparent lithium ion battery. 5. The attachable lighting control apparatus of claim 1, further comprising adhesive material to create an adhesive bond between the attachable lighting control apparatus and the surface. 6. The attachable lighting control apparatus of claim 1, further comprising a magnetic element to create a magnetic bond between the attachable lighting control apparatus and the surface. 7. The attachable lighting control apparatus of claim 1, further comprising a suction portion to create a suction-based bond between the attachable lighting control apparatus and the surface. 8. (canceled) 9. The attachable lighting control apparatus of claim 1, wherein the placement sensor comprises two or more electrodes configured to detect a change in resistance associated with the attachable lighting control apparatus. 10. (canceled) 11. The attachable lighting control apparatus of claim 1, wherein the placement sensor comprises an accelerometer to detect an orientation of the attachable lighting control apparatus, and the microcontroller is configured to perform the transition in response to a determination, based on output of the accelerometer, that the attachable lighting control device has remained stable for greater than a predetermined time interval. 12. The attachable lighting control apparatus of claim 1, wherein the microcontroller is configured to perform the transition responsive to detection of user contact with the one or more touch pads. 13. (canceled) 14. The attachable lighting control apparatus of claim 1, further comprising a commissioning module configured to establish two-way wireless communication with the light source. 15. The attachable lighting control apparatus of claim 14, further comprising a coded light sensor, wherein the commissioning module is configured to extract an identifier associated with the light source from a coded light signal received at the coded light sensor from the light source, and the microcontroller is configured to further base generation of the lighting instruction at least in part on the extracted identifier. 16. (canceled) 17. The attachable lighting control apparatus of claim 1, wherein the one or more touch pads comprise two or more concentric, ring-shaped touch pads, wherein the microcontroller is configured to generate the lighting instruction to cause the light source to emit light having first and second properties based on touch input received at first and second touch pads, respectively, of the two or more concentric, ring-shaped touch pads. 18. (canceled) 19. A method of commandeering and controlling a light source, comprising:
securing an attachable lighting control apparatus to a surface on or near the light source; initiating commissioning of the attachable lighting control apparatus for wireless control of one or more properties of light emitted by the light source; and providing touch input at one or more touch-sensitive sensors of the attachable lighting control apparatus to cause the attachable lighting control apparatus to generate, based on the touch input, a lighting instruction for wireless transmission to the light source, the lighting instruction to cause the light source to emit light having one or more lighting properties, wherein the initiating comprises exposing a coded light sensor of the attachable lighting control apparatus to a coded light signal emitted by the light source, to enable the apparatus to extract an identifier associated with the light source from the coded light signal. 20. The method of claim 19, further comprising exposing a photovoltaic cell to light from the light source to recharge a battery of the attachable lighting control apparatus. 21. (canceled) 22. The method of claim 19, wherein the initiating comprises removing a peelable cover from an adhesive surface of the attachable lighting control apparatus. 23. The method of claim 19, wherein the securing comprises creating suction between an adhesive surface of the attachable lighting control apparatus and the surface on or near the light source. 24. The method of claim 19, wherein the initiating comprises changing a resistance between two or more electrodes of the attachable lighting control apparatus. 25. (canceled) 26. (canceled) 27. An attachable lighting control apparatus adapted to be secured to a surface on or near a light source, comprising:
one or more touch-sensitive sensors; an adhesive surface to secure the attachable lighting control apparatus to the surface on or near the light source; a peelable cover that is removable to expose the adhesive surface and activate the attachable lighting control apparatus; a commissioning module to, on activation, establish two-way wireless communication with the light source; a microcontroller coupled to the one or more touch-sensitive sensors and configured to generate, based on touch input received at the one or more touch-sensitive sensors, a lighting instruction to cause the light source to emit light having one or more lighting properties; a communication interface coupled to the microcontroller and configured to wirelessly transmit the lighting instruction to the light source; a battery to power the one or more touch-sensitive sensors, the commissioning module, the microcontroller and the communication interface; and a photovoltaic cell to recharge the battery. 28. The attachable lighting control apparatus of claim 27, wherein prior to its removal, the peelable cover creates a separation between the battery and the microcontroller, such that removal of the peelable cover removes the separation to cause activation of the attachable lighting control apparatus. | 2,800 |
11,405 | 11,405 | 15,246,200 | 2,847 | A coaxial cable includes: an inner conductor; a dielectric layer surrounding the inner conductor; an outer conductor surrounding the dielectric layer and having a plurality of corrugations, wherein each of the corrugations has a root and a crest connected by a transition section; a jacket surrounding the outer conductor; and a first adhesive layer interposed between the dielectric layer and the roots of the corrugations of the outer conductor. Each of the roots has a curved flattened portion that is adhered to the first adhesive layer. | 1. A coaxial cable, comprising:
an inner conductor; a dielectric layer surrounding the inner conductor; an outer conductor surrounding the dielectric layer and having a plurality of corrugations, wherein each of the corrugations has a root and a crest connected by a transition section; a jacket surrounding the outer conductor; and a first adhesive layer interposed between the dielectric layer and the roots of the corrugations of the outer conductor; wherein each of the roots has a curved flattened portion that is adhered to the first adhesive layer. 2. The coaxial cable defined in claim 1, further comprising a second adhesive layer interposed between the jacket and the crests of the corrugations of the outer conductor. 3. The coaxial cable defined in claim 1, wherein the root has a first radius of curvature, and the crest has a second radius of curvature that is less than the first radius of curvature. 4. The coaxial cable defined in claim 1, wherein the first adhesive layer is coextruded with the dielectric layer. 5. The coaxial cable defined in claim 1, wherein the first adhesive layer comprises polyethylene, ethylene methacrylic acid, ethylene methyl acrylate, ethylene vinyl acrylate, styrene-isoprene-styrene, and/or styrene-ethylene-butylene-styrene. 6. A coaxial cable, comprising:
an inner conductor; a dielectric layer surrounding the inner conductor; an outer conductor surrounding the dielectric layer and having a plurality of corrugations, wherein each of the corrugations has a root and a crest connected by a transition section; a jacket surrounding the outer conductor; a first adhesive layer interposed between the dielectric layer and the roots of the corrugations of the outer conductor; and a second adhesive layer interposed between the jacket and the crests of the corrugations of the outer conductor. 7. The coaxial cable defined in claim 6, wherein the root has a first radius of curvature, and the crest has a second radius of curvature that is less than the first radius of curvature. 8. The coaxial cable defined in claim 6, wherein the first adhesive layer is coextruded with the jacket. 9. The coaxial cable defined in claim 7, wherein the first adhesive layer comprises polyethylene, ethylene methacrylic acid, ethylene methyl acrylate, ethylene vinyl acrylate, styrene-isoprene-styrene, and/or styrene-ethylene-butylene-styrene. 10. A coaxial cable, comprising:
an inner conductor; a dielectric layer surrounding the inner conductor; an outer conductor surrounding the dielectric layer and having a plurality of annular corrugations, wherein each of the corrugations has a root and a crest connected by a transition section; a jacket surrounding the outer conductor; and a first adhesive layer interposed between the dielectric layer and the roots of the corrugations of the outer conductor. 11. The coaxial cable defined in claim 10, further comprising a second adhesive layer interposed between the jacket and the crests of the corrugations of the outer conductor. 12. The coaxial cable defined in claim 10, wherein the root has a first radius of curvature, and the crest has a second radius of curvature that is less than the first radius of curvature. 13. The coaxial cable defined in claim 10, wherein the first adhesive layer is coextruded with the dielectric layer. 14. The coaxial cable defined in claim 10, wherein the first adhesive layer comprises polyethylene, ethylene methacrylic acid, ethylene methyl acrylate, ethylene vinyl acrylate, styrene-isoprene-styrene, and/or styrene-ethylene-butylene-styrene. | A coaxial cable includes: an inner conductor; a dielectric layer surrounding the inner conductor; an outer conductor surrounding the dielectric layer and having a plurality of corrugations, wherein each of the corrugations has a root and a crest connected by a transition section; a jacket surrounding the outer conductor; and a first adhesive layer interposed between the dielectric layer and the roots of the corrugations of the outer conductor. Each of the roots has a curved flattened portion that is adhered to the first adhesive layer.1. A coaxial cable, comprising:
an inner conductor; a dielectric layer surrounding the inner conductor; an outer conductor surrounding the dielectric layer and having a plurality of corrugations, wherein each of the corrugations has a root and a crest connected by a transition section; a jacket surrounding the outer conductor; and a first adhesive layer interposed between the dielectric layer and the roots of the corrugations of the outer conductor; wherein each of the roots has a curved flattened portion that is adhered to the first adhesive layer. 2. The coaxial cable defined in claim 1, further comprising a second adhesive layer interposed between the jacket and the crests of the corrugations of the outer conductor. 3. The coaxial cable defined in claim 1, wherein the root has a first radius of curvature, and the crest has a second radius of curvature that is less than the first radius of curvature. 4. The coaxial cable defined in claim 1, wherein the first adhesive layer is coextruded with the dielectric layer. 5. The coaxial cable defined in claim 1, wherein the first adhesive layer comprises polyethylene, ethylene methacrylic acid, ethylene methyl acrylate, ethylene vinyl acrylate, styrene-isoprene-styrene, and/or styrene-ethylene-butylene-styrene. 6. A coaxial cable, comprising:
an inner conductor; a dielectric layer surrounding the inner conductor; an outer conductor surrounding the dielectric layer and having a plurality of corrugations, wherein each of the corrugations has a root and a crest connected by a transition section; a jacket surrounding the outer conductor; a first adhesive layer interposed between the dielectric layer and the roots of the corrugations of the outer conductor; and a second adhesive layer interposed between the jacket and the crests of the corrugations of the outer conductor. 7. The coaxial cable defined in claim 6, wherein the root has a first radius of curvature, and the crest has a second radius of curvature that is less than the first radius of curvature. 8. The coaxial cable defined in claim 6, wherein the first adhesive layer is coextruded with the jacket. 9. The coaxial cable defined in claim 7, wherein the first adhesive layer comprises polyethylene, ethylene methacrylic acid, ethylene methyl acrylate, ethylene vinyl acrylate, styrene-isoprene-styrene, and/or styrene-ethylene-butylene-styrene. 10. A coaxial cable, comprising:
an inner conductor; a dielectric layer surrounding the inner conductor; an outer conductor surrounding the dielectric layer and having a plurality of annular corrugations, wherein each of the corrugations has a root and a crest connected by a transition section; a jacket surrounding the outer conductor; and a first adhesive layer interposed between the dielectric layer and the roots of the corrugations of the outer conductor. 11. The coaxial cable defined in claim 10, further comprising a second adhesive layer interposed between the jacket and the crests of the corrugations of the outer conductor. 12. The coaxial cable defined in claim 10, wherein the root has a first radius of curvature, and the crest has a second radius of curvature that is less than the first radius of curvature. 13. The coaxial cable defined in claim 10, wherein the first adhesive layer is coextruded with the dielectric layer. 14. The coaxial cable defined in claim 10, wherein the first adhesive layer comprises polyethylene, ethylene methacrylic acid, ethylene methyl acrylate, ethylene vinyl acrylate, styrene-isoprene-styrene, and/or styrene-ethylene-butylene-styrene. | 2,800 |
11,406 | 11,406 | 15,238,862 | 2,845 | Aspects of methods and systems for interleaved multi-band antenna arrays are provided. An array based communications system may comprise element processors and antenna elements. Each element processor of a first plurality of element processors may communicate in a first communication band via an antenna element in a first antenna array. Each element processor of a second plurality of element processors may communicate in a second communication band via an antenna element in a second antenna array. One or more antenna elements of the second antenna array may be positioned between antenna elements of the first antenna array. | 1. An array based communications system comprising:
a first plurality of element processors, each element processor of the first plurality of element processors being operable to communicate in a first communication band, each element processor of the first plurality of element processors being operably coupled to an antenna element in a first antenna array; and a second plurality of element processors, each element processor of the second plurality of element processors being operable to communicate in a second communication band, each element processor of the second plurality of element processors being operably coupled to an antenna element in a second antenna array, one or more antenna elements of the second antenna array being positioned between antenna elements of the first antenna array. 2. The array based communications system of claim 1, wherein the first communication band is the Ku band and the second communication band is the Ka band. 3. The array based communications system of claim 1, wherein each antenna element of first antenna array and the second antenna array is a horn mounted to a printed circuit board with waveguide feed lines. 4. The array based communications system of claim 1, wherein at least one element processor of the first plurality of element processors is operably coupled to the same antenna element as at least one element processor of the second plurality of element processors. 5. The array based communications system of claim 1, wherein a third antenna array comprises the first antenna array and the second antenna array, the center of the third antenna array having a highest power density. 6. The array based communications system of claim 1, wherein each antenna element of the first antenna array is equally spaced over an area and each antenna element of the second antenna array is positioned away from the center of the area. 7. The array based communications system of claim 1, wherein the first antenna array comprises sixteen antenna elements that are equally spaced over an area and the second antenna array comprises sixteen antenna elements that are grouped into four groups of four antenna elements, each group of four antenna elements being located at a corresponding corner of the area, each group of four antenna elements being spaced closer together than the antenna elements of the first antenna array. 8. A method for array based communications, the method comprising:
communicating in a first communication band using a first antenna array; and communicating in a second communication band using a second antenna array, one or more antenna elements of the second antenna array being positioned between antenna elements of the first antenna array. 9. The method of claim 8, wherein the first communication band is the Ku band and the second communication band is the Ka band. 10. The method of claim 8, wherein each antenna element of first antenna array and the second antenna array is a horn mounted to a printed circuit board with waveguide feed lines. 11. The method of claim 8, wherein at least one element processor of a first plurality of element processors is operably coupled to the same antenna element as at least one element processor of a second plurality of element processors. 12. The method of claim 8, wherein a third antenna array comprises the first antenna array and the second antenna array, the center of the third antenna array having a highest power density. 13. The method of claim 8, wherein each antenna element of the first antenna array is equally spaced over an area and each antenna element of the second antenna array is positioned away from the center of the area. 14. The method of claim 8, wherein the first antenna array comprises sixteen antenna elements that are equally spaced over an area and the second antenna array comprises sixteen antenna elements that are grouped into four groups of four antenna elements, each group of four antenna elements being located at a corresponding corner of the area, each group of four antenna elements being spaced closer together than the antenna elements of the first antenna array. 15. A method for array based communications, the method comprising:
positioning antenna elements of a first antenna array, the first antenna array being operable to communicate signals in a first communication band; and positioning one or more antenna elements of a second antenna array between antenna elements of the first antenna array, the second antenna array being operable to communicate signals in a second communication band. 16. The method of claim 15, wherein the first communication band is the Ku band and the second communication band is the Ka band. 17. The method of claim 15, wherein each antenna element of first antenna array and the second antenna array is a horn mounted to a printed circuit board with waveguide feed lines. 18. The method of claim 15, wherein the first antenna array and the second antenna array share at least one antenna element. 19. The method of claim 15, wherein antenna elements of the first antenna array having the highest power density are positioned toward the center of the first antenna array. 20. The method of claim 8, wherein each antenna element of the first antenna array is equally spaced apart in a rectangular area, the antenna elements of the second antenna array being grouped into four groups of antenna elements, each group of antenna elements in the second antenna array being located at a corresponding corner of the rectangular area, the antenna elements in each group antenna elements being spaced closer together than the antenna elements of the first antenna array. | Aspects of methods and systems for interleaved multi-band antenna arrays are provided. An array based communications system may comprise element processors and antenna elements. Each element processor of a first plurality of element processors may communicate in a first communication band via an antenna element in a first antenna array. Each element processor of a second plurality of element processors may communicate in a second communication band via an antenna element in a second antenna array. One or more antenna elements of the second antenna array may be positioned between antenna elements of the first antenna array.1. An array based communications system comprising:
a first plurality of element processors, each element processor of the first plurality of element processors being operable to communicate in a first communication band, each element processor of the first plurality of element processors being operably coupled to an antenna element in a first antenna array; and a second plurality of element processors, each element processor of the second plurality of element processors being operable to communicate in a second communication band, each element processor of the second plurality of element processors being operably coupled to an antenna element in a second antenna array, one or more antenna elements of the second antenna array being positioned between antenna elements of the first antenna array. 2. The array based communications system of claim 1, wherein the first communication band is the Ku band and the second communication band is the Ka band. 3. The array based communications system of claim 1, wherein each antenna element of first antenna array and the second antenna array is a horn mounted to a printed circuit board with waveguide feed lines. 4. The array based communications system of claim 1, wherein at least one element processor of the first plurality of element processors is operably coupled to the same antenna element as at least one element processor of the second plurality of element processors. 5. The array based communications system of claim 1, wherein a third antenna array comprises the first antenna array and the second antenna array, the center of the third antenna array having a highest power density. 6. The array based communications system of claim 1, wherein each antenna element of the first antenna array is equally spaced over an area and each antenna element of the second antenna array is positioned away from the center of the area. 7. The array based communications system of claim 1, wherein the first antenna array comprises sixteen antenna elements that are equally spaced over an area and the second antenna array comprises sixteen antenna elements that are grouped into four groups of four antenna elements, each group of four antenna elements being located at a corresponding corner of the area, each group of four antenna elements being spaced closer together than the antenna elements of the first antenna array. 8. A method for array based communications, the method comprising:
communicating in a first communication band using a first antenna array; and communicating in a second communication band using a second antenna array, one or more antenna elements of the second antenna array being positioned between antenna elements of the first antenna array. 9. The method of claim 8, wherein the first communication band is the Ku band and the second communication band is the Ka band. 10. The method of claim 8, wherein each antenna element of first antenna array and the second antenna array is a horn mounted to a printed circuit board with waveguide feed lines. 11. The method of claim 8, wherein at least one element processor of a first plurality of element processors is operably coupled to the same antenna element as at least one element processor of a second plurality of element processors. 12. The method of claim 8, wherein a third antenna array comprises the first antenna array and the second antenna array, the center of the third antenna array having a highest power density. 13. The method of claim 8, wherein each antenna element of the first antenna array is equally spaced over an area and each antenna element of the second antenna array is positioned away from the center of the area. 14. The method of claim 8, wherein the first antenna array comprises sixteen antenna elements that are equally spaced over an area and the second antenna array comprises sixteen antenna elements that are grouped into four groups of four antenna elements, each group of four antenna elements being located at a corresponding corner of the area, each group of four antenna elements being spaced closer together than the antenna elements of the first antenna array. 15. A method for array based communications, the method comprising:
positioning antenna elements of a first antenna array, the first antenna array being operable to communicate signals in a first communication band; and positioning one or more antenna elements of a second antenna array between antenna elements of the first antenna array, the second antenna array being operable to communicate signals in a second communication band. 16. The method of claim 15, wherein the first communication band is the Ku band and the second communication band is the Ka band. 17. The method of claim 15, wherein each antenna element of first antenna array and the second antenna array is a horn mounted to a printed circuit board with waveguide feed lines. 18. The method of claim 15, wherein the first antenna array and the second antenna array share at least one antenna element. 19. The method of claim 15, wherein antenna elements of the first antenna array having the highest power density are positioned toward the center of the first antenna array. 20. The method of claim 8, wherein each antenna element of the first antenna array is equally spaced apart in a rectangular area, the antenna elements of the second antenna array being grouped into four groups of antenna elements, each group of antenna elements in the second antenna array being located at a corresponding corner of the rectangular area, the antenna elements in each group antenna elements being spaced closer together than the antenna elements of the first antenna array. | 2,800 |
11,407 | 11,407 | 14,643,195 | 2,846 | A vehicle includes an electric machine and a controller configured to inject a voltage into the electric machine. The controller measures the currents caused by the voltage and processes the currents using a discrete Fourier transform to determine positive and negative sequence currents. A phase rotation sequence is identified by comparing the sequence currents to expected positive and negative sequence currents that are associated with possible phase rotation sequences. The electric machine may be controlled according to the identified phase rotation sequence. A cable swapped diagnostic may be output when the phase rotation sequence is different than an expected phase rotation sequence. | 1. A vehicle comprising:
a controller programmed to, in response to a power-on condition, inject a voltage having a predetermined phase rotation sequence into a three-phase electric machine and output a signal indicative of a phase rotation sequence based on a comparison of predetermined sequence current magnitudes and sequence current magnitudes associated with a current flowing through the three-phase electric machine. 2. The vehicle of claim 1 wherein the controller is further programmed to, in response to the signal indicating that the phase rotation sequence is different than the predetermined phase rotation sequence, output a cable swapped diagnostic. 3. The vehicle of claim 1 wherein the predetermined sequence current magnitudes are based on an inductance of the three-phase electric machine. 4. The vehicle of claim 1 wherein the predetermined sequence current magnitudes are based on a magnitude of the voltage. 5. The vehicle of claim 1 wherein the predetermined sequence current magnitudes are based on a frequency of the voltage. 6. The vehicle of claim 1 wherein the sequence current magnitudes associated with the current are derived from a discrete Fourier transform of measurements of the current. 7. The vehicle of claim 1 wherein the controller is further programmed to operate the three-phase electric machine according to the signal to cause the three-phase electric machine to rotate in a predetermined direction corresponding to the predetermined phase rotation sequence. 8. The vehicle of claim 1 wherein the voltage has a predetermined frequency and a predetermined magnitude such that the three-phase electric machine does not rotate when the voltage is injected. 9. The vehicle of claim 1 wherein the power-on condition includes a speed of the vehicle being approximately zero and a torque request to the three-phase electric machine being approximately zero. 10. The vehicle of claim 1 wherein the predetermined sequence current magnitudes include sequence current magnitudes associated with the predetermined phase rotation sequence. 11. A vehicle comprising:
an electric machine that rotates in a predetermined direction in response to application of a predetermined phase rotation sequence; and a controller programmed to inject a voltage with the predetermined phase rotation sequence into the electric machine and output a signal indicative of a phase rotation sequence based on a comparison of predetermined sequence current magnitudes and sequence current magnitudes associated with a current caused by a voltage. 12. The vehicle of claim 11 wherein the controller is further programmed to, in response to the signal indicating that the phase rotation sequence is different than the predetermined phase rotation sequence, output a cable swapped diagnostic. 13. The vehicle of claim 11 wherein the controller is further programmed to, in response to the signal indicating that the phase rotation sequence is different than the predetermined phase rotation sequence, disable operation of the electric machine. 14. The vehicle of claim 11 wherein the controller is further programmed to operate the electric machine according to the signal indicative of the phase rotation sequence to cause the electric machine to rotate in a predetermined direction corresponding to the predetermined phase rotation sequence. 15. The vehicle of claim 11 wherein the predetermined sequence current magnitudes are based on one or more of an inductance of the electric machine, a magnitude of the voltage, and a frequency of the voltage. 16. A method comprising:
applying, by a controller, voltage to an electric machine based on an injection voltage reference; and operating, by the controller, the electric machine based on a phase rotation sequence derived from a comparison of predetermined sequence current magnitudes and sequence current magnitudes associated with a current caused by the voltage. 17. The method of claim 16 wherein the predetermined sequence current magnitudes are based on parameters of the injection voltage reference and parameters of the electric machine. 18. The method of claim 16 wherein the sequence current magnitudes are based on a discrete Fourier transform of measurements of the current. 19. The method of claim 16 wherein a frequency of the injection voltage reference is a predetermined multiple of a switching frequency corresponding to a rate at which the voltage is changed. 20. The method of claim 16 further comprising outputting, by the controller, a cable swapped diagnostic in response to the phase rotation sequence being different than an expected phase rotation sequence. | A vehicle includes an electric machine and a controller configured to inject a voltage into the electric machine. The controller measures the currents caused by the voltage and processes the currents using a discrete Fourier transform to determine positive and negative sequence currents. A phase rotation sequence is identified by comparing the sequence currents to expected positive and negative sequence currents that are associated with possible phase rotation sequences. The electric machine may be controlled according to the identified phase rotation sequence. A cable swapped diagnostic may be output when the phase rotation sequence is different than an expected phase rotation sequence.1. A vehicle comprising:
a controller programmed to, in response to a power-on condition, inject a voltage having a predetermined phase rotation sequence into a three-phase electric machine and output a signal indicative of a phase rotation sequence based on a comparison of predetermined sequence current magnitudes and sequence current magnitudes associated with a current flowing through the three-phase electric machine. 2. The vehicle of claim 1 wherein the controller is further programmed to, in response to the signal indicating that the phase rotation sequence is different than the predetermined phase rotation sequence, output a cable swapped diagnostic. 3. The vehicle of claim 1 wherein the predetermined sequence current magnitudes are based on an inductance of the three-phase electric machine. 4. The vehicle of claim 1 wherein the predetermined sequence current magnitudes are based on a magnitude of the voltage. 5. The vehicle of claim 1 wherein the predetermined sequence current magnitudes are based on a frequency of the voltage. 6. The vehicle of claim 1 wherein the sequence current magnitudes associated with the current are derived from a discrete Fourier transform of measurements of the current. 7. The vehicle of claim 1 wherein the controller is further programmed to operate the three-phase electric machine according to the signal to cause the three-phase electric machine to rotate in a predetermined direction corresponding to the predetermined phase rotation sequence. 8. The vehicle of claim 1 wherein the voltage has a predetermined frequency and a predetermined magnitude such that the three-phase electric machine does not rotate when the voltage is injected. 9. The vehicle of claim 1 wherein the power-on condition includes a speed of the vehicle being approximately zero and a torque request to the three-phase electric machine being approximately zero. 10. The vehicle of claim 1 wherein the predetermined sequence current magnitudes include sequence current magnitudes associated with the predetermined phase rotation sequence. 11. A vehicle comprising:
an electric machine that rotates in a predetermined direction in response to application of a predetermined phase rotation sequence; and a controller programmed to inject a voltage with the predetermined phase rotation sequence into the electric machine and output a signal indicative of a phase rotation sequence based on a comparison of predetermined sequence current magnitudes and sequence current magnitudes associated with a current caused by a voltage. 12. The vehicle of claim 11 wherein the controller is further programmed to, in response to the signal indicating that the phase rotation sequence is different than the predetermined phase rotation sequence, output a cable swapped diagnostic. 13. The vehicle of claim 11 wherein the controller is further programmed to, in response to the signal indicating that the phase rotation sequence is different than the predetermined phase rotation sequence, disable operation of the electric machine. 14. The vehicle of claim 11 wherein the controller is further programmed to operate the electric machine according to the signal indicative of the phase rotation sequence to cause the electric machine to rotate in a predetermined direction corresponding to the predetermined phase rotation sequence. 15. The vehicle of claim 11 wherein the predetermined sequence current magnitudes are based on one or more of an inductance of the electric machine, a magnitude of the voltage, and a frequency of the voltage. 16. A method comprising:
applying, by a controller, voltage to an electric machine based on an injection voltage reference; and operating, by the controller, the electric machine based on a phase rotation sequence derived from a comparison of predetermined sequence current magnitudes and sequence current magnitudes associated with a current caused by the voltage. 17. The method of claim 16 wherein the predetermined sequence current magnitudes are based on parameters of the injection voltage reference and parameters of the electric machine. 18. The method of claim 16 wherein the sequence current magnitudes are based on a discrete Fourier transform of measurements of the current. 19. The method of claim 16 wherein a frequency of the injection voltage reference is a predetermined multiple of a switching frequency corresponding to a rate at which the voltage is changed. 20. The method of claim 16 further comprising outputting, by the controller, a cable swapped diagnostic in response to the phase rotation sequence being different than an expected phase rotation sequence. | 2,800 |
11,408 | 11,408 | 15,159,087 | 2,868 | A high voltage isolation tester has a high voltage side and a low voltage side coupled to each other by isolation amplifiers so that the high and low voltage sides are electrically isolated from each other. The high voltage side includes positive and negative high voltage test inputs and a common test input. The high voltage side also includes a positive switched voltage divider network and a negative switched voltage divider network. The low voltage side includes a controller that automatically controls switching of the switched voltage divider networks to make voltage measurements of voltages at inputs of the isolation amplifiers. Outputs of the isolation amplifiers are coupled to inputs of an analog-to-digital converter and the digitized voltages are read from the analog-to-digital converter by the controller. | 1. A high voltage isolation tester, comprising:
a high voltage side and a low voltage side that are coupled to each other by isolation amplifiers; the high voltage side having a positive test input coupled by a positive side switched voltage divider network to an input of a first one of the isolation amplifiers, the positive side switched voltage divider network having first and second resistances that have different resistivities, a negative test input coupled by a negative side switched voltage divider network to an input of a second one of the isolation amplifiers, the negative side switched voltage divider network having third and fourth resistances that have different resistivities, and a common test input; the positive test input and the negative test input also coupled to opposite sides of a voltage divider network of resistances with a junction of the resistances coupled to an input of a third one of the isolation amplifiers; the low voltage side including an analog-to-digital converter to which outputs of the isolation amplifiers are coupled and a controller that controls switching of the switched voltage divider networks, reads from the analog-to-digital converter digitized data of voltage measurements of voltages across the high voltage test input and common test input, voltages across the negative high voltage test input and the common test input, and a voltage across the positive and negative high voltage test inputs; and the controller configured with control logic to switch the positive side switched voltage divider network to couple the positive high voltage test input to the input of the first isolation amplifier through the first resistance and then through the second resistance and take voltage measurements of the voltage at the input of the first isolation amplifier when the positive high voltage test input is coupled to the input of the first isolation amplifier through the first resistance and also when the positive high voltage test input is coupled to the input of the first isolation amplifier through the second resistance, the controller also configured with control logic to switch the negative side switched voltage divider network to couple the negative high voltage test input to the input of the second isolation amplifier through the third resistance and then through the fourth resistance and take voltage measurements of the voltage at the input of the second isolation amplifier when the negative high voltage test input is coupled to the input of the second isolation amplifier through the third resistance and also when the negative high voltage test input is coupled to the input of the second isolation amplifier through the fourth resistance, the controller also configured with control logic to take a voltage measurement of a voltage at the input of the third isolation amplifier. 2. The tester of claim 1 wherein the controller is configured with control logic to determine isolation between the positive high voltage test input and the common test input and isolation between the negative high voltage test input and common test input based on the voltage measurements of the voltages at the inputs of the first and second isolation amplifiers. 3. The tester of claim 2 wherein the controller is configured with control logic to communicate each determined isolation to a desired destination. 4. The tester of claim 1 wherein the controller is configured with control logic to communicate the voltage measurements to a desired destination. | A high voltage isolation tester has a high voltage side and a low voltage side coupled to each other by isolation amplifiers so that the high and low voltage sides are electrically isolated from each other. The high voltage side includes positive and negative high voltage test inputs and a common test input. The high voltage side also includes a positive switched voltage divider network and a negative switched voltage divider network. The low voltage side includes a controller that automatically controls switching of the switched voltage divider networks to make voltage measurements of voltages at inputs of the isolation amplifiers. Outputs of the isolation amplifiers are coupled to inputs of an analog-to-digital converter and the digitized voltages are read from the analog-to-digital converter by the controller.1. A high voltage isolation tester, comprising:
a high voltage side and a low voltage side that are coupled to each other by isolation amplifiers; the high voltage side having a positive test input coupled by a positive side switched voltage divider network to an input of a first one of the isolation amplifiers, the positive side switched voltage divider network having first and second resistances that have different resistivities, a negative test input coupled by a negative side switched voltage divider network to an input of a second one of the isolation amplifiers, the negative side switched voltage divider network having third and fourth resistances that have different resistivities, and a common test input; the positive test input and the negative test input also coupled to opposite sides of a voltage divider network of resistances with a junction of the resistances coupled to an input of a third one of the isolation amplifiers; the low voltage side including an analog-to-digital converter to which outputs of the isolation amplifiers are coupled and a controller that controls switching of the switched voltage divider networks, reads from the analog-to-digital converter digitized data of voltage measurements of voltages across the high voltage test input and common test input, voltages across the negative high voltage test input and the common test input, and a voltage across the positive and negative high voltage test inputs; and the controller configured with control logic to switch the positive side switched voltage divider network to couple the positive high voltage test input to the input of the first isolation amplifier through the first resistance and then through the second resistance and take voltage measurements of the voltage at the input of the first isolation amplifier when the positive high voltage test input is coupled to the input of the first isolation amplifier through the first resistance and also when the positive high voltage test input is coupled to the input of the first isolation amplifier through the second resistance, the controller also configured with control logic to switch the negative side switched voltage divider network to couple the negative high voltage test input to the input of the second isolation amplifier through the third resistance and then through the fourth resistance and take voltage measurements of the voltage at the input of the second isolation amplifier when the negative high voltage test input is coupled to the input of the second isolation amplifier through the third resistance and also when the negative high voltage test input is coupled to the input of the second isolation amplifier through the fourth resistance, the controller also configured with control logic to take a voltage measurement of a voltage at the input of the third isolation amplifier. 2. The tester of claim 1 wherein the controller is configured with control logic to determine isolation between the positive high voltage test input and the common test input and isolation between the negative high voltage test input and common test input based on the voltage measurements of the voltages at the inputs of the first and second isolation amplifiers. 3. The tester of claim 2 wherein the controller is configured with control logic to communicate each determined isolation to a desired destination. 4. The tester of claim 1 wherein the controller is configured with control logic to communicate the voltage measurements to a desired destination. | 2,800 |
11,409 | 11,409 | 14,219,039 | 2,829 | Aspects of the present invention relate to approaches for forming a semiconductor device such as a field-effect-transistor (FET) having a metal gate with improved performance. A metal gate is formed on a substrate in the semiconductor device. Further processing can result in unwanted oxidation in the metal that forms the metal gate. A reducing agent can be used to de-oxidize the metal that forms the metal gate, leaving a substantially non-oxidized surface. | 1. A method for improving a performance of a metal gate in a semiconductor device, comprising:
forming the metal gate on a substrate in the semiconductor device; and de-oxidizing, using a reducing agent, an oxidation layer formed on the metal gate. 2. The method of claim 1, wherein the reducing agent is selected from a group, consisting of: an H2 plasma, an H2/N2 plasma, a CH4 plasma, or an NH3 forming gas. 3. The method of claim 2, wherein the de-oxidizing is performed using an in-situ treatment with the reducing agent prior to a SiN hardmask deposition. 4. The method of claim 2, wherein the de-oxidizing is performed using an in-situ treatment with the reducing agent subsequent to a forming of a trench to the metal gate through a hardmask. 5. The method of claim 1, wherein the oxidation layer is formed by an oxidation of the metal gate resulting from an open-air environment. 6. The method of claim 1, further comprising:
forming a tungsten contact to the metal gate, wherein the de-oxidizing reduces a susceptibility of the metal gate to encroachment by the tungsten contact. 7. The method of claim 1,
wherein the metal gate comprises aluminum, and wherein the oxidation layer comprises aluminum oxide formed by the interaction of the aluminum in the metal gate with oxygen. 8. The method of claim 7, wherein the metal gate is a replacement metal gate in a replacement metal gate transistor. 9. The method of claim 1, further comprising a semiconductor device formed according to the method of claim 1. 10. A method for improving a performance of a metal gate in a semiconductor device having a gate stack formed on substrate, comprising:
removing a dummy gate from the gate stack formed on a substrate; depositing a series of metal layers in a recess resulting from the removing of the dummy gate to form a replacement metal gate; planarizing the replacement metal gate using a chemical mechanical planarization (CMP) process; and applying a reducing agent to the planarized replacement metal gate to de-oxidize a layer of oxidation in the metal gate formed as a result of the CMP process. 11. The method of claim 10, wherein the reducing agent is selected from a group, consisting of: an H2 plasma, an H2/N2 plasma, a CH4 plasma, or an NH3 forming gas. 12. The method of claim 11, wherein the de-oxidizing is performed using an in-situ treatment with the reducing agent prior to a SiN hardmask deposition. 13. The method of claim 11, wherein the de-oxidizing is performed using an in-situ treatment with the reducing agent subsequent to a forming of a trench to the replacement metal gate through a hardmask. 14. The method of claim 10, wherein the oxidation layer is formed by an oxidation of the replacement metal gate resulting from performing the CMP process in an open-air environment. 15. The method of claim 10, further comprising:
forming a tungsten contact to the gate, wherein the de-oxidizing reduces a susceptibility of the replacement metal gate to encroachment by the tungsten contact. 16. The method of claim 10,
wherein the metal gate comprises aluminum, and wherein the oxidation layer comprises aluminum oxide formed by the interaction of the aluminum in the metal gate with oxygen. 17. The method of claim 16, wherein the semiconductor device is a replacement metal gate transistor. 18. A semiconductor device, comprising:
a substrate; an NFET region and a PFET region formed on the substrate; a set of raised source-drain (RSD) regions formed on each of the NFET region and the PFET region; a replacement metal gate formed on each of the NFET region and the PFET region, the replacement metal gate having a de-oxidized layer formed by de-oxidizing a portion of the replacement metal gate using a de-oxidizing agent; and a contact to the de-oxidized layer of the replacement metal gate. 19. The method of claim 18,
wherein the metal gate comprises aluminum, wherein the contact comprises tungsten, and wherein the de-oxidizing reduces a susceptibility of the replacement metal gate to encroachment by the tungsten contact. 20. The method of claim 18, wherein the reducing agent is selected from a group, consisting of: an H2 plasma, an H2/N2 plasma, a CH4 plasma, or an NH3 forming gas. | Aspects of the present invention relate to approaches for forming a semiconductor device such as a field-effect-transistor (FET) having a metal gate with improved performance. A metal gate is formed on a substrate in the semiconductor device. Further processing can result in unwanted oxidation in the metal that forms the metal gate. A reducing agent can be used to de-oxidize the metal that forms the metal gate, leaving a substantially non-oxidized surface.1. A method for improving a performance of a metal gate in a semiconductor device, comprising:
forming the metal gate on a substrate in the semiconductor device; and de-oxidizing, using a reducing agent, an oxidation layer formed on the metal gate. 2. The method of claim 1, wherein the reducing agent is selected from a group, consisting of: an H2 plasma, an H2/N2 plasma, a CH4 plasma, or an NH3 forming gas. 3. The method of claim 2, wherein the de-oxidizing is performed using an in-situ treatment with the reducing agent prior to a SiN hardmask deposition. 4. The method of claim 2, wherein the de-oxidizing is performed using an in-situ treatment with the reducing agent subsequent to a forming of a trench to the metal gate through a hardmask. 5. The method of claim 1, wherein the oxidation layer is formed by an oxidation of the metal gate resulting from an open-air environment. 6. The method of claim 1, further comprising:
forming a tungsten contact to the metal gate, wherein the de-oxidizing reduces a susceptibility of the metal gate to encroachment by the tungsten contact. 7. The method of claim 1,
wherein the metal gate comprises aluminum, and wherein the oxidation layer comprises aluminum oxide formed by the interaction of the aluminum in the metal gate with oxygen. 8. The method of claim 7, wherein the metal gate is a replacement metal gate in a replacement metal gate transistor. 9. The method of claim 1, further comprising a semiconductor device formed according to the method of claim 1. 10. A method for improving a performance of a metal gate in a semiconductor device having a gate stack formed on substrate, comprising:
removing a dummy gate from the gate stack formed on a substrate; depositing a series of metal layers in a recess resulting from the removing of the dummy gate to form a replacement metal gate; planarizing the replacement metal gate using a chemical mechanical planarization (CMP) process; and applying a reducing agent to the planarized replacement metal gate to de-oxidize a layer of oxidation in the metal gate formed as a result of the CMP process. 11. The method of claim 10, wherein the reducing agent is selected from a group, consisting of: an H2 plasma, an H2/N2 plasma, a CH4 plasma, or an NH3 forming gas. 12. The method of claim 11, wherein the de-oxidizing is performed using an in-situ treatment with the reducing agent prior to a SiN hardmask deposition. 13. The method of claim 11, wherein the de-oxidizing is performed using an in-situ treatment with the reducing agent subsequent to a forming of a trench to the replacement metal gate through a hardmask. 14. The method of claim 10, wherein the oxidation layer is formed by an oxidation of the replacement metal gate resulting from performing the CMP process in an open-air environment. 15. The method of claim 10, further comprising:
forming a tungsten contact to the gate, wherein the de-oxidizing reduces a susceptibility of the replacement metal gate to encroachment by the tungsten contact. 16. The method of claim 10,
wherein the metal gate comprises aluminum, and wherein the oxidation layer comprises aluminum oxide formed by the interaction of the aluminum in the metal gate with oxygen. 17. The method of claim 16, wherein the semiconductor device is a replacement metal gate transistor. 18. A semiconductor device, comprising:
a substrate; an NFET region and a PFET region formed on the substrate; a set of raised source-drain (RSD) regions formed on each of the NFET region and the PFET region; a replacement metal gate formed on each of the NFET region and the PFET region, the replacement metal gate having a de-oxidized layer formed by de-oxidizing a portion of the replacement metal gate using a de-oxidizing agent; and a contact to the de-oxidized layer of the replacement metal gate. 19. The method of claim 18,
wherein the metal gate comprises aluminum, wherein the contact comprises tungsten, and wherein the de-oxidizing reduces a susceptibility of the replacement metal gate to encroachment by the tungsten contact. 20. The method of claim 18, wherein the reducing agent is selected from a group, consisting of: an H2 plasma, an H2/N2 plasma, a CH4 plasma, or an NH3 forming gas. | 2,800 |
11,410 | 11,410 | 13,704,059 | 2,864 | A power-consumption monitoring device, for taking measurements of the power consumed by an appliance. The device is connectable to a mains electrical circuit and operable to transmit the measurements to a master device through the circuit. The device is adapted: to measure the energy consumed by the appliance in each of a series of time intervals, and maintain a first cumulative sum of the resulting energy measurements; to periodically transmit, to the master device, a first quantised value representing the cumulative sum; and to subtract the transmitted quantised value from the cumulative sum. | 1. A power-consumption monitoring device, for taking measurements of the power consumed by an appliance,
the device being connectable to a mains electrical circuit and operable to transmit the measurements to a master device through the circuit, wherein the device is adapted:
to measure the energy consumed by the appliance in each of a series of time intervals, and maintain a first cumulative sum of the resulting energy measurements;
to periodically transmit, to the master device, a first quantised value representing the cumulative sum; and
to subtract the transmitted quantised value from the cumulative sum. 2. The power-consumption monitoring device of claim 1, wherein the quantisation used to generate the first quantised value is non-uniform. 3. The power-consumption monitoring device of claim 2, wherein the quantisation comprises floating point quantisation. 4. The power-consumption monitoring device of claim 1, wherein the device is further adapted:
to maintain a second cumulative sum of the energy measurements; and to intermittently transmit the value of the second cumulative sum to the master device. 5. The power-consumption monitoring device of claim 4, wherein the value of the second cumulative sum is transmitted in place of one of the periodic transmissions of the first cumulative sum. 6. The power-consumption monitoring device of claim 1, wherein the device is adapted to:
receive a spread-spectrum timing-reference signal from the master device; detect a code-phase of the received reference signal; and transmit the measurements to the master device with a timing that is defined relative to the detected code-phase. 7. The power-consumption monitoring device according to claim 6, wherein the spread-spectrum reference signal is periodically modulated by a synchronisation symbol,
the monitoring device being adapted to:
determine a timing by detecting the synchronisation symbol. 8. The power-consumption monitoring device according to claim 6, comprising a time-domain correlator for detecting the code-phase. 9. The power-consumption monitoring device according to claim 6, wherein the monitoring device is adapted to transmit to the master device an upstream signal which comprises a spreading code modulated by a data message, the data message including the power measurements,
a transmit time-interval in which the upstream signal is transmitted and/or a transmit code-phase of the spreading code being defined relative to the detected code-phase of the reference signal. 10. The power-consumption monitoring device according to claim 9, wherein the monitoring device has:
a configuration mode, in which it is adapted to:
transmit the upstream signal using a first, predetermined time interval and/or code-phase reserved for negotiation with the master device; and
receive, from the master device, configuration information assigning a second, different time interval and/or code-phase, and
a normal mode in which it is adapted to:
transmit the upstream signal using the assigned, second time interval and/or code-phase. 11. The power consumption monitoring device according to claim 9, wherein the device is adapted to transmit the upstream signal in a frequency band that is different from the frequency band of the spread-spectrum timing-reference signal received from the master device. 12. A method of monitoring power-consumption, for taking measurements of power consumed and transmitting them to a master device, the method comprising:
measuring energy consumption in each of a series of time intervals, and maintaining a first cumulative sum of the resulting energy measurements; periodically transmitting, to the master device, a first quantised value representing the cumulative sum; and subtracting the transmitted quantised value from the cumulative sum. | A power-consumption monitoring device, for taking measurements of the power consumed by an appliance. The device is connectable to a mains electrical circuit and operable to transmit the measurements to a master device through the circuit. The device is adapted: to measure the energy consumed by the appliance in each of a series of time intervals, and maintain a first cumulative sum of the resulting energy measurements; to periodically transmit, to the master device, a first quantised value representing the cumulative sum; and to subtract the transmitted quantised value from the cumulative sum.1. A power-consumption monitoring device, for taking measurements of the power consumed by an appliance,
the device being connectable to a mains electrical circuit and operable to transmit the measurements to a master device through the circuit, wherein the device is adapted:
to measure the energy consumed by the appliance in each of a series of time intervals, and maintain a first cumulative sum of the resulting energy measurements;
to periodically transmit, to the master device, a first quantised value representing the cumulative sum; and
to subtract the transmitted quantised value from the cumulative sum. 2. The power-consumption monitoring device of claim 1, wherein the quantisation used to generate the first quantised value is non-uniform. 3. The power-consumption monitoring device of claim 2, wherein the quantisation comprises floating point quantisation. 4. The power-consumption monitoring device of claim 1, wherein the device is further adapted:
to maintain a second cumulative sum of the energy measurements; and to intermittently transmit the value of the second cumulative sum to the master device. 5. The power-consumption monitoring device of claim 4, wherein the value of the second cumulative sum is transmitted in place of one of the periodic transmissions of the first cumulative sum. 6. The power-consumption monitoring device of claim 1, wherein the device is adapted to:
receive a spread-spectrum timing-reference signal from the master device; detect a code-phase of the received reference signal; and transmit the measurements to the master device with a timing that is defined relative to the detected code-phase. 7. The power-consumption monitoring device according to claim 6, wherein the spread-spectrum reference signal is periodically modulated by a synchronisation symbol,
the monitoring device being adapted to:
determine a timing by detecting the synchronisation symbol. 8. The power-consumption monitoring device according to claim 6, comprising a time-domain correlator for detecting the code-phase. 9. The power-consumption monitoring device according to claim 6, wherein the monitoring device is adapted to transmit to the master device an upstream signal which comprises a spreading code modulated by a data message, the data message including the power measurements,
a transmit time-interval in which the upstream signal is transmitted and/or a transmit code-phase of the spreading code being defined relative to the detected code-phase of the reference signal. 10. The power-consumption monitoring device according to claim 9, wherein the monitoring device has:
a configuration mode, in which it is adapted to:
transmit the upstream signal using a first, predetermined time interval and/or code-phase reserved for negotiation with the master device; and
receive, from the master device, configuration information assigning a second, different time interval and/or code-phase, and
a normal mode in which it is adapted to:
transmit the upstream signal using the assigned, second time interval and/or code-phase. 11. The power consumption monitoring device according to claim 9, wherein the device is adapted to transmit the upstream signal in a frequency band that is different from the frequency band of the spread-spectrum timing-reference signal received from the master device. 12. A method of monitoring power-consumption, for taking measurements of power consumed and transmitting them to a master device, the method comprising:
measuring energy consumption in each of a series of time intervals, and maintaining a first cumulative sum of the resulting energy measurements; periodically transmitting, to the master device, a first quantised value representing the cumulative sum; and subtracting the transmitted quantised value from the cumulative sum. | 2,800 |
11,411 | 11,411 | 14,259,821 | 2,814 | An IGBT device includes an IGBT stack including a first surface and a second surface opposite the first surface, a collector contact over the first surface of the IGBT stack, a gate contact on the second surface of the IGBT stack, and an emitter contact on the second surface of the IGBT stack. The IGBT stack includes an injector region, which provides the first surface of the IGBT stack, a drift region over the injector region opposite the first surface, a pair of junction implants in the IGBT stack along the second surface of the IGBT stack, and a field termination region between the pair of junction implants in the IGBT stack along the second surface of the IGBT stack. | 1. An insulated gate bipolar transistor (IGBT) device comprising:
an IGBT stack comprising:
an injector region, the injector region providing a first surface of the IGBT stack;
a drift region over the injector region opposite the first surface;
a pair of junction implants in the IGBT stack along a second surface of the IGBT stack, which is opposite the first surface;
a junction field effect transistor (JFET) region between the pair of junction implants along the second surface of the IGBT stack, wherein a doping concentration of the JFET region is different from a doping concentration of the drift region; and
a field termination region between the pair of junction implants and in the JFET region;
a collector contact over the first surface; and a gate contact and an emitter contact on the second surface. 2. The IGBT device of claim 1 wherein the pair of junction implants are laterally separated from one another along the second surface by a distance greater than 5 μm. 3. The IGBT device of claim 2 wherein the pair of junction implants are laterally separated from one another along the second surface by a distance less than 20 μm. 4. The IGBT device of claim 1 wherein the pair of junction implants are contained by the drift region. 5. The IGBT device of claim 1 wherein:
the injector region is a heavily doped P region;
the drift region is a lightly doped N region;
the JFET region is a heavily doped N region; and
the field termination region is a heavily doped P region. 6. The IGBT device of claim 5 wherein:
the injector region has a doping concentration in the range of about 5×1017 cm−3 to about 1×1021 cm−3;
the drift region has a doping concentration in the range of about 1×1013 cm−3 to about 1×1015 cm−3;
the JFET region has a doping concentration in the range of about 1×1016 cm−3 to about 1×1018 cm−3; and
the field termination region has a doping concentration in the range of about 1×1016 cm−3 to about 1×1020 cm−3. 7. The IGBT device of claim 1 wherein each one of the pair of junction implants comprises:
a base well; and
a source well within the base well. 8. The IGBT device of claim 7 wherein:
the base well is a heavily doped P region; and
the source well is an N region. 9. The IGBT device of claim 7 wherein:
the gate contact runs between each source well in the pair of junction implants on the second surface; and
the emitter contact partially overlaps the source well and the base well in each one of the pair of junction implants, respectively, without contacting the gate contact. 10. The IGBT device of claim 9 further comprising a gate oxide layer between the gate contact and the second surface. 11. The IGBT device of claim 1 wherein the IGBT stack further comprises a buffer region between the injector region and the drift region. 12. The IGBT device of claim 1 further comprising a junction field-effect transistor (JFET) region between each one of the junction implants in the IGBT stack along the second surface, such that the field termination region is contained within the JFET region. 13. The IGBT device of claim 1 wherein the IGBT stack is a wide band-gap semiconductor material. 14. The IGBT device of claim 13 wherein the IGBT stack is Silicon Carbide (SiC). 15. The IGBT device of claim 1 wherein the IGBT stack further comprises a spreading region over the drift region opposite the injector region. 16. The IGBT device of claim 15 wherein the pair of junction implants are laterally separated from one another along the second surface by a distance greater than 5 μm. 17. The IGBT device of claim 16 wherein the pair of junction implants are laterally separated from one another along the second surface by a distance less than 20 μm. 18. The IGBT device of claim 15 wherein the pair of junction implants are contained by the spreading region. 19. The IGBT device of claim 15 wherein:
the injector region is a heavily doped P region;
the drift region is a lightly doped N region;
the spreading region is a heavily doped N region; and
the field termination region is a heavily doped P region. 20. The IGBT device of claim 19 wherein:
the injector region has a doping concentration in the range of about 5×1017 cm−3 to about 1×1021 cm−3;
the drift region has a doping concentration in the range of about 1×10−3 cm to about 1×1015 cm−3;
the spreading region has a doping concentration in the range of about 1×1016 cm−3 to about 5×1016 cm−3; and
the field termination region has a doping concentration in the range of about 1×1016 cm−3 to about 1×1020 cm−3. 21. The IGBT device of claim 15 wherein each one of the pair of junction implants comprises:
a base well; and
a source well within the base well. 22. The IGBT device of claim 15 wherein the IGBT stack further comprises a buffer region between the injector region and the drift region. 23. The IGBT device of claim 15 wherein the IGBT stack is a wide band-gap semiconductor material. 24. The IGBT device of claim 23 wherein the IGBT stack is Silicon Carbide (SiC). 25. A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising:
providing an IGBT stack including an injector region and a drift region over the injector region, the injector region providing a first surface of the IGBT stack opposite the drift region; providing a pair of junction implants in the IGBT stack along a second surface of the IGBT stack, which is opposite the first surface; providing a junction field effect transistor (JFET) region in the IGBT stack between the pair of junction implants along the second surface of the IGBT stack; providing a field termination region between the pair of junction implants in the JFET region; providing a collector contact over the first surface; and providing a gate contact and an emitter contact on the second surface. 26. The method of claim 25 wherein the pair of junction implants are laterally separated from one another along the second surface by a distance greater than 5 μm. 27. The method of claim 26 wherein the pair of junction implants are laterally separated from one another along the second surface by a distance less than 20 μm. 28. The method of claim 25 wherein the pair of junction implants are contained by the drift region. 29. The method of claim 25 wherein:
the injector region is a heavily doped P region;
the drift region is a lightly doped N region;
the JFET region is a heavily doped N region; and
the field termination region is a heavily doped P region. 30. The method of claim 29 wherein:
the injector region has a doping concentration in the range of about 1×1017 cm−3 to about 1×1021 cm−3;
the drift region has a doping concentration in the range of about 1×1013 cm−3 to about 1×1015 cm−3;
the JFET region has a doping concentration in the range of about 1×1016 cm−3 to about 1×1018 cm−3; and
the field termination region has a doping concentration in the range of about 1×1016 cm−3 to about 1×1020 cm−3. | An IGBT device includes an IGBT stack including a first surface and a second surface opposite the first surface, a collector contact over the first surface of the IGBT stack, a gate contact on the second surface of the IGBT stack, and an emitter contact on the second surface of the IGBT stack. The IGBT stack includes an injector region, which provides the first surface of the IGBT stack, a drift region over the injector region opposite the first surface, a pair of junction implants in the IGBT stack along the second surface of the IGBT stack, and a field termination region between the pair of junction implants in the IGBT stack along the second surface of the IGBT stack.1. An insulated gate bipolar transistor (IGBT) device comprising:
an IGBT stack comprising:
an injector region, the injector region providing a first surface of the IGBT stack;
a drift region over the injector region opposite the first surface;
a pair of junction implants in the IGBT stack along a second surface of the IGBT stack, which is opposite the first surface;
a junction field effect transistor (JFET) region between the pair of junction implants along the second surface of the IGBT stack, wherein a doping concentration of the JFET region is different from a doping concentration of the drift region; and
a field termination region between the pair of junction implants and in the JFET region;
a collector contact over the first surface; and a gate contact and an emitter contact on the second surface. 2. The IGBT device of claim 1 wherein the pair of junction implants are laterally separated from one another along the second surface by a distance greater than 5 μm. 3. The IGBT device of claim 2 wherein the pair of junction implants are laterally separated from one another along the second surface by a distance less than 20 μm. 4. The IGBT device of claim 1 wherein the pair of junction implants are contained by the drift region. 5. The IGBT device of claim 1 wherein:
the injector region is a heavily doped P region;
the drift region is a lightly doped N region;
the JFET region is a heavily doped N region; and
the field termination region is a heavily doped P region. 6. The IGBT device of claim 5 wherein:
the injector region has a doping concentration in the range of about 5×1017 cm−3 to about 1×1021 cm−3;
the drift region has a doping concentration in the range of about 1×1013 cm−3 to about 1×1015 cm−3;
the JFET region has a doping concentration in the range of about 1×1016 cm−3 to about 1×1018 cm−3; and
the field termination region has a doping concentration in the range of about 1×1016 cm−3 to about 1×1020 cm−3. 7. The IGBT device of claim 1 wherein each one of the pair of junction implants comprises:
a base well; and
a source well within the base well. 8. The IGBT device of claim 7 wherein:
the base well is a heavily doped P region; and
the source well is an N region. 9. The IGBT device of claim 7 wherein:
the gate contact runs between each source well in the pair of junction implants on the second surface; and
the emitter contact partially overlaps the source well and the base well in each one of the pair of junction implants, respectively, without contacting the gate contact. 10. The IGBT device of claim 9 further comprising a gate oxide layer between the gate contact and the second surface. 11. The IGBT device of claim 1 wherein the IGBT stack further comprises a buffer region between the injector region and the drift region. 12. The IGBT device of claim 1 further comprising a junction field-effect transistor (JFET) region between each one of the junction implants in the IGBT stack along the second surface, such that the field termination region is contained within the JFET region. 13. The IGBT device of claim 1 wherein the IGBT stack is a wide band-gap semiconductor material. 14. The IGBT device of claim 13 wherein the IGBT stack is Silicon Carbide (SiC). 15. The IGBT device of claim 1 wherein the IGBT stack further comprises a spreading region over the drift region opposite the injector region. 16. The IGBT device of claim 15 wherein the pair of junction implants are laterally separated from one another along the second surface by a distance greater than 5 μm. 17. The IGBT device of claim 16 wherein the pair of junction implants are laterally separated from one another along the second surface by a distance less than 20 μm. 18. The IGBT device of claim 15 wherein the pair of junction implants are contained by the spreading region. 19. The IGBT device of claim 15 wherein:
the injector region is a heavily doped P region;
the drift region is a lightly doped N region;
the spreading region is a heavily doped N region; and
the field termination region is a heavily doped P region. 20. The IGBT device of claim 19 wherein:
the injector region has a doping concentration in the range of about 5×1017 cm−3 to about 1×1021 cm−3;
the drift region has a doping concentration in the range of about 1×10−3 cm to about 1×1015 cm−3;
the spreading region has a doping concentration in the range of about 1×1016 cm−3 to about 5×1016 cm−3; and
the field termination region has a doping concentration in the range of about 1×1016 cm−3 to about 1×1020 cm−3. 21. The IGBT device of claim 15 wherein each one of the pair of junction implants comprises:
a base well; and
a source well within the base well. 22. The IGBT device of claim 15 wherein the IGBT stack further comprises a buffer region between the injector region and the drift region. 23. The IGBT device of claim 15 wherein the IGBT stack is a wide band-gap semiconductor material. 24. The IGBT device of claim 23 wherein the IGBT stack is Silicon Carbide (SiC). 25. A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising:
providing an IGBT stack including an injector region and a drift region over the injector region, the injector region providing a first surface of the IGBT stack opposite the drift region; providing a pair of junction implants in the IGBT stack along a second surface of the IGBT stack, which is opposite the first surface; providing a junction field effect transistor (JFET) region in the IGBT stack between the pair of junction implants along the second surface of the IGBT stack; providing a field termination region between the pair of junction implants in the JFET region; providing a collector contact over the first surface; and providing a gate contact and an emitter contact on the second surface. 26. The method of claim 25 wherein the pair of junction implants are laterally separated from one another along the second surface by a distance greater than 5 μm. 27. The method of claim 26 wherein the pair of junction implants are laterally separated from one another along the second surface by a distance less than 20 μm. 28. The method of claim 25 wherein the pair of junction implants are contained by the drift region. 29. The method of claim 25 wherein:
the injector region is a heavily doped P region;
the drift region is a lightly doped N region;
the JFET region is a heavily doped N region; and
the field termination region is a heavily doped P region. 30. The method of claim 29 wherein:
the injector region has a doping concentration in the range of about 1×1017 cm−3 to about 1×1021 cm−3;
the drift region has a doping concentration in the range of about 1×1013 cm−3 to about 1×1015 cm−3;
the JFET region has a doping concentration in the range of about 1×1016 cm−3 to about 1×1018 cm−3; and
the field termination region has a doping concentration in the range of about 1×1016 cm−3 to about 1×1020 cm−3. | 2,800 |
11,412 | 11,412 | 14,668,676 | 2,858 | A method of detecting a cold-boot attack on an integrated circuit, including the steps of: periodically sampling a signal delivered by at least one ring oscillator; and verifying that the proportion of states “1” and of states “0” of the result of the sampling is within a range of values. | 1. A method, comprising:
sampling a series of bits output by a logic circuit of an integrated circuit; generating an indication of a proportion of the series of bits in a first state; and generating an indication of a cold-boot attack based on the generated indication of the proportion of the series of bits in the first state. 2. The method of claim 1 wherein the logic circuit comprises at least one ring oscillator and the sampling includes sampling a series of bits output by the ring oscillator. 3. The method of claim 2 wherein the generating the indication of the proportion comprises counting a number of bits in the first state and the generating the indication of the cold-boot attack comprises determining whether the number of bits in the first state is within a range of values. 4. The method of claim 3 wherein said range of values is determined by statistical analysis in a training phase during which the integrated circuit is operated in a normal temperature range. 5. The method of claim 2 wherein the generating the indication of the proportion comprises counting a number of bits in the first state and the generating the indication of the cold-boot attack comprises comparing the number of bits in the first state to one or more threshold values. 6. The method of claim 5 wherein the first state is a one state. 7. The method of claim 2, comprising periodically repeating the sampling, the generating of the indication of the proportion and the generating of the indication of a cold-boot attack. 8. A device, comprising:
a logic circuit; and sampling circuitry configured to:
sample an output generated by the logic circuit;
generate an indication of a proportion of bits in the sampled output in a first state; and
generate an indication of a cold-boot attack based on the generated indication of the proportion of the bits in the first state. 9. The device of claim 8 wherein the device is an integrated circuit and the logic circuit comprises at least one ring oscillator. 10. The device of claim 9 wherein the sampling circuitry is configured to count a number of bits in the sampled output in the first state and to generate the indication of the cold-boot attack based on whether the counted number of bits is within a range of values. 11. The device of claim 10 wherein said range of values is determined by statistical analysis in a training phase during which the integrated circuit is operated in a normal temperature range. 12. The device of claim 9 wherein the sampling circuitry is configured to count a number of bits in the sampled output in the first state and to compare the counted number of bits in the first state to one or more threshold values. 13. The device of claim 8 wherein the sampling circuitry is configured to periodically repeat the sampling, the generating of the indication of the proportion and the generating of the indication of a cold-boot attack. 14. The device of claim 9, comprising a flip-flop configured to sample the output of the ring oscillator. 15. The device of claim 11, comprising a non-volatile memory having said range of values stored therein. 16. The device of claim 9, comprising a volatile memory configured to store information. 17. A system, comprising:
a processing unit; a random access memory; and cold-boot attack detection circuitry, including:
a logic circuit; and
sampling circuitry configured to:
sample an output generated by the logic circuit;
generate an indication of a proportion of bits in the sampled output in a first state; and
generate an indication of a cold-boot attack based on the generated indication of the proportion of the bits in the first state. 18. The system of claim 17 comprising an integrated circuit including the cold-boot attack detection circuitry. 19. The system of claim 18 wherein the logic circuit includes at least one ring oscillator. 20. The system of claim 17 wherein the sampling circuitry is configured to periodically repeat the sampling, the generating of the indication of the proportion and the generating of the indication of a cold-boot attack. | A method of detecting a cold-boot attack on an integrated circuit, including the steps of: periodically sampling a signal delivered by at least one ring oscillator; and verifying that the proportion of states “1” and of states “0” of the result of the sampling is within a range of values.1. A method, comprising:
sampling a series of bits output by a logic circuit of an integrated circuit; generating an indication of a proportion of the series of bits in a first state; and generating an indication of a cold-boot attack based on the generated indication of the proportion of the series of bits in the first state. 2. The method of claim 1 wherein the logic circuit comprises at least one ring oscillator and the sampling includes sampling a series of bits output by the ring oscillator. 3. The method of claim 2 wherein the generating the indication of the proportion comprises counting a number of bits in the first state and the generating the indication of the cold-boot attack comprises determining whether the number of bits in the first state is within a range of values. 4. The method of claim 3 wherein said range of values is determined by statistical analysis in a training phase during which the integrated circuit is operated in a normal temperature range. 5. The method of claim 2 wherein the generating the indication of the proportion comprises counting a number of bits in the first state and the generating the indication of the cold-boot attack comprises comparing the number of bits in the first state to one or more threshold values. 6. The method of claim 5 wherein the first state is a one state. 7. The method of claim 2, comprising periodically repeating the sampling, the generating of the indication of the proportion and the generating of the indication of a cold-boot attack. 8. A device, comprising:
a logic circuit; and sampling circuitry configured to:
sample an output generated by the logic circuit;
generate an indication of a proportion of bits in the sampled output in a first state; and
generate an indication of a cold-boot attack based on the generated indication of the proportion of the bits in the first state. 9. The device of claim 8 wherein the device is an integrated circuit and the logic circuit comprises at least one ring oscillator. 10. The device of claim 9 wherein the sampling circuitry is configured to count a number of bits in the sampled output in the first state and to generate the indication of the cold-boot attack based on whether the counted number of bits is within a range of values. 11. The device of claim 10 wherein said range of values is determined by statistical analysis in a training phase during which the integrated circuit is operated in a normal temperature range. 12. The device of claim 9 wherein the sampling circuitry is configured to count a number of bits in the sampled output in the first state and to compare the counted number of bits in the first state to one or more threshold values. 13. The device of claim 8 wherein the sampling circuitry is configured to periodically repeat the sampling, the generating of the indication of the proportion and the generating of the indication of a cold-boot attack. 14. The device of claim 9, comprising a flip-flop configured to sample the output of the ring oscillator. 15. The device of claim 11, comprising a non-volatile memory having said range of values stored therein. 16. The device of claim 9, comprising a volatile memory configured to store information. 17. A system, comprising:
a processing unit; a random access memory; and cold-boot attack detection circuitry, including:
a logic circuit; and
sampling circuitry configured to:
sample an output generated by the logic circuit;
generate an indication of a proportion of bits in the sampled output in a first state; and
generate an indication of a cold-boot attack based on the generated indication of the proportion of the bits in the first state. 18. The system of claim 17 comprising an integrated circuit including the cold-boot attack detection circuitry. 19. The system of claim 18 wherein the logic circuit includes at least one ring oscillator. 20. The system of claim 17 wherein the sampling circuitry is configured to periodically repeat the sampling, the generating of the indication of the proportion and the generating of the indication of a cold-boot attack. | 2,800 |
11,413 | 11,413 | 14,552,584 | 2,872 | The present disclosure is directed to a novel way to attach various accessories to the temple vents of protective eyewear. In one aspect of the disclosure; a clip with a male key portion is configured to attach accessories by rotationally locking the clip into a vent of a temple of a pair of protective eyewear, with the accessories attached to the clip. | 1. Protective eyewear comprising:
a pair of temples connected to a frame; each temple defining at least two vent openings; a clip having a protruding key portion; at least one vent opening on each temple configured to receive the clip key portion; and wherein the clip key portion is configured to rotationally secure the clip into the at least one vent opening. 2. The protective eyewear of claim 1; further comprising a portion of the clip configured to accept an accessory. 3. The protective eyewear of claim 2 wherein the accessory is a strap. 4. The protective eyewear of claim 2 wherein the accessory is an ear bud. 5. The protective eyewear of claim 2 wherein the accessory is an ear plug. 6. The protective eyewear of claim 2 wherein the accessory is a clip. 7. An eyewear temple comprising:
a temple defining at least two vent openings; a clip having a key portion and an accessory receiving portion; at least one vent opening configure to receive the clip key portion; the clip key portion configured to rotate within the at least one vent opening; and wherein the clip is secure into position on the eyewear temple after rotation of the clip. 8. The eyewear temple of claim 8 wherein the rotation is about 90 degrees. 9. The eyewear temple of claim 7 wherein the clip is generally triangular in shape. 10. The eyewear temple of claim 7 where each vent opening is generally rectangular in shape. 11. The eyewear temple of claim 7 wherein a strap is connected to the accessory receiving portion of the clip. 12. A method for connecting an accessory to the temples of protective eyewear comprising:
Attaching an accessory to one end of a clip; Inserting a key portion; located at the other end of the clip into one of two vents located in a temple of protective eyewear; and rotating the clip about 90 degrees to secure the key portion into one of the two vents. | The present disclosure is directed to a novel way to attach various accessories to the temple vents of protective eyewear. In one aspect of the disclosure; a clip with a male key portion is configured to attach accessories by rotationally locking the clip into a vent of a temple of a pair of protective eyewear, with the accessories attached to the clip.1. Protective eyewear comprising:
a pair of temples connected to a frame; each temple defining at least two vent openings; a clip having a protruding key portion; at least one vent opening on each temple configured to receive the clip key portion; and wherein the clip key portion is configured to rotationally secure the clip into the at least one vent opening. 2. The protective eyewear of claim 1; further comprising a portion of the clip configured to accept an accessory. 3. The protective eyewear of claim 2 wherein the accessory is a strap. 4. The protective eyewear of claim 2 wherein the accessory is an ear bud. 5. The protective eyewear of claim 2 wherein the accessory is an ear plug. 6. The protective eyewear of claim 2 wherein the accessory is a clip. 7. An eyewear temple comprising:
a temple defining at least two vent openings; a clip having a key portion and an accessory receiving portion; at least one vent opening configure to receive the clip key portion; the clip key portion configured to rotate within the at least one vent opening; and wherein the clip is secure into position on the eyewear temple after rotation of the clip. 8. The eyewear temple of claim 8 wherein the rotation is about 90 degrees. 9. The eyewear temple of claim 7 wherein the clip is generally triangular in shape. 10. The eyewear temple of claim 7 where each vent opening is generally rectangular in shape. 11. The eyewear temple of claim 7 wherein a strap is connected to the accessory receiving portion of the clip. 12. A method for connecting an accessory to the temples of protective eyewear comprising:
Attaching an accessory to one end of a clip; Inserting a key portion; located at the other end of the clip into one of two vents located in a temple of protective eyewear; and rotating the clip about 90 degrees to secure the key portion into one of the two vents. | 2,800 |
11,414 | 11,414 | 14,629,538 | 2,829 | Provided are a thin film transistor substrate and a display using the same. A display includes: a first area, a second area, a first thin film transistor disposed at the first area, the first thin film transistor including: a polycrystalline semiconductor layer, a first gate electrode on the polycrystalline semiconductor layer, a first source electrode, and a first drain electrode, a second thin film transistor disposed at the second area, the second thin film transistor including: a second gate electrode, an oxide semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode, a nitride layer on an area of the display device, other than the second area, the nitride layer covering the first gate electrode, and an oxide layer disposed over the first gate electrode and the second gate electrode. | 1. A display, comprising:
a first area; a second area; a first thin film transistor disposed at the first area, the first thin film transistor comprising:
a polycrystalline semiconductor layer;
a first gate electrode on the polycrystalline semiconductor layer;
a first source electrode; and
a first drain electrode;
a second thin film transistor disposed at the second area, the second thin film transistor comprising:
a second gate electrode;
an oxide semiconductor layer on the second gate electrode;
a second source electrode; and
a second drain electrode;
a nitride layer on an area of the display device, other than the second area, the nitride layer covering the first gate electrode; and an oxide layer disposed over the first gate electrode and the second gate electrode. 2. The display of claim 1, further comprising:
a driver, wherein at least one of the first thin film transistor and the second thin film transistor is disposed in a pixel, and wherein at least one of the first thin film transistor and the second thin film transistor is disposed at the driver. 3. The display of claim 1, further comprising a gate insulating layer covering the polycrystalline semiconductor layer. 4. The display of claim 3, wherein the first gate electrode and the second gate electrode are formed on a same layer on the gate insulating layer. 5. The display of claim 1, wherein:
the second thin film transistor is a switching element for selecting a pixel; and the first thin film transistor is a driving element for driving an organic light emitting diode of the pixel selected by the second thin film transistor. 6. The display of claim 3, wherein the driver comprises:
a data driver outputting a data voltage; a multiplexer distributing the data voltage from the data driver to a data line; and a gate driver outputting a scan pulse to a gate line, wherein at least one of the first thin film transistor and the second thin film transistor is disposed at any one of the multiplexer and the gate driver. 7. The display of claim 3, wherein:
the first source electrode is disposed on the oxide layer, the first source electrode being connected to one portion of the polycrystalline semiconductor layer through a source contact hole penetrating the oxide layer, the nitride layer, and the gate insulating layer; the first drain electrode is disposed on the oxide layer, the first drain electrode being connected to another portion of the polycrystalline semiconductor layer through a drain contact hole penetrating the oxide layer, the nitride layer, and the gate insulating layer; the second source electrode contacts one portion of the oxide semiconductor layer on the oxide layer; and the second drain electrode contacts another portion of the oxide semiconductor layer on the oxide layer. 8. The display of claim 1, wherein each of the nitride layer and the oxide layer has a thickness of 1,000 Ř3,000 Å. 9. The display of claim 1, wherein the nitride layer is disposed under the oxide layer. 10. The display of claim 9, further comprising, at the first area, a lower oxide layer disposed between the nitride layer and the first gate electrode. 11. The display of claim 1, wherein the nitride layer is disposed on the oxide layer. 12. A display, comprising:
a first area; a second area; a first semiconductor layer disposed at the first area, the first semiconductor layer comprising a polycrystalline semiconductor material; a gate insulating layer covering the first semiconductor layer; a first gate electrode disposed on the gate insulating layer and overlapping with the first semiconductor layer; a second gate electrode disposed at the second area on the gate insulating layer; a nitride layer disposed on an area of the display, other than the second area, the nitride layer covering the first gate electrode; an oxide layer covering the first gate electrode and the second gate electrode; a second semiconductor layer disposed at the second area on the oxide layer, the second semiconductor layer comprising an oxide semiconductor material, the second semiconductor layer overlapping the second gate electrode; a first source electrode and a first drain electrode disposed on the oxide layer; and a second source electrode and a second drain electrode disposed on the second semiconductor layer. 13. The display of claim 12, wherein:
a first thin film transistor comprises:
the first semiconductor layer;
the first gate electrode;
the first source electrode; and
the first drain electrode; and
a second thin film transistor comprises:
the second semiconductor layer;
the second gate electrode;
the second source electrode; and
the second drain electrode. 14. The display of claim 13, further comprising:
a driver, wherein at least one of the first thin film transistor and the second thin film transistor is disposed in a pixel, and wherein at least one of the first thin film transistor and the second thin film transistor is disposed at the driver. 15. The display of claim 13, wherein:
the second thin film transistor is a switching element for selecting a pixel; and the first thin film transistor is a driving element for driving an organic light emitting diode of the pixel selected by the second thin film transistor. 16. The display of claim 14, wherein the driver includes:
a data driver outputting a data voltage; a multiplexer distributing the data voltage from the data driver to a data line; and a gate driver outputting a scan pulse to a gate line, wherein at least one of the first thin film transistor and the second thin film transistor is disposed at any one of the multiplexer and the gate driver. 17. The display of claim 12, wherein:
the first source electrode is connected to one portion of the first semiconductor layer through a source contact hole penetrating the oxide layer, the nitride layer, and the gate insulating layer; the first drain electrode is connected to another portion of the first semiconductor layer through a drain contact hole penetrating the oxide layer, the nitride layer, and the gate insulating layer; the second source electrode contacts one portion of the second semiconductor layer; and the second drain electrode contacts another portion of the second semiconductor layer. 18. The display of claim 12, wherein each of the nitride layer and the oxide layer has a thickness of 1,000 Ř3,000 Å. 19. The display of claim 12, wherein the nitride layer is disposed under the oxide layer. 20. The display of claim 19, further comprising, at the first area, a lower oxide layer disposed between the nitride layer and the first gate electrode. 21. The display of claim 12, wherein the nitride layer is disposed on the oxide layer. | Provided are a thin film transistor substrate and a display using the same. A display includes: a first area, a second area, a first thin film transistor disposed at the first area, the first thin film transistor including: a polycrystalline semiconductor layer, a first gate electrode on the polycrystalline semiconductor layer, a first source electrode, and a first drain electrode, a second thin film transistor disposed at the second area, the second thin film transistor including: a second gate electrode, an oxide semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode, a nitride layer on an area of the display device, other than the second area, the nitride layer covering the first gate electrode, and an oxide layer disposed over the first gate electrode and the second gate electrode.1. A display, comprising:
a first area; a second area; a first thin film transistor disposed at the first area, the first thin film transistor comprising:
a polycrystalline semiconductor layer;
a first gate electrode on the polycrystalline semiconductor layer;
a first source electrode; and
a first drain electrode;
a second thin film transistor disposed at the second area, the second thin film transistor comprising:
a second gate electrode;
an oxide semiconductor layer on the second gate electrode;
a second source electrode; and
a second drain electrode;
a nitride layer on an area of the display device, other than the second area, the nitride layer covering the first gate electrode; and an oxide layer disposed over the first gate electrode and the second gate electrode. 2. The display of claim 1, further comprising:
a driver, wherein at least one of the first thin film transistor and the second thin film transistor is disposed in a pixel, and wherein at least one of the first thin film transistor and the second thin film transistor is disposed at the driver. 3. The display of claim 1, further comprising a gate insulating layer covering the polycrystalline semiconductor layer. 4. The display of claim 3, wherein the first gate electrode and the second gate electrode are formed on a same layer on the gate insulating layer. 5. The display of claim 1, wherein:
the second thin film transistor is a switching element for selecting a pixel; and the first thin film transistor is a driving element for driving an organic light emitting diode of the pixel selected by the second thin film transistor. 6. The display of claim 3, wherein the driver comprises:
a data driver outputting a data voltage; a multiplexer distributing the data voltage from the data driver to a data line; and a gate driver outputting a scan pulse to a gate line, wherein at least one of the first thin film transistor and the second thin film transistor is disposed at any one of the multiplexer and the gate driver. 7. The display of claim 3, wherein:
the first source electrode is disposed on the oxide layer, the first source electrode being connected to one portion of the polycrystalline semiconductor layer through a source contact hole penetrating the oxide layer, the nitride layer, and the gate insulating layer; the first drain electrode is disposed on the oxide layer, the first drain electrode being connected to another portion of the polycrystalline semiconductor layer through a drain contact hole penetrating the oxide layer, the nitride layer, and the gate insulating layer; the second source electrode contacts one portion of the oxide semiconductor layer on the oxide layer; and the second drain electrode contacts another portion of the oxide semiconductor layer on the oxide layer. 8. The display of claim 1, wherein each of the nitride layer and the oxide layer has a thickness of 1,000 Ř3,000 Å. 9. The display of claim 1, wherein the nitride layer is disposed under the oxide layer. 10. The display of claim 9, further comprising, at the first area, a lower oxide layer disposed between the nitride layer and the first gate electrode. 11. The display of claim 1, wherein the nitride layer is disposed on the oxide layer. 12. A display, comprising:
a first area; a second area; a first semiconductor layer disposed at the first area, the first semiconductor layer comprising a polycrystalline semiconductor material; a gate insulating layer covering the first semiconductor layer; a first gate electrode disposed on the gate insulating layer and overlapping with the first semiconductor layer; a second gate electrode disposed at the second area on the gate insulating layer; a nitride layer disposed on an area of the display, other than the second area, the nitride layer covering the first gate electrode; an oxide layer covering the first gate electrode and the second gate electrode; a second semiconductor layer disposed at the second area on the oxide layer, the second semiconductor layer comprising an oxide semiconductor material, the second semiconductor layer overlapping the second gate electrode; a first source electrode and a first drain electrode disposed on the oxide layer; and a second source electrode and a second drain electrode disposed on the second semiconductor layer. 13. The display of claim 12, wherein:
a first thin film transistor comprises:
the first semiconductor layer;
the first gate electrode;
the first source electrode; and
the first drain electrode; and
a second thin film transistor comprises:
the second semiconductor layer;
the second gate electrode;
the second source electrode; and
the second drain electrode. 14. The display of claim 13, further comprising:
a driver, wherein at least one of the first thin film transistor and the second thin film transistor is disposed in a pixel, and wherein at least one of the first thin film transistor and the second thin film transistor is disposed at the driver. 15. The display of claim 13, wherein:
the second thin film transistor is a switching element for selecting a pixel; and the first thin film transistor is a driving element for driving an organic light emitting diode of the pixel selected by the second thin film transistor. 16. The display of claim 14, wherein the driver includes:
a data driver outputting a data voltage; a multiplexer distributing the data voltage from the data driver to a data line; and a gate driver outputting a scan pulse to a gate line, wherein at least one of the first thin film transistor and the second thin film transistor is disposed at any one of the multiplexer and the gate driver. 17. The display of claim 12, wherein:
the first source electrode is connected to one portion of the first semiconductor layer through a source contact hole penetrating the oxide layer, the nitride layer, and the gate insulating layer; the first drain electrode is connected to another portion of the first semiconductor layer through a drain contact hole penetrating the oxide layer, the nitride layer, and the gate insulating layer; the second source electrode contacts one portion of the second semiconductor layer; and the second drain electrode contacts another portion of the second semiconductor layer. 18. The display of claim 12, wherein each of the nitride layer and the oxide layer has a thickness of 1,000 Ř3,000 Å. 19. The display of claim 12, wherein the nitride layer is disposed under the oxide layer. 20. The display of claim 19, further comprising, at the first area, a lower oxide layer disposed between the nitride layer and the first gate electrode. 21. The display of claim 12, wherein the nitride layer is disposed on the oxide layer. | 2,800 |
11,415 | 11,415 | 14,905,074 | 2,861 | A method to determine a quantity of a liquid in a container. In the method, a actuator is controlled to rotate a member in the container at a first speed. A measurement of electrical current drawn by the actuator at the first speed is received. A quantity of liquid in the container is determined through a look-up table and the measured electrical current. | 1. A method to determine a quantity of a liquid in a chamber, the method comprising:
controlling a motor to rotate a mixer in the chamber at a first speed; receiving a measurement of electrical current drawn by the motor at the first speed; and determining, through a look-up table and the measured electrical current, a quantity of liquid in the chamber. 2. A method as claimed in claim 1, further comprising determining, through the look-up table and the measured electrical current, that the mixer is not coupled to the motor. 3. A method as claimed in claim 2, further comprising preventing supply of a liquid and/or a solid where it is determined that the mixer is not coupled to the motor. 4. A method as claimed in claim 3, further comprising controlling an alarm to alert a user where it is determined that the mixer is not coupled to the motor. 5. A method as claimed in claim 1, further comprising controlling supply of a liquid to the chamber when it is determined that the chamber is not full. 6. A method as claimed in claim 1, further comprising controlling the motor to rotate the mixer in the chamber at a second speed;
receiving a measurement of electrical current drawn by the motor at the second speed; and determining, through a look-up table and the measured electrical current, a quantity of liquid and the viscosity of the liquid in the chamber. 7. A method as claimed in claim 1, further comprising controlling provision of mixed liquid to a container to empty the chamber. 8. A method as claimed in claim 1, wherein the liquid in the chamber comprises: a first liquid only; or a first liquid and a second liquid, the first liquid having a different viscosity to the second liquid; or a liquid and a solid. 9. A non-transitory computer-readable storage medium encoded with instructions that, when performed by a processor, cause performance of:
controlling a motor to rotate a mixer in a chamber at a first speed; receiving a measurement of electrical current drawn by the motor at the first speed; and determining, through a look-up table and the measured electrical current, a quantity of liquid in the chamber. 10. Apparatus to determine a quantity of a liquid in a container, the apparatus comprising a controller to:
control an actuator to move a member in the container at a first speed; receive a measurement of electrical current drawn by the actuator at the first speed; and determine, through a look-up table and the measured electrical current, a quantity of liquid in the container. 11. Apparatus as claimed in claim 10, wherein the controller is arranged to determine, through the look-up table and the measured electrical current, that the member is not coupled to the actuator. 12. Apparatus as claimed in claim 10, wherein the controller is arranged to:
control the actuator to move the member in the container at a second speed; receive a measurement of electrical current drawn by the actuator at the second speed; and determine, through a look-up table and the measured electrical current, a quantity of liquid and the viscosity of the liquid in the container. 13. Apparatus as claimed in claim 10, wherein the apparatus does not comprise a load cell to weigh the container. 14. Apparatus as claimed in claim 10, wherein the apparatus does not comprise sensors within the container to determine the quantity and/or the viscosity of liquid in the container. 15. Apparatus as claimed in claim 10, further comprising an ammeter to measure the electrical current drawn by the actuator and to provide the measured electrical current to the controller. | A method to determine a quantity of a liquid in a container. In the method, a actuator is controlled to rotate a member in the container at a first speed. A measurement of electrical current drawn by the actuator at the first speed is received. A quantity of liquid in the container is determined through a look-up table and the measured electrical current.1. A method to determine a quantity of a liquid in a chamber, the method comprising:
controlling a motor to rotate a mixer in the chamber at a first speed; receiving a measurement of electrical current drawn by the motor at the first speed; and determining, through a look-up table and the measured electrical current, a quantity of liquid in the chamber. 2. A method as claimed in claim 1, further comprising determining, through the look-up table and the measured electrical current, that the mixer is not coupled to the motor. 3. A method as claimed in claim 2, further comprising preventing supply of a liquid and/or a solid where it is determined that the mixer is not coupled to the motor. 4. A method as claimed in claim 3, further comprising controlling an alarm to alert a user where it is determined that the mixer is not coupled to the motor. 5. A method as claimed in claim 1, further comprising controlling supply of a liquid to the chamber when it is determined that the chamber is not full. 6. A method as claimed in claim 1, further comprising controlling the motor to rotate the mixer in the chamber at a second speed;
receiving a measurement of electrical current drawn by the motor at the second speed; and determining, through a look-up table and the measured electrical current, a quantity of liquid and the viscosity of the liquid in the chamber. 7. A method as claimed in claim 1, further comprising controlling provision of mixed liquid to a container to empty the chamber. 8. A method as claimed in claim 1, wherein the liquid in the chamber comprises: a first liquid only; or a first liquid and a second liquid, the first liquid having a different viscosity to the second liquid; or a liquid and a solid. 9. A non-transitory computer-readable storage medium encoded with instructions that, when performed by a processor, cause performance of:
controlling a motor to rotate a mixer in a chamber at a first speed; receiving a measurement of electrical current drawn by the motor at the first speed; and determining, through a look-up table and the measured electrical current, a quantity of liquid in the chamber. 10. Apparatus to determine a quantity of a liquid in a container, the apparatus comprising a controller to:
control an actuator to move a member in the container at a first speed; receive a measurement of electrical current drawn by the actuator at the first speed; and determine, through a look-up table and the measured electrical current, a quantity of liquid in the container. 11. Apparatus as claimed in claim 10, wherein the controller is arranged to determine, through the look-up table and the measured electrical current, that the member is not coupled to the actuator. 12. Apparatus as claimed in claim 10, wherein the controller is arranged to:
control the actuator to move the member in the container at a second speed; receive a measurement of electrical current drawn by the actuator at the second speed; and determine, through a look-up table and the measured electrical current, a quantity of liquid and the viscosity of the liquid in the container. 13. Apparatus as claimed in claim 10, wherein the apparatus does not comprise a load cell to weigh the container. 14. Apparatus as claimed in claim 10, wherein the apparatus does not comprise sensors within the container to determine the quantity and/or the viscosity of liquid in the container. 15. Apparatus as claimed in claim 10, further comprising an ammeter to measure the electrical current drawn by the actuator and to provide the measured electrical current to the controller. | 2,800 |
11,416 | 11,416 | 15,343,492 | 2,832 | An active damper system is provided for a vehicle, in particular a motor vehicle. It includes a damper unit with a cylinder, a piston which is guided in the cylinder, and a piston rod which is connected to the piston. The piston divides the cylinder into a first chamber and a second chamber, and the damper unit is designed to be arranged between a body and a wheel of the vehicle. The damper system also has a pump for changing the pressure in the two chambers and for moving the piston, a first valve, a second valve, which is connected to the first valve in series, a third valve, and a fourth valve, which is connected to the third valve in series. The first and second valve are connected in parallel to the third and fourth valve. A fluid-conductive first line leads to the first chamber between the first valve and the second valve, and a fluid-conductive second line leads to the second chamber between the third valve and the fourth valve. A low-pressure side of the pump is connected between the first valve and the fourth valve, and a pressure side of the pump is connected between the second valve and the third valve. The first valve, the second valve, the third valve, and the fourth valve can be switched in order to selectively block and release the flow of fluid. A control unit is provided for switching the four valves such that the pump rotates in the same direction when compressing and rebounding during an electromotor operation and a generator operation. | 1. An active damper system for a vehicle, comprising:
a damper unit having a cylinder, a piston which is guided in the cylinder, and a piston rod which is connected to the piston, the piston dividing the cylinder into a first chamber and a second chamber, and the damper unit being configured for arranging between a vehicle body and a wheel of the vehicle; a pump for changing pressures in the first and second chambers and for moving the piston; a first valve and a second valve which is connected in series with the first valve; a third valve and a fourth valve which is connected in series with the third valve, wherein the first and second valves are connected in parallel with the third and fourth valves; a fluid-conducting first line leading between the first valve and the second valve to the first chamber; a fluid-conducting second line leading between the third valve and the fourth valve to the second chamber, wherein a low pressure side of the pump is connected between the first valve and the fourth valve, a pressure side of the pump is connected between the second valve and the third valve, the first valve, the second valve, the third valve and the fourth valve are switchable for selectively closing and opening the fluid flow; and a control unit for switching the first, second, third, and fourth valves, with the result that, in electric motor operation and in generator operation, the pump rotates in the same direction, both during compression and during rebound. 2. The active damper system according to claim 1, wherein the first valve, the second valve, the third valve and/or the fourth valve are check valves which can selectively be closed and opened. 3. The active damper system according to claim 1, further comprising:
an electric machine which is operable as an electric motor in order to drive the pump, and which is operable as a generator in order to generate electrical energy by way of the pump. 4. The active damper system according to claim 1, wherein
in each case, two valves are actuatable in pairs by the control unit, with the result that the first valve and the third valve always have the same switching position, and with the result that the second valve and the fourth valve always have the same switching position. 5. The active damper system according to claim 1, wherein the control unit for switching the four valves comprises a directional valve which is connected via control lines to the four valves and is connected via a pressure line to the pressure side of the pump. 6. The active damper system according to claim 5, further comprising:
a fluid-conducting direct connection, which is switchable by the control unit, between the pressure side and the low pressure side of the pump, thus bypassing the four valves. 7. The active damper system according to claim 6, wherein the switchability of the fluid-conducting direct connection is integrated into the directional valve, or wherein a first additional valve is arranged for the switchability of the fluid-conducting direct connection. 8. The active damper system according to claim 1, further comprising:
a first pressure accumulator which is connected between the first valve and the fourth valve; and a second pressure accumulator which is connected between the second valve and the third valve. 9. The active damper system according to claim 8, further comprising:
a second additional valve for controlling inflow and outflow at the second pressure accumulator; and/or a third additional valve for closing the pressure side of the pump. 10. The active damper system according to claim 1, wherein the pump is a hydraulic pump. | An active damper system is provided for a vehicle, in particular a motor vehicle. It includes a damper unit with a cylinder, a piston which is guided in the cylinder, and a piston rod which is connected to the piston. The piston divides the cylinder into a first chamber and a second chamber, and the damper unit is designed to be arranged between a body and a wheel of the vehicle. The damper system also has a pump for changing the pressure in the two chambers and for moving the piston, a first valve, a second valve, which is connected to the first valve in series, a third valve, and a fourth valve, which is connected to the third valve in series. The first and second valve are connected in parallel to the third and fourth valve. A fluid-conductive first line leads to the first chamber between the first valve and the second valve, and a fluid-conductive second line leads to the second chamber between the third valve and the fourth valve. A low-pressure side of the pump is connected between the first valve and the fourth valve, and a pressure side of the pump is connected between the second valve and the third valve. The first valve, the second valve, the third valve, and the fourth valve can be switched in order to selectively block and release the flow of fluid. A control unit is provided for switching the four valves such that the pump rotates in the same direction when compressing and rebounding during an electromotor operation and a generator operation.1. An active damper system for a vehicle, comprising:
a damper unit having a cylinder, a piston which is guided in the cylinder, and a piston rod which is connected to the piston, the piston dividing the cylinder into a first chamber and a second chamber, and the damper unit being configured for arranging between a vehicle body and a wheel of the vehicle; a pump for changing pressures in the first and second chambers and for moving the piston; a first valve and a second valve which is connected in series with the first valve; a third valve and a fourth valve which is connected in series with the third valve, wherein the first and second valves are connected in parallel with the third and fourth valves; a fluid-conducting first line leading between the first valve and the second valve to the first chamber; a fluid-conducting second line leading between the third valve and the fourth valve to the second chamber, wherein a low pressure side of the pump is connected between the first valve and the fourth valve, a pressure side of the pump is connected between the second valve and the third valve, the first valve, the second valve, the third valve and the fourth valve are switchable for selectively closing and opening the fluid flow; and a control unit for switching the first, second, third, and fourth valves, with the result that, in electric motor operation and in generator operation, the pump rotates in the same direction, both during compression and during rebound. 2. The active damper system according to claim 1, wherein the first valve, the second valve, the third valve and/or the fourth valve are check valves which can selectively be closed and opened. 3. The active damper system according to claim 1, further comprising:
an electric machine which is operable as an electric motor in order to drive the pump, and which is operable as a generator in order to generate electrical energy by way of the pump. 4. The active damper system according to claim 1, wherein
in each case, two valves are actuatable in pairs by the control unit, with the result that the first valve and the third valve always have the same switching position, and with the result that the second valve and the fourth valve always have the same switching position. 5. The active damper system according to claim 1, wherein the control unit for switching the four valves comprises a directional valve which is connected via control lines to the four valves and is connected via a pressure line to the pressure side of the pump. 6. The active damper system according to claim 5, further comprising:
a fluid-conducting direct connection, which is switchable by the control unit, between the pressure side and the low pressure side of the pump, thus bypassing the four valves. 7. The active damper system according to claim 6, wherein the switchability of the fluid-conducting direct connection is integrated into the directional valve, or wherein a first additional valve is arranged for the switchability of the fluid-conducting direct connection. 8. The active damper system according to claim 1, further comprising:
a first pressure accumulator which is connected between the first valve and the fourth valve; and a second pressure accumulator which is connected between the second valve and the third valve. 9. The active damper system according to claim 8, further comprising:
a second additional valve for controlling inflow and outflow at the second pressure accumulator; and/or a third additional valve for closing the pressure side of the pump. 10. The active damper system according to claim 1, wherein the pump is a hydraulic pump. | 2,800 |
11,417 | 11,417 | 13,985,964 | 2,861 | A fluid sampling system ( 220 ) includes an inline fluid extraction body ( 210 ). The inline fluid extraction body comprises an inlet ( 202 ), a first outlet ( 206 ) and a second outlet ( 208 ). A pump ( 214 ) directs a portion of a fluid flowing through the inlet into the second outlet. A flow restrictor ( 222 ) is fluidically coupled to the second outlet and regulates pressure of fluid flow through the second outlet. An extraction system ( 230 ) is fluidically coupled to the second outlet and extracts a gas sample from the fluid sample. The gas sample may then be analyzed by an analyzer. | 1. A method of analyzing a fluid comprising:
directing the fluid to an inline fluid extraction body;
wherein the inline fluid extraction body comprises a screen, a first outlet and a second outlet;
directing a first portion of the fluid through a first outlet of the inline fluid extraction body;
wherein the first portion of the fluid is directed to a separator;
directing a second portion of the fluid through a second outlet of the inline fluid extraction body;
wherein the second outlet of the inline fluid extraction body is fluidically coupled to the screen;
wherein a pump directs the second portion of the fluid through the second outlet of the inline fluid extraction body;
directing the second portion of the fluid to an Inline TEE; directing a first portion of the second portion of the fluid to an extraction system. 2. The method of claim 1, further comprising monitoring pressure of the second portion of the fluid through the second outlet of the inline fluid extraction body using a pressure transducer. 3. The method of claim 2, wherein the pressure transducer is communicatively coupled to an information handling system. 4. The method of claim 2, further comprising notifying an operator if the pressure of the second portion of the fluid is one of less than a threshold pressure and greater than a threshold pressure. 5. The method of claim 1, further comprising regulating the pressure of the second portion of the fluid through the second outlet of the suction tube assembly using a flow restrictor. 6. The method of claim 1, further comprising directing a second portion of the second portion of the fluid to a separator. 7. The method of claim 6, wherein the second portion of the second portion of the fluid is directed to a separator through a check valve. 8. A system for continuous analysis of a drilling fluid comprising:
a first inlet; an inline fluid extraction body fluidically coupled to the first inlet;
wherein the inline fluid extraction body comprises a suction tube assembly, a first outlet and a second outlet;
wherein the suction tube assembly comprises a screen and a pipe fluidically coupled to the screen;
wherein the first outlet of the inline fluid extraction body is directed to a separator;
wherein the second outlet of the inline fluid extraction body is directed to an extraction system;
wherein a portion of the drilling fluid that is directed through the second outlet of the inline fluid extraction body flows through the suction tube assembly; and
a pump;
wherein the pump pulls the portion of the drilling fluid that is directed through the second outlet. 9. The system of claim 8, further comprising a pressure transducer, wherein the pressure transducer monitors pressure of the portion of the drilling fluid that is directed through the second outlet of the inline fluid extraction body. 10. The system of claim 8, further comprising a flow restrictor for regulating pressure of the portion of the drilling fluid that is directed through the second outlet of the inline fluid extraction body. 11. The system of claim 8, wherein the pump is selected from a group consisting of a positive displacement pump, a mud pump and a hydraulic pump. 12. The system of claim 8, wherein the screen is self cleaning. 13. The system of claim 8, further comprising a bypass mechanism for bypassing the extraction system. 14. The system of claim 8, wherein the screen is stainless steel. 15. The system of claim 8, further comprising a valve, wherein the valve regulates fluid flow through the second outlet. 16. The system of claim 15, wherein the valve is actuated by an information handling system. 17. The system of claim 8, further comprising:
a flow restrictor fluidically coupled to the second outlet; wherein the flow restrictor regulates pressure of fluid flow through the second outlet; and wherein the extraction system is operable to extract a gas sample from the fluid sample. 18. The fluid sampling system of claim 17, further comprising a bypass mechanism, wherein the bypass mechanism permits bypassing the extraction system. 19. The fluid sampling system of claim 17, wherein the portion of the fluid flowing through the inlet that is directed into the second outlet flows through the screen. 20. The fluid sampling system of claim 17, further comprising a gas analyzer,
wherein the gas sample is directed to the gas analyzer, and wherein the gas analyzer analyzes the gas sample. | A fluid sampling system ( 220 ) includes an inline fluid extraction body ( 210 ). The inline fluid extraction body comprises an inlet ( 202 ), a first outlet ( 206 ) and a second outlet ( 208 ). A pump ( 214 ) directs a portion of a fluid flowing through the inlet into the second outlet. A flow restrictor ( 222 ) is fluidically coupled to the second outlet and regulates pressure of fluid flow through the second outlet. An extraction system ( 230 ) is fluidically coupled to the second outlet and extracts a gas sample from the fluid sample. The gas sample may then be analyzed by an analyzer.1. A method of analyzing a fluid comprising:
directing the fluid to an inline fluid extraction body;
wherein the inline fluid extraction body comprises a screen, a first outlet and a second outlet;
directing a first portion of the fluid through a first outlet of the inline fluid extraction body;
wherein the first portion of the fluid is directed to a separator;
directing a second portion of the fluid through a second outlet of the inline fluid extraction body;
wherein the second outlet of the inline fluid extraction body is fluidically coupled to the screen;
wherein a pump directs the second portion of the fluid through the second outlet of the inline fluid extraction body;
directing the second portion of the fluid to an Inline TEE; directing a first portion of the second portion of the fluid to an extraction system. 2. The method of claim 1, further comprising monitoring pressure of the second portion of the fluid through the second outlet of the inline fluid extraction body using a pressure transducer. 3. The method of claim 2, wherein the pressure transducer is communicatively coupled to an information handling system. 4. The method of claim 2, further comprising notifying an operator if the pressure of the second portion of the fluid is one of less than a threshold pressure and greater than a threshold pressure. 5. The method of claim 1, further comprising regulating the pressure of the second portion of the fluid through the second outlet of the suction tube assembly using a flow restrictor. 6. The method of claim 1, further comprising directing a second portion of the second portion of the fluid to a separator. 7. The method of claim 6, wherein the second portion of the second portion of the fluid is directed to a separator through a check valve. 8. A system for continuous analysis of a drilling fluid comprising:
a first inlet; an inline fluid extraction body fluidically coupled to the first inlet;
wherein the inline fluid extraction body comprises a suction tube assembly, a first outlet and a second outlet;
wherein the suction tube assembly comprises a screen and a pipe fluidically coupled to the screen;
wherein the first outlet of the inline fluid extraction body is directed to a separator;
wherein the second outlet of the inline fluid extraction body is directed to an extraction system;
wherein a portion of the drilling fluid that is directed through the second outlet of the inline fluid extraction body flows through the suction tube assembly; and
a pump;
wherein the pump pulls the portion of the drilling fluid that is directed through the second outlet. 9. The system of claim 8, further comprising a pressure transducer, wherein the pressure transducer monitors pressure of the portion of the drilling fluid that is directed through the second outlet of the inline fluid extraction body. 10. The system of claim 8, further comprising a flow restrictor for regulating pressure of the portion of the drilling fluid that is directed through the second outlet of the inline fluid extraction body. 11. The system of claim 8, wherein the pump is selected from a group consisting of a positive displacement pump, a mud pump and a hydraulic pump. 12. The system of claim 8, wherein the screen is self cleaning. 13. The system of claim 8, further comprising a bypass mechanism for bypassing the extraction system. 14. The system of claim 8, wherein the screen is stainless steel. 15. The system of claim 8, further comprising a valve, wherein the valve regulates fluid flow through the second outlet. 16. The system of claim 15, wherein the valve is actuated by an information handling system. 17. The system of claim 8, further comprising:
a flow restrictor fluidically coupled to the second outlet; wherein the flow restrictor regulates pressure of fluid flow through the second outlet; and wherein the extraction system is operable to extract a gas sample from the fluid sample. 18. The fluid sampling system of claim 17, further comprising a bypass mechanism, wherein the bypass mechanism permits bypassing the extraction system. 19. The fluid sampling system of claim 17, wherein the portion of the fluid flowing through the inlet that is directed into the second outlet flows through the screen. 20. The fluid sampling system of claim 17, further comprising a gas analyzer,
wherein the gas sample is directed to the gas analyzer, and wherein the gas analyzer analyzes the gas sample. | 2,800 |
11,418 | 11,418 | 15,075,126 | 2,883 | Optical modules as used in various types of communication systems are formed to include a flexible substrate to support various optical, electronic, and opto-electronic module components in a manner that can accommodate various packaging constraints. The flexible substrate is formed of a polyimide film is known to exhibit excellent electrical isolation properties, even though the films are generally relatively thin (on the order of 10-100 μms, in most cases). The flexible polyimide film is sized to accommodate the constraints of a given package “footprint”; more particularly, sized to fit an open ‘floor area’ within package, allowing for a populated film to be placed around various other “fixed-in-place” elements . The polyimide film is easily cut and trimmed to exhibit whatever topology is convenient, while providing enough surface area to support the affixed components and associated optical fiber traces. | 1. An optical module comprising
a plurality of optical components; a plurality of electro-optic components; sections of optical fiber interconnecting the plurality of optical components and the plurality of electro-optic components in a predetermined configuration; and a flexible substrate including an adhesive-coated surface layer, where the plurality of optical components and the plurality of electro-optic components are affixed to the adhesive-coated surface layer and the sections of optical fiber are disposed in paths formed within the adhesive-coated surface layer. 2. The optical module as defined in claim 1 wherein the flexible substrate is formed to include openings for accommodating additional system elements. 3. The optical module as defined in claim 2 wherein the additional system elements include fixed-in-place components. 4. The optical module as defined in claim 1 wherein the flexible substrate comprises multiple layers of flexible material disposed over one another. 5. The optical module as defined in claim 4 wherein at least one layer of flexible material supports a coil of optical fiber. 6. The optical module as defined in claim 5 wherein the coil of optical fiber comprises a coil of rare earth-doped optical fiber utilized for an optical amplifier. 7. The optical module as defined in claim 1 wherein the module further comprises at least one heater element affixed to the adhesive-coated surface layer of the flexible substrate. 8. The optical module as defined in claim 1 wherein the module further comprises at least one cooler element affixed to the adhesive-coated surface layer of the flexible substrate. 9. The optical module as defined in claim 1 wherein the adhesive-coated surface layer comprises a pressure-sensitive adhesive material. 10. The optical module as defined in claim 1 wherein the flexible substrate comprises a film of polyimide material. 11. An optical module comprising
a plurality of optical components; a plurality of electro-optic components; sections of optical fiber interconnecting the plurality of optical components and the plurality of electro-optic components in a predetermined configuration; and a flexible substrate including an adhesive-coated surface layer, where the plurality of optical components and the plurality of electro-optic components are affixed to the adhesive-coated surface layer. 12. An optical module as defined in claim 11 wherein the sections of optical fiber are disposed in paths formed within the adhesive-coated surface layer. | Optical modules as used in various types of communication systems are formed to include a flexible substrate to support various optical, electronic, and opto-electronic module components in a manner that can accommodate various packaging constraints. The flexible substrate is formed of a polyimide film is known to exhibit excellent electrical isolation properties, even though the films are generally relatively thin (on the order of 10-100 μms, in most cases). The flexible polyimide film is sized to accommodate the constraints of a given package “footprint”; more particularly, sized to fit an open ‘floor area’ within package, allowing for a populated film to be placed around various other “fixed-in-place” elements . The polyimide film is easily cut and trimmed to exhibit whatever topology is convenient, while providing enough surface area to support the affixed components and associated optical fiber traces.1. An optical module comprising
a plurality of optical components; a plurality of electro-optic components; sections of optical fiber interconnecting the plurality of optical components and the plurality of electro-optic components in a predetermined configuration; and a flexible substrate including an adhesive-coated surface layer, where the plurality of optical components and the plurality of electro-optic components are affixed to the adhesive-coated surface layer and the sections of optical fiber are disposed in paths formed within the adhesive-coated surface layer. 2. The optical module as defined in claim 1 wherein the flexible substrate is formed to include openings for accommodating additional system elements. 3. The optical module as defined in claim 2 wherein the additional system elements include fixed-in-place components. 4. The optical module as defined in claim 1 wherein the flexible substrate comprises multiple layers of flexible material disposed over one another. 5. The optical module as defined in claim 4 wherein at least one layer of flexible material supports a coil of optical fiber. 6. The optical module as defined in claim 5 wherein the coil of optical fiber comprises a coil of rare earth-doped optical fiber utilized for an optical amplifier. 7. The optical module as defined in claim 1 wherein the module further comprises at least one heater element affixed to the adhesive-coated surface layer of the flexible substrate. 8. The optical module as defined in claim 1 wherein the module further comprises at least one cooler element affixed to the adhesive-coated surface layer of the flexible substrate. 9. The optical module as defined in claim 1 wherein the adhesive-coated surface layer comprises a pressure-sensitive adhesive material. 10. The optical module as defined in claim 1 wherein the flexible substrate comprises a film of polyimide material. 11. An optical module comprising
a plurality of optical components; a plurality of electro-optic components; sections of optical fiber interconnecting the plurality of optical components and the plurality of electro-optic components in a predetermined configuration; and a flexible substrate including an adhesive-coated surface layer, where the plurality of optical components and the plurality of electro-optic components are affixed to the adhesive-coated surface layer. 12. An optical module as defined in claim 11 wherein the sections of optical fiber are disposed in paths formed within the adhesive-coated surface layer. | 2,800 |
11,419 | 11,419 | 15,083,478 | 2,837 | A current transformer apparatus is configured to enable it to be electrically connected with and physically mounted to a circuit board. The current transformer apparatus includes a support upon which a coil is situated and upon which a plurality of approximately U-shaped electrical connectors are also situated. The electrical connectors each include an electrical contact that is biased toward a reaction structure. A circuit board is received between the electrical contact and the reaction structure, and the bias between the electrical contact and the reaction structure mounts current transformer apparatus to the circuit board and provides an electrical connection therebetween | 1. A current transformer apparatus that is structured to be electrically connected with and to be mounted to a circuit board, the current transformer apparatus comprising:
a coil apparatus comprising a wire that is wound into a coil; a support, the coil apparatus being situated on the support; a connection apparatus that comprises a plurality of electrical contacts and a number of reaction structures situated on the support, the plurality of electrical contacts comprising a pair of electrical contacts, an electrical contact of the pair of electrical contacts having an electrical connection with the wire, another electrical contact of the pair of electrical contacts having another electrical connection with the wire, at least one of the at least first reaction structure and the plurality of electrical contacts being biased generally toward the other of the at least first reaction structure and the plurality of electrical contacts and being structured to engage the circuit board between the plurality of electrical contacts and the at least first reaction structure to mount the current transformer apparatus to the circuit board. 2. The current transformer apparatus of claim 1 wherein the number of reaction structures comprise a plurality of reaction structures, and wherein the connection apparatus and the plurality of reaction structures together form a plurality of electrical connectors, each reaction structure of the plurality of reaction structures being situated on a corresponding electrical contact of the plurality of electrical contacts and forming with the corresponding electrical contact an electrical connector of the plurality of electrical connectors that is approximately U-shaped and which comprises a first leg that includes at least a portion of the reaction structure, a second leg that includes at least a portion of the corresponding electrical contact, and a junction where the first and second legs are connected with one another, the first and second legs being biased toward one another and structured to engage the circuit board therebetween to mount the current transformer apparatus to the circuit board. 3. The current transformer apparatus of claim 2 wherein the support further comprises a base, each electrical connector being situated on the base. 4. The current transformer apparatus of claim 3 wherein the base comprises a first wall and a second wall, at least a portion of each electrical connector of the plurality of electrical connectors being retained between the first and second walls. 5. The current transformer apparatus of claim 4 wherein the base further comprises a number of dividers, and wherein at least some of the electrical connectors of the plurality of electrical connectors are arranged in a number of adjacent pairs having situated therebetween a divider of the number of dividers. 6. The current transformer apparatus of claim 5 wherein the number of dividers are each formed at least in part of an electrically insulative material. 7. The current transformer apparatus of claim 4 wherein the base further comprises a number of abutments situated adjacent at least one of the first wall and the second wall and which are engageable with the plurality of electrical connectors to retain the at least portion of each electrical connector between the first and second walls. 8. The current transformer apparatus of claim 7 wherein the support further comprises a housing upon which the coil is situated, the base being situated on the housing. 9. The current transformer apparatus of claim 8 wherein the housing has a wall which at least partially surrounds the coil and on which the base is situated, the wall having formed therein at least a first passage situated adjacent the base and through which a portion of the wire extends. 10. The current transformer apparatus of claim 9 wherein each electrical connector of the plurality of electrical connectors further comprises an elongated pin that is electrically connected with the wire and that is electrically interposed between the wire and the corresponding electrical contact. 11. The current transformer apparatus of claim 10 wherein the pin extends from the junction and is situated adjacent an elongated void that is formed in the electrical connector. 12. The current transformer apparatus of claim 10 wherein the pin is situated adjacent the at least first passage. 13. The current transformer apparatus of claim 1 wherein the coil apparatus further comprises another wire that is wound into another coil, and wherein the plurality of electrical contacts further comprise another pair of electrical contacts that are electrically connected with the another wire. | A current transformer apparatus is configured to enable it to be electrically connected with and physically mounted to a circuit board. The current transformer apparatus includes a support upon which a coil is situated and upon which a plurality of approximately U-shaped electrical connectors are also situated. The electrical connectors each include an electrical contact that is biased toward a reaction structure. A circuit board is received between the electrical contact and the reaction structure, and the bias between the electrical contact and the reaction structure mounts current transformer apparatus to the circuit board and provides an electrical connection therebetween1. A current transformer apparatus that is structured to be electrically connected with and to be mounted to a circuit board, the current transformer apparatus comprising:
a coil apparatus comprising a wire that is wound into a coil; a support, the coil apparatus being situated on the support; a connection apparatus that comprises a plurality of electrical contacts and a number of reaction structures situated on the support, the plurality of electrical contacts comprising a pair of electrical contacts, an electrical contact of the pair of electrical contacts having an electrical connection with the wire, another electrical contact of the pair of electrical contacts having another electrical connection with the wire, at least one of the at least first reaction structure and the plurality of electrical contacts being biased generally toward the other of the at least first reaction structure and the plurality of electrical contacts and being structured to engage the circuit board between the plurality of electrical contacts and the at least first reaction structure to mount the current transformer apparatus to the circuit board. 2. The current transformer apparatus of claim 1 wherein the number of reaction structures comprise a plurality of reaction structures, and wherein the connection apparatus and the plurality of reaction structures together form a plurality of electrical connectors, each reaction structure of the plurality of reaction structures being situated on a corresponding electrical contact of the plurality of electrical contacts and forming with the corresponding electrical contact an electrical connector of the plurality of electrical connectors that is approximately U-shaped and which comprises a first leg that includes at least a portion of the reaction structure, a second leg that includes at least a portion of the corresponding electrical contact, and a junction where the first and second legs are connected with one another, the first and second legs being biased toward one another and structured to engage the circuit board therebetween to mount the current transformer apparatus to the circuit board. 3. The current transformer apparatus of claim 2 wherein the support further comprises a base, each electrical connector being situated on the base. 4. The current transformer apparatus of claim 3 wherein the base comprises a first wall and a second wall, at least a portion of each electrical connector of the plurality of electrical connectors being retained between the first and second walls. 5. The current transformer apparatus of claim 4 wherein the base further comprises a number of dividers, and wherein at least some of the electrical connectors of the plurality of electrical connectors are arranged in a number of adjacent pairs having situated therebetween a divider of the number of dividers. 6. The current transformer apparatus of claim 5 wherein the number of dividers are each formed at least in part of an electrically insulative material. 7. The current transformer apparatus of claim 4 wherein the base further comprises a number of abutments situated adjacent at least one of the first wall and the second wall and which are engageable with the plurality of electrical connectors to retain the at least portion of each electrical connector between the first and second walls. 8. The current transformer apparatus of claim 7 wherein the support further comprises a housing upon which the coil is situated, the base being situated on the housing. 9. The current transformer apparatus of claim 8 wherein the housing has a wall which at least partially surrounds the coil and on which the base is situated, the wall having formed therein at least a first passage situated adjacent the base and through which a portion of the wire extends. 10. The current transformer apparatus of claim 9 wherein each electrical connector of the plurality of electrical connectors further comprises an elongated pin that is electrically connected with the wire and that is electrically interposed between the wire and the corresponding electrical contact. 11. The current transformer apparatus of claim 10 wherein the pin extends from the junction and is situated adjacent an elongated void that is formed in the electrical connector. 12. The current transformer apparatus of claim 10 wherein the pin is situated adjacent the at least first passage. 13. The current transformer apparatus of claim 1 wherein the coil apparatus further comprises another wire that is wound into another coil, and wherein the plurality of electrical contacts further comprise another pair of electrical contacts that are electrically connected with the another wire. | 2,800 |
11,420 | 11,420 | 14,998,270 | 2,829 | Technologies for adaptive bandwidth reduction for an Internet of Things (IoT) gateway device are disclosed. The IoT gateway device receives data from one or more sensors, and determines a mathematical model to represent the sensor data. Certain aspects of the mathematical model used, such as the quantity of coefficients and the precision of the coefficients are determined based on the sensor data. For example, if the sensor data is within a normal range, a relatively small number of coefficients might be used, but if the sensor data is past or near an alert threshold, a larger number of coefficients might be used, which allows for the behavior of the sensor data to be better represented. | 1. An Internet of Things (IoT) gateway device for transmitting sensor data, the IoT gateway device comprising:
a sensor data capture module to receive, from a sensor, sensor data; a sensor data representation module to determine a mathematical model to represent the sensor data based on a trend of the sensor data, wherein to determine the mathematical model comprises to (i) determine a number, n, of coefficients to be used in the mathematical model and (ii) determine a value of a plurality of coefficients of the mathematical model; and a communication module to send the values of the plurality of coefficients to a cloud compute device. 2. The IoT gateway device of claim 1, wherein to send the values of the plurality of coefficients comprises to send n coefficients of the plurality of coefficients to the cloud compute device. 3. The IoT gateway device of claim 1, wherein to determine the mathematical model further comprises to determine, based on the trend of the sensor data, a precision of the plurality of coefficients. 4. The IoT gateway device of claim 1, wherein to determine the mathematical model further comprises to determine, based on the trend, a type of the mathematical model. 5. The IoT gateway device of claim 4, wherein the type of the mathematical model is a polynomial fit. 6. The IoT gateway device of claim 1, wherein the sensor data representation module is further to determine, based on the sensor data, a future sampling frequency associated with the sensor. 7. The IoT gateway device of claim 6, wherein the communication module is further to instruct the sensor to send future sensor data sampled at a frequency based on the future sampling frequency. 8. The IoT gateway device of claim 1, wherein to determine the mathematical model comprises to determine the mathematical model based on a comparison performed by the IoT gateway device of the sensor data to an alert threshold. 9. The IoT gateway device of claim 1, wherein to determine the mathematical model comprises to determine the mathematical model based on a comparison performed by the IoT gateway device of past sensor data to an alert threshold. 10. One or more computer-readable media comprising a plurality of instructions stored thereon that, when executed, cause an Internet of Things (IoT) gateway device to:
receive, from a sensor, sensor data; determine a mathematical model to represent the sensor data based on a trend of the sensor data, wherein to determine the mathematical model comprises to (i) determine a number, n, of coefficients to be used in the mathematical model and (ii) determine a value of a plurality of coefficients of the mathematical model; and send the values of the plurality of coefficients to a cloud compute device. 11. The one or more computer-readable media of claim 10, wherein to send the values of the plurality of coefficients comprises to send n coefficients of the plurality of coefficients to the cloud compute device. 12. The one or more computer-readable media of claim 10, wherein to determine the mathematical model further comprises to determine, based on the trend, a type of the mathematical model. 13. The one or more computer-readable media of claim 12, wherein the type of the mathematical model is a polynomial fit. 14. The one or more computer-readable media of claim 10, wherein the plurality of instructions further cause the IoT gateway device to determine, based on the sensor data, a future sampling frequency associated with the sensor. 15. The one or more computer-readable media of claim 14, wherein the plurality of instructions further cause the IoT gateway device to instruct the sensor to send future sensor data sampled at a frequency based on the future sampling frequency. 16. The one or more computer-readable media of claim 10, wherein to determine the mathematical model comprises to determine the mathematical model based on a comparison performed by the IoT gateway device of the sensor data to an alert threshold. 17. The one or more computer-readable media of claim 10, wherein to determine the mathematical model comprises to determine the mathematical model based on a comparison performed by the IoT gateway device of past sensor data to an alert threshold. 18. A method for transmitting sensor data by an Internet of Things (IoT) gateway device, the method comprising:
receiving, by the IoT gateway device and from a sensor, sensor data; determining, by the IoT gateway device, a mathematical model to represent the sensor data based on a trend of the sensor data, wherein determining the mathematical model comprises (i) determining a number, n, of coefficients to be used in the mathematical model and (ii) determining a value of a plurality of coefficients of the mathematical model; and sending, by the IoT gateway device, the values of the plurality of coefficients to a cloud compute device. 19. The method of claim 18, wherein sending the values of the plurality of coefficients comprises sending n coefficients of the plurality of coefficients to the cloud compute device. 20. The method of claim 18, wherein determining the mathematical model further comprises determining, based on the trend, a type of the mathematical model. 21. The method of claim 20, wherein the type of the mathematical model is a polynomial fit. 22. The method of claim 18, further comprising determining, by the IoT gateway device and based on the sensor data, a future sampling frequency associated with the sensor. 23. The method of claim 22, further comprising instructing, by the IoT gateway device, the sensor to send future sensor data sampled at a frequency based on the future sampling frequency. 24. The method of claim 18, wherein determining the mathematical model comprises determining the mathematical model based on a comparison performed by the IoT gateway device of the sensor data to an alert threshold. 25. The method of claim 18, wherein determining the mathematical model comprises determining the mathematical model based on a comparison performed by the IoT gateway device of past sensor data to an alert threshold. | Technologies for adaptive bandwidth reduction for an Internet of Things (IoT) gateway device are disclosed. The IoT gateway device receives data from one or more sensors, and determines a mathematical model to represent the sensor data. Certain aspects of the mathematical model used, such as the quantity of coefficients and the precision of the coefficients are determined based on the sensor data. For example, if the sensor data is within a normal range, a relatively small number of coefficients might be used, but if the sensor data is past or near an alert threshold, a larger number of coefficients might be used, which allows for the behavior of the sensor data to be better represented.1. An Internet of Things (IoT) gateway device for transmitting sensor data, the IoT gateway device comprising:
a sensor data capture module to receive, from a sensor, sensor data; a sensor data representation module to determine a mathematical model to represent the sensor data based on a trend of the sensor data, wherein to determine the mathematical model comprises to (i) determine a number, n, of coefficients to be used in the mathematical model and (ii) determine a value of a plurality of coefficients of the mathematical model; and a communication module to send the values of the plurality of coefficients to a cloud compute device. 2. The IoT gateway device of claim 1, wherein to send the values of the plurality of coefficients comprises to send n coefficients of the plurality of coefficients to the cloud compute device. 3. The IoT gateway device of claim 1, wherein to determine the mathematical model further comprises to determine, based on the trend of the sensor data, a precision of the plurality of coefficients. 4. The IoT gateway device of claim 1, wherein to determine the mathematical model further comprises to determine, based on the trend, a type of the mathematical model. 5. The IoT gateway device of claim 4, wherein the type of the mathematical model is a polynomial fit. 6. The IoT gateway device of claim 1, wherein the sensor data representation module is further to determine, based on the sensor data, a future sampling frequency associated with the sensor. 7. The IoT gateway device of claim 6, wherein the communication module is further to instruct the sensor to send future sensor data sampled at a frequency based on the future sampling frequency. 8. The IoT gateway device of claim 1, wherein to determine the mathematical model comprises to determine the mathematical model based on a comparison performed by the IoT gateway device of the sensor data to an alert threshold. 9. The IoT gateway device of claim 1, wherein to determine the mathematical model comprises to determine the mathematical model based on a comparison performed by the IoT gateway device of past sensor data to an alert threshold. 10. One or more computer-readable media comprising a plurality of instructions stored thereon that, when executed, cause an Internet of Things (IoT) gateway device to:
receive, from a sensor, sensor data; determine a mathematical model to represent the sensor data based on a trend of the sensor data, wherein to determine the mathematical model comprises to (i) determine a number, n, of coefficients to be used in the mathematical model and (ii) determine a value of a plurality of coefficients of the mathematical model; and send the values of the plurality of coefficients to a cloud compute device. 11. The one or more computer-readable media of claim 10, wherein to send the values of the plurality of coefficients comprises to send n coefficients of the plurality of coefficients to the cloud compute device. 12. The one or more computer-readable media of claim 10, wherein to determine the mathematical model further comprises to determine, based on the trend, a type of the mathematical model. 13. The one or more computer-readable media of claim 12, wherein the type of the mathematical model is a polynomial fit. 14. The one or more computer-readable media of claim 10, wherein the plurality of instructions further cause the IoT gateway device to determine, based on the sensor data, a future sampling frequency associated with the sensor. 15. The one or more computer-readable media of claim 14, wherein the plurality of instructions further cause the IoT gateway device to instruct the sensor to send future sensor data sampled at a frequency based on the future sampling frequency. 16. The one or more computer-readable media of claim 10, wherein to determine the mathematical model comprises to determine the mathematical model based on a comparison performed by the IoT gateway device of the sensor data to an alert threshold. 17. The one or more computer-readable media of claim 10, wherein to determine the mathematical model comprises to determine the mathematical model based on a comparison performed by the IoT gateway device of past sensor data to an alert threshold. 18. A method for transmitting sensor data by an Internet of Things (IoT) gateway device, the method comprising:
receiving, by the IoT gateway device and from a sensor, sensor data; determining, by the IoT gateway device, a mathematical model to represent the sensor data based on a trend of the sensor data, wherein determining the mathematical model comprises (i) determining a number, n, of coefficients to be used in the mathematical model and (ii) determining a value of a plurality of coefficients of the mathematical model; and sending, by the IoT gateway device, the values of the plurality of coefficients to a cloud compute device. 19. The method of claim 18, wherein sending the values of the plurality of coefficients comprises sending n coefficients of the plurality of coefficients to the cloud compute device. 20. The method of claim 18, wherein determining the mathematical model further comprises determining, based on the trend, a type of the mathematical model. 21. The method of claim 20, wherein the type of the mathematical model is a polynomial fit. 22. The method of claim 18, further comprising determining, by the IoT gateway device and based on the sensor data, a future sampling frequency associated with the sensor. 23. The method of claim 22, further comprising instructing, by the IoT gateway device, the sensor to send future sensor data sampled at a frequency based on the future sampling frequency. 24. The method of claim 18, wherein determining the mathematical model comprises determining the mathematical model based on a comparison performed by the IoT gateway device of the sensor data to an alert threshold. 25. The method of claim 18, wherein determining the mathematical model comprises determining the mathematical model based on a comparison performed by the IoT gateway device of past sensor data to an alert threshold. | 2,800 |
11,421 | 11,421 | 15,287,255 | 2,898 | Various circuit boards and methods of fabricating and using the same are disclosed. In one aspect, a system is provided that has a circuit board with a pocket and a conductor layer. A chiplet is positioned in the pocket. The chiplet has plural bottom side interconnects electrically connected to the conductor layer and plural top side interconnects adapted to interconnect with two or more semiconductor chips. | 1. A system, comprising:
a circuit board having a pocket and a conductor layer; and a chiplet positioned in the pocket, the chiplet being an organic circuit board and having plural bottom side interconnects electrically connected to the conductor layer and plural top side interconnects adapted to interconnect with two or more semiconductor chips. 2. The system of claim 1, wherein the circuit board comprises a package substrate. 3. The system of claim 1, wherein the circuit board comprises plural build-up layers, the pocket extending vertically into at least one of the build-up layers. 4. The system of claim 1, wherein the organic circuit board comprises plural build-up layers. 5. The system of claim 1, wherein the organic circuit board comprises a monolithic organic structure. 6. The system of claim 1, wherein the bottom side has a central portion and edge portions, the bottom side interconnects being positioned at the central portion and the edge portions of the chiplet. 7. The system of claim 1, wherein the circuit board comprises circuit structures arranged according to a first design rule of a first density, the chiplet comprising circuit structures arranged according to a second design rule of second density smaller than the first density. 8. The system of claim 1, comprising a first semiconductor chip mounted on the circuit board and a second semiconductor chip mounted on the circuit board, the first semiconductor chip being interconnected to the second semiconductor chip by the chiplet. 9. A method of manufacturing a circuit board, comprising:
providing a substrate having a conductor layer; fabricating a pocket in the substrate; positioning a chiplet in the pocket, the chiplet having plural bottom side interconnects and plural top side interconnects, the top side interconnects adapted to interconnect with two or more semiconductor chips; and electrically connecting the bottom side interconnects to the conductor layer. 10. The method of claim 9, wherein the circuit board comprises a package substrate. 11. The method of claim 9, wherein the substrate comprises plural build-up layers, the method comprising fabricating the pocket to extend vertically into at least one of the build-up layers. 12. The method of claim 9, wherein the chiplet comprises an organic circuit board. 13. The method of claim 9, wherein the chiplet comprises a ceramic circuit board. 14. The method of claim 9, wherein the chiplet comprises a semiconductor chip. 15. The method of claim 9, wherein the circuit board comprises circuit structures arranged according to a first design rule of a first density, the chiplet comprising circuit structures arranged according to a second design rule of second density smaller than the first density. 16. The method of claim 9, comprising mounting a first semiconductor chip on the circuit board and a second semiconductor chip on the circuit board, and electrically connecting the first semiconductor chip to the second semiconductor chip with the chiplet. 17. A method of manufacturing, comprising:
fabricating a chiplet to insert into a pocket of a circuit board, the chiplet having plural bottom side interconnects to electrically connect to a conductor layer of the circuit board and plural top side interconnects adapted to interconnect with two or more semiconductor chips. 18. The method of claim 17, wherein the circuit board comprises a package substrate. 19. The method of claim 17, wherein the circuit board comprises plural build-up layers, the pocket extending vertically into at least one of the build-up layers. 20. The method of claim 17, wherein the chiplet comprises an organic circuit board, a ceramic circuit board or a semiconductor chip. | Various circuit boards and methods of fabricating and using the same are disclosed. In one aspect, a system is provided that has a circuit board with a pocket and a conductor layer. A chiplet is positioned in the pocket. The chiplet has plural bottom side interconnects electrically connected to the conductor layer and plural top side interconnects adapted to interconnect with two or more semiconductor chips.1. A system, comprising:
a circuit board having a pocket and a conductor layer; and a chiplet positioned in the pocket, the chiplet being an organic circuit board and having plural bottom side interconnects electrically connected to the conductor layer and plural top side interconnects adapted to interconnect with two or more semiconductor chips. 2. The system of claim 1, wherein the circuit board comprises a package substrate. 3. The system of claim 1, wherein the circuit board comprises plural build-up layers, the pocket extending vertically into at least one of the build-up layers. 4. The system of claim 1, wherein the organic circuit board comprises plural build-up layers. 5. The system of claim 1, wherein the organic circuit board comprises a monolithic organic structure. 6. The system of claim 1, wherein the bottom side has a central portion and edge portions, the bottom side interconnects being positioned at the central portion and the edge portions of the chiplet. 7. The system of claim 1, wherein the circuit board comprises circuit structures arranged according to a first design rule of a first density, the chiplet comprising circuit structures arranged according to a second design rule of second density smaller than the first density. 8. The system of claim 1, comprising a first semiconductor chip mounted on the circuit board and a second semiconductor chip mounted on the circuit board, the first semiconductor chip being interconnected to the second semiconductor chip by the chiplet. 9. A method of manufacturing a circuit board, comprising:
providing a substrate having a conductor layer; fabricating a pocket in the substrate; positioning a chiplet in the pocket, the chiplet having plural bottom side interconnects and plural top side interconnects, the top side interconnects adapted to interconnect with two or more semiconductor chips; and electrically connecting the bottom side interconnects to the conductor layer. 10. The method of claim 9, wherein the circuit board comprises a package substrate. 11. The method of claim 9, wherein the substrate comprises plural build-up layers, the method comprising fabricating the pocket to extend vertically into at least one of the build-up layers. 12. The method of claim 9, wherein the chiplet comprises an organic circuit board. 13. The method of claim 9, wherein the chiplet comprises a ceramic circuit board. 14. The method of claim 9, wherein the chiplet comprises a semiconductor chip. 15. The method of claim 9, wherein the circuit board comprises circuit structures arranged according to a first design rule of a first density, the chiplet comprising circuit structures arranged according to a second design rule of second density smaller than the first density. 16. The method of claim 9, comprising mounting a first semiconductor chip on the circuit board and a second semiconductor chip on the circuit board, and electrically connecting the first semiconductor chip to the second semiconductor chip with the chiplet. 17. A method of manufacturing, comprising:
fabricating a chiplet to insert into a pocket of a circuit board, the chiplet having plural bottom side interconnects to electrically connect to a conductor layer of the circuit board and plural top side interconnects adapted to interconnect with two or more semiconductor chips. 18. The method of claim 17, wherein the circuit board comprises a package substrate. 19. The method of claim 17, wherein the circuit board comprises plural build-up layers, the pocket extending vertically into at least one of the build-up layers. 20. The method of claim 17, wherein the chiplet comprises an organic circuit board, a ceramic circuit board or a semiconductor chip. | 2,800 |
11,422 | 11,422 | 15,677,240 | 2,844 | An apparatus includes: a first inverter configured to receive a first clock signal and output a second clock signal, wherein an input pin, an output pin, a power pin, and a ground pin of the first inverter connect to the first clock signal, the second clock signal, a first source node, and a second source node, respectively; a second inverter configured to receive the second clock signal and output a third clock signal, wherein an input pin, an output pin, a power pin, and a ground pin of the second inverter connect to the second clock signal, the third clock signal, the first source node, and the second source node, respectively; a first resistor connected to a first DC (direct-current) voltage to the first source node; and a second resistor connected to a second DC voltage to the second source node. | 1. A clock buffer circuit comprising:
a first inverter configured to receive a first clock signal and output a second clock signal, wherein an input pin, a power pin, and a ground pin of the first inverter directly connect to the first clock signal, a first source node, and a second source node, respectively, and wherein an output pin of the first inverter generates the second clock signal; a second inverter configured to receive the second clock signal and output a third clock signal, wherein an input pin, a power pin, and a ground pin of the second inverter directly connect to the second clock signal, the first source node, and the second source node, respectively, and wherein an output pin of the second inverter generates the third clock signal; a first resistor directly connected between a first DC (direct-current) voltage and the first source node; and a second resistor directly connected between a second DC voltage and the second source node, wherein the first source node is connected to the first DC voltage only through the first resistor, and the second source node is connected to the second DC voltage only through the second resistor, thereby configuring the circuit to have improved noise immunity. 2. The apparatus of claim 1, wherein the first inverter includes a PMOS (p-channel metal oxide semiconductor) transistor and a NMOS (n-channel metal oxide semiconductor) transistor, wherein a gate terminal and a source terminal of the PMOS transistor connect to the input pin and the power pin of the first inverter, respectively, while a gate terminal and a source terminal of the NMOS transistor connect to the input pin and the ground pin of the first inverter, respectively. 3. The apparatus of claim 1, wherein the second inverter includes a PMOS (p-channel metal oxide semiconductor) transistor and a NMOS (n-channel metal oxide semiconductor) transistor, wherein a gate terminal and a source terminal of the PMOS transistor connect to the input pin and the power pin of the second inverter, respectively, while a gate terminal and a source terminal of the NMOS transistor connect to the input pin and the ground pin of the second inverter, respectively. 4. The apparatus of claim 1, wherein the second inverter is substantially identical to the first inverter. 5. A method for improving noise immunity in a clock buffer circuit comprising:
incorporating a first inverter configured to receive a first clock signal and output a second clock signal, wherein an input pin, a power pin, and a ground pin of the first inverter directly connect to the first clock signal, the second clock signal, a first source node, and a second source node, respectively, and wherein an output pin of the first inverter generates the second clock signal; incorporating a second inverter configured to receive the second clock signal and output a third clock signal, wherein an input pin, a power pin, and a ground pin of the second inverter directly connect to the second clock signal, the third clock signal, the first source node, and the second source node, respectively, and wherein an output pin of the second inverter generates the third clock signal; incorporating a first resistor to directly connect a first DC voltage to the first source node; and incorporating a second resistor to directly connect a second DC voltage to the second source node, wherein the first source node is connected to the first DC voltage only through the first resistor and the second source node is connected to the second DC voltage only through the second resistor, thereby configuring the circuit to have improved noise immunity. 6. The method of claim 5, wherein the first inverter includes a PMOS (p-channel metal oxide semiconductor) transistor and a NMOS (n-channel metal oxide semiconductor) transistor, wherein a gate terminal and a source terminal of the PMOS transistor connect to the input pin and the power pin of the first inverter, respectively, while a gate terminal and a source terminal of the NMOS transistor connect to the input pin and the ground pin of the first inverter, respectively. 7. The method of claim 5, wherein the second inverter includes a PMOS (p-channel metal oxide semiconductor) transistor and a NMOS (n-channel metal oxide semiconductor) transistor, wherein a gate terminal and a source terminal of the PMOS transistor connect to the input pin and the power pin of the second inverter, respectively, while a gate terminal and a source terminal of the NMOS transistor connect to the input pin and the ground pin of the second inverter, respectively. 8. The method of claim 5, wherein the second inverter is substantially identical to the first inverter. | An apparatus includes: a first inverter configured to receive a first clock signal and output a second clock signal, wherein an input pin, an output pin, a power pin, and a ground pin of the first inverter connect to the first clock signal, the second clock signal, a first source node, and a second source node, respectively; a second inverter configured to receive the second clock signal and output a third clock signal, wherein an input pin, an output pin, a power pin, and a ground pin of the second inverter connect to the second clock signal, the third clock signal, the first source node, and the second source node, respectively; a first resistor connected to a first DC (direct-current) voltage to the first source node; and a second resistor connected to a second DC voltage to the second source node.1. A clock buffer circuit comprising:
a first inverter configured to receive a first clock signal and output a second clock signal, wherein an input pin, a power pin, and a ground pin of the first inverter directly connect to the first clock signal, a first source node, and a second source node, respectively, and wherein an output pin of the first inverter generates the second clock signal; a second inverter configured to receive the second clock signal and output a third clock signal, wherein an input pin, a power pin, and a ground pin of the second inverter directly connect to the second clock signal, the first source node, and the second source node, respectively, and wherein an output pin of the second inverter generates the third clock signal; a first resistor directly connected between a first DC (direct-current) voltage and the first source node; and a second resistor directly connected between a second DC voltage and the second source node, wherein the first source node is connected to the first DC voltage only through the first resistor, and the second source node is connected to the second DC voltage only through the second resistor, thereby configuring the circuit to have improved noise immunity. 2. The apparatus of claim 1, wherein the first inverter includes a PMOS (p-channel metal oxide semiconductor) transistor and a NMOS (n-channel metal oxide semiconductor) transistor, wherein a gate terminal and a source terminal of the PMOS transistor connect to the input pin and the power pin of the first inverter, respectively, while a gate terminal and a source terminal of the NMOS transistor connect to the input pin and the ground pin of the first inverter, respectively. 3. The apparatus of claim 1, wherein the second inverter includes a PMOS (p-channel metal oxide semiconductor) transistor and a NMOS (n-channel metal oxide semiconductor) transistor, wherein a gate terminal and a source terminal of the PMOS transistor connect to the input pin and the power pin of the second inverter, respectively, while a gate terminal and a source terminal of the NMOS transistor connect to the input pin and the ground pin of the second inverter, respectively. 4. The apparatus of claim 1, wherein the second inverter is substantially identical to the first inverter. 5. A method for improving noise immunity in a clock buffer circuit comprising:
incorporating a first inverter configured to receive a first clock signal and output a second clock signal, wherein an input pin, a power pin, and a ground pin of the first inverter directly connect to the first clock signal, the second clock signal, a first source node, and a second source node, respectively, and wherein an output pin of the first inverter generates the second clock signal; incorporating a second inverter configured to receive the second clock signal and output a third clock signal, wherein an input pin, a power pin, and a ground pin of the second inverter directly connect to the second clock signal, the third clock signal, the first source node, and the second source node, respectively, and wherein an output pin of the second inverter generates the third clock signal; incorporating a first resistor to directly connect a first DC voltage to the first source node; and incorporating a second resistor to directly connect a second DC voltage to the second source node, wherein the first source node is connected to the first DC voltage only through the first resistor and the second source node is connected to the second DC voltage only through the second resistor, thereby configuring the circuit to have improved noise immunity. 6. The method of claim 5, wherein the first inverter includes a PMOS (p-channel metal oxide semiconductor) transistor and a NMOS (n-channel metal oxide semiconductor) transistor, wherein a gate terminal and a source terminal of the PMOS transistor connect to the input pin and the power pin of the first inverter, respectively, while a gate terminal and a source terminal of the NMOS transistor connect to the input pin and the ground pin of the first inverter, respectively. 7. The method of claim 5, wherein the second inverter includes a PMOS (p-channel metal oxide semiconductor) transistor and a NMOS (n-channel metal oxide semiconductor) transistor, wherein a gate terminal and a source terminal of the PMOS transistor connect to the input pin and the power pin of the second inverter, respectively, while a gate terminal and a source terminal of the NMOS transistor connect to the input pin and the ground pin of the second inverter, respectively. 8. The method of claim 5, wherein the second inverter is substantially identical to the first inverter. | 2,800 |
11,423 | 11,423 | 14,712,871 | 2,825 | Systems, methods and non-transitory, computer-readable mediums are disclosed for pedestrian pace estimation with pace change detection. In some implementations, a method comprises: receiving, by a processor of a mobile device, raw pedometer data from a pedometer included in or coupled to the mobile device; receiving, by the processor, raw GNSS data from a GNSS receiver included in or coupled to the mobile device; estimating, using a first filter implemented on the processor, a step frequency of a user wearing or holding the mobile device, the estimating including using the raw pedometer data; determining, by the processor, a pace change, the pace change determined from the estimated step frequency; responsive to the pace change, adapting by the processor, a bandwidth of a second filter implemented by the processor; and estimating, by the second filter, an estimated pace or speed of the user. | 1. A method comprising:
receiving, by a processor of a mobile device, raw pedometer data from a pedometer included in or coupled to the mobile device; receiving, by the processor, raw Global Navigation Satellite System (GNSS) data from a GNSS receiver included in or coupled to the mobile device; estimating, using a first filter implemented on the processor, a step frequency of a user wearing or holding the mobile device, the estimating including using the raw pedometer data; determining, by the processor, a pace change, the pace change determined from the estimated step frequency; responsive to the pace change, adapting by the processor, a bandwidth of a second filter implemented by the processor; and estimating, by the second filter, an estimated pace or speed of the user. 2. The method of claim 1, wherein the raw pedometer data is step count or step frequency and the raw GNSS data is speed or velocity. 3. The method of claim 1, wherein the pace change is determined by comparing estimated step frequency with a threshold value. 4. The method of claim 1, wherein the first and second filters are Kalman filters. 5. The method of claim 4, wherein the first Kalman filter is configured to estimate step count and step frequency using raw step counts and the second Kalman filter is configured to estimate GNSS speed. 6. The method of claim 5, wherein the second Kalman filter is configured to estimate GNSS speed and pedometer bias. 7. The method of claim 6, wherein adapting the bandwidth of the second filter further comprises:
replacing a process noise value in the second Kalman filter with a different process noise value. 8. The method of claim 7, wherein the different process noise value is used by the second Kalman filter for a time window and then reverts back to a previous process noise value or another process noise value. 9. The method of claim 1, further comprising:
determining a change in a motion activity classification; and adapting the bandwidth of the second filter based on the determining. 10. The method of claim 1, wherein determining a pace change further comprises:
filtering, by a moving median filter, a set of step frequency estimates; and determining the pace change based on a median estimated step frequency determined by the moving median filter. 11. A system comprising:
one or more processors; one or more computer-readable mediums coupled to the one or more processors and configured to store instructions, which, when executed by the one or more processors, causes the one or more processors to perform operations comprising: receiving, by a processor of a mobile device, raw pedometer data from a pedometer included in or coupled to the mobile device; receiving, by the processor, raw Global Navigation Satellite System (GNSS) data from a GNSS receiver included in or coupled to the mobile device; estimating, using a first filter implemented on the processor, a step frequency of a user wearing or holding the mobile device, the estimating including using the raw pedometer data; determining, by the processor, a pace change, the pace change determined from the estimated step frequency; responsive to the pace change, adapting by the processor, a bandwidth of a second filter implemented by the processor; and estimating, by the second filter, an estimated pace or speed of the user. 12. The system of claim 11, wherein the raw pedometer data is step count or step frequency and the raw GNSS data is speed or velocity. 13. The system of claim 11, wherein the pace change is determined by comparing estimated step frequency with a threshold value. 14. The system of claim 11, wherein the first and second filters are Kalman filters. 15. The system of claim 14, wherein the first Kalman filter is configured to estimate step count and step frequency using raw step counts and the second Kalman filter is configured to estimate GNSS speed. 16. The system of claim 15, wherein the second Kalman filter is configured to estimate GNSS speed and pedometer bias. 17. The system of claim 16, wherein adapting the bandwidth of the second filter further comprises:
replacing a process noise value in the second Kalman filter with a different process noise value. 18. The system of claim 17, wherein the different process noise value is used by the second Kalman filter for a time window and then reverts back to a previous process noise value or another process noise value. 19. The system of claim 11, wherein the operations further comprise:
determining a change in a motion activity classification; and adapting the bandwidth of the second filter based on the determining. 20. The system of claim 11, wherein determining a pace change further comprises:
filtering, by a moving median filter, a set of step frequency estimates; and determining the pace change based on a median estimated step frequency determined by the moving median filter. | Systems, methods and non-transitory, computer-readable mediums are disclosed for pedestrian pace estimation with pace change detection. In some implementations, a method comprises: receiving, by a processor of a mobile device, raw pedometer data from a pedometer included in or coupled to the mobile device; receiving, by the processor, raw GNSS data from a GNSS receiver included in or coupled to the mobile device; estimating, using a first filter implemented on the processor, a step frequency of a user wearing or holding the mobile device, the estimating including using the raw pedometer data; determining, by the processor, a pace change, the pace change determined from the estimated step frequency; responsive to the pace change, adapting by the processor, a bandwidth of a second filter implemented by the processor; and estimating, by the second filter, an estimated pace or speed of the user.1. A method comprising:
receiving, by a processor of a mobile device, raw pedometer data from a pedometer included in or coupled to the mobile device; receiving, by the processor, raw Global Navigation Satellite System (GNSS) data from a GNSS receiver included in or coupled to the mobile device; estimating, using a first filter implemented on the processor, a step frequency of a user wearing or holding the mobile device, the estimating including using the raw pedometer data; determining, by the processor, a pace change, the pace change determined from the estimated step frequency; responsive to the pace change, adapting by the processor, a bandwidth of a second filter implemented by the processor; and estimating, by the second filter, an estimated pace or speed of the user. 2. The method of claim 1, wherein the raw pedometer data is step count or step frequency and the raw GNSS data is speed or velocity. 3. The method of claim 1, wherein the pace change is determined by comparing estimated step frequency with a threshold value. 4. The method of claim 1, wherein the first and second filters are Kalman filters. 5. The method of claim 4, wherein the first Kalman filter is configured to estimate step count and step frequency using raw step counts and the second Kalman filter is configured to estimate GNSS speed. 6. The method of claim 5, wherein the second Kalman filter is configured to estimate GNSS speed and pedometer bias. 7. The method of claim 6, wherein adapting the bandwidth of the second filter further comprises:
replacing a process noise value in the second Kalman filter with a different process noise value. 8. The method of claim 7, wherein the different process noise value is used by the second Kalman filter for a time window and then reverts back to a previous process noise value or another process noise value. 9. The method of claim 1, further comprising:
determining a change in a motion activity classification; and adapting the bandwidth of the second filter based on the determining. 10. The method of claim 1, wherein determining a pace change further comprises:
filtering, by a moving median filter, a set of step frequency estimates; and determining the pace change based on a median estimated step frequency determined by the moving median filter. 11. A system comprising:
one or more processors; one or more computer-readable mediums coupled to the one or more processors and configured to store instructions, which, when executed by the one or more processors, causes the one or more processors to perform operations comprising: receiving, by a processor of a mobile device, raw pedometer data from a pedometer included in or coupled to the mobile device; receiving, by the processor, raw Global Navigation Satellite System (GNSS) data from a GNSS receiver included in or coupled to the mobile device; estimating, using a first filter implemented on the processor, a step frequency of a user wearing or holding the mobile device, the estimating including using the raw pedometer data; determining, by the processor, a pace change, the pace change determined from the estimated step frequency; responsive to the pace change, adapting by the processor, a bandwidth of a second filter implemented by the processor; and estimating, by the second filter, an estimated pace or speed of the user. 12. The system of claim 11, wherein the raw pedometer data is step count or step frequency and the raw GNSS data is speed or velocity. 13. The system of claim 11, wherein the pace change is determined by comparing estimated step frequency with a threshold value. 14. The system of claim 11, wherein the first and second filters are Kalman filters. 15. The system of claim 14, wherein the first Kalman filter is configured to estimate step count and step frequency using raw step counts and the second Kalman filter is configured to estimate GNSS speed. 16. The system of claim 15, wherein the second Kalman filter is configured to estimate GNSS speed and pedometer bias. 17. The system of claim 16, wherein adapting the bandwidth of the second filter further comprises:
replacing a process noise value in the second Kalman filter with a different process noise value. 18. The system of claim 17, wherein the different process noise value is used by the second Kalman filter for a time window and then reverts back to a previous process noise value or another process noise value. 19. The system of claim 11, wherein the operations further comprise:
determining a change in a motion activity classification; and adapting the bandwidth of the second filter based on the determining. 20. The system of claim 11, wherein determining a pace change further comprises:
filtering, by a moving median filter, a set of step frequency estimates; and determining the pace change based on a median estimated step frequency determined by the moving median filter. | 2,800 |
11,424 | 11,424 | 14,581,233 | 2,894 | A method of making Flat No-Lead Packages with plated lead surfaces exposed on lateral faces thereof. The method includes providing a plurality of Flat No-Lead Packages having severed, unplated lead surfaces exposed on lateral faces thereof and having plated lead surfaces exposed on bottom faces thereof. The method further includes batch electroplating the severed unplated lead surfaces of the plurality of Flat No-Lead Packages. | 1. A method of making Flat No-Lead Packages with plated lead surfaces exposed on lateral sidewall surfaces of said Flat No-Lead Packages comprising:
providing a plurality of Flat No-Lead Packages having severed, unplated lead surfaces exposed on lateral faces thereof and having plated lead surfaces exposed on bottom faces thereof; and batch electroplating the severed unplated lead surfaces of the plurality of Flat No-Lead Packages. 2. The method of claim 1 wherein said electroplating the severed unplated lead surfaces comprises:
electrically connecting a conductive strip to the plated lead portions of the plurality of Flat No-Lead Packages;
placing the Flat No-Lead Packages and the connected conductor strip in an electroplating bath; and
passing an electrical current through the conductor strip and the electroplating bath. 3. The method of claim 1 wherein said providing a plurality of Flat No-Lead Packages comprises providing a molded leadframe assembly having a plurality of integrally connected leadframes and a plurality of dies mounted on corresponding die pad portions of the plurality of integrally connected leadframes the dies being wire bonded to lead portions of the leadframes. 4. The method of claim 2 wherein said providing a plurality of Flat No-Lead Packages comprises plating exposed lead portions of the plurality of leadframes in the molded leadframe assembly. 5. The method of claim 4 wherein said providing a plurality of Flat No-Lead Packages comprises singulating the plated molded leadframe assembly into a plurality of Flat No-Lead Packages having plated lead surfaces exposed at a bottom surface thereof and severed and unplated lead surfaces exposed at sidewall portions thereof. 6. The method of claim 4 further comprising arranging the plurality of Flat No-Lead Packages in a grid. 7. The method of claim 6 wherein arranging the plurality of Flat No-Lead Packages in a grid comprises placing said plurality of Flat No-Lead Packages in pockets of a tray that are arranged in a grid. 8. The method of claim 7 wherein said electrically connecting a conductive strip to the plated lead portions of the plurality of Flat No-Lead Packages comprises closing a conductive lid against portions of the Flat No-Lead Packages extending from the pockets. 9. The method of claim 8 further comprising lifting the conductive lid after the lead surfaces exposed on lateral side surfaces of the Flat No-Lead Packages are plated. 10. The method of claim 8 further comprising removing the Flat No-Lead Packages from the pockets of the tray. 11. The method of claim 1:
wherein said providing comprises providing a plurality of Quad Flat No-Lead Packages having severed, unplated lead surfaces exposed on lateral faces thereof and having plated lead surfaces on bottom faces thereof; and wherein said batch electroplating comprises batch electroplating the severed unplated lead surfaces of said plurality of Quad Flat No-Lead Packages. 12. A method of making Flat No-Lead Packages comprising:
providing a molded leadframe assembly comprising a plurality of plated leadframes and a plurality of dies mounted on corresponding die pads of the plated leadframes, the dies being wire bonded to leads of the plated leadframes; singulating the plated molded leadframe assembly into a plurality of Flat No-Lead Packages having plated lead surface portions exposed at a bottom faces thereof and unplated severed lead surfaces exposed at lateral faces thereof; electrically connecting a conductive strip to the plated lead portions of the plurality of Flat No-Lead Packages; placing the Flat No-Lead Packages and the connected conductor strip in an electroplating bath; and passing an electrical current through the conductor strip. 13. The method of claim 12:
wherein said singulating comprises singulating the plated molded leadframe assembly into a plurality of Quad Flat No-Lead Packages having plated lead surface portions exposed at a bottom surface thereof and unplated severed lead surfaces exposed at sidewall portions thereof; wherein said electrically connecting comprises electrically connecting a conductive strip to the plated lead portions of the plurality of Quad Flat No-Lead Packages; and wherein said placing comprises placing the Quad Flat No-Lead Packages and the connected conductor strip in an electroplating bath. 14. An assembly for electroplating a plurality of severed lead surfaces that are exposed on sidewall portions of a plurality of Flat No-Lead Packages comprising:
an electroplating bath; and a tray apparatus immersable in said bath comprising a tray bottom plate with a plurality of pockets adapted to support said Flat No-Lead Packages therein and a tray cover plate adapted to make engaging contact with plated leadframe surfaces of Flat No-Lead Packages mounted in said pockets of said tray bottom plate. 15. The assembly of claim 14 wherein said tray apparatus comprises a tray bottom plate with a plurality of pockets adapted to support said Flat No-Lead Packages therein and a tray cover plate adapted to make engaging contact with plated leadframe surfaces of Flat No-Lead Packages mounted in said pockets of said tray bottom plate. 16. The assembly of claim 14 wherein said tray bottom plate is an electrically nonconductive plate. 17. The assembly of claim 14 wherein said tray cover plate is an electrically conductive plate. 18. The assembly of claim 14 further comprising a current source with an electrode connectable to said tray assembly for producing an electrical current through said Flat No-Lead Packages. 19. A Flat No-Lead Package comprising:
a block of mold compound having a bottom face and a plurality of lateral side faces; and a plurality of leads exposed on said bottom face; said plurality of leads having severed electroplated end faces exposed on at least one of said plurality of lateral side faces of said block. 20. The Flat No-Lead package of claim 15 wherein said No-Lead Package is a Quad Flat No-Lead Package. | A method of making Flat No-Lead Packages with plated lead surfaces exposed on lateral faces thereof. The method includes providing a plurality of Flat No-Lead Packages having severed, unplated lead surfaces exposed on lateral faces thereof and having plated lead surfaces exposed on bottom faces thereof. The method further includes batch electroplating the severed unplated lead surfaces of the plurality of Flat No-Lead Packages.1. A method of making Flat No-Lead Packages with plated lead surfaces exposed on lateral sidewall surfaces of said Flat No-Lead Packages comprising:
providing a plurality of Flat No-Lead Packages having severed, unplated lead surfaces exposed on lateral faces thereof and having plated lead surfaces exposed on bottom faces thereof; and batch electroplating the severed unplated lead surfaces of the plurality of Flat No-Lead Packages. 2. The method of claim 1 wherein said electroplating the severed unplated lead surfaces comprises:
electrically connecting a conductive strip to the plated lead portions of the plurality of Flat No-Lead Packages;
placing the Flat No-Lead Packages and the connected conductor strip in an electroplating bath; and
passing an electrical current through the conductor strip and the electroplating bath. 3. The method of claim 1 wherein said providing a plurality of Flat No-Lead Packages comprises providing a molded leadframe assembly having a plurality of integrally connected leadframes and a plurality of dies mounted on corresponding die pad portions of the plurality of integrally connected leadframes the dies being wire bonded to lead portions of the leadframes. 4. The method of claim 2 wherein said providing a plurality of Flat No-Lead Packages comprises plating exposed lead portions of the plurality of leadframes in the molded leadframe assembly. 5. The method of claim 4 wherein said providing a plurality of Flat No-Lead Packages comprises singulating the plated molded leadframe assembly into a plurality of Flat No-Lead Packages having plated lead surfaces exposed at a bottom surface thereof and severed and unplated lead surfaces exposed at sidewall portions thereof. 6. The method of claim 4 further comprising arranging the plurality of Flat No-Lead Packages in a grid. 7. The method of claim 6 wherein arranging the plurality of Flat No-Lead Packages in a grid comprises placing said plurality of Flat No-Lead Packages in pockets of a tray that are arranged in a grid. 8. The method of claim 7 wherein said electrically connecting a conductive strip to the plated lead portions of the plurality of Flat No-Lead Packages comprises closing a conductive lid against portions of the Flat No-Lead Packages extending from the pockets. 9. The method of claim 8 further comprising lifting the conductive lid after the lead surfaces exposed on lateral side surfaces of the Flat No-Lead Packages are plated. 10. The method of claim 8 further comprising removing the Flat No-Lead Packages from the pockets of the tray. 11. The method of claim 1:
wherein said providing comprises providing a plurality of Quad Flat No-Lead Packages having severed, unplated lead surfaces exposed on lateral faces thereof and having plated lead surfaces on bottom faces thereof; and wherein said batch electroplating comprises batch electroplating the severed unplated lead surfaces of said plurality of Quad Flat No-Lead Packages. 12. A method of making Flat No-Lead Packages comprising:
providing a molded leadframe assembly comprising a plurality of plated leadframes and a plurality of dies mounted on corresponding die pads of the plated leadframes, the dies being wire bonded to leads of the plated leadframes; singulating the plated molded leadframe assembly into a plurality of Flat No-Lead Packages having plated lead surface portions exposed at a bottom faces thereof and unplated severed lead surfaces exposed at lateral faces thereof; electrically connecting a conductive strip to the plated lead portions of the plurality of Flat No-Lead Packages; placing the Flat No-Lead Packages and the connected conductor strip in an electroplating bath; and passing an electrical current through the conductor strip. 13. The method of claim 12:
wherein said singulating comprises singulating the plated molded leadframe assembly into a plurality of Quad Flat No-Lead Packages having plated lead surface portions exposed at a bottom surface thereof and unplated severed lead surfaces exposed at sidewall portions thereof; wherein said electrically connecting comprises electrically connecting a conductive strip to the plated lead portions of the plurality of Quad Flat No-Lead Packages; and wherein said placing comprises placing the Quad Flat No-Lead Packages and the connected conductor strip in an electroplating bath. 14. An assembly for electroplating a plurality of severed lead surfaces that are exposed on sidewall portions of a plurality of Flat No-Lead Packages comprising:
an electroplating bath; and a tray apparatus immersable in said bath comprising a tray bottom plate with a plurality of pockets adapted to support said Flat No-Lead Packages therein and a tray cover plate adapted to make engaging contact with plated leadframe surfaces of Flat No-Lead Packages mounted in said pockets of said tray bottom plate. 15. The assembly of claim 14 wherein said tray apparatus comprises a tray bottom plate with a plurality of pockets adapted to support said Flat No-Lead Packages therein and a tray cover plate adapted to make engaging contact with plated leadframe surfaces of Flat No-Lead Packages mounted in said pockets of said tray bottom plate. 16. The assembly of claim 14 wherein said tray bottom plate is an electrically nonconductive plate. 17. The assembly of claim 14 wherein said tray cover plate is an electrically conductive plate. 18. The assembly of claim 14 further comprising a current source with an electrode connectable to said tray assembly for producing an electrical current through said Flat No-Lead Packages. 19. A Flat No-Lead Package comprising:
a block of mold compound having a bottom face and a plurality of lateral side faces; and a plurality of leads exposed on said bottom face; said plurality of leads having severed electroplated end faces exposed on at least one of said plurality of lateral side faces of said block. 20. The Flat No-Lead package of claim 15 wherein said No-Lead Package is a Quad Flat No-Lead Package. | 2,800 |
11,425 | 11,425 | 15,221,478 | 2,853 | In an example, a printer ink dryer unit comprises at least one ultraviolet light source to dry a printer ink layer by causing evaporation of a solvent fluid therefrom. | 1. A printer ink dryer unit comprising at least one ultraviolet light source to dry a printer ink layer by causing evaporation of a solvent fluid therefrom. 2. A printer ink dryer unit according to claim 1 to cause evaporation of solvent fluid from a printer ink comprising at least one colorant, in which the ultraviolet light emitted from the light source is associated with a higher colorant absorption efficiency than solvent absorption efficiency. 3. A printer ink dryer unit according to claim 1 in which the light source comprises an array of ultraviolet light emitting diodes. 4. A printer ink dryer unit according to claim 1 to cause evaporation of solvent from a printer ink comprising at least one colorant, wherein heating of the solvent fluid is substantially due to heat transfer from the colorant. 5. A printer ink dryer unit according to claim 1 in which the light source has a bandwidth of less than 30 nm. 6. A method comprising irradiating a substrate bearing a solvent-based printing substance comprising a colorant with radiation to cause evaporation of solvent fluid therefrom, wherein the waveband of radiation is such that heating of the solvent fluid is substantially due to heat transfer from the colorant. 7. A method according to claim 6 comprising irradiating the substrate with radiation having a radiation absorption efficiency of at least 70% for a colorant of the printing substance. 8. A method according to claim 6 comprising selecting or controlling the waveband or radiation according to the color of at least one colorant. 9. A method according to claim 6 comprising irradiating the printing substance with a waveband of radiation which is between 200 nm and 410 nm. 10. Print apparatus comprising a printing substance distribution unit and a dryer unit,
the printing substance distribution unit being to dispense a solvent-based printing substance comprising a colorant, and the dryer unit comprising at least one ultraviolet light source, the light source being to emit light in a portion of the electromagnetic spectrum absorbed by the colorant, such that evaporation of solvent fluid from the solvent-based printing substance is caused by heat transfer from the colorant. 11. Print apparatus according to claim 10 which comprises an inkjet print apparatus. 12. Print apparatus according to claim 10 in which the printing substance distribution unit is to dispense a plurality printing substances, the printing substances comprising different colors. 13. Print apparatus according to claim 12 in which the light source is to emit light in a portion of the electromagnetic spectrum which is absorbed by each of the colorants, such that the energy absorption efficiency of the colorants for the emitted light is within a range of 30%. 14. Print apparatus according to claim 10, in which the light source comprises at least one light emitting diode, the or each of the light emitting diode emitting radiation in a bandwidth from within the range 200-450 nm. 15. Print apparatus according to claim 10 in which the light source is to emit light in a portion of the electromagnetic spectrum which is absorbed by each of the colorant with a radiation absorption efficiency of at least 70%. | In an example, a printer ink dryer unit comprises at least one ultraviolet light source to dry a printer ink layer by causing evaporation of a solvent fluid therefrom.1. A printer ink dryer unit comprising at least one ultraviolet light source to dry a printer ink layer by causing evaporation of a solvent fluid therefrom. 2. A printer ink dryer unit according to claim 1 to cause evaporation of solvent fluid from a printer ink comprising at least one colorant, in which the ultraviolet light emitted from the light source is associated with a higher colorant absorption efficiency than solvent absorption efficiency. 3. A printer ink dryer unit according to claim 1 in which the light source comprises an array of ultraviolet light emitting diodes. 4. A printer ink dryer unit according to claim 1 to cause evaporation of solvent from a printer ink comprising at least one colorant, wherein heating of the solvent fluid is substantially due to heat transfer from the colorant. 5. A printer ink dryer unit according to claim 1 in which the light source has a bandwidth of less than 30 nm. 6. A method comprising irradiating a substrate bearing a solvent-based printing substance comprising a colorant with radiation to cause evaporation of solvent fluid therefrom, wherein the waveband of radiation is such that heating of the solvent fluid is substantially due to heat transfer from the colorant. 7. A method according to claim 6 comprising irradiating the substrate with radiation having a radiation absorption efficiency of at least 70% for a colorant of the printing substance. 8. A method according to claim 6 comprising selecting or controlling the waveband or radiation according to the color of at least one colorant. 9. A method according to claim 6 comprising irradiating the printing substance with a waveband of radiation which is between 200 nm and 410 nm. 10. Print apparatus comprising a printing substance distribution unit and a dryer unit,
the printing substance distribution unit being to dispense a solvent-based printing substance comprising a colorant, and the dryer unit comprising at least one ultraviolet light source, the light source being to emit light in a portion of the electromagnetic spectrum absorbed by the colorant, such that evaporation of solvent fluid from the solvent-based printing substance is caused by heat transfer from the colorant. 11. Print apparatus according to claim 10 which comprises an inkjet print apparatus. 12. Print apparatus according to claim 10 in which the printing substance distribution unit is to dispense a plurality printing substances, the printing substances comprising different colors. 13. Print apparatus according to claim 12 in which the light source is to emit light in a portion of the electromagnetic spectrum which is absorbed by each of the colorants, such that the energy absorption efficiency of the colorants for the emitted light is within a range of 30%. 14. Print apparatus according to claim 10, in which the light source comprises at least one light emitting diode, the or each of the light emitting diode emitting radiation in a bandwidth from within the range 200-450 nm. 15. Print apparatus according to claim 10 in which the light source is to emit light in a portion of the electromagnetic spectrum which is absorbed by each of the colorant with a radiation absorption efficiency of at least 70%. | 2,800 |
11,426 | 11,426 | 15,151,159 | 2,868 | A handler for holding an electronic device during high voltage testing includes conductive lead guides for shorting leads on one side of the isolator together and connectors connecting the lead guides to conductors. | 1. A handler for holding an electronic device during high voltage testing, the handler comprising:
conductive lead guides, each lead guide for shorting leads on one side of the isolator together; and a plurality of connectors connecting the lead guides to conductors. 2. The handler of claim 1, further comprising:
an insulator, located between the lead guides. 3. The handler of claim 2, where the insulator is made of plastic. 4. The handler of claim 1, where the connectors are spring-loaded test pins. 5. The handler of claim 1, where high voltage is coupled from the conductors through the connectors to the lead guides. 6. The handler of claim 1, where the connectors are arranged into sets, each set contacting one lead guide. 7. The handler of claim 6, further comprising:
an insulator, located between sets of the connectors. 8. The handler of claim 7, where the insulator is made of plastic. 9. The handler of claim 6, where each set of connectors is mounted onto a conductor. 10. The handler of claim 9, where corners of the conductors are rounded. 11. The handler of claim 1, where the lead guides are made of metal. 12. The handler of claim 11, where the lead guides are made of copper. 13. The handler of claim 1 where corners of the lead guides are rounded. 14. A method of high-voltage testing an electronic device, comprising:
pressing, by a handler, a conductive lead guide against one side of leads on the electronic device; pressing, by the handler, the lead guide against connectors; and applying, by the handler, a high voltage to the connectors. 15. The method of claim 14, further comprising:
locating, by the handler, an insulator between the lead guides. 16. The method of claim 14, further comprising:
locating, by the handler, an insulator between sets of the connectors. 17. A method of fabricating a handler for holding an electronic device during high voltage testing, comprising:
mounting lead guides in a position to contact leads on the isolator; and mounting connectors in a position to contact the lead guides. 18. The method of claim 17, further comprising:
mounting an insulator so that it is located between the lead guides. 19. The method of claim 17, further comprising:
mounting an insulator so that it is located between sets of the conductors. | A handler for holding an electronic device during high voltage testing includes conductive lead guides for shorting leads on one side of the isolator together and connectors connecting the lead guides to conductors.1. A handler for holding an electronic device during high voltage testing, the handler comprising:
conductive lead guides, each lead guide for shorting leads on one side of the isolator together; and a plurality of connectors connecting the lead guides to conductors. 2. The handler of claim 1, further comprising:
an insulator, located between the lead guides. 3. The handler of claim 2, where the insulator is made of plastic. 4. The handler of claim 1, where the connectors are spring-loaded test pins. 5. The handler of claim 1, where high voltage is coupled from the conductors through the connectors to the lead guides. 6. The handler of claim 1, where the connectors are arranged into sets, each set contacting one lead guide. 7. The handler of claim 6, further comprising:
an insulator, located between sets of the connectors. 8. The handler of claim 7, where the insulator is made of plastic. 9. The handler of claim 6, where each set of connectors is mounted onto a conductor. 10. The handler of claim 9, where corners of the conductors are rounded. 11. The handler of claim 1, where the lead guides are made of metal. 12. The handler of claim 11, where the lead guides are made of copper. 13. The handler of claim 1 where corners of the lead guides are rounded. 14. A method of high-voltage testing an electronic device, comprising:
pressing, by a handler, a conductive lead guide against one side of leads on the electronic device; pressing, by the handler, the lead guide against connectors; and applying, by the handler, a high voltage to the connectors. 15. The method of claim 14, further comprising:
locating, by the handler, an insulator between the lead guides. 16. The method of claim 14, further comprising:
locating, by the handler, an insulator between sets of the connectors. 17. A method of fabricating a handler for holding an electronic device during high voltage testing, comprising:
mounting lead guides in a position to contact leads on the isolator; and mounting connectors in a position to contact the lead guides. 18. The method of claim 17, further comprising:
mounting an insulator so that it is located between the lead guides. 19. The method of claim 17, further comprising:
mounting an insulator so that it is located between sets of the conductors. | 2,800 |
11,427 | 11,427 | 14,812,540 | 2,847 | A wire harness includes at least one of electrical pathways. The electrical pathway includes a first electrical pathway, a second electrical pathway and an electrical pathway connecting part that connects the first electrical pathway and the second electrical pathway. The first electrical pathway has a flexure resistance that is higher than that of the second electrical pathway. | 1. A wire harness comprising at least one of electrical pathways, wherein
the electrical pathway includes:
a first electrical pathway;
a second electrical pathway; and
an electrical pathway connecting part that connects the first electrical pathway and the second electrical pathway, and
the first electrical pathway has a flexure resistance that is higher than that of the second electrical pathway. 2. The wire harness according to claim 1, wherein
the first electrical pathway is disposed between an external connecting portion which is disposed at a harness terminal and performs connection with an external electrical connecting counterpart, and a fixing member, among a plurality of fixing members which are provided to attach and fix the wire harness to a fixing target, that is nearest to the external connecting portion. 3. The wire harness according to claim 2, wherein
the fixing member that is nearest to the external connecting portion includes the electrical pathway connecting part. 4. The wire harness according to claim 1, wherein
the electrical pathway connecting part not only becomes the connecting portion where the first electrical pathway and the second electrical pathway are connected, but also becomes a branched portion where a third electrical pathway is branched from the electrical pathways. 5. The wire harness according to claim 1, wherein
the electrical pathway is a high voltage electrical pathway, is wired under a vehicle floor, and is electrically connected to an apparatus from which vibration is transmitted to the wire harness. | A wire harness includes at least one of electrical pathways. The electrical pathway includes a first electrical pathway, a second electrical pathway and an electrical pathway connecting part that connects the first electrical pathway and the second electrical pathway. The first electrical pathway has a flexure resistance that is higher than that of the second electrical pathway.1. A wire harness comprising at least one of electrical pathways, wherein
the electrical pathway includes:
a first electrical pathway;
a second electrical pathway; and
an electrical pathway connecting part that connects the first electrical pathway and the second electrical pathway, and
the first electrical pathway has a flexure resistance that is higher than that of the second electrical pathway. 2. The wire harness according to claim 1, wherein
the first electrical pathway is disposed between an external connecting portion which is disposed at a harness terminal and performs connection with an external electrical connecting counterpart, and a fixing member, among a plurality of fixing members which are provided to attach and fix the wire harness to a fixing target, that is nearest to the external connecting portion. 3. The wire harness according to claim 2, wherein
the fixing member that is nearest to the external connecting portion includes the electrical pathway connecting part. 4. The wire harness according to claim 1, wherein
the electrical pathway connecting part not only becomes the connecting portion where the first electrical pathway and the second electrical pathway are connected, but also becomes a branched portion where a third electrical pathway is branched from the electrical pathways. 5. The wire harness according to claim 1, wherein
the electrical pathway is a high voltage electrical pathway, is wired under a vehicle floor, and is electrically connected to an apparatus from which vibration is transmitted to the wire harness. | 2,800 |
11,428 | 11,428 | 15,314,831 | 2,824 | Example implementations relate to tracking memory unit errors on a memory device. In example implementations. a memory device may include on-die error-correcting code (ECC) and a plurality of error counters. One of the plurality of error counters may count errors, detected by the on-die ECC, in a memory unit on the memory device. A post package repair (PPR) may be initiated on the memory device in response to a determination that a value of the one of the plurality of error counters equals a threshold value. | 1. A memory module comprising:
a repair unit; and a memory device having on-die error-correcting code (ECC), wherein:
the memory device comprises a plurality of memory units and a plurality of error counters;
one of the plurality of error counters is to count errors, detected by the on-die ECC, in a first memory unit of the plurality of memory units;
a post package repair (PPR) is initiated on the memory device in response to a determination that a value of the one of the plurality of error counters equals a threshold value; and
during the PPR, data in the first memory unit is copied to the repair unit. 2. The memory module of claim 1, wherein each of the plurality of error counters is associated with a respective one of the plurality of memory units. 3. The memory module of claim 1, further comprising a register associated with the one of the plurality of error counters, wherein:
the first memory unit comprises a first plurality of memory elements; and the register is to store a first memory address that is common to the first plurality of memory elements. 4. The memory module of claim 3, wherein in response to a determination that the on-die ECC has not detected errors in the first memory unit for a predetermined length of time:
the one of the plurality of error counters is to count errors, detected by the on-die ECC, in a second memory unit of the plurality of memory units, the second memory unit comprising a second plurality of memory elements; and the register is to store a second memory address that is common to the second plurality of memory elements. 5. The memory module of claim 1, wherein:
any of the plurality of error counters is capable of counting errors, detected by the on-die ECC, in any of the plurality of memory units; and the plurality of error counters are assigned to respective ones of the plurality of memory units in a first-in, first-out (FIFO) manner. 6. A machine-readable storage medium encoded with instructions executable by a processor, the machine-readable storage medium comprising:
instructions to determine whether a value of one of a plurality of error counters on a memory device equals a threshold value, wherein:
the memory device comprises on-die error-correcting code (ECC);
the one of the plurality of error counters is associated with a memory unit on the memory device; and
the one of the plurality of error counters is to be incremented in response to an error being detected, by the on-die ECC, in the memory unit; and
instructions to initiate, in response to a determination that the value of the one of the plurality of error counters equals the threshold value, a post package repair (PPR), wherein the PPR comprises replacing the memory unit with a repair unit. 7. The machine-readable storage medium of claim 6, further comprising:
instructions to suspend functionality of the on-die ECC during the PPR; instructions to copy, during the PPR, data in the memory unit to a buffer on the memory device; instructions to flush, after the PPR has been completed, data in the buffer to a memory controller, wherein the memory controller is to generate non-erroneous data by correcting erroneous data received from the buffer; instructions to write the non-erroneous data to the repair unit; and instructions to enable, in response to a determination that the write to the repair unit has been completed, functionality of the on-die ECC. 8. The machine-readable storage medium of claim 6, further comprising:
instructions to write, during a precharge cycle that is executed in response to a precharge command received, during the PPR, with a read command directed at the memory unit, data to the repair unit instead of writing data back to the memory unit; instructions to use the on-die ECC to correct, during the precharge cycle, errors in the memory unit; and instructions to transmit data, that the on-die ECC is unable to correct, to a memory controller. 9. The machine-readable storage medium of claim 6, further comprising instructions to write, in response to a write command that is directed at the memory unit and issued during the PPR, data associated with the write command to the repair unit. 10. The machine-readable storage medium of claim 6, further comprising:
instructions to detect, during the PPR, erroneous data that is read from the memory unit; instructions to generate non-erroneous data by correcting the erroneous data; and instructions to write the non-erroneous data to the repair unit. 11. The machine-readable storage medium of claim 6, further comprising instructions to receive a PPR status indicator from the memory device, wherein the PPR is initiated if the received PPR status indicator indicates PPR availability on the memory device. 12. A method comprising:
incrementing, in response to detection of an error in one of a plurality of memory units on a memory device, an error counter on the memory device, wherein:
the error is detected by on-die error-correcting code (ECC) on the memory device; and
the error counter is associated with the one of the plurality of memory units;
performing, in response to a determination that a value of the error counter equals a threshold value, a post package repair (PPR) on the memory device; and copying, during the PPR, data in the one of the plurality of memory units to a repair unit. 13. The method of claim 12, wherein the copying comprises writing, during a precharge cycle that is executed in response to a precharge command received, during the PPR, with a read command directed at the one of the plurality of memory units, data to the repair unit instead of writing data back to the one of the plurality of memory units. 14. The method of claim 13, further comprising:
using the on-die ECC to correct, during the precharge cycle, errors in the one of the plurality of memory units; and transmitting data, that the on-die ECC is unable to correct, to a memory controller. 15. The method of claim 12, further comprising writing, during the PPR, data associated with a write command, that is issued during the PPR and directed to the one of the plurality of memory units, to the repair unit. | Example implementations relate to tracking memory unit errors on a memory device. In example implementations. a memory device may include on-die error-correcting code (ECC) and a plurality of error counters. One of the plurality of error counters may count errors, detected by the on-die ECC, in a memory unit on the memory device. A post package repair (PPR) may be initiated on the memory device in response to a determination that a value of the one of the plurality of error counters equals a threshold value.1. A memory module comprising:
a repair unit; and a memory device having on-die error-correcting code (ECC), wherein:
the memory device comprises a plurality of memory units and a plurality of error counters;
one of the plurality of error counters is to count errors, detected by the on-die ECC, in a first memory unit of the plurality of memory units;
a post package repair (PPR) is initiated on the memory device in response to a determination that a value of the one of the plurality of error counters equals a threshold value; and
during the PPR, data in the first memory unit is copied to the repair unit. 2. The memory module of claim 1, wherein each of the plurality of error counters is associated with a respective one of the plurality of memory units. 3. The memory module of claim 1, further comprising a register associated with the one of the plurality of error counters, wherein:
the first memory unit comprises a first plurality of memory elements; and the register is to store a first memory address that is common to the first plurality of memory elements. 4. The memory module of claim 3, wherein in response to a determination that the on-die ECC has not detected errors in the first memory unit for a predetermined length of time:
the one of the plurality of error counters is to count errors, detected by the on-die ECC, in a second memory unit of the plurality of memory units, the second memory unit comprising a second plurality of memory elements; and the register is to store a second memory address that is common to the second plurality of memory elements. 5. The memory module of claim 1, wherein:
any of the plurality of error counters is capable of counting errors, detected by the on-die ECC, in any of the plurality of memory units; and the plurality of error counters are assigned to respective ones of the plurality of memory units in a first-in, first-out (FIFO) manner. 6. A machine-readable storage medium encoded with instructions executable by a processor, the machine-readable storage medium comprising:
instructions to determine whether a value of one of a plurality of error counters on a memory device equals a threshold value, wherein:
the memory device comprises on-die error-correcting code (ECC);
the one of the plurality of error counters is associated with a memory unit on the memory device; and
the one of the plurality of error counters is to be incremented in response to an error being detected, by the on-die ECC, in the memory unit; and
instructions to initiate, in response to a determination that the value of the one of the plurality of error counters equals the threshold value, a post package repair (PPR), wherein the PPR comprises replacing the memory unit with a repair unit. 7. The machine-readable storage medium of claim 6, further comprising:
instructions to suspend functionality of the on-die ECC during the PPR; instructions to copy, during the PPR, data in the memory unit to a buffer on the memory device; instructions to flush, after the PPR has been completed, data in the buffer to a memory controller, wherein the memory controller is to generate non-erroneous data by correcting erroneous data received from the buffer; instructions to write the non-erroneous data to the repair unit; and instructions to enable, in response to a determination that the write to the repair unit has been completed, functionality of the on-die ECC. 8. The machine-readable storage medium of claim 6, further comprising:
instructions to write, during a precharge cycle that is executed in response to a precharge command received, during the PPR, with a read command directed at the memory unit, data to the repair unit instead of writing data back to the memory unit; instructions to use the on-die ECC to correct, during the precharge cycle, errors in the memory unit; and instructions to transmit data, that the on-die ECC is unable to correct, to a memory controller. 9. The machine-readable storage medium of claim 6, further comprising instructions to write, in response to a write command that is directed at the memory unit and issued during the PPR, data associated with the write command to the repair unit. 10. The machine-readable storage medium of claim 6, further comprising:
instructions to detect, during the PPR, erroneous data that is read from the memory unit; instructions to generate non-erroneous data by correcting the erroneous data; and instructions to write the non-erroneous data to the repair unit. 11. The machine-readable storage medium of claim 6, further comprising instructions to receive a PPR status indicator from the memory device, wherein the PPR is initiated if the received PPR status indicator indicates PPR availability on the memory device. 12. A method comprising:
incrementing, in response to detection of an error in one of a plurality of memory units on a memory device, an error counter on the memory device, wherein:
the error is detected by on-die error-correcting code (ECC) on the memory device; and
the error counter is associated with the one of the plurality of memory units;
performing, in response to a determination that a value of the error counter equals a threshold value, a post package repair (PPR) on the memory device; and copying, during the PPR, data in the one of the plurality of memory units to a repair unit. 13. The method of claim 12, wherein the copying comprises writing, during a precharge cycle that is executed in response to a precharge command received, during the PPR, with a read command directed at the one of the plurality of memory units, data to the repair unit instead of writing data back to the one of the plurality of memory units. 14. The method of claim 13, further comprising:
using the on-die ECC to correct, during the precharge cycle, errors in the one of the plurality of memory units; and transmitting data, that the on-die ECC is unable to correct, to a memory controller. 15. The method of claim 12, further comprising writing, during the PPR, data associated with a write command, that is issued during the PPR and directed to the one of the plurality of memory units, to the repair unit. | 2,800 |
11,429 | 11,429 | 15,028,736 | 2,884 | There is a method and a corresponding system for optimizing X-ray imaging during a mammographic examination. In order to provide an optimization of X-ray imaging in a first step (SOI) a breast ( 7 ) is compressed between a support plate ( 5 ) and a compression plate ( 3 ). In a next step (S 03 ), a force-height curve ( 13 ) is acquired during compression. Then, in a further step (S 05 ) an elasticity value of the breast ( 7 ) is determined radiation-free based on the force-height curve ( 13 ). In a further step (S 07 ), a parameter of an X-ray imaging system is optimized based on the determined glandularity (g). As the glandularity (g) of a breast may influence the attenuation of X-rays, the personalized setting of the parameters of the X-ray imaging system may greatly enhance the image quality. | 1. A method for optimizing X-ray imaging during a mammographic examination, comprising the following steps:
compressing a breast between a support plate and a compression plate; acquiring a force-height curve during compressing; radiation-free determining of an elasticity value of the breast based on the force-height curve; and optimizing a parameter of an X-ray imaging system based on the determined elasticity value. 2. The method according to claim 1,
wherein the optimized parameter is at least one parameter of the following group of parameters: a tube anode voltage of an X-ray source, a tube current of the X-ray source, an X-ray pre-filter property, an X-ray exposure time and an X-ray detector energy threshold value. 3. The method according to claim 1,
wherein determining the elasticity value comprises: determining a breast contact area between the breast and the compression plate or the support plate; and determining a stiffness of the breast based on the force-height curve. 4. The method according to claim 3,
wherein determining the stiffness of the breast is implemented at the end of the compression process. 5. The method according to claim 1,
wherein determining the elasticity value comprises: comparing the acquired force-height curve with a database of measured values. 6. The method according to claim 5,
wherein the comparison implements at least one of the following features: a look-up-table and as a curve fit. 7. The method according to claim 1,
wherein the elasticity value is determined automatically. 8. The method according to claim 1, further comprising
providing a first output signal representative of the elasticity value. 9. The method according to claim 8,
wherein the first output signal is an optical and/or an acoustical signal. 10. The method according to claim 1, further comprising
determining a compression force limit based on at least one of the following quantities: the breast contact area, the stiffness of the breast and the glandularity of the breast; providing a second output signal representative of the relation between the quantity and the compression force limit; wherein the second output signal is provided when the compression force limit is reached during the mammographic examination. 11. A system for optimizing X-ray imaging during a mammographic examination, comprising
an X-ray imaging system for acquiring radiographic images of the breast; a support plate for supporting a breast while radiographic images are obtained; a compression plate for compressing the breast between the support plate and the compression plate while the radiographic images are obtained; a monitoring unit for acquiring a force-height curve during compressing; a processing unit for radiation-free determining of an elasticity value of the breast based on the force-height curve; wherein the processing unit is adapted for optimizing a parameter of the X-ray imaging system based on the determined elasticity value. 12. The system according to claim 11,
wherein the optimized parameter is at least one parameter of the following group of parameters: a tube anode voltage of an X-ray source, a tube current of the X-ray source, an X-ray pre-filter, an X-ray exposure time and an X-ray detector energy threshold value. 13. A computer program element for controlling a system, which, when being executed by a processing unit, is adapted to perform the method steps of claim 1. 14. A computer readable medium having stored the program element of claim 13. | There is a method and a corresponding system for optimizing X-ray imaging during a mammographic examination. In order to provide an optimization of X-ray imaging in a first step (SOI) a breast ( 7 ) is compressed between a support plate ( 5 ) and a compression plate ( 3 ). In a next step (S 03 ), a force-height curve ( 13 ) is acquired during compression. Then, in a further step (S 05 ) an elasticity value of the breast ( 7 ) is determined radiation-free based on the force-height curve ( 13 ). In a further step (S 07 ), a parameter of an X-ray imaging system is optimized based on the determined glandularity (g). As the glandularity (g) of a breast may influence the attenuation of X-rays, the personalized setting of the parameters of the X-ray imaging system may greatly enhance the image quality.1. A method for optimizing X-ray imaging during a mammographic examination, comprising the following steps:
compressing a breast between a support plate and a compression plate; acquiring a force-height curve during compressing; radiation-free determining of an elasticity value of the breast based on the force-height curve; and optimizing a parameter of an X-ray imaging system based on the determined elasticity value. 2. The method according to claim 1,
wherein the optimized parameter is at least one parameter of the following group of parameters: a tube anode voltage of an X-ray source, a tube current of the X-ray source, an X-ray pre-filter property, an X-ray exposure time and an X-ray detector energy threshold value. 3. The method according to claim 1,
wherein determining the elasticity value comprises: determining a breast contact area between the breast and the compression plate or the support plate; and determining a stiffness of the breast based on the force-height curve. 4. The method according to claim 3,
wherein determining the stiffness of the breast is implemented at the end of the compression process. 5. The method according to claim 1,
wherein determining the elasticity value comprises: comparing the acquired force-height curve with a database of measured values. 6. The method according to claim 5,
wherein the comparison implements at least one of the following features: a look-up-table and as a curve fit. 7. The method according to claim 1,
wherein the elasticity value is determined automatically. 8. The method according to claim 1, further comprising
providing a first output signal representative of the elasticity value. 9. The method according to claim 8,
wherein the first output signal is an optical and/or an acoustical signal. 10. The method according to claim 1, further comprising
determining a compression force limit based on at least one of the following quantities: the breast contact area, the stiffness of the breast and the glandularity of the breast; providing a second output signal representative of the relation between the quantity and the compression force limit; wherein the second output signal is provided when the compression force limit is reached during the mammographic examination. 11. A system for optimizing X-ray imaging during a mammographic examination, comprising
an X-ray imaging system for acquiring radiographic images of the breast; a support plate for supporting a breast while radiographic images are obtained; a compression plate for compressing the breast between the support plate and the compression plate while the radiographic images are obtained; a monitoring unit for acquiring a force-height curve during compressing; a processing unit for radiation-free determining of an elasticity value of the breast based on the force-height curve; wherein the processing unit is adapted for optimizing a parameter of the X-ray imaging system based on the determined elasticity value. 12. The system according to claim 11,
wherein the optimized parameter is at least one parameter of the following group of parameters: a tube anode voltage of an X-ray source, a tube current of the X-ray source, an X-ray pre-filter, an X-ray exposure time and an X-ray detector energy threshold value. 13. A computer program element for controlling a system, which, when being executed by a processing unit, is adapted to perform the method steps of claim 1. 14. A computer readable medium having stored the program element of claim 13. | 2,800 |
11,430 | 11,430 | 14,566,825 | 2,825 | A method for operating a Coriolis mass flowmeter in which the interferences when calculating the medium parameters is considered by the eigenfrequency (f 01 ) of the oscillation of the measuring tube being determined in the first and second natural modes during operation of the Coriolis mass flowmeter, and at least one medium parameter ({dot over (m)}) is calculated with the aid of the oscillation measuring variable (Δt) by means of a calculation rule representing a mathematic relation between the oscillation measuring variable (Δt), the medium parameter ({dot over (m)}) and the eigenfrequencies (f 01 , f 02 ) of the oscillations of the measuring tube in the first natural mode and the second natural mode, and the medium parameter ({dot over (m)}) being determined taking into consideration the current determined eigenfrequencies (f 01 , f 02 ) of the oscillations of the measuring tub in the first natural mode and the second natural mode as well as the oscillation measuring variable (Δt). | 1. Method for operating a Coriolis mass flowmeter having at least one electric setting device, at least one electric drive forming an oscillation generator, at least one measuring tube interacting with a medium and having at least one oscillation sensor, comprising the steps of:
using the electric setting device to provide an electric excitation signal for exciting the electric drive, using the electric drive to excite the measuring tube into oscillation in at least one first natural mode, detecting the excited oscillation of the measuring tube with the oscillation sensor as an oscillation measuring variable (x, {dot over (x)}, Δt) and calculating at least one medium parameter ({dot over (m)}) with the aid of the oscillation measuring variable (Δt) by means of a calculation rule, wherein a first eigenfrequency (f01) of the oscillation of the measuring tube is determined in the first natural mode during operation of the Coriolis mass flowmeter, wherein a second eigenfrequency (f02) of the oscillation of the measuring tube is determined in at least one second natural mode during operation of the Coriolis mass flowmeter, wherein the calculation rule represents a mathematic relation between the oscillation measuring variable (Δt), the medium parameter ({dot over (m)}) and the first and second eigenfrequencies (f01, f02) of the oscillations of the measuring tube in the first and second natural modes, and wherein the medium parameter ({dot over (m)}) is determined taking into consideration current determined eigenfrequencies (f01, f02) of the oscillations of the measuring tube in the first and second natural modes as well as the oscillation measuring variable (Δt). 2. Method according to claim 1, wherein at least one of the first eigenfrequency (f01) of the oscillation of the measuring tube is determined in the first natural mode and the second eigenfrequency (f02) of the oscillation of the measuring tube is determined in the second natural mode by specifically exciting the measuring tube in a phase-locked loop. 3. Method according to claim 2, wherein a phase shift between a driving force of the electric drive and a velocity response ({dot over (x)}) of the measuring tube detected via the oscillation sensor is regulated using a variation of the frequency of the excitation signal at a predetermined value. 4. Method according to claim 1, wherein the oscillation of the measuring tube is excited in the second natural mode by at least one of actively exciting the oscillation of the measuring tube in the first natural mode based on structural asymmetries and excitation tracking the eigenfrequency of the second natural mode via a phase-locked loop. 5. Method according to claim 1, wherein the calculation rule has a term for the eigenfrequencies (f01, f02) of the oscillations of the measuring tube in the first natural mode and the second natural mode as an integral correction function fIK. 6. Method according to claim 5, wherein the calculation rule has no further dependencies on the eigenfrequencies (f01, f02) of the oscillations of the measuring tube in the first natural mode and the second natural mode. 7. Method according to claim 5, wherein a term for the integral correction function fIK depending on the eigenfrequencies (f01, f02) of the oscillations of the measuring tube (5) in the first natural mode and the second natural mode has the following form
1
1
-
ω
01
2
ω
02
2
wherein ω01 is the circular eigenfrequency of the oscillation in the first natural mode and ω02 is the circular eigenfrequency of the oscillation in the second natural mode. 8. Method according to claim 5, wherein the integral correction function fIK is additionally dependent on spring stiffness c2 of the measuring tube in oscillation in the second natural mode. 9. Method according to claim 6, wherein an integral correction function fIK has the following form:
f
IK
(
T
,
Δ
T
,
P
,
σ
,
Δ
σ
,
…
)
=
K
·
1
1
-
ω
01
2
ω
02
2
·
1
c
2 10. Method according to claim 1, wherein the medium parameter ({dot over (m)}) pertaining to the medium, the oscillation measuring variable (Δt), the eigenfrequency (f01) of the oscillation of the measuring tube in the first natural mode and the eigenfrequency (f02) of the oscillation of the measuring tube in the second natural mode correlate to one another according to the following calculation rule:
Δ
t
≈
1
1
-
ω
01
2
ω
02
2
·
1
c
2
(
K
CN
·
m
.
+
K
V
)
=
f
IK
(
T
,
Δ
T
,
P
,
σ
,
Δ
σ
,
…
)
·
(
K
CN
·
m
.
+
K
V
)
wherein ω01 is the circular eigenfrequency of the oscillation in the first natural mode and ω02 is the circular eigenfrequency of the oscillation in the second natural mode. 11. Method according to claim 1, wherein at least one parameter of the calculation rule is determined at an initial point in time and an initial value obtained in this manner is compared to a current value of the at least one parameter that is determined at a later point in time and a signal is issued when a predetermined maximum deviation of the current parameter value from the initial value of the parameter is exceeded. 12. Method according to claim 11, wherein the parameter of the calculation rule is one of the value of the correction function (fIK), a zero point (N) of the Coriolis mass flowmeter, and a sensitivity (E) of the Coriolis mass flowmeter. | A method for operating a Coriolis mass flowmeter in which the interferences when calculating the medium parameters is considered by the eigenfrequency (f 01 ) of the oscillation of the measuring tube being determined in the first and second natural modes during operation of the Coriolis mass flowmeter, and at least one medium parameter ({dot over (m)}) is calculated with the aid of the oscillation measuring variable (Δt) by means of a calculation rule representing a mathematic relation between the oscillation measuring variable (Δt), the medium parameter ({dot over (m)}) and the eigenfrequencies (f 01 , f 02 ) of the oscillations of the measuring tube in the first natural mode and the second natural mode, and the medium parameter ({dot over (m)}) being determined taking into consideration the current determined eigenfrequencies (f 01 , f 02 ) of the oscillations of the measuring tub in the first natural mode and the second natural mode as well as the oscillation measuring variable (Δt).1. Method for operating a Coriolis mass flowmeter having at least one electric setting device, at least one electric drive forming an oscillation generator, at least one measuring tube interacting with a medium and having at least one oscillation sensor, comprising the steps of:
using the electric setting device to provide an electric excitation signal for exciting the electric drive, using the electric drive to excite the measuring tube into oscillation in at least one first natural mode, detecting the excited oscillation of the measuring tube with the oscillation sensor as an oscillation measuring variable (x, {dot over (x)}, Δt) and calculating at least one medium parameter ({dot over (m)}) with the aid of the oscillation measuring variable (Δt) by means of a calculation rule, wherein a first eigenfrequency (f01) of the oscillation of the measuring tube is determined in the first natural mode during operation of the Coriolis mass flowmeter, wherein a second eigenfrequency (f02) of the oscillation of the measuring tube is determined in at least one second natural mode during operation of the Coriolis mass flowmeter, wherein the calculation rule represents a mathematic relation between the oscillation measuring variable (Δt), the medium parameter ({dot over (m)}) and the first and second eigenfrequencies (f01, f02) of the oscillations of the measuring tube in the first and second natural modes, and wherein the medium parameter ({dot over (m)}) is determined taking into consideration current determined eigenfrequencies (f01, f02) of the oscillations of the measuring tube in the first and second natural modes as well as the oscillation measuring variable (Δt). 2. Method according to claim 1, wherein at least one of the first eigenfrequency (f01) of the oscillation of the measuring tube is determined in the first natural mode and the second eigenfrequency (f02) of the oscillation of the measuring tube is determined in the second natural mode by specifically exciting the measuring tube in a phase-locked loop. 3. Method according to claim 2, wherein a phase shift between a driving force of the electric drive and a velocity response ({dot over (x)}) of the measuring tube detected via the oscillation sensor is regulated using a variation of the frequency of the excitation signal at a predetermined value. 4. Method according to claim 1, wherein the oscillation of the measuring tube is excited in the second natural mode by at least one of actively exciting the oscillation of the measuring tube in the first natural mode based on structural asymmetries and excitation tracking the eigenfrequency of the second natural mode via a phase-locked loop. 5. Method according to claim 1, wherein the calculation rule has a term for the eigenfrequencies (f01, f02) of the oscillations of the measuring tube in the first natural mode and the second natural mode as an integral correction function fIK. 6. Method according to claim 5, wherein the calculation rule has no further dependencies on the eigenfrequencies (f01, f02) of the oscillations of the measuring tube in the first natural mode and the second natural mode. 7. Method according to claim 5, wherein a term for the integral correction function fIK depending on the eigenfrequencies (f01, f02) of the oscillations of the measuring tube (5) in the first natural mode and the second natural mode has the following form
1
1
-
ω
01
2
ω
02
2
wherein ω01 is the circular eigenfrequency of the oscillation in the first natural mode and ω02 is the circular eigenfrequency of the oscillation in the second natural mode. 8. Method according to claim 5, wherein the integral correction function fIK is additionally dependent on spring stiffness c2 of the measuring tube in oscillation in the second natural mode. 9. Method according to claim 6, wherein an integral correction function fIK has the following form:
f
IK
(
T
,
Δ
T
,
P
,
σ
,
Δ
σ
,
…
)
=
K
·
1
1
-
ω
01
2
ω
02
2
·
1
c
2 10. Method according to claim 1, wherein the medium parameter ({dot over (m)}) pertaining to the medium, the oscillation measuring variable (Δt), the eigenfrequency (f01) of the oscillation of the measuring tube in the first natural mode and the eigenfrequency (f02) of the oscillation of the measuring tube in the second natural mode correlate to one another according to the following calculation rule:
Δ
t
≈
1
1
-
ω
01
2
ω
02
2
·
1
c
2
(
K
CN
·
m
.
+
K
V
)
=
f
IK
(
T
,
Δ
T
,
P
,
σ
,
Δ
σ
,
…
)
·
(
K
CN
·
m
.
+
K
V
)
wherein ω01 is the circular eigenfrequency of the oscillation in the first natural mode and ω02 is the circular eigenfrequency of the oscillation in the second natural mode. 11. Method according to claim 1, wherein at least one parameter of the calculation rule is determined at an initial point in time and an initial value obtained in this manner is compared to a current value of the at least one parameter that is determined at a later point in time and a signal is issued when a predetermined maximum deviation of the current parameter value from the initial value of the parameter is exceeded. 12. Method according to claim 11, wherein the parameter of the calculation rule is one of the value of the correction function (fIK), a zero point (N) of the Coriolis mass flowmeter, and a sensitivity (E) of the Coriolis mass flowmeter. | 2,800 |
11,431 | 11,431 | 14,303,510 | 2,841 | The description relates to devices, such as computing devices that have hinged portions. One example can include a first portion and a second portion and a flexible display secured to the first and second portions. This example can also include a hinge assembly rotatably securing the first and second portions. The hinge assembly can be fixedly secured to the second portion and movably secured to the first portion such that a length of the hinge assembly can change when the first portion and second portion are rotated relative to one another. | 1. A computing device, comprising:
a first portion and a second portion; a flexible display secured to the first and second portions; and, a hinge assembly rotatably securing the first and second portions, the hinge assembly being fixedly secured to the second portion and movably secured to the first portion such that a length of the hinge assembly changes when the first portion and second portion are rotated relative to one another. 2. The computing device of claim 1, wherein the first portion comprises a housing containing electronic components, and wherein the second portion comprises another housing containing other electronic components. 3. The computing device of claim 1, wherein the hinge assembly comprises a radius hinge assembly. 4. The computing device of claim 1, wherein the hinge assembly is configured to allow 0 to 180 degrees of rotation of the first and second portions relative to one another. 5. The computing device of claim 1, wherein the hinge assembly provides progressively increased resistance as an angle between the first portion and the second portion increases. 6. The computing device of claim 1, wherein the hinge assembly further comprises a protuberance that is configured to move in a slot formed in the first portion. 7. The computing device of claim 6, wherein movement of the protuberance in the slot is controlled by the hinge assembly. 8. The computing device of claim 6, wherein movement of the protuberance in the slot is not controlled by the hinge assembly. 9. The computing device of claim 1, wherein the hinge assembly further comprises a slide and a first element of the slide is secured to the hinge assembly and a second element of the slide is secured to the first portion. 10. The computing device of claim 9, wherein the first element comprises a slide carrier and movement of the slide carrier is timed to movement of the first and second portions relative to one another. 11. The computing device of claim 10, wherein the hinge assembly comprises a radius hinge assembly that includes timed link elements and wherein the timed link elements drive the movement of the slide carrier. 12. The computing device of claim 1, wherein the hinge assembly maintains a minimum bend radius to protect the flexible display. 13. The computing device of claim 1, wherein the computing device is manifest as an e-reader, a laptop computer, a tablet computer, a smart phone computer, a home appliance, a component of an airline seat, or a component of a vehicle. 14. A computing device, comprising:
a flexible display secured to a first portion of the computing device and a second portion of the computing device; and, a radius hinge assembly rotatably securing the first and second portions of the computing device and configured to maintain a minimum bend radius of the flexible display when the first and second portions are rotated relative to one another. 15. The computing device of claim 14, wherein the flexible display covers an entire planar surface of the first portion and another planar surface of the second portion. 16. The computing device of claim 14, wherein the flexible display functions as a neutral axis when the first and second portions are rotated relative to one another. 17. The computing device of claim 16, wherein a dimension of the radius hinge assembly can change when the first and second portions are rotated relative to one another to decrease stress forces experienced by the flexible display. 18. A computing device, comprising:
a radius hinge assembly rotatably securing first and second rigid portions to allow transition from a deployed configuration to a storage configuration; and, a flexible display secured to an inside surface of the first rigid portion and an inside surface of the second rigid portion, and wherein the radius hinge assembly is configured to protect the flexible display from being crimped when the inside surfaces are brought together in the storage configuration. 19. The computing device of claim 18, wherein the radius hinge assembly is fixedly secured to the second rigid portion and movably secured to the first rigid portion. 20. The computing device of claim 18, wherein the deployed configuration orients the first rigid portion at about 180 degrees from the second rigid portion, and wherein the storage configuration orients the first rigid portion at about 0 degrees from the second rigid portion with the flexible display being positioned therebetween. | The description relates to devices, such as computing devices that have hinged portions. One example can include a first portion and a second portion and a flexible display secured to the first and second portions. This example can also include a hinge assembly rotatably securing the first and second portions. The hinge assembly can be fixedly secured to the second portion and movably secured to the first portion such that a length of the hinge assembly can change when the first portion and second portion are rotated relative to one another.1. A computing device, comprising:
a first portion and a second portion; a flexible display secured to the first and second portions; and, a hinge assembly rotatably securing the first and second portions, the hinge assembly being fixedly secured to the second portion and movably secured to the first portion such that a length of the hinge assembly changes when the first portion and second portion are rotated relative to one another. 2. The computing device of claim 1, wherein the first portion comprises a housing containing electronic components, and wherein the second portion comprises another housing containing other electronic components. 3. The computing device of claim 1, wherein the hinge assembly comprises a radius hinge assembly. 4. The computing device of claim 1, wherein the hinge assembly is configured to allow 0 to 180 degrees of rotation of the first and second portions relative to one another. 5. The computing device of claim 1, wherein the hinge assembly provides progressively increased resistance as an angle between the first portion and the second portion increases. 6. The computing device of claim 1, wherein the hinge assembly further comprises a protuberance that is configured to move in a slot formed in the first portion. 7. The computing device of claim 6, wherein movement of the protuberance in the slot is controlled by the hinge assembly. 8. The computing device of claim 6, wherein movement of the protuberance in the slot is not controlled by the hinge assembly. 9. The computing device of claim 1, wherein the hinge assembly further comprises a slide and a first element of the slide is secured to the hinge assembly and a second element of the slide is secured to the first portion. 10. The computing device of claim 9, wherein the first element comprises a slide carrier and movement of the slide carrier is timed to movement of the first and second portions relative to one another. 11. The computing device of claim 10, wherein the hinge assembly comprises a radius hinge assembly that includes timed link elements and wherein the timed link elements drive the movement of the slide carrier. 12. The computing device of claim 1, wherein the hinge assembly maintains a minimum bend radius to protect the flexible display. 13. The computing device of claim 1, wherein the computing device is manifest as an e-reader, a laptop computer, a tablet computer, a smart phone computer, a home appliance, a component of an airline seat, or a component of a vehicle. 14. A computing device, comprising:
a flexible display secured to a first portion of the computing device and a second portion of the computing device; and, a radius hinge assembly rotatably securing the first and second portions of the computing device and configured to maintain a minimum bend radius of the flexible display when the first and second portions are rotated relative to one another. 15. The computing device of claim 14, wherein the flexible display covers an entire planar surface of the first portion and another planar surface of the second portion. 16. The computing device of claim 14, wherein the flexible display functions as a neutral axis when the first and second portions are rotated relative to one another. 17. The computing device of claim 16, wherein a dimension of the radius hinge assembly can change when the first and second portions are rotated relative to one another to decrease stress forces experienced by the flexible display. 18. A computing device, comprising:
a radius hinge assembly rotatably securing first and second rigid portions to allow transition from a deployed configuration to a storage configuration; and, a flexible display secured to an inside surface of the first rigid portion and an inside surface of the second rigid portion, and wherein the radius hinge assembly is configured to protect the flexible display from being crimped when the inside surfaces are brought together in the storage configuration. 19. The computing device of claim 18, wherein the radius hinge assembly is fixedly secured to the second rigid portion and movably secured to the first rigid portion. 20. The computing device of claim 18, wherein the deployed configuration orients the first rigid portion at about 180 degrees from the second rigid portion, and wherein the storage configuration orients the first rigid portion at about 0 degrees from the second rigid portion with the flexible display being positioned therebetween. | 2,800 |
11,432 | 11,432 | 14,146,373 | 2,837 | Until now, the direct effect or the converse effect is used in piezoelectric devices to provide respectively a disturbance force in external objects via electric field or acoustic waves. The collective displacement of the internal polarized molecules of the piezoelectric materials can be used in innovative ways when the direct or the converse effect takes place. This attribute is associated when all particles which are part of macroscopic objects are widely coupled to each other via quantum entanglements and it can generate a distance induction force. Considering this, an induction force can be inducted in the external objects, thereby thrusting or pull them. | 1. A method for using piezoelectric devices to produce induction forces in other external objects comprising the step of:
generalized quantum coupling between internal polarized molecules of the piezoelectric devices and external particles or objects placed in a beam environment. 2. The method as claimed in claim 1, where the piezoelectric devices use a Direct or a Converse effect. | Until now, the direct effect or the converse effect is used in piezoelectric devices to provide respectively a disturbance force in external objects via electric field or acoustic waves. The collective displacement of the internal polarized molecules of the piezoelectric materials can be used in innovative ways when the direct or the converse effect takes place. This attribute is associated when all particles which are part of macroscopic objects are widely coupled to each other via quantum entanglements and it can generate a distance induction force. Considering this, an induction force can be inducted in the external objects, thereby thrusting or pull them.1. A method for using piezoelectric devices to produce induction forces in other external objects comprising the step of:
generalized quantum coupling between internal polarized molecules of the piezoelectric devices and external particles or objects placed in a beam environment. 2. The method as claimed in claim 1, where the piezoelectric devices use a Direct or a Converse effect. | 2,800 |
11,433 | 11,433 | 15,935,958 | 2,853 | Compatible acrylate ink sets include an acrylate ink composition having 30% or less by weight pigment, 10% or less dispersant, between 40% and 80% acrylate, 12% or less photoinitiator, a viscosity between 5×10 5 and 3×10 7 cps at 35° C., and a 60 second tack between 25 and 50 g-m at 35° C. | 1. An acrylate ink composition comprising:
a tetrafunctional polyester acrylate oligomer; a polyester acrylate oligomer that is different than the tetrafunctional polyester acrylate oligomer; a pigment; an optional dispersant; and an optional photoinitiator. 2. The ink composition of claim 1, further comprising:
at least one member of the group consisting of a propoxylated trimethololpropane triacrylate monomer and an ethoxylated trimethylolpropane triacrylate monomer. 3. The ink composition of claim 1, further comprising:
at least one member of the group consisting of a propoxylated trimethololpropane triacrylate monomer, an ethoxylated trimethylolpropane triacrylate monomer, and a monomer having a functionality greater than or equal to 4. 4. The ink composition of claim 1, wherein a viscosity of the ink composition is between 5×105 and 3×107 cps at 35° C. 5. The ink composition of claim 1, wherein a 60 second tack of the ink composition is between 25 and 50 g-m at 35° C. 6. The ink composition of claim 1, wherein the ink composition comprises between 40% and 50% by weight acrylate, based on a total weight of the ink composition;
30% or less by weight pigment, based on the total weight of the ink composition; 10% or less by weight dispersant, based on the total weight of the ink composition; and 12% or less by weight photoinitiator, based on the total weight of the ink composition. 7. The ink composition of claim 1, further comprising:
a stabilizer; and a rheology modifier; wherein the ink composition comprises: between 10% and 20% pigment; between 2% and 10% dispersant; between 40% and 50% acrylate; 10% or less photoinitiator; 0.4% or less stabilizer; between 1% and 5% rheology modifier; wherein a viscosity of the ink composition is between 8×105 and 2×107 cps at 35° C.; and wherein a 60 second tack of the ink composition is between 35 and 45 g-m at 35° C. 8. The ink composition of claim 1, further comprising:
a stabilizer; and a rheology modifier; wherein the ink composition comprises: between 12% and 18% pigment; between 4% and 8% dispersant; between 40% and 50% acrylate; between 5% and 10% less photoinitiator; between 0.1% and 0.3% stabilizer; 3% or less rheology modifier; wherein a viscosity of the ink composition is between 1×106 and 1×107 cps at 35° C.; and wherein a 60 second tack of the ink composition is about 40 g-m at 35° C. 9. The ink composition of claim 1, wherein the photoinitiator is a free-radical photoinitiator. 10. The ink composition of claim 1, wherein the pigment is one of a cyan pigment, a magenta pigment, a yellow pigment, or a black pigment. 11. A set of compatible acrylate ink compositions comprising:
a first acrylate ink composition comprising a first pigment; a second acrylate ink composition comprising a second pigment; wherein each of the acrylate ink compositions comprises: a tetrafunctional polyester acrylate oligomer; a polyester acrylate oligomer that is different than the tetrafunctional polyester acrylate oligomer; an optional dispersant; and an optional photoinitiator. 12. The set of compatible acrylate ink compositions of claim 11, wherein each of acrylate ink compositions further comprises:
at least one member of the group consisting of a propoxylated trimethololpropane triacrylate monomer and an ethoxylated trimethylolpropane triacrylate monomer. 13. The set of compatible acrylate ink compositions of claim 11, wherein each of acrylate ink compositions further comprises:
at least one member of the group consisting of a propoxylated trimethololpropane triacrylate monomer, an ethoxylated trimethylolpropane triacrylate monomer, and a monomer having a functionality greater than or equal to 4. 14. The set of compatible acrylate ink compositions of claim 11, wherein a viscosity of each of the ink compositions is between 5×105 and 3×107 cps at 35° C. 15. The set of compatible acrylate ink compositions of claim 11, wherein a 60 second tack of each of the ink composition is between 25 and 50 g-m at 35° C. 16. The set of compatible acrylate ink compositions of claim 11, wherein each of the ink compositions comprises:
between 40% and 50% by weight acrylate, based on a total weight of the ink composition; 30% or less by weight pigment, based on the total weight of the ink composition; 10% or less by weight dispersant, based on the total weight of the ink composition; and 12% or less by weight photoinitiator, based on the total weight of the ink composition. 17. The set of compatible acrylate ink compositions of claim 11, wherein each of the ink compositions further comprises:
a stabilizer; and a rheology modifier. 18. The set of compatible acrylate ink compositions of claim 11, wherein each of the ink compositions further comprises:
a rheology modifier; and wherein each of the ink compositions comprises: between 12% and 18% pigment; between 4% and 8% dispersant; between 40% and 50% acrylate; between 5% and 10% less photoinitiator; between 0.1% and 0.3% stabilizer; 3% or less rheology modifier; wherein a viscosity of each ink composition is between 1×106 and 1×107 cps at 35° C.; and wherein a 60 second tack of each ink composition is about 40 g-m at 35° C. 19. The set of compatible acrylate ink compositions of claim 11, wherein the photoinitiator is a free-radical photoinitiator. 20. The set of compatible acrylate ink compositions of claim 11, wherein the first pigment is one of a cyan pigment, a magenta pigment, and a yellow pigment; and
wherein the second pigment is a black pigment. | Compatible acrylate ink sets include an acrylate ink composition having 30% or less by weight pigment, 10% or less dispersant, between 40% and 80% acrylate, 12% or less photoinitiator, a viscosity between 5×10 5 and 3×10 7 cps at 35° C., and a 60 second tack between 25 and 50 g-m at 35° C.1. An acrylate ink composition comprising:
a tetrafunctional polyester acrylate oligomer; a polyester acrylate oligomer that is different than the tetrafunctional polyester acrylate oligomer; a pigment; an optional dispersant; and an optional photoinitiator. 2. The ink composition of claim 1, further comprising:
at least one member of the group consisting of a propoxylated trimethololpropane triacrylate monomer and an ethoxylated trimethylolpropane triacrylate monomer. 3. The ink composition of claim 1, further comprising:
at least one member of the group consisting of a propoxylated trimethololpropane triacrylate monomer, an ethoxylated trimethylolpropane triacrylate monomer, and a monomer having a functionality greater than or equal to 4. 4. The ink composition of claim 1, wherein a viscosity of the ink composition is between 5×105 and 3×107 cps at 35° C. 5. The ink composition of claim 1, wherein a 60 second tack of the ink composition is between 25 and 50 g-m at 35° C. 6. The ink composition of claim 1, wherein the ink composition comprises between 40% and 50% by weight acrylate, based on a total weight of the ink composition;
30% or less by weight pigment, based on the total weight of the ink composition; 10% or less by weight dispersant, based on the total weight of the ink composition; and 12% or less by weight photoinitiator, based on the total weight of the ink composition. 7. The ink composition of claim 1, further comprising:
a stabilizer; and a rheology modifier; wherein the ink composition comprises: between 10% and 20% pigment; between 2% and 10% dispersant; between 40% and 50% acrylate; 10% or less photoinitiator; 0.4% or less stabilizer; between 1% and 5% rheology modifier; wherein a viscosity of the ink composition is between 8×105 and 2×107 cps at 35° C.; and wherein a 60 second tack of the ink composition is between 35 and 45 g-m at 35° C. 8. The ink composition of claim 1, further comprising:
a stabilizer; and a rheology modifier; wherein the ink composition comprises: between 12% and 18% pigment; between 4% and 8% dispersant; between 40% and 50% acrylate; between 5% and 10% less photoinitiator; between 0.1% and 0.3% stabilizer; 3% or less rheology modifier; wherein a viscosity of the ink composition is between 1×106 and 1×107 cps at 35° C.; and wherein a 60 second tack of the ink composition is about 40 g-m at 35° C. 9. The ink composition of claim 1, wherein the photoinitiator is a free-radical photoinitiator. 10. The ink composition of claim 1, wherein the pigment is one of a cyan pigment, a magenta pigment, a yellow pigment, or a black pigment. 11. A set of compatible acrylate ink compositions comprising:
a first acrylate ink composition comprising a first pigment; a second acrylate ink composition comprising a second pigment; wherein each of the acrylate ink compositions comprises: a tetrafunctional polyester acrylate oligomer; a polyester acrylate oligomer that is different than the tetrafunctional polyester acrylate oligomer; an optional dispersant; and an optional photoinitiator. 12. The set of compatible acrylate ink compositions of claim 11, wherein each of acrylate ink compositions further comprises:
at least one member of the group consisting of a propoxylated trimethololpropane triacrylate monomer and an ethoxylated trimethylolpropane triacrylate monomer. 13. The set of compatible acrylate ink compositions of claim 11, wherein each of acrylate ink compositions further comprises:
at least one member of the group consisting of a propoxylated trimethololpropane triacrylate monomer, an ethoxylated trimethylolpropane triacrylate monomer, and a monomer having a functionality greater than or equal to 4. 14. The set of compatible acrylate ink compositions of claim 11, wherein a viscosity of each of the ink compositions is between 5×105 and 3×107 cps at 35° C. 15. The set of compatible acrylate ink compositions of claim 11, wherein a 60 second tack of each of the ink composition is between 25 and 50 g-m at 35° C. 16. The set of compatible acrylate ink compositions of claim 11, wherein each of the ink compositions comprises:
between 40% and 50% by weight acrylate, based on a total weight of the ink composition; 30% or less by weight pigment, based on the total weight of the ink composition; 10% or less by weight dispersant, based on the total weight of the ink composition; and 12% or less by weight photoinitiator, based on the total weight of the ink composition. 17. The set of compatible acrylate ink compositions of claim 11, wherein each of the ink compositions further comprises:
a stabilizer; and a rheology modifier. 18. The set of compatible acrylate ink compositions of claim 11, wherein each of the ink compositions further comprises:
a rheology modifier; and wherein each of the ink compositions comprises: between 12% and 18% pigment; between 4% and 8% dispersant; between 40% and 50% acrylate; between 5% and 10% less photoinitiator; between 0.1% and 0.3% stabilizer; 3% or less rheology modifier; wherein a viscosity of each ink composition is between 1×106 and 1×107 cps at 35° C.; and wherein a 60 second tack of each ink composition is about 40 g-m at 35° C. 19. The set of compatible acrylate ink compositions of claim 11, wherein the photoinitiator is a free-radical photoinitiator. 20. The set of compatible acrylate ink compositions of claim 11, wherein the first pigment is one of a cyan pigment, a magenta pigment, and a yellow pigment; and
wherein the second pigment is a black pigment. | 2,800 |
11,434 | 11,434 | 15,262,583 | 2,834 | An apparatus includes an electric machine. The electric machine includes an internal housing, an armature coil disposed within the internal housing and separated from the internal housing by a gap, and a magnetic core associated with the armature coil. The apparatus also includes a fan configured to cause air to flow in the gap between the armature coil and the internal housing. | 1-20. (canceled) 21. An apparatus comprising:
a linear motor disposed to generate a linear force, the linear motor including: a first armature coil associated with a first magnetic core and disposed within an internal housing; a second armature coil associated with a second magnetic core and disposed within the internal housing; and a central support core extending from a top of the internal housing to a bottom of the internal housing and disposed between the first armature coil and the second armature coil; wherein the central support core defines a first side gap separating the first armature coil from the central support core and a second side gap separating the second armature coil from the central support core. 22. The apparatus of claim 21, wherein a first portion of the top of the internal housing and the first armature coil define a first upper gap allowing air to flow along a length of the first armature coil, and a second portion of the top of the internal housing and the second armature coil define a second upper gap allowing air to flow along a length of the second armature coil. 23. The apparatus of claim 21, further comprising:
a third armature coil associated with a third magnetic core and disposed within the internal housing adjacent to the first armature coil; and a fourth armature coil associated with a fourth magnetic core and disposed within the internal housing adjacent to the second armature coil; wherein the central support core is disposed between the third armature coil and the fourth armature coil. 24. The apparatus of claim 23, wherein a first portion of the bottom of the internal housing and the third armature coil define a first lower gap allowing air to flow along a length of the third armature coil, and a second portion of the bottom of the internal housing and the fourth armature coil define a second lower gap allowing air to flow along a length of the fourth armature coil. 25. The apparatus of claim 23, wherein a portion of the first armature coil and a portion of the third armature coil define a first central gap between the first armature coil and the third armature coil, and wherein a portion of the second armature coil and a portion of the fourth armature coil define a second central gap between the second armature coil and the fourth armature coil. 26. The apparatus of claim 23, wherein the central support core further defines a third side gap separating the third armature coil from the central support core and a fourth side gap separating the fourth armature coil from the central support core. 27. The apparatus of claim 26, wherein the third side gap is configured to allow air to flow in contact with the third magnetic core and the fourth side gap is configured to allow air to flow in contact with the fourth magnetic core. 28. The apparatus of claim 26, wherein the third side gap and the fourth side gap are configured to allow air to flow in a direction substantially parallel to the linear force of the linear motor. 29. The apparatus of claim 21, wherein the first side gap is configured to allow air to flow in contact with the first magnetic core and the second side gap is configured to allow air to flow in contact with the second magnetic core. 30. The apparatus of claim 21, wherein the first side gap and the second side gap are configured to allow air to flow in a direction substantially parallel to the linear force of the linear motor. 31. A method of cooling armature coils of a linear motor, the method comprising:
providing a linear motor disposed to generate a linear force, the linear motor comprising:
a first armature coil associated with a first magnetic core and disposed within an internal housing;
a second armature coil associated with a second magnetic core and disposed within the internal housing; and
a central support core extending from a top of the internal housing to a bottom of the internal housing and disposed between the first armature coil and the second armature coil;
flowing air in contact with the first magnetic core through a first side gap separating the first armature coil from the central support core; and flowing air in contact with the second magnetic core through a second side gap separating the second armature coil from the central support core. 32. The method of claim 31, wherein flowing air through the first side gap and flowing air through the second side gap includes operating a fan to direct a turbulent air flow through the first side gap and the second side gap in a direction substantially parallel to the linear force of the linear motor. 33. The method of claim 31, further comprising:
flowing air along a length of the first armature coil through a first upper gap defined by a first portion of the top of the internal housing and the first armature coil; and flowing air along a length of the second armature coil through a second upper gap defined by a second portion of the top of the internal housing and the second armature coil. 34. The method of claim 31, wherein the linear motor further comprises:
a third armature coil associated with a third magnetic core and disposed within the internal housing adjacent to the first armature coil; and a fourth armature coil associated with a fourth magnetic core and disposed within the internal housing adjacent to the second armature coil, wherein the central support core is disposed between the third armature coil and the fourth armature coil; wherein the method further comprises: flowing air in contact with the third magnetic core through a third side gap defined by the central support core and the third armature coil; and flowing air in contact with the fourth magnetic core through a fourth side gap defined by the central support core and the fourth armature coil. 35. The method of claim 34, further comprising:
flowing air along a length of the third armature coil through a first lower gap defined by a first portion of the bottom of the internal housing and the third armature coil; and flowing air along a length of the fourth armature coil through a second lower gap defined by a second portion of the bottom of the internal housing and the fourth armature coil. 36. The method of claim 34, further comprising:
flowing air through a first central gap between the first armature coil and the third armature coil; and flowing air through a second central gap between the second armature coil and the fourth armature coil. | An apparatus includes an electric machine. The electric machine includes an internal housing, an armature coil disposed within the internal housing and separated from the internal housing by a gap, and a magnetic core associated with the armature coil. The apparatus also includes a fan configured to cause air to flow in the gap between the armature coil and the internal housing.1-20. (canceled) 21. An apparatus comprising:
a linear motor disposed to generate a linear force, the linear motor including: a first armature coil associated with a first magnetic core and disposed within an internal housing; a second armature coil associated with a second magnetic core and disposed within the internal housing; and a central support core extending from a top of the internal housing to a bottom of the internal housing and disposed between the first armature coil and the second armature coil; wherein the central support core defines a first side gap separating the first armature coil from the central support core and a second side gap separating the second armature coil from the central support core. 22. The apparatus of claim 21, wherein a first portion of the top of the internal housing and the first armature coil define a first upper gap allowing air to flow along a length of the first armature coil, and a second portion of the top of the internal housing and the second armature coil define a second upper gap allowing air to flow along a length of the second armature coil. 23. The apparatus of claim 21, further comprising:
a third armature coil associated with a third magnetic core and disposed within the internal housing adjacent to the first armature coil; and a fourth armature coil associated with a fourth magnetic core and disposed within the internal housing adjacent to the second armature coil; wherein the central support core is disposed between the third armature coil and the fourth armature coil. 24. The apparatus of claim 23, wherein a first portion of the bottom of the internal housing and the third armature coil define a first lower gap allowing air to flow along a length of the third armature coil, and a second portion of the bottom of the internal housing and the fourth armature coil define a second lower gap allowing air to flow along a length of the fourth armature coil. 25. The apparatus of claim 23, wherein a portion of the first armature coil and a portion of the third armature coil define a first central gap between the first armature coil and the third armature coil, and wherein a portion of the second armature coil and a portion of the fourth armature coil define a second central gap between the second armature coil and the fourth armature coil. 26. The apparatus of claim 23, wherein the central support core further defines a third side gap separating the third armature coil from the central support core and a fourth side gap separating the fourth armature coil from the central support core. 27. The apparatus of claim 26, wherein the third side gap is configured to allow air to flow in contact with the third magnetic core and the fourth side gap is configured to allow air to flow in contact with the fourth magnetic core. 28. The apparatus of claim 26, wherein the third side gap and the fourth side gap are configured to allow air to flow in a direction substantially parallel to the linear force of the linear motor. 29. The apparatus of claim 21, wherein the first side gap is configured to allow air to flow in contact with the first magnetic core and the second side gap is configured to allow air to flow in contact with the second magnetic core. 30. The apparatus of claim 21, wherein the first side gap and the second side gap are configured to allow air to flow in a direction substantially parallel to the linear force of the linear motor. 31. A method of cooling armature coils of a linear motor, the method comprising:
providing a linear motor disposed to generate a linear force, the linear motor comprising:
a first armature coil associated with a first magnetic core and disposed within an internal housing;
a second armature coil associated with a second magnetic core and disposed within the internal housing; and
a central support core extending from a top of the internal housing to a bottom of the internal housing and disposed between the first armature coil and the second armature coil;
flowing air in contact with the first magnetic core through a first side gap separating the first armature coil from the central support core; and flowing air in contact with the second magnetic core through a second side gap separating the second armature coil from the central support core. 32. The method of claim 31, wherein flowing air through the first side gap and flowing air through the second side gap includes operating a fan to direct a turbulent air flow through the first side gap and the second side gap in a direction substantially parallel to the linear force of the linear motor. 33. The method of claim 31, further comprising:
flowing air along a length of the first armature coil through a first upper gap defined by a first portion of the top of the internal housing and the first armature coil; and flowing air along a length of the second armature coil through a second upper gap defined by a second portion of the top of the internal housing and the second armature coil. 34. The method of claim 31, wherein the linear motor further comprises:
a third armature coil associated with a third magnetic core and disposed within the internal housing adjacent to the first armature coil; and a fourth armature coil associated with a fourth magnetic core and disposed within the internal housing adjacent to the second armature coil, wherein the central support core is disposed between the third armature coil and the fourth armature coil; wherein the method further comprises: flowing air in contact with the third magnetic core through a third side gap defined by the central support core and the third armature coil; and flowing air in contact with the fourth magnetic core through a fourth side gap defined by the central support core and the fourth armature coil. 35. The method of claim 34, further comprising:
flowing air along a length of the third armature coil through a first lower gap defined by a first portion of the bottom of the internal housing and the third armature coil; and flowing air along a length of the fourth armature coil through a second lower gap defined by a second portion of the bottom of the internal housing and the fourth armature coil. 36. The method of claim 34, further comprising:
flowing air through a first central gap between the first armature coil and the third armature coil; and flowing air through a second central gap between the second armature coil and the fourth armature coil. | 2,800 |
11,435 | 11,435 | 15,078,162 | 2,883 | An optical block includes a first surface that receives light entering the optical block, a second surface through which the light exits the optical block, and a reflector that reflects light from the first surface towards the second surface. The reflector includes a textured surface that scatters or absorbs some of the light received from the first surface to attenuate the light exiting the optical block through the second surface. | 1. An optical block comprising:
a first surface that receives light entering the optical block; a second surface through which the light exits the optical block; and a reflector that reflects light from the first surface towards the second surface; wherein the reflector includes a textured surface that scatters or absorbs some of the light received from the first surface to attenuate the light exiting the optical block through the second surface. 2. The optical block of claim 1, wherein the textured surface includes dimples. 3. The optical block of claim 1, wherein the textured surface include dots. 4. The optical block of claim 3, wherein the dots are made of material with an index of refraction that matches or substantially matches an index of refraction of the optical block. 5. The optical block of claim 1, wherein the textured surface includes scratches. 6. The optical block of claim 1, wherein the optical block is a molded optical block. 7. The optical block of claim 1, wherein the textured surface includes defects formed by a molding process or a surface modification process. 8. An optical engine comprising:
a substrate; a laser mounted to the substrate; an optical block according to claim 1; and an optical fiber that receives light from the second surface of the optical block; wherein the light received by the first surface of the optical block is generated by the laser. 9. The optical engine of claim 8, further comprising a photodetector that detects light scattered by the textured surface. 10. The optical engine of claim 8, wherein the optical engine includes multiple channels. 11. The optical engine of claim 10, wherein at least two optical channels have different attenuation levels. 12. The optical engine of claim 10, wherein the textured surface scatters the same amount of light for each channel of the multiple channels. 13. A method of attenuating light in an optical engine, the method comprising:
providing an optical engine, the optical engine including:
a substrate;
a laser mounted to the substrate;
an optical block including:
a first surface that receives light entering the optical block from the laser;
a second surface through which the light exits the optical block; and
a reflector that reflects light from the first surface towards the second surface; and
an optical fiber that receives light from the second surface of the optical block;
determining a current provided to the laser; measuring optical power in the optical fiber; and texturing a surface of the reflector until the optical power measured in the optical fiber is reduced to a predetermined level to form a textured surface. 14. The method of claim 13, wherein the textured surface includes dimples. 15. The method of claim 13, wherein the textured surface include dots. 16. The method of claim 15, wherein the dots are made of material with an index of refraction that matches or substantially matches an index of refraction of the optical block. 17. The method of claim 13, wherein the textured surface includes scratches. 18. The method of claim 13, further comprising molding the optical block. 19. The method of claim 18, wherein the textured surface includes defects formed during the molding of the optical block. 20. The method of claim 13, wherein the textured surface is formed from laser processing. 21. The method of claim 20, wherein the laser is a pulsed laser and has an emission wavelength that is absorbed in the optical block. 22. The method of claim 20, wherein the laser processing includes scanning the laser across the reflective surface. | An optical block includes a first surface that receives light entering the optical block, a second surface through which the light exits the optical block, and a reflector that reflects light from the first surface towards the second surface. The reflector includes a textured surface that scatters or absorbs some of the light received from the first surface to attenuate the light exiting the optical block through the second surface.1. An optical block comprising:
a first surface that receives light entering the optical block; a second surface through which the light exits the optical block; and a reflector that reflects light from the first surface towards the second surface; wherein the reflector includes a textured surface that scatters or absorbs some of the light received from the first surface to attenuate the light exiting the optical block through the second surface. 2. The optical block of claim 1, wherein the textured surface includes dimples. 3. The optical block of claim 1, wherein the textured surface include dots. 4. The optical block of claim 3, wherein the dots are made of material with an index of refraction that matches or substantially matches an index of refraction of the optical block. 5. The optical block of claim 1, wherein the textured surface includes scratches. 6. The optical block of claim 1, wherein the optical block is a molded optical block. 7. The optical block of claim 1, wherein the textured surface includes defects formed by a molding process or a surface modification process. 8. An optical engine comprising:
a substrate; a laser mounted to the substrate; an optical block according to claim 1; and an optical fiber that receives light from the second surface of the optical block; wherein the light received by the first surface of the optical block is generated by the laser. 9. The optical engine of claim 8, further comprising a photodetector that detects light scattered by the textured surface. 10. The optical engine of claim 8, wherein the optical engine includes multiple channels. 11. The optical engine of claim 10, wherein at least two optical channels have different attenuation levels. 12. The optical engine of claim 10, wherein the textured surface scatters the same amount of light for each channel of the multiple channels. 13. A method of attenuating light in an optical engine, the method comprising:
providing an optical engine, the optical engine including:
a substrate;
a laser mounted to the substrate;
an optical block including:
a first surface that receives light entering the optical block from the laser;
a second surface through which the light exits the optical block; and
a reflector that reflects light from the first surface towards the second surface; and
an optical fiber that receives light from the second surface of the optical block;
determining a current provided to the laser; measuring optical power in the optical fiber; and texturing a surface of the reflector until the optical power measured in the optical fiber is reduced to a predetermined level to form a textured surface. 14. The method of claim 13, wherein the textured surface includes dimples. 15. The method of claim 13, wherein the textured surface include dots. 16. The method of claim 15, wherein the dots are made of material with an index of refraction that matches or substantially matches an index of refraction of the optical block. 17. The method of claim 13, wherein the textured surface includes scratches. 18. The method of claim 13, further comprising molding the optical block. 19. The method of claim 18, wherein the textured surface includes defects formed during the molding of the optical block. 20. The method of claim 13, wherein the textured surface is formed from laser processing. 21. The method of claim 20, wherein the laser is a pulsed laser and has an emission wavelength that is absorbed in the optical block. 22. The method of claim 20, wherein the laser processing includes scanning the laser across the reflective surface. | 2,800 |
11,436 | 11,436 | 12,225,962 | 2,858 | The invention relates to an inductive sensor with an electrical coil assembly ( 1, 2,3 ) which has a coil body ( 2 ) and a wire wound coil ( 1 ), wherein at least one wire end ( 6, 7 ) is guided out of the wire wound coil ( 1 ) to electrical connection elements ( 17, 18 ) which connect the coil assembly ( 1, 2, 3 ) to the surrounding area, wherein the coil assembly ( 1, 2, 3 ) is at least partly extrusion-coated by an extrusion-coat mass ( 12 ) and is located in a pot-shaped housing ( 13 ). Therefore, an improved inductive sensor with regard to temperature change stability is specified. Said inductive sensor has at least one barrier ( 10, 11, 100 ) near the wire ends ( 6, 7 ) which are guided out of the wire wound coil ( 1 ) and is located between the wire ends ( 6, 7 ) which are guided out of the wire wound coil ( 1 ) and the injection point of the extrusion-coat mass ( 12 ) during the extrusion-coating. The extrusion-coat mass ( 12 ) is laterally deflected from the area within which the wire ends run and basically flows at a right angle to the wire ends, wherein the partial streams meet near the wire ends. | 1. An inductive sensor having an electric coil subassembly (1, 2, 3), including a coil former (2) and a coil winding (1) of wire, wherein at least one wire end (6, 7) is led out of the coil winding (1) to electric terminal elements (17, 18), which are used for connecting the coil subassembly (1, 2, 3) to the surroundings, the coil subassembly (1, 2, 3) being at least partly coated with an injection-molding compound (12) and being disposed in a pot-like housing (13), characterized in that there is provided, in the region of the wire end (6, 7) led out of the coil winding (1), at least one barrier (10, 11, 100), which is disposed between the wire end (6, 7) led out of the coil winding (1) and the point of injection of the compound (12) during the injection-molding operation. 2. A sensor according to claim 1, characterized in that, once the compound (12) has solidified in the region of the wire end (6, 7) led out of the coil winding (1), it has lower density than is the case in the other regions provided with the compound (12). 3. A sensor according to at least one of the preceding claims, characterized in that the molecular orientation of the compound (12) that has solidified in the region of the wire end (6, 7) led out of the coil winding (1) runs predominantly perpendicular to the wire end. 4. A sensor according to at least one of the preceding claims, characterized in that the pot-like housing (13) is made of metal. 5. A sensor according to at least one of the preceding claims, characterized in that the coil subassembly (1, 2, 3) is completely coated with the compound (12). 6. A sensor according to at least one of the preceding claims, characterized in that the compound (12) is reinforced with glass beads. 7. A sensor according to at least one of the preceding claims, characterized in that the compound (12) is reinforced with glass fibers. 8. A sensor according to claim 7, characterized in that, after the compound (12) has solidified in the region of the wire end (6, 7) led out of the coil winding (1), the fiber direction thereof is predominantly perpendicular to the wire end. 9. A sensor according to at least one of the preceding claims, characterized in that each terminal element (17, 18) has a respective terminal point (15, 16) for connection of the wire end, which point is disposed between the barrier (10, 11, 100) and the coil winding (1) relative to the longitudinal extent of the coil subassembly (1, 2, 3). 10. A sensor according to claim 9, characterized in that, after the compound (12) has solidified in the region of the terminal point (15, 16), it has lower density than in the other regions provided with the compound (12). 11. A sensor according to at least one of claims 9 to 10, characterized in that, after the compound (12) has solidified in the region of the wire end (6, 7) led out of the coil winding (1), the molecular orientation thereof is predominantly perpendicular to the area in which the terminal point (15, 16) extends. 12. A sensor according to at least one of claims 9 to 11, characterized in that, after the compound (12) has solidified in the region of the terminal point (15, 16), the fiber direction thereof is predominantly perpendicular to the area in which the terminal point extends. 13. A sensor according to at least one of the preceding claims, characterized in that the barrier (10, 11, 100) deflects the flow direction of the injection-molding compound approximately at right angles after it has passed the barrier during the injection-molding operation. 14. A sensor according to at least one of the preceding claims, characterized in that the barrier (10, 11, 100) extends in radial direction at least approximately to the outside surface of the injection-molding compound (12). 15. A sensor according to at least one of the preceding claims, characterized in that the barrier (10, 11, 100) is provided with a least one ramp-like guide contour (90) for guiding the injection-molding compound during the injection-molding operation. 16. A sensor according to at least one of the preceding claims, characterized in that the coil former (2) extends beyond the coil winding (1) in longitudinal direction of the coil subassembly (1, 2, 3) and the barrier (10, 11, 100) is disposed in the region (3) extending therebeyond. 17. A sensor according to claim 16, characterized in that the wire end (6, 7) led out of the coil winding (1) is routed along the region (3) of the coil former (2) that extends beyond the coil winding (1). 18. A sensor according to at least one of claims 16 to 17, characterized in that at least one guide element (4, 5) for guiding the wire end (6, 7) is disposed on the region (3) of the coil former (2) that extends beyond the coil winding (1). 19. A sensor according to claim 18, characterized in that the guide element (4, 5) is provided with a tangentially open guide contour for receiving the wire end (6, 7). 20. A sensor according to at least one of the preceding claims, characterized in that the barrier (100) is formed as a plate-like component. 21. A sensor according to at least one of the preceding claims, characterized in that a thermoplastic, especially polyamide, is used as the injection-molding compound (12). | The invention relates to an inductive sensor with an electrical coil assembly ( 1, 2,3 ) which has a coil body ( 2 ) and a wire wound coil ( 1 ), wherein at least one wire end ( 6, 7 ) is guided out of the wire wound coil ( 1 ) to electrical connection elements ( 17, 18 ) which connect the coil assembly ( 1, 2, 3 ) to the surrounding area, wherein the coil assembly ( 1, 2, 3 ) is at least partly extrusion-coated by an extrusion-coat mass ( 12 ) and is located in a pot-shaped housing ( 13 ). Therefore, an improved inductive sensor with regard to temperature change stability is specified. Said inductive sensor has at least one barrier ( 10, 11, 100 ) near the wire ends ( 6, 7 ) which are guided out of the wire wound coil ( 1 ) and is located between the wire ends ( 6, 7 ) which are guided out of the wire wound coil ( 1 ) and the injection point of the extrusion-coat mass ( 12 ) during the extrusion-coating. The extrusion-coat mass ( 12 ) is laterally deflected from the area within which the wire ends run and basically flows at a right angle to the wire ends, wherein the partial streams meet near the wire ends.1. An inductive sensor having an electric coil subassembly (1, 2, 3), including a coil former (2) and a coil winding (1) of wire, wherein at least one wire end (6, 7) is led out of the coil winding (1) to electric terminal elements (17, 18), which are used for connecting the coil subassembly (1, 2, 3) to the surroundings, the coil subassembly (1, 2, 3) being at least partly coated with an injection-molding compound (12) and being disposed in a pot-like housing (13), characterized in that there is provided, in the region of the wire end (6, 7) led out of the coil winding (1), at least one barrier (10, 11, 100), which is disposed between the wire end (6, 7) led out of the coil winding (1) and the point of injection of the compound (12) during the injection-molding operation. 2. A sensor according to claim 1, characterized in that, once the compound (12) has solidified in the region of the wire end (6, 7) led out of the coil winding (1), it has lower density than is the case in the other regions provided with the compound (12). 3. A sensor according to at least one of the preceding claims, characterized in that the molecular orientation of the compound (12) that has solidified in the region of the wire end (6, 7) led out of the coil winding (1) runs predominantly perpendicular to the wire end. 4. A sensor according to at least one of the preceding claims, characterized in that the pot-like housing (13) is made of metal. 5. A sensor according to at least one of the preceding claims, characterized in that the coil subassembly (1, 2, 3) is completely coated with the compound (12). 6. A sensor according to at least one of the preceding claims, characterized in that the compound (12) is reinforced with glass beads. 7. A sensor according to at least one of the preceding claims, characterized in that the compound (12) is reinforced with glass fibers. 8. A sensor according to claim 7, characterized in that, after the compound (12) has solidified in the region of the wire end (6, 7) led out of the coil winding (1), the fiber direction thereof is predominantly perpendicular to the wire end. 9. A sensor according to at least one of the preceding claims, characterized in that each terminal element (17, 18) has a respective terminal point (15, 16) for connection of the wire end, which point is disposed between the barrier (10, 11, 100) and the coil winding (1) relative to the longitudinal extent of the coil subassembly (1, 2, 3). 10. A sensor according to claim 9, characterized in that, after the compound (12) has solidified in the region of the terminal point (15, 16), it has lower density than in the other regions provided with the compound (12). 11. A sensor according to at least one of claims 9 to 10, characterized in that, after the compound (12) has solidified in the region of the wire end (6, 7) led out of the coil winding (1), the molecular orientation thereof is predominantly perpendicular to the area in which the terminal point (15, 16) extends. 12. A sensor according to at least one of claims 9 to 11, characterized in that, after the compound (12) has solidified in the region of the terminal point (15, 16), the fiber direction thereof is predominantly perpendicular to the area in which the terminal point extends. 13. A sensor according to at least one of the preceding claims, characterized in that the barrier (10, 11, 100) deflects the flow direction of the injection-molding compound approximately at right angles after it has passed the barrier during the injection-molding operation. 14. A sensor according to at least one of the preceding claims, characterized in that the barrier (10, 11, 100) extends in radial direction at least approximately to the outside surface of the injection-molding compound (12). 15. A sensor according to at least one of the preceding claims, characterized in that the barrier (10, 11, 100) is provided with a least one ramp-like guide contour (90) for guiding the injection-molding compound during the injection-molding operation. 16. A sensor according to at least one of the preceding claims, characterized in that the coil former (2) extends beyond the coil winding (1) in longitudinal direction of the coil subassembly (1, 2, 3) and the barrier (10, 11, 100) is disposed in the region (3) extending therebeyond. 17. A sensor according to claim 16, characterized in that the wire end (6, 7) led out of the coil winding (1) is routed along the region (3) of the coil former (2) that extends beyond the coil winding (1). 18. A sensor according to at least one of claims 16 to 17, characterized in that at least one guide element (4, 5) for guiding the wire end (6, 7) is disposed on the region (3) of the coil former (2) that extends beyond the coil winding (1). 19. A sensor according to claim 18, characterized in that the guide element (4, 5) is provided with a tangentially open guide contour for receiving the wire end (6, 7). 20. A sensor according to at least one of the preceding claims, characterized in that the barrier (100) is formed as a plate-like component. 21. A sensor according to at least one of the preceding claims, characterized in that a thermoplastic, especially polyamide, is used as the injection-molding compound (12). | 2,800 |
11,437 | 11,437 | 14,467,413 | 2,832 | A system for electric power production from wind includes a glider having an airfoil, an on-board steering unit, a flight controller for controlling the steering unit, and a connection unit for a tether. The system further includes a ground station including a reel for the tether, a rotating electrical machine connected to the reel, and a ground station controller for controlling the reel and the rotating electrical machine. A master controller operates the system in at least first and second operation modes. In the first operation mode electric power is produced with the rotating electrical machine from rotation of the reel caused by reeling out the tether using a lift force generated upon exposure of the airfoil of the airborne glider to wind. In the second operation mode, the reel is driven by the rotating electrical machine, thereby reeling in the tether onto the reel. | 1. A system for electric power production from wind comprising a glider, said glider having an airfoil, on-board steering unit for pitching, rolling and yawing the glider when airborne, a flight controller for operation of the steering unit, and a connection unit for a tether, the system further comprising a ground station, said ground station comprising a reel for the tether, a rotating electrical machine connected to the reel, and a ground station controller for operation of the reel and the rotating electrical machine, and the system further comprising a master controller for operation of the system in at least two alternative operation modes, wherein a first operation mode of the system is provided for electric power production with the rotating electrical machine from a rotation of the reel induced by reeling out the tether using a lift force generated upon exposure of the airfoil of the airborne glider to wind, and wherein a second operation mode of the system is provided for system recovery by driving the reel with the rotating electrical machine, thereby reeling in the tether onto the reel. 2. The system according to claim 1, wherein the flight controller provides for a first flight control mode for automated flight operation and for a second flight control mode for manual operation, in particular via a remote control unit with wired or wireless connection to the flight controller. 3. The system according to claim 1, wherein the glider further comprises an air speed sensor for determining an air speed of the glider. 4. The system according to claim 1, wherein the glider comprises a control unit incorporating both the flight controller and the master controller. 5. The system according to claim 1, wherein the ground station further comprises a tension sensor for determining a tension of the tether. 6. The system according to claim 1, wherein the ground station controller is designed for retaining a predetermined target tension of the tether, in particular during reeling out the tether. 7. The system according to claim 1, wherein the ground station controller is designed for retaining a predetermined target reel speed, in particular during reeling in the tether. 8. The system according to claim 1, wherein the tether comprises a power transmission line and/or a data transmission line between the glider and the ground station. 9. A method for operation of a system for electric power production from wind, said system comprising a glider connected to a tether and a ground station with a reel for the tether, wherein said system is operated alternately in a first operation mode for power production and a second operation mode for system recovery, wherein the first operation mode comprises:
steering the glider to follow a first flight pattern, thereby generating a lift force via an airfoil of the glider being exposed to the wind, pulling the tether by said lift force and reeling out the tether, thereby inducing a rotation of the reel, and converting the rotation of the reel into electric power via a rotating electrical machine connected to the reel,
wherein the second operation mode comprises:
steering the glider to follow a second flight pattern for reduced pull on the tether and
reeling in the tether onto the reel by driving the reel via said rotating electrical machine connected to the reel. 10. The method according to claim 9, wherein reeling out the tether is controlled to retain a target tension of the tether, which is predetermined as a function of an air speed of the glider. 11. The method according to claim 9, wherein reeling in the tether is controlled to retain a target reel speed, which is predetermined as a function of an air speed of the glider. 12. A glider that is adapted to be used in a system for electric power production from wind, wherein the system comprises a ground station, said ground station comprising a reel for the tether, a rotating electrical machine connected to the reel, and a ground station controller for operation of the reel and the rotating electrical machine, said glider comprising an airfoil for generating a lift force upon exposure of the airfoil to wind, on-board steering unit for pitching, rolling and yawing the glider when airborne, a flight controller for operation of the steering unit and a connection unit for a tether, wherein the glider comprises an on-board control unit incorporating the flight controller and a master controller for the operation of the system in at least two alternative operation modes;
wherein a first operation mode of the system is provided for electric power production with the rotating electrical machine from a rotation of the reel induced by reeling out the tether using a lift force generated upon exposure of the airfoil of the airborne glider to wind, and wherein a second operation mode of the system is provided for system recovery by driving the reel with the rotating electrical machine, thereby reeling in the tether onto the reel. | A system for electric power production from wind includes a glider having an airfoil, an on-board steering unit, a flight controller for controlling the steering unit, and a connection unit for a tether. The system further includes a ground station including a reel for the tether, a rotating electrical machine connected to the reel, and a ground station controller for controlling the reel and the rotating electrical machine. A master controller operates the system in at least first and second operation modes. In the first operation mode electric power is produced with the rotating electrical machine from rotation of the reel caused by reeling out the tether using a lift force generated upon exposure of the airfoil of the airborne glider to wind. In the second operation mode, the reel is driven by the rotating electrical machine, thereby reeling in the tether onto the reel.1. A system for electric power production from wind comprising a glider, said glider having an airfoil, on-board steering unit for pitching, rolling and yawing the glider when airborne, a flight controller for operation of the steering unit, and a connection unit for a tether, the system further comprising a ground station, said ground station comprising a reel for the tether, a rotating electrical machine connected to the reel, and a ground station controller for operation of the reel and the rotating electrical machine, and the system further comprising a master controller for operation of the system in at least two alternative operation modes, wherein a first operation mode of the system is provided for electric power production with the rotating electrical machine from a rotation of the reel induced by reeling out the tether using a lift force generated upon exposure of the airfoil of the airborne glider to wind, and wherein a second operation mode of the system is provided for system recovery by driving the reel with the rotating electrical machine, thereby reeling in the tether onto the reel. 2. The system according to claim 1, wherein the flight controller provides for a first flight control mode for automated flight operation and for a second flight control mode for manual operation, in particular via a remote control unit with wired or wireless connection to the flight controller. 3. The system according to claim 1, wherein the glider further comprises an air speed sensor for determining an air speed of the glider. 4. The system according to claim 1, wherein the glider comprises a control unit incorporating both the flight controller and the master controller. 5. The system according to claim 1, wherein the ground station further comprises a tension sensor for determining a tension of the tether. 6. The system according to claim 1, wherein the ground station controller is designed for retaining a predetermined target tension of the tether, in particular during reeling out the tether. 7. The system according to claim 1, wherein the ground station controller is designed for retaining a predetermined target reel speed, in particular during reeling in the tether. 8. The system according to claim 1, wherein the tether comprises a power transmission line and/or a data transmission line between the glider and the ground station. 9. A method for operation of a system for electric power production from wind, said system comprising a glider connected to a tether and a ground station with a reel for the tether, wherein said system is operated alternately in a first operation mode for power production and a second operation mode for system recovery, wherein the first operation mode comprises:
steering the glider to follow a first flight pattern, thereby generating a lift force via an airfoil of the glider being exposed to the wind, pulling the tether by said lift force and reeling out the tether, thereby inducing a rotation of the reel, and converting the rotation of the reel into electric power via a rotating electrical machine connected to the reel,
wherein the second operation mode comprises:
steering the glider to follow a second flight pattern for reduced pull on the tether and
reeling in the tether onto the reel by driving the reel via said rotating electrical machine connected to the reel. 10. The method according to claim 9, wherein reeling out the tether is controlled to retain a target tension of the tether, which is predetermined as a function of an air speed of the glider. 11. The method according to claim 9, wherein reeling in the tether is controlled to retain a target reel speed, which is predetermined as a function of an air speed of the glider. 12. A glider that is adapted to be used in a system for electric power production from wind, wherein the system comprises a ground station, said ground station comprising a reel for the tether, a rotating electrical machine connected to the reel, and a ground station controller for operation of the reel and the rotating electrical machine, said glider comprising an airfoil for generating a lift force upon exposure of the airfoil to wind, on-board steering unit for pitching, rolling and yawing the glider when airborne, a flight controller for operation of the steering unit and a connection unit for a tether, wherein the glider comprises an on-board control unit incorporating the flight controller and a master controller for the operation of the system in at least two alternative operation modes;
wherein a first operation mode of the system is provided for electric power production with the rotating electrical machine from a rotation of the reel induced by reeling out the tether using a lift force generated upon exposure of the airfoil of the airborne glider to wind, and wherein a second operation mode of the system is provided for system recovery by driving the reel with the rotating electrical machine, thereby reeling in the tether onto the reel. | 2,800 |
11,438 | 11,438 | 15,480,584 | 2,842 | Provided is a bias circuit that supplies a first bias current or voltage to an amplifier that amplifies a radio frequency signal. The bias circuit includes: an FET that has a power supply voltage supplied to a drain thereof and that outputs the first bias current or voltage from a source thereof; a first bipolar transistor that has a collector thereof connected to a gate of the FET, that has a base thereof connected to the source of the FET, that has a common emitter and that has a constant current supplied to the collector thereof; and a first capacitor that has one end thereof connected to the collector of the first bipolar transistor and that suppresses variations in a collector voltage of the first bipolar transistor. | 1. A bias circuit that supplies a first bias current or voltage to an amplifier that amplifies a radio frequency signal, the bias circuit comprising:
a field-effect transistor (FET), wherein a power supply voltage is supplied to a drain of the FET and a source of the FET outputs the first bias current or voltage; a first bipolar transistor, wherein a collector of the first bipolar transistor is connected to a gate of the FET, a base of the first bipolar transistor is connected to the source of the FET, the first bipolar transistor has a common emitter, and a constant current is supplied to the collector of the first bipolar transistor; and a first capacitor, wherein a first end of the first capacitor is connected to the collector of the first bipolar transistor and the first capacitor suppresses variations in a collector voltage of the first bipolar transistor. 2. The bias circuit according to claim 1,
wherein a second end of the first capacitor is connected to the base of the first bipolar transistor. 3. The bias circuit according to claim 1,
wherein a second end of the first capacitor is grounded. 4. The bias circuit according to claim 1,
wherein a second end of the first capacitor is connected to the source of the FET. 5. The bias circuit according to claim 1, further comprising:
a second bipolar transistor, wherein a power supply voltage is supplied to a collector of the second bipolar transistor, a control voltage is supplied to a base of the second bipolar transistor, and a second bias current or voltage is supplied from an emitter of the second bipolar transistor to the amplifier; and a second capacitor, wherein a first end of the second capacitor is connected to the emitter of the second bipolar transistor and the radio frequency signal is supplied to a second end of the second capacitor. 6. The bias circuit according to claim 2, further comprising:
a second bipolar transistor, wherein a power supply voltage is supplied to a collector of the second bipolar transistor, a control voltage is supplied to a base of the second bipolar transistor, and a second bias current or voltage is supplied from an emitter of the second bipolar transistor to the amplifier; and a second capacitor, wherein a first end of the second capacitor is connected to the emitter of the second bipolar transistor and the radio frequency signal is supplied to a second end of the second capacitor. 7. The bias circuit according to claim 3, further comprising:
a second bipolar transistor, wherein a power supply voltage is supplied to a collector of the second bipolar transistor, a control voltage is supplied to a base of the second bipolar transistor, and a second bias current or voltage is supplied from an emitter of the second bipolar transistor to the amplifier; and a second capacitor, wherein a first end of the second capacitor is connected to the emitter of the second bipolar transistor and the radio frequency signal is supplied to a second end of the second capacitor. 8. The bias circuit according to claim 4, further comprising:
a second bipolar transistor, wherein a power supply voltage is supplied to a collector of the second bipolar transistor, a control voltage is supplied to a base of the second bipolar transistor, and a second bias current or voltage is supplied from an emitter of the second bipolar transistor to the amplifier; and a second capacitor, wherein a first end of the second capacitor is connected to the emitter of the second bipolar transistor and the radio frequency signal is supplied to a second end of the second capacitor. 9. The bias circuit according to claim 1, further comprising:
a first resistor having a first end connected to the source of the FET and a second end connected to the amplifier; and a second resistor having a first end connected to the source of the FET and a second end connected to the base of the first bipolar transistor. 10. The bias circuit according to claim 2, further comprising:
a first resistor having a first end connected to the source of the FET and a second end connected to the amplifier; and a second resistor having a first end connected to the source of the FET and a second end connected to the base of the first bipolar transistor. 11. The bias circuit according to claim 3, further comprising:
a first resistor having a first end connected to the source of the FET and a second end connected to the amplifier; and a second resistor having a first end connected to the source of the FET and a second end connected to the base of the first bipolar transistor. 12. The bias circuit according to claim 4, further comprising:
a first resistor having a first end connected to the source of the FET and a second end connected to the amplifier; and a second resistor having a first end connected to the source of the FET and a second end connected to the base of the first bipolar transistor. 13. The bias circuit according to claim 5, further comprising:
a third resistor having a first end connected to the emitter of the second bipolar transistor and a second end connected to the amplifier. 14. The bias circuit according to claim 6, further comprising:
a third resistor having a first end connected to the emitter of the second bipolar transistor and a second end connected to the amplifier. 15. The bias circuit according to claim 7, further comprising:
a third resistor having a first end connected to the emitter of the second bipolar transistor and a second end connected to the amplifier. 16. The bias circuit according to claim 8, further comprising:
a third resistor having a first end connected to the emitter of the second bipolar transistor and a second end connected to the amplifier. | Provided is a bias circuit that supplies a first bias current or voltage to an amplifier that amplifies a radio frequency signal. The bias circuit includes: an FET that has a power supply voltage supplied to a drain thereof and that outputs the first bias current or voltage from a source thereof; a first bipolar transistor that has a collector thereof connected to a gate of the FET, that has a base thereof connected to the source of the FET, that has a common emitter and that has a constant current supplied to the collector thereof; and a first capacitor that has one end thereof connected to the collector of the first bipolar transistor and that suppresses variations in a collector voltage of the first bipolar transistor.1. A bias circuit that supplies a first bias current or voltage to an amplifier that amplifies a radio frequency signal, the bias circuit comprising:
a field-effect transistor (FET), wherein a power supply voltage is supplied to a drain of the FET and a source of the FET outputs the first bias current or voltage; a first bipolar transistor, wherein a collector of the first bipolar transistor is connected to a gate of the FET, a base of the first bipolar transistor is connected to the source of the FET, the first bipolar transistor has a common emitter, and a constant current is supplied to the collector of the first bipolar transistor; and a first capacitor, wherein a first end of the first capacitor is connected to the collector of the first bipolar transistor and the first capacitor suppresses variations in a collector voltage of the first bipolar transistor. 2. The bias circuit according to claim 1,
wherein a second end of the first capacitor is connected to the base of the first bipolar transistor. 3. The bias circuit according to claim 1,
wherein a second end of the first capacitor is grounded. 4. The bias circuit according to claim 1,
wherein a second end of the first capacitor is connected to the source of the FET. 5. The bias circuit according to claim 1, further comprising:
a second bipolar transistor, wherein a power supply voltage is supplied to a collector of the second bipolar transistor, a control voltage is supplied to a base of the second bipolar transistor, and a second bias current or voltage is supplied from an emitter of the second bipolar transistor to the amplifier; and a second capacitor, wherein a first end of the second capacitor is connected to the emitter of the second bipolar transistor and the radio frequency signal is supplied to a second end of the second capacitor. 6. The bias circuit according to claim 2, further comprising:
a second bipolar transistor, wherein a power supply voltage is supplied to a collector of the second bipolar transistor, a control voltage is supplied to a base of the second bipolar transistor, and a second bias current or voltage is supplied from an emitter of the second bipolar transistor to the amplifier; and a second capacitor, wherein a first end of the second capacitor is connected to the emitter of the second bipolar transistor and the radio frequency signal is supplied to a second end of the second capacitor. 7. The bias circuit according to claim 3, further comprising:
a second bipolar transistor, wherein a power supply voltage is supplied to a collector of the second bipolar transistor, a control voltage is supplied to a base of the second bipolar transistor, and a second bias current or voltage is supplied from an emitter of the second bipolar transistor to the amplifier; and a second capacitor, wherein a first end of the second capacitor is connected to the emitter of the second bipolar transistor and the radio frequency signal is supplied to a second end of the second capacitor. 8. The bias circuit according to claim 4, further comprising:
a second bipolar transistor, wherein a power supply voltage is supplied to a collector of the second bipolar transistor, a control voltage is supplied to a base of the second bipolar transistor, and a second bias current or voltage is supplied from an emitter of the second bipolar transistor to the amplifier; and a second capacitor, wherein a first end of the second capacitor is connected to the emitter of the second bipolar transistor and the radio frequency signal is supplied to a second end of the second capacitor. 9. The bias circuit according to claim 1, further comprising:
a first resistor having a first end connected to the source of the FET and a second end connected to the amplifier; and a second resistor having a first end connected to the source of the FET and a second end connected to the base of the first bipolar transistor. 10. The bias circuit according to claim 2, further comprising:
a first resistor having a first end connected to the source of the FET and a second end connected to the amplifier; and a second resistor having a first end connected to the source of the FET and a second end connected to the base of the first bipolar transistor. 11. The bias circuit according to claim 3, further comprising:
a first resistor having a first end connected to the source of the FET and a second end connected to the amplifier; and a second resistor having a first end connected to the source of the FET and a second end connected to the base of the first bipolar transistor. 12. The bias circuit according to claim 4, further comprising:
a first resistor having a first end connected to the source of the FET and a second end connected to the amplifier; and a second resistor having a first end connected to the source of the FET and a second end connected to the base of the first bipolar transistor. 13. The bias circuit according to claim 5, further comprising:
a third resistor having a first end connected to the emitter of the second bipolar transistor and a second end connected to the amplifier. 14. The bias circuit according to claim 6, further comprising:
a third resistor having a first end connected to the emitter of the second bipolar transistor and a second end connected to the amplifier. 15. The bias circuit according to claim 7, further comprising:
a third resistor having a first end connected to the emitter of the second bipolar transistor and a second end connected to the amplifier. 16. The bias circuit according to claim 8, further comprising:
a third resistor having a first end connected to the emitter of the second bipolar transistor and a second end connected to the amplifier. | 2,800 |
11,439 | 11,439 | 14,700,205 | 2,827 | A method of determining the frequency and amplitude of a perturbing cyclic EM signal in the field of view of an NMR or MRI system during acquisition of a spin-echo spectrum. The frequency ν of the perturbing electromagnetic signal is determined by acquiring a plurality of n 2 D NMR spectra with n different values of T R ; selecting a peak in each of the n NMR spectra; determining the area of the peak; calculating possible frequencies along the Ω TR axis; and eliminating results that do not match the position along the Ω τ axis, thereby obtaining ν. The amplitude α of the perturbing electromagnetic signal is determined by calculating the square of the area of the peak. | 1. A method for determining the frequency of a perturbing cyclic electromagnetic signal within the field of view of an NMR or MRI instrument during the acquisition of a spin-echo spectrum in said instrument, wherein said method comprises:
acquiring a plurality of n 2D NMR spectra, each of said 2D NMR spectra having a ΩTR axis, a Ωτ axis, and a different value of TR; selecting a peak in each of said n NMR spectra, said peak having a peak value along said Ωτ axis, a peak value along said ΩTR axis, and an area A(Ωτ, ΩTR); calculating, for each n, possible frequencies of said peak along said ΩTR axis; and, eliminating results that do not match the peak value of said peak along said Ωτ axis, thereby obtaining ν. 2. The method according to claim 1, wherein said step of calculating, for each n, possible frequencies along the ΩTR axis comprises calculating said possible frequencies by using the relation ν=nTRSWTR n −yn. 3. The method according to claim 1, wherein said step of eliminating results that do not match the peak value of said peak along said Ωτ axis comprises eliminating results that do not match the peak value of said peak along said Ωτ axis by using
Δ
Ω
τ
=
n
τ
×
SW
τ
-
δ
y
TR
1
+
N
TR
SW
τ
/
SW
TR
. 4. The method according to claim 1, further comprising determining the amplitude α of said perturbing electromagnetic signal, said step of determining the amplitude comprising:
calculating φα=1(tτ, tTR); and,
determining said amplitude α from φα=1(tτ, tTR). 5. The method according to claim 4, wherein said step of calculating φα=1(tτ, tTR) comprises calculating φα=1 (tτ, tTR) from
φ
(
t
τ
,
t
TR
)
=
-
4
π
ω
(
sin
(
φ
0
+
ω
x
t
τ
+
ω
t
TR
)
(
1
-
cos
(
ω
t
τ
)
)
,
where ωx=ω(1+NTRΔtTR/Δtτ). 6. The method according to claim 4, wherein said step of determining said amplitude determining said amplitude α from φα=1(tτ, tTR) comprises:
determining A(Ωτ, ΩTR) of said peak;
calculating A(Ωτ, ΩTR)2 of said peak; and,
determining said amplitude α from
α
=
2
×
∑
Ω
TR
,
Ω
τ
A
(
Ω
τ
,
Ω
TR
)
2
/
N
∑
t
TR
,
t
τ
φ
α
=
1
(
t
τ
,
t
TR
)
2
. 7. The method according to claim 1, wherein n=3. 8. The method according to claim 1, wherein:
said step of selecting a peak in each of said n NMR spectra comprises manually selecting a peak; and, said step of determining A(Ωτ, ΩTR) of said peak comprises: manually selecting a region of said spectrum containing said peak, said region having an area A(R); calculating A(R); and, setting A(Ωτ, ΩTR) of said peak to be equal to A(R). 9. The method according to claim 1, wherein said NMR or MRI instrument comprises a permanent magnet and a plurality of pole pieces. 10. The method according to claim 4, wherein n=3. 11. The method according to claim 4, wherein:
said step of selecting a peak in each of said n NMR spectra comprises manually selecting a peak; and, said step of determining A(Ωτ, ΩTR) of said peak comprises: manually selecting a region of said spectrum containing said peak, said region having an area A(R); calculating A(R); and, setting A(Ωτ, ΩTR) of said peak to be equal to A(R). 12. The method according to claim 4, wherein said NMR or MRI instrument comprises a permanent magnet and a plurality of pole pieces. | A method of determining the frequency and amplitude of a perturbing cyclic EM signal in the field of view of an NMR or MRI system during acquisition of a spin-echo spectrum. The frequency ν of the perturbing electromagnetic signal is determined by acquiring a plurality of n 2 D NMR spectra with n different values of T R ; selecting a peak in each of the n NMR spectra; determining the area of the peak; calculating possible frequencies along the Ω TR axis; and eliminating results that do not match the position along the Ω τ axis, thereby obtaining ν. The amplitude α of the perturbing electromagnetic signal is determined by calculating the square of the area of the peak.1. A method for determining the frequency of a perturbing cyclic electromagnetic signal within the field of view of an NMR or MRI instrument during the acquisition of a spin-echo spectrum in said instrument, wherein said method comprises:
acquiring a plurality of n 2D NMR spectra, each of said 2D NMR spectra having a ΩTR axis, a Ωτ axis, and a different value of TR; selecting a peak in each of said n NMR spectra, said peak having a peak value along said Ωτ axis, a peak value along said ΩTR axis, and an area A(Ωτ, ΩTR); calculating, for each n, possible frequencies of said peak along said ΩTR axis; and, eliminating results that do not match the peak value of said peak along said Ωτ axis, thereby obtaining ν. 2. The method according to claim 1, wherein said step of calculating, for each n, possible frequencies along the ΩTR axis comprises calculating said possible frequencies by using the relation ν=nTRSWTR n −yn. 3. The method according to claim 1, wherein said step of eliminating results that do not match the peak value of said peak along said Ωτ axis comprises eliminating results that do not match the peak value of said peak along said Ωτ axis by using
Δ
Ω
τ
=
n
τ
×
SW
τ
-
δ
y
TR
1
+
N
TR
SW
τ
/
SW
TR
. 4. The method according to claim 1, further comprising determining the amplitude α of said perturbing electromagnetic signal, said step of determining the amplitude comprising:
calculating φα=1(tτ, tTR); and,
determining said amplitude α from φα=1(tτ, tTR). 5. The method according to claim 4, wherein said step of calculating φα=1(tτ, tTR) comprises calculating φα=1 (tτ, tTR) from
φ
(
t
τ
,
t
TR
)
=
-
4
π
ω
(
sin
(
φ
0
+
ω
x
t
τ
+
ω
t
TR
)
(
1
-
cos
(
ω
t
τ
)
)
,
where ωx=ω(1+NTRΔtTR/Δtτ). 6. The method according to claim 4, wherein said step of determining said amplitude determining said amplitude α from φα=1(tτ, tTR) comprises:
determining A(Ωτ, ΩTR) of said peak;
calculating A(Ωτ, ΩTR)2 of said peak; and,
determining said amplitude α from
α
=
2
×
∑
Ω
TR
,
Ω
τ
A
(
Ω
τ
,
Ω
TR
)
2
/
N
∑
t
TR
,
t
τ
φ
α
=
1
(
t
τ
,
t
TR
)
2
. 7. The method according to claim 1, wherein n=3. 8. The method according to claim 1, wherein:
said step of selecting a peak in each of said n NMR spectra comprises manually selecting a peak; and, said step of determining A(Ωτ, ΩTR) of said peak comprises: manually selecting a region of said spectrum containing said peak, said region having an area A(R); calculating A(R); and, setting A(Ωτ, ΩTR) of said peak to be equal to A(R). 9. The method according to claim 1, wherein said NMR or MRI instrument comprises a permanent magnet and a plurality of pole pieces. 10. The method according to claim 4, wherein n=3. 11. The method according to claim 4, wherein:
said step of selecting a peak in each of said n NMR spectra comprises manually selecting a peak; and, said step of determining A(Ωτ, ΩTR) of said peak comprises: manually selecting a region of said spectrum containing said peak, said region having an area A(R); calculating A(R); and, setting A(Ωτ, ΩTR) of said peak to be equal to A(R). 12. The method according to claim 4, wherein said NMR or MRI instrument comprises a permanent magnet and a plurality of pole pieces. | 2,800 |
11,440 | 11,440 | 13,371,991 | 2,872 | A microscope is described, having an illumination light path for illuminating a sample or object and a viewing light path for viewing the sample. The microscope includes an illumination light path focussing arrangement in the illumination light path, defining a substantially two-dimensional sample or object illumination region extending along an illumination direction of the illumination light path and transversely thereto. The microscope further includes an illumination region-confining device in the illumination light path for selectively illuminating a portion of the substantially two-dimensional object illumination region, wherein the portion of the substantially two-dimensional object illumination region is confined at least in the illumination direction and/or in the direction transversely thereto. | 1. A microscope having an illumination light path for illuminating a sample and at least one viewing light path for viewing the sample, the microscope comprising
an illumination light path focussing arrangement in the illumination light path, the illumination light path focussing arrangement defining a substantially two-dimensional object illumination region extending along an illumination direction of the illumination light path and transversely thereto, and an illumination region-confining device in the illumination light path for selectively illuminating a portion of the substantially two-dimensional object illumination region, wherein the portion of the substantially two-dimensional object illumination region is confined at least in one of the illumination direction and the direction transverse thereto. 2. The microscope of claim 1, wherein the illumination light path focussing arrangement comprises at least one of a cylindrical lens, an anamorphically shaped lens, a one-dimensional array of spherical or of aspherical lenses. 3. The microscope of claim 1, wherein the illumination light path focussing arrangement comprises at least one anamorphically shaped mirror. 4. The microscope of claim 1, wherein the illumination region-confining device comprises at least a first aperture for confining the portion of the substantially two-dimensional object illumination region in the in the illumination direction. 5. The microscope of claim 1, wherein the illumination region confining device comprises at least a second aperture for confining the portion of the substantially two-dimensional object illumination region in a direction transversely to the illumination direction. 6. The microscope of claim 1, wherein the illumination region-confining devices comprises a light beam shaper. 7. The microscope of claim 1, wherein a viewing direction of the at least one viewing light path is substantially perpendicular to the illumination direction and to the substantially two-dimensional object illumination region. 8. The microscope of claim 1, further comprising an adjustable detection aperture in the detection path that allows to reduce an effectively viewed region in one or two dimensions. 9. The microscope of claim 8, wherein the portion of substantially two-dimensional object illumination region and the effectively observed/viewed region are congruent and/or coincident. 10. The microscope of claim 9, wherein the portion of substantially two-dimensional object illumination region and the effectively observed/viewed region are congruently and/or coincidentally moveable through the sample (8). 11. The microscope of claim 1, further comprising an additional objective lens for illumination and viewing of a sample arranged in the sample illumination region. 12. The microscope of claim 11, wherein the additional objective lens is part of an epifluorescence microscope. 13. The microscope of claim 11, wherein the additional objective lens is part of an inverted microscope. 14. A method for detecting a sample, the method comprising:
illuminating a two-dimensional portion of a sample by focussing an illumination light beam into a substantially two-dimensional object illumination region extending in an illumination direction of the illumination light beam and transversely thereto; wherein illuminating the two-dimensional portion further comprises confining the substantially two-dimensional object illumination region for selectively illuminating a portion of the substantially two-dimensional object illumination region, wherein the portion of the substantially two-dimensional object illumination region is confined at least in the illumination direction. 15. The method of claim 14, further comprising viewing the substantially two-dimensional object illumination region in a viewing direction, the viewing direction being substantially perpendicular to the illumination direction. 16. The method of claim 14, further comprising moving at least one of the substantially two-dimensional object illumination region or the portion of the substantially two-dimensional object illumination region through the sample. 17. The method of claim 14, further comprising measuring a signal fluctuation in the portion of the substantially two-dimensional object illumination region. 18. The method of claim 14, further comprising measuring a fluorescence intensity contrast for alignment. | A microscope is described, having an illumination light path for illuminating a sample or object and a viewing light path for viewing the sample. The microscope includes an illumination light path focussing arrangement in the illumination light path, defining a substantially two-dimensional sample or object illumination region extending along an illumination direction of the illumination light path and transversely thereto. The microscope further includes an illumination region-confining device in the illumination light path for selectively illuminating a portion of the substantially two-dimensional object illumination region, wherein the portion of the substantially two-dimensional object illumination region is confined at least in the illumination direction and/or in the direction transversely thereto.1. A microscope having an illumination light path for illuminating a sample and at least one viewing light path for viewing the sample, the microscope comprising
an illumination light path focussing arrangement in the illumination light path, the illumination light path focussing arrangement defining a substantially two-dimensional object illumination region extending along an illumination direction of the illumination light path and transversely thereto, and an illumination region-confining device in the illumination light path for selectively illuminating a portion of the substantially two-dimensional object illumination region, wherein the portion of the substantially two-dimensional object illumination region is confined at least in one of the illumination direction and the direction transverse thereto. 2. The microscope of claim 1, wherein the illumination light path focussing arrangement comprises at least one of a cylindrical lens, an anamorphically shaped lens, a one-dimensional array of spherical or of aspherical lenses. 3. The microscope of claim 1, wherein the illumination light path focussing arrangement comprises at least one anamorphically shaped mirror. 4. The microscope of claim 1, wherein the illumination region-confining device comprises at least a first aperture for confining the portion of the substantially two-dimensional object illumination region in the in the illumination direction. 5. The microscope of claim 1, wherein the illumination region confining device comprises at least a second aperture for confining the portion of the substantially two-dimensional object illumination region in a direction transversely to the illumination direction. 6. The microscope of claim 1, wherein the illumination region-confining devices comprises a light beam shaper. 7. The microscope of claim 1, wherein a viewing direction of the at least one viewing light path is substantially perpendicular to the illumination direction and to the substantially two-dimensional object illumination region. 8. The microscope of claim 1, further comprising an adjustable detection aperture in the detection path that allows to reduce an effectively viewed region in one or two dimensions. 9. The microscope of claim 8, wherein the portion of substantially two-dimensional object illumination region and the effectively observed/viewed region are congruent and/or coincident. 10. The microscope of claim 9, wherein the portion of substantially two-dimensional object illumination region and the effectively observed/viewed region are congruently and/or coincidentally moveable through the sample (8). 11. The microscope of claim 1, further comprising an additional objective lens for illumination and viewing of a sample arranged in the sample illumination region. 12. The microscope of claim 11, wherein the additional objective lens is part of an epifluorescence microscope. 13. The microscope of claim 11, wherein the additional objective lens is part of an inverted microscope. 14. A method for detecting a sample, the method comprising:
illuminating a two-dimensional portion of a sample by focussing an illumination light beam into a substantially two-dimensional object illumination region extending in an illumination direction of the illumination light beam and transversely thereto; wherein illuminating the two-dimensional portion further comprises confining the substantially two-dimensional object illumination region for selectively illuminating a portion of the substantially two-dimensional object illumination region, wherein the portion of the substantially two-dimensional object illumination region is confined at least in the illumination direction. 15. The method of claim 14, further comprising viewing the substantially two-dimensional object illumination region in a viewing direction, the viewing direction being substantially perpendicular to the illumination direction. 16. The method of claim 14, further comprising moving at least one of the substantially two-dimensional object illumination region or the portion of the substantially two-dimensional object illumination region through the sample. 17. The method of claim 14, further comprising measuring a signal fluctuation in the portion of the substantially two-dimensional object illumination region. 18. The method of claim 14, further comprising measuring a fluorescence intensity contrast for alignment. | 2,800 |
11,441 | 11,441 | 14,831,235 | 2,847 | It is an object of the present invention to provide an epoxy resin composition containing an epoxy compound, a low-molecular-weight phenol-modified polyphenylene ether and a cyanate compound as essential components, the epoxy resin composition having excellent dielectric characteristics and exhibiting high heat resistance while maintaining flame retardancy. To achieve this, the epoxy resin composition of the present invention is a thermosetting resin composition composed of a resin varnish containing (A) an epoxy compound having a number-average molecular weight of 1000 or less and containing at least two epoxy groups in the molecule without containing any halogen atoms, (B) a polyphenylene ether having a number-average molecular weight of 5000 or less, (C) a cyanate ester compound, (D) a curing catalyst and (E) a halogen flame retardant, all of the components (A) to (C) are dissolved in the resin varnish, while component (E) is dispersed without being dissolved in the resin varnish. | 1. An epoxy resin composition which is a thermosetting resin composition composed of a resin varnish containing (A) an epoxy compound having a number-average molecular weight of 1000 or less and containing at least two epoxy groups in the molecule without containing any halogen atoms, (B) a polyphenylene ether having a number-average molecular weight of 5000 or less, (C) a cyanate ester compound, (D) a curing catalyst and (E) a halogen flame retardant,
wherein all of the components (A) to (C) are dissolved in the resin varnish, while the component (E) is dispersed without being dissolved in the resin varnish, and said halogen flame retardant (E) is at least one kind selected from the group consisting of ethylene dipentabromobenzene, ethylene bistetrabromoimide, decabromodiphenyl oxide and tetradecabromodiphenoxy benzene. 2. The epoxy resin composition according to claim 1, wherein said halogen flame retardant (E) has a melting point of 300° C. or more. 3. The epoxy resin composition according to claim 1, wherein said epoxy compound (A) is at least one epoxy compound selected from dicyclopentadiene epoxy compounds, bisphenol F epoxy compounds, bisphenol A epoxy compounds and biphenyl epoxy compounds. 4. The epoxy resin composition according to claim 1, wherein said polyphenylene ether (B) is obtained by subjecting a polyphenylene ether with a number-average molecular weight of 10,000 to 30,000 to a redistribution reaction in a solvent in the presence of a phenol compound and a radical initiator. 5. The epoxy resin composition according to claim 1, wherein said curing catalyst (D) contains an organic metal salt. 6. The epoxy resin composition according to claim 1, wherein the epoxy resin composition further contains (F) an inorganic filler. 7. The epoxy resin composition according to claim 6, wherein the inorganic filler (F) is at least one kind selected from the group consisting of spherical silica, aluminum hydroxide and magnesium hydroxide. 8. The epoxy resin composition according to claim 7, wherein the inorganic filler (F) is spherical silica that has been treated with at least one kind of silane coupling agent selected from epoxysilane type silane coupling agents and aminosilane type silane coupling agents. 9. A prepreg comprising a fiber substrate impregnated with the epoxy resin composition according to claim 1. 10. A metal-clad laminate comprising a cured product of the prepreg according to claim 9, and a metal foil laminated on one or both surface(s) of the cured product. 11. A printed wiring board comprising a cured product of the prepreg according to claim 9, and a conductive pattern of circuits formed on a surface of the cured product. | It is an object of the present invention to provide an epoxy resin composition containing an epoxy compound, a low-molecular-weight phenol-modified polyphenylene ether and a cyanate compound as essential components, the epoxy resin composition having excellent dielectric characteristics and exhibiting high heat resistance while maintaining flame retardancy. To achieve this, the epoxy resin composition of the present invention is a thermosetting resin composition composed of a resin varnish containing (A) an epoxy compound having a number-average molecular weight of 1000 or less and containing at least two epoxy groups in the molecule without containing any halogen atoms, (B) a polyphenylene ether having a number-average molecular weight of 5000 or less, (C) a cyanate ester compound, (D) a curing catalyst and (E) a halogen flame retardant, all of the components (A) to (C) are dissolved in the resin varnish, while component (E) is dispersed without being dissolved in the resin varnish.1. An epoxy resin composition which is a thermosetting resin composition composed of a resin varnish containing (A) an epoxy compound having a number-average molecular weight of 1000 or less and containing at least two epoxy groups in the molecule without containing any halogen atoms, (B) a polyphenylene ether having a number-average molecular weight of 5000 or less, (C) a cyanate ester compound, (D) a curing catalyst and (E) a halogen flame retardant,
wherein all of the components (A) to (C) are dissolved in the resin varnish, while the component (E) is dispersed without being dissolved in the resin varnish, and said halogen flame retardant (E) is at least one kind selected from the group consisting of ethylene dipentabromobenzene, ethylene bistetrabromoimide, decabromodiphenyl oxide and tetradecabromodiphenoxy benzene. 2. The epoxy resin composition according to claim 1, wherein said halogen flame retardant (E) has a melting point of 300° C. or more. 3. The epoxy resin composition according to claim 1, wherein said epoxy compound (A) is at least one epoxy compound selected from dicyclopentadiene epoxy compounds, bisphenol F epoxy compounds, bisphenol A epoxy compounds and biphenyl epoxy compounds. 4. The epoxy resin composition according to claim 1, wherein said polyphenylene ether (B) is obtained by subjecting a polyphenylene ether with a number-average molecular weight of 10,000 to 30,000 to a redistribution reaction in a solvent in the presence of a phenol compound and a radical initiator. 5. The epoxy resin composition according to claim 1, wherein said curing catalyst (D) contains an organic metal salt. 6. The epoxy resin composition according to claim 1, wherein the epoxy resin composition further contains (F) an inorganic filler. 7. The epoxy resin composition according to claim 6, wherein the inorganic filler (F) is at least one kind selected from the group consisting of spherical silica, aluminum hydroxide and magnesium hydroxide. 8. The epoxy resin composition according to claim 7, wherein the inorganic filler (F) is spherical silica that has been treated with at least one kind of silane coupling agent selected from epoxysilane type silane coupling agents and aminosilane type silane coupling agents. 9. A prepreg comprising a fiber substrate impregnated with the epoxy resin composition according to claim 1. 10. A metal-clad laminate comprising a cured product of the prepreg according to claim 9, and a metal foil laminated on one or both surface(s) of the cured product. 11. A printed wiring board comprising a cured product of the prepreg according to claim 9, and a conductive pattern of circuits formed on a surface of the cured product. | 2,800 |
11,442 | 11,442 | 15,374,154 | 2,846 | Methods and apparatus for controlling a three-phase motor and providing sinusoidal phase currents during startup. In embodiments, differential outputs from a magnetic field sensing element are used to generate a polarity signal used to provide a motor direction drive signal. An amplitude signal derived from the magnetic field sensing element and a measured motor current are used to generate a current amplitude signal. A PWM module generates signals for driving the motor with sinusoidal phase currents from the current amplitude signal and the motor direction drive signal. | 1. A method for three-phase motor startup, comprising:
receiving differential outputs from a magnetic field sensing element; generating a polarity signal from the differential outputs; receiving the differential outputs and generating an amplitude signal; generating a motor direction drive signal from the polarity signal; and generating sinusoidal motor drive signals during the motor startup from a measured motor current signal and the amplitude signal, wherein the motor drive signals drive the motor in a direction corresponding to the motor direction drive signal. 2. The method according to claim 1, wherein the magnetic field sensing element comprises a Hall element. 3. The method according to claim 1, wherein the sinusoidal motor drive signals during motor startup are generated from a single Hall element, which comprises the magnetic field sensing element. 4. The method according to claim 3, wherein the motor direction drive signal corresponds to a position of the signal Hall element in relation to phases of the motor. 5. The method according to claim 1, wherein the magnetic field sensing element comprises an anisotropic magnetoresistance (AMR) element. 6. The method according to claim 1, wherein the magnetic field sensing element comprises a giant magnetoresistance (GMR) element. 7. The method according to claim 1, wherein the magnetic field sensing element comprises a tunneling magnetoresistance (TMR) element. 8. The method according to claim 1, further including using a comparator to generate the polarity signal. 9. The method according to claim 1, further including rectifying the differential outputs to generating the amplitude signal. 10. The method according to claim 1, further including using a proportional-integral (PI) controller to generate a control vector amplitude signal for a PWM signal generator from the amplitude signal and the measured motor current. 11. The method according to claim 1, wherein the motor comprises a brushless DC motor. 12. A motor controller system comprising:
a control module configured to receive polarity information generated from differential outputs that are output by a magnetic field sensing element positioned in relation to phases of a three-phase motor and amplitude information generated from the differential outputs that are output by the magnetic field sensing element, the control module configured to generate a motor driving direction signal corresponding to the received polarity information and to generate an amplitude control signal from the amplitude information and a measured motor current information; and a pulse width modulation (PWM) module configured to receive the amplitude control signal and the motor driving direction signal and generate control signals for switching elements driving the motor that provide sinusoidal phase currents to the motor during startup, wherein the motor drive signals drive the motor in a direction corresponding to the motor direction drive signal. 13. The system according to claim 12, wherein the magnetic field sensing element comprises a Hall element. 14. The system according to claim 12, wherein the sinusoidal motor drive signals during motor startup are generated from a single Hall element, which comprises the magnetic field sensing element. 15. The system according to claim 14, wherein the motor direction drive signal corresponds to a position of the signal Hall element in relation to phases of the motor. 16. The system according to claim 12, further including a comparator to generate the polarity signal. 17. The system according to claim 12, further including rectifying the differential outputs to generating the amplitude signal. 18. The system according to claim 12, further including a proportional-integral (PI) controller to generate a control vector amplitude signal for a PWM signal generator from the amplitude signal and the measured motor current. 19. The system according to claim 12, wherein the motor comprises a brushless DC motor. 20. The system according to claim 12, wherein the magnetic field sensing element comprises an anisotropic magnetoresistance (AMR) element. 21. The system according to claim 12, wherein the magnetic field sensing element comprises a giant magnetoresistance (GMR) element. 22. The system according to claim 12, wherein the magnetic field sensing element comprises a tunneling magnetoresistance (TMR) element. 23. A motor controller system comprising:
a control means for receiving polarity information generated from differential outputs that are output by a magnetic field sensing element positioned in relation to phases of a three-phase motor and amplitude information generated from the differential outputs that are output by the magnetic field sensing element, and to generate a motor driving direction signal corresponding to the received polarity information and to generate an amplitude control signal from the amplitude information and the motor current information; and a pulse width modulation (PWM) means for receiving the amplitude control signal and the motor driving direction signal and generate control signals for switching elements driving the motor that provide sinusoidal phase currents to the motor during startup, wherein the motor drive signals drive the motor in a direction corresponding to the motor direction drive signal. 24. The system according to claim 23, wherein the magnetic field sensing element comprises a Hall element. 25. The system according to claim 23, wherein the sinusoidal motor drive signals during motor startup are generated from a single Hall element, which comprises the magnetic field sensing element. 26. The system according to claim 25, wherein the motor direction drive signal corresponds to a position of the signal Hall element in relation to phases of the motor. 27. The system according to claim 23, further including a rectifier coupled to the differential outputs to generate the amplitude signal. 28. The system according to claim 23, further including a proportional-integral (PI) controller means for generating a control vector amplitude signal for a PWM signal generator from the amplitude signal and the measured motor current. 29. The system according to claim 23, wherein the motor comprises a brushless DC motor. 30. The system according to claim 23, wherein the magnetic field sensing element comprises an anisotropic magnetoresistance (AMR) element. 31. The system according to claim 23, wherein the magnetic field sensing element comprises a giant magnetoresistance (GMR) element. 32. The system according to claim 23, wherein the magnetic field sensing element comprises a tunneling magnetoresistance (TMR) element. | Methods and apparatus for controlling a three-phase motor and providing sinusoidal phase currents during startup. In embodiments, differential outputs from a magnetic field sensing element are used to generate a polarity signal used to provide a motor direction drive signal. An amplitude signal derived from the magnetic field sensing element and a measured motor current are used to generate a current amplitude signal. A PWM module generates signals for driving the motor with sinusoidal phase currents from the current amplitude signal and the motor direction drive signal.1. A method for three-phase motor startup, comprising:
receiving differential outputs from a magnetic field sensing element; generating a polarity signal from the differential outputs; receiving the differential outputs and generating an amplitude signal; generating a motor direction drive signal from the polarity signal; and generating sinusoidal motor drive signals during the motor startup from a measured motor current signal and the amplitude signal, wherein the motor drive signals drive the motor in a direction corresponding to the motor direction drive signal. 2. The method according to claim 1, wherein the magnetic field sensing element comprises a Hall element. 3. The method according to claim 1, wherein the sinusoidal motor drive signals during motor startup are generated from a single Hall element, which comprises the magnetic field sensing element. 4. The method according to claim 3, wherein the motor direction drive signal corresponds to a position of the signal Hall element in relation to phases of the motor. 5. The method according to claim 1, wherein the magnetic field sensing element comprises an anisotropic magnetoresistance (AMR) element. 6. The method according to claim 1, wherein the magnetic field sensing element comprises a giant magnetoresistance (GMR) element. 7. The method according to claim 1, wherein the magnetic field sensing element comprises a tunneling magnetoresistance (TMR) element. 8. The method according to claim 1, further including using a comparator to generate the polarity signal. 9. The method according to claim 1, further including rectifying the differential outputs to generating the amplitude signal. 10. The method according to claim 1, further including using a proportional-integral (PI) controller to generate a control vector amplitude signal for a PWM signal generator from the amplitude signal and the measured motor current. 11. The method according to claim 1, wherein the motor comprises a brushless DC motor. 12. A motor controller system comprising:
a control module configured to receive polarity information generated from differential outputs that are output by a magnetic field sensing element positioned in relation to phases of a three-phase motor and amplitude information generated from the differential outputs that are output by the magnetic field sensing element, the control module configured to generate a motor driving direction signal corresponding to the received polarity information and to generate an amplitude control signal from the amplitude information and a measured motor current information; and a pulse width modulation (PWM) module configured to receive the amplitude control signal and the motor driving direction signal and generate control signals for switching elements driving the motor that provide sinusoidal phase currents to the motor during startup, wherein the motor drive signals drive the motor in a direction corresponding to the motor direction drive signal. 13. The system according to claim 12, wherein the magnetic field sensing element comprises a Hall element. 14. The system according to claim 12, wherein the sinusoidal motor drive signals during motor startup are generated from a single Hall element, which comprises the magnetic field sensing element. 15. The system according to claim 14, wherein the motor direction drive signal corresponds to a position of the signal Hall element in relation to phases of the motor. 16. The system according to claim 12, further including a comparator to generate the polarity signal. 17. The system according to claim 12, further including rectifying the differential outputs to generating the amplitude signal. 18. The system according to claim 12, further including a proportional-integral (PI) controller to generate a control vector amplitude signal for a PWM signal generator from the amplitude signal and the measured motor current. 19. The system according to claim 12, wherein the motor comprises a brushless DC motor. 20. The system according to claim 12, wherein the magnetic field sensing element comprises an anisotropic magnetoresistance (AMR) element. 21. The system according to claim 12, wherein the magnetic field sensing element comprises a giant magnetoresistance (GMR) element. 22. The system according to claim 12, wherein the magnetic field sensing element comprises a tunneling magnetoresistance (TMR) element. 23. A motor controller system comprising:
a control means for receiving polarity information generated from differential outputs that are output by a magnetic field sensing element positioned in relation to phases of a three-phase motor and amplitude information generated from the differential outputs that are output by the magnetic field sensing element, and to generate a motor driving direction signal corresponding to the received polarity information and to generate an amplitude control signal from the amplitude information and the motor current information; and a pulse width modulation (PWM) means for receiving the amplitude control signal and the motor driving direction signal and generate control signals for switching elements driving the motor that provide sinusoidal phase currents to the motor during startup, wherein the motor drive signals drive the motor in a direction corresponding to the motor direction drive signal. 24. The system according to claim 23, wherein the magnetic field sensing element comprises a Hall element. 25. The system according to claim 23, wherein the sinusoidal motor drive signals during motor startup are generated from a single Hall element, which comprises the magnetic field sensing element. 26. The system according to claim 25, wherein the motor direction drive signal corresponds to a position of the signal Hall element in relation to phases of the motor. 27. The system according to claim 23, further including a rectifier coupled to the differential outputs to generate the amplitude signal. 28. The system according to claim 23, further including a proportional-integral (PI) controller means for generating a control vector amplitude signal for a PWM signal generator from the amplitude signal and the measured motor current. 29. The system according to claim 23, wherein the motor comprises a brushless DC motor. 30. The system according to claim 23, wherein the magnetic field sensing element comprises an anisotropic magnetoresistance (AMR) element. 31. The system according to claim 23, wherein the magnetic field sensing element comprises a giant magnetoresistance (GMR) element. 32. The system according to claim 23, wherein the magnetic field sensing element comprises a tunneling magnetoresistance (TMR) element. | 2,800 |
11,443 | 11,443 | 15,246,159 | 2,844 | There is provided a lighting device comprising an exhaust tube and a wireless communication antenna arranged inside the exhaust tube. There is also provided a method for producing such a lighting device. | 1. A lighting device comprising
an exhaust tube and a wireless communication antenna arranged inside the exhaust tube. 2. The lighting device according to claim 1, wherein an outer portion of the antenna protrudes from an open end of the exhaust tube. 3. The lighting device according to claim 2, wherein the outer portion of the antenna extends straight along the exhaust tube. 4. The lighting device according to claim 2, wherein the outer portion of the antenna is wound around the exhaust tube. 5. The lighting device according to claim 2, further comprising a support structure supporting the outer portion of the antenna at a distance from the exhaust tube. 6. The lighting device according to claim 1, further comprising
a tubular light source carrier attached to the exhaust tube, the exhaust tube being arranged partly inside the tubular light source carrier. 7. The lighting device according to claim 6, wherein an open end of the exhaust tube is situated inside the tubular light source carrier. 8. The lighting device according to claim 6, wherein the exhaust tube extends throughout the entire tubular light source carrier so that an open end of the exhaust tube is outside the tubular light source carrier. 9. The lighting device according to claim 6, wherein the tubular light source carrier is adapted to act as a radiator, an electrical resonance frequency of the tubular light source carrier being approximately equal to a receiving frequency of the antenna. 10. The lighting device according to claim 6, further comprising:
a connector for mechanically and electrically connecting the lighting device to a lamp socket; a light source carrier having one or more solid state light sources; a light transmissive envelope, the light source carrier and the exhaust tube being arranged inside the envelope; a driver configured to power the one or more solid state light sources; and a control circuit electrically connected to the antenna and configured to control the one or more solid state light sources. 11. The lighting device according to claim 10, wherein the control circuit is positioned completely inside the envelope. 12. The lighting device according to claim 10, further comprising at least one of a light scattering layer and a wavelength converting layer. 13. The lighting device according to claim 10, wherein the lighting device is a gas filled light bulb. 14. A method for producing a lighting device, comprising
arranging an antenna inside an exhaust tube of the lighting device. 15. The method according to claim 14, further comprising
forming an airtight connection between the antenna and the exhaust tube. | There is provided a lighting device comprising an exhaust tube and a wireless communication antenna arranged inside the exhaust tube. There is also provided a method for producing such a lighting device.1. A lighting device comprising
an exhaust tube and a wireless communication antenna arranged inside the exhaust tube. 2. The lighting device according to claim 1, wherein an outer portion of the antenna protrudes from an open end of the exhaust tube. 3. The lighting device according to claim 2, wherein the outer portion of the antenna extends straight along the exhaust tube. 4. The lighting device according to claim 2, wherein the outer portion of the antenna is wound around the exhaust tube. 5. The lighting device according to claim 2, further comprising a support structure supporting the outer portion of the antenna at a distance from the exhaust tube. 6. The lighting device according to claim 1, further comprising
a tubular light source carrier attached to the exhaust tube, the exhaust tube being arranged partly inside the tubular light source carrier. 7. The lighting device according to claim 6, wherein an open end of the exhaust tube is situated inside the tubular light source carrier. 8. The lighting device according to claim 6, wherein the exhaust tube extends throughout the entire tubular light source carrier so that an open end of the exhaust tube is outside the tubular light source carrier. 9. The lighting device according to claim 6, wherein the tubular light source carrier is adapted to act as a radiator, an electrical resonance frequency of the tubular light source carrier being approximately equal to a receiving frequency of the antenna. 10. The lighting device according to claim 6, further comprising:
a connector for mechanically and electrically connecting the lighting device to a lamp socket; a light source carrier having one or more solid state light sources; a light transmissive envelope, the light source carrier and the exhaust tube being arranged inside the envelope; a driver configured to power the one or more solid state light sources; and a control circuit electrically connected to the antenna and configured to control the one or more solid state light sources. 11. The lighting device according to claim 10, wherein the control circuit is positioned completely inside the envelope. 12. The lighting device according to claim 10, further comprising at least one of a light scattering layer and a wavelength converting layer. 13. The lighting device according to claim 10, wherein the lighting device is a gas filled light bulb. 14. A method for producing a lighting device, comprising
arranging an antenna inside an exhaust tube of the lighting device. 15. The method according to claim 14, further comprising
forming an airtight connection between the antenna and the exhaust tube. | 2,800 |
11,444 | 11,444 | 15,321,878 | 2,833 | An electric wire with terminal ( 1 ) includes an electric wire (W) and a terminal (T) electrically connected to the electric wire. The electric wire with terminal includes at least one selected from a group consisting of: a first anti-corrosion structure configured to provide a ceramic layer ( 40 ) having a thickness from 1 μm to 200 μm so as to internally contain a connection part of a conductor ( 10 ) of the electric wire and the terminal; and a second anti-corrosion structure configured to connect the conductor ( 10 ) of the electric wire and the terminal (T) through a conductive ceramic layer having a thickness from 1 μm to 200 μm. | 1. An electric wire with terminal comprising an electric wire and a terminal electrically connected to the electric wire,
the electric wire with terminal including at least one selected from a group consisting of: a first anti-corrosion structure configured to provide a ceramic layer having a thickness from 1 μm to 200 μm so as to internally contain a connection part of a conductor of the electric wire and the terminal; and a second anti-corrosion structure configured to connect the conductor of the electric wire and the terminal through a conductive ceramic layer having a thickness from 1 μm to 200 μm. | An electric wire with terminal ( 1 ) includes an electric wire (W) and a terminal (T) electrically connected to the electric wire. The electric wire with terminal includes at least one selected from a group consisting of: a first anti-corrosion structure configured to provide a ceramic layer ( 40 ) having a thickness from 1 μm to 200 μm so as to internally contain a connection part of a conductor ( 10 ) of the electric wire and the terminal; and a second anti-corrosion structure configured to connect the conductor ( 10 ) of the electric wire and the terminal (T) through a conductive ceramic layer having a thickness from 1 μm to 200 μm.1. An electric wire with terminal comprising an electric wire and a terminal electrically connected to the electric wire,
the electric wire with terminal including at least one selected from a group consisting of: a first anti-corrosion structure configured to provide a ceramic layer having a thickness from 1 μm to 200 μm so as to internally contain a connection part of a conductor of the electric wire and the terminal; and a second anti-corrosion structure configured to connect the conductor of the electric wire and the terminal through a conductive ceramic layer having a thickness from 1 μm to 200 μm. | 2,800 |
11,445 | 11,445 | 14,466,923 | 2,892 | A semiconductor device has a leadframe with a plurality of bodies extending from the base plate. A first semiconductor die is mounted to the base plate of the leadframe between the bodies. An encapsulant is deposited over the first semiconductor die and base plate and around the bodies of the leadframe. A portion of the encapsulant over the bodies of the leadframe is removed to form first openings in the encapsulant that expose the bodies. An interconnect structure is formed over the encapsulant and extending into the first openings to the bodies of the leadframe. The leadframe and bodies are removed to form second openings in the encapsulant corresponding to space previously occupied by the bodies to expose the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with bumps extending into the second openings of the encapsulant to electrically connect to the interconnect structure. | 1. A semiconductor device, comprising:
a substrate; a semiconductor die disposed over the substrate; an encapsulant formed over the substrate and semiconductor die; a first opening formed in the encapsulant extending to the substrate; a first conductive layer formed in the opening; and a first insulating layer formed in the opening. 2. The semiconductor device of claim 1, wherein the substrate includes a base plate with a plurality of portions extending from the base plate. 3. The semiconductor device of claim 1, further including a second opening formed in the encapsulant and extending to the semiconductor die. 4. The semiconductor device of claim 3, further including the first conductive layer formed in the second opening. 5. The semiconductor device of claim 1, further including a second conductive layer formed over the first conductive layer. 6. The semiconductor device of claim 1, further including a conductive via formed through the semiconductor die. 7. A semiconductor device, comprising:
a first semiconductor die; an encapsulant deposited over the first semiconductor die; a first conductive layer formed partially through the encapsulant; an insulating layer formed over the first conductive layer and partially through the encapsulant; and an opening formed in the encapsulant extending to the first conductive layer. 8. The semiconductor device of claim 7, further including a substrate disposed over the first semiconductor die and within the opening in the encapsulant. 9. The semiconductor device of claim 7, further including a second semiconductor die disposed over the first semiconductor die. 10. The semiconductor device of claim 9, further including a third semiconductor die disposed over the second semiconductor die. 11. The semiconductor device of claim 7, further including an interconnect structure formed in the opening. 12. The semiconductor device of claim 11, wherein the interconnect structure includes a bump. 13. The semiconductor device of claim 7, further including a heat spreader or shielding layer formed over the semiconductor die. 14. A semiconductor device, comprising:
a first semiconductor die; an encapsulant deposited over the first semiconductor die; a first conductive layer formed partially through the encapsulant; and an insulating layer formed partially through the encapsulant. 15. The semiconductor device of claim 14, further including an opening formed in the encapsulant and extending to the first conductive layer. 16. The semiconductor device of claim 15, further including a second conductive layer conformally applied over a surface of the encapsulant and within the opening. 17. The semiconductor device of claim 15, further including a substrate disposed over the first semiconductor die and within the opening in the encapsulant. 18. The semiconductor device of claim 14, further including a second semiconductor die disposed over the first semiconductor die. 19. The semiconductor device of claim 14, further including an interconnect structure formed over the first conductive layer. 20. The semiconductor device of claim 19, wherein the interconnect structure includes a bump. 21. A semiconductor device, comprising:
a first semiconductor die; an encapsulant deposited over the first semiconductor die; a first conductive layer formed through the encapsulant; and an opening formed in the encapsulant and extending to the first conductive layer. 22. The semiconductor device of claim 21, further including a second semiconductor die disposed over the first semiconductor die. 23. The semiconductor device of claim 21, further including a substrate disposed over the first semiconductor die and within the opening in the encapsulant. 24. The semiconductor device of claim 21, further including an interconnect structure formed in the opening. 25. The semiconductor device of claim 21, further including a conductive via formed through the first semiconductor die. | A semiconductor device has a leadframe with a plurality of bodies extending from the base plate. A first semiconductor die is mounted to the base plate of the leadframe between the bodies. An encapsulant is deposited over the first semiconductor die and base plate and around the bodies of the leadframe. A portion of the encapsulant over the bodies of the leadframe is removed to form first openings in the encapsulant that expose the bodies. An interconnect structure is formed over the encapsulant and extending into the first openings to the bodies of the leadframe. The leadframe and bodies are removed to form second openings in the encapsulant corresponding to space previously occupied by the bodies to expose the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with bumps extending into the second openings of the encapsulant to electrically connect to the interconnect structure.1. A semiconductor device, comprising:
a substrate; a semiconductor die disposed over the substrate; an encapsulant formed over the substrate and semiconductor die; a first opening formed in the encapsulant extending to the substrate; a first conductive layer formed in the opening; and a first insulating layer formed in the opening. 2. The semiconductor device of claim 1, wherein the substrate includes a base plate with a plurality of portions extending from the base plate. 3. The semiconductor device of claim 1, further including a second opening formed in the encapsulant and extending to the semiconductor die. 4. The semiconductor device of claim 3, further including the first conductive layer formed in the second opening. 5. The semiconductor device of claim 1, further including a second conductive layer formed over the first conductive layer. 6. The semiconductor device of claim 1, further including a conductive via formed through the semiconductor die. 7. A semiconductor device, comprising:
a first semiconductor die; an encapsulant deposited over the first semiconductor die; a first conductive layer formed partially through the encapsulant; an insulating layer formed over the first conductive layer and partially through the encapsulant; and an opening formed in the encapsulant extending to the first conductive layer. 8. The semiconductor device of claim 7, further including a substrate disposed over the first semiconductor die and within the opening in the encapsulant. 9. The semiconductor device of claim 7, further including a second semiconductor die disposed over the first semiconductor die. 10. The semiconductor device of claim 9, further including a third semiconductor die disposed over the second semiconductor die. 11. The semiconductor device of claim 7, further including an interconnect structure formed in the opening. 12. The semiconductor device of claim 11, wherein the interconnect structure includes a bump. 13. The semiconductor device of claim 7, further including a heat spreader or shielding layer formed over the semiconductor die. 14. A semiconductor device, comprising:
a first semiconductor die; an encapsulant deposited over the first semiconductor die; a first conductive layer formed partially through the encapsulant; and an insulating layer formed partially through the encapsulant. 15. The semiconductor device of claim 14, further including an opening formed in the encapsulant and extending to the first conductive layer. 16. The semiconductor device of claim 15, further including a second conductive layer conformally applied over a surface of the encapsulant and within the opening. 17. The semiconductor device of claim 15, further including a substrate disposed over the first semiconductor die and within the opening in the encapsulant. 18. The semiconductor device of claim 14, further including a second semiconductor die disposed over the first semiconductor die. 19. The semiconductor device of claim 14, further including an interconnect structure formed over the first conductive layer. 20. The semiconductor device of claim 19, wherein the interconnect structure includes a bump. 21. A semiconductor device, comprising:
a first semiconductor die; an encapsulant deposited over the first semiconductor die; a first conductive layer formed through the encapsulant; and an opening formed in the encapsulant and extending to the first conductive layer. 22. The semiconductor device of claim 21, further including a second semiconductor die disposed over the first semiconductor die. 23. The semiconductor device of claim 21, further including a substrate disposed over the first semiconductor die and within the opening in the encapsulant. 24. The semiconductor device of claim 21, further including an interconnect structure formed in the opening. 25. The semiconductor device of claim 21, further including a conductive via formed through the first semiconductor die. | 2,800 |
11,446 | 11,446 | 15,427,123 | 2,848 | A multilayer ceramic capacitor includes a capacitor body including a first internal electrode laminated portion in which three or more first internal electrodes are laminated in a laminating direction, and a second internal electrode laminated portion in which three or more second internal electrodes are laminated in the laminating direction. The second internal electrode laminated portion is opposite to the first internal electrode laminated portion in the laminating direction. | 1. A multilayer ceramic capacitor comprising:
a capacitor body including first and second principal surfaces extending in a length direction and a width direction, first and second lateral surfaces extending in the length direction and a laminating direction, and first and second end surfaces extending in the width direction and the laminating direction; a first external electrode disposed on at least one surface of the first and second lateral surfaces and the first and second end surfaces; a second external electrode disposed on at least one surface of the first and second lateral surfaces and the first and second end surfaces, the second external electrode being disposed at a position different from a position where the first external electrode is disposed; a first internal electrode disposed inside the capacitor body and connected with the first external electrode; and a second internal electrode disposed inside the capacitor body and connected with the second external electrode; wherein the capacitor body includes:
a first internal electrode laminated portion in which three or more first internal electrodes are sequentially laminated in the laminating direction; and
a second internal electrode laminated portion in which three or more second internal electrodes are sequentially laminated in the laminating direction; wherein
the second internal electrode laminated portion is opposite to the first internal electrode laminated portion in the laminating direction. 2. The multilayer ceramic capacitor according to claim 1, wherein
the capacitor body includes a plurality of the first internal electrode laminated portions and a plurality of the second internal electrode laminated portions; a distance between the first internal electrode laminated portions adjacent in the laminating direction divided by a sum of thicknesses of the second internal electrodes and a distance between the second internal electrodes adjacent in the laminating direction is 25 or less; and a distance between the second internal electrode laminated portions adjacent in the laminating direction divided by a sum of thicknesses of the first internal electrodes and a distance between the first internal electrodes adjacent in the laminating direction is 25 or less. 3. The multilayer ceramic capacitor according to claim 1, wherein
the capacitor body includes a plurality of the first internal electrode laminated portions and a plurality of the second internal electrode laminated portions; each of a distance between the first internal electrode laminated portions adjacent in the laminating direction, and a distance between the second internal electrode laminated portions adjacent in the laminating direction is about 31 μm or less. 4. The multilayer ceramic capacitor according to claim 1, wherein the capacitor body includes an alternate laminated portion in which the first internal electrode and the second internal electrode are alternately laminated in the laminating direction. 5. The multilayer ceramic capacitor according to claim 1, wherein the external electrode to which the internal electrode disposed closest to the first principal surface in the capacitor body is connected is different from the external electrode to which the internal electrode adjacent in the laminating direction is connected. 6. The multilayer ceramic capacitor according to claim 1, wherein the external electrode to which the internal electrode disposed closest to the second principal surface in the capacitor body is connected is different from the external electrode to which the internal electrode adjacent in the laminating direction is connected. 7. The multilayer ceramic capacitor according to claim 1, wherein the capacitor body includes a portion where the first internal electrode laminated portion and the second internal electrode laminated portion are alternately laminated and include a total of eleven or more layers. 8. The multilayer ceramic capacitor according to claim 1, wherein the capacitor body has a rectangular or substantially rectangular parallelepiped shape. 9. The multilayer ceramic capacitor according to claim 1, wherein ridges or corners of the capacitor body have chamfered or rounded shapes. 10. The multilayer ceramic capacitor according to claim 1, wherein three of the first external electrode are provided on the capacitor body, and three of the second external electrode are provided on the capacitor body. 11. The multilayer ceramic capacitor according to claim 10, wherein each of the first external electrodes and each of the three second external electrodes is U-shaped or substantially U-shaped. 12. The multilayer ceramic capacitor according to claim 10, wherein each of the first external electrodes and each of the three second external electrodes includes a base electrode layer disposed on the capacitor body, a Ni plating layer disposed on the base electrode layer, and a Sn plating layer disposed on the Ni plating layer. 13. The multilayer ceramic capacitor according to claim 1, wherein
the capacitor body includes a plurality of the first internal electrode laminated portions and a plurality of the second internal electrode laminated portions; a distance between the first internal electrode laminated portions adjacent in the laminating direction divided by a sum of thicknesses of the second internal electrodes and a distance between the second internal electrodes adjacent in the laminating direction is 8 or less; and a distance between the second internal electrode laminated portions adjacent in the laminating direction divided by a sum of thicknesses of the first internal electrodes and a distance between the first internal electrodes adjacent in the laminating direction is 8 or less. 14. The multilayer ceramic capacitor according to claim 1, wherein
the capacitor body includes a plurality of the first internal electrode laminated portions and a plurality of the second internal electrode laminated portions; each of a distance between the first internal electrode laminated portions adjacent in the laminating direction, and a distance between the second internal electrode laminated portions adjacent in the laminating direction is about 26 μm or less. 15. The multilayer ceramic capacitor according to claim 1, wherein
the capacitor body includes a plurality of the first internal electrode laminated portions and a plurality of the second internal electrode laminated portions; each of a distance between the first internal electrode laminated portions adjacent in the laminating direction, and a distance between the second internal electrode laminated portions adjacent in the laminating direction is about 18 μm or less. | A multilayer ceramic capacitor includes a capacitor body including a first internal electrode laminated portion in which three or more first internal electrodes are laminated in a laminating direction, and a second internal electrode laminated portion in which three or more second internal electrodes are laminated in the laminating direction. The second internal electrode laminated portion is opposite to the first internal electrode laminated portion in the laminating direction.1. A multilayer ceramic capacitor comprising:
a capacitor body including first and second principal surfaces extending in a length direction and a width direction, first and second lateral surfaces extending in the length direction and a laminating direction, and first and second end surfaces extending in the width direction and the laminating direction; a first external electrode disposed on at least one surface of the first and second lateral surfaces and the first and second end surfaces; a second external electrode disposed on at least one surface of the first and second lateral surfaces and the first and second end surfaces, the second external electrode being disposed at a position different from a position where the first external electrode is disposed; a first internal electrode disposed inside the capacitor body and connected with the first external electrode; and a second internal electrode disposed inside the capacitor body and connected with the second external electrode; wherein the capacitor body includes:
a first internal electrode laminated portion in which three or more first internal electrodes are sequentially laminated in the laminating direction; and
a second internal electrode laminated portion in which three or more second internal electrodes are sequentially laminated in the laminating direction; wherein
the second internal electrode laminated portion is opposite to the first internal electrode laminated portion in the laminating direction. 2. The multilayer ceramic capacitor according to claim 1, wherein
the capacitor body includes a plurality of the first internal electrode laminated portions and a plurality of the second internal electrode laminated portions; a distance between the first internal electrode laminated portions adjacent in the laminating direction divided by a sum of thicknesses of the second internal electrodes and a distance between the second internal electrodes adjacent in the laminating direction is 25 or less; and a distance between the second internal electrode laminated portions adjacent in the laminating direction divided by a sum of thicknesses of the first internal electrodes and a distance between the first internal electrodes adjacent in the laminating direction is 25 or less. 3. The multilayer ceramic capacitor according to claim 1, wherein
the capacitor body includes a plurality of the first internal electrode laminated portions and a plurality of the second internal electrode laminated portions; each of a distance between the first internal electrode laminated portions adjacent in the laminating direction, and a distance between the second internal electrode laminated portions adjacent in the laminating direction is about 31 μm or less. 4. The multilayer ceramic capacitor according to claim 1, wherein the capacitor body includes an alternate laminated portion in which the first internal electrode and the second internal electrode are alternately laminated in the laminating direction. 5. The multilayer ceramic capacitor according to claim 1, wherein the external electrode to which the internal electrode disposed closest to the first principal surface in the capacitor body is connected is different from the external electrode to which the internal electrode adjacent in the laminating direction is connected. 6. The multilayer ceramic capacitor according to claim 1, wherein the external electrode to which the internal electrode disposed closest to the second principal surface in the capacitor body is connected is different from the external electrode to which the internal electrode adjacent in the laminating direction is connected. 7. The multilayer ceramic capacitor according to claim 1, wherein the capacitor body includes a portion where the first internal electrode laminated portion and the second internal electrode laminated portion are alternately laminated and include a total of eleven or more layers. 8. The multilayer ceramic capacitor according to claim 1, wherein the capacitor body has a rectangular or substantially rectangular parallelepiped shape. 9. The multilayer ceramic capacitor according to claim 1, wherein ridges or corners of the capacitor body have chamfered or rounded shapes. 10. The multilayer ceramic capacitor according to claim 1, wherein three of the first external electrode are provided on the capacitor body, and three of the second external electrode are provided on the capacitor body. 11. The multilayer ceramic capacitor according to claim 10, wherein each of the first external electrodes and each of the three second external electrodes is U-shaped or substantially U-shaped. 12. The multilayer ceramic capacitor according to claim 10, wherein each of the first external electrodes and each of the three second external electrodes includes a base electrode layer disposed on the capacitor body, a Ni plating layer disposed on the base electrode layer, and a Sn plating layer disposed on the Ni plating layer. 13. The multilayer ceramic capacitor according to claim 1, wherein
the capacitor body includes a plurality of the first internal electrode laminated portions and a plurality of the second internal electrode laminated portions; a distance between the first internal electrode laminated portions adjacent in the laminating direction divided by a sum of thicknesses of the second internal electrodes and a distance between the second internal electrodes adjacent in the laminating direction is 8 or less; and a distance between the second internal electrode laminated portions adjacent in the laminating direction divided by a sum of thicknesses of the first internal electrodes and a distance between the first internal electrodes adjacent in the laminating direction is 8 or less. 14. The multilayer ceramic capacitor according to claim 1, wherein
the capacitor body includes a plurality of the first internal electrode laminated portions and a plurality of the second internal electrode laminated portions; each of a distance between the first internal electrode laminated portions adjacent in the laminating direction, and a distance between the second internal electrode laminated portions adjacent in the laminating direction is about 26 μm or less. 15. The multilayer ceramic capacitor according to claim 1, wherein
the capacitor body includes a plurality of the first internal electrode laminated portions and a plurality of the second internal electrode laminated portions; each of a distance between the first internal electrode laminated portions adjacent in the laminating direction, and a distance between the second internal electrode laminated portions adjacent in the laminating direction is about 18 μm or less. | 2,800 |
11,447 | 11,447 | 13,835,760 | 2,863 | A battery pack monitoring apparatus is provided. The apparatus includes a voltage measurement system configured to couple to opposed ends of each of a plurality of blocks of a battery pack and to measure voltages thereof, the blocks being coupled in series by interconnects each having an interconnect resistance. The voltage measurement system is configured to derive an internal resistance of each of the plurality of blocks based upon the voltages of the opposed ends of each of the plurality of blocks and based upon a measurement of current of the battery pack and derive the interconnect resistance of each of the interconnects based upon the voltages of the opposed ends of each of the plurality of blocks and based upon the measurement of current. | 1. A battery pack monitoring apparatus, comprising:
a voltage measurement system configured to couple to opposed ends of each of a plurality of blocks of a battery pack and to measure voltages thereof, the blocks being coupled in series by interconnects each having an interconnect resistance; and the voltage measurement system being further configured to:
derive an internal resistance of each of the plurality of blocks based upon the voltages of the opposed ends of each of the plurality of blocks and based upon a measurement of current of the battery pack; and
derive the interconnect resistance of each of the interconnects based upon the voltages of the opposed ends of each of the plurality of blocks and based upon the measurement of current. 2. The battery pack monitoring apparatus of claim 1, wherein a plurality of the voltages of the opposed ends of each of the plurality of blocks are applied as voltages of a higher end and a lower end, respectively, of each of the interconnects. 3. The battery pack monitoring apparatus of claim 1, wherein each of the plurality of blocks has one or more cells in parallel. 4. The battery pack monitoring apparatus of claim 1, further comprising:
a current sensor configured coupled to the battery pack and to provide the measurement of current. 5. The battery pack monitoring apparatus of claim 1, wherein the voltage measurement system includes:
a first voltage measurement unit configured to couple to a negative terminal of a battery pack and to a first end of each of the opposed ends of each of the plurality of blocks; and a second voltage measurement unit configured to couple to a second end of each of the opposed ends of each of the plurality of blocks and to the positive terminal of the battery pack. 6. The battery pack monitoring apparatus of claim 1, comprising the voltage measurement system being further configured to estimate the current of the battery pack based upon the voltages of the opposed ends of each of the plurality of blocks and based upon the derived internal resistance of two of the interconnects. 7. A battery pack monitoring apparatus, comprising:
a first voltage measurement unit configured to couple to a negative terminal of a battery pack, to a positive terminal of the battery pack, and to a first end of each of a plurality of block interconnects of the battery pack; a second voltage measurement unit configured to couple to the negative terminal of the battery pack, to the positive terminal of the battery pack, and to a second end of each of the plurality of block interconnects; and the first voltage measurement unit and the second voltage measurement unit being configured to:
derive an interconnect resistance of each of the interconnects based upon voltages of the first end and the second end of each of the plurality of block interconnects and based upon a measurement of current of the battery pack; and
derive an internal resistance of each of a plurality of blocks of the battery pack based upon voltages of the first end and the second end of each of the plurality of block interconnects and based upon the measurement of current; wherein the battery pack includes the plurality of blocks with the blocks being connected in series by the block interconnects. 8. The battery pack monitoring apparatus of claim 7, wherein:
the first voltage measurement unit is operable in an event of a failure of the second voltage measurement unit; and the second voltage measurement unit is operable in an event of a failure of the first voltage measurement unit. 9. The battery pack monitoring apparatus of claim 7, wherein the first voltage measurement unit and the second voltage measurement unit are further configured to estimate a current of the battery pack, based upon the derived interconnect resistance of two of the interconnects, and the voltages of the first end and the second end of each of the plurality of block interconnects, in absence of a current sensor. 10. The battery pack monitoring apparatus of claim 7, wherein the first voltage measurement unit and the second voltage measurement unit are further configured to:
apply the voltages of the first end and the second end of each of the plurality of block interconnects as voltages of second ends and first ends of the blocks; apply a voltage of the negative terminal of the battery pack as a reference voltage; and measure a voltage of the positive terminal of the battery pack. 11. The battery pack monitoring apparatus of claim 7, wherein:
couplings of the first voltage measurement unit to the first end of each of the plurality of block interconnects are positioned proximate to positive terminals of the blocks; and couplings of the second voltage measurement unit to the second end of each of the plurality of block interconnects are positioned proximate to negative terminals of the blocks. 12. The battery pack monitoring apparatus of claim 7, further comprising:
a current sensor configured to couple to the battery pack and to provide the measurement of current, the current sensor including one from the set consisting of a resistor and a Hall effect device. 13. A method of monitoring a battery pack, comprising:
measuring voltages of first ends of a plurality of interconnects that serially couple blocks of a battery pack, wherein for each of the plurality of interconnects a first end is closer to a negative terminal of the battery pack and an opposed second end is closer to a positive terminal of the battery pack; measuring voltages of opposed second ends of the plurality of interconnects; measuring a current of the battery pack; calculating an interconnect resistance of each of the plurality of interconnects based upon the current, the voltages of the first ends of the interconnects and the voltages of the opposed second ends of the interconnects; and calculating an internal resistance of each of the blocks based upon the current, the voltages of the first ends of the interconnects and the voltages of the opposed second ends of the interconnects. 14. The method of claim 13, further comprising:
calculating an estimate of the current of the battery pack based upon the voltages of the first ends of the interconnects, the voltages of the opposed second ends of the interconnects, and the calculated interconnect resistance of two of the plurality of interconnects, in response to a failure of a current sensor. 15. The method of claim 13, further comprising:
maintaining operation of a first voltage measurement unit in an event of a failure of a second voltage measurement unit, wherein the first voltage measurement unit is configured to measure the voltages of the first ends of the plurality of interconnects. 16. The method of claim 13, further comprising:
maintaining operation of a second voltage measurement unit in an event of a failure of a first voltage measurement unit, wherein the second voltage measurement unit is configured to measure the voltages of the opposed second ends of the plurality of interconnects. 17. The method of claim 13, further comprising:
applying a voltage of the negative terminal as a reference voltage, wherein the voltages of the first ends of the plurality of interconnects and the voltages of the opposed second ends of the plurality of interconnects are measured relative to the reference voltage. 18. The method of claim 13, further comprising:
coupling a first voltage measurement unit to the negative terminal of the battery pack and to the first ends of the plurality of interconnects, wherein the voltages of the first ends of the plurality of interconnects are measured relative to the negative terminal of the battery pack, by the first voltage measurement unit; and coupling a second voltage measurement unit to the negative terminal of the battery pack and to the opposed second ends of the plurality of interconnects, wherein the voltages of the opposed second ends of the plurality of interconnects are measured relative to the negative terminal of the battery pack, by the second voltage measurement unit. 19. The method of claim 13, further comprising:
estimating resistance by application of a formula Rblock — i+Rinterconnect — i=(Vi(t1)−Vi(t2)−Vi−1(t1)+Vi−1(t2))/(I(t1)−I(t2)). 20. The method of claim 13, further comprising:
estimating current by application of a formula Iestimated=((Vtop — (i+1)−Vtop — i)−(Vbottom — (i+1)−Vbottom — i))/(Rinterconnect — (i−1)−Rinterconnect — i). | A battery pack monitoring apparatus is provided. The apparatus includes a voltage measurement system configured to couple to opposed ends of each of a plurality of blocks of a battery pack and to measure voltages thereof, the blocks being coupled in series by interconnects each having an interconnect resistance. The voltage measurement system is configured to derive an internal resistance of each of the plurality of blocks based upon the voltages of the opposed ends of each of the plurality of blocks and based upon a measurement of current of the battery pack and derive the interconnect resistance of each of the interconnects based upon the voltages of the opposed ends of each of the plurality of blocks and based upon the measurement of current.1. A battery pack monitoring apparatus, comprising:
a voltage measurement system configured to couple to opposed ends of each of a plurality of blocks of a battery pack and to measure voltages thereof, the blocks being coupled in series by interconnects each having an interconnect resistance; and the voltage measurement system being further configured to:
derive an internal resistance of each of the plurality of blocks based upon the voltages of the opposed ends of each of the plurality of blocks and based upon a measurement of current of the battery pack; and
derive the interconnect resistance of each of the interconnects based upon the voltages of the opposed ends of each of the plurality of blocks and based upon the measurement of current. 2. The battery pack monitoring apparatus of claim 1, wherein a plurality of the voltages of the opposed ends of each of the plurality of blocks are applied as voltages of a higher end and a lower end, respectively, of each of the interconnects. 3. The battery pack monitoring apparatus of claim 1, wherein each of the plurality of blocks has one or more cells in parallel. 4. The battery pack monitoring apparatus of claim 1, further comprising:
a current sensor configured coupled to the battery pack and to provide the measurement of current. 5. The battery pack monitoring apparatus of claim 1, wherein the voltage measurement system includes:
a first voltage measurement unit configured to couple to a negative terminal of a battery pack and to a first end of each of the opposed ends of each of the plurality of blocks; and a second voltage measurement unit configured to couple to a second end of each of the opposed ends of each of the plurality of blocks and to the positive terminal of the battery pack. 6. The battery pack monitoring apparatus of claim 1, comprising the voltage measurement system being further configured to estimate the current of the battery pack based upon the voltages of the opposed ends of each of the plurality of blocks and based upon the derived internal resistance of two of the interconnects. 7. A battery pack monitoring apparatus, comprising:
a first voltage measurement unit configured to couple to a negative terminal of a battery pack, to a positive terminal of the battery pack, and to a first end of each of a plurality of block interconnects of the battery pack; a second voltage measurement unit configured to couple to the negative terminal of the battery pack, to the positive terminal of the battery pack, and to a second end of each of the plurality of block interconnects; and the first voltage measurement unit and the second voltage measurement unit being configured to:
derive an interconnect resistance of each of the interconnects based upon voltages of the first end and the second end of each of the plurality of block interconnects and based upon a measurement of current of the battery pack; and
derive an internal resistance of each of a plurality of blocks of the battery pack based upon voltages of the first end and the second end of each of the plurality of block interconnects and based upon the measurement of current; wherein the battery pack includes the plurality of blocks with the blocks being connected in series by the block interconnects. 8. The battery pack monitoring apparatus of claim 7, wherein:
the first voltage measurement unit is operable in an event of a failure of the second voltage measurement unit; and the second voltage measurement unit is operable in an event of a failure of the first voltage measurement unit. 9. The battery pack monitoring apparatus of claim 7, wherein the first voltage measurement unit and the second voltage measurement unit are further configured to estimate a current of the battery pack, based upon the derived interconnect resistance of two of the interconnects, and the voltages of the first end and the second end of each of the plurality of block interconnects, in absence of a current sensor. 10. The battery pack monitoring apparatus of claim 7, wherein the first voltage measurement unit and the second voltage measurement unit are further configured to:
apply the voltages of the first end and the second end of each of the plurality of block interconnects as voltages of second ends and first ends of the blocks; apply a voltage of the negative terminal of the battery pack as a reference voltage; and measure a voltage of the positive terminal of the battery pack. 11. The battery pack monitoring apparatus of claim 7, wherein:
couplings of the first voltage measurement unit to the first end of each of the plurality of block interconnects are positioned proximate to positive terminals of the blocks; and couplings of the second voltage measurement unit to the second end of each of the plurality of block interconnects are positioned proximate to negative terminals of the blocks. 12. The battery pack monitoring apparatus of claim 7, further comprising:
a current sensor configured to couple to the battery pack and to provide the measurement of current, the current sensor including one from the set consisting of a resistor and a Hall effect device. 13. A method of monitoring a battery pack, comprising:
measuring voltages of first ends of a plurality of interconnects that serially couple blocks of a battery pack, wherein for each of the plurality of interconnects a first end is closer to a negative terminal of the battery pack and an opposed second end is closer to a positive terminal of the battery pack; measuring voltages of opposed second ends of the plurality of interconnects; measuring a current of the battery pack; calculating an interconnect resistance of each of the plurality of interconnects based upon the current, the voltages of the first ends of the interconnects and the voltages of the opposed second ends of the interconnects; and calculating an internal resistance of each of the blocks based upon the current, the voltages of the first ends of the interconnects and the voltages of the opposed second ends of the interconnects. 14. The method of claim 13, further comprising:
calculating an estimate of the current of the battery pack based upon the voltages of the first ends of the interconnects, the voltages of the opposed second ends of the interconnects, and the calculated interconnect resistance of two of the plurality of interconnects, in response to a failure of a current sensor. 15. The method of claim 13, further comprising:
maintaining operation of a first voltage measurement unit in an event of a failure of a second voltage measurement unit, wherein the first voltage measurement unit is configured to measure the voltages of the first ends of the plurality of interconnects. 16. The method of claim 13, further comprising:
maintaining operation of a second voltage measurement unit in an event of a failure of a first voltage measurement unit, wherein the second voltage measurement unit is configured to measure the voltages of the opposed second ends of the plurality of interconnects. 17. The method of claim 13, further comprising:
applying a voltage of the negative terminal as a reference voltage, wherein the voltages of the first ends of the plurality of interconnects and the voltages of the opposed second ends of the plurality of interconnects are measured relative to the reference voltage. 18. The method of claim 13, further comprising:
coupling a first voltage measurement unit to the negative terminal of the battery pack and to the first ends of the plurality of interconnects, wherein the voltages of the first ends of the plurality of interconnects are measured relative to the negative terminal of the battery pack, by the first voltage measurement unit; and coupling a second voltage measurement unit to the negative terminal of the battery pack and to the opposed second ends of the plurality of interconnects, wherein the voltages of the opposed second ends of the plurality of interconnects are measured relative to the negative terminal of the battery pack, by the second voltage measurement unit. 19. The method of claim 13, further comprising:
estimating resistance by application of a formula Rblock — i+Rinterconnect — i=(Vi(t1)−Vi(t2)−Vi−1(t1)+Vi−1(t2))/(I(t1)−I(t2)). 20. The method of claim 13, further comprising:
estimating current by application of a formula Iestimated=((Vtop — (i+1)−Vtop — i)−(Vbottom — (i+1)−Vbottom — i))/(Rinterconnect — (i−1)−Rinterconnect — i). | 2,800 |
11,448 | 11,448 | 14,325,787 | 2,893 | A complementary metal-oxide-semiconductor (CMOS) integrated circuit structure, and method of fabricating the same according to a replacement metal gate process. P-channel and n-channel MOS transistors are formed with high-k gate dielectric material that differ from one another in composition or thickness, and with interface dielectric material that differ from one another in composition or thickness. The described replacement gate process enables construction so that neither of the p-channel or n-channel transistor gate structures includes the metal gate material from the other transistor, thus facilitating reliable filling of the gate structures with fill metal. | 1. A method of forming an integrated circuit structure at a semiconducting surface of a body, the integrated circuit structure including first and second transistors of opposite channel conductivity types, comprising:
forming first and second dummy gate electrodes overlying a dummy gate dielectric material at selected locations of the surface, the second dummy gate electrode overlying a region of a first conductivity type, and the first dummy gate electrode overlying a region of a second conductivity type, the second conductivity type opposite the first conductivity type; forming source/drain regions of the first conductivity type into the region of second conductivity type, at locations on opposite sides of the first dummy gate electrode; forming source/drain regions of the second conductivity type into the region of first conductivity type, at locations on opposite sides of the second dummy gate electrode; depositing filler dielectric between the first and second dummy gate electrodes; patterning a mask layer over a portion of the structure including the second dummy gate electrode, the mask layer exposing a portion of the structure including the first dummy gate electrode; removing the first dummy gate electrode and its underlying dummy gate dielectric material to define a gap between filler dielectric structures and to expose a portion of the region of second conductivity type; forming a first dielectric interface layer at the exposed portion of the region of second conductivity type; depositing a first high-k dielectric layer overall; then depositing a first metal gate layer, the first metal gate layer comprising a metal or metal compound; then depositing a first fill metal to fill the gap at the location from which the second dummy gate electrode was removed; then planarizing the structure to expose a top surface of the second dummy gate electrode; removing the second dummy gate electrode and its underlying dummy gate dielectric material to define a gap between filler dielectric structures and to expose a portion of the region of first conductivity type; forming a second dielectric interface layer at the exposed portion of the region of first conductivity type; depositing a second high-k dielectric layer overall; then depositing a second metal gate layer, the second metal gate layer comprising a metal or metal compound; then depositing a second fill metal to fill the gap at the location from which the second dummy gate electrode was removed; then planarizing the structure to expose top surfaces of the first and second fill metal and of the filler dielectric. 2. The method of claim 1, wherein the first high-k dielectric layer is of a different dielectric material than the second high-k dielectric layer. 3. The method of claim 2, wherein the first high-k dielectric layer has a different thickness than that of the second high-k dielectric layer. 4. The method of claim 1, wherein the first high-k dielectric layer has a different thickness than that of the second high-k dielectric layer. 5. The method of claim 4, wherein the first dielectric interface layer has a different thickness than that of the second dielectric interface layer. 6. The method of claim 5, wherein the first conductivity type is n-type;
wherein the second conductivity type is p-type; wherein the first dielectric interface layer is thicker than the second dielectric interface layer; and wherein the first high-k dielectric layer is thinner than the second high-k dielectric layer. 8. The method of claim 1, wherein the first dielectric interface layer has a different thickness than that of the second dielectric interface layer. 9. The method of claim 1, further comprising:
after the step of removing the first dummy gate electrode and its underlying dummy gate dielectric material and before the step of forming the first dielectric interface layer, removing the mask layer. 10. The method of claim 1, further comprising:
after the step of depositing the first high-k dielectric layer and before the step of depositing the first metal gate layer, depositing a first barrier layer; and after the step of depositing the second high-k dielectric layer and before the step of depositing the second metal gate layer, depositing a second barrier layer. 11. The method of claim 1, further comprising:
after the step of depositing the first metal gate layer and before the step of depositing the first fill metal, depositing a third barrier layer; and after the step of depositing the second metal gate layer and before the step of depositing the second fill metal, depositing a fourth barrier layer. | A complementary metal-oxide-semiconductor (CMOS) integrated circuit structure, and method of fabricating the same according to a replacement metal gate process. P-channel and n-channel MOS transistors are formed with high-k gate dielectric material that differ from one another in composition or thickness, and with interface dielectric material that differ from one another in composition or thickness. The described replacement gate process enables construction so that neither of the p-channel or n-channel transistor gate structures includes the metal gate material from the other transistor, thus facilitating reliable filling of the gate structures with fill metal.1. A method of forming an integrated circuit structure at a semiconducting surface of a body, the integrated circuit structure including first and second transistors of opposite channel conductivity types, comprising:
forming first and second dummy gate electrodes overlying a dummy gate dielectric material at selected locations of the surface, the second dummy gate electrode overlying a region of a first conductivity type, and the first dummy gate electrode overlying a region of a second conductivity type, the second conductivity type opposite the first conductivity type; forming source/drain regions of the first conductivity type into the region of second conductivity type, at locations on opposite sides of the first dummy gate electrode; forming source/drain regions of the second conductivity type into the region of first conductivity type, at locations on opposite sides of the second dummy gate electrode; depositing filler dielectric between the first and second dummy gate electrodes; patterning a mask layer over a portion of the structure including the second dummy gate electrode, the mask layer exposing a portion of the structure including the first dummy gate electrode; removing the first dummy gate electrode and its underlying dummy gate dielectric material to define a gap between filler dielectric structures and to expose a portion of the region of second conductivity type; forming a first dielectric interface layer at the exposed portion of the region of second conductivity type; depositing a first high-k dielectric layer overall; then depositing a first metal gate layer, the first metal gate layer comprising a metal or metal compound; then depositing a first fill metal to fill the gap at the location from which the second dummy gate electrode was removed; then planarizing the structure to expose a top surface of the second dummy gate electrode; removing the second dummy gate electrode and its underlying dummy gate dielectric material to define a gap between filler dielectric structures and to expose a portion of the region of first conductivity type; forming a second dielectric interface layer at the exposed portion of the region of first conductivity type; depositing a second high-k dielectric layer overall; then depositing a second metal gate layer, the second metal gate layer comprising a metal or metal compound; then depositing a second fill metal to fill the gap at the location from which the second dummy gate electrode was removed; then planarizing the structure to expose top surfaces of the first and second fill metal and of the filler dielectric. 2. The method of claim 1, wherein the first high-k dielectric layer is of a different dielectric material than the second high-k dielectric layer. 3. The method of claim 2, wherein the first high-k dielectric layer has a different thickness than that of the second high-k dielectric layer. 4. The method of claim 1, wherein the first high-k dielectric layer has a different thickness than that of the second high-k dielectric layer. 5. The method of claim 4, wherein the first dielectric interface layer has a different thickness than that of the second dielectric interface layer. 6. The method of claim 5, wherein the first conductivity type is n-type;
wherein the second conductivity type is p-type; wherein the first dielectric interface layer is thicker than the second dielectric interface layer; and wherein the first high-k dielectric layer is thinner than the second high-k dielectric layer. 8. The method of claim 1, wherein the first dielectric interface layer has a different thickness than that of the second dielectric interface layer. 9. The method of claim 1, further comprising:
after the step of removing the first dummy gate electrode and its underlying dummy gate dielectric material and before the step of forming the first dielectric interface layer, removing the mask layer. 10. The method of claim 1, further comprising:
after the step of depositing the first high-k dielectric layer and before the step of depositing the first metal gate layer, depositing a first barrier layer; and after the step of depositing the second high-k dielectric layer and before the step of depositing the second metal gate layer, depositing a second barrier layer. 11. The method of claim 1, further comprising:
after the step of depositing the first metal gate layer and before the step of depositing the first fill metal, depositing a third barrier layer; and after the step of depositing the second metal gate layer and before the step of depositing the second fill metal, depositing a fourth barrier layer. | 2,800 |
11,449 | 11,449 | 15,606,741 | 2,832 | An electric motor comprising: an motor main body, a fan motor for cooling the motor main body, and a casing which is attached to the motor main body to hold the fan motor, wherein the fan motor has engagement parts, and both of the motor main body and the casing are provided with engagement parts which can engage with the engagement parts on the fan motor to fasten the fan motor. | 1. An electric motor comprising:
a motor main body, a fan motor for cooling said motor main body, and a casing which is attached to said motor main body to hold said fan motor, wherein said fan motor has a plurality of engagement parts comprising female threads, and both of said motor main body and said casing are each provided with corresponding plurality of engagement parts (1E, 3E) comprising through holes, wherein the plurality of engagement parts on the fan motor align with either the plurality of engagement parts on the motor main body or casing so that a plurality of bolts can be received in either the plurality of engagement parts of the motor main body or casing and engage the plurality of engagement parts of the fan motor to fasten said fan motor to either the main motor body or casing. 2. The electric motor according to claim 1, wherein
the engagement parts on said fan motor are provided on only one of the two end faces of said fan motor in a blowing direction of said fan motor, and the engagement parts on said motor main body and the engagement parts on said casing have common structures with each other. 3. The electric motor according to claim 1, wherein the engagement parts on said fan motor are provided on both of the two end faces of said fan motor in the blowing direction of said fan motor. 4. The electric motor according to claim 1, wherein
said fan motor has fitting parts which can fit with both said motor main body and said casing. 5. The electric motor according to claim 4, wherein
said fitting parts are formed on both of two end faces of said fan motor in the blowing direction of said fan motor. | An electric motor comprising: an motor main body, a fan motor for cooling the motor main body, and a casing which is attached to the motor main body to hold the fan motor, wherein the fan motor has engagement parts, and both of the motor main body and the casing are provided with engagement parts which can engage with the engagement parts on the fan motor to fasten the fan motor.1. An electric motor comprising:
a motor main body, a fan motor for cooling said motor main body, and a casing which is attached to said motor main body to hold said fan motor, wherein said fan motor has a plurality of engagement parts comprising female threads, and both of said motor main body and said casing are each provided with corresponding plurality of engagement parts (1E, 3E) comprising through holes, wherein the plurality of engagement parts on the fan motor align with either the plurality of engagement parts on the motor main body or casing so that a plurality of bolts can be received in either the plurality of engagement parts of the motor main body or casing and engage the plurality of engagement parts of the fan motor to fasten said fan motor to either the main motor body or casing. 2. The electric motor according to claim 1, wherein
the engagement parts on said fan motor are provided on only one of the two end faces of said fan motor in a blowing direction of said fan motor, and the engagement parts on said motor main body and the engagement parts on said casing have common structures with each other. 3. The electric motor according to claim 1, wherein the engagement parts on said fan motor are provided on both of the two end faces of said fan motor in the blowing direction of said fan motor. 4. The electric motor according to claim 1, wherein
said fan motor has fitting parts which can fit with both said motor main body and said casing. 5. The electric motor according to claim 4, wherein
said fitting parts are formed on both of two end faces of said fan motor in the blowing direction of said fan motor. | 2,800 |
11,450 | 11,450 | 15,244,720 | 2,881 | A method includes parallel or serial ionization of a gas mixture by activating at least two ionization devices operating using different ionization procedures, and/or by ionizing the gas mixture in a detector to which the gas mixture and ions and/or metastable particles of an ionization gas are fed. The method also includes detecting the ionized gas mixture in the detector for the mass spectrometric examination thereof. A mass spectrometer for mass spectrometric examination of gas mixtures includes an ionization unit for ionizing a gas mixture and a detector for detecting the ionized gas mixture. | 1-16. (canceled) 17. A method, comprising:
in a three dimensional ion trap configured to store ions, interacting a gas mixture with ions and/or metastable particles to produce an ionized gas mixture; and using the three dimensional ion trap to mass spectrometrically examine the ionized gas mixture. 18. The method of claim 17, further comprising:
exposing an ionization gas to an ionizer to produce the ions and/or metastable particles; and disposing the ions and/or metastable particles in the three dimensional ion trap. 19. The method of claim 18, wherein the ionizer comprises a member selected from the group consisting of a charge exchange ionizer, an electron impact ionizer, a filament ionizer, a field ionizer, a pulsed laser ionizer, a photon ionizer, a UV light ionizer, a VUV light ionizer and an EUV light ionizer. 20. The method of claim 18, wherein the ionizer comprises a plasma ionization device. 21. The method of claim 20, wherein:
the plasma ionization device uses a dielectric barrier to produce a plasma; and the method comprises exposing the ionization gas to the plasma to produce the ions and/or metastable particles. 22. The method of claim 20, wherein:
the plasma ionization device uses a dielectric barrier to produce a radiofrequency plasma; and the method comprises exposing the ionization gas to the radiofrequency plasma to produce the ions and/or metastable particles. 23. The method of claim 20, wherein:
the plasma ionization device uses a dielectric barrier to produce a direct current plasma; and the method comprises exposing the ionization gas to the direct current plasma to produce the ions and/or metastable particles. 24. The method of claim 20, further comprising setting an ionization energy of the ionizer based on the gas mixture. 25. The method of claim 24, further comprising, prior to producing the ionized gas mixture, using the ionizer to produce a plasma to clean at least one member selected from the group consisting of the three dimensional ion trap, a measurement chamber, and the ionizer. 26. The method of claim 24, further comprising, prior to ionizing the gas mixture, using the ionizer to produce a plasma to clean a measurement chamber at a pressure of between one bar and 1×10−10 millibar. 27. The method of claim 17, wherein the gas mixture comprises particles having an atomic mass number of between 100 and 20,000. 28. The method of claim 17, wherein the gas mixture comprises particles having an atomic mass number between 20,000 and 2,000,000. 29. The method of claim 17, wherein the gas mixture comprises ions. 30. The method of claim 17, wherein the gas mixture comprises ions, and the method further comprises:
exposing an ionization gas to an ionizer to produce the ions; and disposing the ions in the three dimensional ion trap. 31. The method of claim 30, wherein the ionizer comprises a plasma ionization device. 32. The method of claim 31, further comprising setting an ionization energy of the ionizer based on the gas mixture. 33. The method of claim 32, further comprising, prior to producing the ionized gas mixture, using the ionizer to produce a plasma to clean at least one member selected from the group consisting of the three dimensional ion trap, a measurement chamber, and the ionizer. 34. A mass spectrometer, comprising:
an ionizer; and a three dimensional ion trap configured to store ions, wherein the mass spectrometer is configured so that during use of the mass spectrometer:
an ionization gas is exposed to the ionizer to produce ions and/or metastable particles;
the ions and/or metastable particles are transferred from the ionizer to the three dimensional ion trap;
in the three dimensional ion trap, the ions and/metastable particles ionize a gas mixture to provide an ionized gas mixture; and
the three dimensional ion trap mass spectrometrically examines the ionized gas mixture. 35. The mass spectrometer of claim 34, wherein the mass spectrometer is configured so that during use of the mass spectrometer the ionization gas is exposed to the ionizer to produce ions. 36. The mass spectrometer of claim 34, wherein the mass spectrometer is configured so that during use of the mass spectrometer:
the ionization gas is exposed to the ionizer to produce ions;
the ions are transferred from the ionizer to the three dimensional ion trap;
in the three dimensional ion trap, the ions ionize a gas mixture to provide an ionized gas mixture; and
the three dimensional ion trap mass spectrometrically examines the ionized gas mixture. | A method includes parallel or serial ionization of a gas mixture by activating at least two ionization devices operating using different ionization procedures, and/or by ionizing the gas mixture in a detector to which the gas mixture and ions and/or metastable particles of an ionization gas are fed. The method also includes detecting the ionized gas mixture in the detector for the mass spectrometric examination thereof. A mass spectrometer for mass spectrometric examination of gas mixtures includes an ionization unit for ionizing a gas mixture and a detector for detecting the ionized gas mixture.1-16. (canceled) 17. A method, comprising:
in a three dimensional ion trap configured to store ions, interacting a gas mixture with ions and/or metastable particles to produce an ionized gas mixture; and using the three dimensional ion trap to mass spectrometrically examine the ionized gas mixture. 18. The method of claim 17, further comprising:
exposing an ionization gas to an ionizer to produce the ions and/or metastable particles; and disposing the ions and/or metastable particles in the three dimensional ion trap. 19. The method of claim 18, wherein the ionizer comprises a member selected from the group consisting of a charge exchange ionizer, an electron impact ionizer, a filament ionizer, a field ionizer, a pulsed laser ionizer, a photon ionizer, a UV light ionizer, a VUV light ionizer and an EUV light ionizer. 20. The method of claim 18, wherein the ionizer comprises a plasma ionization device. 21. The method of claim 20, wherein:
the plasma ionization device uses a dielectric barrier to produce a plasma; and the method comprises exposing the ionization gas to the plasma to produce the ions and/or metastable particles. 22. The method of claim 20, wherein:
the plasma ionization device uses a dielectric barrier to produce a radiofrequency plasma; and the method comprises exposing the ionization gas to the radiofrequency plasma to produce the ions and/or metastable particles. 23. The method of claim 20, wherein:
the plasma ionization device uses a dielectric barrier to produce a direct current plasma; and the method comprises exposing the ionization gas to the direct current plasma to produce the ions and/or metastable particles. 24. The method of claim 20, further comprising setting an ionization energy of the ionizer based on the gas mixture. 25. The method of claim 24, further comprising, prior to producing the ionized gas mixture, using the ionizer to produce a plasma to clean at least one member selected from the group consisting of the three dimensional ion trap, a measurement chamber, and the ionizer. 26. The method of claim 24, further comprising, prior to ionizing the gas mixture, using the ionizer to produce a plasma to clean a measurement chamber at a pressure of between one bar and 1×10−10 millibar. 27. The method of claim 17, wherein the gas mixture comprises particles having an atomic mass number of between 100 and 20,000. 28. The method of claim 17, wherein the gas mixture comprises particles having an atomic mass number between 20,000 and 2,000,000. 29. The method of claim 17, wherein the gas mixture comprises ions. 30. The method of claim 17, wherein the gas mixture comprises ions, and the method further comprises:
exposing an ionization gas to an ionizer to produce the ions; and disposing the ions in the three dimensional ion trap. 31. The method of claim 30, wherein the ionizer comprises a plasma ionization device. 32. The method of claim 31, further comprising setting an ionization energy of the ionizer based on the gas mixture. 33. The method of claim 32, further comprising, prior to producing the ionized gas mixture, using the ionizer to produce a plasma to clean at least one member selected from the group consisting of the three dimensional ion trap, a measurement chamber, and the ionizer. 34. A mass spectrometer, comprising:
an ionizer; and a three dimensional ion trap configured to store ions, wherein the mass spectrometer is configured so that during use of the mass spectrometer:
an ionization gas is exposed to the ionizer to produce ions and/or metastable particles;
the ions and/or metastable particles are transferred from the ionizer to the three dimensional ion trap;
in the three dimensional ion trap, the ions and/metastable particles ionize a gas mixture to provide an ionized gas mixture; and
the three dimensional ion trap mass spectrometrically examines the ionized gas mixture. 35. The mass spectrometer of claim 34, wherein the mass spectrometer is configured so that during use of the mass spectrometer the ionization gas is exposed to the ionizer to produce ions. 36. The mass spectrometer of claim 34, wherein the mass spectrometer is configured so that during use of the mass spectrometer:
the ionization gas is exposed to the ionizer to produce ions;
the ions are transferred from the ionizer to the three dimensional ion trap;
in the three dimensional ion trap, the ions ionize a gas mixture to provide an ionized gas mixture; and
the three dimensional ion trap mass spectrometrically examines the ionized gas mixture. | 2,800 |
11,451 | 11,451 | 15,151,323 | 2,852 | A method and apparatus for testing closed hydraulic systems such as a blowout preventer for leaks maintain a constant pressure in the portion of the hydraulic system to be tested. A variable displacement pump is connected to the system for maintaining a constant pressure within the system. Any amount of fluid introduced into or removed from the blowout preventer in order to maintain constant pressure is measured and is an indication of the leak rate in the closed hydraulic system. | 1. A method of testing for leaks in a closed hydraulic system comprising:
a. pressurizing the portion of the closed hydraulic system to a first pressure level, b. maintaining a constant pressure within the portion of the closed hydraulic system to be tested, and c. immediately measuring any amount of fluid added to or removed from the pressurized portion of the closed hydraulic system that is required to maintain the pressure within the portion to be tested at a constant level. 2. The method as claimed in claim 2 wherein the pressure is maintained constant by a intensifier pump driven by a variable displacement hydraulic pump. 3. The method as claimed in claim 1 wherein the intensifier pump includes an axially movable piston and the amount of fluid added to or removed from the portion of the portion of the closed hydraulic system is measured by measuring any displacement of the piston after the portion of the closed hydraulic system to be tested has been pressurized to the first pressure level. 4. The method as claimed in claim 1 further including step of raising the pressure within the portion of the closed hydraulic system to be tested to a second pressure level and immediately measuring any amount of fluid added to or removed from the portion of the blowout preventer to be tested in order to maintain a constant pressure at the second pressure level. 5. The method as claimed in claim 1 wherein the pressurizing step includes an initial pressurization phase and a transitional pressurization phase that mitigates the effects of thermal and mechanical induced pressure changes. | A method and apparatus for testing closed hydraulic systems such as a blowout preventer for leaks maintain a constant pressure in the portion of the hydraulic system to be tested. A variable displacement pump is connected to the system for maintaining a constant pressure within the system. Any amount of fluid introduced into or removed from the blowout preventer in order to maintain constant pressure is measured and is an indication of the leak rate in the closed hydraulic system.1. A method of testing for leaks in a closed hydraulic system comprising:
a. pressurizing the portion of the closed hydraulic system to a first pressure level, b. maintaining a constant pressure within the portion of the closed hydraulic system to be tested, and c. immediately measuring any amount of fluid added to or removed from the pressurized portion of the closed hydraulic system that is required to maintain the pressure within the portion to be tested at a constant level. 2. The method as claimed in claim 2 wherein the pressure is maintained constant by a intensifier pump driven by a variable displacement hydraulic pump. 3. The method as claimed in claim 1 wherein the intensifier pump includes an axially movable piston and the amount of fluid added to or removed from the portion of the portion of the closed hydraulic system is measured by measuring any displacement of the piston after the portion of the closed hydraulic system to be tested has been pressurized to the first pressure level. 4. The method as claimed in claim 1 further including step of raising the pressure within the portion of the closed hydraulic system to be tested to a second pressure level and immediately measuring any amount of fluid added to or removed from the portion of the blowout preventer to be tested in order to maintain a constant pressure at the second pressure level. 5. The method as claimed in claim 1 wherein the pressurizing step includes an initial pressurization phase and a transitional pressurization phase that mitigates the effects of thermal and mechanical induced pressure changes. | 2,800 |
11,452 | 11,452 | 14,695,890 | 2,883 | A circuit is disclosed having a component having repeatable distortion characteristics; and a drive circuit for providing a drive signal and comprising a non-linear filter for pre-compensating for distortion introduced by the component having repeatable distortion characteristics in response to the drive signal, the distortion having a non-linear response to the drive signal. | 1. A circuit comprising:
a component having repeatable distortion characteristics; and a drive circuit for providing a drive signal and comprising a non-linear filter having at least a tap for pre-compensating for distortion introduced by the component having repeatable distortion characteristics in response to the drive signal, the distortion having a non-linear response to the drive signal. 2. A circuit according to claim 1 wherein the component comprises a Directly Modulated Laser (DML). 3. A circuit according to claim 2 wherein the DML comprises a Vertical Cavity Surface Emitting Laser (VCSEL). 4. A circuit according to claim 2 wherein the DML comprises a Distributed FeedBack (DFB) laser. 5. A circuit according to claim 3 wherein the DML is operated at at least 25 Gbps. 6. A circuit according to claim 4 wherein the non-linear filter comprises a non-linear Finite Impulse Response (FIR) filter having at least 2 weights for application at each delayed tap and supporting at least one delayed tap. 7. A circuit according to claim 4 wherein the non-linear filter comprises a non-linear Finite Impulse Response (FIR) filter having at least 2 weights for application at each delayed tap and supporting at least 3 delayed taps. 8. A circuit according to claim 1 wherein the non-linear filter comprises a non-linear Finite Impulse Response (FIR) filter having at least 2 weights for application at each delayed tap and supporting filtering of both a rising edge, low to high signal level response and a falling edge, high to low signal level response. 9. A circuit according to claim 8 comprising:
for each tap a first input port for receiving a first weight, a second input port for receiving a second other weight, a switch for switching between the first weight and the second weight, and a weighting circuit for weighting of a signal within the tap to produce a tap output, tap output signals from different taps combined to form the drive signal. 10. A circuit according to claim 8 comprising:
for each tap a first input port for receiving a first weight, a second input port for receiving a second other weight, a scaling circuit for scaling the first weight and the second weight, and a weighting circuit for weighting of a signal within the tap to produce a tap output, tap output signals from different taps combined to form the drive signal. 11. A circuit according to claim 1 wherein the non-linear filter comprises a non-linear Finite Impulse Response (FIR) filter having greater than 2 weights at each delayed tap supporting filtering of a complex amplitude dependent non-linear distortion for a signal with a modulation scheme having greater than 2 amplitude levels of consequence for a given data symbol, such as PAM4 or 4-Level Pulse Amplitude Modulation. 12. A circuit according to claim 11 consisting of an analogue filter circuit. 13. A circuit according to claim 12 wherein the circuit is implemented in an integrated semiconductor. 14. A circuit according to claim 11 comprising:
for each tap a first input port for receiving a first weight, a second input port for receiving a second other weight, a scaling circuit for scaling the first weight and the second weight, and a weighting circuit for weighting of a signal within the tap to produce a tap output, tap output signals from different taps combined to form the drive signal. 15. A method comprising:
providing a drive current for driving a component; filtering the drive current with a non-linear filter to provide pre-compensated drive current pre-compensated for distortion in a signal resulting from driving the component with the drive current, wherein an output signal from the component in response to the pre-compensated drive current has reduced distortion and better approximates an ideal transmit signal for an intended modulation. 16. A method according to claim 15 wherein the component comprises a Directly Modulated Laser (DML). 17. A method according to claim 16 wherein the directly modulated laser comprises a Vertical Cavity Surface Emitting Laser (VCSEL). 18. A method according to claim 16 wherein the directly modulated laser comprises a Distributed FeedBack (DFB) laser. 19. A method according to claim 18 wherein filtering is performed with an analogue filter. 20. A method according to claim 15 wherein the analogue filter is implemented in semiconductor. 21. A method according to claim 15 wherein the non-linear filter comprises a non-linear FIR filter. 22. A method according to claim 15 wherein filtering corrects for both a rising edge, low to high signal level response, and a falling edge, high to low signal level response. 23. A circuit comprising:
an input port for receiving a first signal; a plurality of taps, each tap comprising an input port for receiving a tap input signal, a first input port for receiving a first weight, a second input port for receiving a second other weight, and a scaling circuit for scaling an applied weighting based on the first weight and the second weight to scale the tap signal, the scaled tap signal for modifying the first signal. 24. A circuit according to claim 23 wherein the scaling circuit comprises a switching circuit for switching between the different weights to select one weight for application at a first time and another weight for application at another time within a same signal to be filtered. 25. A circuit according to claim 23 wherein the scaling circuit comprises a switching circuit for switching between the different weights to select one weight for application at a first time and another weight for application at another time in dependence upon a content of the signal to be filtered. 26. A circuit according to claim 23 comprising a summer for summing an output of each of the plurality of taps. 27. A circuit comprising:
an input port for receiving a first signal; a plurality of taps, each tap comprising an input port for receiving a tap input signal, a first input port for receiving a first weight, a second input port for receiving a second other weight, and a scaling circuit for scaling an applied weighting between the first weight and the second weight to scale the tap signal, the scaled tap signal for modifying the first signal. 28. A circuit comprising:
an input port for receiving a first signal; a plurality of taps, each tap comprising an input port for receiving a tap input signal, a plurality of input ports each for receiving a weight, and a scaling circuit for scaling an applied weighting based on the received weights to scale the tap signal, the scaled tap signal for modifying the first signal. 29. A circuit according to claim 28 wherein the scaling circuit comprises a switching circuit for switching between the different weights to select one weight for application at a first time and another weight for application at another time within a same signal to be filtered. 30. A circuit according to claim 28 wherein the scaling circuit comprises a switching circuit for switching between the different weights to select one weight for application at a first time and another weight for application at another time in dependence upon a content of the signal to be filtered. 31. A circuit according to claim 28 comprising a summer for summing an output of each of the plurality of taps. 32. A circuit comprising:
an input port for receiving a first signal, the first signal received at a receiver via a communication interface and from a remote location; a plurality of taps, each tap comprising an input port for receiving a tap input signal, a plurality of weight input ports each for receiving a weight, and a scaling circuit for scaling an applied weighting based on the received weights to scale the tap signal, the scaled tap signal for modifying the first signal. 33. A circuit according to claim 32 wherein the scaling circuit comprises a switching circuit for switching between the different weights to select one weight for application at a first time and another weight for application at another time within a same signal to be filtered. 34. A circuit according to claim 32 wherein the scaling circuit comprises a switching circuit for switching between the different weights to select one weight for application at a first time and another weight for application at another time in dependence upon a content of the signal to be filtered. 35. A circuit according to claim 32 comprising a summer for summing an output of each of the plurality of taps. 36. A method comprising
providing a receiver for receiving a signal transmitted across an optical fibre and for providing an electrical first signal; using a filter, filtering the first signal with a non-linear filter to provide compensation to the first signal for distortion in the signal when transmitted resulting from driving a transmitter at a transmit end, wherein an output signal from the filter better approximates an ideal transmit signal for an intended modulation. 37. A method comprising:
manufacturing a circuit comprising:
an input port for receiving a first signal;
a plurality of taps, each tap comprising an input port for receiving a tap input signal, a plurality of input ports each for receiving a weight, and a scaling circuit for scaling an applied weighting based on the received weights to scale the tap signal, the scaled tap signal for modifying the first signal;
testing the circuit and determining each of the plurality of weights based on testing thereof; and
setting each of the plurality of weights based on a result of the testing thereof and fixing each of the plurality of weights. 38. A circuit comprising:
a non-linear FIR filter comprising a plurality of taps, each tap having multiple weights and a scaling circuit for scaling the multiple weights to affect a signal propagating within the tap for nonlinear filtering of a first signal. 39. A circuit according to claim 38 wherein the non-linear filter is implemented as an analogue component within an integrated circuit. | A circuit is disclosed having a component having repeatable distortion characteristics; and a drive circuit for providing a drive signal and comprising a non-linear filter for pre-compensating for distortion introduced by the component having repeatable distortion characteristics in response to the drive signal, the distortion having a non-linear response to the drive signal.1. A circuit comprising:
a component having repeatable distortion characteristics; and a drive circuit for providing a drive signal and comprising a non-linear filter having at least a tap for pre-compensating for distortion introduced by the component having repeatable distortion characteristics in response to the drive signal, the distortion having a non-linear response to the drive signal. 2. A circuit according to claim 1 wherein the component comprises a Directly Modulated Laser (DML). 3. A circuit according to claim 2 wherein the DML comprises a Vertical Cavity Surface Emitting Laser (VCSEL). 4. A circuit according to claim 2 wherein the DML comprises a Distributed FeedBack (DFB) laser. 5. A circuit according to claim 3 wherein the DML is operated at at least 25 Gbps. 6. A circuit according to claim 4 wherein the non-linear filter comprises a non-linear Finite Impulse Response (FIR) filter having at least 2 weights for application at each delayed tap and supporting at least one delayed tap. 7. A circuit according to claim 4 wherein the non-linear filter comprises a non-linear Finite Impulse Response (FIR) filter having at least 2 weights for application at each delayed tap and supporting at least 3 delayed taps. 8. A circuit according to claim 1 wherein the non-linear filter comprises a non-linear Finite Impulse Response (FIR) filter having at least 2 weights for application at each delayed tap and supporting filtering of both a rising edge, low to high signal level response and a falling edge, high to low signal level response. 9. A circuit according to claim 8 comprising:
for each tap a first input port for receiving a first weight, a second input port for receiving a second other weight, a switch for switching between the first weight and the second weight, and a weighting circuit for weighting of a signal within the tap to produce a tap output, tap output signals from different taps combined to form the drive signal. 10. A circuit according to claim 8 comprising:
for each tap a first input port for receiving a first weight, a second input port for receiving a second other weight, a scaling circuit for scaling the first weight and the second weight, and a weighting circuit for weighting of a signal within the tap to produce a tap output, tap output signals from different taps combined to form the drive signal. 11. A circuit according to claim 1 wherein the non-linear filter comprises a non-linear Finite Impulse Response (FIR) filter having greater than 2 weights at each delayed tap supporting filtering of a complex amplitude dependent non-linear distortion for a signal with a modulation scheme having greater than 2 amplitude levels of consequence for a given data symbol, such as PAM4 or 4-Level Pulse Amplitude Modulation. 12. A circuit according to claim 11 consisting of an analogue filter circuit. 13. A circuit according to claim 12 wherein the circuit is implemented in an integrated semiconductor. 14. A circuit according to claim 11 comprising:
for each tap a first input port for receiving a first weight, a second input port for receiving a second other weight, a scaling circuit for scaling the first weight and the second weight, and a weighting circuit for weighting of a signal within the tap to produce a tap output, tap output signals from different taps combined to form the drive signal. 15. A method comprising:
providing a drive current for driving a component; filtering the drive current with a non-linear filter to provide pre-compensated drive current pre-compensated for distortion in a signal resulting from driving the component with the drive current, wherein an output signal from the component in response to the pre-compensated drive current has reduced distortion and better approximates an ideal transmit signal for an intended modulation. 16. A method according to claim 15 wherein the component comprises a Directly Modulated Laser (DML). 17. A method according to claim 16 wherein the directly modulated laser comprises a Vertical Cavity Surface Emitting Laser (VCSEL). 18. A method according to claim 16 wherein the directly modulated laser comprises a Distributed FeedBack (DFB) laser. 19. A method according to claim 18 wherein filtering is performed with an analogue filter. 20. A method according to claim 15 wherein the analogue filter is implemented in semiconductor. 21. A method according to claim 15 wherein the non-linear filter comprises a non-linear FIR filter. 22. A method according to claim 15 wherein filtering corrects for both a rising edge, low to high signal level response, and a falling edge, high to low signal level response. 23. A circuit comprising:
an input port for receiving a first signal; a plurality of taps, each tap comprising an input port for receiving a tap input signal, a first input port for receiving a first weight, a second input port for receiving a second other weight, and a scaling circuit for scaling an applied weighting based on the first weight and the second weight to scale the tap signal, the scaled tap signal for modifying the first signal. 24. A circuit according to claim 23 wherein the scaling circuit comprises a switching circuit for switching between the different weights to select one weight for application at a first time and another weight for application at another time within a same signal to be filtered. 25. A circuit according to claim 23 wherein the scaling circuit comprises a switching circuit for switching between the different weights to select one weight for application at a first time and another weight for application at another time in dependence upon a content of the signal to be filtered. 26. A circuit according to claim 23 comprising a summer for summing an output of each of the plurality of taps. 27. A circuit comprising:
an input port for receiving a first signal; a plurality of taps, each tap comprising an input port for receiving a tap input signal, a first input port for receiving a first weight, a second input port for receiving a second other weight, and a scaling circuit for scaling an applied weighting between the first weight and the second weight to scale the tap signal, the scaled tap signal for modifying the first signal. 28. A circuit comprising:
an input port for receiving a first signal; a plurality of taps, each tap comprising an input port for receiving a tap input signal, a plurality of input ports each for receiving a weight, and a scaling circuit for scaling an applied weighting based on the received weights to scale the tap signal, the scaled tap signal for modifying the first signal. 29. A circuit according to claim 28 wherein the scaling circuit comprises a switching circuit for switching between the different weights to select one weight for application at a first time and another weight for application at another time within a same signal to be filtered. 30. A circuit according to claim 28 wherein the scaling circuit comprises a switching circuit for switching between the different weights to select one weight for application at a first time and another weight for application at another time in dependence upon a content of the signal to be filtered. 31. A circuit according to claim 28 comprising a summer for summing an output of each of the plurality of taps. 32. A circuit comprising:
an input port for receiving a first signal, the first signal received at a receiver via a communication interface and from a remote location; a plurality of taps, each tap comprising an input port for receiving a tap input signal, a plurality of weight input ports each for receiving a weight, and a scaling circuit for scaling an applied weighting based on the received weights to scale the tap signal, the scaled tap signal for modifying the first signal. 33. A circuit according to claim 32 wherein the scaling circuit comprises a switching circuit for switching between the different weights to select one weight for application at a first time and another weight for application at another time within a same signal to be filtered. 34. A circuit according to claim 32 wherein the scaling circuit comprises a switching circuit for switching between the different weights to select one weight for application at a first time and another weight for application at another time in dependence upon a content of the signal to be filtered. 35. A circuit according to claim 32 comprising a summer for summing an output of each of the plurality of taps. 36. A method comprising
providing a receiver for receiving a signal transmitted across an optical fibre and for providing an electrical first signal; using a filter, filtering the first signal with a non-linear filter to provide compensation to the first signal for distortion in the signal when transmitted resulting from driving a transmitter at a transmit end, wherein an output signal from the filter better approximates an ideal transmit signal for an intended modulation. 37. A method comprising:
manufacturing a circuit comprising:
an input port for receiving a first signal;
a plurality of taps, each tap comprising an input port for receiving a tap input signal, a plurality of input ports each for receiving a weight, and a scaling circuit for scaling an applied weighting based on the received weights to scale the tap signal, the scaled tap signal for modifying the first signal;
testing the circuit and determining each of the plurality of weights based on testing thereof; and
setting each of the plurality of weights based on a result of the testing thereof and fixing each of the plurality of weights. 38. A circuit comprising:
a non-linear FIR filter comprising a plurality of taps, each tap having multiple weights and a scaling circuit for scaling the multiple weights to affect a signal propagating within the tap for nonlinear filtering of a first signal. 39. A circuit according to claim 38 wherein the non-linear filter is implemented as an analogue component within an integrated circuit. | 2,800 |
11,453 | 11,453 | 15,356,475 | 2,813 | Embodiments include methods and systems of 3D structure fill. In one embodiment, a method of filling a trench in a wafer includes performing directional plasma treatment with an ion beam at an angle with respect to a sidewall of the trench to form a treated portion of the sidewall and an untreated bottom of the trench. A material is deposited in the trench. The deposition rate of the material on the treated portion of the sidewall is different than a second deposition rate on the untreated bottom of the trench. In one embodiment, a method includes depositing a material on the wafer, filling a bottom of the trench and forming a layer on a sidewall of the trench and a top surface adjacent to the trench. The method includes etching the layer with an ion beam at an angle with respect to the sidewall. | 1. A system to fill a trench in a semiconductor wafer, the system comprising:
a plasma chamber to generate an ion beam at an angle with respect to a sidewall of the trench to form a treated portion of the sidewall and an untreated bottom of the trench; and a deposition chamber to deposit a material in the trench, wherein a deposition rate of the material on the treated portion of the sidewall is different than a second deposition rate on the untreated bottom of the trench. 2. The system of claim 1, wherein the plasma chamber is to generate the ion beam at the angle in a range of 1-85 degrees with respect to the sidewall. 3. The system of claim 1, further comprising:
a stage to support the semiconductor wafer in the plasma chamber, wherein the stage rotates, exposing a second sidewall of the trench to the ion beam at the angle with respect to the second sidewall. 4. The system of claim 1, wherein the deposition chamber comprises a chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD) chamber to fill the trench with a dielectric or metal. 5. A deposition system, comprising:
a first ion beam at a first angle with respect to a substrate, the first ion beam for performing a directional plasma treatment; a deposition module for depositing a material on the substrate with two different deposition rates at the same time; and a second ion beam at a second angle with respect to the substrate, the second ion beam for performing an angled ion beam etching, and the second angle different than the first angle. 6. The deposition system of claim 5, wherein performing the directional plasma treatment comprises generating the ion beam at the first angle in a range of 1-85 degrees. 7. The deposition system of claim 5, wherein performing the directional plasma treatment further comprises generating a second ion beam at a third angle with respect to the substrate, the third angle different than the first angle. 8. The deposition system of claim 5, wherein performing the directional plasma treatment comprises generating the ion beam with an ion species to change a dopant or impurity concentration, dopant or impurity profile, or hydrophobicity of a surface of the substrate. 9. The deposition system of claim 5, further comprising:
a stage for supporting the substrate. 10. The deposition system of claim 9, wherein the stage is rotatable. 11. The deposition system of claim 5, wherein the deposition module is a chemical vapor deposition (CVD) process. 12. The deposition system of claim 5, wherein the deposition module is a physical vapor deposition (PVD) module. 13. The deposition system of claim 5, wherein the deposition module is a plasma-enhanced chemical vapor deposition (PECVD) module. 14. The deposition system of claim 5, wherein the deposition module is an atomic layer deposition (ALD) module. 15. A method of filling a trench in a semiconductor wafer, the method comprising:
depositing a material on the semiconductor wafer, filling a bottom of the trench and forming a layer on a sidewall of the trench and a top surface adjacent to the trench; and etching the layer on the sidewall of the trench and the top surface with an ion beam at an angle with respect to the sidewall. 16. The method of claim 15, further comprising multiple iterations of depositing the material on the semiconductor wafer, and etching the layer on the sidewall of the trench and the top surface with the ion beam at the angle with respect to the sidewall. 17. The method of claim 15, wherein etching the layer on the sidewall of the trench and the top surface comprises generating the ion beam at the angle in a range of 1 to 85 degrees with respect to the sidewall. 18. The method of claim 15, wherein the trench has an aspect ratio of approximately 5 to 1, and wherein etching the layer on the sidewall of the trench and the top surface comprises generating the ion beam at the angle in a range of 1 to 20 degrees with respect to the sidewall. 19. The method of claim 15, wherein the trench has an aspect ratio of approximately 5 to 1, and wherein etching the layer on the sidewall of the trench and the top surface comprises etching the layer on a top 20-30% of the sidewall. 20. The method of claim 15, wherein depositing the material on the semiconductor wafer comprises filling a bottom of the trench with a dielectric or metal via chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). | Embodiments include methods and systems of 3D structure fill. In one embodiment, a method of filling a trench in a wafer includes performing directional plasma treatment with an ion beam at an angle with respect to a sidewall of the trench to form a treated portion of the sidewall and an untreated bottom of the trench. A material is deposited in the trench. The deposition rate of the material on the treated portion of the sidewall is different than a second deposition rate on the untreated bottom of the trench. In one embodiment, a method includes depositing a material on the wafer, filling a bottom of the trench and forming a layer on a sidewall of the trench and a top surface adjacent to the trench. The method includes etching the layer with an ion beam at an angle with respect to the sidewall.1. A system to fill a trench in a semiconductor wafer, the system comprising:
a plasma chamber to generate an ion beam at an angle with respect to a sidewall of the trench to form a treated portion of the sidewall and an untreated bottom of the trench; and a deposition chamber to deposit a material in the trench, wherein a deposition rate of the material on the treated portion of the sidewall is different than a second deposition rate on the untreated bottom of the trench. 2. The system of claim 1, wherein the plasma chamber is to generate the ion beam at the angle in a range of 1-85 degrees with respect to the sidewall. 3. The system of claim 1, further comprising:
a stage to support the semiconductor wafer in the plasma chamber, wherein the stage rotates, exposing a second sidewall of the trench to the ion beam at the angle with respect to the second sidewall. 4. The system of claim 1, wherein the deposition chamber comprises a chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD) chamber to fill the trench with a dielectric or metal. 5. A deposition system, comprising:
a first ion beam at a first angle with respect to a substrate, the first ion beam for performing a directional plasma treatment; a deposition module for depositing a material on the substrate with two different deposition rates at the same time; and a second ion beam at a second angle with respect to the substrate, the second ion beam for performing an angled ion beam etching, and the second angle different than the first angle. 6. The deposition system of claim 5, wherein performing the directional plasma treatment comprises generating the ion beam at the first angle in a range of 1-85 degrees. 7. The deposition system of claim 5, wherein performing the directional plasma treatment further comprises generating a second ion beam at a third angle with respect to the substrate, the third angle different than the first angle. 8. The deposition system of claim 5, wherein performing the directional plasma treatment comprises generating the ion beam with an ion species to change a dopant or impurity concentration, dopant or impurity profile, or hydrophobicity of a surface of the substrate. 9. The deposition system of claim 5, further comprising:
a stage for supporting the substrate. 10. The deposition system of claim 9, wherein the stage is rotatable. 11. The deposition system of claim 5, wherein the deposition module is a chemical vapor deposition (CVD) process. 12. The deposition system of claim 5, wherein the deposition module is a physical vapor deposition (PVD) module. 13. The deposition system of claim 5, wherein the deposition module is a plasma-enhanced chemical vapor deposition (PECVD) module. 14. The deposition system of claim 5, wherein the deposition module is an atomic layer deposition (ALD) module. 15. A method of filling a trench in a semiconductor wafer, the method comprising:
depositing a material on the semiconductor wafer, filling a bottom of the trench and forming a layer on a sidewall of the trench and a top surface adjacent to the trench; and etching the layer on the sidewall of the trench and the top surface with an ion beam at an angle with respect to the sidewall. 16. The method of claim 15, further comprising multiple iterations of depositing the material on the semiconductor wafer, and etching the layer on the sidewall of the trench and the top surface with the ion beam at the angle with respect to the sidewall. 17. The method of claim 15, wherein etching the layer on the sidewall of the trench and the top surface comprises generating the ion beam at the angle in a range of 1 to 85 degrees with respect to the sidewall. 18. The method of claim 15, wherein the trench has an aspect ratio of approximately 5 to 1, and wherein etching the layer on the sidewall of the trench and the top surface comprises generating the ion beam at the angle in a range of 1 to 20 degrees with respect to the sidewall. 19. The method of claim 15, wherein the trench has an aspect ratio of approximately 5 to 1, and wherein etching the layer on the sidewall of the trench and the top surface comprises etching the layer on a top 20-30% of the sidewall. 20. The method of claim 15, wherein depositing the material on the semiconductor wafer comprises filling a bottom of the trench with a dielectric or metal via chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). | 2,800 |
11,454 | 11,454 | 14,315,262 | 2,848 | A sun shield for shielding outdoor electrical equipment from sunlight is provided. The sun shield comprises a front, the front capable of shielding a front portion of the outdoor electrical equipment; a pair of sides, the pair of sides capable of shielding respective side portions of the outdoor electrical equipment; and a slanted roof, the slanted roof capable of shielding a top portion of the outdoor electrical equipment. Preferably, the slanted roof is provided at an angle such that sunlight is reflected no matter the elevation or azimuth of the sun during the day. The sun shield is placed over a cover of the outdoor electrical equipment leaving an air gap between the sun shield and the cover of the outdoor equipment. Advantageously, the air gap provides for air flow between the sun shield and the cover of the electrical equipment, encouraging heat dissipation. The sun shield is capable of being fastened to the outdoor electrical equipment by attachment to pre-existing screw holes in the cover of the outdoor electrical equipment or bracketing to a wall mount. | 1. A sunlight protection system, comprising:
an inverter installed on an outside of a building, the inverter capable of converting direct electrical current from at least one solar panel to alternating current; and a sun shield attached to a cover of the inverter. 2. The sunlight protection system of claim 1, wherein the sun shield comprises:
a front the structured and arranged to shield a front portion of the inverter; a pair of slanted sides, the pair of slanted sides structured and arranged to shield respective side portions of the inverter; and a slanted roof, the slanted roof angle structured and arranged to shield a top portion of the inverter; wherein the front, the pair of slanted sides and the slanted roof are each substantially planar; and when mounted to the cover, an air gap of at least one inch exists between the sun shield and the inverter. 3. The sunlight protection system of claim 1, wherein the sun shield does not cover a back portion of the electrical equipment, the back portion on an opposite side from the front portion. 4. The sunlight protection system of claim 1, wherein the sun shield does not cover a bottom portion of the electrical equipment, the bottom portion on an opposite side from the top portion. 5. The sunlight protection system of claim 1, wherein the sun shield is capable of being fastened to a cover of the outdoor electrical equipment leaving the air gap of at least one inch between the sun shield and the cover of the outdoor equipment. 6. The sunlight protection system of claim 1, wherein the sun shield is capable of being fastened to the outdoor electrical equipment by attachment to pre-existing screw holes in the cover of the outdoor electrical equipment. 7. The sunlight protection system of claim 1, wherein the front of the sun shield includes an opening to allow access to operation of the outdoor electrical equipment. 8. The sunlight protection system of of claim 7, wherein the opening includes a visor. 10. The sunlight protection system of claim 1, wherein each of the front, the pair of sides, and the slanted roof are substantially planar. 11. The sunlight protection system of claim 10, wherein the pair of sides and the slanted roof are each attached to the front. 12. The sunlight protection system of claim 1, wherein the sun shield is capable of attachment to the inverter using mounting brackets. 13. The sunlight protection system of claim 1, wherein the sun shield is formed by bending a single sheet of substantially flat metal. 14. The sunlight protection system of claim 13, wherein the pair of sides each are bent to a predetermined angle relative to the front, the predetermined angle being an acute angle greater than 30 degrees. 15. The sunlight protection system of claim 14, wherein the slanted roof is bent to a predetermined angle relative to the front, the predetermined angle being an acute angle. | A sun shield for shielding outdoor electrical equipment from sunlight is provided. The sun shield comprises a front, the front capable of shielding a front portion of the outdoor electrical equipment; a pair of sides, the pair of sides capable of shielding respective side portions of the outdoor electrical equipment; and a slanted roof, the slanted roof capable of shielding a top portion of the outdoor electrical equipment. Preferably, the slanted roof is provided at an angle such that sunlight is reflected no matter the elevation or azimuth of the sun during the day. The sun shield is placed over a cover of the outdoor electrical equipment leaving an air gap between the sun shield and the cover of the outdoor equipment. Advantageously, the air gap provides for air flow between the sun shield and the cover of the electrical equipment, encouraging heat dissipation. The sun shield is capable of being fastened to the outdoor electrical equipment by attachment to pre-existing screw holes in the cover of the outdoor electrical equipment or bracketing to a wall mount.1. A sunlight protection system, comprising:
an inverter installed on an outside of a building, the inverter capable of converting direct electrical current from at least one solar panel to alternating current; and a sun shield attached to a cover of the inverter. 2. The sunlight protection system of claim 1, wherein the sun shield comprises:
a front the structured and arranged to shield a front portion of the inverter; a pair of slanted sides, the pair of slanted sides structured and arranged to shield respective side portions of the inverter; and a slanted roof, the slanted roof angle structured and arranged to shield a top portion of the inverter; wherein the front, the pair of slanted sides and the slanted roof are each substantially planar; and when mounted to the cover, an air gap of at least one inch exists between the sun shield and the inverter. 3. The sunlight protection system of claim 1, wherein the sun shield does not cover a back portion of the electrical equipment, the back portion on an opposite side from the front portion. 4. The sunlight protection system of claim 1, wherein the sun shield does not cover a bottom portion of the electrical equipment, the bottom portion on an opposite side from the top portion. 5. The sunlight protection system of claim 1, wherein the sun shield is capable of being fastened to a cover of the outdoor electrical equipment leaving the air gap of at least one inch between the sun shield and the cover of the outdoor equipment. 6. The sunlight protection system of claim 1, wherein the sun shield is capable of being fastened to the outdoor electrical equipment by attachment to pre-existing screw holes in the cover of the outdoor electrical equipment. 7. The sunlight protection system of claim 1, wherein the front of the sun shield includes an opening to allow access to operation of the outdoor electrical equipment. 8. The sunlight protection system of of claim 7, wherein the opening includes a visor. 10. The sunlight protection system of claim 1, wherein each of the front, the pair of sides, and the slanted roof are substantially planar. 11. The sunlight protection system of claim 10, wherein the pair of sides and the slanted roof are each attached to the front. 12. The sunlight protection system of claim 1, wherein the sun shield is capable of attachment to the inverter using mounting brackets. 13. The sunlight protection system of claim 1, wherein the sun shield is formed by bending a single sheet of substantially flat metal. 14. The sunlight protection system of claim 13, wherein the pair of sides each are bent to a predetermined angle relative to the front, the predetermined angle being an acute angle greater than 30 degrees. 15. The sunlight protection system of claim 14, wherein the slanted roof is bent to a predetermined angle relative to the front, the predetermined angle being an acute angle. | 2,800 |
11,455 | 11,455 | 15,389,974 | 2,891 | A semiconductor device package includes a conductive clip that has a recess and that is configured to mount to a substrate along a first surface and a second surface that bound the recess, and that includes at least two vertical channel transistors that are of a same type and that are mounted within the recess in a same orientation such that a drain or source contact is coupled to the conductive clip, and such that a gate contact and a source or drain contact extend exposed within the recess and along a same long axis of the conductive clip. | 1. A semiconductor device package comprising:
a conductive clip that includes a recess and that is configured to mount to a substrate along a first surface and a second surface that bound the recess; and at least two vertical channel transistors that are of a same type, and that are mounted within the recess along a continuous surface and in a same orientation such that a drain or source contact is coupled to the conductive clip along the continuous surface, and such that a gate contact and a source or drain contact extend exposed within the recess and along a same long axis of the conductive clip. 2. The semiconductor device package of claim 1, wherein the drain contact of each one of the at least two vertical channel transistors is electrically coupled to the conductive clip, and the gate contact and the source contact extend exposed within the recess and along the same long axis of the conductive clip. 3. The semiconductor device package of claim 1, wherein the source contact of each one of the at least two vertical channel transistors is electrically coupled to the conductive clip, and the gate contact and the drain contact extend exposed within the recess and along the same long axis of the conductive clip. 4. The semiconductor device package of claim 1, wherein each one of the at least two vertical channel transistors is a distinct semiconductor die. 5. The semiconductor device package of claim 1, wherein the at least two vertical transistors are integrated within a common semiconductor die. 6. A system comprising:
a first semiconductor package that includes a first conductive clip and a first plurality of transistors, wherein:
the first conductive clip includes a recess and is configured to mount to a substrate along a first surface and a second surface of the first conductive clip that bound the recess, and
the first plurality of transistors include at least two vertical channel transistors that are of a same type, and that are mounted within the recess of the first conductive clip along a continuous surface and in a same orientation such that a drain contact is coupled to the first conductive clip along the continuous surface, and such that a gate contact and a source contact extend exposed within the recess and along a same long axis of the first conductive clip; and
a second semiconductor package that includes a second conductive clip and a second plurality of transistors, wherein:
the second conductive clip includes a recess and is configured to mount to the substrate along a first surface and a second surface of the second conductive clip that bound the recess, and
the second plurality of transistors include at least two vertical channel transistors that are of a same type, and that are mounted within the recess of the second conductive clip along a continuous surface and in a same orientation such that a source contact is coupled to the second conductive clip along the continuous surface, and such that a gate contact and a drain contact extend exposed within the recess and along a same long axis of the second conductive clip. 7. The system of claim 6, wherein each one of the first plurality of transistors is a distinct semiconductor die. 8. The system of claim 6, wherein the first plurality of transistors are integrated within a common semiconductor die. 9. The system of claim 6, wherein each one of the second plurality of transistors is a distinct semiconductor die. 10. The system of claim 6, wherein the second plurality of transistors are integrated within a common semiconductor die. 11. The system of claim 6, wherein each one of the first plurality of transistors is a vertical n-channel power transistor. 12. The system of claim 6, wherein each one of the first plurality of transistors is a vertical p-channel power transistor. 13. The system of claim 6, wherein each one of the second plurality of transistors is a vertical n-channel power transistor. 14. The system of claim 6, wherein each one of the second plurality of transistors is a vertical p-channel power transistor. 15. The system of claim 6, wherein each one of the first plurality of transistors is a vertical fin-based multi-gate transistor. 16. The system of claim 6, wherein each one of the second plurality of transistors is a vertical fin-based multi-gate transistor. 17. The system of claim 6, further comprising a printed circuit board, wherein the first semiconductor package and the second semiconductor package are mounted to the printed circuit board as part of a multi-phase bridge circuit. 18. A method comprising:
mounting at least two vertical channel transistors that are of a same type to a recess of a conductive clip, that is configured to mount to a substrate along a first surface and a second surface that bound the recess, in a same orientation such that a drain or source contact is coupled to the conductive clip, and such that a gate contact and a source or drain contact extend exposed within the recess and along a same long axis of the conductive clip. 19. The method of claim 18, wherein the drain contact of each one of the at least two vertical channel transistors is electrically coupled to the conductive clip, and the gate contact and the source contact extend exposed within the recess and along the same long axis of the conductive clip, and the method further comprising:
mounting the conductive clip to the substrate; and coupling the conductive clip to a ground reference node of half-bridge circuitry that is configured to drive a multi-phase motor. 20. The method of claim 18, wherein the source contact of each one of the at least two vertical channel transistors is electrically coupled to the conductive clip, and the gate contact and the drain contact extend exposed within the recess and along the same long axis of the conductive clip, and the method further comprising:
mounting the conductive clip to the substrate; and coupling the conductive clip to a battery supply node of half-bridge circuitry that is configured to drive a multi-phase motor. | A semiconductor device package includes a conductive clip that has a recess and that is configured to mount to a substrate along a first surface and a second surface that bound the recess, and that includes at least two vertical channel transistors that are of a same type and that are mounted within the recess in a same orientation such that a drain or source contact is coupled to the conductive clip, and such that a gate contact and a source or drain contact extend exposed within the recess and along a same long axis of the conductive clip.1. A semiconductor device package comprising:
a conductive clip that includes a recess and that is configured to mount to a substrate along a first surface and a second surface that bound the recess; and at least two vertical channel transistors that are of a same type, and that are mounted within the recess along a continuous surface and in a same orientation such that a drain or source contact is coupled to the conductive clip along the continuous surface, and such that a gate contact and a source or drain contact extend exposed within the recess and along a same long axis of the conductive clip. 2. The semiconductor device package of claim 1, wherein the drain contact of each one of the at least two vertical channel transistors is electrically coupled to the conductive clip, and the gate contact and the source contact extend exposed within the recess and along the same long axis of the conductive clip. 3. The semiconductor device package of claim 1, wherein the source contact of each one of the at least two vertical channel transistors is electrically coupled to the conductive clip, and the gate contact and the drain contact extend exposed within the recess and along the same long axis of the conductive clip. 4. The semiconductor device package of claim 1, wherein each one of the at least two vertical channel transistors is a distinct semiconductor die. 5. The semiconductor device package of claim 1, wherein the at least two vertical transistors are integrated within a common semiconductor die. 6. A system comprising:
a first semiconductor package that includes a first conductive clip and a first plurality of transistors, wherein:
the first conductive clip includes a recess and is configured to mount to a substrate along a first surface and a second surface of the first conductive clip that bound the recess, and
the first plurality of transistors include at least two vertical channel transistors that are of a same type, and that are mounted within the recess of the first conductive clip along a continuous surface and in a same orientation such that a drain contact is coupled to the first conductive clip along the continuous surface, and such that a gate contact and a source contact extend exposed within the recess and along a same long axis of the first conductive clip; and
a second semiconductor package that includes a second conductive clip and a second plurality of transistors, wherein:
the second conductive clip includes a recess and is configured to mount to the substrate along a first surface and a second surface of the second conductive clip that bound the recess, and
the second plurality of transistors include at least two vertical channel transistors that are of a same type, and that are mounted within the recess of the second conductive clip along a continuous surface and in a same orientation such that a source contact is coupled to the second conductive clip along the continuous surface, and such that a gate contact and a drain contact extend exposed within the recess and along a same long axis of the second conductive clip. 7. The system of claim 6, wherein each one of the first plurality of transistors is a distinct semiconductor die. 8. The system of claim 6, wherein the first plurality of transistors are integrated within a common semiconductor die. 9. The system of claim 6, wherein each one of the second plurality of transistors is a distinct semiconductor die. 10. The system of claim 6, wherein the second plurality of transistors are integrated within a common semiconductor die. 11. The system of claim 6, wherein each one of the first plurality of transistors is a vertical n-channel power transistor. 12. The system of claim 6, wherein each one of the first plurality of transistors is a vertical p-channel power transistor. 13. The system of claim 6, wherein each one of the second plurality of transistors is a vertical n-channel power transistor. 14. The system of claim 6, wherein each one of the second plurality of transistors is a vertical p-channel power transistor. 15. The system of claim 6, wherein each one of the first plurality of transistors is a vertical fin-based multi-gate transistor. 16. The system of claim 6, wherein each one of the second plurality of transistors is a vertical fin-based multi-gate transistor. 17. The system of claim 6, further comprising a printed circuit board, wherein the first semiconductor package and the second semiconductor package are mounted to the printed circuit board as part of a multi-phase bridge circuit. 18. A method comprising:
mounting at least two vertical channel transistors that are of a same type to a recess of a conductive clip, that is configured to mount to a substrate along a first surface and a second surface that bound the recess, in a same orientation such that a drain or source contact is coupled to the conductive clip, and such that a gate contact and a source or drain contact extend exposed within the recess and along a same long axis of the conductive clip. 19. The method of claim 18, wherein the drain contact of each one of the at least two vertical channel transistors is electrically coupled to the conductive clip, and the gate contact and the source contact extend exposed within the recess and along the same long axis of the conductive clip, and the method further comprising:
mounting the conductive clip to the substrate; and coupling the conductive clip to a ground reference node of half-bridge circuitry that is configured to drive a multi-phase motor. 20. The method of claim 18, wherein the source contact of each one of the at least two vertical channel transistors is electrically coupled to the conductive clip, and the gate contact and the drain contact extend exposed within the recess and along the same long axis of the conductive clip, and the method further comprising:
mounting the conductive clip to the substrate; and coupling the conductive clip to a battery supply node of half-bridge circuitry that is configured to drive a multi-phase motor. | 2,800 |
11,456 | 11,456 | 13,587,989 | 2,872 | An infrared camouflage textile, including an emissivity layer on one side of the textile and adapted to provide at least two different infrared emissivities in a pattern; a heating layer between the emissivity and insulating layers; and a power source to the heating layer. The emissivity layer may include a display module including pixel elements displaying the pattern, each pixel element including a display segment; a plurality of first charged pigments in the display segment each having a first charge; a plurality of second charged pigments in the display segment each having a charge opposite the first charge; an electrical contact coupled to the display segment to receive signals creating an electric field in the display segment; at least one computer-readable storage medium including code to transmit signals to the display module that create an electric field in a pixel element form the pattern in the emissivity layer. | 1. An infrared camouflage textile, comprising:
an emissivity layer disposed on a side of the textile and adapted to provide at least two different infrared emissivities in a predetermined pattern; a heating layer disposed below the emissivity layer and above the insulating layer; and a power source operably linked to the heating layer. 2. The infrared camouflage textile of claim 1 further comprising an insulating layer disposed on a first side of a textile and adapted to absorb a native infrared signature of a body adjacent the first side; 3. The infrared camouflage textile of claim 1 further comprising a thermal conductive or thermal foil layer disposed between the heating layer and the emissivity layer. 4. The infrared camouflage textile of claim 1 wherein the at least two different infrared emissivities create an infrared signature distinct from the native infrared signature. 5. The infrared camouflage textile of claim 1 wherein the at least two different infrared emissivities are disposed on a same layer and/or are at the same temperature. 6. The infrared camouflage textile of claim 1 wherein the predetermined pattern is composed of pixels or subpixels. 7. The infrared camouflage textile of claim 3 wherein size of the pixels or subpixels is based on predetermined estimated resolution of and predetermined estimated distance from a FLIR device or a thermal imaging device against which the textile is to provide camouflage. 8. The infrared camouflage textile of claim 1 further comprising a spacer or stand-off layer between the heating layer and the insulating layer. 9. The infrared camouflage textile of claim 1 wherein the emissivity layer comprises at least two materials having different infrared emissivities. 10. An infrared camouflage textile, comprising:
an emissivity layer disposed on a second side of the textile and adapted to provide at least two different infrared emissivities in a selectably pixelated pattern; a heating layer disposed below the emissivity layer and above the insulating layer; and a power source operably linked to the heating layer,
wherein the emissivity layer comprises:
a display module comprising a plurality of pixel elements operable to display the selectably pixelated pattern in the emissivity layer, wherein each pixel element comprises:
a display segment;
a plurality of first charged pigments housed within the display segment each having a first charge;
a plurality of second charged pigments housed within the display segment each having a second charge, wherein the first charge is opposite the second charge;
an electrical contact coupled to the display segment and operable to receive signals that cause an electric field to be present in the display segment;
at least one computer-readable tangible storage medium comprising executable code that, when executed by at least one processor, is operable to transmit signals to the display module that cause an electric field to be present in at least one pixel element of the plurality of pixel elements to form the selectably pixelated pattern in the emissivity layer. 11. The infrared camouflage textile of claim 10 further comprising an insulating layer disposed on a first side of a textile and adapted to absorb a native infrared signature of a body adjacent the first side; 12. The infrared camouflage textile of claim 10 further comprising a thermal conductive or thermal foil layer disposed between the heating layer and the emissivity layer. 13. The infrared camouflage textile of claim 10 wherein the at least two different infrared emissivities create an infrared signature distinct from the native infrared signature. 14. The infrared camouflage textile of claim 10 wherein the selectably pixelated pattern comprises subpixels. 15. The infrared camouflage textile of claim 14 wherein size of the subpixels is based on a predetermined estimated resolution of and a predetermined estimated distance from an infrared camera or non-imaging thermal sensing device against which the textile is to provide camouflage. 16. The infrared camouflage textile of claim 10 further comprising a spacer or stand-off layer. 17. The infrared camouflage textile of claim 10 wherein the emissivity layer comprises at least two materials having different infrared emissivities. 18. The infrared camouflage textile of claim 10 wherein the selectably pixelated pattern is based on output of an infrared camera or non-imaging thermal sensing device. 19. The infrared camouflage textile of claim 10 further comprising a plurality of outwardly facing surfaces each displaying a portion of the selectably pixelated pattern, and the selectably pixilated pattern of each outwardly facing surface is selected based on output of an infrared camera or non-imaging thermal sensing device associated with that outwardly facing surface. | An infrared camouflage textile, including an emissivity layer on one side of the textile and adapted to provide at least two different infrared emissivities in a pattern; a heating layer between the emissivity and insulating layers; and a power source to the heating layer. The emissivity layer may include a display module including pixel elements displaying the pattern, each pixel element including a display segment; a plurality of first charged pigments in the display segment each having a first charge; a plurality of second charged pigments in the display segment each having a charge opposite the first charge; an electrical contact coupled to the display segment to receive signals creating an electric field in the display segment; at least one computer-readable storage medium including code to transmit signals to the display module that create an electric field in a pixel element form the pattern in the emissivity layer.1. An infrared camouflage textile, comprising:
an emissivity layer disposed on a side of the textile and adapted to provide at least two different infrared emissivities in a predetermined pattern; a heating layer disposed below the emissivity layer and above the insulating layer; and a power source operably linked to the heating layer. 2. The infrared camouflage textile of claim 1 further comprising an insulating layer disposed on a first side of a textile and adapted to absorb a native infrared signature of a body adjacent the first side; 3. The infrared camouflage textile of claim 1 further comprising a thermal conductive or thermal foil layer disposed between the heating layer and the emissivity layer. 4. The infrared camouflage textile of claim 1 wherein the at least two different infrared emissivities create an infrared signature distinct from the native infrared signature. 5. The infrared camouflage textile of claim 1 wherein the at least two different infrared emissivities are disposed on a same layer and/or are at the same temperature. 6. The infrared camouflage textile of claim 1 wherein the predetermined pattern is composed of pixels or subpixels. 7. The infrared camouflage textile of claim 3 wherein size of the pixels or subpixels is based on predetermined estimated resolution of and predetermined estimated distance from a FLIR device or a thermal imaging device against which the textile is to provide camouflage. 8. The infrared camouflage textile of claim 1 further comprising a spacer or stand-off layer between the heating layer and the insulating layer. 9. The infrared camouflage textile of claim 1 wherein the emissivity layer comprises at least two materials having different infrared emissivities. 10. An infrared camouflage textile, comprising:
an emissivity layer disposed on a second side of the textile and adapted to provide at least two different infrared emissivities in a selectably pixelated pattern; a heating layer disposed below the emissivity layer and above the insulating layer; and a power source operably linked to the heating layer,
wherein the emissivity layer comprises:
a display module comprising a plurality of pixel elements operable to display the selectably pixelated pattern in the emissivity layer, wherein each pixel element comprises:
a display segment;
a plurality of first charged pigments housed within the display segment each having a first charge;
a plurality of second charged pigments housed within the display segment each having a second charge, wherein the first charge is opposite the second charge;
an electrical contact coupled to the display segment and operable to receive signals that cause an electric field to be present in the display segment;
at least one computer-readable tangible storage medium comprising executable code that, when executed by at least one processor, is operable to transmit signals to the display module that cause an electric field to be present in at least one pixel element of the plurality of pixel elements to form the selectably pixelated pattern in the emissivity layer. 11. The infrared camouflage textile of claim 10 further comprising an insulating layer disposed on a first side of a textile and adapted to absorb a native infrared signature of a body adjacent the first side; 12. The infrared camouflage textile of claim 10 further comprising a thermal conductive or thermal foil layer disposed between the heating layer and the emissivity layer. 13. The infrared camouflage textile of claim 10 wherein the at least two different infrared emissivities create an infrared signature distinct from the native infrared signature. 14. The infrared camouflage textile of claim 10 wherein the selectably pixelated pattern comprises subpixels. 15. The infrared camouflage textile of claim 14 wherein size of the subpixels is based on a predetermined estimated resolution of and a predetermined estimated distance from an infrared camera or non-imaging thermal sensing device against which the textile is to provide camouflage. 16. The infrared camouflage textile of claim 10 further comprising a spacer or stand-off layer. 17. The infrared camouflage textile of claim 10 wherein the emissivity layer comprises at least two materials having different infrared emissivities. 18. The infrared camouflage textile of claim 10 wherein the selectably pixelated pattern is based on output of an infrared camera or non-imaging thermal sensing device. 19. The infrared camouflage textile of claim 10 further comprising a plurality of outwardly facing surfaces each displaying a portion of the selectably pixelated pattern, and the selectably pixilated pattern of each outwardly facing surface is selected based on output of an infrared camera or non-imaging thermal sensing device associated with that outwardly facing surface. | 2,800 |
11,457 | 11,457 | 14,356,186 | 2,846 | The invention relates to a method for operating a multiphase electrical machine ( 2 ) in the event of a fault, wherein the electrical machine ( 2 ) is driven with the aid of a driver circuit ( 3 ), wherein the driver circuit ( 3 ) has half-bridge circuits ( 31 ), each associated with a phase (U, V, W), and bridge paths ( 32 ) for connecting or disconnecting predetermined voltage potentials to/from the respective phases (U, V, W) of the electrical machine ( 2 ), wherein one or more of the bridge paths ( 32 ) are operated according to a first fault operating mode if a fault is detected, wherein, in the first fault operating mode, the one or more bridge paths ( 32 ) are controlled in such a manner that said paths connect a first of the predetermined voltage potentials to the phase (U, V, W) via a predetermined electrical resistor. | 1. A method for operating a multiphase electrical machine (2) in the event of a malfunction, the method comprising:
driving the electrical machine (2) with the aid of a driver circuit (3), the driver circuit (3) comprising half-bridge circuits (31), allocating each half-bridge circuit (31) to a phase (U, V, W), and electrically connecting or disconnecting predefined voltage potentials to and/or from the respective phases (U, V, W) of the electrical machine (2) via bridge branches (32), operating one or a multiple of the bridge branches (32) in in a first malfunction operation mode when a malfunction is detected, and in the first malfunction operation mode controlling the one or the multiple bridge branches (32) so that they connect a first predefined voltage potential of the predefined voltage potentials to the phase (U, V, W) by way of a predefined electrical resistance. 2. The method as claimed in claim 1, wherein the malfunction corresponds to a short circuit between two of the phases (U, V, W). 3. The method as claimed in claim 1, wherein, if one of the bridge branches (32) is defective and one phase (U, V, W) of the electrical machine (2) is permanently connected to the first predefined voltage potential, one or a multiple of the remaining bridge branches (32) that are provided for connecting or disconnecting the remaining phases (U, V, W) to and/or from the first predefined voltage potential are operated in the first malfunction operation mode,
wherein, in the first malfunction operation mode, the corresponding bridge branches (32) are controlled so that they connect the first predefined voltage potential to the phase (U, V, W) by way of a defined electrical resistance. 4. The method as claimed in claim 3, wherein the one or the multiple remaining bridge branches (32) that are provided for connecting or disconnecting the remaining phases (U, V, W) to and/or from the first predefined voltage potential are operated in the first malfunction operation mode if a rotational speed of the electrical machine (2) is below a predetermined threshold rotational speed. 5. The method as claimed in claim 3, wherein in the first malfunction operation mode the remaining bridge branches (32) that are provided for connecting or disconnecting the remaining phases (U, V, W) to and/or from a second voltage potential of the predefined voltage potentials are disconnected from the phases (U, V, W). 6. The method as claimed in claim 4, wherein the one or the multiple bridge branches (32) that are provided for connecting or disconnecting the remaining phases (U, V, W) to and/or from the first predefined voltage potential are operated in a second malfunction operation mode if a rotational speed of the electrical machine (2) is above a predetermined threshold rotational speed, wherein in the second malfunction operation mode the one or the multiple remaining bridge branches (32) are switched to be completely conductive in order to connect the remaining phases to the first predefined voltage potential. 7. The method as claimed in claim 1, wherein the defined electrical resistance of the one or the multiple bridge branches (32) that are operated in the first malfunction mode is varied in dependence upon the rotational speed and/or in dependence upon a motor current and/or in dependence upon a position of a rotor of the electrical machine (2). 8. The method as claimed in claim 1, wherein the one or the multiple bridge branches (32) comprise semiconductor switches (S1, S2, S3, S4, S5, S6) that are operated in the first malfunction operation mode in a partially controlled manner in order to form the predefined electrical resistance. 9. The method as claimed in claim 1, wherein the predefined electrical resistance is between the electrical resistance of one of the bridge branches (32) in the case of the first predefined voltage potential being connected to the respective phases (U, V, W) of the electrical machine (2) and the electrical resistance of one of the bridge branches (32) in the case of the first predefined voltage potential being disconnected from the respective phases (U, V, W) of the electrical machine (2). 10. The method as claimed in claim 9, wherein in the first malfunction operation mode the defined electrical resistance corresponds to a resistance between a half line resistance and a double line resistance of a phase line of the electrical machine (2). 11. A device for operating a multiphase electrical machine (2) in the event of a malfunction, the device comprising:
a driver circuit (3) to aid if the driving of the electrical machine (2), the driver circuit (3) comprising
half-bridge circuits (31), which are allocated in each case to a phase (U, V, W), and
bridge branches (32) for electrically connecting or disconnecting predefined voltage potentials to and/or from the respective phases (U, V, W) of the electrical machine (2),
wherein the device is configured to operate one or a multiple of the bridge branches (32) in accordance with a first malfunction operation mode when a malfunction is detected, wherein the device is configured to control the one or the multiple bridge branches (32) so that they connect a first predefined voltage potential of the predefined voltage potentials to the phase by way of a predefined electrical resistance in the first malfunction operation mode. 12. A motor system comprising:
a multiphase electrical machine (2); a driver circuit (3), half-bridge circuits (31), which are allocated in each case to a phase of the electrical machine (2), and bridge branches (32) for connecting or disconnecting predefined voltage potentials to and/or from the respective phases (U, V, W) of the electrical machine (2), and a device as claimed in claim 11. 13. A computer program product that has a program code that performs the method as claimed in claim 1 if said program code is implemented on a data processing device. 14. The method as claimed in claim 1, wherein the malfunction corresponds to a short circuit of a phase (U, V, W) to a voltage potential. 15. The method as claimed in claim 1, wherein the malfunction corresponds to a voltage potential or a permanently open bridge branch. 16. The method as claimed in claim 1, wherein the defined electrical resistance of the one or the multiple bridge branches (32) that are operated in the first malfunction mode is varied in dependence upon the rotational speed. 17. The method as claimed in claim 1, wherein the defined electrical resistance of the one or the multiple bridge branches (32) that are operated in the first malfunction mode is varied in dependence upon a motor current. 18. The method as claimed in claim 1, wherein the defined electrical resistance of the one or the multiple bridge branches (32) that are operated in the first malfunction mode is varied in dependence upon a position of a rotor of the electrical machine (2). | The invention relates to a method for operating a multiphase electrical machine ( 2 ) in the event of a fault, wherein the electrical machine ( 2 ) is driven with the aid of a driver circuit ( 3 ), wherein the driver circuit ( 3 ) has half-bridge circuits ( 31 ), each associated with a phase (U, V, W), and bridge paths ( 32 ) for connecting or disconnecting predetermined voltage potentials to/from the respective phases (U, V, W) of the electrical machine ( 2 ), wherein one or more of the bridge paths ( 32 ) are operated according to a first fault operating mode if a fault is detected, wherein, in the first fault operating mode, the one or more bridge paths ( 32 ) are controlled in such a manner that said paths connect a first of the predetermined voltage potentials to the phase (U, V, W) via a predetermined electrical resistor.1. A method for operating a multiphase electrical machine (2) in the event of a malfunction, the method comprising:
driving the electrical machine (2) with the aid of a driver circuit (3), the driver circuit (3) comprising half-bridge circuits (31), allocating each half-bridge circuit (31) to a phase (U, V, W), and electrically connecting or disconnecting predefined voltage potentials to and/or from the respective phases (U, V, W) of the electrical machine (2) via bridge branches (32), operating one or a multiple of the bridge branches (32) in in a first malfunction operation mode when a malfunction is detected, and in the first malfunction operation mode controlling the one or the multiple bridge branches (32) so that they connect a first predefined voltage potential of the predefined voltage potentials to the phase (U, V, W) by way of a predefined electrical resistance. 2. The method as claimed in claim 1, wherein the malfunction corresponds to a short circuit between two of the phases (U, V, W). 3. The method as claimed in claim 1, wherein, if one of the bridge branches (32) is defective and one phase (U, V, W) of the electrical machine (2) is permanently connected to the first predefined voltage potential, one or a multiple of the remaining bridge branches (32) that are provided for connecting or disconnecting the remaining phases (U, V, W) to and/or from the first predefined voltage potential are operated in the first malfunction operation mode,
wherein, in the first malfunction operation mode, the corresponding bridge branches (32) are controlled so that they connect the first predefined voltage potential to the phase (U, V, W) by way of a defined electrical resistance. 4. The method as claimed in claim 3, wherein the one or the multiple remaining bridge branches (32) that are provided for connecting or disconnecting the remaining phases (U, V, W) to and/or from the first predefined voltage potential are operated in the first malfunction operation mode if a rotational speed of the electrical machine (2) is below a predetermined threshold rotational speed. 5. The method as claimed in claim 3, wherein in the first malfunction operation mode the remaining bridge branches (32) that are provided for connecting or disconnecting the remaining phases (U, V, W) to and/or from a second voltage potential of the predefined voltage potentials are disconnected from the phases (U, V, W). 6. The method as claimed in claim 4, wherein the one or the multiple bridge branches (32) that are provided for connecting or disconnecting the remaining phases (U, V, W) to and/or from the first predefined voltage potential are operated in a second malfunction operation mode if a rotational speed of the electrical machine (2) is above a predetermined threshold rotational speed, wherein in the second malfunction operation mode the one or the multiple remaining bridge branches (32) are switched to be completely conductive in order to connect the remaining phases to the first predefined voltage potential. 7. The method as claimed in claim 1, wherein the defined electrical resistance of the one or the multiple bridge branches (32) that are operated in the first malfunction mode is varied in dependence upon the rotational speed and/or in dependence upon a motor current and/or in dependence upon a position of a rotor of the electrical machine (2). 8. The method as claimed in claim 1, wherein the one or the multiple bridge branches (32) comprise semiconductor switches (S1, S2, S3, S4, S5, S6) that are operated in the first malfunction operation mode in a partially controlled manner in order to form the predefined electrical resistance. 9. The method as claimed in claim 1, wherein the predefined electrical resistance is between the electrical resistance of one of the bridge branches (32) in the case of the first predefined voltage potential being connected to the respective phases (U, V, W) of the electrical machine (2) and the electrical resistance of one of the bridge branches (32) in the case of the first predefined voltage potential being disconnected from the respective phases (U, V, W) of the electrical machine (2). 10. The method as claimed in claim 9, wherein in the first malfunction operation mode the defined electrical resistance corresponds to a resistance between a half line resistance and a double line resistance of a phase line of the electrical machine (2). 11. A device for operating a multiphase electrical machine (2) in the event of a malfunction, the device comprising:
a driver circuit (3) to aid if the driving of the electrical machine (2), the driver circuit (3) comprising
half-bridge circuits (31), which are allocated in each case to a phase (U, V, W), and
bridge branches (32) for electrically connecting or disconnecting predefined voltage potentials to and/or from the respective phases (U, V, W) of the electrical machine (2),
wherein the device is configured to operate one or a multiple of the bridge branches (32) in accordance with a first malfunction operation mode when a malfunction is detected, wherein the device is configured to control the one or the multiple bridge branches (32) so that they connect a first predefined voltage potential of the predefined voltage potentials to the phase by way of a predefined electrical resistance in the first malfunction operation mode. 12. A motor system comprising:
a multiphase electrical machine (2); a driver circuit (3), half-bridge circuits (31), which are allocated in each case to a phase of the electrical machine (2), and bridge branches (32) for connecting or disconnecting predefined voltage potentials to and/or from the respective phases (U, V, W) of the electrical machine (2), and a device as claimed in claim 11. 13. A computer program product that has a program code that performs the method as claimed in claim 1 if said program code is implemented on a data processing device. 14. The method as claimed in claim 1, wherein the malfunction corresponds to a short circuit of a phase (U, V, W) to a voltage potential. 15. The method as claimed in claim 1, wherein the malfunction corresponds to a voltage potential or a permanently open bridge branch. 16. The method as claimed in claim 1, wherein the defined electrical resistance of the one or the multiple bridge branches (32) that are operated in the first malfunction mode is varied in dependence upon the rotational speed. 17. The method as claimed in claim 1, wherein the defined electrical resistance of the one or the multiple bridge branches (32) that are operated in the first malfunction mode is varied in dependence upon a motor current. 18. The method as claimed in claim 1, wherein the defined electrical resistance of the one or the multiple bridge branches (32) that are operated in the first malfunction mode is varied in dependence upon a position of a rotor of the electrical machine (2). | 2,800 |
11,458 | 11,458 | 14,881,477 | 2,811 | First trenches extend from a process surface into a semiconductor layer. An alignment layer with mask pits in a with respect to the process surface vertical projection of the first trenches is formed on the process surface. Sidewalls of the mask pits have a smaller tilt angle with respect to the process surface than sidewalls of the first trenches. The mask pits are filled with an auxiliary material. A gate trench for a gate structure is formed in a mesa section of the semiconductor layer between the first trenches, wherein the auxiliary material is used as an etch mask. | 1. A method of manufacturing a semiconductor device, the method comprising:
forming first trenches extending from a process surface into a semiconductor layer; forming, on the process surface, an alignment layer comprising mask pits in a with respect to the process surface vertical projection of the first trenches, wherein sidewalls of the mask pits have a smaller tilt angle with respect to the process surface than sidewalls of the first trenches; filling the mask pits with an auxiliary material; and forming, by using the auxiliary material as an etch mask, a gate trench for a gate structure in a mesa section of the semiconductor layer between the first trenches. 2. The method of claim 1, wherein
forming the first trenches comprises forming field electrode structures extending from the process surface into the semiconductor layer and forming the first trenches in portions of the field electrode structures. 3. The method of claim 2, wherein
forming the field electrode structures comprises forming field electrodes and field dielectrics separating the field electrodes from the mesa section and forming the first trenches in the field dielectrics. 4. The method of claim 1, wherein
forming the first trenches comprises forming recesses and filling first portions of the recesses with a conductive material, wherein remaining second portions of the recesses form the first trenches. 5. The method of claim 4, wherein
the conductive material comprises at least one of a metal, a conductive metal compound and a metal alloy. 6. The method of claim 1, wherein
the tilt angle of the sidewalls of the mask pits with respect to the process surface is between 30 degree and 60 degree. 7. The method of claim 1, wherein
the alignment layer is formed by a high density plasma deposition of silicon oxide. 8. The method of claim 1, wherein
at an exposed surface of the alignment layer a distance between neighboring mask pits in the vertical projection of the mesa section is at least 20 nm. 9. The method of claim 1, wherein
before forming the alignment layer, a depth of the first trenches is at least 80 nm. 10. The method of claim 1, further comprising
removing the auxiliary material and depositing a dielectric layer on the alignment layer, wherein the dielectric layer fills the mask pits. 11. The method of claim 1, further comprising
forming gate structures in the gate trenches. 12. The method of claim 1, wherein
forming the gate trench comprises forming a mask opening in the alignment layer by using the auxiliary material as an etch mask. 13. The method of claim 12, further comprising
forming auxiliary spacers along sidewalls of the mask opening. 14. The method of claim 12, further comprising
forming a gate contact in a portion of the mask opening. 15. A semiconductor device comprising:
a gate structure extending from a first surface of a semiconductor portion into a mesa section between neighboring field electrode structures; and an alignment layer formed on the first surface, wherein the alignment layer comprises mask pits in a with respect to the first surface vertical projection of portions of the field electrode structures, sidewalls of the mask pits have a smaller tilt angle with respect to the first surface than sidewalls of the field electrode structures, and the gate structure is in the vertical projection of a gap between neighboring mask pits. 16. The semiconductor device of claim 15, wherein
the field electrode structures comprise a field electrode and a field dielectric, respectively, and the field dielectrics separate the field electrodes from a material of the semiconductor portion. 17. The semiconductor device of claim 16, further comprising
a buried contact formed at a distance to the first surface and directly adjoining the mesa section and one of the field electrodes. 18. The semiconductor device of claim 15, wherein
the tilt angle of the sidewalls of the mask pits with respect to the first surface is between 30 degree and 60 degree. 19. The semiconductor device of claim 15, wherein
the alignment layer is formed by high density plasma deposition of silicon oxide. 20. The semiconductor device of claim 15, further comprising
an auxiliary spacer formed along sidewalls of mask openings in the alignment layer between neighboring mask pits. | First trenches extend from a process surface into a semiconductor layer. An alignment layer with mask pits in a with respect to the process surface vertical projection of the first trenches is formed on the process surface. Sidewalls of the mask pits have a smaller tilt angle with respect to the process surface than sidewalls of the first trenches. The mask pits are filled with an auxiliary material. A gate trench for a gate structure is formed in a mesa section of the semiconductor layer between the first trenches, wherein the auxiliary material is used as an etch mask.1. A method of manufacturing a semiconductor device, the method comprising:
forming first trenches extending from a process surface into a semiconductor layer; forming, on the process surface, an alignment layer comprising mask pits in a with respect to the process surface vertical projection of the first trenches, wherein sidewalls of the mask pits have a smaller tilt angle with respect to the process surface than sidewalls of the first trenches; filling the mask pits with an auxiliary material; and forming, by using the auxiliary material as an etch mask, a gate trench for a gate structure in a mesa section of the semiconductor layer between the first trenches. 2. The method of claim 1, wherein
forming the first trenches comprises forming field electrode structures extending from the process surface into the semiconductor layer and forming the first trenches in portions of the field electrode structures. 3. The method of claim 2, wherein
forming the field electrode structures comprises forming field electrodes and field dielectrics separating the field electrodes from the mesa section and forming the first trenches in the field dielectrics. 4. The method of claim 1, wherein
forming the first trenches comprises forming recesses and filling first portions of the recesses with a conductive material, wherein remaining second portions of the recesses form the first trenches. 5. The method of claim 4, wherein
the conductive material comprises at least one of a metal, a conductive metal compound and a metal alloy. 6. The method of claim 1, wherein
the tilt angle of the sidewalls of the mask pits with respect to the process surface is between 30 degree and 60 degree. 7. The method of claim 1, wherein
the alignment layer is formed by a high density plasma deposition of silicon oxide. 8. The method of claim 1, wherein
at an exposed surface of the alignment layer a distance between neighboring mask pits in the vertical projection of the mesa section is at least 20 nm. 9. The method of claim 1, wherein
before forming the alignment layer, a depth of the first trenches is at least 80 nm. 10. The method of claim 1, further comprising
removing the auxiliary material and depositing a dielectric layer on the alignment layer, wherein the dielectric layer fills the mask pits. 11. The method of claim 1, further comprising
forming gate structures in the gate trenches. 12. The method of claim 1, wherein
forming the gate trench comprises forming a mask opening in the alignment layer by using the auxiliary material as an etch mask. 13. The method of claim 12, further comprising
forming auxiliary spacers along sidewalls of the mask opening. 14. The method of claim 12, further comprising
forming a gate contact in a portion of the mask opening. 15. A semiconductor device comprising:
a gate structure extending from a first surface of a semiconductor portion into a mesa section between neighboring field electrode structures; and an alignment layer formed on the first surface, wherein the alignment layer comprises mask pits in a with respect to the first surface vertical projection of portions of the field electrode structures, sidewalls of the mask pits have a smaller tilt angle with respect to the first surface than sidewalls of the field electrode structures, and the gate structure is in the vertical projection of a gap between neighboring mask pits. 16. The semiconductor device of claim 15, wherein
the field electrode structures comprise a field electrode and a field dielectric, respectively, and the field dielectrics separate the field electrodes from a material of the semiconductor portion. 17. The semiconductor device of claim 16, further comprising
a buried contact formed at a distance to the first surface and directly adjoining the mesa section and one of the field electrodes. 18. The semiconductor device of claim 15, wherein
the tilt angle of the sidewalls of the mask pits with respect to the first surface is between 30 degree and 60 degree. 19. The semiconductor device of claim 15, wherein
the alignment layer is formed by high density plasma deposition of silicon oxide. 20. The semiconductor device of claim 15, further comprising
an auxiliary spacer formed along sidewalls of mask openings in the alignment layer between neighboring mask pits. | 2,800 |
11,459 | 11,459 | 15,014,847 | 2,884 | A high-resolution imaging approach is described. The described approach includes use of a small focal spot size and positioning of the patient offset from the center of the imaging volume. The off-center displacement is combined with a small focal spot size and with modified image reconstruction methods to provide high intrinsic spatial resolution without hardware changes to the imaging system. | 1. A method for generating a high-resolution image, comprising:
specifying a focal spot size for an X-ray source of an imaging system that is less than the size of a detector cell of a detector of the imaging system; positioning a region-of-interest of an imaged subject so the region-of-interest is offset from an iso-center of a field-of-view of the imaging system; acquiring a first set of projection data over a limited angular range that is less than 180°+α, wherein the X-ray source moves in the limited angular range on a first side of the field-of-view containing the region of interest when acquiring the first set of projection data; changing one or both of a relative orientation of the region-of-interest or a relative position of the region-of interest within the field-of-view, wherein the region-of-interest remains offset from the iso-center after the change to its orientation or position; acquiring a second set of projection data over the limited angular range, wherein the X-ray source moves in the limited angular range on a second side of the field-of-view containing the region of interest when acquiring the second set of projection data; registering at least the first set of projection data and the second set of projection data to generate registered projection data; and reconstructing the registered projection data to generate an image. 2. The method of claim 1, wherein the focal spot size is less than 1 mm. 3. The method of claim 1, wherein the focal spot size is less than half the detector cell size. 4. The method of claim 1, wherein the region-of-interest is offset 20 cm to 30 cm toward the edge of the 40 to 60 cm field-of-view or towards the edge of the 60 cm to 90 cm bore opening. 5. The method of claim 1, wherein changing one or both of a relative orientation of the region-of-interest or a relative position of the region-of interest within the field-of-view comprises moving or turning the imaged subject within a gantry of a CT imaging system. 6. The method of claim 1, wherein changing one or both of a relative orientation of the region-of-interest or a relative position of the region-of interest within the field-of-view comprises repositioning a C-arm to which the X-ray source and the detector are attached. 7. The method of claim 1, wherein the imaged subject comprises a patient, a package, a piece of baggage, a material sample, or a manufactured part. 8. The method of claim 1, wherein reconstructing the registered projection data comprises reconstructing the registered projection data using an iterative reconstruction. 9. The method of claim 1, wherein reconstructing the registered projection data comprises initially generating low-quality images and combining high-frequency information obtained at different orientations in the frequency domain to generate the image. 10. The method of claim 1, wherein reconstructing the registered projection data comprises generating a synthetic or merged sinogram and reconstructing the image from the synthetic or merged sinogram. 11. The method of claim 1, comprising:
acquiring additional sets of projection data over the limited angular range after again changing one or both of a relative orientation of the region-of-interest or a relative position of the region-of interest within the field-of-view; and registering the additional sets of projection data with the first set of projection data and the second set of projection data to generate registered projection data. 12. The method of claim 1, wherein the limited angular ranges, when summed, correspond to angular range of at least 180° plus a fan angle α. 13. An imaging system, comprising:
a detector comprising a plurality of detector cells; an X-ray source configured to generate X-rays at a focal spot; an imaging volume about which the detector and X-ray source rotate, wherein the imaging volume comprises a field-of-view centered about an iso-center; a system controller configured to operate the X-ray source and detector, wherein the system controller, during two or more scan operations:
controls the X-ray source to have a focal spot size less than a detector cell size; and
rotates the X-ray source and detector about a region-of-interest that is offset from the iso-center, wherein for each of a plurality of scans the X-ray source and detector are rotated over a respective limited angular range on a side of the field of view where the region-of-interest is offset and wherein the region-of-interest is moved or re-oriented between scans;
image processing circuitry configured to reconstruct registered projection data acquired over the respective limited angular range scans. 14. The imaging system of claim 13, wherein the focal spot size is less than 1 mm. 15. The imaging system of claim 13, wherein the imaging system comprises a computed tomography imaging system or a C-arm imaging system. 16. The imaging system of claim 13, wherein the image processing circuitry reconstructs the registered projection data using an iterative reconstruction algorithm. 17. The imaging system of claim 13, wherein the image processing circuitry reconstructs the registered projection data using complementary frequency data derived from different scans. 18. The imaging system of claim 13, wherein the image processing circuitry reconstructs the registered projection data using a synthetic or merged sinogram derived from different scans. 19. A method for generating a high-resolution image, comprising:
performing a plurality of X-ray scan operations, each scan operation is performed over a limited angular range with respect to a field-of-view, wherein a region-of-interest being imaged is offset from a center of the field-of-view during each scan operation and is differently positioned or oriented during each scan operation; controlling a focal spot size from which X-rays are emitted during each scan operation so that the focal spot is less than 1 mm×1 mm during each scan operation; registering and reconstructing projection data acquired during each scan operation to generate an image. 20. The method of claim 19, wherein the scan operations, when considered together, have an aggregate angular range of at least 180° plus a fan angle α. | A high-resolution imaging approach is described. The described approach includes use of a small focal spot size and positioning of the patient offset from the center of the imaging volume. The off-center displacement is combined with a small focal spot size and with modified image reconstruction methods to provide high intrinsic spatial resolution without hardware changes to the imaging system.1. A method for generating a high-resolution image, comprising:
specifying a focal spot size for an X-ray source of an imaging system that is less than the size of a detector cell of a detector of the imaging system; positioning a region-of-interest of an imaged subject so the region-of-interest is offset from an iso-center of a field-of-view of the imaging system; acquiring a first set of projection data over a limited angular range that is less than 180°+α, wherein the X-ray source moves in the limited angular range on a first side of the field-of-view containing the region of interest when acquiring the first set of projection data; changing one or both of a relative orientation of the region-of-interest or a relative position of the region-of interest within the field-of-view, wherein the region-of-interest remains offset from the iso-center after the change to its orientation or position; acquiring a second set of projection data over the limited angular range, wherein the X-ray source moves in the limited angular range on a second side of the field-of-view containing the region of interest when acquiring the second set of projection data; registering at least the first set of projection data and the second set of projection data to generate registered projection data; and reconstructing the registered projection data to generate an image. 2. The method of claim 1, wherein the focal spot size is less than 1 mm. 3. The method of claim 1, wherein the focal spot size is less than half the detector cell size. 4. The method of claim 1, wherein the region-of-interest is offset 20 cm to 30 cm toward the edge of the 40 to 60 cm field-of-view or towards the edge of the 60 cm to 90 cm bore opening. 5. The method of claim 1, wherein changing one or both of a relative orientation of the region-of-interest or a relative position of the region-of interest within the field-of-view comprises moving or turning the imaged subject within a gantry of a CT imaging system. 6. The method of claim 1, wherein changing one or both of a relative orientation of the region-of-interest or a relative position of the region-of interest within the field-of-view comprises repositioning a C-arm to which the X-ray source and the detector are attached. 7. The method of claim 1, wherein the imaged subject comprises a patient, a package, a piece of baggage, a material sample, or a manufactured part. 8. The method of claim 1, wherein reconstructing the registered projection data comprises reconstructing the registered projection data using an iterative reconstruction. 9. The method of claim 1, wherein reconstructing the registered projection data comprises initially generating low-quality images and combining high-frequency information obtained at different orientations in the frequency domain to generate the image. 10. The method of claim 1, wherein reconstructing the registered projection data comprises generating a synthetic or merged sinogram and reconstructing the image from the synthetic or merged sinogram. 11. The method of claim 1, comprising:
acquiring additional sets of projection data over the limited angular range after again changing one or both of a relative orientation of the region-of-interest or a relative position of the region-of interest within the field-of-view; and registering the additional sets of projection data with the first set of projection data and the second set of projection data to generate registered projection data. 12. The method of claim 1, wherein the limited angular ranges, when summed, correspond to angular range of at least 180° plus a fan angle α. 13. An imaging system, comprising:
a detector comprising a plurality of detector cells; an X-ray source configured to generate X-rays at a focal spot; an imaging volume about which the detector and X-ray source rotate, wherein the imaging volume comprises a field-of-view centered about an iso-center; a system controller configured to operate the X-ray source and detector, wherein the system controller, during two or more scan operations:
controls the X-ray source to have a focal spot size less than a detector cell size; and
rotates the X-ray source and detector about a region-of-interest that is offset from the iso-center, wherein for each of a plurality of scans the X-ray source and detector are rotated over a respective limited angular range on a side of the field of view where the region-of-interest is offset and wherein the region-of-interest is moved or re-oriented between scans;
image processing circuitry configured to reconstruct registered projection data acquired over the respective limited angular range scans. 14. The imaging system of claim 13, wherein the focal spot size is less than 1 mm. 15. The imaging system of claim 13, wherein the imaging system comprises a computed tomography imaging system or a C-arm imaging system. 16. The imaging system of claim 13, wherein the image processing circuitry reconstructs the registered projection data using an iterative reconstruction algorithm. 17. The imaging system of claim 13, wherein the image processing circuitry reconstructs the registered projection data using complementary frequency data derived from different scans. 18. The imaging system of claim 13, wherein the image processing circuitry reconstructs the registered projection data using a synthetic or merged sinogram derived from different scans. 19. A method for generating a high-resolution image, comprising:
performing a plurality of X-ray scan operations, each scan operation is performed over a limited angular range with respect to a field-of-view, wherein a region-of-interest being imaged is offset from a center of the field-of-view during each scan operation and is differently positioned or oriented during each scan operation; controlling a focal spot size from which X-rays are emitted during each scan operation so that the focal spot is less than 1 mm×1 mm during each scan operation; registering and reconstructing projection data acquired during each scan operation to generate an image. 20. The method of claim 19, wherein the scan operations, when considered together, have an aggregate angular range of at least 180° plus a fan angle α. | 2,800 |
11,460 | 11,460 | 14,756,700 | 2,853 | A drum tank gauge device is disclosed in which the device comprises a housing having a level indication display, an audible alarm, and a visual alarm, a level sensor shaft having a capacitance sensor positioned at an end which is inserted into a drum, and a threaded cap for securing the housing and the level sensor shaft in place. | 1. A drum tank gauge device for use in measuring the quantity of petroleum products in a drum tank, comprising:
a housing having a level indication display, an audible alarm, and a visual alarm; a level sensor shaft having a capacitance sensor positioned at an end which is inserted into a drum; and a threaded cap for securing the housing and the level sensor shaft in place. 2. The drum tank gauge device of claim 1 wherein the level indication display comprises a first LED for indicating 90% capacity, a second LED for indicating 75% capacity, a third LED for indicating 50% capacity, a fourth LED for indicating 25% capacity, and a fifth LED for indicating 5% capacity. 3. The drum tank gauge device of claim 1 wherein the visual alarm is an LED. 4. The drum tank gauge device of claim 1 wherein the audible alarm is a speaker. 5. The drum tank gauge device of claim 1 wherein the housing further comprises a side having a touch sensitive switch for operating the drum tank gauge device. 6. The drum tank gauge device of claim 1 wherein the housing further comprises a switch for muting the operation of the audible alarm. 7. The drum tank gauge device of claim 1 further comprising a battery positioned within the housing for powering the drum tank gauge device. 8. A drum tank gauge device for use in measuring the quantity of petroleum products in a drum tank, comprising:
a housing having a level indication display, an audible alarm, and a visual alarm; a level sensor shaft having a capacitance sensor positioned at an end which is inserted into a drum; an integrated circuit connected to the level indication display, the audible alarm, the visual alarm, and the capacitance sensor; and a threaded cap for securing the housing and the level sensor shaft in place. 9. The drum tank gauge device of claim 8 wherein the level indication display comprises a first LED for indicating 90% capacity, a second LED for indicating 75% capacity, a third LED for indicating 50% capacity, a fourth LED for indicating 25% capacity, and a fifth LED for indicating 5% capacity. 10. The drum tank gauge device of claim 8 wherein the housing further comprises a side having a switch connected to the integrated circuit, operation of the switch for actuating the capacitance sensor for providing a signal to the integrated circuit for the integrated circuit to determine a level of contents within a drum. 11. The drum tank gauge device of claim 10 wherein the switch is a touch sensitive switch. 12. The drum tank gauge device of claim 8 wherein the visual alarm is an LED. 13. The drum tank gauge device of claim 8 wherein the audible alarm is a buzzer. 14. The drum tank gauge device of claim 8 wherein the housing further comprises a switch for muting the operation of the audible alarm. 15. The drum tank gauge device of claim 8 further comprising a battery positioned within the housing for providing power to the integrated circuit. 16. A drum tank gauge device for use in measuring the quantity of petroleum products in a drum tank, comprising:
a housing having a level indication display, an audible alarm, a visual alarm, a first switch, and a second switch; a level sensor shaft having a capacitance sensor positioned at an end which is inserted into a drum; an integrated circuit connected to the level indication display, the audible alarm, the visual alarm, the first switch, the second switch, and the capacitance sensor; and a threaded cap for securing the housing and the level sensor shaft in place. 17. The drum tank gauge device of claim 16 wherein the level indication display comprises a first LED for indicating 90% capacity, a second LED for indicating 75% capacity, a third LED for indicating 50% capacity, a fourth LED for indicating 25% capacity, and a fifth LED for indicating 5% capacity. 18. The drum tank gauge device of claim 16 wherein operation of the first switch actuates the capacitance sensor for providing a signal to the integrated circuit for the integrated circuit to determine a level of contents within the drum. 19. The drum tank gauge device of claim 16 wherein operation of the second switch actuates the capacitance sensor for providing a signal to the integrated circuit for the integrated circuit to determine a level of contents within the drum. 20. The drum tank gauge device of claim 16 wherein the housing further comprises a switch for muting the operation of the audible alarm. | A drum tank gauge device is disclosed in which the device comprises a housing having a level indication display, an audible alarm, and a visual alarm, a level sensor shaft having a capacitance sensor positioned at an end which is inserted into a drum, and a threaded cap for securing the housing and the level sensor shaft in place.1. A drum tank gauge device for use in measuring the quantity of petroleum products in a drum tank, comprising:
a housing having a level indication display, an audible alarm, and a visual alarm; a level sensor shaft having a capacitance sensor positioned at an end which is inserted into a drum; and a threaded cap for securing the housing and the level sensor shaft in place. 2. The drum tank gauge device of claim 1 wherein the level indication display comprises a first LED for indicating 90% capacity, a second LED for indicating 75% capacity, a third LED for indicating 50% capacity, a fourth LED for indicating 25% capacity, and a fifth LED for indicating 5% capacity. 3. The drum tank gauge device of claim 1 wherein the visual alarm is an LED. 4. The drum tank gauge device of claim 1 wherein the audible alarm is a speaker. 5. The drum tank gauge device of claim 1 wherein the housing further comprises a side having a touch sensitive switch for operating the drum tank gauge device. 6. The drum tank gauge device of claim 1 wherein the housing further comprises a switch for muting the operation of the audible alarm. 7. The drum tank gauge device of claim 1 further comprising a battery positioned within the housing for powering the drum tank gauge device. 8. A drum tank gauge device for use in measuring the quantity of petroleum products in a drum tank, comprising:
a housing having a level indication display, an audible alarm, and a visual alarm; a level sensor shaft having a capacitance sensor positioned at an end which is inserted into a drum; an integrated circuit connected to the level indication display, the audible alarm, the visual alarm, and the capacitance sensor; and a threaded cap for securing the housing and the level sensor shaft in place. 9. The drum tank gauge device of claim 8 wherein the level indication display comprises a first LED for indicating 90% capacity, a second LED for indicating 75% capacity, a third LED for indicating 50% capacity, a fourth LED for indicating 25% capacity, and a fifth LED for indicating 5% capacity. 10. The drum tank gauge device of claim 8 wherein the housing further comprises a side having a switch connected to the integrated circuit, operation of the switch for actuating the capacitance sensor for providing a signal to the integrated circuit for the integrated circuit to determine a level of contents within a drum. 11. The drum tank gauge device of claim 10 wherein the switch is a touch sensitive switch. 12. The drum tank gauge device of claim 8 wherein the visual alarm is an LED. 13. The drum tank gauge device of claim 8 wherein the audible alarm is a buzzer. 14. The drum tank gauge device of claim 8 wherein the housing further comprises a switch for muting the operation of the audible alarm. 15. The drum tank gauge device of claim 8 further comprising a battery positioned within the housing for providing power to the integrated circuit. 16. A drum tank gauge device for use in measuring the quantity of petroleum products in a drum tank, comprising:
a housing having a level indication display, an audible alarm, a visual alarm, a first switch, and a second switch; a level sensor shaft having a capacitance sensor positioned at an end which is inserted into a drum; an integrated circuit connected to the level indication display, the audible alarm, the visual alarm, the first switch, the second switch, and the capacitance sensor; and a threaded cap for securing the housing and the level sensor shaft in place. 17. The drum tank gauge device of claim 16 wherein the level indication display comprises a first LED for indicating 90% capacity, a second LED for indicating 75% capacity, a third LED for indicating 50% capacity, a fourth LED for indicating 25% capacity, and a fifth LED for indicating 5% capacity. 18. The drum tank gauge device of claim 16 wherein operation of the first switch actuates the capacitance sensor for providing a signal to the integrated circuit for the integrated circuit to determine a level of contents within the drum. 19. The drum tank gauge device of claim 16 wherein operation of the second switch actuates the capacitance sensor for providing a signal to the integrated circuit for the integrated circuit to determine a level of contents within the drum. 20. The drum tank gauge device of claim 16 wherein the housing further comprises a switch for muting the operation of the audible alarm. | 2,800 |
11,461 | 11,461 | 15,194,393 | 2,853 | An image processing device ( 100 ) includes a non-discharge correction processing unit ( 114 ) that performs an image correction process for correcting an image defect caused by a non-discharge nozzle in an inkjet head and includes, as different files, a first halftone processing program file ( 152 ) that performs first halftone processing for a normal portion, which is an image region other than a non-discharge correction portion to be subjected to non-discharge correction and a non-discharge portion, and a second halftone processing program file ( 154 ) that performs second halftone processing for the non-discharge correction portion. The image processing device executes the first halftone processing program file ( 152 ) for the normal portion in an input image ( 102 ) and executes the second halftone processing program file ( 154 ) for the non-discharge correction portion, thereby obtaining a non-discharge-corrected halftone image ( 104 ). | 1. An image processing device comprising:
a non-discharge correction processing unit that performs an image correction process for correcting an image defect caused by a non-discharge nozzle in an inkjet head including a plurality of nozzles; at least one first halftone processing program file that performs first halftone processing for a normal portion, which is an image region other than a non-discharge correction portion to be subjected to the image correction process by the non-discharge correction processing unit and a non-discharge portion in which recording is not possible due to the non-discharge nozzle, to generate a first halftone image; and at least one second halftone processing program file that is different from the first halftone processing program file and performs second halftone processing, which is different from the first halftone processing, for the non-discharge correction portion to generate a second halftone image, wherein the first halftone processing program file is executed for the normal portion of an input image and the second halftone processing program file is executed for the non-discharge correction portion of the input image. 2. The image processing device according to claim 1, further comprising:
a non-discharge portion information storage unit that stores non-discharge portion information corresponding to a position of the non-discharge nozzle; an image region discrimination unit that discriminates between the normal portion and the non-discharge correction portion in the input image, on the basis of the non-discharge portion information; and a halftone processing switching unit that executes the first halftone processing program file and the second halftone processing program file for the normal portion and the non-discharge correction portion, respectively, on the basis of a determination result of the image region discrimination unit, to switch halftone processing to be applied to the normal portion and the non-discharge correction portion. 3. The image processing device according to claim 1, further comprising:
a non-discharge portion information storage unit that stores non-discharge portion information corresponding to a position of the non-discharge nozzle; an image division processing unit that divides the input image into the normal portion and the non-discharge correction portion on the basis of the non-discharge portion information; and an integration processing unit that integrates the first halftone image obtained by the execution of the first halftone processing program file for the normal portion divided by the image division processing unit with the second halftone image obtained by the execution of the second halftone processing program file for the non-discharge correction portion divided by the image division processing unit. 4. The image processing device according to claim 1,
wherein an algorithm of the first halftone processing by the first halftone processing program file is different from an algorithm of the second halftone processing by the second halftone processing program file. 5. The image processing device according to claim 4,
wherein the second halftone processing is performed by the second halftone processing program file using a dither mask. 6. The image processing device according to claim 1,
wherein the first halftone processing for the normal portion and the second halftone processing for the non-discharge correction portion are performed at different times, the frequency of the second halftone processing for the non-discharge correction portion is higher than the frequency of the first halftone processing for the normal portion, or the number of times the second halftone processing is performed for the non-discharge correction portion is larger than the number of times the first halftone processing is performed for the normal portion. 7. The image processing device according to claim 6, further comprising:
a first halftone image storage unit that stores the first halftone image obtained by the execution of the first halftone processing for the normal portion, wherein a process which integrates the second halftone image of the non-discharge correction portion that is sequentially created by performing the second halftone processing for the non-discharge correction portion according to a state of the non-discharge nozzle in the inkjet head with the first halftone image that is stored in the first halftone image storage unit in advance is performed. 8. The image processing device according to claim 1,
wherein data created by the first halftone processing is given as an input to the second halftone processing. 9. The image processing device according to claim 8, further comprising:
an arithmetic processing unit, wherein data of the first halftone image of the normal portion created by the first halftone processing is given as an input to the second halftone processing, the arithmetic processing unit applies a blur function to the first halftone image which is given as the input to the second halftone processing, and the second halftone processing is performed for data obtained by applying the blur function to the first halftone image. 10. The image processing device according to claim 9,
wherein the blur function is a Dooley's visual transfer function. 11. The image processing device according to claim 8,
wherein the data which is created by the first halftone processing and is given as the input to the second halftone processing is a cumulative error which is generated by an error diffusion process in the first halftone processing, and the second halftone processing program file performs the error diffusion process in the non-discharge correction portion, using the cumulative error as initial error data. 12. The image processing device according to claim 8,
wherein the second halftone processing program file performs the second halftone processing for the non-discharge correction portion, using the input image in addition to the data created by the first halftone processing. 13. The image processing device according to claim 12,
wherein, in the second halftone processing, a process that arranges no dots is performed in a case in which a signal value of a pixel to be processed which corresponds to the non-discharge correction portion of the input image is equal to a specific value or a process that certainly arranges dots is performed in a case in which the signal value of the pixel to be process is equal to or less than the specific value. 14. The image processing device according to claim 1,
wherein a plurality of the second halftone processing program files that can be applied to the second halftone processing for the non-discharge correction portion are provided. 15. The image processing device according to claim 14, further comprising:
a user interface that enables a user to select a second halftone processing program file used for the second halftone processing from the plurality of second halftone processing program files. 16. The image processing device according to claim 1,
wherein the inkjet head is a line head used in an inkjet printing system that records an image using a single-pass method, and the non-discharge correction portion is an image region including pixel rows which are adjacent to both sides of a pixel row of the non-discharge portion. 17. An image processing method comprising:
a non-discharge correction processing step of performing an image correction process for correcting an image defect caused by a non-discharge nozzle in an inkjet head including a plurality of nozzles; a first halftone processing step of executing a first halftone processing program file to perform first halftone processing for a normal portion, which is an image region other than a non-discharge correction portion to be subjected to the image correction process in the non-discharge correction processing step and a non-discharge portion in which recording is not possible due to the non-discharge nozzle in an input image, thereby generating a first halftone image; and a second halftone processing step of executing a second halftone processing program file that is different from the first halftone processing program file to perform second halftone processing, which is different from the first halftone processing, for the non-discharge correction portion in the input image, thereby generating a second halftone image. 18. A non-transitory computer-readable recording medium storing commands that are read by a computer and cause the computer to perform:
a non-discharge correction processing step of performing an image correction process for correcting an image defect caused by a non-discharge nozzle in an inkjet head including a plurality of nozzles; a first halftone processing step of executing a first halftone processing program file to perform first halftone processing for a normal portion, which is an image region other than a non-discharge correction portion to be subjected to the image correction process in the non-discharge correction processing step and a non-discharge portion in which recording is not possible due to the non-discharge nozzle in an input image, thereby generating a first halftone image; and a second halftone processing step of executing a second halftone processing program file that is different from the first halftone processing program file to perform second halftone processing, which is different from the first halftone processing, for the non-discharge correction portion in the input image, thereby generating a second halftone image. 19. An inkjet printing system comprising:
the image processing device according to claim 1; and the inkjet head, wherein the inkjet head records an image on the basis of data of a halftone image generated by the image processing device. | An image processing device ( 100 ) includes a non-discharge correction processing unit ( 114 ) that performs an image correction process for correcting an image defect caused by a non-discharge nozzle in an inkjet head and includes, as different files, a first halftone processing program file ( 152 ) that performs first halftone processing for a normal portion, which is an image region other than a non-discharge correction portion to be subjected to non-discharge correction and a non-discharge portion, and a second halftone processing program file ( 154 ) that performs second halftone processing for the non-discharge correction portion. The image processing device executes the first halftone processing program file ( 152 ) for the normal portion in an input image ( 102 ) and executes the second halftone processing program file ( 154 ) for the non-discharge correction portion, thereby obtaining a non-discharge-corrected halftone image ( 104 ).1. An image processing device comprising:
a non-discharge correction processing unit that performs an image correction process for correcting an image defect caused by a non-discharge nozzle in an inkjet head including a plurality of nozzles; at least one first halftone processing program file that performs first halftone processing for a normal portion, which is an image region other than a non-discharge correction portion to be subjected to the image correction process by the non-discharge correction processing unit and a non-discharge portion in which recording is not possible due to the non-discharge nozzle, to generate a first halftone image; and at least one second halftone processing program file that is different from the first halftone processing program file and performs second halftone processing, which is different from the first halftone processing, for the non-discharge correction portion to generate a second halftone image, wherein the first halftone processing program file is executed for the normal portion of an input image and the second halftone processing program file is executed for the non-discharge correction portion of the input image. 2. The image processing device according to claim 1, further comprising:
a non-discharge portion information storage unit that stores non-discharge portion information corresponding to a position of the non-discharge nozzle; an image region discrimination unit that discriminates between the normal portion and the non-discharge correction portion in the input image, on the basis of the non-discharge portion information; and a halftone processing switching unit that executes the first halftone processing program file and the second halftone processing program file for the normal portion and the non-discharge correction portion, respectively, on the basis of a determination result of the image region discrimination unit, to switch halftone processing to be applied to the normal portion and the non-discharge correction portion. 3. The image processing device according to claim 1, further comprising:
a non-discharge portion information storage unit that stores non-discharge portion information corresponding to a position of the non-discharge nozzle; an image division processing unit that divides the input image into the normal portion and the non-discharge correction portion on the basis of the non-discharge portion information; and an integration processing unit that integrates the first halftone image obtained by the execution of the first halftone processing program file for the normal portion divided by the image division processing unit with the second halftone image obtained by the execution of the second halftone processing program file for the non-discharge correction portion divided by the image division processing unit. 4. The image processing device according to claim 1,
wherein an algorithm of the first halftone processing by the first halftone processing program file is different from an algorithm of the second halftone processing by the second halftone processing program file. 5. The image processing device according to claim 4,
wherein the second halftone processing is performed by the second halftone processing program file using a dither mask. 6. The image processing device according to claim 1,
wherein the first halftone processing for the normal portion and the second halftone processing for the non-discharge correction portion are performed at different times, the frequency of the second halftone processing for the non-discharge correction portion is higher than the frequency of the first halftone processing for the normal portion, or the number of times the second halftone processing is performed for the non-discharge correction portion is larger than the number of times the first halftone processing is performed for the normal portion. 7. The image processing device according to claim 6, further comprising:
a first halftone image storage unit that stores the first halftone image obtained by the execution of the first halftone processing for the normal portion, wherein a process which integrates the second halftone image of the non-discharge correction portion that is sequentially created by performing the second halftone processing for the non-discharge correction portion according to a state of the non-discharge nozzle in the inkjet head with the first halftone image that is stored in the first halftone image storage unit in advance is performed. 8. The image processing device according to claim 1,
wherein data created by the first halftone processing is given as an input to the second halftone processing. 9. The image processing device according to claim 8, further comprising:
an arithmetic processing unit, wherein data of the first halftone image of the normal portion created by the first halftone processing is given as an input to the second halftone processing, the arithmetic processing unit applies a blur function to the first halftone image which is given as the input to the second halftone processing, and the second halftone processing is performed for data obtained by applying the blur function to the first halftone image. 10. The image processing device according to claim 9,
wherein the blur function is a Dooley's visual transfer function. 11. The image processing device according to claim 8,
wherein the data which is created by the first halftone processing and is given as the input to the second halftone processing is a cumulative error which is generated by an error diffusion process in the first halftone processing, and the second halftone processing program file performs the error diffusion process in the non-discharge correction portion, using the cumulative error as initial error data. 12. The image processing device according to claim 8,
wherein the second halftone processing program file performs the second halftone processing for the non-discharge correction portion, using the input image in addition to the data created by the first halftone processing. 13. The image processing device according to claim 12,
wherein, in the second halftone processing, a process that arranges no dots is performed in a case in which a signal value of a pixel to be processed which corresponds to the non-discharge correction portion of the input image is equal to a specific value or a process that certainly arranges dots is performed in a case in which the signal value of the pixel to be process is equal to or less than the specific value. 14. The image processing device according to claim 1,
wherein a plurality of the second halftone processing program files that can be applied to the second halftone processing for the non-discharge correction portion are provided. 15. The image processing device according to claim 14, further comprising:
a user interface that enables a user to select a second halftone processing program file used for the second halftone processing from the plurality of second halftone processing program files. 16. The image processing device according to claim 1,
wherein the inkjet head is a line head used in an inkjet printing system that records an image using a single-pass method, and the non-discharge correction portion is an image region including pixel rows which are adjacent to both sides of a pixel row of the non-discharge portion. 17. An image processing method comprising:
a non-discharge correction processing step of performing an image correction process for correcting an image defect caused by a non-discharge nozzle in an inkjet head including a plurality of nozzles; a first halftone processing step of executing a first halftone processing program file to perform first halftone processing for a normal portion, which is an image region other than a non-discharge correction portion to be subjected to the image correction process in the non-discharge correction processing step and a non-discharge portion in which recording is not possible due to the non-discharge nozzle in an input image, thereby generating a first halftone image; and a second halftone processing step of executing a second halftone processing program file that is different from the first halftone processing program file to perform second halftone processing, which is different from the first halftone processing, for the non-discharge correction portion in the input image, thereby generating a second halftone image. 18. A non-transitory computer-readable recording medium storing commands that are read by a computer and cause the computer to perform:
a non-discharge correction processing step of performing an image correction process for correcting an image defect caused by a non-discharge nozzle in an inkjet head including a plurality of nozzles; a first halftone processing step of executing a first halftone processing program file to perform first halftone processing for a normal portion, which is an image region other than a non-discharge correction portion to be subjected to the image correction process in the non-discharge correction processing step and a non-discharge portion in which recording is not possible due to the non-discharge nozzle in an input image, thereby generating a first halftone image; and a second halftone processing step of executing a second halftone processing program file that is different from the first halftone processing program file to perform second halftone processing, which is different from the first halftone processing, for the non-discharge correction portion in the input image, thereby generating a second halftone image. 19. An inkjet printing system comprising:
the image processing device according to claim 1; and the inkjet head, wherein the inkjet head records an image on the basis of data of a halftone image generated by the image processing device. | 2,800 |
11,462 | 11,462 | 15,324,367 | 2,844 | The invention further describes tube LED lamp ( 1 ) realised to replace a fluorescent tube lamp ( 70 ), which tube LED lamp ( 1 ) comprises a tube ( 12 ) containing an LED arrangement ( 10 ) with a number of LEDs ( 100 ); a connector arrangement ( 16 A, 16 B) with connectors ( 16 ) realized for insertion into sockets ( 50 ) of a socket arrangement ( 50 A, 50 B) of a tube lamp housing ( 5 ) incorporating a dimming ballast ( 20, 21 ); a driver circuit arrangement ( 11 ) for driving the LED arrangement ( 10 ), which driver circuit arrangement ( 11 ) is realized to output an LED current (I LED ) on the basis of an input current provided by the dimming ballast ( 20, 21 ); and a safety switch (S 13 , M 1 ) arranged within the tube ( 12 ) to electrically isolate connectors ( 16 ) of the connector arrangement ( 16 A, 16 B), wherein the safety switch (S 13 , M 1 ) is arranged between the driver circuit arrangement ( 11 ) and the LED arrangement ( 10 ). The invention further describes a method of driving a tube LED lamp ( 1 ) from a dimming ballast ( 20, 21 ) of a fluorescent tube lamp ( 70 ). | 1. A tube LED lamp realised to replace a fluorescent tube lamp, which tube LED lamp comprises
a tube containing an LED arrangement with a number of LEDs; a connector arrangement with connectors realized for insertion into sockets of a socket arrangement of a tube lamp housing incorporating a dimming ballast; a driver circuit arrangement for driving the LED arrangement, which driver circuit arrangement is realized to output an LED current on the basis of an input current provided by the dimming ballast; and a safety switch arranged within the tube to electrically isolate connectors of the connector arrangement, wherein the safety switch is arranged between the driver circuit arrangement and the LED arrangement. 2. A tube LED lamp according to claim 1, wherein the driver circuit arrangement is realized for connection to a dimming ballast of the PS type. 3. A tube LED lamp according to claim 1, wherein the safety switch comprises a semiconductor device. 4. A tube LED lamp according to claim 1, wherein the safety switch comprises an electromechanical device. 5. A tube LED lamp according to claim 1, wherein the connector arrangement comprises at least one connector at each of two outer ends of a linear tube, wherein a connector is realized for insertion into one of a pair of sockets in a linear tube lamp housing. 6. A tube LED lamp according to claim 1, comprising a switch control circuit realised to close the safety switch only when the connectors of a tube LED lamp are completely inserted into corresponding sockets of a tube lamp housing. 7. A tube LED lamp according to claim 6, wherein the switch control circuit is realised to detect an electrical connection between only one connector of the connector arrangement and one socket of the socket arrangement. 8. A tube LED lamp according to claim 5, wherein the switch control circuit comprises a mains frequency detection circuit for detecting a mains frequency component in a lamp voltage. 9. A tube LED lamp according to claim 5, wherein the switch control circuit is realised to detect a filament voltage at both connectors of the connector arrangement. 10. A tube LED lamp according to claim 5, wherein the switch control circuit comprises a DC blocking circuit portion realised to block a DC offset current of the dimmable ballast. 11. A tube LED lamp according to claim 1, comprising a protection circuit module realised to disconnect the LED driver from the LED arrangement in the event of an excessive lamp temperature and/or an excessive lamp current and/or an excessive lamp voltage. 12. A tube LED lamp according to claim 1, realized to retrofit any of a linear fluorescent tube lamp, a circular fluorescent tube lamp, a compact fluorescent lamp. 13. A method of driving a tube LED lamp from a dimming ballast of a fluorescent tube lamp, which method comprises the steps of
arranging a number of LEDs in a lamp tube, which lamp tube comprises a connector arrangement with connectors for insertion into sockets of a socket arrangement of a tube lamp housing comprising the dimming ballast; providing a driver circuit arrangement for driving the LEDs, which driver circuit arrangement is realized to output an LED current on the basis of an input current provided by the dimming ballast; and arranging a safety switch between the driver circuit arrangement and the LED arrangement to electrically isolate connectors of the connector arrangement when the connector arrangement is not completely connected to the socket arrangement. 14. A method according to claim 13, comprising the step of maintaining an electrical disconnection between connectors of the connector arrangement until all connectors are correctly inserted into the corresponding sockets. | The invention further describes tube LED lamp ( 1 ) realised to replace a fluorescent tube lamp ( 70 ), which tube LED lamp ( 1 ) comprises a tube ( 12 ) containing an LED arrangement ( 10 ) with a number of LEDs ( 100 ); a connector arrangement ( 16 A, 16 B) with connectors ( 16 ) realized for insertion into sockets ( 50 ) of a socket arrangement ( 50 A, 50 B) of a tube lamp housing ( 5 ) incorporating a dimming ballast ( 20, 21 ); a driver circuit arrangement ( 11 ) for driving the LED arrangement ( 10 ), which driver circuit arrangement ( 11 ) is realized to output an LED current (I LED ) on the basis of an input current provided by the dimming ballast ( 20, 21 ); and a safety switch (S 13 , M 1 ) arranged within the tube ( 12 ) to electrically isolate connectors ( 16 ) of the connector arrangement ( 16 A, 16 B), wherein the safety switch (S 13 , M 1 ) is arranged between the driver circuit arrangement ( 11 ) and the LED arrangement ( 10 ). The invention further describes a method of driving a tube LED lamp ( 1 ) from a dimming ballast ( 20, 21 ) of a fluorescent tube lamp ( 70 ).1. A tube LED lamp realised to replace a fluorescent tube lamp, which tube LED lamp comprises
a tube containing an LED arrangement with a number of LEDs; a connector arrangement with connectors realized for insertion into sockets of a socket arrangement of a tube lamp housing incorporating a dimming ballast; a driver circuit arrangement for driving the LED arrangement, which driver circuit arrangement is realized to output an LED current on the basis of an input current provided by the dimming ballast; and a safety switch arranged within the tube to electrically isolate connectors of the connector arrangement, wherein the safety switch is arranged between the driver circuit arrangement and the LED arrangement. 2. A tube LED lamp according to claim 1, wherein the driver circuit arrangement is realized for connection to a dimming ballast of the PS type. 3. A tube LED lamp according to claim 1, wherein the safety switch comprises a semiconductor device. 4. A tube LED lamp according to claim 1, wherein the safety switch comprises an electromechanical device. 5. A tube LED lamp according to claim 1, wherein the connector arrangement comprises at least one connector at each of two outer ends of a linear tube, wherein a connector is realized for insertion into one of a pair of sockets in a linear tube lamp housing. 6. A tube LED lamp according to claim 1, comprising a switch control circuit realised to close the safety switch only when the connectors of a tube LED lamp are completely inserted into corresponding sockets of a tube lamp housing. 7. A tube LED lamp according to claim 6, wherein the switch control circuit is realised to detect an electrical connection between only one connector of the connector arrangement and one socket of the socket arrangement. 8. A tube LED lamp according to claim 5, wherein the switch control circuit comprises a mains frequency detection circuit for detecting a mains frequency component in a lamp voltage. 9. A tube LED lamp according to claim 5, wherein the switch control circuit is realised to detect a filament voltage at both connectors of the connector arrangement. 10. A tube LED lamp according to claim 5, wherein the switch control circuit comprises a DC blocking circuit portion realised to block a DC offset current of the dimmable ballast. 11. A tube LED lamp according to claim 1, comprising a protection circuit module realised to disconnect the LED driver from the LED arrangement in the event of an excessive lamp temperature and/or an excessive lamp current and/or an excessive lamp voltage. 12. A tube LED lamp according to claim 1, realized to retrofit any of a linear fluorescent tube lamp, a circular fluorescent tube lamp, a compact fluorescent lamp. 13. A method of driving a tube LED lamp from a dimming ballast of a fluorescent tube lamp, which method comprises the steps of
arranging a number of LEDs in a lamp tube, which lamp tube comprises a connector arrangement with connectors for insertion into sockets of a socket arrangement of a tube lamp housing comprising the dimming ballast; providing a driver circuit arrangement for driving the LEDs, which driver circuit arrangement is realized to output an LED current on the basis of an input current provided by the dimming ballast; and arranging a safety switch between the driver circuit arrangement and the LED arrangement to electrically isolate connectors of the connector arrangement when the connector arrangement is not completely connected to the socket arrangement. 14. A method according to claim 13, comprising the step of maintaining an electrical disconnection between connectors of the connector arrangement until all connectors are correctly inserted into the corresponding sockets. | 2,800 |
11,463 | 11,463 | 15,349,585 | 2,883 | A method for securing a fiber optic component includes: providing a holding medium having a tack and mounted on a substrate; and placing the fiber optic component in intimate contact with the holding medium to thereby secure the fiber optic component to the substrate. The tack of the holding medium releasably bonds the fiber optic component to the holding medium and the holding medium retains its tack upon removal of the fiber optic component to permit re-placement of the fiber optic component or placement of a further fiber optic component on the holding medium to secure said fiber optic component or further fiber optic component to the substrate. | 1. A fiber optic component holder for securing a fiber optic component, the fiber optic component holder comprising:
a substrate to support the fiber optic component; and a holding medium mounted on the substrate, the holding medium having a contacting surface, the contacting surface having a tack, wherein the tack of the contacting surface releasably bonds the fiber optic component to the contacting surface, and wherein upon removal of the fiber optic component from the contacting surface, the contacting surface retains its tack and remains mounted on the substrate to permit re-placement of the same or a different fiber optic component on the contacting surface, wherein the tack of the contacting surface releasably bonds the re-placed same or different fiber optic component to the contacting surface. 2. The fiber optic component holder of claim 1, wherein the fiber optic component comprises an optical fiber. 3. The fiber optic component holder of claim 1, wherein the fiber optic component comprises a fiber optic splice sleeve, a fiber optic splitter, an optic wavelength filter or a mechanical splice connector. 4. The fiber optic component of claim 1, wherein the contacting surface of the holding medium has a tack in the range of from about 8 to 25 grams. 5. The fiber optic component of claim 1, wherein the holding medium has a thickness in the range of from about 0.1 to 0.4 mm. 6. The fiber optic component of claim 1, wherein the substrate comprises a first substrate and a second substrate mounted to the first substrate. 7. The fiber optic component of claim 1, wherein the second substrate is releasably mounted to the first substrate. 8. An optical fiber splice tray device, the optical fiber splice tray device comprising:
a tray having a mounting feature; a substrate to support an optical fiber splice sleeve, the substrate mounted on the mounting feature; and a holding medium mounted on the substrate, the holding medium having a contacting surface, the contacting surface having a tack, wherein the tack of the contacting surface releasably bonds the optical fiber splice sleeve to the contacting surface, and wherein upon removal of the optical fiber splice sleeve from the contacting surface, the contacting surface retains its tack and remains mounted on the substrate to permit re-placement of the same or a different optical fiber splice sleeve, wherein the tack of the contacting surface releasably bonds the re-placed same or different splice sleeve to the contacting surface. 10. The optical fiber splice tray device of claim 8, wherein the contacting surface of the holding medium has a tack in the range of from about 8 to 25 grams. 11. The optical fiber splice tray device of claim 8, wherein the holding medium has a thickness in the range of from about 0.1 to 0.4 mm. 12. The optical fiber splice tray device of claim 8, wherein the substrate comprises a first substrate and a second substrate mounted to the first substrate. 13. The optical fiber splice tray device of claim 12, wherein the second substrate is releasably mounted to the first substrate. 14. The optical fiber splice tray device of claim 12, wherein the first substrate is releasably mounted to the tray. 15. The optical fiber splice tray device of claim 1, wherein the substrate supports a plurality of optical fiber splice sleeves. 16. The optical fiber splice tray device of claim 15, wherein at least twelve optical fiber splice sleeves. 17. A method for splicing an optical fiber, the method comprising:
providing a splice tray having mounted thereon a substrate, wherein the substrate includes a holding medium having a contacting surface that has a tack; placing an optical fiber splice sleeve on the contacting surface, wherein the tack of the contacting surface releasably bonds the splice sleeve to the contacting surface; inserting a first optical fiber into a first end of the optical fiber splice sleeve; inserting a second optical fiber into a second end of the optical fiber splice sleeve; and optically coupling the first and second optical fibers within the optical fiber splice sleeve. 18. The method of claim 17, further comprising
removing the optical fiber splice sleeve from the contacting surface; and replacing the optical fiber splice sleeve on the contacting surface with the same or a different optical fiber splice sleeve, wherein the tack of the contacting surface releasably bonds the same or different splice sleeve to the contacting surface. 19. The method of claim 17, wherein the contacting surface of the holding medium has a tack in the range of from about 8 to 25 grams. 20. The method of claim 17, wherein the holding medium has a thickness in the range of from about 0.1 to 0.4 mm. | A method for securing a fiber optic component includes: providing a holding medium having a tack and mounted on a substrate; and placing the fiber optic component in intimate contact with the holding medium to thereby secure the fiber optic component to the substrate. The tack of the holding medium releasably bonds the fiber optic component to the holding medium and the holding medium retains its tack upon removal of the fiber optic component to permit re-placement of the fiber optic component or placement of a further fiber optic component on the holding medium to secure said fiber optic component or further fiber optic component to the substrate.1. A fiber optic component holder for securing a fiber optic component, the fiber optic component holder comprising:
a substrate to support the fiber optic component; and a holding medium mounted on the substrate, the holding medium having a contacting surface, the contacting surface having a tack, wherein the tack of the contacting surface releasably bonds the fiber optic component to the contacting surface, and wherein upon removal of the fiber optic component from the contacting surface, the contacting surface retains its tack and remains mounted on the substrate to permit re-placement of the same or a different fiber optic component on the contacting surface, wherein the tack of the contacting surface releasably bonds the re-placed same or different fiber optic component to the contacting surface. 2. The fiber optic component holder of claim 1, wherein the fiber optic component comprises an optical fiber. 3. The fiber optic component holder of claim 1, wherein the fiber optic component comprises a fiber optic splice sleeve, a fiber optic splitter, an optic wavelength filter or a mechanical splice connector. 4. The fiber optic component of claim 1, wherein the contacting surface of the holding medium has a tack in the range of from about 8 to 25 grams. 5. The fiber optic component of claim 1, wherein the holding medium has a thickness in the range of from about 0.1 to 0.4 mm. 6. The fiber optic component of claim 1, wherein the substrate comprises a first substrate and a second substrate mounted to the first substrate. 7. The fiber optic component of claim 1, wherein the second substrate is releasably mounted to the first substrate. 8. An optical fiber splice tray device, the optical fiber splice tray device comprising:
a tray having a mounting feature; a substrate to support an optical fiber splice sleeve, the substrate mounted on the mounting feature; and a holding medium mounted on the substrate, the holding medium having a contacting surface, the contacting surface having a tack, wherein the tack of the contacting surface releasably bonds the optical fiber splice sleeve to the contacting surface, and wherein upon removal of the optical fiber splice sleeve from the contacting surface, the contacting surface retains its tack and remains mounted on the substrate to permit re-placement of the same or a different optical fiber splice sleeve, wherein the tack of the contacting surface releasably bonds the re-placed same or different splice sleeve to the contacting surface. 10. The optical fiber splice tray device of claim 8, wherein the contacting surface of the holding medium has a tack in the range of from about 8 to 25 grams. 11. The optical fiber splice tray device of claim 8, wherein the holding medium has a thickness in the range of from about 0.1 to 0.4 mm. 12. The optical fiber splice tray device of claim 8, wherein the substrate comprises a first substrate and a second substrate mounted to the first substrate. 13. The optical fiber splice tray device of claim 12, wherein the second substrate is releasably mounted to the first substrate. 14. The optical fiber splice tray device of claim 12, wherein the first substrate is releasably mounted to the tray. 15. The optical fiber splice tray device of claim 1, wherein the substrate supports a plurality of optical fiber splice sleeves. 16. The optical fiber splice tray device of claim 15, wherein at least twelve optical fiber splice sleeves. 17. A method for splicing an optical fiber, the method comprising:
providing a splice tray having mounted thereon a substrate, wherein the substrate includes a holding medium having a contacting surface that has a tack; placing an optical fiber splice sleeve on the contacting surface, wherein the tack of the contacting surface releasably bonds the splice sleeve to the contacting surface; inserting a first optical fiber into a first end of the optical fiber splice sleeve; inserting a second optical fiber into a second end of the optical fiber splice sleeve; and optically coupling the first and second optical fibers within the optical fiber splice sleeve. 18. The method of claim 17, further comprising
removing the optical fiber splice sleeve from the contacting surface; and replacing the optical fiber splice sleeve on the contacting surface with the same or a different optical fiber splice sleeve, wherein the tack of the contacting surface releasably bonds the same or different splice sleeve to the contacting surface. 19. The method of claim 17, wherein the contacting surface of the holding medium has a tack in the range of from about 8 to 25 grams. 20. The method of claim 17, wherein the holding medium has a thickness in the range of from about 0.1 to 0.4 mm. | 2,800 |
11,464 | 11,464 | 12,880,286 | 2,815 | It is an object to provide a highly reliable thin film transistor with stable electric characteristics, which includes an oxide semiconductor film. The channel length of the thin film transistor including the oxide semiconductor film is in the range of 1.5 μm to 100 μm inclusive, preferably 3 μm to 10 μm inclusive; when the amount of change in threshold voltage is less than or equal to 3 V, preferably less than or equal to 1.5 V in an operation temperature range of room temperature to 180° C. inclusive or −25° C. to −150° C. inclusive, a semiconductor device with stable electric characteristics can be manufactured. In particular, in a display device which is an embodiment of the semiconductor device, display unevenness due to variation in threshold voltage can be reduced. | 1. A semiconductor device comprising:
a gate electrode layer over a substrate having an insulating surface; a gate insulating layer over the gate electrode layer; an oxide semiconductor layer over the gate insulating layer; a source electrode layer and a drain electrode layer over the oxide semiconductor layer; and a protective insulating layer in contact with a part of the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, wherein an amount of change in threshold voltage is less than or equal to 3 V in a temperature range of room temperature to 180° C. 2. The semiconductor device according to claim 1, wherein a channel length of the oxide semiconductor layer is greater than or equal to 1.5 μm and less than or equal to 100 μm. 3. The semiconductor device according to claim 1, wherein a channel length of the oxide semiconductor layer is greater than or equal to 3 μm and less than or equal to 100 μm. 4. The semiconductor device according to claim 1, wherein the semiconductor device is one selected from the group consisting of an e-book reader, a television set, a digital photo frame, a game machine, a computer and a mobile phone. 5. A semiconductor device comprising:
a gate electrode layer over a substrate having an insulating surface; a gate insulating layer over the gate electrode layer; an oxide semiconductor layer over the gate insulating layer; a source electrode layer and a drain electrode layer over the oxide semiconductor layer; and a protective insulating layer in contact with a part of the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, wherein an amount of change in threshold voltage is less than or equal to 1.5 V in a temperature range of room temperature to 180° C. 6. The semiconductor device according to claim 5, wherein a channel length of the oxide semiconductor layer is greater than or equal to 1.5 μm and less than or equal to 100 μm. 7. The semiconductor device according to claim 5, wherein a channel length of the oxide semiconductor layer is greater than or equal to 3 μm and less than or equal to 100 μm. 8. The semiconductor device according to claim 5, wherein the semiconductor device is one selected from the group consisting of an e-book reader, a television set, a digital photo frame, a game machine, a computer and a mobile phone. 9. A semiconductor device comprising:
a gate electrode layer over a substrate having an insulating surface; a gate insulating layer over the gate electrode layer; an oxide semiconductor layer over the gate insulating layer; a source electrode layer and a drain electrode layer over the oxide semiconductor layer; and a protective insulating layer in contact with a part of the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, wherein an amount of change in threshold voltage is less than or equal to 3 V in a temperature range of −25° C. to 150° C. 10. The semiconductor device according to claim 9, wherein a channel length of the oxide semiconductor layer is greater than or equal to 1.5 μm and less than or equal to 100 μm. 11. The semiconductor device according to claim 9, wherein a channel length of the oxide semiconductor layer is greater than or equal to 3 μm and less than or equal to 100 μm. 12. The semiconductor device according to claim 9, wherein the semiconductor device is one selected from the group consisting of an e-book reader, a television set, a digital photo frame, a game machine, a computer and a mobile phone. 13. A semiconductor device comprising:
a gate electrode layer over a substrate having an insulating surface; a gate insulating layer over the gate electrode layer; an oxide semiconductor layer over the gate insulating layer; a source electrode layer and a drain electrode layer over the oxide semiconductor layer; and a protective insulating layer in contact with a part of the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, wherein an amount of change in threshold voltage is less than or equal to 1.5 V in a temperature range of −25° C. to 150° C. 14. The semiconductor device according to claim 13, wherein a channel length of the oxide semiconductor layer is greater than or equal to 1.5 μm and less than or equal to 100 μm. 15. The semiconductor device according to claim 13, wherein a channel length of the oxide semiconductor layer is greater than or equal to 3 μm and less than or equal to 100 μm. 16. The semiconductor device according to claim 13, wherein the semiconductor device is one selected from the group consisting of an e-book reader, a television set, a digital photo frame, a game machine, a computer and a mobile phone. 17. A method for manufacturing a semiconductor device, comprising the steps of:
forming a gate electrode layer over a substrate having an insulating surface; forming a gate insulating layer over the gate electrode layer; forming an oxide semiconductor layer over the gate insulating layer; performing a first heat treatment after forming the oxide semiconductor layer; forming a source electrode layer and a drain electrode layer over the oxide semiconductor layer; forming a protective insulating layer in contact with a part of the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and performing a second heat treatment after forming the protective insulating layer, wherein the second heat treatment is performed at a lower temperature than the first heat treatment. 18. The method for manufacturing a semiconductor device according to claim 17, wherein the first heat treatment is performed at a temperature of greater than or equal to 350° C. and less than or equal to 750° C. 19. The method for manufacturing a semiconductor device according to claim 17, wherein the first heat treatment is performed in a nitrogen atmosphere or a rare gas atmosphere. 20. The method for manufacturing a semiconductor device according to claim 17, wherein the second heat treatment is performed at a temperature of greater than or equal to 100° C. and less than or equal to the temperature of the first heat treatment. 21. The method for manufacturing a semiconductor device according to claim 17, wherein the second heat treatment is performed in air, an oxygen atmosphere, a nitrogen atmosphere, or a rare gas atmosphere. | It is an object to provide a highly reliable thin film transistor with stable electric characteristics, which includes an oxide semiconductor film. The channel length of the thin film transistor including the oxide semiconductor film is in the range of 1.5 μm to 100 μm inclusive, preferably 3 μm to 10 μm inclusive; when the amount of change in threshold voltage is less than or equal to 3 V, preferably less than or equal to 1.5 V in an operation temperature range of room temperature to 180° C. inclusive or −25° C. to −150° C. inclusive, a semiconductor device with stable electric characteristics can be manufactured. In particular, in a display device which is an embodiment of the semiconductor device, display unevenness due to variation in threshold voltage can be reduced.1. A semiconductor device comprising:
a gate electrode layer over a substrate having an insulating surface; a gate insulating layer over the gate electrode layer; an oxide semiconductor layer over the gate insulating layer; a source electrode layer and a drain electrode layer over the oxide semiconductor layer; and a protective insulating layer in contact with a part of the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, wherein an amount of change in threshold voltage is less than or equal to 3 V in a temperature range of room temperature to 180° C. 2. The semiconductor device according to claim 1, wherein a channel length of the oxide semiconductor layer is greater than or equal to 1.5 μm and less than or equal to 100 μm. 3. The semiconductor device according to claim 1, wherein a channel length of the oxide semiconductor layer is greater than or equal to 3 μm and less than or equal to 100 μm. 4. The semiconductor device according to claim 1, wherein the semiconductor device is one selected from the group consisting of an e-book reader, a television set, a digital photo frame, a game machine, a computer and a mobile phone. 5. A semiconductor device comprising:
a gate electrode layer over a substrate having an insulating surface; a gate insulating layer over the gate electrode layer; an oxide semiconductor layer over the gate insulating layer; a source electrode layer and a drain electrode layer over the oxide semiconductor layer; and a protective insulating layer in contact with a part of the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, wherein an amount of change in threshold voltage is less than or equal to 1.5 V in a temperature range of room temperature to 180° C. 6. The semiconductor device according to claim 5, wherein a channel length of the oxide semiconductor layer is greater than or equal to 1.5 μm and less than or equal to 100 μm. 7. The semiconductor device according to claim 5, wherein a channel length of the oxide semiconductor layer is greater than or equal to 3 μm and less than or equal to 100 μm. 8. The semiconductor device according to claim 5, wherein the semiconductor device is one selected from the group consisting of an e-book reader, a television set, a digital photo frame, a game machine, a computer and a mobile phone. 9. A semiconductor device comprising:
a gate electrode layer over a substrate having an insulating surface; a gate insulating layer over the gate electrode layer; an oxide semiconductor layer over the gate insulating layer; a source electrode layer and a drain electrode layer over the oxide semiconductor layer; and a protective insulating layer in contact with a part of the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, wherein an amount of change in threshold voltage is less than or equal to 3 V in a temperature range of −25° C. to 150° C. 10. The semiconductor device according to claim 9, wherein a channel length of the oxide semiconductor layer is greater than or equal to 1.5 μm and less than or equal to 100 μm. 11. The semiconductor device according to claim 9, wherein a channel length of the oxide semiconductor layer is greater than or equal to 3 μm and less than or equal to 100 μm. 12. The semiconductor device according to claim 9, wherein the semiconductor device is one selected from the group consisting of an e-book reader, a television set, a digital photo frame, a game machine, a computer and a mobile phone. 13. A semiconductor device comprising:
a gate electrode layer over a substrate having an insulating surface; a gate insulating layer over the gate electrode layer; an oxide semiconductor layer over the gate insulating layer; a source electrode layer and a drain electrode layer over the oxide semiconductor layer; and a protective insulating layer in contact with a part of the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, wherein an amount of change in threshold voltage is less than or equal to 1.5 V in a temperature range of −25° C. to 150° C. 14. The semiconductor device according to claim 13, wherein a channel length of the oxide semiconductor layer is greater than or equal to 1.5 μm and less than or equal to 100 μm. 15. The semiconductor device according to claim 13, wherein a channel length of the oxide semiconductor layer is greater than or equal to 3 μm and less than or equal to 100 μm. 16. The semiconductor device according to claim 13, wherein the semiconductor device is one selected from the group consisting of an e-book reader, a television set, a digital photo frame, a game machine, a computer and a mobile phone. 17. A method for manufacturing a semiconductor device, comprising the steps of:
forming a gate electrode layer over a substrate having an insulating surface; forming a gate insulating layer over the gate electrode layer; forming an oxide semiconductor layer over the gate insulating layer; performing a first heat treatment after forming the oxide semiconductor layer; forming a source electrode layer and a drain electrode layer over the oxide semiconductor layer; forming a protective insulating layer in contact with a part of the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and performing a second heat treatment after forming the protective insulating layer, wherein the second heat treatment is performed at a lower temperature than the first heat treatment. 18. The method for manufacturing a semiconductor device according to claim 17, wherein the first heat treatment is performed at a temperature of greater than or equal to 350° C. and less than or equal to 750° C. 19. The method for manufacturing a semiconductor device according to claim 17, wherein the first heat treatment is performed in a nitrogen atmosphere or a rare gas atmosphere. 20. The method for manufacturing a semiconductor device according to claim 17, wherein the second heat treatment is performed at a temperature of greater than or equal to 100° C. and less than or equal to the temperature of the first heat treatment. 21. The method for manufacturing a semiconductor device according to claim 17, wherein the second heat treatment is performed in air, an oxygen atmosphere, a nitrogen atmosphere, or a rare gas atmosphere. | 2,800 |
11,465 | 11,465 | 15,250,005 | 2,891 | A semiconductor device, including a substrate, and a deposit layer and a semiconductor layer formed sequentially on the substrate. The semiconductor layer has selectively disposed therein a first region, a second region and a contact region. A gate electrode is disposed on the first region and the semiconductor layer via a gate insulating film. A source electrode is formed in contact with the contact region and the second region. A drain electrode is disposed on the back surface of the substrate. The source electrode has a first titanium (Ti) film, and a titanium nitride (TiN) film, a second Ti film, and a metal film containing aluminum (Al) sequentially formed on the first Ti film. The source electrode may further include another TiN film, on which the first Ti film is formed. | 1. A semiconductor device, comprising:
a substrate formed of a wide-band-gap semiconductor material that has a band gap greater than that of silicon, the substrate having a front surface and a back surface; a deposit layer formed of the wide-band-gap semiconductor material and having an impurity concentration lower than that of the substrate, the deposit layer having a first side and a second side opposite to the first side, and being deposited on the front surface of the substrate that is located on the second side; a semiconductor region selectively disposed in the deposit layer on the first side thereof; a semiconductor layer formed of the wide-band-gap semiconductor material, disposed on a surface of the deposit layer on the first side and a surface of the semiconductor region formed in the deposit layer, the semiconductor layer having selectively disposed therein a first region, a second region and a contact region; a gate electrode disposed, via a gate insulating film, on the semiconductor layer and the first region; an interlayer insulating film covering the gate electrode; a source electrode in contact with the contact region and the second region; a drain electrode disposed on the back surface of the substrate; a plating film selectively disposed on the source electrode; and a pin electrode in contact with the plating film, wherein the substrate, the deposit layer, and the first and second regions formed in the semiconductor layer are of a first conductivity type, the semiconductor region, the semiconductor layer and the contact region formed therein are of a second conductivity type, and the source electrode has a first titanium (Ti) film, and a titanium nitride (TiN) film, a second Ti film, and a metal film containing aluminum (Al) sequentially formed on the first Ti film. 2. The semiconductor device according to claim 1, wherein the source electrode further includes another TiN film, on which the first Ti film is formed. 3. The semiconductor device according to claim 1, wherein the metal film containing Al is any one of an Al-silicon (Si) film, an Al—Cu (Copper) film, and an Al—Si—Cu film. 4. The semiconductor device according claim 1, further comprising:
a protective film selectively disposed on the source electrode; and a second protective film covering a junction of the plating film and the protective film, wherein the second protective film is a polyamide film. 5. The semiconductor device according claim 1, wherein the first region is formed on the semiconductor region. 6. The semiconductor device according claim 1, wherein the pin electrode is soldered to the plating film. 7. A method of manufacturing a semiconductor device, comprising:
providing a substrate of a first conductivity type, formed of a wide-band-gap semiconductor material that has a band gap greater than that of silicon; forming, on a front surface of the substrate, a deposit layer made of the wide-band-gap semiconductor material, the deposit layer being of the first conductivity type and having an impurity concentration lower than that of the substrate; selectively forming, in the deposit layer, a semiconductor region of a second conductivity type; forming, on a surface of the deposit layer, a semiconductor layer of the second conductivity formed of the wide-band-gap semiconductor material; selectively forming a first region of the first conductivity type in the semiconductor layer; selectively forming a second region of the first conductivity type in the semiconductor layer; selectively forming a contact region of the second conductivity type in the semiconductor layer; forming a gate electrode on the semiconductor layer and the first region via a gate insulating film; forming an interlayer insulating film to cover the gate electrode; forming a source electrode to contact the contact region and the second region, including
forming a first titanium (Ti) film, and
forming a titanium nitride (TiN) film, a second Ti film, and a metal film containing aluminum (Al) sequentially on the first Ti film;
forming a drain electrode on a back surface of the substrate;
selectively forming a plating film on the source electrode; and forming a pin electrode in contact with the plating film. 8. The method of claim 7, wherein the first region is formed on the semiconductor region. 9. The method of claim 7, wherein forming the pin electrode includes soldering the pin electrode to the plating film. | A semiconductor device, including a substrate, and a deposit layer and a semiconductor layer formed sequentially on the substrate. The semiconductor layer has selectively disposed therein a first region, a second region and a contact region. A gate electrode is disposed on the first region and the semiconductor layer via a gate insulating film. A source electrode is formed in contact with the contact region and the second region. A drain electrode is disposed on the back surface of the substrate. The source electrode has a first titanium (Ti) film, and a titanium nitride (TiN) film, a second Ti film, and a metal film containing aluminum (Al) sequentially formed on the first Ti film. The source electrode may further include another TiN film, on which the first Ti film is formed.1. A semiconductor device, comprising:
a substrate formed of a wide-band-gap semiconductor material that has a band gap greater than that of silicon, the substrate having a front surface and a back surface; a deposit layer formed of the wide-band-gap semiconductor material and having an impurity concentration lower than that of the substrate, the deposit layer having a first side and a second side opposite to the first side, and being deposited on the front surface of the substrate that is located on the second side; a semiconductor region selectively disposed in the deposit layer on the first side thereof; a semiconductor layer formed of the wide-band-gap semiconductor material, disposed on a surface of the deposit layer on the first side and a surface of the semiconductor region formed in the deposit layer, the semiconductor layer having selectively disposed therein a first region, a second region and a contact region; a gate electrode disposed, via a gate insulating film, on the semiconductor layer and the first region; an interlayer insulating film covering the gate electrode; a source electrode in contact with the contact region and the second region; a drain electrode disposed on the back surface of the substrate; a plating film selectively disposed on the source electrode; and a pin electrode in contact with the plating film, wherein the substrate, the deposit layer, and the first and second regions formed in the semiconductor layer are of a first conductivity type, the semiconductor region, the semiconductor layer and the contact region formed therein are of a second conductivity type, and the source electrode has a first titanium (Ti) film, and a titanium nitride (TiN) film, a second Ti film, and a metal film containing aluminum (Al) sequentially formed on the first Ti film. 2. The semiconductor device according to claim 1, wherein the source electrode further includes another TiN film, on which the first Ti film is formed. 3. The semiconductor device according to claim 1, wherein the metal film containing Al is any one of an Al-silicon (Si) film, an Al—Cu (Copper) film, and an Al—Si—Cu film. 4. The semiconductor device according claim 1, further comprising:
a protective film selectively disposed on the source electrode; and a second protective film covering a junction of the plating film and the protective film, wherein the second protective film is a polyamide film. 5. The semiconductor device according claim 1, wherein the first region is formed on the semiconductor region. 6. The semiconductor device according claim 1, wherein the pin electrode is soldered to the plating film. 7. A method of manufacturing a semiconductor device, comprising:
providing a substrate of a first conductivity type, formed of a wide-band-gap semiconductor material that has a band gap greater than that of silicon; forming, on a front surface of the substrate, a deposit layer made of the wide-band-gap semiconductor material, the deposit layer being of the first conductivity type and having an impurity concentration lower than that of the substrate; selectively forming, in the deposit layer, a semiconductor region of a second conductivity type; forming, on a surface of the deposit layer, a semiconductor layer of the second conductivity formed of the wide-band-gap semiconductor material; selectively forming a first region of the first conductivity type in the semiconductor layer; selectively forming a second region of the first conductivity type in the semiconductor layer; selectively forming a contact region of the second conductivity type in the semiconductor layer; forming a gate electrode on the semiconductor layer and the first region via a gate insulating film; forming an interlayer insulating film to cover the gate electrode; forming a source electrode to contact the contact region and the second region, including
forming a first titanium (Ti) film, and
forming a titanium nitride (TiN) film, a second Ti film, and a metal film containing aluminum (Al) sequentially on the first Ti film;
forming a drain electrode on a back surface of the substrate;
selectively forming a plating film on the source electrode; and forming a pin electrode in contact with the plating film. 8. The method of claim 7, wherein the first region is formed on the semiconductor region. 9. The method of claim 7, wherein forming the pin electrode includes soldering the pin electrode to the plating film. | 2,800 |
11,466 | 11,466 | 13,434,692 | 2,859 | A battery pack management system adjusts the relative state-of-charge of respective battery blocks in a battery pack to equalize (i.e., align, balance or otherwise make similar) the peak battery block voltages (i.e., maximum or “upper peak” battery block voltages when the battery pack is being charged and/or minimum or “lower peak” battery block voltages when the battery is being discharged). Upon detecting an anomalous battery block that exhibits outlier upper and lower peak voltages, the battery pack management system adjusts the relative state of charge of respective battery blocks to center their respective upper and lower peak voltages between operating limits, thus maximizing the operating margin of the battery pack as a whole. | 1. A method of operation within a battery system, the method comprising:
charging a plurality of battery blocks during a first interval; measuring respective charging voltages of the battery blocks during the first interval; identifying a first battery block of the plurality of battery blocks that has a charging voltage higher than a charging voltage of another of the battery blocks; and discharging the first battery block without discharging others of the plurality of battery blocks to reduce the difference between the charging voltage of the first battery block and the charging voltages of the other of the battery blocks. 2. The method of claim 1 wherein charging comprises applying a current pulse. 3. The method of claim 1 wherein charging comprises applying current from a regenerative braking system within a hybrid electric vehicle or an electric vehicle. 4. The method of claim 1 wherein measuring respective charging voltages of the battery blocks during the first interval comprises measuring each of the battery block voltages concurrently. 5. The method of claim 1 wherein identifying a first battery block of the plurality of battery blocks that has a charging voltage higher than a charging voltage of another of the battery blocks comprises determining a minimum voltage of any of the charging voltages. 6. The method of claim 1 wherein identifying a first battery block of the plurality of battery blocks that has a charging voltage higher than a charging voltage of another of the battery blocks comprises determining a maximum voltage of any of the charging voltages. 7. The method of claim 1 wherein identifying a first battery block of the plurality of battery blocks that has a charging voltage higher than a charging voltage of another of the battery blocks comprises identifying a statistical outlier of the charging voltages. 8. The method of claim 7 wherein identifying a statistical outlier of the charging voltages comprises identifying based on, at least in part, one of the following:
battery pack age, number of discharge cycles, battery pack state of charge, battery pack temperature, and battery cell chemistry. 9. The method of claim 1 wherein discharging the first battery block comprises switchably coupling balance resistors to the first battery block. 10. A method of operation within a battery system, the method comprising:
discharging a plurality of battery blocks during a first interval; measuring respective discharging voltages of the battery blocks during the first interval; identifying a first battery block of the plurality of battery blocks that has a discharging voltage lower than a discharging voltage of another of the battery blocks; and discharging the other of the battery blocks to reduce the difference between the discharging voltage of the first battery block and the discharging voltage of the other of the battery blocks. 11. A battery system apparatus comprising:
a plurality of voltage measurement inputs to receive charging voltage measurements corresponding to respective battery blocks during a first interval in which the respective battery blocks are being charged; voltage measurement logic to identify a first battery block of the plurality of battery blocks that yields a charging voltage measurement higher than a charging voltage measurement of another of the battery blocks during the first interval; and discharge logic to discharge the first battery block to reduce the difference between the charging voltage measurement of the first battery block and the charging voltage measurement of the other of the battery blocks. 12. The battery system apparatus of claim 11 wherein the battery system is disposed within a hybrid electric vehicle or an electric vehicle. 13. The battery system apparatus of claim 11 wherein the number voltage measurement inputs is equal to the number of battery blocks. 14. The battery system apparatus of claim 11 wherein one or both of the voltage measurement logic and the discharge logic is implemented at least in part by a programmed processor. 15. The battery system apparatus of claim 11 wherein the voltage measurement logic comprises circuitry to determine the minimum voltage of any of the charging voltage measurements. 16. The battery system apparatus of claim 11 wherein the voltage measurement logic comprises circuitry to determine the maximum voltage of any of the charging voltage measurements. 17. The battery system apparatus of claim 11 wherein the voltage measurement logic comprises circuitry to determine a statistical outlier of any of the charging voltage measurements. 18. The battery system apparatus of claim 11 wherein the voltage measurement logic comprises circuitry comprising operating parameter inputs including battery pack age, number of discharge cycles, battery pack state of charge, battery pack temperature, and battery cell chemistry. 19. The battery system apparatus of claim 11 wherein the discharge logic comprises circuitry to switchably couple an electrical load between positive and negative output terminals of each battery block. 20. A battery system comprising:
means for receiving charging voltage measurements corresponding to respective battery blocks during a first interval in which the respective battery blocks are being charged; means for identifying a first battery block of the plurality of battery blocks that yields a charging voltage measurement higher than a charging voltage measurement of another of the battery blocks during the first interval; and means for discharging the first battery block to reduce the difference between the charging voltage measurement of the first battery block and the charging voltage measurement of the other of the battery blocks. | A battery pack management system adjusts the relative state-of-charge of respective battery blocks in a battery pack to equalize (i.e., align, balance or otherwise make similar) the peak battery block voltages (i.e., maximum or “upper peak” battery block voltages when the battery pack is being charged and/or minimum or “lower peak” battery block voltages when the battery is being discharged). Upon detecting an anomalous battery block that exhibits outlier upper and lower peak voltages, the battery pack management system adjusts the relative state of charge of respective battery blocks to center their respective upper and lower peak voltages between operating limits, thus maximizing the operating margin of the battery pack as a whole.1. A method of operation within a battery system, the method comprising:
charging a plurality of battery blocks during a first interval; measuring respective charging voltages of the battery blocks during the first interval; identifying a first battery block of the plurality of battery blocks that has a charging voltage higher than a charging voltage of another of the battery blocks; and discharging the first battery block without discharging others of the plurality of battery blocks to reduce the difference between the charging voltage of the first battery block and the charging voltages of the other of the battery blocks. 2. The method of claim 1 wherein charging comprises applying a current pulse. 3. The method of claim 1 wherein charging comprises applying current from a regenerative braking system within a hybrid electric vehicle or an electric vehicle. 4. The method of claim 1 wherein measuring respective charging voltages of the battery blocks during the first interval comprises measuring each of the battery block voltages concurrently. 5. The method of claim 1 wherein identifying a first battery block of the plurality of battery blocks that has a charging voltage higher than a charging voltage of another of the battery blocks comprises determining a minimum voltage of any of the charging voltages. 6. The method of claim 1 wherein identifying a first battery block of the plurality of battery blocks that has a charging voltage higher than a charging voltage of another of the battery blocks comprises determining a maximum voltage of any of the charging voltages. 7. The method of claim 1 wherein identifying a first battery block of the plurality of battery blocks that has a charging voltage higher than a charging voltage of another of the battery blocks comprises identifying a statistical outlier of the charging voltages. 8. The method of claim 7 wherein identifying a statistical outlier of the charging voltages comprises identifying based on, at least in part, one of the following:
battery pack age, number of discharge cycles, battery pack state of charge, battery pack temperature, and battery cell chemistry. 9. The method of claim 1 wherein discharging the first battery block comprises switchably coupling balance resistors to the first battery block. 10. A method of operation within a battery system, the method comprising:
discharging a plurality of battery blocks during a first interval; measuring respective discharging voltages of the battery blocks during the first interval; identifying a first battery block of the plurality of battery blocks that has a discharging voltage lower than a discharging voltage of another of the battery blocks; and discharging the other of the battery blocks to reduce the difference between the discharging voltage of the first battery block and the discharging voltage of the other of the battery blocks. 11. A battery system apparatus comprising:
a plurality of voltage measurement inputs to receive charging voltage measurements corresponding to respective battery blocks during a first interval in which the respective battery blocks are being charged; voltage measurement logic to identify a first battery block of the plurality of battery blocks that yields a charging voltage measurement higher than a charging voltage measurement of another of the battery blocks during the first interval; and discharge logic to discharge the first battery block to reduce the difference between the charging voltage measurement of the first battery block and the charging voltage measurement of the other of the battery blocks. 12. The battery system apparatus of claim 11 wherein the battery system is disposed within a hybrid electric vehicle or an electric vehicle. 13. The battery system apparatus of claim 11 wherein the number voltage measurement inputs is equal to the number of battery blocks. 14. The battery system apparatus of claim 11 wherein one or both of the voltage measurement logic and the discharge logic is implemented at least in part by a programmed processor. 15. The battery system apparatus of claim 11 wherein the voltage measurement logic comprises circuitry to determine the minimum voltage of any of the charging voltage measurements. 16. The battery system apparatus of claim 11 wherein the voltage measurement logic comprises circuitry to determine the maximum voltage of any of the charging voltage measurements. 17. The battery system apparatus of claim 11 wherein the voltage measurement logic comprises circuitry to determine a statistical outlier of any of the charging voltage measurements. 18. The battery system apparatus of claim 11 wherein the voltage measurement logic comprises circuitry comprising operating parameter inputs including battery pack age, number of discharge cycles, battery pack state of charge, battery pack temperature, and battery cell chemistry. 19. The battery system apparatus of claim 11 wherein the discharge logic comprises circuitry to switchably couple an electrical load between positive and negative output terminals of each battery block. 20. A battery system comprising:
means for receiving charging voltage measurements corresponding to respective battery blocks during a first interval in which the respective battery blocks are being charged; means for identifying a first battery block of the plurality of battery blocks that yields a charging voltage measurement higher than a charging voltage measurement of another of the battery blocks during the first interval; and means for discharging the first battery block to reduce the difference between the charging voltage measurement of the first battery block and the charging voltage measurement of the other of the battery blocks. | 2,800 |
11,467 | 11,467 | 14,988,800 | 2,847 | An electronic component includes an electronic component body and an external electrode. The external electrode is disposed on the electronic component body. The external electrode includes a Pd plating layer and a Ni plating layer. The Pd plating layer defines an outermost layer. The Ni plating layer is disposed inside the Pd plating layer. The Ni plating layer is partly exposed from the Pd plating layer. | 1. An electronic component comprising:
an electronic component body; and an external electrode disposed on the electronic component body; wherein the external electrode includes:
a Pd plating layer that defines an outermost layer; and
a Ni plating layer disposed inside the Pd plating layer;
the Ni plating layer being partially exposed from the Pd plating layer. 2. The electronic component according to claim 1, wherein an exposed portion of the Ni plating layer that is partially exposed from the Pd plating layer is at least partially oxidized. 3. The electronic component according to claim 1, wherein the Pd plating layer includes a pinhole facing the Ni plating layer. 4. The electronic component according to claim 1, wherein the Pd plating layer has a thickness of less than or equal to about 0.02 μm. 5. The electronic component according to claim 1, wherein the electronic component is one of a ceramic capacitor, a piezoelectric component, a thermistor, and an inductor. 6. The electronic component according to claim 1, wherein the external electrode further includes a fired electrode layer located under between the electronic component body and the Ni plating layer and the Pd plating layer. 7. The electronic component according to claim 6, wherein the fired electrode layer is made of a paste containing metal and glass. 8. The electronic component according to claim 1, wherein the Pd plating layer includes a plurality of pinholes facing the Ni plating layer, and an area ratio between the area where Ni of the Ni plating layer and an area where Pd of the Pd plating layer is present is about 0.01 to about 0.2. 9. An electronic component-mounted structure comprising:
the electronic component according to claim 1; a mounting substrate on which the electronic component is mounted; and a conductive resin adhesion portion bonding the external electrode and the mounting substrate; wherein the conductive resin adhesion portion is in contact with the Ni plating layer. 10. The electronic component-mounted structure according to claim 9, wherein the Pd plating layer includes a pinhole facing the Ni plating layer and the conductive resin adhesive is located inside of the pinhole to contact with the Ni plating layer. 11. The electronic component-mounted structure according to claim 9, wherein an exposed portion of the Ni plating layer that is partially exposed from the Pd plating layer is at least partially oxidized. 12. The electronic component-mounted structure according to claim 9, wherein the Pd plating layer includes a pinhole facing the Ni plating layer. 13. The electronic component-mounted structure according to claim 9, wherein the Pd plating layer has a thickness of less than or equal to about 0.02 μm. 14. The electronic component-mounted structure according to claim 9, wherein the electronic component is one of a ceramic capacitor, a piezoelectric component, a thermistor, and an inductor. 15. The electronic component-mounted structure according to claim 9, wherein the external electrode further includes a fired electrode layer located under between the electronic component body and the Ni plating layer and the Pd plating layer. 16. The electronic component-mounted structure according to claim 15, wherein the fired electrode layer is made of a paste containing metal and glass. 17. The electronic component-mounted structure according to claim 9, wherein the Pd plating layer includes a plurality of pinholes facing the Ni plating layer, and an area ratio between the area where Ni of the Ni plating layer and an area where Pd of the Pd plating layer is present is about 0.01 to about 0.2. | An electronic component includes an electronic component body and an external electrode. The external electrode is disposed on the electronic component body. The external electrode includes a Pd plating layer and a Ni plating layer. The Pd plating layer defines an outermost layer. The Ni plating layer is disposed inside the Pd plating layer. The Ni plating layer is partly exposed from the Pd plating layer.1. An electronic component comprising:
an electronic component body; and an external electrode disposed on the electronic component body; wherein the external electrode includes:
a Pd plating layer that defines an outermost layer; and
a Ni plating layer disposed inside the Pd plating layer;
the Ni plating layer being partially exposed from the Pd plating layer. 2. The electronic component according to claim 1, wherein an exposed portion of the Ni plating layer that is partially exposed from the Pd plating layer is at least partially oxidized. 3. The electronic component according to claim 1, wherein the Pd plating layer includes a pinhole facing the Ni plating layer. 4. The electronic component according to claim 1, wherein the Pd plating layer has a thickness of less than or equal to about 0.02 μm. 5. The electronic component according to claim 1, wherein the electronic component is one of a ceramic capacitor, a piezoelectric component, a thermistor, and an inductor. 6. The electronic component according to claim 1, wherein the external electrode further includes a fired electrode layer located under between the electronic component body and the Ni plating layer and the Pd plating layer. 7. The electronic component according to claim 6, wherein the fired electrode layer is made of a paste containing metal and glass. 8. The electronic component according to claim 1, wherein the Pd plating layer includes a plurality of pinholes facing the Ni plating layer, and an area ratio between the area where Ni of the Ni plating layer and an area where Pd of the Pd plating layer is present is about 0.01 to about 0.2. 9. An electronic component-mounted structure comprising:
the electronic component according to claim 1; a mounting substrate on which the electronic component is mounted; and a conductive resin adhesion portion bonding the external electrode and the mounting substrate; wherein the conductive resin adhesion portion is in contact with the Ni plating layer. 10. The electronic component-mounted structure according to claim 9, wherein the Pd plating layer includes a pinhole facing the Ni plating layer and the conductive resin adhesive is located inside of the pinhole to contact with the Ni plating layer. 11. The electronic component-mounted structure according to claim 9, wherein an exposed portion of the Ni plating layer that is partially exposed from the Pd plating layer is at least partially oxidized. 12. The electronic component-mounted structure according to claim 9, wherein the Pd plating layer includes a pinhole facing the Ni plating layer. 13. The electronic component-mounted structure according to claim 9, wherein the Pd plating layer has a thickness of less than or equal to about 0.02 μm. 14. The electronic component-mounted structure according to claim 9, wherein the electronic component is one of a ceramic capacitor, a piezoelectric component, a thermistor, and an inductor. 15. The electronic component-mounted structure according to claim 9, wherein the external electrode further includes a fired electrode layer located under between the electronic component body and the Ni plating layer and the Pd plating layer. 16. The electronic component-mounted structure according to claim 15, wherein the fired electrode layer is made of a paste containing metal and glass. 17. The electronic component-mounted structure according to claim 9, wherein the Pd plating layer includes a plurality of pinholes facing the Ni plating layer, and an area ratio between the area where Ni of the Ni plating layer and an area where Pd of the Pd plating layer is present is about 0.01 to about 0.2. | 2,800 |
11,468 | 11,468 | 14,673,524 | 2,898 | In some examples, a processor is configured to predict the presence of ice crystals (e.g., high altitude ice crystals) in a volume of airspace based on radar reflectivity values and one or more other types of information indicative of weather conditions in the volume of airspace, such as one or more of: ambient air temperature and altitude. For example, the processor may predict the ice crystals presence by at least estimating the iced water content level within a volume of airspace of interest based on radar reflectivity values for the volume of airspace (e.g., stored as in a three-dimensional buffer) and other information indicative of weather conditions of the volume of airspace. The processor may estimate the iced water content level using a model that relates the information indicative of weather conditions in and around the volume of interest to iced water content in the atmosphere. | 1. A method comprising:
receiving, by a processor, information indicative of weather in a volume of airspace surrounding a volume of interest, wherein the information comprises radar reflectivity values; and determining, by the processor and based at least in part on a model and the received information, a predicted iced water content level for the volume of interest. 2. The method of claim 1, further comprising:
outputting, by the processor for display at a display device, a graphical indication, wherein the graphical indication is indicative of the predicted iced water content being above a specified level or of one or more ranges of predicted iced water content values. 3. The method of claim 1, wherein the information indicative of weather conditions further comprises one or more of: an aircraft altitude, an altitude of the volume of interest, or an ambient air temperature around the aircraft. 4. The method of claim 1, further comprising:
utilizing, by the processor, the model to determine predicted iced water content level by at least preprocessing one or more of: a freezing altitude calculation, a predicted temperature at the volume of interest, a vertically integrated reflectivity calculation, or an iced-water-content-reflectivity power law value. 5. The method of claim 1, wherein the model comprises a polynomial model of one or more information types and one or more weights associated with the respective information type, wherein the one or more information types are each indicative of the weather in the volume of interest. 6. The method of claim 1, further comprising:
utilizing, by the processor, the model to determine the predicted iced water content level by at least applying a nonlinear regression technique to previously measured information indicative of known weather and corresponding previously measured iced water content. 7. The method of claim 1, wherein the model comprises a plurality of submodels, wherein the plurality of submodels are based on one of an input quantity or an output quantity. 8. The method of claim 1, further comprising:
receiving, by the processor, information indicative of weather in the volume of interest, wherein the information comprises radar reflectivity values; and determining, by the processor and based at least in part on the model, the information indicative of weather in the volume of interest, and the information indicative of weather in the volume of airspace surrounding the volume of interest, the predicted iced water content level for the volume of interest. 9. A system comprising:
a memory configured to store a model and information indicative of weather in a volume of airspace surrounding a volume of interest, wherein the information comprises radar reflectivity values; and a processor configured to determine, based at least in part on the model and the information, a predicted iced water content for the volume of interest. 10. The system of claim 9,
wherein the memory is further configured to store information indicative of weather in the volume of interest, wherein the information comprises radar reflectivity values; and wherein the processor is further configured to determine, based at least in part on the model, the information indicative of weather in the volume of interest, and the information indicative of weather in the volume of airspace surrounding the volume of interest, the predicted iced water content level for the volume of interest. 11. The system of claim 9, wherein the processor is further configured to:
detect a core of a deep convective storm; and determine a distance between the volume of interest and the core. 12. The system of claim 9, further comprising:
a display device configured to display a graphical indication, wherein the graphical indication is output by the processor and indicative of the predicted iced water content being above a specified level or of one or more ranges of predicted iced water content values. 13. The system of claim 9, wherein the information indicative of weather conditions further comprises one or more of: an aircraft altitude, an altitude of the volume of interest, or an ambient air temperature around the aircraft. 14. The system of claim 9, wherein the processor is further configured to:
the model to determine the predicted iced water content level by at least preprocessing one or more of: a freezing altitude calculation, a predicted temperature at the volume of interest, a vertically integrated reflectivity calculation, or an iced-water-content-reflectivity power law value. 15. The system of claim 9, wherein the model comprises a polynomial model of one or more information types and one or more weights associated with the respective information type, wherein the one or more information types are each indicative of the weather in the volume of interest. 16. The system of claim 9, wherein the processor is further configured to:
utilize the model to determine predicted iced water content level by at least applying a nonlinear regression technique to previously measured information indicative of known weather and corresponding previously measured iced water content. 16. The system of claim 9, wherein the model comprises a plurality of submodels. 17. The system of claim 16, wherein the plurality of submodels are based on one of an input quantity or an output quantity. 18. A computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to:
receive information indicative of weather in a volume of airspace surrounding a volume of interest, wherein the information comprises radar reflectivity values; and determine, based at least in part on a model and the received information, a predicted iced water content level for the volume of interest. 19. The computer-readable storage medium of claim 19, wherein the instructions further cause the processor to:
output, for display at a display device, a graphical indication, wherein the graphical indication is indicative of the predicted iced water content being above a specified level or of one or more ranges of predicted iced water content values. 20. The computer-readable storage medium of claim 19, wherein the instructions further cause the processor to:
receive information indicative of weather in the volume of interest, wherein the information comprises radar reflectivity values; and determine, based at least in part on the model, the information indicative of weather in the volume of interest, and the information indicative of weather in the volume of airspace surrounding the volume of interest, the predicted iced water content level for the volume of interest. | In some examples, a processor is configured to predict the presence of ice crystals (e.g., high altitude ice crystals) in a volume of airspace based on radar reflectivity values and one or more other types of information indicative of weather conditions in the volume of airspace, such as one or more of: ambient air temperature and altitude. For example, the processor may predict the ice crystals presence by at least estimating the iced water content level within a volume of airspace of interest based on radar reflectivity values for the volume of airspace (e.g., stored as in a three-dimensional buffer) and other information indicative of weather conditions of the volume of airspace. The processor may estimate the iced water content level using a model that relates the information indicative of weather conditions in and around the volume of interest to iced water content in the atmosphere.1. A method comprising:
receiving, by a processor, information indicative of weather in a volume of airspace surrounding a volume of interest, wherein the information comprises radar reflectivity values; and determining, by the processor and based at least in part on a model and the received information, a predicted iced water content level for the volume of interest. 2. The method of claim 1, further comprising:
outputting, by the processor for display at a display device, a graphical indication, wherein the graphical indication is indicative of the predicted iced water content being above a specified level or of one or more ranges of predicted iced water content values. 3. The method of claim 1, wherein the information indicative of weather conditions further comprises one or more of: an aircraft altitude, an altitude of the volume of interest, or an ambient air temperature around the aircraft. 4. The method of claim 1, further comprising:
utilizing, by the processor, the model to determine predicted iced water content level by at least preprocessing one or more of: a freezing altitude calculation, a predicted temperature at the volume of interest, a vertically integrated reflectivity calculation, or an iced-water-content-reflectivity power law value. 5. The method of claim 1, wherein the model comprises a polynomial model of one or more information types and one or more weights associated with the respective information type, wherein the one or more information types are each indicative of the weather in the volume of interest. 6. The method of claim 1, further comprising:
utilizing, by the processor, the model to determine the predicted iced water content level by at least applying a nonlinear regression technique to previously measured information indicative of known weather and corresponding previously measured iced water content. 7. The method of claim 1, wherein the model comprises a plurality of submodels, wherein the plurality of submodels are based on one of an input quantity or an output quantity. 8. The method of claim 1, further comprising:
receiving, by the processor, information indicative of weather in the volume of interest, wherein the information comprises radar reflectivity values; and determining, by the processor and based at least in part on the model, the information indicative of weather in the volume of interest, and the information indicative of weather in the volume of airspace surrounding the volume of interest, the predicted iced water content level for the volume of interest. 9. A system comprising:
a memory configured to store a model and information indicative of weather in a volume of airspace surrounding a volume of interest, wherein the information comprises radar reflectivity values; and a processor configured to determine, based at least in part on the model and the information, a predicted iced water content for the volume of interest. 10. The system of claim 9,
wherein the memory is further configured to store information indicative of weather in the volume of interest, wherein the information comprises radar reflectivity values; and wherein the processor is further configured to determine, based at least in part on the model, the information indicative of weather in the volume of interest, and the information indicative of weather in the volume of airspace surrounding the volume of interest, the predicted iced water content level for the volume of interest. 11. The system of claim 9, wherein the processor is further configured to:
detect a core of a deep convective storm; and determine a distance between the volume of interest and the core. 12. The system of claim 9, further comprising:
a display device configured to display a graphical indication, wherein the graphical indication is output by the processor and indicative of the predicted iced water content being above a specified level or of one or more ranges of predicted iced water content values. 13. The system of claim 9, wherein the information indicative of weather conditions further comprises one or more of: an aircraft altitude, an altitude of the volume of interest, or an ambient air temperature around the aircraft. 14. The system of claim 9, wherein the processor is further configured to:
the model to determine the predicted iced water content level by at least preprocessing one or more of: a freezing altitude calculation, a predicted temperature at the volume of interest, a vertically integrated reflectivity calculation, or an iced-water-content-reflectivity power law value. 15. The system of claim 9, wherein the model comprises a polynomial model of one or more information types and one or more weights associated with the respective information type, wherein the one or more information types are each indicative of the weather in the volume of interest. 16. The system of claim 9, wherein the processor is further configured to:
utilize the model to determine predicted iced water content level by at least applying a nonlinear regression technique to previously measured information indicative of known weather and corresponding previously measured iced water content. 16. The system of claim 9, wherein the model comprises a plurality of submodels. 17. The system of claim 16, wherein the plurality of submodels are based on one of an input quantity or an output quantity. 18. A computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to:
receive information indicative of weather in a volume of airspace surrounding a volume of interest, wherein the information comprises radar reflectivity values; and determine, based at least in part on a model and the received information, a predicted iced water content level for the volume of interest. 19. The computer-readable storage medium of claim 19, wherein the instructions further cause the processor to:
output, for display at a display device, a graphical indication, wherein the graphical indication is indicative of the predicted iced water content being above a specified level or of one or more ranges of predicted iced water content values. 20. The computer-readable storage medium of claim 19, wherein the instructions further cause the processor to:
receive information indicative of weather in the volume of interest, wherein the information comprises radar reflectivity values; and determine, based at least in part on the model, the information indicative of weather in the volume of interest, and the information indicative of weather in the volume of airspace surrounding the volume of interest, the predicted iced water content level for the volume of interest. | 2,800 |
11,469 | 11,469 | 15,028,769 | 2,826 | Some aspects determining formation gas composition during well drilling can be implemented as a computer-implemented method, a computer-readable medium, or a computer system. A theoretical diffusion coefficient for a drilling fluid that comprises gas from a formation through which the drilling fluid is flowed is determined. The theoretical diffusion coefficient is based on an extraction of all of the gas from the drilling fluid. An experimental diffusion coefficient for the drilling fluid based on well drilling parameters is determined. A concentration of the gas at the formation is determined based, at least in part, on a difference between the theoretical diffusion coefficient and the experimental diffusion coefficient. The determined concentration at the formation is provided. | 1. A computer-implemented method comprising:
determining a theoretical diffusion coefficient for a drilling fluid comprising a gas from a formation, the theoretical diffusion coefficient determined based on an extraction of all of the gas from the drilling fluid; determining an experimental diffusion coefficient for the drilling fluid based on well drilling parameters including a flow rate of the drilling fluid through the well; determining a concentration of the gas at the formation based, at least in part, on a difference between the theoretical diffusion coefficient and the experimental diffusion coefficient; and providing the determined concentration of the gas at the formation. 2. The method of claim 1, wherein determining the theoretical diffusion coefficient comprises solving Fick's first law of diffusion or Fick's second law of diffusion for the theoretical diffusion coefficient. 3. The method of claim 1, wherein determining the theoretical diffusion coefficient and the experimental diffusion coefficient comprises determining the theoretical diffusion coefficient and the experimental diffusion coefficient from sample data describing the drilling fluid carrying the gas near the formation. 4. The method of claim 1, wherein determining the theoretical diffusion coefficient and the experimental diffusion coefficient comprises determining the theoretical diffusion coefficient and the experimental diffusion coefficient from sample data describing the drilling fluid carrying the gas at the surface. 5. The method of claim 4, wherein determining the theoretical diffusion coefficient and the experimental diffusion coefficient from sample data comprises measuring the concentration of the gas in a sample of the drilling fluid using one or more of gas chromatography, liquid chromatography, and mass spectrometry. 6. The method of claim 1, wherein determining the experimental diffusion coefficient comprises:
identifying physical and chemical properties of the drilling fluid at an instant in time; and determining the experimental diffusion coefficient for the drilling fluid having the identified physical and chemical properties at the instant in time. 7. The method of claim 6, wherein determining the experimental diffusion coefficient comprises providing the identified physical and chemical properties at the instant in time to a mathematical model that determines the experimental coefficient based on the identified physical and chemical properties at the instant in time. 8. The method of claim 1, further comprising determining a plurality of experimental diffusion coefficients of the gas at the formation at a respective plurality of sequential instances in time. 9. The method of claim 8, further comprising periodically determining the concentration of the gas at the formation based, at least in part, on a plurality of differences between the theoretical diffusion coefficient and the plurality of experimental diffusion coefficients. 10. The method of claim 1, further comprising:
determining a plurality of concentrations of the gas at a corresponding plurality of formations, each concentration of gas determined based, at least in part, on a difference between the theoretical diffusion coefficient and a corresponding experimental diffusion coefficient determined for each formation; comparing the plurality of concentrations with each other, determining that a first concentration at a first formation is similar to a second concentration at a second formation; and determining that the first formation is similar to the second formation based on determining that the first concentration at the first formation is similar to the second concentration at the second formation. 11. A non-transitory computer-readable medium storing instructions executable by one or more processors to perform operations comprising:
determining a theoretical diffusion coefficient for a drilling fluid comprising a gas from a formation, the theoretical diffusion coefficient determined based on an extraction of all of the gas from the drilling fluid; determining an experimental diffusion coefficient for the drilling fluid based on well drilling parameters including a flow rate of the drilling fluid through the well; determining a concentration of the gas at the formation based, at least in part, on a difference between the theoretical diffusion coefficient and the experimental diffusion coefficient; and providing the determined concentration of the gas at the formation. 12. The medium of claim 11, wherein determining the theoretical diffusion coefficient comprises solving Fick's first law of diffusion or Fick's second law of diffusion for the theoretical diffusion coefficient. 13. The medium of claim 11, wherein determining the theoretical diffusion coefficient and the experimental diffusion coefficient comprises determining the theoretical diffusion coefficient and the experimental diffusion coefficient from sample data describing the drilling fluid carrying the gas near the formation. 14. The medium of claim 11, wherein determining the theoretical diffusion coefficient and the experimental diffusion coefficient comprises determining the theoretical diffusion coefficient and the experimental diffusion coefficient from sample data describing the drilling fluid carrying the gas at the surface. 15. The medium of claim 14, wherein the sample data comprises the concentration of the gasmeasured using one or more of gas chromatography, liquid chromatography, or mass spectrometry. 16. A system comprising:
one or more processors; and a computer-readable medium storing instructions executable by the one or more processors to perform operations comprising:
determining a theoretical diffusion coefficient for a drilling fluid comprising a gas from a formation, the theoretical diffusion coefficient determined based on an extraction of all of the gas from the drilling fluid;
determining an experimental diffusion coefficient for the drilling fluid based on well drilling parameters including a flow rate of the drilling fluid through the well;
determining a concentration of the gas at the formation based, at least in part, on a difference between the theoretical diffusion coefficient and the experimental diffusion coefficient; and
providing the determined concentration of the gas at the formation. 17. The system of claim 16, wherein determining the experimental diffusion coefficient comprises:
identifying physical and chemical properties of the drilling fluid at an instant in time; and determining the experimental diffusion coefficient for the drilling fluid having the identified physical and chemical properties at the instant in time. 18. The system of claim 17, wherein determining the experimental diffusion coefficient comprises providing the identified physical and chemical properties at the instant in time to a mathematical model that determines the experimental coefficient based on the identified physical and chemical properties at the instant in time. 19. The system of claim 16, the operations further comprising determining a plurality of experimental diffusion coefficients of the gas at the formation at a respective plurality of sequential instances in time. 20. The system of claim 19, the operations further comprising periodically determining the concentration of the gas at the formation based, at least in part, on a plurality of differences between the theoretical diffusion coefficient and the plurality of experimental diffusion coefficients. | Some aspects determining formation gas composition during well drilling can be implemented as a computer-implemented method, a computer-readable medium, or a computer system. A theoretical diffusion coefficient for a drilling fluid that comprises gas from a formation through which the drilling fluid is flowed is determined. The theoretical diffusion coefficient is based on an extraction of all of the gas from the drilling fluid. An experimental diffusion coefficient for the drilling fluid based on well drilling parameters is determined. A concentration of the gas at the formation is determined based, at least in part, on a difference between the theoretical diffusion coefficient and the experimental diffusion coefficient. The determined concentration at the formation is provided.1. A computer-implemented method comprising:
determining a theoretical diffusion coefficient for a drilling fluid comprising a gas from a formation, the theoretical diffusion coefficient determined based on an extraction of all of the gas from the drilling fluid; determining an experimental diffusion coefficient for the drilling fluid based on well drilling parameters including a flow rate of the drilling fluid through the well; determining a concentration of the gas at the formation based, at least in part, on a difference between the theoretical diffusion coefficient and the experimental diffusion coefficient; and providing the determined concentration of the gas at the formation. 2. The method of claim 1, wherein determining the theoretical diffusion coefficient comprises solving Fick's first law of diffusion or Fick's second law of diffusion for the theoretical diffusion coefficient. 3. The method of claim 1, wherein determining the theoretical diffusion coefficient and the experimental diffusion coefficient comprises determining the theoretical diffusion coefficient and the experimental diffusion coefficient from sample data describing the drilling fluid carrying the gas near the formation. 4. The method of claim 1, wherein determining the theoretical diffusion coefficient and the experimental diffusion coefficient comprises determining the theoretical diffusion coefficient and the experimental diffusion coefficient from sample data describing the drilling fluid carrying the gas at the surface. 5. The method of claim 4, wherein determining the theoretical diffusion coefficient and the experimental diffusion coefficient from sample data comprises measuring the concentration of the gas in a sample of the drilling fluid using one or more of gas chromatography, liquid chromatography, and mass spectrometry. 6. The method of claim 1, wherein determining the experimental diffusion coefficient comprises:
identifying physical and chemical properties of the drilling fluid at an instant in time; and determining the experimental diffusion coefficient for the drilling fluid having the identified physical and chemical properties at the instant in time. 7. The method of claim 6, wherein determining the experimental diffusion coefficient comprises providing the identified physical and chemical properties at the instant in time to a mathematical model that determines the experimental coefficient based on the identified physical and chemical properties at the instant in time. 8. The method of claim 1, further comprising determining a plurality of experimental diffusion coefficients of the gas at the formation at a respective plurality of sequential instances in time. 9. The method of claim 8, further comprising periodically determining the concentration of the gas at the formation based, at least in part, on a plurality of differences between the theoretical diffusion coefficient and the plurality of experimental diffusion coefficients. 10. The method of claim 1, further comprising:
determining a plurality of concentrations of the gas at a corresponding plurality of formations, each concentration of gas determined based, at least in part, on a difference between the theoretical diffusion coefficient and a corresponding experimental diffusion coefficient determined for each formation; comparing the plurality of concentrations with each other, determining that a first concentration at a first formation is similar to a second concentration at a second formation; and determining that the first formation is similar to the second formation based on determining that the first concentration at the first formation is similar to the second concentration at the second formation. 11. A non-transitory computer-readable medium storing instructions executable by one or more processors to perform operations comprising:
determining a theoretical diffusion coefficient for a drilling fluid comprising a gas from a formation, the theoretical diffusion coefficient determined based on an extraction of all of the gas from the drilling fluid; determining an experimental diffusion coefficient for the drilling fluid based on well drilling parameters including a flow rate of the drilling fluid through the well; determining a concentration of the gas at the formation based, at least in part, on a difference between the theoretical diffusion coefficient and the experimental diffusion coefficient; and providing the determined concentration of the gas at the formation. 12. The medium of claim 11, wherein determining the theoretical diffusion coefficient comprises solving Fick's first law of diffusion or Fick's second law of diffusion for the theoretical diffusion coefficient. 13. The medium of claim 11, wherein determining the theoretical diffusion coefficient and the experimental diffusion coefficient comprises determining the theoretical diffusion coefficient and the experimental diffusion coefficient from sample data describing the drilling fluid carrying the gas near the formation. 14. The medium of claim 11, wherein determining the theoretical diffusion coefficient and the experimental diffusion coefficient comprises determining the theoretical diffusion coefficient and the experimental diffusion coefficient from sample data describing the drilling fluid carrying the gas at the surface. 15. The medium of claim 14, wherein the sample data comprises the concentration of the gasmeasured using one or more of gas chromatography, liquid chromatography, or mass spectrometry. 16. A system comprising:
one or more processors; and a computer-readable medium storing instructions executable by the one or more processors to perform operations comprising:
determining a theoretical diffusion coefficient for a drilling fluid comprising a gas from a formation, the theoretical diffusion coefficient determined based on an extraction of all of the gas from the drilling fluid;
determining an experimental diffusion coefficient for the drilling fluid based on well drilling parameters including a flow rate of the drilling fluid through the well;
determining a concentration of the gas at the formation based, at least in part, on a difference between the theoretical diffusion coefficient and the experimental diffusion coefficient; and
providing the determined concentration of the gas at the formation. 17. The system of claim 16, wherein determining the experimental diffusion coefficient comprises:
identifying physical and chemical properties of the drilling fluid at an instant in time; and determining the experimental diffusion coefficient for the drilling fluid having the identified physical and chemical properties at the instant in time. 18. The system of claim 17, wherein determining the experimental diffusion coefficient comprises providing the identified physical and chemical properties at the instant in time to a mathematical model that determines the experimental coefficient based on the identified physical and chemical properties at the instant in time. 19. The system of claim 16, the operations further comprising determining a plurality of experimental diffusion coefficients of the gas at the formation at a respective plurality of sequential instances in time. 20. The system of claim 19, the operations further comprising periodically determining the concentration of the gas at the formation based, at least in part, on a plurality of differences between the theoretical diffusion coefficient and the plurality of experimental diffusion coefficients. | 2,800 |
11,470 | 11,470 | 15,466,671 | 2,853 | The invention relates to a litho sheet for electrochemical roughening, consisting of a rolled aluminium alloy, wherein the sheet surface has a topography with a maximum peak height Rp or Sp of not more than 1.4 μm, preferably not more than 1.2 μm, in particular not more than 1.0 μm. The invention also relates to a method which is intended for producing a litho sheet and in the case of which a litho sheet consisting of an aluminium alloy is cold-rolled and in the case of which the litho sheet, following the final cold-rolling pass, is subjected to a degreasing treatment with a pickling step using an aqueous pickling medium. | 1. Ctp-printing plate manufactured from a litho strip for electrochemical roughening, comprising a rolled aluminium alloy, wherein a strip surface of the litho strip has a topography with a maximum peak height Rp and/or Sp of a maximum of 1.4 μm, wherein the topography of the litho strip surface is essentially an imprint of a rolling topography of a final cold rolling step conducted after a controlled degreasing treatment with simultaneous pickling until a surface erosion of at least 0.25 g/m2 is achieved. 2. Ctp-printing plate according to claim 1, wherein the strip surface has a topography with a reduced peak height of Rpk and/or Spk of a maximum of 0.4 μm, preferably a maximum of 0.37 μm. 3. Ctp-printing plate according to claim 1, wherein the thickness of the litho strip is between 0.5 mm and 0.1 mm. 4. Ctp-printing plate according to claim 1, wherein the litho strip consists of an AA1050, AA1100, AA3103 or AlMg0.5 alloy. 5. Ctp-printing plate according to claim 1, wherein the litho strip has the following alloy composition in percent by weight:
0.3
%
≤
Fe
≤
1.0
%
0.05
%
≤
Mg
≤
0.6
%
0.05
%
≤
Si
≤
0.25
%
Mn
≤
0.05
%
Cu
≤
0.04
%
plus residual Al and unavoidable impurities, to an individual maximum of 0.05% and totalling a maximum of 0.15%. 6. Ctp-printing plate according to claim 1, wherein the litho strip has the following alloy content in percent by weight:
0.3
%
≤
Fe
≤
0.4
%
0.1
%
≤
Mg
≤
0.3
%
0.05
%
≤
Si
≤
0.25
%
Mn
≤
0.05
%
Cu
≤
0.04
%
7. Ctp-printing plate according to claim 1, wherein the impurities in the alloy of the litho strip have the following threshold values in percent by weight:
Cr
≤
0.01
%
Zn
≤
0.02
%
Ti
≤
0.04
%
B
≤
50
ppm
. 8. Method for the manufacture of a Ctp-printing plate, comprising a process in which a litho strip consisting of an aluminium alloy is cold rolled in a final cold rolling step and in which after the final cold rolling step the litho strip is subject to a controlled degreasing process with a simultaneous pickling process in an aqueous pickling medium, wherein the aqueous pickling medium contains at least 1.5% to 3% by weight of a mixture of 5% to 40% sodium tripolyphosphate, 3% to 10% sodium gluconate, 3% to 8% non-ionic and anionic surfactants and optionally 0.5% to 70% soda and the sodium hydroxide concentration in the aqueous pickling medium is between 0.1% and 5% by weight, wherein the controlled degreasing treatment with simultaneous pickling is conducted until a surface erosion caused thereby is at least 0.25 g/m2. 9. Method according to claim 8, wherein the sodium hydroxide concentration in the aqueous pickling medium is between 2% and 3.5% by weight and optionally the degreasing treatment with pickling takes place at temperatures between 70° C. and 85° C. for a duration of between 1 and 3.5 seconds. 10. Method according to claim 8, wherein the pickling temperature is between 76° C. and 84° C. and/or the sodium hydroxide concentration in the aqueous pickling medium is between 2.6% and 3.5% by weight. 11. Method according to claim 8, wherein the pickling duration is between 1 and 2 seconds, preferably between 1.1 and 1.9 seconds. 12. Method according to claim 8, wherein the litho strip is rolled to a final thickness of 0.5 mm to 0.1 mm in the final cold rolling step. 13. Method according to claim 8, wherein AA1050, AA1100, AA3103 or AlMg0.5 are used as an aluminium alloy. 14. Method for the manufacture of a printing plate carrier, wherein the printing plate carrier has a topography with a maximum peak height Rp and/or Sp of a maximum of 1.4 μm, at which the printing plate carrier is manufactured from a litho strip according to claim 1. 15. Use of a printing plate carrier manufactured according to claim 14 for a CtP printing plate. 16. Ctp-printing plate according to claim 1, wherein a strip surface of the litho strip has a topography with a maximum peak height Rp and/or Sp of a maximum of 1.2 μm. 17. Ctp-printing plate according to claim 1, wherein a strip surface of the litho strip has a topography with a maximum peak height Rp and/or Sp of a maximum of 1.0 μm. 18. Method according to claim 8, wherein the printing plate carrier has a photosensitive coating with a thickness of less than 2 μm. | The invention relates to a litho sheet for electrochemical roughening, consisting of a rolled aluminium alloy, wherein the sheet surface has a topography with a maximum peak height Rp or Sp of not more than 1.4 μm, preferably not more than 1.2 μm, in particular not more than 1.0 μm. The invention also relates to a method which is intended for producing a litho sheet and in the case of which a litho sheet consisting of an aluminium alloy is cold-rolled and in the case of which the litho sheet, following the final cold-rolling pass, is subjected to a degreasing treatment with a pickling step using an aqueous pickling medium.1. Ctp-printing plate manufactured from a litho strip for electrochemical roughening, comprising a rolled aluminium alloy, wherein a strip surface of the litho strip has a topography with a maximum peak height Rp and/or Sp of a maximum of 1.4 μm, wherein the topography of the litho strip surface is essentially an imprint of a rolling topography of a final cold rolling step conducted after a controlled degreasing treatment with simultaneous pickling until a surface erosion of at least 0.25 g/m2 is achieved. 2. Ctp-printing plate according to claim 1, wherein the strip surface has a topography with a reduced peak height of Rpk and/or Spk of a maximum of 0.4 μm, preferably a maximum of 0.37 μm. 3. Ctp-printing plate according to claim 1, wherein the thickness of the litho strip is between 0.5 mm and 0.1 mm. 4. Ctp-printing plate according to claim 1, wherein the litho strip consists of an AA1050, AA1100, AA3103 or AlMg0.5 alloy. 5. Ctp-printing plate according to claim 1, wherein the litho strip has the following alloy composition in percent by weight:
0.3
%
≤
Fe
≤
1.0
%
0.05
%
≤
Mg
≤
0.6
%
0.05
%
≤
Si
≤
0.25
%
Mn
≤
0.05
%
Cu
≤
0.04
%
plus residual Al and unavoidable impurities, to an individual maximum of 0.05% and totalling a maximum of 0.15%. 6. Ctp-printing plate according to claim 1, wherein the litho strip has the following alloy content in percent by weight:
0.3
%
≤
Fe
≤
0.4
%
0.1
%
≤
Mg
≤
0.3
%
0.05
%
≤
Si
≤
0.25
%
Mn
≤
0.05
%
Cu
≤
0.04
%
7. Ctp-printing plate according to claim 1, wherein the impurities in the alloy of the litho strip have the following threshold values in percent by weight:
Cr
≤
0.01
%
Zn
≤
0.02
%
Ti
≤
0.04
%
B
≤
50
ppm
. 8. Method for the manufacture of a Ctp-printing plate, comprising a process in which a litho strip consisting of an aluminium alloy is cold rolled in a final cold rolling step and in which after the final cold rolling step the litho strip is subject to a controlled degreasing process with a simultaneous pickling process in an aqueous pickling medium, wherein the aqueous pickling medium contains at least 1.5% to 3% by weight of a mixture of 5% to 40% sodium tripolyphosphate, 3% to 10% sodium gluconate, 3% to 8% non-ionic and anionic surfactants and optionally 0.5% to 70% soda and the sodium hydroxide concentration in the aqueous pickling medium is between 0.1% and 5% by weight, wherein the controlled degreasing treatment with simultaneous pickling is conducted until a surface erosion caused thereby is at least 0.25 g/m2. 9. Method according to claim 8, wherein the sodium hydroxide concentration in the aqueous pickling medium is between 2% and 3.5% by weight and optionally the degreasing treatment with pickling takes place at temperatures between 70° C. and 85° C. for a duration of between 1 and 3.5 seconds. 10. Method according to claim 8, wherein the pickling temperature is between 76° C. and 84° C. and/or the sodium hydroxide concentration in the aqueous pickling medium is between 2.6% and 3.5% by weight. 11. Method according to claim 8, wherein the pickling duration is between 1 and 2 seconds, preferably between 1.1 and 1.9 seconds. 12. Method according to claim 8, wherein the litho strip is rolled to a final thickness of 0.5 mm to 0.1 mm in the final cold rolling step. 13. Method according to claim 8, wherein AA1050, AA1100, AA3103 or AlMg0.5 are used as an aluminium alloy. 14. Method for the manufacture of a printing plate carrier, wherein the printing plate carrier has a topography with a maximum peak height Rp and/or Sp of a maximum of 1.4 μm, at which the printing plate carrier is manufactured from a litho strip according to claim 1. 15. Use of a printing plate carrier manufactured according to claim 14 for a CtP printing plate. 16. Ctp-printing plate according to claim 1, wherein a strip surface of the litho strip has a topography with a maximum peak height Rp and/or Sp of a maximum of 1.2 μm. 17. Ctp-printing plate according to claim 1, wherein a strip surface of the litho strip has a topography with a maximum peak height Rp and/or Sp of a maximum of 1.0 μm. 18. Method according to claim 8, wherein the printing plate carrier has a photosensitive coating with a thickness of less than 2 μm. | 2,800 |
11,471 | 11,471 | 15,256,640 | 2,896 | Method for manufacturing an electronic semiconductor package, in which method an electronic chip ( 100 ) is coupled to a carrier, the electronic chip is at least partially encapsulated by means of an encapsulation structure having a discontinuity, and the carrier is partially encapsulated, and at least one part of the discontinuity and a volume connected thereto adjoining an exposed surface section of the carrier are covered by an electrically insulating thermal interface structure, which electrically decouples at least one part of the carrier with respect to its surroundings. | 1. Method for manufacturing an electronic semiconductor package, wherein the method comprises:
coupling an electronic chip to a carrier; encapsulating the electronic chip at least partially and encapsulating the carrier partially by an encapsulation structure having a discontinuity; covering at least a part of the discontinuity and a volume connected thereto, which adjoins an exposed surface section of the carrier, with an electrically insulating thermal interface structure, which electrically decouples at least a part of the carrier with respect to a surrounding. 2. Method in accordance with claim 1, wherein the thermal interface structure for providing a thermal coupling is formed between the carrier and a heat dissipation element, which is connectable to the thermal interface structure. 3. Method in accordance with claim 1, wherein the method comprises a formation of the discontinuity during the encapsulation. 4. Method in accordance with claim 3, wherein the discontinuity is formed by a protrusion, at an encapsulation tool, shaped inversely to the discontinuity, whereby encapsulation material is precluded from flowing into the discontinuity. 5. Method in accordance with claim 1, wherein the method comprises a formation of the discontinuity after the encapsulation. 6. Method in accordance with claim 5, wherein the discontinuity is formed by removing material of the encapsulation structure after curing material of the encapsulation structure. 7. Method in accordance with claim 5, wherein the discontinuity is formed by at least one of the group consisting of a laser treatment, grinding, scraping, a plasma treatment and etching. 8. Method in accordance with claim 5, wherein the encapsulation structure has a waxy surface layer outside the discontinuity, wherein the method comprises a removal of material of the encapsulation structure to form the discontinuity down to such a depth that the waxy surface layer is removed locally at the site of the discontinuity, so that the discontinuity is delimited at least in sections by a rough wall of the encapsulation structure, which is formed by filling particles below the waxy surface layer. 9. Method in accordance with claim 5, wherein the discontinuity is formed by removing material of the encapsulation structure, wherein the carrier is used as a removal stop during the removal. 10. Method in accordance with claim 1, wherein the discontinuity is formed as a closed, annular discontinuity. 11. Method in accordance with claim 10, wherein the closed, annular discontinuity is formed to surround the exposed surface section of the carrier completely. 12. Method in accordance with claim 1, wherein the carrier is an electric carrier, which is coupled electrically to the electronic chip. 13. Method in accordance with claim 1, wherein the discontinuity is selected from a group consisting of a recess, a protrusion, a cavity, an indentation, scoring, roughening, and a step. 14. Method in accordance with claim 1, wherein the covering is selected from a group consisting of printing the thermal interface structure onto the discontinuity and onto the connected volume, dispersing material onto the discontinuity and onto the connected volume for forming the thermal interface structure, laminating the thermal interface structure onto the discontinuity and onto the connected volume, form pressing the thermal interface structure onto the discontinuity and onto the connected volume, and immersing at least a part of an external surface of the encapsulated electronic chip and the encapsulated carrier into an at least partially liquid precursor for forming the thermal interface structure. 15. Method in accordance with claim 1, wherein the method comprises a connection of a heat dissipation element with the thermal interface structure. 16-26. (canceled) | Method for manufacturing an electronic semiconductor package, in which method an electronic chip ( 100 ) is coupled to a carrier, the electronic chip is at least partially encapsulated by means of an encapsulation structure having a discontinuity, and the carrier is partially encapsulated, and at least one part of the discontinuity and a volume connected thereto adjoining an exposed surface section of the carrier are covered by an electrically insulating thermal interface structure, which electrically decouples at least one part of the carrier with respect to its surroundings.1. Method for manufacturing an electronic semiconductor package, wherein the method comprises:
coupling an electronic chip to a carrier; encapsulating the electronic chip at least partially and encapsulating the carrier partially by an encapsulation structure having a discontinuity; covering at least a part of the discontinuity and a volume connected thereto, which adjoins an exposed surface section of the carrier, with an electrically insulating thermal interface structure, which electrically decouples at least a part of the carrier with respect to a surrounding. 2. Method in accordance with claim 1, wherein the thermal interface structure for providing a thermal coupling is formed between the carrier and a heat dissipation element, which is connectable to the thermal interface structure. 3. Method in accordance with claim 1, wherein the method comprises a formation of the discontinuity during the encapsulation. 4. Method in accordance with claim 3, wherein the discontinuity is formed by a protrusion, at an encapsulation tool, shaped inversely to the discontinuity, whereby encapsulation material is precluded from flowing into the discontinuity. 5. Method in accordance with claim 1, wherein the method comprises a formation of the discontinuity after the encapsulation. 6. Method in accordance with claim 5, wherein the discontinuity is formed by removing material of the encapsulation structure after curing material of the encapsulation structure. 7. Method in accordance with claim 5, wherein the discontinuity is formed by at least one of the group consisting of a laser treatment, grinding, scraping, a plasma treatment and etching. 8. Method in accordance with claim 5, wherein the encapsulation structure has a waxy surface layer outside the discontinuity, wherein the method comprises a removal of material of the encapsulation structure to form the discontinuity down to such a depth that the waxy surface layer is removed locally at the site of the discontinuity, so that the discontinuity is delimited at least in sections by a rough wall of the encapsulation structure, which is formed by filling particles below the waxy surface layer. 9. Method in accordance with claim 5, wherein the discontinuity is formed by removing material of the encapsulation structure, wherein the carrier is used as a removal stop during the removal. 10. Method in accordance with claim 1, wherein the discontinuity is formed as a closed, annular discontinuity. 11. Method in accordance with claim 10, wherein the closed, annular discontinuity is formed to surround the exposed surface section of the carrier completely. 12. Method in accordance with claim 1, wherein the carrier is an electric carrier, which is coupled electrically to the electronic chip. 13. Method in accordance with claim 1, wherein the discontinuity is selected from a group consisting of a recess, a protrusion, a cavity, an indentation, scoring, roughening, and a step. 14. Method in accordance with claim 1, wherein the covering is selected from a group consisting of printing the thermal interface structure onto the discontinuity and onto the connected volume, dispersing material onto the discontinuity and onto the connected volume for forming the thermal interface structure, laminating the thermal interface structure onto the discontinuity and onto the connected volume, form pressing the thermal interface structure onto the discontinuity and onto the connected volume, and immersing at least a part of an external surface of the encapsulated electronic chip and the encapsulated carrier into an at least partially liquid precursor for forming the thermal interface structure. 15. Method in accordance with claim 1, wherein the method comprises a connection of a heat dissipation element with the thermal interface structure. 16-26. (canceled) | 2,800 |
11,472 | 11,472 | 15,596,063 | 2,833 | The present disclosure provides a conductive member for a circuit breaker high voltage portion conductor assembly, the conductive member including a body with a transfer portion and a coupling portion. The body transfer portion has an electro-thermally efficient contour. That is, the body transfer portion has an electrically efficient contour and a thermally efficient contour. The body transfer portion includes a number of slots defining fins. In this configuration, the body transfer portion distributes current generally evenly across a cross-sectional area of the conductive member body. Further, the fins provide heat dissipation via convection. | 1. A conductive member for a circuit breaker high voltage portion conductor assembly, said conductive member comprising:
a body; said body includes a transfer portion and a coupling portion; and wherein said body transfer portion has an electrically efficient contour. 2. The conductive member of claim 1 wherein:
wherein said body transfer portion also has a thermally efficient contour; and
whereby said body transfer portion has an electro-thermally efficient contour. 3. The conductive member of claim 2 wherein said body transfer portion includes a number of slots extending through said body transfer portion. 4. The conductive member of claim 3 wherein:
each slot extends generally vertically through said body transfer portion;
wherein said slots define a number of fins;
wherein said number of fins includes a number of inner fins, each inner fin disposed between adjacent slots; and
wherein said number of fins includes two outer fins, each outer fin disposed between a slot and the adjacent outer lateral side of body transfer portion. 5. The conductive member of claim 4 wherein:
said body transfer portion includes a centerline;
each fin has a thickness; and
wherein each said fin thickness increases the further a fin is from said body transfer portion centerline. 6. The conductive member of claim 4 wherein:
said number of fins includes a number of sets of fins; and
each fin in a set of fins having substantially the same thickness as other fins in the same set. 7. The conductive member of claim 1 wherein:
said body transfer portion is substantially cylindrical;
said body transfer portion includes a number of slots extending through said body transfer portion;
wherein each slot extends generally vertically through said body transfer portion; and
wherein said slots define a number of fins. 8. The conductive member of claim 7 wherein each slot is one of wider at the top and narrow at the bottom, or, narrower at the top and wider at the bottom. 9. The conductive member of claim 1 wherein said body is a unitary body. 10. The conductive member of claim 1 wherein said body is an aluminum body. 11. A vacuum circuit breaker comprising:
a low voltage portion, and high voltage portion; said low voltage portion including an operating mechanism; said low voltage portion operatively coupled to said high voltage portion; said high voltage portion including a conductor assembly and a vacuum interrupter assembly; said conductor assembly including a first terminal, a primary first conductor, a primary second conductor, and a second terminal; said vacuum interrupter assembly including first stem assembly, a first contact, a second contact, a second stem assembly, and a vacuum housing; said first contact coupled to, and in electrical communication with, said first stem assembly; said first stem assembly coupled to, and in electrical communication with, said first conductor; said second contact coupled to, and in electrical communication with, said second stem assembly; said second stem assembly coupled to, and in electrical communication with, said second conductor; said first contact disposed in said vacuum housing; said second contact movably disposed in said vacuum housing; said operating mechanism operatively coupled to said second contact, wherein said second contact is structured to move between a first position, wherein said second contact assembly contact member is not directly coupled to said first contact assembly contact member, and a second position, wherein said second contact assembly contact member is coupled to, and in electrical communication with, said first contact assembly contact member; wherein one of said primary first conductor or said primary second conductor includes a body; said body includes a transfer portion and a coupling portion; and wherein said body transfer portion has an electrically efficient contour. 12. The vacuum circuit breaker of claim 11 wherein:
wherein said body transfer portion also has a thermally efficient contour; and
whereby said body transfer portion has an electro-thermally efficient contour. 13. The vacuum circuit breaker of claim 12 wherein said body transfer portion includes a number of slots extending through said body transfer portion. 14. The vacuum circuit breaker of claim 13 wherein:
each slot extends generally vertically through said body transfer portion;
wherein said slots define a number of fins;
wherein said number of fins includes a number of inner fins, each inner fin disposed between adjacent slots; and
wherein said number of fins includes two outer fins, each outer fin disposed between a slot and the adjacent outer lateral side of body transfer portion. 15. The vacuum circuit breaker of claim 14 wherein:
said body transfer portion includes a centerline;
each fin has a thickness; and
wherein each said fin thickness increases the further a fin is from said body transfer portion centerline. 16. The vacuum circuit breaker of claim 14 wherein:
said number of fins includes a number of sets of fins; and
each fin in a set of fins having substantially the same thickness as other fins in the same set. 17. The vacuum circuit breaker of claim 11 wherein:
said body transfer portion is substantially cylindrical;
said body transfer portion includes a number of slots extending through said body transfer portion;
wherein each slot extends generally vertically through said body transfer portion; and
wherein said slots define a number of fins. 18. The vacuum circuit breaker of claim 17 wherein each slot is one of wider at the top and narrow at the bottom, or, narrower at the top and wider at the bottom. 19. The vacuum circuit breaker of claim 11 wherein said body is a unitary body. 20. The vacuum circuit breaker of claim 11 wherein said body is an aluminum body. | The present disclosure provides a conductive member for a circuit breaker high voltage portion conductor assembly, the conductive member including a body with a transfer portion and a coupling portion. The body transfer portion has an electro-thermally efficient contour. That is, the body transfer portion has an electrically efficient contour and a thermally efficient contour. The body transfer portion includes a number of slots defining fins. In this configuration, the body transfer portion distributes current generally evenly across a cross-sectional area of the conductive member body. Further, the fins provide heat dissipation via convection.1. A conductive member for a circuit breaker high voltage portion conductor assembly, said conductive member comprising:
a body; said body includes a transfer portion and a coupling portion; and wherein said body transfer portion has an electrically efficient contour. 2. The conductive member of claim 1 wherein:
wherein said body transfer portion also has a thermally efficient contour; and
whereby said body transfer portion has an electro-thermally efficient contour. 3. The conductive member of claim 2 wherein said body transfer portion includes a number of slots extending through said body transfer portion. 4. The conductive member of claim 3 wherein:
each slot extends generally vertically through said body transfer portion;
wherein said slots define a number of fins;
wherein said number of fins includes a number of inner fins, each inner fin disposed between adjacent slots; and
wherein said number of fins includes two outer fins, each outer fin disposed between a slot and the adjacent outer lateral side of body transfer portion. 5. The conductive member of claim 4 wherein:
said body transfer portion includes a centerline;
each fin has a thickness; and
wherein each said fin thickness increases the further a fin is from said body transfer portion centerline. 6. The conductive member of claim 4 wherein:
said number of fins includes a number of sets of fins; and
each fin in a set of fins having substantially the same thickness as other fins in the same set. 7. The conductive member of claim 1 wherein:
said body transfer portion is substantially cylindrical;
said body transfer portion includes a number of slots extending through said body transfer portion;
wherein each slot extends generally vertically through said body transfer portion; and
wherein said slots define a number of fins. 8. The conductive member of claim 7 wherein each slot is one of wider at the top and narrow at the bottom, or, narrower at the top and wider at the bottom. 9. The conductive member of claim 1 wherein said body is a unitary body. 10. The conductive member of claim 1 wherein said body is an aluminum body. 11. A vacuum circuit breaker comprising:
a low voltage portion, and high voltage portion; said low voltage portion including an operating mechanism; said low voltage portion operatively coupled to said high voltage portion; said high voltage portion including a conductor assembly and a vacuum interrupter assembly; said conductor assembly including a first terminal, a primary first conductor, a primary second conductor, and a second terminal; said vacuum interrupter assembly including first stem assembly, a first contact, a second contact, a second stem assembly, and a vacuum housing; said first contact coupled to, and in electrical communication with, said first stem assembly; said first stem assembly coupled to, and in electrical communication with, said first conductor; said second contact coupled to, and in electrical communication with, said second stem assembly; said second stem assembly coupled to, and in electrical communication with, said second conductor; said first contact disposed in said vacuum housing; said second contact movably disposed in said vacuum housing; said operating mechanism operatively coupled to said second contact, wherein said second contact is structured to move between a first position, wherein said second contact assembly contact member is not directly coupled to said first contact assembly contact member, and a second position, wherein said second contact assembly contact member is coupled to, and in electrical communication with, said first contact assembly contact member; wherein one of said primary first conductor or said primary second conductor includes a body; said body includes a transfer portion and a coupling portion; and wherein said body transfer portion has an electrically efficient contour. 12. The vacuum circuit breaker of claim 11 wherein:
wherein said body transfer portion also has a thermally efficient contour; and
whereby said body transfer portion has an electro-thermally efficient contour. 13. The vacuum circuit breaker of claim 12 wherein said body transfer portion includes a number of slots extending through said body transfer portion. 14. The vacuum circuit breaker of claim 13 wherein:
each slot extends generally vertically through said body transfer portion;
wherein said slots define a number of fins;
wherein said number of fins includes a number of inner fins, each inner fin disposed between adjacent slots; and
wherein said number of fins includes two outer fins, each outer fin disposed between a slot and the adjacent outer lateral side of body transfer portion. 15. The vacuum circuit breaker of claim 14 wherein:
said body transfer portion includes a centerline;
each fin has a thickness; and
wherein each said fin thickness increases the further a fin is from said body transfer portion centerline. 16. The vacuum circuit breaker of claim 14 wherein:
said number of fins includes a number of sets of fins; and
each fin in a set of fins having substantially the same thickness as other fins in the same set. 17. The vacuum circuit breaker of claim 11 wherein:
said body transfer portion is substantially cylindrical;
said body transfer portion includes a number of slots extending through said body transfer portion;
wherein each slot extends generally vertically through said body transfer portion; and
wherein said slots define a number of fins. 18. The vacuum circuit breaker of claim 17 wherein each slot is one of wider at the top and narrow at the bottom, or, narrower at the top and wider at the bottom. 19. The vacuum circuit breaker of claim 11 wherein said body is a unitary body. 20. The vacuum circuit breaker of claim 11 wherein said body is an aluminum body. | 2,800 |
11,473 | 11,473 | 15,139,393 | 2,834 | A wound stator for a dynamo-electric machine comprising a stator stack having a unitary cylindrical yoke and a plurality of circumferentially spaced, radially inward extending stator teeth defining stator slots therebetween. A winding is formed by a strand of wire forming turns around each stator tooth, each winding including a first lead end extending from a stator slot on a first side of a respective stator tooth and a second lead end extending from a stator slot on a second side of the respective stator tooth. An insulation system is provided including an insulating structure septum extending through each stator slot between windings located on two adjacent stator teeth, the turns of each winding located between a respective stator tooth and a first surface of the insulating structure septum engaged with the winding. | 1. A wound stator for a dynamo-electric machine comprising:
a stator stack comprising a unitary cylindrical yoke and a plurality of circumferentially spaced, radially inward extending stator teeth defining stator slots therebetween; a winding formed by a strand of wire forming turns around each stator tooth, each winding including a first lead end extending from a stator slot on a first side of a respective stator tooth and a second lead end extending from a stator slot on a second side of the respective stator tooth; and an insulation system including an insulating structure extending through each stator slot between windings located on two adjacent stator teeth, the turns of each winding located between a respective stator tooth and a first surface of the insulating structure engaged with the winding. 2. The wound stator of claim 1, wherein the insulating structure further includes a second surface connected to the first surface of the insulating structure, each second surface being located between the turns of a winding and a respective stator tooth. 3. The wound stator of claim 2, wherein the first and second surfaces of the insulating structure each have radius portions, each radius portion having a radius that intersects a central axis of a wire turn engaged on a respective surface of the insulating structure. 4. The wound stator of claim 3, wherein the insulating structure comprises an insert member located in each stator slot, each insert member having axially extending holes for receiving respective turns of a winding, and each hole defining respective first and second surfaces of the insulating structure. 5. The wound stator of claim 4, wherein the holes are located in a row extending in a radial direction. 6. The wound stator of claim 5, including one or more additional holes located adjacent to and circumferentially displaced from each row of holes. 7. The wound stator of claim 2, wherein the insulating structure comprises an insert member located in each stator slot, each insert member having a pair of insert slots and each insert slot defined by circumferentially spaced, radially elongated walls defining the first and second surfaces of the insulating structure. 8. The wound stator of claim 7, wherein a radially inner end of the insert slots includes walls circumferentially spaced about equal to a diameter of the strand of wire. 9. The wound stator of claim 8, wherein a radially outer end of the insert slots is circumferentially spaced about equal to twice the diameter of the strand of wire. 10. The wound stator of claim 7, including axially extending rib structures on the first and second surfaces, the rib structures extending between adjacent turns of a winding. 11. The wound stator of claim 10, wherein the rib structures extending between adjacent turns of the winding define discrete curved surfaces for engaging the turns of the winding. 12. The wound stator of claim 2, wherein the insulating structure includes a radially inner wall extending in a gap between inner ends of the adjacent stator teeth and a radially outer wall extending along an inner surface of the yoke, and the first and second surfaces of the insulating structure are connected to the radially inner and outer walls. 13. The wound stator of claim 2, wherein the insulation system includes an end lamina defining an axially outer side of the stator teeth having circumferential grooves defining radially spaced positions between adjacent end turns of a respective winding located in the grooves. 14. A wound stator for a dynamo-electric machine comprising:
a stator stack comprising a unitary cylindrical yoke and a plurality of circumferentially spaced, radially inward extending stator teeth defining stator slots therebetween; a winding formed by a strand of wire forming turns around each stator tooth, each winding including a first lead end extending from a stator slot on a first side of a respective stator tooth and a second lead end extending from a stator slot on a second side of the respective stator tooth; and an insulation system including an insulating septum wall extending through each stator slot between windings located on adjacent stator teeth and filling interstitial space defined between the windings on the adjacent stator teeth. 15. The wound stator of claim 14, wherein the insulation system includes a radially inner wall extending in a gap between inner ends of the adjacent stator teeth and a radially outer wall extending along an inner surface of the yoke, and the septum wall is connected to the radially inner and outer walls. 16. The wound stator of claim 15, wherein the insulation system includes stator slot lining walls connected to the radially inner and outer walls and extending radially along surfaces of the adjacent stator teeth between respective windings and stator teeth. 17. The wound stator of claim 16, including a row of axially extending holes located between the septum wall and each stator slot lining wall, and a turn of the wire strand for one winding extending through each hole in a respective row. 18. The wound stator of claim 17, including one or more additional holes located between each row of holes and a respective septum wall. 19. The wound stator of claim 17, wherein the insulation system includes end lamina defining an axially outer side of the stator teeth having circumferential grooves defining radially spaced positions between adjacent end turns of a respective winding located in the grooves. 20. The wound stator of claim 19, wherein the insulation system isolates adjacent turns in each winding from contact with each other within the slots and at the end turns. 21. The wound stator of claim 15, wherein the insulation system comprises an insert member located in each stator slot, each insert member having a pair of insert slots located on either side of the septum wall, and each insert slot comprising a radially elongated and axially extending opening between the septum wall and a stator slot lining wall. 22. The wound stator of claim 21, wherein each insert slot is dimensioned in the circumferential direction to define a space about equal to a diameter of the strand of wire. 23. The wound stator of claim 22, wherein the walls defining the radially elongated openings define discrete rib structures extending between adjacent turns of a winding. 24. A wound stator for a dynamo-electric machine comprising:
a stator stack comprising a cylindrical yoke and a plurality of circumferentially spaced, radially inward extending stator teeth defining stator slots therebetween; a non-conductive insert member located within each slot; each insert member including a plurality of axially extending holes, each hole defining a guide passage that is electrically isolated from the stator teeth; at least one strand of wire forming a winding spanning circumferentially across a stator tooth between first and second insert members located on either side of the stator tooth. 25. The wound stator of claim 24, wherein the holes in the insert members are arranged in rows, each row being oriented in a generally radial direction of a respective slot. 26. The wound stator of claim 25, wherein each insert member includes two rows of holes located on circumferentially spaced sides of each slot adjacent to a tooth. 27. The wound stator of claim 26, including additional axially extending holes located between the two rows of holes. | A wound stator for a dynamo-electric machine comprising a stator stack having a unitary cylindrical yoke and a plurality of circumferentially spaced, radially inward extending stator teeth defining stator slots therebetween. A winding is formed by a strand of wire forming turns around each stator tooth, each winding including a first lead end extending from a stator slot on a first side of a respective stator tooth and a second lead end extending from a stator slot on a second side of the respective stator tooth. An insulation system is provided including an insulating structure septum extending through each stator slot between windings located on two adjacent stator teeth, the turns of each winding located between a respective stator tooth and a first surface of the insulating structure septum engaged with the winding.1. A wound stator for a dynamo-electric machine comprising:
a stator stack comprising a unitary cylindrical yoke and a plurality of circumferentially spaced, radially inward extending stator teeth defining stator slots therebetween; a winding formed by a strand of wire forming turns around each stator tooth, each winding including a first lead end extending from a stator slot on a first side of a respective stator tooth and a second lead end extending from a stator slot on a second side of the respective stator tooth; and an insulation system including an insulating structure extending through each stator slot between windings located on two adjacent stator teeth, the turns of each winding located between a respective stator tooth and a first surface of the insulating structure engaged with the winding. 2. The wound stator of claim 1, wherein the insulating structure further includes a second surface connected to the first surface of the insulating structure, each second surface being located between the turns of a winding and a respective stator tooth. 3. The wound stator of claim 2, wherein the first and second surfaces of the insulating structure each have radius portions, each radius portion having a radius that intersects a central axis of a wire turn engaged on a respective surface of the insulating structure. 4. The wound stator of claim 3, wherein the insulating structure comprises an insert member located in each stator slot, each insert member having axially extending holes for receiving respective turns of a winding, and each hole defining respective first and second surfaces of the insulating structure. 5. The wound stator of claim 4, wherein the holes are located in a row extending in a radial direction. 6. The wound stator of claim 5, including one or more additional holes located adjacent to and circumferentially displaced from each row of holes. 7. The wound stator of claim 2, wherein the insulating structure comprises an insert member located in each stator slot, each insert member having a pair of insert slots and each insert slot defined by circumferentially spaced, radially elongated walls defining the first and second surfaces of the insulating structure. 8. The wound stator of claim 7, wherein a radially inner end of the insert slots includes walls circumferentially spaced about equal to a diameter of the strand of wire. 9. The wound stator of claim 8, wherein a radially outer end of the insert slots is circumferentially spaced about equal to twice the diameter of the strand of wire. 10. The wound stator of claim 7, including axially extending rib structures on the first and second surfaces, the rib structures extending between adjacent turns of a winding. 11. The wound stator of claim 10, wherein the rib structures extending between adjacent turns of the winding define discrete curved surfaces for engaging the turns of the winding. 12. The wound stator of claim 2, wherein the insulating structure includes a radially inner wall extending in a gap between inner ends of the adjacent stator teeth and a radially outer wall extending along an inner surface of the yoke, and the first and second surfaces of the insulating structure are connected to the radially inner and outer walls. 13. The wound stator of claim 2, wherein the insulation system includes an end lamina defining an axially outer side of the stator teeth having circumferential grooves defining radially spaced positions between adjacent end turns of a respective winding located in the grooves. 14. A wound stator for a dynamo-electric machine comprising:
a stator stack comprising a unitary cylindrical yoke and a plurality of circumferentially spaced, radially inward extending stator teeth defining stator slots therebetween; a winding formed by a strand of wire forming turns around each stator tooth, each winding including a first lead end extending from a stator slot on a first side of a respective stator tooth and a second lead end extending from a stator slot on a second side of the respective stator tooth; and an insulation system including an insulating septum wall extending through each stator slot between windings located on adjacent stator teeth and filling interstitial space defined between the windings on the adjacent stator teeth. 15. The wound stator of claim 14, wherein the insulation system includes a radially inner wall extending in a gap between inner ends of the adjacent stator teeth and a radially outer wall extending along an inner surface of the yoke, and the septum wall is connected to the radially inner and outer walls. 16. The wound stator of claim 15, wherein the insulation system includes stator slot lining walls connected to the radially inner and outer walls and extending radially along surfaces of the adjacent stator teeth between respective windings and stator teeth. 17. The wound stator of claim 16, including a row of axially extending holes located between the septum wall and each stator slot lining wall, and a turn of the wire strand for one winding extending through each hole in a respective row. 18. The wound stator of claim 17, including one or more additional holes located between each row of holes and a respective septum wall. 19. The wound stator of claim 17, wherein the insulation system includes end lamina defining an axially outer side of the stator teeth having circumferential grooves defining radially spaced positions between adjacent end turns of a respective winding located in the grooves. 20. The wound stator of claim 19, wherein the insulation system isolates adjacent turns in each winding from contact with each other within the slots and at the end turns. 21. The wound stator of claim 15, wherein the insulation system comprises an insert member located in each stator slot, each insert member having a pair of insert slots located on either side of the septum wall, and each insert slot comprising a radially elongated and axially extending opening between the septum wall and a stator slot lining wall. 22. The wound stator of claim 21, wherein each insert slot is dimensioned in the circumferential direction to define a space about equal to a diameter of the strand of wire. 23. The wound stator of claim 22, wherein the walls defining the radially elongated openings define discrete rib structures extending between adjacent turns of a winding. 24. A wound stator for a dynamo-electric machine comprising:
a stator stack comprising a cylindrical yoke and a plurality of circumferentially spaced, radially inward extending stator teeth defining stator slots therebetween; a non-conductive insert member located within each slot; each insert member including a plurality of axially extending holes, each hole defining a guide passage that is electrically isolated from the stator teeth; at least one strand of wire forming a winding spanning circumferentially across a stator tooth between first and second insert members located on either side of the stator tooth. 25. The wound stator of claim 24, wherein the holes in the insert members are arranged in rows, each row being oriented in a generally radial direction of a respective slot. 26. The wound stator of claim 25, wherein each insert member includes two rows of holes located on circumferentially spaced sides of each slot adjacent to a tooth. 27. The wound stator of claim 26, including additional axially extending holes located between the two rows of holes. | 2,800 |
11,474 | 11,474 | 14,751,878 | 2,872 | A directional privacy display may include a waveguide; and an array of light sources and spatial light modulator that operate in a time sequential manner. The waveguide may include light extraction features arranged to direct light from an array of light sources by total internal reflection to an array of viewing windows and a reflector arranged to direct light from the waveguide by transmission through extraction features of the waveguide to the same array of viewing windows. First and second phases may be temporally multiplexed with respective primary and secondary images and primary and secondary angular illumination distributions. An efficient and bright privacy display may be provided with obscured primary image visibility for off-axis observers. | 1. A directional display apparatus comprising:
a directional backlight comprising a waveguide comprising first and second, opposed guide surfaces for guiding input light along the waveguide, and an array of light sources arranged to generate the input light at different input positions across the waveguide, wherein the first guide surface is arranged to guide light by total internal reflection, the second guide surface comprises a plurality of light extraction features arranged to deflect light guided through the waveguide out of the waveguide through the first guide surface as output light and intermediate regions between the light extraction features that are arranged to guide light along the waveguide, and the waveguide is arranged to direct the output light into optical windows in output directions that are distributed in a lateral direction in dependence on the input position of the input light; a transmissive spatial light modulator arranged to receive the output light from the first guide surface of the waveguide and to modulate it to display an image; and a control system capable of controlling the spatial light modulator and capable of selectively operating of light sources to direct light into corresponding optical windows, wherein stray light in the directional backlight is directed in output directions outside the optical windows corresponding to selectively operated light sources, the control system is arranged to control the spatial light modulator and the array of light sources in synchronization with each other so that: (a) the spatial light modulator displays a primary image while at least one primary light source is selectively operated to direct light into at least one primary optical window for viewing by a primary observer, and (b) in a temporally multiplexed manner with the display of the primary image, the spatial light modulator displays a secondary image while at least one light source other than the at least one primary light source is selectively operated to direct light into secondary optical windows outside the at least one primary optical window, the secondary image as perceived by a secondary observer outside the primary optical window obscuring the primary image that modulates the stray light directed outside the primary optical window. 2. A directional display apparatus according to claim 1, wherein said at least one light source other than the at least one primary light source that is selectively operated to direct light into secondary optical windows outside the at least one primary optical window comprises plural light sources other than the at least one primary light source. 3. A directional display apparatus according to claim 2, wherein said plural light sources other than the at least one primary light source are selectively operated to output light with differing luminous flux. 4. A directional display apparatus according to claim 1, wherein the control system is arranged to control the spatial light modulator and the array of light sources in synchronization with each other so that:
(a) while the spatial light modulator displays the primary image, at least one additional light source in addition to the at least one primary light source is selectively operated to direct light into an additional optical window, and (b) while the spatial light modulator displays the secondary image, the plural light sources include the at least one additional light source and other light sources, the additional light source being operated to output light with higher luminous flux than the other light sources. 5. A directional display apparatus according to claim 1, wherein the at least one additional light source changes in different temporal phases of operation. 6. A directional display apparatus according to claim 1, wherein the secondary image comprises an inverted copy of the primary image arranged to at least partly cancel the primary image that modulates the stray light directed outside the primary optical window, as perceived by the primary observer. 7. A directional display apparatus according to claim 6, wherein the control system is arranged to control the spatial light modulator and the array of light sources so that the secondary image has the same luminance as the primary image that modulates the stray light directed outside the primary optical window. 8. A directional display apparatus according to claim 6, wherein the inverted copy of the primary image comprises a copy of the primary image inverted by an inversion function varies spatially across the image. 9. A directional display apparatus according to claim 8, wherein the inversion function varies spatially across the image in correspondence with a spatial variation of the luminance of the output windows. 10. A directional display apparatus according to claim 2, wherein the secondary image comprises the inverted copy of the primary image superimposed by a disruptive pattern. 11. A directional display apparatus according to claim 1, wherein the secondary image comprises a disruptive pattern. 12. A directional display apparatus according to claim 11, wherein the primary image comprises an image for display to the primary observer superimposed by an inverted copy of the disruptive pattern arranged to at least partly cancel the disruptive pattern that modulates the stray light directed outside the secondary optical window, as perceived by the primary observer. 13. A directional display apparatus according to claim 1, wherein the control system is arranged to control the spatial light modulator and the array of light sources in synchronization with each other so that the spatial light modulator displays a primary image and the secondary image in a temporally multiplexed manner in time slots of unequal length. 14. A directional display apparatus according to claim 1, wherein the spatial light modulator comprises an array of pixels and the control system is arranged to control the spatial light modulator to control the drive level of each pixel during the temporally multiplexed display of the primary and secondary images taking into account the desired grey level of the pixel and the expected hysteresis of the pixel. 15. A directional display apparatus according to claim 1, wherein the primary image is a two dimensional image. 16. A directional display apparatus according to claim 1, wherein the primary image is a three dimensional image comprising a left eye image and a right eye image, and the control system is arranged to control the spatial light modulator to display the primary image by (a1) controlling the spatial light modulator to display the left eye image and the right eye image in a temporally multiplexed manner, and (a2) in synchronization with the control of the spatial light modulator, controlling the array of light sources to selectively operate different primary light sources to direct light into at least one primary optical window for viewing by the left and right eyes of the primary observer, when the spatial light modulator displays the left eye image and the right eye image, respectively. 17. A directional display apparatus according to claim 16, wherein the secondary image is a two dimensional image. 18. A directional display apparatus according to claim 1, wherein the second guide surface has a stepped shape comprising facets, that are said light extraction features, and the intermediate regions. 19. A directional display apparatus according to claim 18, wherein the directional backlight further comprises a rear reflector comprising a linear array of reflective facets arranged to reflect light from the light sources that is transmitted through the plurality of facets of the waveguide, back through the waveguide to exit through the first guide surface into said optical windows. 20. A directional display apparatus according to claim 1, wherein the light extraction features have positive optical power in the lateral direction. 21. A directional display apparatus according to claim 1, wherein the waveguide further comprises an input end, the array of light sources being arranged along the input end. 22. A directional display apparatus according to claim 1, wherein the waveguide further comprises a reflective end for reflecting input light back through the waveguide, the second guide surface being arranged to deflect light as output light through the first guide surface after reflection from the reflective end. 23. A directional display apparatus according to claim 22, wherein the reflective end has positive optical power in the lateral direction. 24. A directional display apparatus according to claim 1, wherein the waveguide further comprises a reflective end that is elongated in a lateral direction, the first and second guide surfaces extending from laterally extending edges of the reflective end, the waveguide further comprising side surfaces extending between the first and second guide surfaces, and
wherein the light sources include an array of light sources arranged along a side surface to provide said input light through that side surface, and the reflective end comprises first and second facets alternating with each other in the lateral direction, the first facets being reflective and forming reflective facets of a Fresnel reflector having positive optical power in the lateral direction, the second facets forming draft facets of the Fresnel reflector, the Fresnel reflector having an optical axis that is inclined towards the side surface in a direction in which the Fresnel reflector deflects input light from the array of light sources into the waveguide. 25. A directional display apparatus according to claim 1, further comprising a sensor system arranged to detect the position of the head of the primary observer, the control system being arranged to control the light sources in accordance with the detected position of the head of the observer. 26. A directional display apparatus according to claim 25, wherein
the sensor system is arranged to detect a secondary observer outside the primary optical window, and the control system is arranged, in response to detecting the secondary observer, to perform said control of the spatial light modulator and the array of light sources in synchronization with each other so that the spatial light modulator displays the primary image and the secondary image in a temporally multiplexed manner, and, in response to not detecting the secondary observer, to control the spatial light modulator and the array of light sources so that the spatial light modulator displays the primary image while at least one primary light source is selectively operated to direct light into at least one primary optical window for viewing by a primary observer, without displaying the secondary image in a temporally multiplexed manner. 27. A method of obscuring a primary image that modulates stray light directed outside the primary optical window in a directional display apparatus comprising:
a directional backlight comprising a waveguide comprising first and second, opposed guide surfaces for guiding input light along the waveguide, and an array of light sources arranged to generate the input light at different input positions across the waveguide, wherein the first guide surface is arranged to guide light by total internal reflection, the second guide surface comprises a plurality of light extraction features arranged to deflect light guided through the waveguide out of the waveguide through the first guide surface as output light and intermediate regions between the light extraction features that are arranged to guide light along the waveguide, and the waveguide is arranged to direct the output light into optical windows in output directions that are distributed in a lateral direction in dependence on the input position of the input light so that selectively operation of light sources causes light to be directed into corresponding optical windows, wherein stray light in the directional backlight is directed in output directions outside the optical windows corresponding to selectively operated light sources; and a transmissive spatial light modulator arranged to receive the output light from the first guide surface of the waveguide and to modulate it to display an image; the method comprising controlling the spatial light modulator and the array of light sources in synchronization with each other so that: (a) the spatial light modulator displays a primary image while at least one primary light source is selectively operated to direct light into at least one primary optical window for viewing by a primary observer, and (b) in a temporally multiplexed manner with the display of the primary image, the spatial light modulator displays a secondary image while at least one light source other than the at least one primary light source is selectively operated to direct light into secondary optical windows outside the at least one primary optical window, the secondary image as perceived by a secondary observer outside the primary optical window obscuring the primary image that modulates the stray light directed outside the primary optical window. | A directional privacy display may include a waveguide; and an array of light sources and spatial light modulator that operate in a time sequential manner. The waveguide may include light extraction features arranged to direct light from an array of light sources by total internal reflection to an array of viewing windows and a reflector arranged to direct light from the waveguide by transmission through extraction features of the waveguide to the same array of viewing windows. First and second phases may be temporally multiplexed with respective primary and secondary images and primary and secondary angular illumination distributions. An efficient and bright privacy display may be provided with obscured primary image visibility for off-axis observers.1. A directional display apparatus comprising:
a directional backlight comprising a waveguide comprising first and second, opposed guide surfaces for guiding input light along the waveguide, and an array of light sources arranged to generate the input light at different input positions across the waveguide, wherein the first guide surface is arranged to guide light by total internal reflection, the second guide surface comprises a plurality of light extraction features arranged to deflect light guided through the waveguide out of the waveguide through the first guide surface as output light and intermediate regions between the light extraction features that are arranged to guide light along the waveguide, and the waveguide is arranged to direct the output light into optical windows in output directions that are distributed in a lateral direction in dependence on the input position of the input light; a transmissive spatial light modulator arranged to receive the output light from the first guide surface of the waveguide and to modulate it to display an image; and a control system capable of controlling the spatial light modulator and capable of selectively operating of light sources to direct light into corresponding optical windows, wherein stray light in the directional backlight is directed in output directions outside the optical windows corresponding to selectively operated light sources, the control system is arranged to control the spatial light modulator and the array of light sources in synchronization with each other so that: (a) the spatial light modulator displays a primary image while at least one primary light source is selectively operated to direct light into at least one primary optical window for viewing by a primary observer, and (b) in a temporally multiplexed manner with the display of the primary image, the spatial light modulator displays a secondary image while at least one light source other than the at least one primary light source is selectively operated to direct light into secondary optical windows outside the at least one primary optical window, the secondary image as perceived by a secondary observer outside the primary optical window obscuring the primary image that modulates the stray light directed outside the primary optical window. 2. A directional display apparatus according to claim 1, wherein said at least one light source other than the at least one primary light source that is selectively operated to direct light into secondary optical windows outside the at least one primary optical window comprises plural light sources other than the at least one primary light source. 3. A directional display apparatus according to claim 2, wherein said plural light sources other than the at least one primary light source are selectively operated to output light with differing luminous flux. 4. A directional display apparatus according to claim 1, wherein the control system is arranged to control the spatial light modulator and the array of light sources in synchronization with each other so that:
(a) while the spatial light modulator displays the primary image, at least one additional light source in addition to the at least one primary light source is selectively operated to direct light into an additional optical window, and (b) while the spatial light modulator displays the secondary image, the plural light sources include the at least one additional light source and other light sources, the additional light source being operated to output light with higher luminous flux than the other light sources. 5. A directional display apparatus according to claim 1, wherein the at least one additional light source changes in different temporal phases of operation. 6. A directional display apparatus according to claim 1, wherein the secondary image comprises an inverted copy of the primary image arranged to at least partly cancel the primary image that modulates the stray light directed outside the primary optical window, as perceived by the primary observer. 7. A directional display apparatus according to claim 6, wherein the control system is arranged to control the spatial light modulator and the array of light sources so that the secondary image has the same luminance as the primary image that modulates the stray light directed outside the primary optical window. 8. A directional display apparatus according to claim 6, wherein the inverted copy of the primary image comprises a copy of the primary image inverted by an inversion function varies spatially across the image. 9. A directional display apparatus according to claim 8, wherein the inversion function varies spatially across the image in correspondence with a spatial variation of the luminance of the output windows. 10. A directional display apparatus according to claim 2, wherein the secondary image comprises the inverted copy of the primary image superimposed by a disruptive pattern. 11. A directional display apparatus according to claim 1, wherein the secondary image comprises a disruptive pattern. 12. A directional display apparatus according to claim 11, wherein the primary image comprises an image for display to the primary observer superimposed by an inverted copy of the disruptive pattern arranged to at least partly cancel the disruptive pattern that modulates the stray light directed outside the secondary optical window, as perceived by the primary observer. 13. A directional display apparatus according to claim 1, wherein the control system is arranged to control the spatial light modulator and the array of light sources in synchronization with each other so that the spatial light modulator displays a primary image and the secondary image in a temporally multiplexed manner in time slots of unequal length. 14. A directional display apparatus according to claim 1, wherein the spatial light modulator comprises an array of pixels and the control system is arranged to control the spatial light modulator to control the drive level of each pixel during the temporally multiplexed display of the primary and secondary images taking into account the desired grey level of the pixel and the expected hysteresis of the pixel. 15. A directional display apparatus according to claim 1, wherein the primary image is a two dimensional image. 16. A directional display apparatus according to claim 1, wherein the primary image is a three dimensional image comprising a left eye image and a right eye image, and the control system is arranged to control the spatial light modulator to display the primary image by (a1) controlling the spatial light modulator to display the left eye image and the right eye image in a temporally multiplexed manner, and (a2) in synchronization with the control of the spatial light modulator, controlling the array of light sources to selectively operate different primary light sources to direct light into at least one primary optical window for viewing by the left and right eyes of the primary observer, when the spatial light modulator displays the left eye image and the right eye image, respectively. 17. A directional display apparatus according to claim 16, wherein the secondary image is a two dimensional image. 18. A directional display apparatus according to claim 1, wherein the second guide surface has a stepped shape comprising facets, that are said light extraction features, and the intermediate regions. 19. A directional display apparatus according to claim 18, wherein the directional backlight further comprises a rear reflector comprising a linear array of reflective facets arranged to reflect light from the light sources that is transmitted through the plurality of facets of the waveguide, back through the waveguide to exit through the first guide surface into said optical windows. 20. A directional display apparatus according to claim 1, wherein the light extraction features have positive optical power in the lateral direction. 21. A directional display apparatus according to claim 1, wherein the waveguide further comprises an input end, the array of light sources being arranged along the input end. 22. A directional display apparatus according to claim 1, wherein the waveguide further comprises a reflective end for reflecting input light back through the waveguide, the second guide surface being arranged to deflect light as output light through the first guide surface after reflection from the reflective end. 23. A directional display apparatus according to claim 22, wherein the reflective end has positive optical power in the lateral direction. 24. A directional display apparatus according to claim 1, wherein the waveguide further comprises a reflective end that is elongated in a lateral direction, the first and second guide surfaces extending from laterally extending edges of the reflective end, the waveguide further comprising side surfaces extending between the first and second guide surfaces, and
wherein the light sources include an array of light sources arranged along a side surface to provide said input light through that side surface, and the reflective end comprises first and second facets alternating with each other in the lateral direction, the first facets being reflective and forming reflective facets of a Fresnel reflector having positive optical power in the lateral direction, the second facets forming draft facets of the Fresnel reflector, the Fresnel reflector having an optical axis that is inclined towards the side surface in a direction in which the Fresnel reflector deflects input light from the array of light sources into the waveguide. 25. A directional display apparatus according to claim 1, further comprising a sensor system arranged to detect the position of the head of the primary observer, the control system being arranged to control the light sources in accordance with the detected position of the head of the observer. 26. A directional display apparatus according to claim 25, wherein
the sensor system is arranged to detect a secondary observer outside the primary optical window, and the control system is arranged, in response to detecting the secondary observer, to perform said control of the spatial light modulator and the array of light sources in synchronization with each other so that the spatial light modulator displays the primary image and the secondary image in a temporally multiplexed manner, and, in response to not detecting the secondary observer, to control the spatial light modulator and the array of light sources so that the spatial light modulator displays the primary image while at least one primary light source is selectively operated to direct light into at least one primary optical window for viewing by a primary observer, without displaying the secondary image in a temporally multiplexed manner. 27. A method of obscuring a primary image that modulates stray light directed outside the primary optical window in a directional display apparatus comprising:
a directional backlight comprising a waveguide comprising first and second, opposed guide surfaces for guiding input light along the waveguide, and an array of light sources arranged to generate the input light at different input positions across the waveguide, wherein the first guide surface is arranged to guide light by total internal reflection, the second guide surface comprises a plurality of light extraction features arranged to deflect light guided through the waveguide out of the waveguide through the first guide surface as output light and intermediate regions between the light extraction features that are arranged to guide light along the waveguide, and the waveguide is arranged to direct the output light into optical windows in output directions that are distributed in a lateral direction in dependence on the input position of the input light so that selectively operation of light sources causes light to be directed into corresponding optical windows, wherein stray light in the directional backlight is directed in output directions outside the optical windows corresponding to selectively operated light sources; and a transmissive spatial light modulator arranged to receive the output light from the first guide surface of the waveguide and to modulate it to display an image; the method comprising controlling the spatial light modulator and the array of light sources in synchronization with each other so that: (a) the spatial light modulator displays a primary image while at least one primary light source is selectively operated to direct light into at least one primary optical window for viewing by a primary observer, and (b) in a temporally multiplexed manner with the display of the primary image, the spatial light modulator displays a secondary image while at least one light source other than the at least one primary light source is selectively operated to direct light into secondary optical windows outside the at least one primary optical window, the secondary image as perceived by a secondary observer outside the primary optical window obscuring the primary image that modulates the stray light directed outside the primary optical window. | 2,800 |
11,475 | 11,475 | 14,461,193 | 2,862 | Method for using a non-stationary, multi-scale domain transformation to combine multiple geophysical data sources, for example seismic data and well log data, into one coherent reservoir model. The seismic data are inverted ( 71 ) to obtain one or more geophysical properties which are converted using petrophysical relationships to a subsurface model of a reservoir property such as porosity or shale volume fraction. The well log data are used to generate a geostatistical forward model ( 72 ) of the reservoir property. Both models of the reservoir property are transformed to a joint space/scale domain, of order >1, where processing is applied ( 73 ) to merge the models into a coherent way into a single model before inverse transforming back to the space domain ( 74 ). The transform is a non-stationary multi-scale transform such as a wavelet, ridgelet, or curvelet transform. The processing may be by, for example, information theory or convex combination. | 1. A method for integrating well log and seismic data into a single subsurface reservoir model, comprising:
(a) obtaining seismic data and well log data from a subsurface region; (b) inverting the seismic data and applying a petrophysical transformation to generate a subsurface model of a reservoir property; (c) generating a reservoir model of the reservoir property using the well log data; (d) transforming the reservoir property model from inverting seismic data and the reservoir property model from reservoir modeling with well log data, to a joint domain, of order >1; (e) processing the transformed models in the joint domain to coherently combine them into one reservoir model; and (f) inverse transforming to obtain a reservoir model in space domain;
wherein (b)-(f) are performed using a computer. 2. The method of claim 1, wherein the transforming is performed using a non-stationary multi-scale transform. 3. The method of claim 2, wherein the non-stationary multi-scale transform is one of: a wavelet transform; a ridgelet transform; a curvelet transform; and second generation wavelets and lifting schemes. 4. The method of claim 1, wherein the processing is one of a heuristic method using information theory; a convex combination with spatially co-located weighting coefficients; and another processing method. 5. The method of claim 4, wherein the information theory method comprises minimizing or maximizing Shannon's entropy to determine which data source—seismic or well log—within the joint domain to choose at each cell in a discrete computational grid in order to generate a merged data output. 6. The method of claim 4, wherein the convex combination method further comprises:
obtaining a third co-located data source, being weighting fields to be used to indicate how to combine the reservoir model and the model derived from inverted seismic data; transforming the weighting fields to the joint domain; and using the weighting fields to combine the transformed models. 7. The method of claim 1, wherein the joint domain is of order 2, being space and scale;
the transform is a wavelet transform; and the processing is by a heuristic method using information theory. 8. The method of claim 1, wherein the joint domain is of order 2, being space and scale; the transform is a wavelet transform; and the processing uses convex combination with spatially co-located weighting coefficients. 9. The method of claim 1, wherein the joint domain is of order 3, being space, scale and azimuth; the transform is a curvelet transform; and the processing is by a heuristic method using information theory. 10. The method of claim 1, wherein the joint domain is of order 3, being space, scale and azimuth; the transform is a curvelet transform; and the processing uses convex combination with spatially co-located weighting coefficients. 11. The method of claim 1, wherein (d) and (e) comprise:
representing the inverted seismic model and the reservoir model each by a series expansion of basis functions and corresponding coefficients in the joint domain; for each basis function, forming a single merged coefficient from two coefficients, which are the coefficient for the inverted seismic model and the coefficient for the geostatistical forward model;
wherein the combined reservoir model is represented by a series expansion of the basis functions with the merged coefficients. 12. The method of claim 11, wherein the processing is a heuristic method using information theory, and each merged coefficient is the coefficient, of the two coefficients, with minimum or maximum entropy. 13. The method of claim 11, wherein the processing is a convex combination with spatially co-located weighting coefficients, and each merged coefficient is determined by convex weighting of the two coefficients with the merged coefficients being normalized. | Method for using a non-stationary, multi-scale domain transformation to combine multiple geophysical data sources, for example seismic data and well log data, into one coherent reservoir model. The seismic data are inverted ( 71 ) to obtain one or more geophysical properties which are converted using petrophysical relationships to a subsurface model of a reservoir property such as porosity or shale volume fraction. The well log data are used to generate a geostatistical forward model ( 72 ) of the reservoir property. Both models of the reservoir property are transformed to a joint space/scale domain, of order >1, where processing is applied ( 73 ) to merge the models into a coherent way into a single model before inverse transforming back to the space domain ( 74 ). The transform is a non-stationary multi-scale transform such as a wavelet, ridgelet, or curvelet transform. The processing may be by, for example, information theory or convex combination.1. A method for integrating well log and seismic data into a single subsurface reservoir model, comprising:
(a) obtaining seismic data and well log data from a subsurface region; (b) inverting the seismic data and applying a petrophysical transformation to generate a subsurface model of a reservoir property; (c) generating a reservoir model of the reservoir property using the well log data; (d) transforming the reservoir property model from inverting seismic data and the reservoir property model from reservoir modeling with well log data, to a joint domain, of order >1; (e) processing the transformed models in the joint domain to coherently combine them into one reservoir model; and (f) inverse transforming to obtain a reservoir model in space domain;
wherein (b)-(f) are performed using a computer. 2. The method of claim 1, wherein the transforming is performed using a non-stationary multi-scale transform. 3. The method of claim 2, wherein the non-stationary multi-scale transform is one of: a wavelet transform; a ridgelet transform; a curvelet transform; and second generation wavelets and lifting schemes. 4. The method of claim 1, wherein the processing is one of a heuristic method using information theory; a convex combination with spatially co-located weighting coefficients; and another processing method. 5. The method of claim 4, wherein the information theory method comprises minimizing or maximizing Shannon's entropy to determine which data source—seismic or well log—within the joint domain to choose at each cell in a discrete computational grid in order to generate a merged data output. 6. The method of claim 4, wherein the convex combination method further comprises:
obtaining a third co-located data source, being weighting fields to be used to indicate how to combine the reservoir model and the model derived from inverted seismic data; transforming the weighting fields to the joint domain; and using the weighting fields to combine the transformed models. 7. The method of claim 1, wherein the joint domain is of order 2, being space and scale;
the transform is a wavelet transform; and the processing is by a heuristic method using information theory. 8. The method of claim 1, wherein the joint domain is of order 2, being space and scale; the transform is a wavelet transform; and the processing uses convex combination with spatially co-located weighting coefficients. 9. The method of claim 1, wherein the joint domain is of order 3, being space, scale and azimuth; the transform is a curvelet transform; and the processing is by a heuristic method using information theory. 10. The method of claim 1, wherein the joint domain is of order 3, being space, scale and azimuth; the transform is a curvelet transform; and the processing uses convex combination with spatially co-located weighting coefficients. 11. The method of claim 1, wherein (d) and (e) comprise:
representing the inverted seismic model and the reservoir model each by a series expansion of basis functions and corresponding coefficients in the joint domain; for each basis function, forming a single merged coefficient from two coefficients, which are the coefficient for the inverted seismic model and the coefficient for the geostatistical forward model;
wherein the combined reservoir model is represented by a series expansion of the basis functions with the merged coefficients. 12. The method of claim 11, wherein the processing is a heuristic method using information theory, and each merged coefficient is the coefficient, of the two coefficients, with minimum or maximum entropy. 13. The method of claim 11, wherein the processing is a convex combination with spatially co-located weighting coefficients, and each merged coefficient is determined by convex weighting of the two coefficients with the merged coefficients being normalized. | 2,800 |
11,476 | 11,476 | 14,436,138 | 2,832 | A stator or rotor for an electric motor or generator comprising a circumferential support having a protrusion; a tooth arranged to receive coil windings, wherein the tooth includes a recess in which is housed the protrusion of the circumferential support, and the protrusion and the recess in the tooth are arranged to have a cavity or channel formed on an adjacent surface of the recess and the protrusion when the protrusion is housed in the recess, wherein a material is placed inside the cavities or channels formed by the adjacent surfaces of the recess and the protrusion for retaining the tooth to the support. | 1. A stator or rotor for an electric motor or generator comprising a circumferential support having a protrusion; a tooth arranged to receive coil windings, wherein the tooth includes a recess in which is housed the protrusion of the circumferential support, wherein the protrusion and the recess in the tooth are arranged to have a cavity or channel formed on an adjacent surface of the recess and the protrusion when the protrusion is housed in the recess, and a material is placed between the cavities or channels formed on the adjacent surfaces of the recess and the protrusion for retaining the tooth to the support. 2. A stator or rotor according to claim 1, wherein the circumferential support includes a plurality of protrusions with each protrusion housed within a recess of a tooth, wherein each protrusion and recess in which it is housed are arranged to have a cavity or channel formed on an adjacent surface of the recess and the protrusion, wherein a material is placed between the cavities or channels formed on the adjacent surfaces of the respective recesses and the protrusions for retaining the plurality of teeth to the support. 3. A stator or rotor according to claim 1, wherein the material is a cured polymer, polyurethane potting material, or silicone potting material. 4. A stator or rotor according to claim 3, wherein the cured polymer is an epoxy resin. 5. A stator or rotor according to claim 1, wherein the cavities or channels formed on the adjacent surfaces of the recess and the protrusion are at substantially the same radial position relative to the circumferential support. 6. A stator or rotor according to claim 1, wherein the protrusion and the recess in which it is housed are arranged to have a cavity or channel formed on first pair of adjacent surfaces of the recess and the protrusion and a second pair of adjacent surfaces of the recess and the protrusion. 7. A stator or rotor according to claim 6, wherein the first pair of adjacent surfaces and the second pair of adjacent surfaces are on opposite sides of the protrusion and the recess. 8. A stator or rotor according to claim 1, wherein the material is arranged to harden after being placed between the cavities or channels formed on the adjacent surfaces of the recess and the protrusion. 9. A stator or rotor according to claim 1, wherein the protrusion extends in a radial direction away from the circumferential support. 10. A stator or rotor according to claim 1, wherein the circumferential support is formed of a series of laminations. 11. A stator or rotor according to claim 1, wherein the tooth is formed of a series of laminations. 12. A stator or rotor according to claim 1, wherein the tooth is over-moulded prior to receiving coil windings. 13. A stator or rotor according to claim 12, wherein the over-moulded layer is an injection moulded plastics layer formed on a plurality of sides of the tooth with a first gap formed in the injection moulded plastics layer on a first side of the tooth with a first insulation element placed in the first gap formed in the injection moulded plastics layer, wherein the injection moulded plastics layer and first insulation element are arranged to electrically insulate the tooth from the coil windings. 14. A stator or rotor or tooth according to claim 13, wherein the first insulation element has a channel formed on a surface of the first insulation elements for allowing the material to be channeled into the tooth recess when the first insulation element is placed in the first gap formed in the injection moulded plastics layer. 15. A stator or rotor according to claim 1, wherein the circumferential support has a recess on at least one side of a protrusion in which a side element of a tooth is mounted within to inhibit tangential movement of the tooth. 16. A stator or rotor according to claim 1, wherein the protrusion and tooth extend from the circumferential support in a radial direction away from the centre point of the circumferential support. 17. A stator or rotor according to claim 1, wherein the protrusion and tooth extend from the circumferential support in a radial direction towards the centre point of the circumferential support. 18. An electric motor comprising:
a stator or rotor comprising a circumferential support having a protrusion; a tooth arranged to receive coil windings, wherein the tooth includes a recess in which is housed the protrusion of the circumferential support, wherein the protrusion and the recess in the tooth are arranged to have a cavity or channel formed on an adjacent surface of the recess and the protrusion when the protrusion is housed in the recess, and a material is placed between the cavities or channels formed on the adjacent surfaces of the recess and the protrusion for retaining the tooth to the support. 19. A method of manufacturing a stator or rotor comprising providing a plurality of teeth, wherein each tooth includes a recess with a cavity or channel formed in a surface of the recess, and a circumferential support having a plurality of protrusions circumferentially distributed about the support, wherein the plurality of protrusions have a cavity or channel formed on a surface of the protrusions; placing coil windings around each of the plurality of teeth and mounting the protrusions formed on the circumferential support into a recess of a respective tooth so that the cavity or channel formed in the surface of the recess and the cavity or channel formed on the surface of the protrusions are on adjacent surfaces; and placing material between the cavities or channels formed on the adjacent surfaces of the recess, wherein the material is arranged to harden after being placed in the cavities or channels formed on the adjacent surfaces, thereby retaining the tooth to the support. | A stator or rotor for an electric motor or generator comprising a circumferential support having a protrusion; a tooth arranged to receive coil windings, wherein the tooth includes a recess in which is housed the protrusion of the circumferential support, and the protrusion and the recess in the tooth are arranged to have a cavity or channel formed on an adjacent surface of the recess and the protrusion when the protrusion is housed in the recess, wherein a material is placed inside the cavities or channels formed by the adjacent surfaces of the recess and the protrusion for retaining the tooth to the support.1. A stator or rotor for an electric motor or generator comprising a circumferential support having a protrusion; a tooth arranged to receive coil windings, wherein the tooth includes a recess in which is housed the protrusion of the circumferential support, wherein the protrusion and the recess in the tooth are arranged to have a cavity or channel formed on an adjacent surface of the recess and the protrusion when the protrusion is housed in the recess, and a material is placed between the cavities or channels formed on the adjacent surfaces of the recess and the protrusion for retaining the tooth to the support. 2. A stator or rotor according to claim 1, wherein the circumferential support includes a plurality of protrusions with each protrusion housed within a recess of a tooth, wherein each protrusion and recess in which it is housed are arranged to have a cavity or channel formed on an adjacent surface of the recess and the protrusion, wherein a material is placed between the cavities or channels formed on the adjacent surfaces of the respective recesses and the protrusions for retaining the plurality of teeth to the support. 3. A stator or rotor according to claim 1, wherein the material is a cured polymer, polyurethane potting material, or silicone potting material. 4. A stator or rotor according to claim 3, wherein the cured polymer is an epoxy resin. 5. A stator or rotor according to claim 1, wherein the cavities or channels formed on the adjacent surfaces of the recess and the protrusion are at substantially the same radial position relative to the circumferential support. 6. A stator or rotor according to claim 1, wherein the protrusion and the recess in which it is housed are arranged to have a cavity or channel formed on first pair of adjacent surfaces of the recess and the protrusion and a second pair of adjacent surfaces of the recess and the protrusion. 7. A stator or rotor according to claim 6, wherein the first pair of adjacent surfaces and the second pair of adjacent surfaces are on opposite sides of the protrusion and the recess. 8. A stator or rotor according to claim 1, wherein the material is arranged to harden after being placed between the cavities or channels formed on the adjacent surfaces of the recess and the protrusion. 9. A stator or rotor according to claim 1, wherein the protrusion extends in a radial direction away from the circumferential support. 10. A stator or rotor according to claim 1, wherein the circumferential support is formed of a series of laminations. 11. A stator or rotor according to claim 1, wherein the tooth is formed of a series of laminations. 12. A stator or rotor according to claim 1, wherein the tooth is over-moulded prior to receiving coil windings. 13. A stator or rotor according to claim 12, wherein the over-moulded layer is an injection moulded plastics layer formed on a plurality of sides of the tooth with a first gap formed in the injection moulded plastics layer on a first side of the tooth with a first insulation element placed in the first gap formed in the injection moulded plastics layer, wherein the injection moulded plastics layer and first insulation element are arranged to electrically insulate the tooth from the coil windings. 14. A stator or rotor or tooth according to claim 13, wherein the first insulation element has a channel formed on a surface of the first insulation elements for allowing the material to be channeled into the tooth recess when the first insulation element is placed in the first gap formed in the injection moulded plastics layer. 15. A stator or rotor according to claim 1, wherein the circumferential support has a recess on at least one side of a protrusion in which a side element of a tooth is mounted within to inhibit tangential movement of the tooth. 16. A stator or rotor according to claim 1, wherein the protrusion and tooth extend from the circumferential support in a radial direction away from the centre point of the circumferential support. 17. A stator or rotor according to claim 1, wherein the protrusion and tooth extend from the circumferential support in a radial direction towards the centre point of the circumferential support. 18. An electric motor comprising:
a stator or rotor comprising a circumferential support having a protrusion; a tooth arranged to receive coil windings, wherein the tooth includes a recess in which is housed the protrusion of the circumferential support, wherein the protrusion and the recess in the tooth are arranged to have a cavity or channel formed on an adjacent surface of the recess and the protrusion when the protrusion is housed in the recess, and a material is placed between the cavities or channels formed on the adjacent surfaces of the recess and the protrusion for retaining the tooth to the support. 19. A method of manufacturing a stator or rotor comprising providing a plurality of teeth, wherein each tooth includes a recess with a cavity or channel formed in a surface of the recess, and a circumferential support having a plurality of protrusions circumferentially distributed about the support, wherein the plurality of protrusions have a cavity or channel formed on a surface of the protrusions; placing coil windings around each of the plurality of teeth and mounting the protrusions formed on the circumferential support into a recess of a respective tooth so that the cavity or channel formed in the surface of the recess and the cavity or channel formed on the surface of the protrusions are on adjacent surfaces; and placing material between the cavities or channels formed on the adjacent surfaces of the recess, wherein the material is arranged to harden after being placed in the cavities or channels formed on the adjacent surfaces, thereby retaining the tooth to the support. | 2,800 |
11,477 | 11,477 | 14,507,928 | 2,834 | A generator comprises a rotor to be driven for rotation adjacent a stator. The stator includes laminated core teeth having circumferentially intermediate slots and a conductor received within the slots. The conductor has an outer copper layer and an inner aluminum core. A stator is also disclosed. | 1. A generator comprising:
a rotor to be driven for rotation adjacent a stator; and said stator including laminated core having circumferentially intermediate slots, and a conductor received within said slots, said conductor having an outer copper layer and an inner aluminum core. 2. The generator as set forth in claim 1, wherein said conductor has a generally oval shape with longer sides and shorter sides. 3. The generator as set forth in claim 2, wherein there are a pair of conductors in each of said slots. 4. The generator as set forth in claim 3, wherein slot insulators surround said conductors within said slots. 5. The generator as set forth in claim 4, wherein said outer copper layer extends inwardly for a skin depth which is determined, at least in part, based upon a calculation of the skin depth. 6. The generator as set forth in claim 5, wherein the skin depth is defined by the following formula.
δ
=
2
ρ
ωμ
r
ω
0
where
p=resistivity of the conductor
ω=angular frequency of current=2π×frequency
μr=relative magnetic permeability of the conductor
μ0=the permeability of free space 7. The generator as set forth in claim 6, wherein the frequency of the generator is 300-800 hz. 8. The generator as set forth in claim 1, wherein there are a pair of conductors in each of said slots. 9. The generator as set forth in claim 3, wherein slot insulators surround said conductors within said slots. 10. The generator as set forth in claim 4, wherein said outer copper layer extends inwardly for a skin depth which is determined, at least in part, based upon a calculation of the skin depth. 11. The generator as set forth in claim 10, wherein the skin depth is defined by the following formula.
δ
=
2
ρ
ωμ
r
ω
0
where
p=resistivity of the conductor
ω=angular frequency of current=2π×frequency
μr=relative magnetic permeability of the conductor
μ0=the permeability of free space 12. The generator as set forth in claim 11, wherein the frequency of the generator is 300-800 Hz. 13. The generator as set forth in claim 1, wherein said outer copper layer extends inwardly for a skin depth which is determined, at least in part, based upon a calculation of the skin depth. 14. The generator as set forth in claim 13, wherein the skin depth is defined by the following formula.
δ
=
2
ρ
ωμ
r
ω
0
where
p=resistivity of the conductor
ω=angular frequency of current=2π×frequency
μr=relative magnetic permeability of the conductor
μ0=the permeability of free space 15. The generator as set forth in claim 1, wherein the frequency of the generator is 300-800 Hz. | A generator comprises a rotor to be driven for rotation adjacent a stator. The stator includes laminated core teeth having circumferentially intermediate slots and a conductor received within the slots. The conductor has an outer copper layer and an inner aluminum core. A stator is also disclosed.1. A generator comprising:
a rotor to be driven for rotation adjacent a stator; and said stator including laminated core having circumferentially intermediate slots, and a conductor received within said slots, said conductor having an outer copper layer and an inner aluminum core. 2. The generator as set forth in claim 1, wherein said conductor has a generally oval shape with longer sides and shorter sides. 3. The generator as set forth in claim 2, wherein there are a pair of conductors in each of said slots. 4. The generator as set forth in claim 3, wherein slot insulators surround said conductors within said slots. 5. The generator as set forth in claim 4, wherein said outer copper layer extends inwardly for a skin depth which is determined, at least in part, based upon a calculation of the skin depth. 6. The generator as set forth in claim 5, wherein the skin depth is defined by the following formula.
δ
=
2
ρ
ωμ
r
ω
0
where
p=resistivity of the conductor
ω=angular frequency of current=2π×frequency
μr=relative magnetic permeability of the conductor
μ0=the permeability of free space 7. The generator as set forth in claim 6, wherein the frequency of the generator is 300-800 hz. 8. The generator as set forth in claim 1, wherein there are a pair of conductors in each of said slots. 9. The generator as set forth in claim 3, wherein slot insulators surround said conductors within said slots. 10. The generator as set forth in claim 4, wherein said outer copper layer extends inwardly for a skin depth which is determined, at least in part, based upon a calculation of the skin depth. 11. The generator as set forth in claim 10, wherein the skin depth is defined by the following formula.
δ
=
2
ρ
ωμ
r
ω
0
where
p=resistivity of the conductor
ω=angular frequency of current=2π×frequency
μr=relative magnetic permeability of the conductor
μ0=the permeability of free space 12. The generator as set forth in claim 11, wherein the frequency of the generator is 300-800 Hz. 13. The generator as set forth in claim 1, wherein said outer copper layer extends inwardly for a skin depth which is determined, at least in part, based upon a calculation of the skin depth. 14. The generator as set forth in claim 13, wherein the skin depth is defined by the following formula.
δ
=
2
ρ
ωμ
r
ω
0
where
p=resistivity of the conductor
ω=angular frequency of current=2π×frequency
μr=relative magnetic permeability of the conductor
μ0=the permeability of free space 15. The generator as set forth in claim 1, wherein the frequency of the generator is 300-800 Hz. | 2,800 |
11,478 | 11,478 | 15,288,259 | 2,831 | An apparatus and method for crosstalk compensation in a jack of a modular communications connector includes connected to the plug interface contacts proximate the plug/jack interface. The structure configured to allow the current to flow generally orthogonal to the plug interface contact. | 1. A communication jack configured to receive a plug to form a communication connection, comprising:
a plurality of jack contacts, the plurality of jack contacts at least partially disposed within a plug receiving cavity in the jack; a structure attached to at least one of the plurality of jack contacts, the structure connected to the at least one jack contact such as to allow the current to flow generally orthogonal the jack contact, 2. The communication jack of claim 1 wherein the structure is attached to the at least one contact proximate to the plug/jack interface. 3. The communication jack of claim 2 wherein the structure is a flexible printed circuit board connected to the jack contact. 4. The communication jack of claim 2 wherein the structure is a plug interface contact (PIC) cover. | An apparatus and method for crosstalk compensation in a jack of a modular communications connector includes connected to the plug interface contacts proximate the plug/jack interface. The structure configured to allow the current to flow generally orthogonal to the plug interface contact.1. A communication jack configured to receive a plug to form a communication connection, comprising:
a plurality of jack contacts, the plurality of jack contacts at least partially disposed within a plug receiving cavity in the jack; a structure attached to at least one of the plurality of jack contacts, the structure connected to the at least one jack contact such as to allow the current to flow generally orthogonal the jack contact, 2. The communication jack of claim 1 wherein the structure is attached to the at least one contact proximate to the plug/jack interface. 3. The communication jack of claim 2 wherein the structure is a flexible printed circuit board connected to the jack contact. 4. The communication jack of claim 2 wherein the structure is a plug interface contact (PIC) cover. | 2,800 |
11,479 | 11,479 | 14,649,499 | 2,853 | A method for determining a cylinder pressure-crankshaft position association for an internal combustion engine, including metrological detection of the crankshaft angle; metrological detection of the cylinder pressure; calculation of a cylinder volume as a function of the crankshaft angle; determination of a curve for the logarithmic cylinder pressure over the logarithmic cylinder volume as a function of the crankshaft angle; analysis of the curve, and determination of an offset value for the crankshaft angle for determining a temporally exact cylinder pressure-crankshaft position association. | 1.-8. (canceled) 9. A method for determining a cylinder pressure-crankshaft position association for an internal combustion engine, comprising:
metrological detection of a crankshaft angle; metrological detection of a cylinder pressure; calculating of a cylinder volume based at least in part on the crankshaft angle; determining of a curve for a logarithmic cylinder pressure over a logarithmic cylinder volume based at least in part on the crankshaft angle; analyzing the curve; determining of an offset value for the crankshaft angle for determining a temporal cylinder pressure-crankshaft position association; concluding that a cylinder pressure signal is retarded in relation to a crankshaft angle signal when an intersection of curve segments of the curve is determined in a region of a cylinder reversal point; and determining an offset value for compensating displacement is determined as a function of a surface area between the curve segments of the curve in the region of the cylinder reversal point. 10. The method according to claim 9, wherein the determination of the cylinder pressure-crankshaft position association for the internal combustion engine is carried out automatically in fired operation of the internal combustion engine. 11. The method according to claim 9, wherein the determination of the cylinder pressure-crankshaft position association for the internal combustion engine is carried out automatically in towed operation of the internal combustion engine. 12. The method according to claim 9, further comprising analyzing the curve in the region of the cylinder reversal point to determine the offset value. 13. The method according to claim 12, wherein the curve in the region of a bottom cylinder reversal point is analyzed to determine the offset value. 14. The method according to claim 12, wherein the curve in the region of a top cylinder reversal point is analyzed to determine the offset value. 15. The method according to claim 12, further comprising:
concluding that a cylinder pressure signal is premature in relation to the crankshaft angle signal when a non-intersection of curve segments of the curve is determined in the region of the cylinder reversal point; and determining an offset value for compensating displacement as a function of the surface area between the curve segments of the curve in the region of the cylinder reversal point. | A method for determining a cylinder pressure-crankshaft position association for an internal combustion engine, including metrological detection of the crankshaft angle; metrological detection of the cylinder pressure; calculation of a cylinder volume as a function of the crankshaft angle; determination of a curve for the logarithmic cylinder pressure over the logarithmic cylinder volume as a function of the crankshaft angle; analysis of the curve, and determination of an offset value for the crankshaft angle for determining a temporally exact cylinder pressure-crankshaft position association.1.-8. (canceled) 9. A method for determining a cylinder pressure-crankshaft position association for an internal combustion engine, comprising:
metrological detection of a crankshaft angle; metrological detection of a cylinder pressure; calculating of a cylinder volume based at least in part on the crankshaft angle; determining of a curve for a logarithmic cylinder pressure over a logarithmic cylinder volume based at least in part on the crankshaft angle; analyzing the curve; determining of an offset value for the crankshaft angle for determining a temporal cylinder pressure-crankshaft position association; concluding that a cylinder pressure signal is retarded in relation to a crankshaft angle signal when an intersection of curve segments of the curve is determined in a region of a cylinder reversal point; and determining an offset value for compensating displacement is determined as a function of a surface area between the curve segments of the curve in the region of the cylinder reversal point. 10. The method according to claim 9, wherein the determination of the cylinder pressure-crankshaft position association for the internal combustion engine is carried out automatically in fired operation of the internal combustion engine. 11. The method according to claim 9, wherein the determination of the cylinder pressure-crankshaft position association for the internal combustion engine is carried out automatically in towed operation of the internal combustion engine. 12. The method according to claim 9, further comprising analyzing the curve in the region of the cylinder reversal point to determine the offset value. 13. The method according to claim 12, wherein the curve in the region of a bottom cylinder reversal point is analyzed to determine the offset value. 14. The method according to claim 12, wherein the curve in the region of a top cylinder reversal point is analyzed to determine the offset value. 15. The method according to claim 12, further comprising:
concluding that a cylinder pressure signal is premature in relation to the crankshaft angle signal when a non-intersection of curve segments of the curve is determined in the region of the cylinder reversal point; and determining an offset value for compensating displacement as a function of the surface area between the curve segments of the curve in the region of the cylinder reversal point. | 2,800 |
11,480 | 11,480 | 14,945,201 | 2,831 | Embodiments described herein automatically detect a power state of an electronic device and perform a control scheme based thereon. For example, a control device determines that an electronic device is to be in a desired power state. A socket device coupled to the electronic device determines an amount of current or power being provided to the electronic device and transmits an indication of the amount of current or power or a determined power state to the control device. Based on the indication, the control device determines the current power state of the electronic device. If the control device determines that the current power state is not the desired power state, the control device transmits a signal to the electronic device, which causes it to transition to the desired power state. | 1. A socket device, comprising:
a first receptacle configured to receive a first prong of an electrical plug and couple the first prong to a first conductive element of the socket device; a second receptacle configured to receive a second prong of the electrical plug and couple the second prong to a second conductive element of the socket device; a sensing component configured to determine an amount of current provided via at least one of the first conductive element and the second conductive element; and a transmit component configured to transmit an indication of the amount of current to a control device. 2. The socket device of claim 1, further comprising:
a first prong configured to be inserted into a first receptacle of a power socket; and a second prong configured to be inserted into a second receptacle of the power socket. 3. The socket device of claim 1, wherein the transmit component comprises an antenna configured to wirelessly provide the indication to the control device. 4. The socket device of claim 1, wherein the sensing component comprises:
a resistive element coupled to at least one of the first conductive element and the second conductive element, wherein the sensing component is configured to determine an amount of voltage across at least one of the first conductive element and the second conductive element and determine the amount of current based on the determined voltage. 5. The socket device of claim 1, wherein the sensing component comprises at least one of:
a current transformer coupled to at least one of the first conductive element and the second conductive element and configured to measure the amount of current provided via at least one of the first conductive element and the second conductive element; and a Hall effect current sensor coupled to at least one of the first conductive element and the second conductive element and configured to measure the amount of current provided via at least one of the first conductive element and the second conductive element. 6. The socket device of claim 1, wherein the socket device is integrated into an audio-video receiver. 7. A system, comprising:
a socket device configured to determine an amount of current being provided to a first electronic device attached thereto and transmit an indication of the amount of current; and a control device configured to:
receive the indication of the amount of current from the socket device;
determine that the first electronic device is to be in a first power state;
determine whether the first electronic device is in one of the first power state or a second power state based on the indication; and
in response to a determination that the first electronic device is in the second power state, transmit a signal to the first electronic device that causes the first electronic device to transition to the first power state. 8. The system of claim 7, wherein the first power state is a power-on state, and wherein the second power state is at least one of a low-power state or a power-off state. 9. The system of claim 7, wherein the first power state is at least one of a low-power state or a power-off state, and wherein the second power state is a power-on state. 10. The system of claim 7, wherein the control device is configured to determine that the first electronic device is to be in the first power state by:
detecting a triggering event indicative of a user performing an action intended to cause the first electronic device to transition to the first power state. 11. The system of claim 10, wherein the action comprises the user interacting with an interface element of a remote control device that, when activated, is intended to cause the first electronic device to be in the first power state. 12. The system of claim 10, wherein the socket device is configured to transmit the indication of the amount of current and the control device is configured to receive the indication of the amount of current wirelessly. 13. A method for controlling a first electronic device, comprising:
receiving an indication of an amount of current being provided to the first electronic device from a socket device attached to the first electronic device; determining that the first electronic device is to be in a first power state; determining whether the first electronic device is in one of the first power state or a second power state based on the indication; and in response to determining that the first electronic device is in the second power state, transmitting a control signal to the first electronic device that causes the first electronic device to transition to the first power state. 14. The method of claim 13, wherein the first power state is a power-on state, and wherein the second power state is at least one of a low-power state or a power-off state. 15. The method of claim 13, wherein the first power state is at least one of a low-power state or a power-off state, and wherein the second power state is a power-on state. 16. The method of claim 13, wherein determining that the first electronic device is to be in the first power state comprises:
detecting a triggering event indicative of a user performing an action intended to cause the first electronic device to transition to the first power state. 17. The method of claim 16, wherein the action comprises the user interacting with an interface element of a remote control device that, when activated, is intended to cause the first electronic device to be in the first power state. 18. The method of claim 13, wherein determining that the first electronic device is to be in the first power state comprises:
detecting a triggering event that indicates that another electronic device has transitioned to a particular power state. 19. The method of claim 13, wherein receiving the indication of the amount of current being provided to the first electronic device from the socket device attached to the first electronic device comprises:
wirelessly receiving the indication of the amount of current being provided to the first electronic device from the socket device attached to the first electronic device. 20. A socket device, comprising:
a sensing component configured to determine an amount of power being provided to the socket device from an electronic device attached to the socket device; a processing component configured to determine a power state of the electronic device based on the determined amount of power; and a transmit component configured to provide an indication indicating the determined power state to a control device. | Embodiments described herein automatically detect a power state of an electronic device and perform a control scheme based thereon. For example, a control device determines that an electronic device is to be in a desired power state. A socket device coupled to the electronic device determines an amount of current or power being provided to the electronic device and transmits an indication of the amount of current or power or a determined power state to the control device. Based on the indication, the control device determines the current power state of the electronic device. If the control device determines that the current power state is not the desired power state, the control device transmits a signal to the electronic device, which causes it to transition to the desired power state.1. A socket device, comprising:
a first receptacle configured to receive a first prong of an electrical plug and couple the first prong to a first conductive element of the socket device; a second receptacle configured to receive a second prong of the electrical plug and couple the second prong to a second conductive element of the socket device; a sensing component configured to determine an amount of current provided via at least one of the first conductive element and the second conductive element; and a transmit component configured to transmit an indication of the amount of current to a control device. 2. The socket device of claim 1, further comprising:
a first prong configured to be inserted into a first receptacle of a power socket; and a second prong configured to be inserted into a second receptacle of the power socket. 3. The socket device of claim 1, wherein the transmit component comprises an antenna configured to wirelessly provide the indication to the control device. 4. The socket device of claim 1, wherein the sensing component comprises:
a resistive element coupled to at least one of the first conductive element and the second conductive element, wherein the sensing component is configured to determine an amount of voltage across at least one of the first conductive element and the second conductive element and determine the amount of current based on the determined voltage. 5. The socket device of claim 1, wherein the sensing component comprises at least one of:
a current transformer coupled to at least one of the first conductive element and the second conductive element and configured to measure the amount of current provided via at least one of the first conductive element and the second conductive element; and a Hall effect current sensor coupled to at least one of the first conductive element and the second conductive element and configured to measure the amount of current provided via at least one of the first conductive element and the second conductive element. 6. The socket device of claim 1, wherein the socket device is integrated into an audio-video receiver. 7. A system, comprising:
a socket device configured to determine an amount of current being provided to a first electronic device attached thereto and transmit an indication of the amount of current; and a control device configured to:
receive the indication of the amount of current from the socket device;
determine that the first electronic device is to be in a first power state;
determine whether the first electronic device is in one of the first power state or a second power state based on the indication; and
in response to a determination that the first electronic device is in the second power state, transmit a signal to the first electronic device that causes the first electronic device to transition to the first power state. 8. The system of claim 7, wherein the first power state is a power-on state, and wherein the second power state is at least one of a low-power state or a power-off state. 9. The system of claim 7, wherein the first power state is at least one of a low-power state or a power-off state, and wherein the second power state is a power-on state. 10. The system of claim 7, wherein the control device is configured to determine that the first electronic device is to be in the first power state by:
detecting a triggering event indicative of a user performing an action intended to cause the first electronic device to transition to the first power state. 11. The system of claim 10, wherein the action comprises the user interacting with an interface element of a remote control device that, when activated, is intended to cause the first electronic device to be in the first power state. 12. The system of claim 10, wherein the socket device is configured to transmit the indication of the amount of current and the control device is configured to receive the indication of the amount of current wirelessly. 13. A method for controlling a first electronic device, comprising:
receiving an indication of an amount of current being provided to the first electronic device from a socket device attached to the first electronic device; determining that the first electronic device is to be in a first power state; determining whether the first electronic device is in one of the first power state or a second power state based on the indication; and in response to determining that the first electronic device is in the second power state, transmitting a control signal to the first electronic device that causes the first electronic device to transition to the first power state. 14. The method of claim 13, wherein the first power state is a power-on state, and wherein the second power state is at least one of a low-power state or a power-off state. 15. The method of claim 13, wherein the first power state is at least one of a low-power state or a power-off state, and wherein the second power state is a power-on state. 16. The method of claim 13, wherein determining that the first electronic device is to be in the first power state comprises:
detecting a triggering event indicative of a user performing an action intended to cause the first electronic device to transition to the first power state. 17. The method of claim 16, wherein the action comprises the user interacting with an interface element of a remote control device that, when activated, is intended to cause the first electronic device to be in the first power state. 18. The method of claim 13, wherein determining that the first electronic device is to be in the first power state comprises:
detecting a triggering event that indicates that another electronic device has transitioned to a particular power state. 19. The method of claim 13, wherein receiving the indication of the amount of current being provided to the first electronic device from the socket device attached to the first electronic device comprises:
wirelessly receiving the indication of the amount of current being provided to the first electronic device from the socket device attached to the first electronic device. 20. A socket device, comprising:
a sensing component configured to determine an amount of power being provided to the socket device from an electronic device attached to the socket device; a processing component configured to determine a power state of the electronic device based on the determined amount of power; and a transmit component configured to provide an indication indicating the determined power state to a control device. | 2,800 |
11,481 | 11,481 | 15,189,067 | 2,894 | A method of manufacturing a silicon wafer includes extracting an n-type silicon ingot over an extraction time period from a silicon melt comprising n-type dopants, adding p-type dopants to the silicon melt over at least part of the extraction time period, so as to compensate an n-type doping in the n-type silicon ingot by 20% to 80%, and slicing the silicon ingot. | 1. A method of manufacturing a silicon wafer, the method comprising:
extracting an n-type silicon ingot over an extraction time period from a silicon melt comprising n-type dopants; adding p-type dopants to the silicon melt over at least part of the extraction time period, so as to compensate an n-type doping in the n-type silicon ingot by 20% to 80%; and slicing the silicon ingot. 2. The method of claim 1, wherein a segregation coefficient of an n-type dopant species of the n-type dopants and a segregation coefficient of a p-type dopant species of the p-type dopants differ by at least a factor of three. 3. The method of claim 2, wherein the n-type dopant species is phosphorus and the p-type dopant species is boron. 4. The method of claim 3, further comprising:
adding, in addition to boron, a second p-type dopant species to the silicon melt over at least part of the extraction time period, the second p-type dopant species having a segregation coefficient smaller than phosphorus. 5. The method of claim 4, wherein the second p-type dopant species corresponds to at least one of aluminum and gallium. 6. The method of claim 3, wherein the boron is added to the silicon melt from at least one of a boron doped quartz material or from boron in a gas phase. 7. The method of claim 3, wherein the boron is added to the silicon melt from a boron carbide or a boron nitride source material. 8. The method of claim 3, wherein the boron is added to the silicon melt from a boron doped crucible. 9. The method of claim 8, wherein the boron doped crucible is formed by at least one of implanting boron into the crucible, diffusion of boron into the crucible and in-situ doping. 10. The method of claim 9, wherein the boron is implanted into the crucible at various energies and doses. 11. The method of claim 8, further comprising:
applying a thermal budget to the boron doped crucible by heating that is configured to set a retrograde profile of the boron in the crucible. 12. The method of claim 8, further comprising:
forming a layer at inner walls of the boron doped crucible. 13. The method of claim 3, further comprising:
altering a rate of adding the boron to the silicon melt. 14. The method of claim 13, wherein altering the rate of adding the boron to the silicon melt includes altering at least one of size, geometry and rate of delivery of particles, a flow or partial pressure of a boron carrier gas. 15. The method of claim 13, wherein altering the rate of adding the boron to the silicon melt includes at least one of altering a depth of a source material dipped into the silicon melt and altering a temperature of the source material, wherein the source material is doped with the boron. 16. The method of claim 15, wherein doping of the source material is carried out by one of in-situ doping, by a plasma deposition process through a surface of the source material, by ion implantation through the surface of the source material and by a diffusion process through the surface of the source material. 17. The method of claim 13, further comprising:
controlling a rate of adding the boron to the silicon melt by measuring a weight of the silicon ingot during the Czochralski growth process. 18. The method of claim 13, further comprising:
controlling a rate of adding the boron to the silicon melt by optically measuring a change in dimensions of a quartz source material doped with the boron. 19. The method of claim 13, further comprising:
altering a rate of adding the boron to the silicon melt by altering at least one of a contact area between a source material and the silicon melt and heating of the source material. 20. The method of claim 1, wherein adding the p-type dopants into the silicon melt includes dissolving p-type dopants from a p-type dopant source material into the silicon melt. | A method of manufacturing a silicon wafer includes extracting an n-type silicon ingot over an extraction time period from a silicon melt comprising n-type dopants, adding p-type dopants to the silicon melt over at least part of the extraction time period, so as to compensate an n-type doping in the n-type silicon ingot by 20% to 80%, and slicing the silicon ingot.1. A method of manufacturing a silicon wafer, the method comprising:
extracting an n-type silicon ingot over an extraction time period from a silicon melt comprising n-type dopants; adding p-type dopants to the silicon melt over at least part of the extraction time period, so as to compensate an n-type doping in the n-type silicon ingot by 20% to 80%; and slicing the silicon ingot. 2. The method of claim 1, wherein a segregation coefficient of an n-type dopant species of the n-type dopants and a segregation coefficient of a p-type dopant species of the p-type dopants differ by at least a factor of three. 3. The method of claim 2, wherein the n-type dopant species is phosphorus and the p-type dopant species is boron. 4. The method of claim 3, further comprising:
adding, in addition to boron, a second p-type dopant species to the silicon melt over at least part of the extraction time period, the second p-type dopant species having a segregation coefficient smaller than phosphorus. 5. The method of claim 4, wherein the second p-type dopant species corresponds to at least one of aluminum and gallium. 6. The method of claim 3, wherein the boron is added to the silicon melt from at least one of a boron doped quartz material or from boron in a gas phase. 7. The method of claim 3, wherein the boron is added to the silicon melt from a boron carbide or a boron nitride source material. 8. The method of claim 3, wherein the boron is added to the silicon melt from a boron doped crucible. 9. The method of claim 8, wherein the boron doped crucible is formed by at least one of implanting boron into the crucible, diffusion of boron into the crucible and in-situ doping. 10. The method of claim 9, wherein the boron is implanted into the crucible at various energies and doses. 11. The method of claim 8, further comprising:
applying a thermal budget to the boron doped crucible by heating that is configured to set a retrograde profile of the boron in the crucible. 12. The method of claim 8, further comprising:
forming a layer at inner walls of the boron doped crucible. 13. The method of claim 3, further comprising:
altering a rate of adding the boron to the silicon melt. 14. The method of claim 13, wherein altering the rate of adding the boron to the silicon melt includes altering at least one of size, geometry and rate of delivery of particles, a flow or partial pressure of a boron carrier gas. 15. The method of claim 13, wherein altering the rate of adding the boron to the silicon melt includes at least one of altering a depth of a source material dipped into the silicon melt and altering a temperature of the source material, wherein the source material is doped with the boron. 16. The method of claim 15, wherein doping of the source material is carried out by one of in-situ doping, by a plasma deposition process through a surface of the source material, by ion implantation through the surface of the source material and by a diffusion process through the surface of the source material. 17. The method of claim 13, further comprising:
controlling a rate of adding the boron to the silicon melt by measuring a weight of the silicon ingot during the Czochralski growth process. 18. The method of claim 13, further comprising:
controlling a rate of adding the boron to the silicon melt by optically measuring a change in dimensions of a quartz source material doped with the boron. 19. The method of claim 13, further comprising:
altering a rate of adding the boron to the silicon melt by altering at least one of a contact area between a source material and the silicon melt and heating of the source material. 20. The method of claim 1, wherein adding the p-type dopants into the silicon melt includes dissolving p-type dopants from a p-type dopant source material into the silicon melt. | 2,800 |
11,482 | 11,482 | 15,437,714 | 2,846 | A powertrain for a vehicle includes an electric machine coupled with a first inverter, a traction battery and a second inverter. The traction battery is coupled between a neutral terminal of the electric machine and a negative terminal of the first inverter. The second inverter is coupled in parallel with the first inverter with respect to a direct current (DC) bus, and configured to drive a second electric machine. | 1. A powertrain for a vehicle comprising:
an electric machine coupled with a first inverter; a traction battery coupled between a neutral terminal of the electric machine and a negative terminal of the first inverter to provide power to the electric machine during electric propulsion of the vehicle; and a second inverter coupled in parallel with the first inverter with respect to a direct current (DC) bus, and configured to drive a second electric machine. 2. The powertrain of claim 1 further comprising a bus capacitor that is coupled between the negative terminal and positive terminal of the first inverter. 3. The powertrain of claim 1, wherein the electric machine is a 3-phase wye wound electric machine in which the first inverter is configured to flow a DC battery current equally through each phase of the electric machine. 4. (canceled) 5. The powertrain of claim 4, wherein the first inverter is configured to flow a DC battery current equally through each phase of the electric machine. 6. The powertrain of claim 4, wherein the first inverter is configured to flow a DC battery current through 3 phases of the electric machine in which each of the 3 phases are separated from the other two phases by 120 degrees. 7. (canceled) 8. The powertrain of claim 7, wherein the first inverter is configured to flow a DC battery current equally through each phase of the electric machine. 9. The powertrain of claim 7, wherein the first inverter is configured to flow a DC battery current through 3 phases of the electric machine in which each of the 3 phases are separated from the other two phases by 120 degrees. 10. The powertrain of claim 1, wherein the electric machine is a multi-phase wye wound electric machine and the first inverter is configured to flow a DC battery current equally through each phase of the electric machine. 11. A method of controlling a powertrain comprising:
by a controller,
modulating switches of a first inverter to generate phase signals for a wye wound electric machine; and
offsetting the phase signals by a direct current (DC) bias applied to less than all phases of the electric machine such that a rotational torque of the electric machine associated with the DC bias is zero. 12. The method of claim 11, wherein the DC bias is applied by a traction battery coupled between a neutral terminal of the electric machine and a negative terminal of the first inverter. 13. The method of claim 12 further comprising modulating signals of a second inverter, coupled in parallel with the first inverter, to drive a second electric machine with power from the traction battery. 14. The method of claim 11, wherein the electric machine is a 3-phase wye wound electric machine and the first inverter modulates the switches to flow a DC battery current equally through each phase of the electric machine. 15. A powertrain for a vehicle comprising:
a wye wound electric machine coupled between a first inverter and a traction battery, wherein the traction battery is coupled between a neutral terminal of the electric machine and a negative terminal of the first inverter to provide power to the wye wound electric machine during electric propulsion of the vehicle; and a second electric machine coupled with a second inverter that is coupled in parallel with the first inverter with respect to a direct current (DC) bus. 16. The powertrain of claim 15, wherein the electric machine is a 3-phase wye wound electric machine in which the first inverter is configured to flow a DC battery current equally through each phase of the electric machine. 17. (canceled) 18. The powertrain of claim 17, wherein the first inverter is configured to flow a DC battery current equally through each phase of the electric machine. 19. The powertrain of claim 17, wherein the first inverter is configured to flow a DC battery current through 3 phases of the electric machine in which each of the 3 phases are separated from the other two phases by 120 degrees. 20. The powertrain of claim 15 further comprising a bus capacitor that is coupled between the negative terminal and positive terminal of the first inverter. | A powertrain for a vehicle includes an electric machine coupled with a first inverter, a traction battery and a second inverter. The traction battery is coupled between a neutral terminal of the electric machine and a negative terminal of the first inverter. The second inverter is coupled in parallel with the first inverter with respect to a direct current (DC) bus, and configured to drive a second electric machine.1. A powertrain for a vehicle comprising:
an electric machine coupled with a first inverter; a traction battery coupled between a neutral terminal of the electric machine and a negative terminal of the first inverter to provide power to the electric machine during electric propulsion of the vehicle; and a second inverter coupled in parallel with the first inverter with respect to a direct current (DC) bus, and configured to drive a second electric machine. 2. The powertrain of claim 1 further comprising a bus capacitor that is coupled between the negative terminal and positive terminal of the first inverter. 3. The powertrain of claim 1, wherein the electric machine is a 3-phase wye wound electric machine in which the first inverter is configured to flow a DC battery current equally through each phase of the electric machine. 4. (canceled) 5. The powertrain of claim 4, wherein the first inverter is configured to flow a DC battery current equally through each phase of the electric machine. 6. The powertrain of claim 4, wherein the first inverter is configured to flow a DC battery current through 3 phases of the electric machine in which each of the 3 phases are separated from the other two phases by 120 degrees. 7. (canceled) 8. The powertrain of claim 7, wherein the first inverter is configured to flow a DC battery current equally through each phase of the electric machine. 9. The powertrain of claim 7, wherein the first inverter is configured to flow a DC battery current through 3 phases of the electric machine in which each of the 3 phases are separated from the other two phases by 120 degrees. 10. The powertrain of claim 1, wherein the electric machine is a multi-phase wye wound electric machine and the first inverter is configured to flow a DC battery current equally through each phase of the electric machine. 11. A method of controlling a powertrain comprising:
by a controller,
modulating switches of a first inverter to generate phase signals for a wye wound electric machine; and
offsetting the phase signals by a direct current (DC) bias applied to less than all phases of the electric machine such that a rotational torque of the electric machine associated with the DC bias is zero. 12. The method of claim 11, wherein the DC bias is applied by a traction battery coupled between a neutral terminal of the electric machine and a negative terminal of the first inverter. 13. The method of claim 12 further comprising modulating signals of a second inverter, coupled in parallel with the first inverter, to drive a second electric machine with power from the traction battery. 14. The method of claim 11, wherein the electric machine is a 3-phase wye wound electric machine and the first inverter modulates the switches to flow a DC battery current equally through each phase of the electric machine. 15. A powertrain for a vehicle comprising:
a wye wound electric machine coupled between a first inverter and a traction battery, wherein the traction battery is coupled between a neutral terminal of the electric machine and a negative terminal of the first inverter to provide power to the wye wound electric machine during electric propulsion of the vehicle; and a second electric machine coupled with a second inverter that is coupled in parallel with the first inverter with respect to a direct current (DC) bus. 16. The powertrain of claim 15, wherein the electric machine is a 3-phase wye wound electric machine in which the first inverter is configured to flow a DC battery current equally through each phase of the electric machine. 17. (canceled) 18. The powertrain of claim 17, wherein the first inverter is configured to flow a DC battery current equally through each phase of the electric machine. 19. The powertrain of claim 17, wherein the first inverter is configured to flow a DC battery current through 3 phases of the electric machine in which each of the 3 phases are separated from the other two phases by 120 degrees. 20. The powertrain of claim 15 further comprising a bus capacitor that is coupled between the negative terminal and positive terminal of the first inverter. | 2,800 |
11,483 | 11,483 | 14,893,456 | 2,834 | An electric machine has rotor rotatably supported in bearings for rotation about an axis of rotation, a stator surrounding the rotor with respect to the axis of rotation and having stator sheets, which are stacked in the direction of the axis of rotation. The stator sheets have a number of recesses which form grooves extending parallel to the axis of rotation. Tension strips are arranged in the grooves and connected to end rings. The stator sheets include at least first stator sheets. The first stator sheets each have at least one large lug. Between the two tension strips adjacent to the respective large lug in a circumferential direction about the axis of rotation, the large lug protrudes radially outward beyond the two adjacent tension strips. The large lug has cantilevers extending about the axis of rotation and reaching over the two adjacent tension strips. | 1.-16. (canceled) 17. An electric machine, comprising:
a rotor supported in bearings for rotation about an axis of rotation; a stator arranged in radial surrounding relationship with respect to the axis of rotation and including stator sheets which are stacked upon one another in a direction of the axis of rotation, said stator sheets having a number of recesses radially outside with respect to the axis of rotation to form grooves in parallel relationship to the axis of rotation; tension strips arranged in the grooves and having ends; and end rings connected at the ends of the tension strips, wherein a first plurality of the stator sheets have each at least one first lug configured to project radially outwards between two of the tension strips adjacent to the first lug as viewed in a circumferential direction about the axis of rotation over the two adjacent tension strips, said first lug having cantilevers configured to extend about the axis of rotation and sized to reach over the two adjacent tension strips. 18. The electric machine of claim 17, wherein the first plurality of stator sheets have second lugs configured to respectively project radially outwards between two of the tension strips adjacent to the second lugs as viewed in the circumferential direction about the axis of rotation. 19. The electric machine of claim 18, wherein the second lugs are sized to extend radially outwards beyond the two adjacent tension strips. 20. The electric machine of claim 18, wherein the second lugs of the first plurality of stator sheets extend radially outwards by different distances. 21. The electric machine of claim 17, wherein six of the tension strips are provided. 22. The electric machine of claim 18, wherein the second lugs are sized more shallow than the first lug. 23. The electric machine of claim 17, wherein the stator sheets include a second plurality of stator sheets having each plural lugs, each lug of the second plurality of stator sheets being sized to project radially outwards between two of the tension strips adjacent to the lug as viewed in the circumferential direction about the axis of rotation beyond the two adjacent tension strips, said lugs of the second stator sheets being sized more shallow that the first lug of the first plurality of stator sheets in the absence of any cantilever extending about the axis of rotation and reaching over the tension strips. 24. The electric machine of claim 23, wherein the lugs of the second plurality of stator sheets are sized to project radially outwards to different distances, 25. The electric machine of claim 18, wherein a number of lugs of the second plurality of stator sheets is equal to a number of first and second lugs of the first plurality of stator sheets. 26. The electric machine of claim 17, wherein the stator sheets do not include any further stator sheets. 27. The electric machine of claim 17, wherein the tension strips have a rectangular or trapezoidal cross section. 28. The electric machine of claim 17, wherein the stator sheets are grouped into groups of directly consecutive stator sheets viewed in the direction of the axis of rotation, each said group having a uniform group contour, with the group contour varying from one of the groups of stator sheets to another one of the groups of stator sheets. 29. The electric machine of claim 28, wherein a number of stator sheets per group is between 4 and 10 and/or a thickness of the groups, viewed in the direction of the axis of rotation, is between 2.5 mm and 6.0 mm. 30. The electric machine of claim 28, wherein, viewed in the direction of the axis of rotation, the groups of stator sheets in the middle follow each other in a first sequence and, in edge areas adjacent to the middle on both sides, follow each other in a second sequence different from the first sequence. 31. A land vehicle, comprising:
drive wheels; and an electric machine including a rotor operatively connected to at least one of the drive wheels and supported in bearings for rotation about an axis of rotation which extends transverse to a direction of travel of the land vehicle, a stator arranged in radial surrounding relationship with respect to the axis of rotation and including stator sheets which are stacked upon one another in a direction of the axis of rotation, said stator sheets having a number of recesses radially outside with respect to the axis of rotation to form grooves in parallel relationship to the axis of rotation, tension strips arranged in the grooves and having ends, and end rings connected at the ends of the tension strips, wherein a first plurality of the stator sheets have each at least one lug configured to project radially outwards between two of the tension strips adjacent to the lug as viewed in a circumferential direction about the axis of rotation over the two adjacent tension strips, said lug configured without projecting downwards and having cantilevers configured to extend about the axis of rotation and sized to reach over the two adjacent tension strips. 32. The land vehicle of claim 31, wherein the lug is configured without projecting upwards. 33. The land vehicle of claim 31, wherein the drive wheels are embodied as running wheels of a rail vehicle. | An electric machine has rotor rotatably supported in bearings for rotation about an axis of rotation, a stator surrounding the rotor with respect to the axis of rotation and having stator sheets, which are stacked in the direction of the axis of rotation. The stator sheets have a number of recesses which form grooves extending parallel to the axis of rotation. Tension strips are arranged in the grooves and connected to end rings. The stator sheets include at least first stator sheets. The first stator sheets each have at least one large lug. Between the two tension strips adjacent to the respective large lug in a circumferential direction about the axis of rotation, the large lug protrudes radially outward beyond the two adjacent tension strips. The large lug has cantilevers extending about the axis of rotation and reaching over the two adjacent tension strips.1.-16. (canceled) 17. An electric machine, comprising:
a rotor supported in bearings for rotation about an axis of rotation; a stator arranged in radial surrounding relationship with respect to the axis of rotation and including stator sheets which are stacked upon one another in a direction of the axis of rotation, said stator sheets having a number of recesses radially outside with respect to the axis of rotation to form grooves in parallel relationship to the axis of rotation; tension strips arranged in the grooves and having ends; and end rings connected at the ends of the tension strips, wherein a first plurality of the stator sheets have each at least one first lug configured to project radially outwards between two of the tension strips adjacent to the first lug as viewed in a circumferential direction about the axis of rotation over the two adjacent tension strips, said first lug having cantilevers configured to extend about the axis of rotation and sized to reach over the two adjacent tension strips. 18. The electric machine of claim 17, wherein the first plurality of stator sheets have second lugs configured to respectively project radially outwards between two of the tension strips adjacent to the second lugs as viewed in the circumferential direction about the axis of rotation. 19. The electric machine of claim 18, wherein the second lugs are sized to extend radially outwards beyond the two adjacent tension strips. 20. The electric machine of claim 18, wherein the second lugs of the first plurality of stator sheets extend radially outwards by different distances. 21. The electric machine of claim 17, wherein six of the tension strips are provided. 22. The electric machine of claim 18, wherein the second lugs are sized more shallow than the first lug. 23. The electric machine of claim 17, wherein the stator sheets include a second plurality of stator sheets having each plural lugs, each lug of the second plurality of stator sheets being sized to project radially outwards between two of the tension strips adjacent to the lug as viewed in the circumferential direction about the axis of rotation beyond the two adjacent tension strips, said lugs of the second stator sheets being sized more shallow that the first lug of the first plurality of stator sheets in the absence of any cantilever extending about the axis of rotation and reaching over the tension strips. 24. The electric machine of claim 23, wherein the lugs of the second plurality of stator sheets are sized to project radially outwards to different distances, 25. The electric machine of claim 18, wherein a number of lugs of the second plurality of stator sheets is equal to a number of first and second lugs of the first plurality of stator sheets. 26. The electric machine of claim 17, wherein the stator sheets do not include any further stator sheets. 27. The electric machine of claim 17, wherein the tension strips have a rectangular or trapezoidal cross section. 28. The electric machine of claim 17, wherein the stator sheets are grouped into groups of directly consecutive stator sheets viewed in the direction of the axis of rotation, each said group having a uniform group contour, with the group contour varying from one of the groups of stator sheets to another one of the groups of stator sheets. 29. The electric machine of claim 28, wherein a number of stator sheets per group is between 4 and 10 and/or a thickness of the groups, viewed in the direction of the axis of rotation, is between 2.5 mm and 6.0 mm. 30. The electric machine of claim 28, wherein, viewed in the direction of the axis of rotation, the groups of stator sheets in the middle follow each other in a first sequence and, in edge areas adjacent to the middle on both sides, follow each other in a second sequence different from the first sequence. 31. A land vehicle, comprising:
drive wheels; and an electric machine including a rotor operatively connected to at least one of the drive wheels and supported in bearings for rotation about an axis of rotation which extends transverse to a direction of travel of the land vehicle, a stator arranged in radial surrounding relationship with respect to the axis of rotation and including stator sheets which are stacked upon one another in a direction of the axis of rotation, said stator sheets having a number of recesses radially outside with respect to the axis of rotation to form grooves in parallel relationship to the axis of rotation, tension strips arranged in the grooves and having ends, and end rings connected at the ends of the tension strips, wherein a first plurality of the stator sheets have each at least one lug configured to project radially outwards between two of the tension strips adjacent to the lug as viewed in a circumferential direction about the axis of rotation over the two adjacent tension strips, said lug configured without projecting downwards and having cantilevers configured to extend about the axis of rotation and sized to reach over the two adjacent tension strips. 32. The land vehicle of claim 31, wherein the lug is configured without projecting upwards. 33. The land vehicle of claim 31, wherein the drive wheels are embodied as running wheels of a rail vehicle. | 2,800 |
11,484 | 11,484 | 15,029,342 | 2,845 | The invention describes an easy-to-manufacture wide-band antenna arrangement ( 100 ) and a kitchen appliance including this antenna arrangement. A resonating part of any antenna arrangement has a flat shape, its outer edges have an elliptical curvature and a coaxial cable is located at a feed in a slit in the middle of the resonating plate. The resonating plate is parallel to a ground plane 105, and together those parts form a planar inverted-F antenna. Such an antenna is useful in combination with a kitchen hob and sensor applications that wirelessly communicate with the kitchen hob, e.g. for improving cooking results. | 1. Antenna arrangement comprising:
a ground-connecting part at one end, a shape part distal from the ground-connecting part with a curvature, a slit between the curvature, and a feed located within the slit. 2. Antenna arrangement according to claim 1, wherein the curvature is located at an outer edge. 3. Antenna arrangement according to claim 1, wherein the curvature has an elliptical shape. 4. Antenna arrangement according to claim 1, wherein the feed is coaxial. 5. Antenna arrangement according to claim 1, wherein the feed is connected on a tongue in the slit. 6. Antenna arrangement according to claim 1, wherein the slit extends in a longitudinal direction of the antenna arrangement. 7. Antenna arrangement according to claim 1, wherein the slit has parallel edges and/or is located in the middle of the shape part. 8. Antenna arrangement according to claim 1, having a flat shape and/or a ground plane connected to the ground-connecting part. 9. Antenna arrangement according to claim 1, wherein the shape part has a trapezoidal part next to the curvature. 10. Antenna arrangement according to claim 1, having a rectangular part next to the ground-connecting part. 11. Antenna arrangement according to claim 1, said antenna arrangement being manufactured of sheet metal. 12. Antenna arrangement according to claim 11, said antenna arrangement having a stepped shape wherein the ground-connecting part is parallel to the shape part and a rectangular part forms a right angle with both. 13. Antenna arrangement according to claim 1, said antenna arrangement being arranged as a planar inverted-F antenna with elliptically tapered resonating metallic plate. 14. Kitchen appliance comprising an antenna arrangement according to claim 1. 15. Kitchen appliance according to claim 14, comprising a wireless device adapted to communicate with the antenna arrangement. | The invention describes an easy-to-manufacture wide-band antenna arrangement ( 100 ) and a kitchen appliance including this antenna arrangement. A resonating part of any antenna arrangement has a flat shape, its outer edges have an elliptical curvature and a coaxial cable is located at a feed in a slit in the middle of the resonating plate. The resonating plate is parallel to a ground plane 105, and together those parts form a planar inverted-F antenna. Such an antenna is useful in combination with a kitchen hob and sensor applications that wirelessly communicate with the kitchen hob, e.g. for improving cooking results.1. Antenna arrangement comprising:
a ground-connecting part at one end, a shape part distal from the ground-connecting part with a curvature, a slit between the curvature, and a feed located within the slit. 2. Antenna arrangement according to claim 1, wherein the curvature is located at an outer edge. 3. Antenna arrangement according to claim 1, wherein the curvature has an elliptical shape. 4. Antenna arrangement according to claim 1, wherein the feed is coaxial. 5. Antenna arrangement according to claim 1, wherein the feed is connected on a tongue in the slit. 6. Antenna arrangement according to claim 1, wherein the slit extends in a longitudinal direction of the antenna arrangement. 7. Antenna arrangement according to claim 1, wherein the slit has parallel edges and/or is located in the middle of the shape part. 8. Antenna arrangement according to claim 1, having a flat shape and/or a ground plane connected to the ground-connecting part. 9. Antenna arrangement according to claim 1, wherein the shape part has a trapezoidal part next to the curvature. 10. Antenna arrangement according to claim 1, having a rectangular part next to the ground-connecting part. 11. Antenna arrangement according to claim 1, said antenna arrangement being manufactured of sheet metal. 12. Antenna arrangement according to claim 11, said antenna arrangement having a stepped shape wherein the ground-connecting part is parallel to the shape part and a rectangular part forms a right angle with both. 13. Antenna arrangement according to claim 1, said antenna arrangement being arranged as a planar inverted-F antenna with elliptically tapered resonating metallic plate. 14. Kitchen appliance comprising an antenna arrangement according to claim 1. 15. Kitchen appliance according to claim 14, comprising a wireless device adapted to communicate with the antenna arrangement. | 2,800 |
11,485 | 11,485 | 15,496,681 | 2,864 | An electronic device that can be worn by a user can include a processing unit and one or more sensors operatively connected to the processing unit. The processing unit can be adapted to determine an installation position of the electronic device based on one or more signals received from at least one sensor. | 1. A computer-implemented method for determining an installation position of a wearable audio device, the method comprising:
acquiring, using an accelerometer disposed in a wearable audio device, acceleration data over a period of time; transmitting the acceleration data to a processing unit; computing, using the processing unit, an aggregate metric based on the acceleration data, the aggregate metric indicating a net-positive or net-negative acceleration condition over the period of time; and determining, using the aggregate metric, the installation position of the wearable audio device that corresponds to a right ear or a left ear of a user. 2. The method of claim 1, wherein computing the aggregate metric for the acceleration data comprises determining at least one of a mean, median, or mode of the acceleration data over at least a portion of the period of time. 3. The method of claim 1, wherein:
the acceleration data comprises a set of acceleration values; and computing the aggregate metric for the acceleration data comprises analyzing a distribution of the set of acceleration values. 4. The method of claim 3, wherein analyzing the distribution of the set of acceleration values comprises:
defining two or more categories of possible accelerometer outputs; and identifying a category of the two or more categories for each value of the set of acceleration values. 5. The method of claim 4, wherein the aggregate metric corresponds to a prominent category of the two or more categories to which a highest number of values of the set of acceleration values are classified. 6. The method of claim 4, wherein a first category of the two or more categories corresponds to a positive acceleration condition and a second category of the two or more categories corresponds to a negative acceleration condition. 7. The method of claim 4, wherein classifying each value of the set of acceleration values comprises using at least one of a Bayes classifier or a mixture model. 8. The method of claim 1, wherein:
the accelerometer is a multi-axis accelerometer; and the acceleration data comprises acceleration data measured along three axes of the multi-axis accelerometer. 9. The method of claim 1, wherein:
the wearable audio device is a first wearable audio device; the processing unit is a processing unit of a portable electronic device that is communicatively coupled to the first wearable audio device; the portable electronic device is further communicatively coupled to a second wearable audio device; and the method further comprises:
determining, by the processing unit, based on the installation position of the first wearable audio device, which of the first wearable audio device or second wearable audio device to transmit an audio signal to. 10. The method of claim 9, wherein:
the audio signal is a first audio signal; and the method further comprises:
transmitting the first audio signal to the first wearable audio device; and
transmitting a second audio signal to the second wearable audio device; and
the first and second audio signals are left and right channels for an audio track, respectively. 11. The method of claim 1, wherein the processing unit is disposed in a portable electronic device. 12. The method of claim 1, wherein the processing unit is disposed in the wearable audio device. 13. A method for determining an installation position of a pair of wearable audio devices, the method comprising:
acquiring a first magnetometer data set using a first magnetometer disposed in a first wearable audio device of the pair of wearable audio devices; acquiring a second magnetometer data set using a second magnetometer disposed in a second wearable audio device of the pair of wearable audio devices; computing, by a processing unit, a first bearing using the first magnetometer data set, the first bearing having an associated first vector; computing, by the processing unit, a second bearing using the second magnetometer data set, the second bearing having an associated second vector; and determining, by the processing unit, an installation position of the first wearable audio device; wherein:
the installation position of the first wearable audio device corresponds to a condition in which the first vector and the second vector intersect. 14. The method of claim 13, wherein the installation position of the first wearable audio device indicates whether the first wearable audio device is installed at a left ear or a right ear of a user. 15. The method of claim 14, further comprising:
determining whether the first bearing is greater than the second bearing, wherein the installation position of the first wearable audio device is the left ear of the user if the first bearing is greater than the second bearing. 16. The method of claim 13, wherein determining the installation position of the first wearable audio device comprises analyzing, by the processing unit, acceleration data acquired by an accelerometer disposed in the first wearable audio device. 17. A system comprising:
a first wearable audio device comprising a first sensor configured to acquire first sensor data; a second wearable audio device comprising a second sensor configured to acquire second sensor data; and a portable electronic device comprising a processing unit, the portable electronic device communicatively coupled to the first and second wearable audio devices; wherein:
the portable electronic device is configured to determine, by the processing unit, using the first and second sensor data, a first installation position of the first wearable audio device and a second installation position of the second wearable audio device. 18. The system of claim 17, wherein the portable electronic device is configured to determine the first and second installation positions by computing a first aggregate metric for the first sensor data and a second aggregate metric for the second sensor data. 19. The system of claim 17, wherein the portable electronic device is further configured to send first audio data to the first wearable audio device and second audio data to the second wearable audio device based on the determined first and second installation positions. 20. The system of claim 17, wherein the first and second wearable audio devices are wireless earbuds. | An electronic device that can be worn by a user can include a processing unit and one or more sensors operatively connected to the processing unit. The processing unit can be adapted to determine an installation position of the electronic device based on one or more signals received from at least one sensor.1. A computer-implemented method for determining an installation position of a wearable audio device, the method comprising:
acquiring, using an accelerometer disposed in a wearable audio device, acceleration data over a period of time; transmitting the acceleration data to a processing unit; computing, using the processing unit, an aggregate metric based on the acceleration data, the aggregate metric indicating a net-positive or net-negative acceleration condition over the period of time; and determining, using the aggregate metric, the installation position of the wearable audio device that corresponds to a right ear or a left ear of a user. 2. The method of claim 1, wherein computing the aggregate metric for the acceleration data comprises determining at least one of a mean, median, or mode of the acceleration data over at least a portion of the period of time. 3. The method of claim 1, wherein:
the acceleration data comprises a set of acceleration values; and computing the aggregate metric for the acceleration data comprises analyzing a distribution of the set of acceleration values. 4. The method of claim 3, wherein analyzing the distribution of the set of acceleration values comprises:
defining two or more categories of possible accelerometer outputs; and identifying a category of the two or more categories for each value of the set of acceleration values. 5. The method of claim 4, wherein the aggregate metric corresponds to a prominent category of the two or more categories to which a highest number of values of the set of acceleration values are classified. 6. The method of claim 4, wherein a first category of the two or more categories corresponds to a positive acceleration condition and a second category of the two or more categories corresponds to a negative acceleration condition. 7. The method of claim 4, wherein classifying each value of the set of acceleration values comprises using at least one of a Bayes classifier or a mixture model. 8. The method of claim 1, wherein:
the accelerometer is a multi-axis accelerometer; and the acceleration data comprises acceleration data measured along three axes of the multi-axis accelerometer. 9. The method of claim 1, wherein:
the wearable audio device is a first wearable audio device; the processing unit is a processing unit of a portable electronic device that is communicatively coupled to the first wearable audio device; the portable electronic device is further communicatively coupled to a second wearable audio device; and the method further comprises:
determining, by the processing unit, based on the installation position of the first wearable audio device, which of the first wearable audio device or second wearable audio device to transmit an audio signal to. 10. The method of claim 9, wherein:
the audio signal is a first audio signal; and the method further comprises:
transmitting the first audio signal to the first wearable audio device; and
transmitting a second audio signal to the second wearable audio device; and
the first and second audio signals are left and right channels for an audio track, respectively. 11. The method of claim 1, wherein the processing unit is disposed in a portable electronic device. 12. The method of claim 1, wherein the processing unit is disposed in the wearable audio device. 13. A method for determining an installation position of a pair of wearable audio devices, the method comprising:
acquiring a first magnetometer data set using a first magnetometer disposed in a first wearable audio device of the pair of wearable audio devices; acquiring a second magnetometer data set using a second magnetometer disposed in a second wearable audio device of the pair of wearable audio devices; computing, by a processing unit, a first bearing using the first magnetometer data set, the first bearing having an associated first vector; computing, by the processing unit, a second bearing using the second magnetometer data set, the second bearing having an associated second vector; and determining, by the processing unit, an installation position of the first wearable audio device; wherein:
the installation position of the first wearable audio device corresponds to a condition in which the first vector and the second vector intersect. 14. The method of claim 13, wherein the installation position of the first wearable audio device indicates whether the first wearable audio device is installed at a left ear or a right ear of a user. 15. The method of claim 14, further comprising:
determining whether the first bearing is greater than the second bearing, wherein the installation position of the first wearable audio device is the left ear of the user if the first bearing is greater than the second bearing. 16. The method of claim 13, wherein determining the installation position of the first wearable audio device comprises analyzing, by the processing unit, acceleration data acquired by an accelerometer disposed in the first wearable audio device. 17. A system comprising:
a first wearable audio device comprising a first sensor configured to acquire first sensor data; a second wearable audio device comprising a second sensor configured to acquire second sensor data; and a portable electronic device comprising a processing unit, the portable electronic device communicatively coupled to the first and second wearable audio devices; wherein:
the portable electronic device is configured to determine, by the processing unit, using the first and second sensor data, a first installation position of the first wearable audio device and a second installation position of the second wearable audio device. 18. The system of claim 17, wherein the portable electronic device is configured to determine the first and second installation positions by computing a first aggregate metric for the first sensor data and a second aggregate metric for the second sensor data. 19. The system of claim 17, wherein the portable electronic device is further configured to send first audio data to the first wearable audio device and second audio data to the second wearable audio device based on the determined first and second installation positions. 20. The system of claim 17, wherein the first and second wearable audio devices are wireless earbuds. | 2,800 |
11,486 | 11,486 | 15,355,498 | 2,843 | An RF power package includes a substrate having a metallized part and an insulating part, an RF power transistor die embedded in or attached to the substrate, the RF power transistor die having a die input terminal, a die output terminal, an input impedance and an output impedance, a package input terminal formed in the metallized part or attached to the insulating part of the substrate, a package output terminal formed in the metallized part or attached to the insulating part of the substrate, and a first plurality of planar tuning lines formed in the metallized part of the substrate and electrically connecting the die output terminal to the package output terminal. The first plurality of planar tuning lines is shaped so as to transform the output impedance at the die output terminal to a higher target level at the package output terminal. | 1. An RF power package, comprising:
a substrate having a metallized part and an insulating part; an RF power transistor die embedded in or attached to the substrate, the RF power transistor die having a die input terminal, a die output terminal, an input impedance and an output impedance; a package input terminal formed in the metallized part or attached to the insulating part of the substrate; a package output terminal formed in the metallized part or attached to the insulating part of the substrate; and a first plurality of planar tuning lines formed in the metallized part of the substrate and electrically connecting the die output terminal to the package output terminal, wherein the first plurality of planar tuning lines is shaped so as to transform the output impedance at the die output terminal to a higher target level at the package output terminal. 2. The RF power package of claim 1, wherein the substrate comprises a ceramic body and a patterned metallization applied to the ceramic body, and wherein the patterned metallization forms the metallized part of the substrate. 3. The RF power package of claim 1, wherein the substrate is a printed circuit board comprising conductive tracks patterned into one or more copper sheets laminated onto a non-conductive body, and wherein the conductive tracks and the one or more copper sheets form the metallized part of the substrate. 4. The RF power package of claim 1, wherein the substrate comprises a first insulating material in which the RF power transistor die is embedded, a second insulating material covering the first insulating material and the RF power transistor die, and one or more metal redistribution layers disposed in the second insulating material, wherein each metal redistribution layer is electrically connected to die input terminal and/or die output terminal through openings in the second insulating material, and wherein the one or more metal redistribution layers form the metallized part of the substrate. 5. The RF power package of claim 1, wherein the first plurality of planar tuning lines is formed in straight lines. 6. The RF power package of claim 1, further comprising:
a capacitor embedded in or attached to the substrate and electrically connected between the die output terminal and the package output terminal, wherein the first plurality of planar tuning lines and the capacitor form an output impedance matching network. 7. The RF power package of claim 1, further comprising:
a second plurality of planar tuning lines formed in the metallized part of the substrate and electrically connecting the die input terminal to the package input terminal, wherein the second plurality of planar tuning lines is shaped so as to transform the input impedance at the die input terminal to a different level at the package input terminal. 8. The RF power package of claim 7, further comprising:
a capacitor embedded in or attached to the substrate and electrically connected between the die input terminal and the package input terminal, wherein the second plurality of planar tuning lines and the second capacitor form an input impedance matching network. 9. The RF power package of claim 7, wherein the second plurality of planar tuning lines is formed in meandering lines. 10. The RF power package of claim 1, further comprising:
an additional RF power transistor die embedded in or attached to the substrate, the additional RF power transistor die having a die input terminal, a die output terminal, an input impedance and an output impedance, wherein the RF power transistor die is a main amplifier of a Doherty amplifier circuit, wherein the additional RF power transistor die is a peaking amplifier of the Doherty amplifier circuit, wherein the first plurality of planar tuning lines is shaped so as to form a first ¼ wave transmission line for phase aligning signal outputs of the RF power transistor dies such that the signal outputs are reactively combined at a first impedance level which is above the output impedance of the RF power transistor dies, and so as to form a second ¼ wave transmission line for increasing the impedance of the signal outputs to a second impedance level greater than the first impedance level at the package output terminal. 11. A method of manufacturing an RF power package, the method comprising:
embedding or attaching an RF power transistor die to a substrate having a metallized part and an insulating part, the RF power transistor die having a die input terminal, a die output terminal, an input impedance and an output impedance; and forming a first plurality of planar tuning lines in the metallized part of the substrate, the first plurality of planar tuning lines electrically connecting the die output terminal to a package output terminal formed in the metallized part or attached to the insulating part of the substrate, wherein forming the first plurality of planar tuning lines comprises shaping the first plurality of planar tuning lines so that the first plurality of planar tuning lines transforms the output impedance at the die output terminal to a higher target level at the package output terminal. 12. The method of claim 11, wherein shaping the first plurality of planar tuning lines so as to transform the output impedance at the die output terminal to the higher target level at the package output terminal comprises shaping the first plurality of planar tuning lines as straight lines. 13. The method of claim 11, further comprising:
embedding or attaching a capacitor to the substrate; and electrically connecting the capacitor between the die output terminal and the package output terminal via the first plurality of planar tuning lines, wherein the first plurality of planar tuning lines and the capacitor form an output impedance matching network. 14. The RF power package of claim 11, further comprising:
forming a second plurality of planar tuning lines in the metallized part of the substrate; and electrically connecting the die input terminal to a package input terminal formed in the metallized part or attached to the insulating part of the substrate via the second plurality of planar tuning lines, wherein the second plurality of planar tuning lines is shaped so as to transform the input impedance at the die input terminal to a different level at the package input terminal. 15. The RF power package of claim 14, further comprising:
embedding or attaching a capacitor to the substrate; and electrically connecting the capacitor between the die input terminal and the package input terminal via the second plurality of planar tuning lines, wherein the second plurality of planar tuning lines and the second capacitor form an input impedance matching network. 16. The RF power package of claim 14, wherein shaping the second plurality of planar tuning lines so as transform the input impedance at the die input terminal to a different level at the package input terminal comprises shaping the first plurality of planar tuning lines as meandering lines. 17. The RF power package of claim 11, further comprising:
embedding or attaching an additional RF power transistor die to the substrate, the additional RF power transistor die having a die input terminal, a die output terminal, an input impedance and an output impedance, wherein the RF power transistor die is a main amplifier of a Doherty amplifier circuit, wherein the additional RF power transistor die is a peaking amplifier of the Doherty amplifier circuit, wherein shaping the first plurality of planar tuning lines so as transform the output impedance at the die output terminal to the higher target level at the package output terminal comprises shaping the first plurality of planar tuning lines so as to form a first ¼ wave transmission line for phase aligning signal outputs of the RF power transistor dies such that the signal outputs are reactively combined at a first impedance level which is above the output impedance of the RF power transistor dies, and so as to form a second ¼ wave transmission line for increasing the impedance of the signal outputs to a second impedance level greater than the first impedance level at the package output terminal. 18. The RF power package of claim 11, wherein an initial shape of the first plurality of planar tuning lines is determined prior to formation based on a nominal thickness specified for the substrate, and wherein forming the first plurality of planar tuning lines comprises:
determining the difference between the nominal thickness and a measured thickness of the substrate; and determining, based on the difference between the nominal thickness and the measured thickness, an amount of adjustment needed to the initial shape so that the output impedance at the die output terminal is still transformed to the higher target level at the package output terminal via the first plurality of planar tuning lines when formed with the adjusted shape. 19. The RF power package of claim 11, wherein an initial shape of the first plurality of planar tuning lines is determined prior to formation based on an expected electrical parameter for the RF power transistor die, and wherein forming the first plurality of planar tuning lines comprises:
determining the difference between the expected electrical parameter and a measured electrical parameter of the RF power transistor die; and determining, based on the difference between the expected electrical parameter and the measured electrical parameter, an amount of adjustment needed to the initial shape so that the output impedance at the die output terminal is still transformed to the higher target level at the package output terminal via the first plurality of planar tuning lines when formed with the adjusted shape. | An RF power package includes a substrate having a metallized part and an insulating part, an RF power transistor die embedded in or attached to the substrate, the RF power transistor die having a die input terminal, a die output terminal, an input impedance and an output impedance, a package input terminal formed in the metallized part or attached to the insulating part of the substrate, a package output terminal formed in the metallized part or attached to the insulating part of the substrate, and a first plurality of planar tuning lines formed in the metallized part of the substrate and electrically connecting the die output terminal to the package output terminal. The first plurality of planar tuning lines is shaped so as to transform the output impedance at the die output terminal to a higher target level at the package output terminal.1. An RF power package, comprising:
a substrate having a metallized part and an insulating part; an RF power transistor die embedded in or attached to the substrate, the RF power transistor die having a die input terminal, a die output terminal, an input impedance and an output impedance; a package input terminal formed in the metallized part or attached to the insulating part of the substrate; a package output terminal formed in the metallized part or attached to the insulating part of the substrate; and a first plurality of planar tuning lines formed in the metallized part of the substrate and electrically connecting the die output terminal to the package output terminal, wherein the first plurality of planar tuning lines is shaped so as to transform the output impedance at the die output terminal to a higher target level at the package output terminal. 2. The RF power package of claim 1, wherein the substrate comprises a ceramic body and a patterned metallization applied to the ceramic body, and wherein the patterned metallization forms the metallized part of the substrate. 3. The RF power package of claim 1, wherein the substrate is a printed circuit board comprising conductive tracks patterned into one or more copper sheets laminated onto a non-conductive body, and wherein the conductive tracks and the one or more copper sheets form the metallized part of the substrate. 4. The RF power package of claim 1, wherein the substrate comprises a first insulating material in which the RF power transistor die is embedded, a second insulating material covering the first insulating material and the RF power transistor die, and one or more metal redistribution layers disposed in the second insulating material, wherein each metal redistribution layer is electrically connected to die input terminal and/or die output terminal through openings in the second insulating material, and wherein the one or more metal redistribution layers form the metallized part of the substrate. 5. The RF power package of claim 1, wherein the first plurality of planar tuning lines is formed in straight lines. 6. The RF power package of claim 1, further comprising:
a capacitor embedded in or attached to the substrate and electrically connected between the die output terminal and the package output terminal, wherein the first plurality of planar tuning lines and the capacitor form an output impedance matching network. 7. The RF power package of claim 1, further comprising:
a second plurality of planar tuning lines formed in the metallized part of the substrate and electrically connecting the die input terminal to the package input terminal, wherein the second plurality of planar tuning lines is shaped so as to transform the input impedance at the die input terminal to a different level at the package input terminal. 8. The RF power package of claim 7, further comprising:
a capacitor embedded in or attached to the substrate and electrically connected between the die input terminal and the package input terminal, wherein the second plurality of planar tuning lines and the second capacitor form an input impedance matching network. 9. The RF power package of claim 7, wherein the second plurality of planar tuning lines is formed in meandering lines. 10. The RF power package of claim 1, further comprising:
an additional RF power transistor die embedded in or attached to the substrate, the additional RF power transistor die having a die input terminal, a die output terminal, an input impedance and an output impedance, wherein the RF power transistor die is a main amplifier of a Doherty amplifier circuit, wherein the additional RF power transistor die is a peaking amplifier of the Doherty amplifier circuit, wherein the first plurality of planar tuning lines is shaped so as to form a first ¼ wave transmission line for phase aligning signal outputs of the RF power transistor dies such that the signal outputs are reactively combined at a first impedance level which is above the output impedance of the RF power transistor dies, and so as to form a second ¼ wave transmission line for increasing the impedance of the signal outputs to a second impedance level greater than the first impedance level at the package output terminal. 11. A method of manufacturing an RF power package, the method comprising:
embedding or attaching an RF power transistor die to a substrate having a metallized part and an insulating part, the RF power transistor die having a die input terminal, a die output terminal, an input impedance and an output impedance; and forming a first plurality of planar tuning lines in the metallized part of the substrate, the first plurality of planar tuning lines electrically connecting the die output terminal to a package output terminal formed in the metallized part or attached to the insulating part of the substrate, wherein forming the first plurality of planar tuning lines comprises shaping the first plurality of planar tuning lines so that the first plurality of planar tuning lines transforms the output impedance at the die output terminal to a higher target level at the package output terminal. 12. The method of claim 11, wherein shaping the first plurality of planar tuning lines so as to transform the output impedance at the die output terminal to the higher target level at the package output terminal comprises shaping the first plurality of planar tuning lines as straight lines. 13. The method of claim 11, further comprising:
embedding or attaching a capacitor to the substrate; and electrically connecting the capacitor between the die output terminal and the package output terminal via the first plurality of planar tuning lines, wherein the first plurality of planar tuning lines and the capacitor form an output impedance matching network. 14. The RF power package of claim 11, further comprising:
forming a second plurality of planar tuning lines in the metallized part of the substrate; and electrically connecting the die input terminal to a package input terminal formed in the metallized part or attached to the insulating part of the substrate via the second plurality of planar tuning lines, wherein the second plurality of planar tuning lines is shaped so as to transform the input impedance at the die input terminal to a different level at the package input terminal. 15. The RF power package of claim 14, further comprising:
embedding or attaching a capacitor to the substrate; and electrically connecting the capacitor between the die input terminal and the package input terminal via the second plurality of planar tuning lines, wherein the second plurality of planar tuning lines and the second capacitor form an input impedance matching network. 16. The RF power package of claim 14, wherein shaping the second plurality of planar tuning lines so as transform the input impedance at the die input terminal to a different level at the package input terminal comprises shaping the first plurality of planar tuning lines as meandering lines. 17. The RF power package of claim 11, further comprising:
embedding or attaching an additional RF power transistor die to the substrate, the additional RF power transistor die having a die input terminal, a die output terminal, an input impedance and an output impedance, wherein the RF power transistor die is a main amplifier of a Doherty amplifier circuit, wherein the additional RF power transistor die is a peaking amplifier of the Doherty amplifier circuit, wherein shaping the first plurality of planar tuning lines so as transform the output impedance at the die output terminal to the higher target level at the package output terminal comprises shaping the first plurality of planar tuning lines so as to form a first ¼ wave transmission line for phase aligning signal outputs of the RF power transistor dies such that the signal outputs are reactively combined at a first impedance level which is above the output impedance of the RF power transistor dies, and so as to form a second ¼ wave transmission line for increasing the impedance of the signal outputs to a second impedance level greater than the first impedance level at the package output terminal. 18. The RF power package of claim 11, wherein an initial shape of the first plurality of planar tuning lines is determined prior to formation based on a nominal thickness specified for the substrate, and wherein forming the first plurality of planar tuning lines comprises:
determining the difference between the nominal thickness and a measured thickness of the substrate; and determining, based on the difference between the nominal thickness and the measured thickness, an amount of adjustment needed to the initial shape so that the output impedance at the die output terminal is still transformed to the higher target level at the package output terminal via the first plurality of planar tuning lines when formed with the adjusted shape. 19. The RF power package of claim 11, wherein an initial shape of the first plurality of planar tuning lines is determined prior to formation based on an expected electrical parameter for the RF power transistor die, and wherein forming the first plurality of planar tuning lines comprises:
determining the difference between the expected electrical parameter and a measured electrical parameter of the RF power transistor die; and determining, based on the difference between the expected electrical parameter and the measured electrical parameter, an amount of adjustment needed to the initial shape so that the output impedance at the die output terminal is still transformed to the higher target level at the package output terminal via the first plurality of planar tuning lines when formed with the adjusted shape. | 2,800 |
11,487 | 11,487 | 15,424,956 | 2,853 | A printing apparatus provides a printing path disposed along one level, the printing path having a first portion and second portion, each portion having a printhead associated therewith. The apparatus further includes a drying path along a second level, the drying path including two dryer modules. In one arrangement in which the apparatus can operate, a sheet path provides for printing in the first portion of the print path, drying in the first drying module, printing on the second side of a sheet in the second portion of the sheet path, and drying in the second drying module. In another arrangement in which the apparatus can operate, a sheet path can provide for printing in either or both portions of the sheet path, followed by drying in one or both drying modules and then exit from the apparatus, such as to a second apparatus. The architecture enables the apparatus to function by itself or as part of a multi-apparatus printing system. | 1. A printing apparatus, comprising:
a printing path disposed along a first level, the printing path defining a first portion having a first printhead associated therewith, and a second portion having a second printhead associated therewith; a drying path, including a first dryer module and a second dryer module, the drying path being disposed along a second level; a return path disposed along a third level, the return path being configured to convey a sheet passing to the left from the drying path to the right through the return path; whereby a sheet can be fed in one of:
(a) a first arrangement, whereby a sheet is fed to the right through the first portion of the printing path, to the left through the first drying module, through at least a portion of the return path, through the left through the second portion of the printing path, and to the right through the second drying module, and
(b) a second arrangement, whereby a sheet is fed to the right through at least the first portion of the printing path, and to the left through at least the first drying module, and then out of the printing apparatus. 2. The apparatus of claim 1, wherein the first printhead and second printhead are each capable of placing a multi-color image on the sheet. 3. The apparatus of claim 1, the second level being disposed below the first level. 4. The apparatus of claim 1, wherein the first portion of the printing path and the second portion of the printing path are collinear. 5. The apparatus of claim 1, whereby, in the second arrangement, the sheet is fed in series through the second drying module and the first drying module. 6. The apparatus of claim 1, wherein the first drying module and the second drying module are positionally interchangeable. 7. The apparatus of claim 1, further comprising an extension module, the extension module including an extension to the second portion of the printing path, and a printhead that prints on a sheet passing through the extension. 8. The apparatus of claim 1, further comprising an inverter operatively disposed along the return path, the inverter inverting a sheet being fed out of the apparatus. 9. A printing system having a first printing apparatus and a second printing apparatus, whereby a sheet is fed from the first printing apparatus to the second printing apparatus, each printing apparatus comprising:
a printing path disposed along a first level, the printing path defining at least a first portion having a first printhead associated therewith, and a drying path, including at least a first dryer module, the drying path being disposed along a second level; wherein a sheet may be fed in one of:
(a) a first arrangement wherein a sheet is fed to the right in the printing path of the first printing apparatus, then to the left in the drying path of the first printing apparatus, to the left in the printing path of the second printing apparatus, then to the right in the drying path of the second printing apparatus, or
(b) a second arrangement wherein a sheet is fed to the right in the printing path of the first printing apparatus, then to the left in the drying path of the first printing apparatus, to the right in the printing path of the second printing apparatus, then to the left in the drying path of the second printing apparatus. 10. The printing system of claim 9, further comprising an inverter operatively disposed between the first printing apparatus to the second printing apparatus. 11. The printing system of claim 9, further comprising an inverter operatively disposed after the second printing apparatus. 12. The printing system of claim 9, wherein the printing path of the first printing apparatus is capable of printing a multi-color image on the sheet. 13. The printing system of claim 9, wherein the printing path of the first printing apparatus and the second printing apparatus is capable of printing a multi-color image on the sheet. 14. The printing system of claim 9, wherein the drying path of the first printing apparatus includes a plurality of dryer modules, wherein the drying modules are positionally interchangeable. 15. The printing system of claim 9, wherein the drying path of the first printing apparatus and the second printing apparatus includes a plurality of dryer modules, wherein the drying modules are positionally interchangeable. | A printing apparatus provides a printing path disposed along one level, the printing path having a first portion and second portion, each portion having a printhead associated therewith. The apparatus further includes a drying path along a second level, the drying path including two dryer modules. In one arrangement in which the apparatus can operate, a sheet path provides for printing in the first portion of the print path, drying in the first drying module, printing on the second side of a sheet in the second portion of the sheet path, and drying in the second drying module. In another arrangement in which the apparatus can operate, a sheet path can provide for printing in either or both portions of the sheet path, followed by drying in one or both drying modules and then exit from the apparatus, such as to a second apparatus. The architecture enables the apparatus to function by itself or as part of a multi-apparatus printing system.1. A printing apparatus, comprising:
a printing path disposed along a first level, the printing path defining a first portion having a first printhead associated therewith, and a second portion having a second printhead associated therewith; a drying path, including a first dryer module and a second dryer module, the drying path being disposed along a second level; a return path disposed along a third level, the return path being configured to convey a sheet passing to the left from the drying path to the right through the return path; whereby a sheet can be fed in one of:
(a) a first arrangement, whereby a sheet is fed to the right through the first portion of the printing path, to the left through the first drying module, through at least a portion of the return path, through the left through the second portion of the printing path, and to the right through the second drying module, and
(b) a second arrangement, whereby a sheet is fed to the right through at least the first portion of the printing path, and to the left through at least the first drying module, and then out of the printing apparatus. 2. The apparatus of claim 1, wherein the first printhead and second printhead are each capable of placing a multi-color image on the sheet. 3. The apparatus of claim 1, the second level being disposed below the first level. 4. The apparatus of claim 1, wherein the first portion of the printing path and the second portion of the printing path are collinear. 5. The apparatus of claim 1, whereby, in the second arrangement, the sheet is fed in series through the second drying module and the first drying module. 6. The apparatus of claim 1, wherein the first drying module and the second drying module are positionally interchangeable. 7. The apparatus of claim 1, further comprising an extension module, the extension module including an extension to the second portion of the printing path, and a printhead that prints on a sheet passing through the extension. 8. The apparatus of claim 1, further comprising an inverter operatively disposed along the return path, the inverter inverting a sheet being fed out of the apparatus. 9. A printing system having a first printing apparatus and a second printing apparatus, whereby a sheet is fed from the first printing apparatus to the second printing apparatus, each printing apparatus comprising:
a printing path disposed along a first level, the printing path defining at least a first portion having a first printhead associated therewith, and a drying path, including at least a first dryer module, the drying path being disposed along a second level; wherein a sheet may be fed in one of:
(a) a first arrangement wherein a sheet is fed to the right in the printing path of the first printing apparatus, then to the left in the drying path of the first printing apparatus, to the left in the printing path of the second printing apparatus, then to the right in the drying path of the second printing apparatus, or
(b) a second arrangement wherein a sheet is fed to the right in the printing path of the first printing apparatus, then to the left in the drying path of the first printing apparatus, to the right in the printing path of the second printing apparatus, then to the left in the drying path of the second printing apparatus. 10. The printing system of claim 9, further comprising an inverter operatively disposed between the first printing apparatus to the second printing apparatus. 11. The printing system of claim 9, further comprising an inverter operatively disposed after the second printing apparatus. 12. The printing system of claim 9, wherein the printing path of the first printing apparatus is capable of printing a multi-color image on the sheet. 13. The printing system of claim 9, wherein the printing path of the first printing apparatus and the second printing apparatus is capable of printing a multi-color image on the sheet. 14. The printing system of claim 9, wherein the drying path of the first printing apparatus includes a plurality of dryer modules, wherein the drying modules are positionally interchangeable. 15. The printing system of claim 9, wherein the drying path of the first printing apparatus and the second printing apparatus includes a plurality of dryer modules, wherein the drying modules are positionally interchangeable. | 2,800 |
11,488 | 11,488 | 15,014,096 | 2,847 | A method of forming a high-conductivity electrical interconnect on a substrate may include forming a graphene film with a plurality of graphene members, depositing a metal over the graphene film, and providing a metallic overlay that connects the plurality of graphene members together through the depositing operation to form a covered graphene film. | 1. A high-conductivity electrical interconnect configured to electrically interconnect electrical components, the high-conductivity electrical interconnect comprising:
a plurality of graphene members; and a metallic overlay connecting the plurality of graphene members together. 2. The high-conductivity electrical interconnect of claim 1, wherein the metallic overlay connects peripheral edges of the plurality of graphene members together. 3. The high-conductivity electrical interconnect of claim 1, wherein the metallic overlay renders the plurality of graphene members conductively isotropic with respect to X, Y, and Z axes. 4. The high-conductivity electrical interconnect of claim 1, wherein the plurality of graphene members are embedded in the metallic overlay. 5. The high-conductivity electrical interconnect of claim 1, wherein the plurality of graphene members are doped. 6. The high-conductivity electrical interconnect of claim 5, wherein the plurality of graphene members are doped with bromine. 7. The high-conductivity electrical interconnect of claim 1, wherein the plurality of graphene members are positioned on a dielectric substrate, and wherein metal is deposited over the plurality of graphene members to form the metallic overlay. 8. The high-conductivity electrical interconnect of claim 7, wherein the metal is deposited over the plurality of graphene members through one or more of sputtering, atomic layer deposition, chemical vapor deposition, or electrochemical deposition. 9. The high-conductivity electrical interconnect of claim 7, wherein the dielectric substrate is formed of one or more of FR4 material, glass, or a circuit board. 10. The high-conductivity electrical interconnect of claim 1, wherein the metallic overlay is formed of one or more of copper, aluminum, gold, palladium, or silver. 11. The high-conductivity electrical interconnect of claim 1, wherein the high-conductivity electrical interconnect is configured to be mixed into a printer ink. 12. A method of forming a high-conductivity electrical interconnect on a substrate, the method comprising:
forming a graphene film with a plurality of graphene members; depositing a metal over the graphene film; and providing a metallic overlay that connects the plurality of graphene members together through the depositing operation to form a covered graphene film. 13. The method of claim 12, wherein the providing operation comprises connecting peripheral edges of the plurality of graphene members together. 14. The method of claim 12, wherein the providing operation comprises rendering the plurality of graphene members conductively isotropic with respect to X, Y, and Z axes. 15. The method of claim 12, further comprising doping the plurality of graphene members with bromine. 16. The method of claim 12, further comprising positioning the graphene film onto the substrate, and wherein the depositing operation occurs after the positioning operation. 17. The method of claim 12, wherein the depositing operation comprises one or more of sputtering, atomic layer deposition, chemical vapor deposition, or electrochemical deposition. 18. The method of claim 12, further comprising:
mixing the covered graphene film and other covered graphene films in ink; and depositing the ink having the covered graphene films onto the substrate. 19. A high-conductivity electrical interconnect configured to electrically interconnect electrical components, the high-conductivity electrical interconnect comprising:
a plurality of bromine-doped graphene members; and a metallic overlay connecting the plurality of graphene members together, wherein the metallic overlay connects peripheral edges of the plurality of graphene members together, wherein the metallic overlay renders the plurality of graphene members conductively isotropic with respect to X, Y, and Z axes. 20. The high-conductivity electrical interconnect of claim 19, wherein the plurality of graphene members are positioned on a dielectric substrate, and wherein metal is deposited over the plurality of graphene members to form the metallic overlay, and wherein the metal is deposited over the plurality of graphene members through one or more of sputtering, atomic layer deposition, chemical vapor deposition, or electrochemical deposition. | A method of forming a high-conductivity electrical interconnect on a substrate may include forming a graphene film with a plurality of graphene members, depositing a metal over the graphene film, and providing a metallic overlay that connects the plurality of graphene members together through the depositing operation to form a covered graphene film.1. A high-conductivity electrical interconnect configured to electrically interconnect electrical components, the high-conductivity electrical interconnect comprising:
a plurality of graphene members; and a metallic overlay connecting the plurality of graphene members together. 2. The high-conductivity electrical interconnect of claim 1, wherein the metallic overlay connects peripheral edges of the plurality of graphene members together. 3. The high-conductivity electrical interconnect of claim 1, wherein the metallic overlay renders the plurality of graphene members conductively isotropic with respect to X, Y, and Z axes. 4. The high-conductivity electrical interconnect of claim 1, wherein the plurality of graphene members are embedded in the metallic overlay. 5. The high-conductivity electrical interconnect of claim 1, wherein the plurality of graphene members are doped. 6. The high-conductivity electrical interconnect of claim 5, wherein the plurality of graphene members are doped with bromine. 7. The high-conductivity electrical interconnect of claim 1, wherein the plurality of graphene members are positioned on a dielectric substrate, and wherein metal is deposited over the plurality of graphene members to form the metallic overlay. 8. The high-conductivity electrical interconnect of claim 7, wherein the metal is deposited over the plurality of graphene members through one or more of sputtering, atomic layer deposition, chemical vapor deposition, or electrochemical deposition. 9. The high-conductivity electrical interconnect of claim 7, wherein the dielectric substrate is formed of one or more of FR4 material, glass, or a circuit board. 10. The high-conductivity electrical interconnect of claim 1, wherein the metallic overlay is formed of one or more of copper, aluminum, gold, palladium, or silver. 11. The high-conductivity electrical interconnect of claim 1, wherein the high-conductivity electrical interconnect is configured to be mixed into a printer ink. 12. A method of forming a high-conductivity electrical interconnect on a substrate, the method comprising:
forming a graphene film with a plurality of graphene members; depositing a metal over the graphene film; and providing a metallic overlay that connects the plurality of graphene members together through the depositing operation to form a covered graphene film. 13. The method of claim 12, wherein the providing operation comprises connecting peripheral edges of the plurality of graphene members together. 14. The method of claim 12, wherein the providing operation comprises rendering the plurality of graphene members conductively isotropic with respect to X, Y, and Z axes. 15. The method of claim 12, further comprising doping the plurality of graphene members with bromine. 16. The method of claim 12, further comprising positioning the graphene film onto the substrate, and wherein the depositing operation occurs after the positioning operation. 17. The method of claim 12, wherein the depositing operation comprises one or more of sputtering, atomic layer deposition, chemical vapor deposition, or electrochemical deposition. 18. The method of claim 12, further comprising:
mixing the covered graphene film and other covered graphene films in ink; and depositing the ink having the covered graphene films onto the substrate. 19. A high-conductivity electrical interconnect configured to electrically interconnect electrical components, the high-conductivity electrical interconnect comprising:
a plurality of bromine-doped graphene members; and a metallic overlay connecting the plurality of graphene members together, wherein the metallic overlay connects peripheral edges of the plurality of graphene members together, wherein the metallic overlay renders the plurality of graphene members conductively isotropic with respect to X, Y, and Z axes. 20. The high-conductivity electrical interconnect of claim 19, wherein the plurality of graphene members are positioned on a dielectric substrate, and wherein metal is deposited over the plurality of graphene members to form the metallic overlay, and wherein the metal is deposited over the plurality of graphene members through one or more of sputtering, atomic layer deposition, chemical vapor deposition, or electrochemical deposition. | 2,800 |
11,489 | 11,489 | 14,904,809 | 2,896 | The invention relates to an optical coupler ( 10 ) in a vertical configuration, capable of working for a wavelength and comprising a first waveguide ( 12 ) and a second waveguide ( 14 ). The second waveguide ( 14 ) has a patterning ( 33 ) in the form of a series of patterns ( 36 ), the patterns ( 36 ) extending along a transverse direction (X) perpendicular to the longitudinal direction (Z), being parallel to each other and orthogonal to the general direction of the first waveguide ( 12 ), each pattern ( 36 ) being arranged both in the core ( 30 ) and the cladding ( 32 ) of the second waveguide ( 14 ) and having parameters influencing the evanescent wave coupling between the first waveguide ( 12 ) and the second waveguide ( 14 ), said parameters being chosen such that the coupling (C) is greater than 15%. | 1. An optical coupler in a vertical configuration, capable of working for a wavelength and comprising:
a first waveguide extending in the longitudinal direction and capable of propagating a first propagation mode of the light having a first effective index, a second waveguide distinct from the first waveguide, parallel to the first waveguide, having a core and a cladding and capable of propagating a second propagation mode of the light having a second effective index, the second effective index being different from the first effective index, the second waveguide having a patterning, the patterning having a period along the longitudinal direction below the ratio between the wavelength at which the optical coupler is capable of operating and the product of two by the second effective index, the patterning being in the form of a series of patterns, the patterns extending along a transverse direction perpendicular to the longitudinal direction, being parallel to each other and orthogonal to the general direction of the first waveguide, each pattern having parameters influencing the evanescent wave coupling between the first waveguide and the second waveguide, said parameters being chosen such that the coupling is greater than 15%. 2. The optical coupler according to claim 1, wherein the patterns are chosen from the group made up of:
openings made in the second waveguide, and blades. 3. The optical coupler according to claim 1, wherein the patterns have a dimension along the transverse direction larger than the dimension of the core of the second waveguide along the transverse direction. 4. The optical coupler according to claim 1, wherein the core of the second waveguide having an optical index, the second effective index is greater than the first effective index and the patterns are made from a material having an optical index below the optical index of the core of the second waveguide. 5. The optical coupler according to claim 1, wherein the patterning has a fill factor, the patterns are made from a material having an optical index, the parameters influencing the evanescent wave coupling between the first waveguide and the second waveguide being the fill factor of the patterning, the optical index of the material from which the patterns are made, and the spacing along the longitudinal direction between each pattern. 6. The optical coupler according to claim 1, wherein each pattern is arranged both in the core and the cladding of the second waveguide. 7. The optical coupler according to claim 1, wherein each waveguide includes a cladding and a core, the optical index of the core of the first waveguide being below the optical index of the cladding of the second waveguide. 8. The optical coupler according to claim 1, wherein the spacing along the longitudinal direction between the patterns is variable in the longitudinal direction. 9. The optical coupler according to claim 1, wherein the first waveguide includes a core made from a material belonging to column III of the periodic table formed with a material from column V of the periodic table and two lower and upper layers surrounding the core. 10. The optical coupler according to claim 1, wherein the core of the second waveguide has a variable dimension in the transverse direction. 11. The optical coupler according to claim 1, wherein the optical coupler includes a substrate, made from a first material, in which the second waveguide is buried, the first waveguide being arranged in contact with the substrate and formed from a material different from the first material. 12. The optical coupler according to claim 1, wherein the optical coupler includes a third waveguide distinct from the first and second waveguides and extending parallel to the first and second waveguides, the third waveguide being arranged between the first waveguide and the second waveguide and being capable of propagating a third light propagation mode having a third effective index. 13. The optical coupler according to claim 1, including a thermal insulation zone of the first waveguide in which the patterning is arranged. 14. An optical component comprising an optical coupler according claim. 15. A method for determining an optical coupler in a vertical configuration, capable of working for a wavelength and comprising:
a first waveguide extending in the longitudinal direction and capable of propagating a first propagation mode of the light having a first effective index, a second waveguide distinct from the first waveguide, parallel to the first waveguide, having a core and a cladding and capable of propagating a second propagation mode of the light having a second effective index, the second effective index being greater than the first effective index, the second waveguide (14) having a patterning, the patterning having a period along the longitudinal direction below the ratio between the wavelength at which the optical coupler is capable of operating and the product of two by the second effective index, the patterning being in the form of a series of patterns having parameters influencing the evanescent wave coupling between the first waveguide and the second waveguide, the patterns extending along a transverse direction perpendicular to the longitudinal direction, being parallel to each other and orthogonal to the general direction of the first waveguide, each pattern having parameters influencing the evanescent wave coupling between the first waveguide and the second waveguide, the method comprising a step for: choosing a desired evanescent wave coupling between the first waveguide and the second waveguide, the desired coupling being greater than or equal to 15%, modifying the parameters of the patterning to obtain the desired evanescent wave coupling between the first waveguide and the second waveguide. 16. A method for manufacturing an optical coupler according to claim 1, wherein the manufacturing method comprises steps for manufacturing waveguides and the patterning involving techniques for deposition, epitaxy, polishing, gluing and material removal by etching. | The invention relates to an optical coupler ( 10 ) in a vertical configuration, capable of working for a wavelength and comprising a first waveguide ( 12 ) and a second waveguide ( 14 ). The second waveguide ( 14 ) has a patterning ( 33 ) in the form of a series of patterns ( 36 ), the patterns ( 36 ) extending along a transverse direction (X) perpendicular to the longitudinal direction (Z), being parallel to each other and orthogonal to the general direction of the first waveguide ( 12 ), each pattern ( 36 ) being arranged both in the core ( 30 ) and the cladding ( 32 ) of the second waveguide ( 14 ) and having parameters influencing the evanescent wave coupling between the first waveguide ( 12 ) and the second waveguide ( 14 ), said parameters being chosen such that the coupling (C) is greater than 15%.1. An optical coupler in a vertical configuration, capable of working for a wavelength and comprising:
a first waveguide extending in the longitudinal direction and capable of propagating a first propagation mode of the light having a first effective index, a second waveguide distinct from the first waveguide, parallel to the first waveguide, having a core and a cladding and capable of propagating a second propagation mode of the light having a second effective index, the second effective index being different from the first effective index, the second waveguide having a patterning, the patterning having a period along the longitudinal direction below the ratio between the wavelength at which the optical coupler is capable of operating and the product of two by the second effective index, the patterning being in the form of a series of patterns, the patterns extending along a transverse direction perpendicular to the longitudinal direction, being parallel to each other and orthogonal to the general direction of the first waveguide, each pattern having parameters influencing the evanescent wave coupling between the first waveguide and the second waveguide, said parameters being chosen such that the coupling is greater than 15%. 2. The optical coupler according to claim 1, wherein the patterns are chosen from the group made up of:
openings made in the second waveguide, and blades. 3. The optical coupler according to claim 1, wherein the patterns have a dimension along the transverse direction larger than the dimension of the core of the second waveguide along the transverse direction. 4. The optical coupler according to claim 1, wherein the core of the second waveguide having an optical index, the second effective index is greater than the first effective index and the patterns are made from a material having an optical index below the optical index of the core of the second waveguide. 5. The optical coupler according to claim 1, wherein the patterning has a fill factor, the patterns are made from a material having an optical index, the parameters influencing the evanescent wave coupling between the first waveguide and the second waveguide being the fill factor of the patterning, the optical index of the material from which the patterns are made, and the spacing along the longitudinal direction between each pattern. 6. The optical coupler according to claim 1, wherein each pattern is arranged both in the core and the cladding of the second waveguide. 7. The optical coupler according to claim 1, wherein each waveguide includes a cladding and a core, the optical index of the core of the first waveguide being below the optical index of the cladding of the second waveguide. 8. The optical coupler according to claim 1, wherein the spacing along the longitudinal direction between the patterns is variable in the longitudinal direction. 9. The optical coupler according to claim 1, wherein the first waveguide includes a core made from a material belonging to column III of the periodic table formed with a material from column V of the periodic table and two lower and upper layers surrounding the core. 10. The optical coupler according to claim 1, wherein the core of the second waveguide has a variable dimension in the transverse direction. 11. The optical coupler according to claim 1, wherein the optical coupler includes a substrate, made from a first material, in which the second waveguide is buried, the first waveguide being arranged in contact with the substrate and formed from a material different from the first material. 12. The optical coupler according to claim 1, wherein the optical coupler includes a third waveguide distinct from the first and second waveguides and extending parallel to the first and second waveguides, the third waveguide being arranged between the first waveguide and the second waveguide and being capable of propagating a third light propagation mode having a third effective index. 13. The optical coupler according to claim 1, including a thermal insulation zone of the first waveguide in which the patterning is arranged. 14. An optical component comprising an optical coupler according claim. 15. A method for determining an optical coupler in a vertical configuration, capable of working for a wavelength and comprising:
a first waveguide extending in the longitudinal direction and capable of propagating a first propagation mode of the light having a first effective index, a second waveguide distinct from the first waveguide, parallel to the first waveguide, having a core and a cladding and capable of propagating a second propagation mode of the light having a second effective index, the second effective index being greater than the first effective index, the second waveguide (14) having a patterning, the patterning having a period along the longitudinal direction below the ratio between the wavelength at which the optical coupler is capable of operating and the product of two by the second effective index, the patterning being in the form of a series of patterns having parameters influencing the evanescent wave coupling between the first waveguide and the second waveguide, the patterns extending along a transverse direction perpendicular to the longitudinal direction, being parallel to each other and orthogonal to the general direction of the first waveguide, each pattern having parameters influencing the evanescent wave coupling between the first waveguide and the second waveguide, the method comprising a step for: choosing a desired evanescent wave coupling between the first waveguide and the second waveguide, the desired coupling being greater than or equal to 15%, modifying the parameters of the patterning to obtain the desired evanescent wave coupling between the first waveguide and the second waveguide. 16. A method for manufacturing an optical coupler according to claim 1, wherein the manufacturing method comprises steps for manufacturing waveguides and the patterning involving techniques for deposition, epitaxy, polishing, gluing and material removal by etching. | 2,800 |
11,490 | 11,490 | 15,057,622 | 2,891 | In an integrated chip stack arrangement, wherein power is provided to an upper integrated chip, including a processor core with a grid arrangement of cells connected to a power supply in a substrate by a conventional C4 solder ball array on the substrate connected through TSVs in an intermediate integrated circuit chip, it has been recognized that for maximum current efficiency and minimum electro migration the vias should not be directly coincident with the micro C4 solder balls connecting the upper chip with the intermediate chip. | 1-11. (canceled) 12. A method for making an integrated circuit package comprising:
forming a first grid array of C4 solder balls on a substrate having conductive interconnectors, said solder balls being respectively connected to the substrate interconnectors; mounting a first integrated circuit chip including TSVs (Through Silicon Vias) on said grid array of C4 solder balls, said chip having a conductive connector grid pattern coincident with said grid array of C4 solder balls wherein said integrated circuit is connected to said conductive interconnectors in said substrate; forming a second grid array of C4 solder balls on the upper surface of said integrated circuit chip connected to conductive interconnectors on said upper surface of said first integrated circuit chip; and mounting a second integrated circuit chip mounted on said second grid array of C4 solder balls, wherein said second grid array of C4 solder balls connects conductive connectors in said second chip to said conductive interconnectors on said upper surface, wherein aid C4 solder balls in said second grid array are offset so as not to horizontally coincide with TSVs in said first integrated circuit chip. 13. The method of claim 12, further including connecting a power source on said substrate to said second integrated circuit chip through said second grid array of C4 solder balls, and said TSVs in said first integrated circuit chip. 14. The method of claim 13, wherein the C4 solder balls in said second array are smaller than the C4 solder bans in said first array. 15. The method of claim 13, wherein said second integrated circuit chip includes a core area, and connection is provided through said TSVs to power said core area. 16. The method of claim 15, wherein a core area includes RAM, and said power is provided to said RAM. 17. The method of claim 15, wherein a core area includes core logic integrated circuitry, and said power is provided to said core logic integrated circuitry. 18. The method of claim 15, wherein:
said core area in said second integrated circuit chip is a rectilinear area comprising an array of rectilinear cells mounted on a coincident rectilinear cells of C4 solder balls in said second grid array, wherein each cell of C4 solder balls is coincident with a corresponding TSV in the first integrated circuit chip, and offsetting the C4 solder balls in each cell so as to not coincide with said corresponding TSV. 19. The method of claim 17 wherein:
said core area in said second integrated circuit chip is a rectilinear area comprising an array of rectilinear cells mounted on a coincident rectilinear cells of C4 solder balls in said second grid array, wherein
each cell of C4 solder balls is coincident with a central corresponding TSV in the first integrated circuit chip, and
forming the C4 solder balls in each cell in a regular column and row pattern, but with a missing central C4 ball over the TSV. 20. The method of claim 18, wherein:
said core area in said second integrated circuit chip is a rectilinear area comprising an array of rectilinear cells mounted on a coincident rectilinear cells of C4 solder balls in said second grid array, wherein each cell of C4 solder balls is coincident with a central corresponding TSV in the first integrated circuit chip, and forming the C4 solder balls in each cell are formed in a regular column and row pattern, but with the row over the TSV being offset so that no C4 solder ball coincides with said TSV. 21. The method of claim 19, wherein said TSV coincident with cell of C4 solder balls provides said conductive connection through said coincident TSV to provide power to in the core area. 22. The method of claim 18, wherein said TSV coincident with cell of C4 solder balls provides said conductive connection through said coincident TSV to provide power to logic in the core area. | In an integrated chip stack arrangement, wherein power is provided to an upper integrated chip, including a processor core with a grid arrangement of cells connected to a power supply in a substrate by a conventional C4 solder ball array on the substrate connected through TSVs in an intermediate integrated circuit chip, it has been recognized that for maximum current efficiency and minimum electro migration the vias should not be directly coincident with the micro C4 solder balls connecting the upper chip with the intermediate chip.1-11. (canceled) 12. A method for making an integrated circuit package comprising:
forming a first grid array of C4 solder balls on a substrate having conductive interconnectors, said solder balls being respectively connected to the substrate interconnectors; mounting a first integrated circuit chip including TSVs (Through Silicon Vias) on said grid array of C4 solder balls, said chip having a conductive connector grid pattern coincident with said grid array of C4 solder balls wherein said integrated circuit is connected to said conductive interconnectors in said substrate; forming a second grid array of C4 solder balls on the upper surface of said integrated circuit chip connected to conductive interconnectors on said upper surface of said first integrated circuit chip; and mounting a second integrated circuit chip mounted on said second grid array of C4 solder balls, wherein said second grid array of C4 solder balls connects conductive connectors in said second chip to said conductive interconnectors on said upper surface, wherein aid C4 solder balls in said second grid array are offset so as not to horizontally coincide with TSVs in said first integrated circuit chip. 13. The method of claim 12, further including connecting a power source on said substrate to said second integrated circuit chip through said second grid array of C4 solder balls, and said TSVs in said first integrated circuit chip. 14. The method of claim 13, wherein the C4 solder balls in said second array are smaller than the C4 solder bans in said first array. 15. The method of claim 13, wherein said second integrated circuit chip includes a core area, and connection is provided through said TSVs to power said core area. 16. The method of claim 15, wherein a core area includes RAM, and said power is provided to said RAM. 17. The method of claim 15, wherein a core area includes core logic integrated circuitry, and said power is provided to said core logic integrated circuitry. 18. The method of claim 15, wherein:
said core area in said second integrated circuit chip is a rectilinear area comprising an array of rectilinear cells mounted on a coincident rectilinear cells of C4 solder balls in said second grid array, wherein each cell of C4 solder balls is coincident with a corresponding TSV in the first integrated circuit chip, and offsetting the C4 solder balls in each cell so as to not coincide with said corresponding TSV. 19. The method of claim 17 wherein:
said core area in said second integrated circuit chip is a rectilinear area comprising an array of rectilinear cells mounted on a coincident rectilinear cells of C4 solder balls in said second grid array, wherein
each cell of C4 solder balls is coincident with a central corresponding TSV in the first integrated circuit chip, and
forming the C4 solder balls in each cell in a regular column and row pattern, but with a missing central C4 ball over the TSV. 20. The method of claim 18, wherein:
said core area in said second integrated circuit chip is a rectilinear area comprising an array of rectilinear cells mounted on a coincident rectilinear cells of C4 solder balls in said second grid array, wherein each cell of C4 solder balls is coincident with a central corresponding TSV in the first integrated circuit chip, and forming the C4 solder balls in each cell are formed in a regular column and row pattern, but with the row over the TSV being offset so that no C4 solder ball coincides with said TSV. 21. The method of claim 19, wherein said TSV coincident with cell of C4 solder balls provides said conductive connection through said coincident TSV to provide power to in the core area. 22. The method of claim 18, wherein said TSV coincident with cell of C4 solder balls provides said conductive connection through said coincident TSV to provide power to logic in the core area. | 2,800 |
11,491 | 11,491 | 14,665,750 | 2,834 | Certain embodiments provide systems and methods for cooling a drive end bearing. The system may include an alternator including a drive end bearing, a drive end fan and a front housing face. The drive end fan may include a shaft aperture and auxiliary air flow inlet apertures positioned circumferentially around the shaft aperture. The front housing face may include auxiliary fins coupled to the drive end bearing. The auxiliary fins may protrude from the front housing face. The auxiliary fins may be arrayed axially on the front housing face. In various embodiments, the drive end fan is rotated to draw air through the auxiliary air flow inlet apertures and adjacent to at least a portion of auxiliary fins of the front housing face. The at least a portion of the auxiliary fins transfers heat from the drive end bearing to the air. | 1-20. (canceled) 21. An alternator comprising:
a drive end; a rear end opposite the drive end; a drive end bearing; a drive end fan at the drive end, the drive end fan comprising a shaft aperture and a plurality of auxiliary air flow inlet apertures positioned circumferentially around the shaft aperture; and a front housing face adjacent to the drive end fan, the front housing face comprising a plurality of auxiliary fins coupled to the drive end bearing, the plurality of auxiliary fins protruding from the front housing face, and the plurality of auxiliary fins arrayed axially on the front housing face. 22. The alternator according to claim 21, wherein the drive end fan is rotated to draw air into the alternator via the plurality of auxiliary air flow inlet apertures and adjacent to at least a portion of the plurality of auxiliary fins of the front housing face. 23. The alternator according to claim 22, wherein the air drawn into the alternator via the plurality of auxiliary air flow inlet apertures is ambient temperature air. 24. The alternator according to claim 23, wherein the at least a portion of the plurality of auxiliary fins transfers heat from the drive end bearing to the air. 25. The alternator according to claim 21, wherein each of the plurality of auxiliary air flow inlet apertures is substantially a same size. 26. The alternator according to claim 21, wherein each of the plurality of auxiliary air flow inlet apertures is evenly spaced about the shaft aperture. 27. The alternator according to claim 21, wherein the plurality of auxiliary air flow inlet apertures are at least one of eight auxiliary air flow inlet apertures and sixteen auxiliary air flow inlet apertures. 28. The alternator according to claim 22, wherein the air drawn into the alternator via the plurality of auxiliary air flow inlet apertures and adjacent to the at least a portion of the plurality of auxiliary fins of the front housing face is expelled from the alternator by the drive end fan. 29. The alternator according to claim 28, wherein air from the rear end is drawn through the alternator and joins the air drawn into the alternator via the plurality of auxiliary air flow inlet apertures prior to being expelled from the alternator by the drive end fan. 30. The alternator according to claim 21, wherein the drive end fan comprises a front face and a rear face, the front face comprising a plurality of fan face slots positioned circumferentially around the shaft aperture, wherein each of the plurality of the auxiliary air flow inlet apertures is positioned within a corresponding one of the plurality of fan face slots. 31. The alternator according to claim 21, wherein the drive end fan comprises a front face and a rear face, the front face comprising a fan face depression positioned around the shaft aperture, wherein the plurality of auxiliary air flow inlet apertures are positioned within the fan face depression. 32. The alternator according to claim 21, wherein the drive end fan comprises a front face and a rear face opposite the front face, the rear face comprising a plurality of fan blades, and the rear face facing the front housing face. 33. A method for cooling a drive end bearing, the method comprising:
rotating a drive end fan at a drive end of an alternator; drawing air into the alternator via a plurality of auxiliary air flow inlet apertures of the drive end fan; pulling the air across a plurality of auxiliary fins arrayed axially on a front housing face adjacent the drive end fan to transfer drive end bearing heat to the air; and expelling the drive end bearing-heated air from the alternator by the drive end fan. 34. The method according to claim 33, wherein the air drawn into the alternator via the plurality of auxiliary air flow inlet apertures is ambient temperature. 35. The method according to claim 33, wherein the plurality of auxiliary air flow inlet apertures are positioned circumferentially around a shaft aperture of the drive end fan. 36. The method according to claim 35, wherein each of the plurality of auxiliary air flow inlet apertures is substantially a same size. 37. The method according to claim 35, wherein each of the plurality of auxiliary air flow inlet apertures is evenly spaced about the shaft aperture. 38. The method according to claim 33, comprising drawing air from a rear end of the alternator through the alternator, wherein the air drawn from the rear end of the alternator and through the alternator joins the air drawn into the alternator via the plurality of auxiliary air flow inlet apertures prior to being expelled from the alternator by the drive end fan, wherein the rear end is opposite the drive end of the alternator. 39. The method according to claim 33, comprising drawing the air behind a pulley prior to drawing the air into the alternator via the plurality of auxiliary air flow inlet apertures of the drive end fan. 40. The method according to claim 39, wherein the air drawn behind the pulley is drawn through a plurality of fan face slots positioned circumferentially around a shaft aperture of the drive end fan, wherein each of the plurality of the auxiliary air flow inlet apertures is positioned within a corresponding one of the plurality of fan face slots. 41. The method according to claim 39, wherein the air drawn behind the pulley is drawn through a fan face depression positioned around a shaft aperture of the drive end fan, wherein the plurality of auxiliary air flow inlet apertures are positioned within the fan face depression. 42. The method according to claim 33, wherein the drive end fan comprises a front face and a rear face opposite the front face, the rear face comprising a plurality of fan blades, and the rear face facing the front housing face. | Certain embodiments provide systems and methods for cooling a drive end bearing. The system may include an alternator including a drive end bearing, a drive end fan and a front housing face. The drive end fan may include a shaft aperture and auxiliary air flow inlet apertures positioned circumferentially around the shaft aperture. The front housing face may include auxiliary fins coupled to the drive end bearing. The auxiliary fins may protrude from the front housing face. The auxiliary fins may be arrayed axially on the front housing face. In various embodiments, the drive end fan is rotated to draw air through the auxiliary air flow inlet apertures and adjacent to at least a portion of auxiliary fins of the front housing face. The at least a portion of the auxiliary fins transfers heat from the drive end bearing to the air.1-20. (canceled) 21. An alternator comprising:
a drive end; a rear end opposite the drive end; a drive end bearing; a drive end fan at the drive end, the drive end fan comprising a shaft aperture and a plurality of auxiliary air flow inlet apertures positioned circumferentially around the shaft aperture; and a front housing face adjacent to the drive end fan, the front housing face comprising a plurality of auxiliary fins coupled to the drive end bearing, the plurality of auxiliary fins protruding from the front housing face, and the plurality of auxiliary fins arrayed axially on the front housing face. 22. The alternator according to claim 21, wherein the drive end fan is rotated to draw air into the alternator via the plurality of auxiliary air flow inlet apertures and adjacent to at least a portion of the plurality of auxiliary fins of the front housing face. 23. The alternator according to claim 22, wherein the air drawn into the alternator via the plurality of auxiliary air flow inlet apertures is ambient temperature air. 24. The alternator according to claim 23, wherein the at least a portion of the plurality of auxiliary fins transfers heat from the drive end bearing to the air. 25. The alternator according to claim 21, wherein each of the plurality of auxiliary air flow inlet apertures is substantially a same size. 26. The alternator according to claim 21, wherein each of the plurality of auxiliary air flow inlet apertures is evenly spaced about the shaft aperture. 27. The alternator according to claim 21, wherein the plurality of auxiliary air flow inlet apertures are at least one of eight auxiliary air flow inlet apertures and sixteen auxiliary air flow inlet apertures. 28. The alternator according to claim 22, wherein the air drawn into the alternator via the plurality of auxiliary air flow inlet apertures and adjacent to the at least a portion of the plurality of auxiliary fins of the front housing face is expelled from the alternator by the drive end fan. 29. The alternator according to claim 28, wherein air from the rear end is drawn through the alternator and joins the air drawn into the alternator via the plurality of auxiliary air flow inlet apertures prior to being expelled from the alternator by the drive end fan. 30. The alternator according to claim 21, wherein the drive end fan comprises a front face and a rear face, the front face comprising a plurality of fan face slots positioned circumferentially around the shaft aperture, wherein each of the plurality of the auxiliary air flow inlet apertures is positioned within a corresponding one of the plurality of fan face slots. 31. The alternator according to claim 21, wherein the drive end fan comprises a front face and a rear face, the front face comprising a fan face depression positioned around the shaft aperture, wherein the plurality of auxiliary air flow inlet apertures are positioned within the fan face depression. 32. The alternator according to claim 21, wherein the drive end fan comprises a front face and a rear face opposite the front face, the rear face comprising a plurality of fan blades, and the rear face facing the front housing face. 33. A method for cooling a drive end bearing, the method comprising:
rotating a drive end fan at a drive end of an alternator; drawing air into the alternator via a plurality of auxiliary air flow inlet apertures of the drive end fan; pulling the air across a plurality of auxiliary fins arrayed axially on a front housing face adjacent the drive end fan to transfer drive end bearing heat to the air; and expelling the drive end bearing-heated air from the alternator by the drive end fan. 34. The method according to claim 33, wherein the air drawn into the alternator via the plurality of auxiliary air flow inlet apertures is ambient temperature. 35. The method according to claim 33, wherein the plurality of auxiliary air flow inlet apertures are positioned circumferentially around a shaft aperture of the drive end fan. 36. The method according to claim 35, wherein each of the plurality of auxiliary air flow inlet apertures is substantially a same size. 37. The method according to claim 35, wherein each of the plurality of auxiliary air flow inlet apertures is evenly spaced about the shaft aperture. 38. The method according to claim 33, comprising drawing air from a rear end of the alternator through the alternator, wherein the air drawn from the rear end of the alternator and through the alternator joins the air drawn into the alternator via the plurality of auxiliary air flow inlet apertures prior to being expelled from the alternator by the drive end fan, wherein the rear end is opposite the drive end of the alternator. 39. The method according to claim 33, comprising drawing the air behind a pulley prior to drawing the air into the alternator via the plurality of auxiliary air flow inlet apertures of the drive end fan. 40. The method according to claim 39, wherein the air drawn behind the pulley is drawn through a plurality of fan face slots positioned circumferentially around a shaft aperture of the drive end fan, wherein each of the plurality of the auxiliary air flow inlet apertures is positioned within a corresponding one of the plurality of fan face slots. 41. The method according to claim 39, wherein the air drawn behind the pulley is drawn through a fan face depression positioned around a shaft aperture of the drive end fan, wherein the plurality of auxiliary air flow inlet apertures are positioned within the fan face depression. 42. The method according to claim 33, wherein the drive end fan comprises a front face and a rear face opposite the front face, the rear face comprising a plurality of fan blades, and the rear face facing the front housing face. | 2,800 |
11,492 | 11,492 | 15,196,376 | 2,872 | Disclosed is an optical scope including an objective lens, an eyepiece lens, and a reticle, wherein a field lens having negative power is disposed in at least one of a front and a back of the reticle disposed on an image formation surface of the objective lens to increase eye-relief. | 1-20. (canceled) 21. An optical scope, comprising:
an objective lens; an eyepiece lens; a reticle disposed between the objective lens and the eye piece; an erecting optical system that erects an image and is disposed between the objective lens and the reticle; and a field lens having negative power disposed between the eyepiece lens and the erecting optical system, wherein a straight imaginary line is defined from a center of the objective lens to a center of the eyepiece lens, the reticle, the erecting optical system, and the field lens are arranged such that the imaginary line intersects each of the reticle, the erecting optical system, and the field lens respectively, and a surface of the field lens towards the reticle is flat. 22. The optical scope according to claim 21, wherein the flat surface of the field lens faces the reticle. 23. The optical scope according to claim 21, wherein the flat surface of the field lens is adjacent to the reticle. 24. The optical scope according to claim 23, wherein the flat surface of the field lens is in contact with the reticle. 25. The optical scope according to claim 24, wherein the reticle is formed on the flat surface of the field lens. 26. The optical scope according to claim 21, wherein the flat surface of the field lens is disposed towards the objective lens. 27. The optical scope according to claim 21, wherein the erecting optical system comprises an erecting prism. 28. The optical scope according to claim 21, wherein the objective lens, the field lens, the reticle and the eyepiece lens are arranged in sequence. 29. The optical scope according to claim 21, wherein the objective lens, the reticle, the field lens, and the eyepiece lens are arranged in sequence. 30. The optical scope according to claim 21, further comprising a second field lens having negative power, wherein the objective lens, the field lens, the reticle, the second field lens, and the eyepiece lens are arranged in sequence. 31. The optical scope according to claim 21, wherein the objective lens, the second field lens, the reticle, the field lens, and the eyepiece lens are arranged in sequence. 32. The optical scope according to claim 21, wherein the objective lens includes a doublet lens. 33. The optical scope according to claim 21, wherein the eyepiece lens includes a lens group. 34. The optical scope according to claim 33, wherein the lens group of the eyepiece lens includes a doublet lens. 35. The optical scope according to claim 33, wherein the lens group of the eyepiece lens includes a meniscus lens. 36. The optical scope according to claim 35, wherein the meniscus lens is disposed at a side of the lens group towards the objective lens. 37. The optical scope according to claim 21, wherein the field lens is a single negative power lens. 38. The optical scope according to claim 21, wherein the reticle is disposed between the field lens and the objective lens. | Disclosed is an optical scope including an objective lens, an eyepiece lens, and a reticle, wherein a field lens having negative power is disposed in at least one of a front and a back of the reticle disposed on an image formation surface of the objective lens to increase eye-relief.1-20. (canceled) 21. An optical scope, comprising:
an objective lens; an eyepiece lens; a reticle disposed between the objective lens and the eye piece; an erecting optical system that erects an image and is disposed between the objective lens and the reticle; and a field lens having negative power disposed between the eyepiece lens and the erecting optical system, wherein a straight imaginary line is defined from a center of the objective lens to a center of the eyepiece lens, the reticle, the erecting optical system, and the field lens are arranged such that the imaginary line intersects each of the reticle, the erecting optical system, and the field lens respectively, and a surface of the field lens towards the reticle is flat. 22. The optical scope according to claim 21, wherein the flat surface of the field lens faces the reticle. 23. The optical scope according to claim 21, wherein the flat surface of the field lens is adjacent to the reticle. 24. The optical scope according to claim 23, wherein the flat surface of the field lens is in contact with the reticle. 25. The optical scope according to claim 24, wherein the reticle is formed on the flat surface of the field lens. 26. The optical scope according to claim 21, wherein the flat surface of the field lens is disposed towards the objective lens. 27. The optical scope according to claim 21, wherein the erecting optical system comprises an erecting prism. 28. The optical scope according to claim 21, wherein the objective lens, the field lens, the reticle and the eyepiece lens are arranged in sequence. 29. The optical scope according to claim 21, wherein the objective lens, the reticle, the field lens, and the eyepiece lens are arranged in sequence. 30. The optical scope according to claim 21, further comprising a second field lens having negative power, wherein the objective lens, the field lens, the reticle, the second field lens, and the eyepiece lens are arranged in sequence. 31. The optical scope according to claim 21, wherein the objective lens, the second field lens, the reticle, the field lens, and the eyepiece lens are arranged in sequence. 32. The optical scope according to claim 21, wherein the objective lens includes a doublet lens. 33. The optical scope according to claim 21, wherein the eyepiece lens includes a lens group. 34. The optical scope according to claim 33, wherein the lens group of the eyepiece lens includes a doublet lens. 35. The optical scope according to claim 33, wherein the lens group of the eyepiece lens includes a meniscus lens. 36. The optical scope according to claim 35, wherein the meniscus lens is disposed at a side of the lens group towards the objective lens. 37. The optical scope according to claim 21, wherein the field lens is a single negative power lens. 38. The optical scope according to claim 21, wherein the reticle is disposed between the field lens and the objective lens. | 2,800 |
11,493 | 11,493 | 13,642,562 | 2,856 | The present invention provides an instrument and a method for examining the condition of column-shaped or cylindrical sections of objects. It comprises a drive device having a drill chuck, which holds a drill needle that can be driven by the drive device, and a guiding device for guided insertion of the drill needle into the object to be examined. The guiding device is a telescopic tube that comprises a shorter inner tube section that is arranged in a longer outer tube section such that it is axially displaceable, and has a longitudinally arranged measuring scale on its outer circumference. The telescopic tube is placed on the drive device in non-rotating manner via the inner tube section. The inner and the outer tube sections have guiding means for centrally-axially guiding the drill needle, which extends in central-axial direction from the drill chuck through the inner tube section and through the outer tube section. When the inner tube section is being inserted into the outer tube section, the drill needle can be driven into the object to be examined in a manner guided by the guiding means. | 1. Hand-held testing instrument for examining the condition of column-shaped or cylindrical sections of objects, comprising
a drive means having a drill chuck, which holds a drill needle that can be driven by the drive means, a guiding device for guided insertion of the drill needle into the object to be examined, wherein the guiding device is a telescopic tube, wherein said telescopic tube comprises a shorter inner tube section which is arranged in a longer outer tube section such that it is axially displaceable and has a longitudinally arranged measuring scale on its outer circumference, wherein said telescopic tube is placed on the drive means in non-rotating manner via the inner tube section, wherein the inner and the outer tube sections comprise a guiding means for centrally-axially guiding the drill needle, wherein the drill needle extends in central-axial direction from the drill chuck through the inner tube section and through the outer tube section, wherein the drill needle can be driven into the object to be examined in a manner guided by the guiding means while the inner tube section is being inserted into the outer tube section. 2. Hand-held testing instrument according to claim 1, wherein the guiding means are selected from the group consisting of guide bushings situated in the inner tube section or the outer tube section, sleeves, or sleeves having a spiral internal thread,
wherein the spiral internal thread has a shape that corresponds with the shape of an external thread situated on the drill needle. 3. Hand-held testing instrument according to claim 1, further comprising a sleeve that is connected to the inner tube section which is imposed in a non-rotating manner on the drill chuck of the drive device. 4. Hand-held testing instrument according to claim 1, further comprising a handle sleeve around an external circumference of the outer tube section which is arranged to guide and support the handling of the telescopic tube. 5. Hand-held testing instrument according to claim 1 wherein the longitudinally arranged measuring scale comprises a scale in units of millimeters or centimeters for reading an inserted length of the inner tube section in the outer tube section. 6. Hand-held testing instrument according to claim 1, wherein the drill needle is fixed in place in the drill chuck by means of a clamping screw. 7. Method for examining the condition of column-shaped or cylindrical sections of objects using a hand-held testing instrument according to claim 1, comprising the steps of:
providing the telescopic tube, wherein the shorter inner tube section is in a pulled-out state; placing the drill needle, which projects from the outer tube section in a manner guided by the guiding means, on the object to be examined; actuating the drive device and driving the drill needle in rotary manner and driving the drill needle into the object against a first resistance given by the object; while axially displacing the drive device by hand in the direction of the object and thus inserting the inner tube section into the outer tube section; reading an inserted length of the inner tube section in the outer tube section as soon as the resistance provided by the object changes abruptly. 8. Hand-held testing instrument according to claim or 2, further comprising a sleeve that is connected to the inner tube section which is imposed in a non-rotating manner on the drill chuck of the drive device. 9. Hand-held testing instrument according to claim 2, further comprising a handle sleeve around an external circumference of the outer tube section which is arranged to guide and support the handling of the telescopic tube. 10. Hand-held testing instrument according to claim 2, wherein the longitudinally arranged measuring scale comprises a scale in units of millimeters or centimeters for reading an inserted length of the inner tube section in the outer tube section. 11. Hand-held testing instrument according to claim 2, wherein the drill needle is fixed in place in the drill chuck by means of a clamping screw. 12. Method for examining the condition of column-shaped or cylindrical sections of objects using a hand-held testing instrument according to claim 2, comprising the steps of:
providing the telescopic tube,
wherein the shorter inner tube section is in a pulled-out state;
placing the drill needle, which projects from the outer tube section in a manner guided by the guiding means, on the object to be examined; actuating the drive device and driving the drill needle in rotary manner and driving the drill needle into the object against a first resistance given by the object; axially displacing the drive device by hand in the direction of the object and thus inserting the inner tube section into the outer tube section; reading an inserted length of the inner tube section in the outer tube section as soon as the resistance provided by the object changes abruptly. 13. Hand-held testing instrument according to claim 9, further comprising a handle sleeve around an external circumference of the outer tube section which is arranged to guide and support the handling of the telescopic tube. 14. Hand-held testing instrument according to claim 9, wherein the longitudinally arranged measuring scale comprises a scale in units of millimeters or centimeters for reading an inserted length of the inner tube section in the outer tube section. 15. Hand-held testing instrument according to claim 9, wherein the drill needle is fixed in place in the drill chuck by means of a clamping screw. 16. Method for examining the condition of column-shaped or cylindrical sections of objects using a hand-held testing instrument according to claim 9, comprising the steps of:
providing the telescopic tube,
wherein the shorter inner tube section is in a pulled-out state;
placing the drill needle, which projects from the outer tube section in a manner guided by the guiding means, on the object to be examined; actuating the drive device and driving the drill needle in rotary manner and driving the drill needle into the object against a first resistance given by the object; axially displacing the drive device by hand in the direction of the object and thus inserting the inner tube section into the outer tube section;
reading an inserted length of the inner tube section in the outer tube section as soon as the resistance provided by the object changes abruptly. 17. Hand-held testing instrument according to claim 13, wherein the longitudinally arranged measuring scale comprises a scale in units of millimeters or centimeters for reading an inserted length of the inner tube section in the outer tube section. 18. Hand-held testing instrument according to claim 13, wherein the drill needle is fixed in place in the drill chuck by means of a clamping screw. 19. Method for examining the condition of column-shaped or cylindrical sections of objects using a hand-held testing instrument according to claim 13, comprising the steps of:
providing the telescopic tube,
wherein the shorter inner tube section is in a pulled-out state;
placing the drill needle, which projects from the outer tube section in a manner guided by the guiding means, on the object to be examined; actuating the drive device and driving the drill needle in rotary manner and driving the drill needle into the object against a first resistance given by the object; axially displacing the drive device by hand in the direction of the object and thus inserting the inner tube section into the outer tube section;
reading an inserted length of the inner tube section in the outer tube section as soon as the resistance provided by the object changes abruptly. | The present invention provides an instrument and a method for examining the condition of column-shaped or cylindrical sections of objects. It comprises a drive device having a drill chuck, which holds a drill needle that can be driven by the drive device, and a guiding device for guided insertion of the drill needle into the object to be examined. The guiding device is a telescopic tube that comprises a shorter inner tube section that is arranged in a longer outer tube section such that it is axially displaceable, and has a longitudinally arranged measuring scale on its outer circumference. The telescopic tube is placed on the drive device in non-rotating manner via the inner tube section. The inner and the outer tube sections have guiding means for centrally-axially guiding the drill needle, which extends in central-axial direction from the drill chuck through the inner tube section and through the outer tube section. When the inner tube section is being inserted into the outer tube section, the drill needle can be driven into the object to be examined in a manner guided by the guiding means.1. Hand-held testing instrument for examining the condition of column-shaped or cylindrical sections of objects, comprising
a drive means having a drill chuck, which holds a drill needle that can be driven by the drive means, a guiding device for guided insertion of the drill needle into the object to be examined, wherein the guiding device is a telescopic tube, wherein said telescopic tube comprises a shorter inner tube section which is arranged in a longer outer tube section such that it is axially displaceable and has a longitudinally arranged measuring scale on its outer circumference, wherein said telescopic tube is placed on the drive means in non-rotating manner via the inner tube section, wherein the inner and the outer tube sections comprise a guiding means for centrally-axially guiding the drill needle, wherein the drill needle extends in central-axial direction from the drill chuck through the inner tube section and through the outer tube section, wherein the drill needle can be driven into the object to be examined in a manner guided by the guiding means while the inner tube section is being inserted into the outer tube section. 2. Hand-held testing instrument according to claim 1, wherein the guiding means are selected from the group consisting of guide bushings situated in the inner tube section or the outer tube section, sleeves, or sleeves having a spiral internal thread,
wherein the spiral internal thread has a shape that corresponds with the shape of an external thread situated on the drill needle. 3. Hand-held testing instrument according to claim 1, further comprising a sleeve that is connected to the inner tube section which is imposed in a non-rotating manner on the drill chuck of the drive device. 4. Hand-held testing instrument according to claim 1, further comprising a handle sleeve around an external circumference of the outer tube section which is arranged to guide and support the handling of the telescopic tube. 5. Hand-held testing instrument according to claim 1 wherein the longitudinally arranged measuring scale comprises a scale in units of millimeters or centimeters for reading an inserted length of the inner tube section in the outer tube section. 6. Hand-held testing instrument according to claim 1, wherein the drill needle is fixed in place in the drill chuck by means of a clamping screw. 7. Method for examining the condition of column-shaped or cylindrical sections of objects using a hand-held testing instrument according to claim 1, comprising the steps of:
providing the telescopic tube, wherein the shorter inner tube section is in a pulled-out state; placing the drill needle, which projects from the outer tube section in a manner guided by the guiding means, on the object to be examined; actuating the drive device and driving the drill needle in rotary manner and driving the drill needle into the object against a first resistance given by the object; while axially displacing the drive device by hand in the direction of the object and thus inserting the inner tube section into the outer tube section; reading an inserted length of the inner tube section in the outer tube section as soon as the resistance provided by the object changes abruptly. 8. Hand-held testing instrument according to claim or 2, further comprising a sleeve that is connected to the inner tube section which is imposed in a non-rotating manner on the drill chuck of the drive device. 9. Hand-held testing instrument according to claim 2, further comprising a handle sleeve around an external circumference of the outer tube section which is arranged to guide and support the handling of the telescopic tube. 10. Hand-held testing instrument according to claim 2, wherein the longitudinally arranged measuring scale comprises a scale in units of millimeters or centimeters for reading an inserted length of the inner tube section in the outer tube section. 11. Hand-held testing instrument according to claim 2, wherein the drill needle is fixed in place in the drill chuck by means of a clamping screw. 12. Method for examining the condition of column-shaped or cylindrical sections of objects using a hand-held testing instrument according to claim 2, comprising the steps of:
providing the telescopic tube,
wherein the shorter inner tube section is in a pulled-out state;
placing the drill needle, which projects from the outer tube section in a manner guided by the guiding means, on the object to be examined; actuating the drive device and driving the drill needle in rotary manner and driving the drill needle into the object against a first resistance given by the object; axially displacing the drive device by hand in the direction of the object and thus inserting the inner tube section into the outer tube section; reading an inserted length of the inner tube section in the outer tube section as soon as the resistance provided by the object changes abruptly. 13. Hand-held testing instrument according to claim 9, further comprising a handle sleeve around an external circumference of the outer tube section which is arranged to guide and support the handling of the telescopic tube. 14. Hand-held testing instrument according to claim 9, wherein the longitudinally arranged measuring scale comprises a scale in units of millimeters or centimeters for reading an inserted length of the inner tube section in the outer tube section. 15. Hand-held testing instrument according to claim 9, wherein the drill needle is fixed in place in the drill chuck by means of a clamping screw. 16. Method for examining the condition of column-shaped or cylindrical sections of objects using a hand-held testing instrument according to claim 9, comprising the steps of:
providing the telescopic tube,
wherein the shorter inner tube section is in a pulled-out state;
placing the drill needle, which projects from the outer tube section in a manner guided by the guiding means, on the object to be examined; actuating the drive device and driving the drill needle in rotary manner and driving the drill needle into the object against a first resistance given by the object; axially displacing the drive device by hand in the direction of the object and thus inserting the inner tube section into the outer tube section;
reading an inserted length of the inner tube section in the outer tube section as soon as the resistance provided by the object changes abruptly. 17. Hand-held testing instrument according to claim 13, wherein the longitudinally arranged measuring scale comprises a scale in units of millimeters or centimeters for reading an inserted length of the inner tube section in the outer tube section. 18. Hand-held testing instrument according to claim 13, wherein the drill needle is fixed in place in the drill chuck by means of a clamping screw. 19. Method for examining the condition of column-shaped or cylindrical sections of objects using a hand-held testing instrument according to claim 13, comprising the steps of:
providing the telescopic tube,
wherein the shorter inner tube section is in a pulled-out state;
placing the drill needle, which projects from the outer tube section in a manner guided by the guiding means, on the object to be examined; actuating the drive device and driving the drill needle in rotary manner and driving the drill needle into the object against a first resistance given by the object; axially displacing the drive device by hand in the direction of the object and thus inserting the inner tube section into the outer tube section;
reading an inserted length of the inner tube section in the outer tube section as soon as the resistance provided by the object changes abruptly. | 2,800 |
11,494 | 11,494 | 13,897,115 | 2,865 | An open circuit voltage estimation device for estimating an open circuit voltage of an electric storage device includes a voltage measurement portion and a controller. The voltage measurement portion measures terminal voltages of the electric storage device. The controller is configured to: control the voltage measurement portion to measure the terminal voltages; store the terminal voltages in association with elapsed time since charge or discharge completion time; calculate a variation in terminal voltage per unit time at predetermined elapsed time since the charge or the discharge of the electric storage device is complete based on the terminal voltages measured by the voltage measurement portion; and estimate the open circuit voltage based on the predetermined elapsed time, the voltage at the predetermined elapsed time, and the variation. | 1. An open circuit voltage estimation device for estimating an open circuit voltage of an electric storage device, the open circuit voltage estimation device comprising:
a voltage measurement portion configured to measure terminal voltages of the electric storage device; and a controller configured to:
control the voltage measurement portion to measure the terminal voltages of the electric storage device after charge or discharge of the electric storage device is complete;
store the terminal voltages in association with elapsed time since charge or discharge completion time at which charge or discharge of the electric storage device is complete;
calculate a variation in terminal voltage per unit time at predetermined elapsed time since the charge or the discharge of the electric storage device is complete based on the terminal voltages measured by the voltage measurement portion; and
estimate the open circuit voltage based on the predetermined elapsed time, the voltage at the predetermined elapsed time, and the variation. 2. The open circuit voltage estimation device according to claim 1, wherein the controller is further configured to:
calculate the variation in terminal voltage per unit time by calculating an approximate equation of an approximate line of the terminal voltages, the approximate line being at the predetermined elapsed time; and estimate the open circuit voltage:
by calculating calculation time based on the predetermined elapsed time and a coefficient defined according to an active material of the electric storage device and the predetermined elapsed time; and
by defining a value calculated substituting the calculation time in the approximate equation as an estimated open circuit voltage. 3. The open circuit voltage estimation device according to claim 2, wherein the controller is further configured to use a common logarithm of the predetermined elapsed time for calculating the approximate equation. 4. The open circuit voltage estimation device according to claim 2, wherein the controller is further configured to:
detect a peak at which a gradient of the terminal voltages is the largest; and use elapsed time from when the charge or the discharge of the electric storage device is complete to when the terminal voltage reaches the peak as the predetermined elapsed time. 5. The open circuit voltage estimation device according to claim 2, further comprising a temperature measurement portion configured to measure a temperature of the electric storage device, wherein
the coefficient is defined based on a temperature of the electric storage device, and the controller is further configured to determine the coefficient based on the temperature of the electric storage device at the predetermined elapsed time for calculating the calculation time. 6. The open circuit voltage estimation device according to claim 2, wherein the controller is further configured to control the voltage measurement portion to terminate the measurement of terminal voltages when the elapsed time has passed a predefined reference time. 7. The open circuit voltage estimation device according to claim 2, further comprising a current detection portion configured to detect at least one of charge and discharge currents of the electric storage device, wherein the controller is further configured to detect the charge or discharge completion time according to a detection result of the current detection portion for controlling the voltage measurement portion. 8. A condition estimation device comprising:
the open circuit voltage estimation device according to claim 1; and a memory configured to store information on correlation between open circuit voltage and internal condition of the electric storage device, wherein the controller is further configured to estimate an internal condition of the electric storage device based on the estimated open circuit voltage and the information on the correlation stored in the memory. 9. A method of estimating an internal condition of an electric storage device comprising:
measuring terminal voltages of the electric storage device after charge or discharge of the electric storage device is complete; storing the terminal voltages in association with elapsed time since charge or discharge completion time at which charge or discharge of the electric storage device is complete; calculating a variation in terminal voltages per unit time at predetermined elapsed time since the charge or the discharge of the electric storage device is complete based on the terminal voltages measured by the voltage measurement portion; and estimating the open circuit voltage based on the predetermined elapsed time, the voltage at the predetermined elapsed time, and the variation. 10. The method according to claim 9, wherein
the calculating a variation in terminal voltages per unit time includes calculating an approximate equation of an approximate line of the terminal voltages, the approximate line being at the predetermined elapsed time; and the estimating the open circuit voltage includes:
calculating calculation time based on the predetermined elapsed time and coefficient defined according to an active material of the electric storage device and the predetermined elapsed time; and
defining a value calculated substituting the calculation time in the approximate equation as an estimated open circuit voltage. 11. The method according to claim 9, wherein the calculating an approximate equation includes using a common logarithm of the elapsed time for calculating the approximate equation. 12. The method according to claim 10, further comprising detecting a peak at which a gradient of the terminal voltages is the largest, wherein the calculating an approximate equation includes using elapsed time from when the charge or the discharge of the electric storage device is complete to when the terminal voltage reaches the peak as the predetermined elapsed time. 13. The method according to claim 10, wherein
the coefficient is defined based on a temperature of the electric storage device, and the calculating calculation time includes determining the coefficient based on the temperature of the electric storage device at the predetermined elapsed time for calculating the calculation time. 14. The method according to claim 10, wherein the measuring terminal voltages includes terminating the measurement of terminal voltages when the elapsed time has passed a predefined reference time. 15. The method according to claim 10, wherein the measuring terminal voltages includes detecting the charge or discharge completion time according to a detection result of detection for detecting charge or discharge current of the electric storage device. | An open circuit voltage estimation device for estimating an open circuit voltage of an electric storage device includes a voltage measurement portion and a controller. The voltage measurement portion measures terminal voltages of the electric storage device. The controller is configured to: control the voltage measurement portion to measure the terminal voltages; store the terminal voltages in association with elapsed time since charge or discharge completion time; calculate a variation in terminal voltage per unit time at predetermined elapsed time since the charge or the discharge of the electric storage device is complete based on the terminal voltages measured by the voltage measurement portion; and estimate the open circuit voltage based on the predetermined elapsed time, the voltage at the predetermined elapsed time, and the variation.1. An open circuit voltage estimation device for estimating an open circuit voltage of an electric storage device, the open circuit voltage estimation device comprising:
a voltage measurement portion configured to measure terminal voltages of the electric storage device; and a controller configured to:
control the voltage measurement portion to measure the terminal voltages of the electric storage device after charge or discharge of the electric storage device is complete;
store the terminal voltages in association with elapsed time since charge or discharge completion time at which charge or discharge of the electric storage device is complete;
calculate a variation in terminal voltage per unit time at predetermined elapsed time since the charge or the discharge of the electric storage device is complete based on the terminal voltages measured by the voltage measurement portion; and
estimate the open circuit voltage based on the predetermined elapsed time, the voltage at the predetermined elapsed time, and the variation. 2. The open circuit voltage estimation device according to claim 1, wherein the controller is further configured to:
calculate the variation in terminal voltage per unit time by calculating an approximate equation of an approximate line of the terminal voltages, the approximate line being at the predetermined elapsed time; and estimate the open circuit voltage:
by calculating calculation time based on the predetermined elapsed time and a coefficient defined according to an active material of the electric storage device and the predetermined elapsed time; and
by defining a value calculated substituting the calculation time in the approximate equation as an estimated open circuit voltage. 3. The open circuit voltage estimation device according to claim 2, wherein the controller is further configured to use a common logarithm of the predetermined elapsed time for calculating the approximate equation. 4. The open circuit voltage estimation device according to claim 2, wherein the controller is further configured to:
detect a peak at which a gradient of the terminal voltages is the largest; and use elapsed time from when the charge or the discharge of the electric storage device is complete to when the terminal voltage reaches the peak as the predetermined elapsed time. 5. The open circuit voltage estimation device according to claim 2, further comprising a temperature measurement portion configured to measure a temperature of the electric storage device, wherein
the coefficient is defined based on a temperature of the electric storage device, and the controller is further configured to determine the coefficient based on the temperature of the electric storage device at the predetermined elapsed time for calculating the calculation time. 6. The open circuit voltage estimation device according to claim 2, wherein the controller is further configured to control the voltage measurement portion to terminate the measurement of terminal voltages when the elapsed time has passed a predefined reference time. 7. The open circuit voltage estimation device according to claim 2, further comprising a current detection portion configured to detect at least one of charge and discharge currents of the electric storage device, wherein the controller is further configured to detect the charge or discharge completion time according to a detection result of the current detection portion for controlling the voltage measurement portion. 8. A condition estimation device comprising:
the open circuit voltage estimation device according to claim 1; and a memory configured to store information on correlation between open circuit voltage and internal condition of the electric storage device, wherein the controller is further configured to estimate an internal condition of the electric storage device based on the estimated open circuit voltage and the information on the correlation stored in the memory. 9. A method of estimating an internal condition of an electric storage device comprising:
measuring terminal voltages of the electric storage device after charge or discharge of the electric storage device is complete; storing the terminal voltages in association with elapsed time since charge or discharge completion time at which charge or discharge of the electric storage device is complete; calculating a variation in terminal voltages per unit time at predetermined elapsed time since the charge or the discharge of the electric storage device is complete based on the terminal voltages measured by the voltage measurement portion; and estimating the open circuit voltage based on the predetermined elapsed time, the voltage at the predetermined elapsed time, and the variation. 10. The method according to claim 9, wherein
the calculating a variation in terminal voltages per unit time includes calculating an approximate equation of an approximate line of the terminal voltages, the approximate line being at the predetermined elapsed time; and the estimating the open circuit voltage includes:
calculating calculation time based on the predetermined elapsed time and coefficient defined according to an active material of the electric storage device and the predetermined elapsed time; and
defining a value calculated substituting the calculation time in the approximate equation as an estimated open circuit voltage. 11. The method according to claim 9, wherein the calculating an approximate equation includes using a common logarithm of the elapsed time for calculating the approximate equation. 12. The method according to claim 10, further comprising detecting a peak at which a gradient of the terminal voltages is the largest, wherein the calculating an approximate equation includes using elapsed time from when the charge or the discharge of the electric storage device is complete to when the terminal voltage reaches the peak as the predetermined elapsed time. 13. The method according to claim 10, wherein
the coefficient is defined based on a temperature of the electric storage device, and the calculating calculation time includes determining the coefficient based on the temperature of the electric storage device at the predetermined elapsed time for calculating the calculation time. 14. The method according to claim 10, wherein the measuring terminal voltages includes terminating the measurement of terminal voltages when the elapsed time has passed a predefined reference time. 15. The method according to claim 10, wherein the measuring terminal voltages includes detecting the charge or discharge completion time according to a detection result of detection for detecting charge or discharge current of the electric storage device. | 2,800 |
11,495 | 11,495 | 15,094,866 | 2,838 | The disclosure provides a multi-phase converter. The multi-phase converter includes a controller and one or more switches. The one or more switches are coupled to the controller, and configured to receive an input voltage. A switch of the one or more switches is activated by the controller in a predefined phase of N phases in the multi-phase converter, where N is a positive integer. A processing unit is coupled to the controller and estimates a number of phases to be activated based on a load current. The processing unit also stores a threshold current limit corresponding to each phase of the N phases based on the input voltage and a switching frequency. | 1. A multi-phase converter driving a load comprising:
a controller; one or more switches coupled to the controller and configured to receive an input voltage, a switch of the one or more switches is activated by the controller in a predefined phase of N phases in the multi-phase converter, where N is a positive integer; and a processing unit coupled to the controller and configured to:
estimate a number of phases to be activated based on a load current; and
store a threshold current limit corresponding to each phase of the N phases based on the input voltage and a switching frequency. 2. The multi-phase converter of claim 1, wherein the processing unit configures the controller based on:
the estimated number of phases to be activated; and the threshold current limit corresponding to each phase of N phases. 3. The multi-phase converter of claim 1, wherein the controller is configured to measure a single-phase power loss at multiples values of the load current, and the controller is configured to provide single-phase power loss across the load to the processing unit, and wherein the load current is a current across the load. 4. The multi-phase converter of claim 1, wherein the controller is configured to determine a changeover load current such that the changeover load current represents a point of discontinuity in the single-phase power loss. 5. The multi-phase converter of claim 1, wherein the controller is configured to measure a constant loss from power loss in N phases and in single-phase at no load. 6. The multi-phase converter of claim 1, wherein the processing unit is configured to generate:
a first polynomial function to fit values of single-phase power loss which are less than the point of discontinuity; and a second polynomial function to fit values of single-phase power loss which are greater than the point of discontinuity. 7. The multi-phase converter of claim 1, wherein the processing unit is configured to subtract the constant loss from the first polynomial function and the second polynomial function to generate the single-phase power loss curve. 8. The multi-phase converter of claim 1, wherein the processing unit is configured to measure power loss for each phase of the N phases at multiples values of load current from the single-phase power loss curve. 9. The multi-phase converter of claim 8, wherein the processing unit is configured to estimate the number of phases to be activated using the measured power loss for each phase of the N phases. 10. The multi-phase converter of claim 1, wherein the load is coupled to the one or more switches, and when a switch of the one or more switches is activated by the controller, the switch is configured to provide a current to the load. 11. The multi-phase converter of claim 1, wherein the controller activates a first switch of the one or more switches corresponding to a first phase of the N phases, and the controller activates a second switch of the one or more switches when a threshold current limit corresponding to the first phase is reached, and wherein the second switch corresponds to a second phase of the N phases. 12. The multi-phase converter of claim 11, wherein the first switch and the second switch are activated when the threshold current limit of the first phase is reached, and the multi-phase converter operates in two phases when the load current is greater than the threshold current limit of the first phase. 13. The multi-phase converter of claim 1, wherein the processing unit is configured to measure hysteresis current from an average of an output ripple current amplitude for N phases and an output ripple current amplitude for N+1 phases. 14. The multi-phase converter of claim 1, wherein each switch of the one or more switch comprises:
a first transistor configured to receive the input voltage; a second transistor coupled to the first transistor at a common node; and an inductor coupled between the common node and the load, wherein a gate terminal of each of the first transistor and the second transistor is coupled to the controller. 15. The multi-phase converter of claim 1, wherein a number of switches is equal to the number of phases in the multi-phase converter. 16. A method comprising:
generating a single-phase power loss curve; measuring power loss for each phase of N phases at multiples values of load current from the single-phase power loss curve; estimating a number of phases to be activated from the measured power loss for each phase of the N phases; and storing a threshold current limit corresponding to each phase of N phases based on an input voltage and a switching frequency. 17. The method of claim 16, wherein generating the single-phase power loss curve further comprises:
measuring a single-phase power loss at multiple values of load current; measuring a changeover load current, the changeover load current represent a point of discontinuity in the single-phase power loss; measuring a constant loss; generating a first polynomial function to fit values of single-phase power loss which are less than the point of discontinuity; generating a second polynomial function to fit values of single-phase power loss which are greater than the point of discontinuity; and subtracting the constant loss from the first polynomial function and the second polynomial function. 18. The method of claim 17 further comprises measuring the constant loss from power loss in N phases and in single-phase at no load. 19. A computing device comprising:
a power supply configured to generate an input voltage; a processor configured to receive an output voltage; and a multi-phase converter coupled between the power supply and the processor, the multi-phase converter configured to generate the output voltage in response to the input voltage, the multi-phase converter comprising:
a controller;
one or more switches coupled to the controller and configured to receive the input voltage, a switch of the one or more switches is activated by the controller in a predefined phase of N phases in the multi-phase converter, where N is a positive integer; and
a processing unit coupled to the controller and configured to:
estimate a number of phases to be activated based on a load current; and
store a threshold current limit corresponding to each phase of the N phases based on the input voltage and a switching frequency. 20. The computing device of claim 19, wherein the processing unit configures the controller based on:
the estimated number of phases to be activated; and the threshold current limit corresponding to each phase of N phases. | The disclosure provides a multi-phase converter. The multi-phase converter includes a controller and one or more switches. The one or more switches are coupled to the controller, and configured to receive an input voltage. A switch of the one or more switches is activated by the controller in a predefined phase of N phases in the multi-phase converter, where N is a positive integer. A processing unit is coupled to the controller and estimates a number of phases to be activated based on a load current. The processing unit also stores a threshold current limit corresponding to each phase of the N phases based on the input voltage and a switching frequency.1. A multi-phase converter driving a load comprising:
a controller; one or more switches coupled to the controller and configured to receive an input voltage, a switch of the one or more switches is activated by the controller in a predefined phase of N phases in the multi-phase converter, where N is a positive integer; and a processing unit coupled to the controller and configured to:
estimate a number of phases to be activated based on a load current; and
store a threshold current limit corresponding to each phase of the N phases based on the input voltage and a switching frequency. 2. The multi-phase converter of claim 1, wherein the processing unit configures the controller based on:
the estimated number of phases to be activated; and the threshold current limit corresponding to each phase of N phases. 3. The multi-phase converter of claim 1, wherein the controller is configured to measure a single-phase power loss at multiples values of the load current, and the controller is configured to provide single-phase power loss across the load to the processing unit, and wherein the load current is a current across the load. 4. The multi-phase converter of claim 1, wherein the controller is configured to determine a changeover load current such that the changeover load current represents a point of discontinuity in the single-phase power loss. 5. The multi-phase converter of claim 1, wherein the controller is configured to measure a constant loss from power loss in N phases and in single-phase at no load. 6. The multi-phase converter of claim 1, wherein the processing unit is configured to generate:
a first polynomial function to fit values of single-phase power loss which are less than the point of discontinuity; and a second polynomial function to fit values of single-phase power loss which are greater than the point of discontinuity. 7. The multi-phase converter of claim 1, wherein the processing unit is configured to subtract the constant loss from the first polynomial function and the second polynomial function to generate the single-phase power loss curve. 8. The multi-phase converter of claim 1, wherein the processing unit is configured to measure power loss for each phase of the N phases at multiples values of load current from the single-phase power loss curve. 9. The multi-phase converter of claim 8, wherein the processing unit is configured to estimate the number of phases to be activated using the measured power loss for each phase of the N phases. 10. The multi-phase converter of claim 1, wherein the load is coupled to the one or more switches, and when a switch of the one or more switches is activated by the controller, the switch is configured to provide a current to the load. 11. The multi-phase converter of claim 1, wherein the controller activates a first switch of the one or more switches corresponding to a first phase of the N phases, and the controller activates a second switch of the one or more switches when a threshold current limit corresponding to the first phase is reached, and wherein the second switch corresponds to a second phase of the N phases. 12. The multi-phase converter of claim 11, wherein the first switch and the second switch are activated when the threshold current limit of the first phase is reached, and the multi-phase converter operates in two phases when the load current is greater than the threshold current limit of the first phase. 13. The multi-phase converter of claim 1, wherein the processing unit is configured to measure hysteresis current from an average of an output ripple current amplitude for N phases and an output ripple current amplitude for N+1 phases. 14. The multi-phase converter of claim 1, wherein each switch of the one or more switch comprises:
a first transistor configured to receive the input voltage; a second transistor coupled to the first transistor at a common node; and an inductor coupled between the common node and the load, wherein a gate terminal of each of the first transistor and the second transistor is coupled to the controller. 15. The multi-phase converter of claim 1, wherein a number of switches is equal to the number of phases in the multi-phase converter. 16. A method comprising:
generating a single-phase power loss curve; measuring power loss for each phase of N phases at multiples values of load current from the single-phase power loss curve; estimating a number of phases to be activated from the measured power loss for each phase of the N phases; and storing a threshold current limit corresponding to each phase of N phases based on an input voltage and a switching frequency. 17. The method of claim 16, wherein generating the single-phase power loss curve further comprises:
measuring a single-phase power loss at multiple values of load current; measuring a changeover load current, the changeover load current represent a point of discontinuity in the single-phase power loss; measuring a constant loss; generating a first polynomial function to fit values of single-phase power loss which are less than the point of discontinuity; generating a second polynomial function to fit values of single-phase power loss which are greater than the point of discontinuity; and subtracting the constant loss from the first polynomial function and the second polynomial function. 18. The method of claim 17 further comprises measuring the constant loss from power loss in N phases and in single-phase at no load. 19. A computing device comprising:
a power supply configured to generate an input voltage; a processor configured to receive an output voltage; and a multi-phase converter coupled between the power supply and the processor, the multi-phase converter configured to generate the output voltage in response to the input voltage, the multi-phase converter comprising:
a controller;
one or more switches coupled to the controller and configured to receive the input voltage, a switch of the one or more switches is activated by the controller in a predefined phase of N phases in the multi-phase converter, where N is a positive integer; and
a processing unit coupled to the controller and configured to:
estimate a number of phases to be activated based on a load current; and
store a threshold current limit corresponding to each phase of the N phases based on the input voltage and a switching frequency. 20. The computing device of claim 19, wherein the processing unit configures the controller based on:
the estimated number of phases to be activated; and the threshold current limit corresponding to each phase of N phases. | 2,800 |
11,496 | 11,496 | 15,044,411 | 2,844 | A chronograph mechanism including its own energy accumulator, its own regulating system, and a gear train connecting the energy accumulator to the regulating system. The energy accumulator is formed by a strip-spring and includes a device for driving the gear train arranged to regulate the torque delivered by the strip-spring. | 1. A chronograph mechanism comprising its own energy accumulator, its own regulating system and a gear train connecting the energy accumulator to the regulating system, wherein said energy accumulator is formed by a strip-spring. 2. The chronograph mechanism according to claim 1, wherein the mechanism comprises means for driving the gear train arranged to regulate the torque delivered by the strip-spring. 3. The chronograph mechanism according to claim 2, wherein the gear train drive means comprise a rack having one end arranged to cooperate with the strip-spring and another end arranged to cooperate with the gear train, wherein said rack is mounted to pivot in one direction of rotation to drive the gear train. 4. The chronograph mechanism according to claim 3, wherein the gear train comprises a minute-counter comprising a first toothed sector and wherein the rack has a toothing arranged to cooperate with said first toothed sector, wherein the first toothed sector of the minute-counter and the rack toothing are not concentric. 5. The chronograph mechanism according to claim 4, wherein the rack is also mounted to pivot in the opposite direction of rotation in order to reset the minute-counter to zero and to wind the strip-spring at the same time. 6. The chronograph mechanism according to claim 1, wherein the mechanism comprises a device for regulating the torque delivered by the strip-spring. 7. The chronograph mechanism according to claim 6, wherein the torque regulating device comprises an adjustable eccentric. 8. The chronograph mechanism according to claim 1, wherein the mechanism comprises a mechanism for winding the energy accumulator and resetting the minutes to zero, arranged to wind the energy accumulator and reset the minutes to zero at the same time. 9. The chronograph mechanism according to claim 1, wherein the mechanism comprises a mechanism for starting the counting, arranged to release the regulating system when the counting starts. 10. A timepiece including a chronograph mechanism according to claim 1. | A chronograph mechanism including its own energy accumulator, its own regulating system, and a gear train connecting the energy accumulator to the regulating system. The energy accumulator is formed by a strip-spring and includes a device for driving the gear train arranged to regulate the torque delivered by the strip-spring.1. A chronograph mechanism comprising its own energy accumulator, its own regulating system and a gear train connecting the energy accumulator to the regulating system, wherein said energy accumulator is formed by a strip-spring. 2. The chronograph mechanism according to claim 1, wherein the mechanism comprises means for driving the gear train arranged to regulate the torque delivered by the strip-spring. 3. The chronograph mechanism according to claim 2, wherein the gear train drive means comprise a rack having one end arranged to cooperate with the strip-spring and another end arranged to cooperate with the gear train, wherein said rack is mounted to pivot in one direction of rotation to drive the gear train. 4. The chronograph mechanism according to claim 3, wherein the gear train comprises a minute-counter comprising a first toothed sector and wherein the rack has a toothing arranged to cooperate with said first toothed sector, wherein the first toothed sector of the minute-counter and the rack toothing are not concentric. 5. The chronograph mechanism according to claim 4, wherein the rack is also mounted to pivot in the opposite direction of rotation in order to reset the minute-counter to zero and to wind the strip-spring at the same time. 6. The chronograph mechanism according to claim 1, wherein the mechanism comprises a device for regulating the torque delivered by the strip-spring. 7. The chronograph mechanism according to claim 6, wherein the torque regulating device comprises an adjustable eccentric. 8. The chronograph mechanism according to claim 1, wherein the mechanism comprises a mechanism for winding the energy accumulator and resetting the minutes to zero, arranged to wind the energy accumulator and reset the minutes to zero at the same time. 9. The chronograph mechanism according to claim 1, wherein the mechanism comprises a mechanism for starting the counting, arranged to release the regulating system when the counting starts. 10. A timepiece including a chronograph mechanism according to claim 1. | 2,800 |
11,497 | 11,497 | 14,896,854 | 2,898 | A method and apparatus for processing a substrate are provided. In some implementations, the method comprises providing a silicon substrate having an aperture containing an exposed silicon contact surface at a bottom of the aperture, depositing a metal seed layer on the exposed silicon contact surface and exposing the substrate to an electroplating process by flowing a current through a backside of the substrate to form a metal layer on the metal seed layer. | 1. A method for depositing a material on a substrate, comprising:
providing a silicon substrate having an aperture containing an exposed silicon contact surface at a bottom of the aperture; depositing a metal seed layer on the exposed silicon contact surface at the bottom of the aperture; and exposing the substrate to an electroplating process by flowing a current through a backside of the substrate to form a metal layer on the metal seed layer. 2. The method of claim 1, wherein exposing the substrate to an electroplating process comprises filling the aperture with the metal layer. 3. The method of claim 1, wherein the metal of the metal seed layer is selected from cobalt and nickel. 4. The method of claim 3, wherein the metal of the metal seed layer is nickel deposited by an electroless process. 5. The method of claim 3, wherein the metal of the metal seed layer is cobalt deposited by either an electroless or a chemical vapor deposition process. 6. The method of claim 1, wherein exposing the substrate to an electroplating process by flowing a current through a backside of the substrate to form a metal layer on the metal seed layer comprises exposing the backside of the substrate to a hydrofluoric acid solution and exposing the seed layer to a copper containing solution. 7. The method of claim 1, wherein exposing the substrate to an electroplating process by flowing a current through a backside of the substrate to form a metal layer on the metal seed layer comprises exposing the backside of the substrate to a potassium hydroxide solution and exposing the seed layer to a copper containing solution. 8. The method of claim 1, wherein the metal of the metal contact layer is copper. 9. A method for depositing a material on a substrate, comprising:
providing a silicon substrate having:
a field region;
a backside, and
a feature extending from the field region toward the backside, the feature having at least one sidewall and a bottom surface;
depositing a conformal barrier layer over the field region, the at least one sidewall and the bottom surface; removing a portion of the conformal barrier layer from the bottom surface of the feature to expose the silicon substrate; depositing a metal seed layer on the exposed silicon substrate at the bottom of the feature; and exposing the substrate to an electroplating process by flowing a current through the backside of the silicon substrate to form a metal layer on the metal seed layer. 10. The method of claim 9, further comprising forming an oxide containing layer over the field region of the silicon substrate prior to depositing a conformal barrier layer over the field region, the at least one sidewall and the bottom surface. 11. The method of claim 9, wherein exposing the substrate to an electroplating process by flowing a current through the backside of the silicon substrate to form a metal layer on the metal seed layer comprises exposing the backside of the substrate to a wet contact solution comprising a hydrofluoric acid solution and exposing the seed layer to a copper containing solution. 12. The method of claim 11, wherein the wet contact solution further comprises potassium fluoride. 13. The method of claim 9, wherein the barrier layer comprises a tantalum nitride barrier layer. 14. The method of claim 13, wherein the barrier layer further comprises a silicon dioxide layer and the silicon dioxide layer is positioned under the tantalum nitride barrier layer. 15. The method of claim 9, wherein exposing the substrate to an electroplating process by flowing a current through a backside of the substrate to form a metal layer on the metal seed layer comprises exposing the backside of the substrate to a potassium hydroxide solution and exposing the seed layer to a copper containing solution. | A method and apparatus for processing a substrate are provided. In some implementations, the method comprises providing a silicon substrate having an aperture containing an exposed silicon contact surface at a bottom of the aperture, depositing a metal seed layer on the exposed silicon contact surface and exposing the substrate to an electroplating process by flowing a current through a backside of the substrate to form a metal layer on the metal seed layer.1. A method for depositing a material on a substrate, comprising:
providing a silicon substrate having an aperture containing an exposed silicon contact surface at a bottom of the aperture; depositing a metal seed layer on the exposed silicon contact surface at the bottom of the aperture; and exposing the substrate to an electroplating process by flowing a current through a backside of the substrate to form a metal layer on the metal seed layer. 2. The method of claim 1, wherein exposing the substrate to an electroplating process comprises filling the aperture with the metal layer. 3. The method of claim 1, wherein the metal of the metal seed layer is selected from cobalt and nickel. 4. The method of claim 3, wherein the metal of the metal seed layer is nickel deposited by an electroless process. 5. The method of claim 3, wherein the metal of the metal seed layer is cobalt deposited by either an electroless or a chemical vapor deposition process. 6. The method of claim 1, wherein exposing the substrate to an electroplating process by flowing a current through a backside of the substrate to form a metal layer on the metal seed layer comprises exposing the backside of the substrate to a hydrofluoric acid solution and exposing the seed layer to a copper containing solution. 7. The method of claim 1, wherein exposing the substrate to an electroplating process by flowing a current through a backside of the substrate to form a metal layer on the metal seed layer comprises exposing the backside of the substrate to a potassium hydroxide solution and exposing the seed layer to a copper containing solution. 8. The method of claim 1, wherein the metal of the metal contact layer is copper. 9. A method for depositing a material on a substrate, comprising:
providing a silicon substrate having:
a field region;
a backside, and
a feature extending from the field region toward the backside, the feature having at least one sidewall and a bottom surface;
depositing a conformal barrier layer over the field region, the at least one sidewall and the bottom surface; removing a portion of the conformal barrier layer from the bottom surface of the feature to expose the silicon substrate; depositing a metal seed layer on the exposed silicon substrate at the bottom of the feature; and exposing the substrate to an electroplating process by flowing a current through the backside of the silicon substrate to form a metal layer on the metal seed layer. 10. The method of claim 9, further comprising forming an oxide containing layer over the field region of the silicon substrate prior to depositing a conformal barrier layer over the field region, the at least one sidewall and the bottom surface. 11. The method of claim 9, wherein exposing the substrate to an electroplating process by flowing a current through the backside of the silicon substrate to form a metal layer on the metal seed layer comprises exposing the backside of the substrate to a wet contact solution comprising a hydrofluoric acid solution and exposing the seed layer to a copper containing solution. 12. The method of claim 11, wherein the wet contact solution further comprises potassium fluoride. 13. The method of claim 9, wherein the barrier layer comprises a tantalum nitride barrier layer. 14. The method of claim 13, wherein the barrier layer further comprises a silicon dioxide layer and the silicon dioxide layer is positioned under the tantalum nitride barrier layer. 15. The method of claim 9, wherein exposing the substrate to an electroplating process by flowing a current through a backside of the substrate to form a metal layer on the metal seed layer comprises exposing the backside of the substrate to a potassium hydroxide solution and exposing the seed layer to a copper containing solution. | 2,800 |
11,498 | 11,498 | 14,467,069 | 2,867 | Disclosed herein is a method of detecting faults beneath a construction supported by earth. The method comprises detecting the conditions of fabric built into the construction supported by earth. One condition of the fabric indicates a fault while a second condition indicates no fault. The detected condition is associated with the location of the fabric that was built into the construction. The detected condition of the fabric is reported. Also disclosed is a fabric that can be included when constructing a road or similar construction such as a highway, railway, runway or dike. The fabric is an array of electronic circuits such that stretching or tearing said fabric will damage electrical characteristics of the fabric. An apparatus for detecting faults beneath a road is also disclosed. The apparatus comprises a fabric built into the road, and a sensor apparatus configured to measure conditions of the fabric at multiple locations. A subset of the conditions of the fabric indicates faults beneath the road. | 1. A method of detecting faults beneath a construction supported by earth, comprising:
detecting one of a plurality of conditions of a fabric built into the construction supported by earth wherein the plurality of conditions of the fabric includes a first condition indicating a fault and a second condition indicating no fault, associating the detected condition with a location of the fabric built into the construction, and reporting the detected condition of the fabric at associated locations. 2. The method of claim 1, wherein the conditions are electrical characteristics of the fabric. 3. The method of claim 1, wherein the detecting comprises sending a radio-frequency inquiry from an RFID sensor. 4. The method of claim 3, wherein the first condition is a lack of response from an RFID tag in the fabric and the second condition is a response from the RFID tag at the associated location. 5. The method of claim 1, wherein the detecting comprises passing a radio-frequency transmitter along a surface of the construction. 6. The method of claim 5, wherein the first condition is a failure to absorb energy at a predetermined resonant frequency at the associated location and the second condition is absorption of energy at the predetermined resonant frequency at the associated location. 7. The method of claim 1, wherein the detecting comprises passing a sensor along an external surface of the construction. 8. The method of claim 1, wherein the construction supported by earth is a road. 9. A fabric included when constructing a road such that stretching or tearing said fabric will damage electrical characteristics of the fabric, said fabric comprising an array of electronic circuits. 10. The fabric of claim 9, wherein the array of electronic circuits comprises a regular array of RFID tags. 11. The fabric of claim 9, wherein the array of electronic circuits comprises loops with a predetermined resonant frequency. 12. The fabric of claim 9, wherein the damage to the electrical characteristics of the fabric prevents one or more of the electronic circuits from responding to a radio-frequency signal. 13. An apparatus for detecting faults beneath a road, comprising:
a fabric built into said road, and a sensor apparatus configured to measure conditions of said fabric at multiple locations, wherein a subset of the conditions of said fabric indicates faults beneath said road. 14. The apparatus of claim 13, wherein the fabric comprises a regular array of electronic circuits. 15. The apparatus of claim 13, wherein the fabric can respond to a radio-frequency signal from the sensor apparatus. 16. The apparatus of claim 13, wherein the fabric includes a means for determining and reporting the conditions of the fabric at multiple locations. 17. The apparatus of claim 13, wherein the fabric includes RFID tags arranged in the fabric. 18. The apparatus of claim 13, wherein the fabric comprises wires arranged in a mesh and the wires are electrically connected at each intersection of the mesh. 19. The apparatus of claim 13, wherein the sensor apparatus is configured to measure conditions of the fabric by being passed along a surface of the road. 20. The apparatus of claim 13, wherein the fabric is located at a position selected from the group consisting of beneath all layers of the road or between adjacent layers of the road. | Disclosed herein is a method of detecting faults beneath a construction supported by earth. The method comprises detecting the conditions of fabric built into the construction supported by earth. One condition of the fabric indicates a fault while a second condition indicates no fault. The detected condition is associated with the location of the fabric that was built into the construction. The detected condition of the fabric is reported. Also disclosed is a fabric that can be included when constructing a road or similar construction such as a highway, railway, runway or dike. The fabric is an array of electronic circuits such that stretching or tearing said fabric will damage electrical characteristics of the fabric. An apparatus for detecting faults beneath a road is also disclosed. The apparatus comprises a fabric built into the road, and a sensor apparatus configured to measure conditions of the fabric at multiple locations. A subset of the conditions of the fabric indicates faults beneath the road.1. A method of detecting faults beneath a construction supported by earth, comprising:
detecting one of a plurality of conditions of a fabric built into the construction supported by earth wherein the plurality of conditions of the fabric includes a first condition indicating a fault and a second condition indicating no fault, associating the detected condition with a location of the fabric built into the construction, and reporting the detected condition of the fabric at associated locations. 2. The method of claim 1, wherein the conditions are electrical characteristics of the fabric. 3. The method of claim 1, wherein the detecting comprises sending a radio-frequency inquiry from an RFID sensor. 4. The method of claim 3, wherein the first condition is a lack of response from an RFID tag in the fabric and the second condition is a response from the RFID tag at the associated location. 5. The method of claim 1, wherein the detecting comprises passing a radio-frequency transmitter along a surface of the construction. 6. The method of claim 5, wherein the first condition is a failure to absorb energy at a predetermined resonant frequency at the associated location and the second condition is absorption of energy at the predetermined resonant frequency at the associated location. 7. The method of claim 1, wherein the detecting comprises passing a sensor along an external surface of the construction. 8. The method of claim 1, wherein the construction supported by earth is a road. 9. A fabric included when constructing a road such that stretching or tearing said fabric will damage electrical characteristics of the fabric, said fabric comprising an array of electronic circuits. 10. The fabric of claim 9, wherein the array of electronic circuits comprises a regular array of RFID tags. 11. The fabric of claim 9, wherein the array of electronic circuits comprises loops with a predetermined resonant frequency. 12. The fabric of claim 9, wherein the damage to the electrical characteristics of the fabric prevents one or more of the electronic circuits from responding to a radio-frequency signal. 13. An apparatus for detecting faults beneath a road, comprising:
a fabric built into said road, and a sensor apparatus configured to measure conditions of said fabric at multiple locations, wherein a subset of the conditions of said fabric indicates faults beneath said road. 14. The apparatus of claim 13, wherein the fabric comprises a regular array of electronic circuits. 15. The apparatus of claim 13, wherein the fabric can respond to a radio-frequency signal from the sensor apparatus. 16. The apparatus of claim 13, wherein the fabric includes a means for determining and reporting the conditions of the fabric at multiple locations. 17. The apparatus of claim 13, wherein the fabric includes RFID tags arranged in the fabric. 18. The apparatus of claim 13, wherein the fabric comprises wires arranged in a mesh and the wires are electrically connected at each intersection of the mesh. 19. The apparatus of claim 13, wherein the sensor apparatus is configured to measure conditions of the fabric by being passed along a surface of the road. 20. The apparatus of claim 13, wherein the fabric is located at a position selected from the group consisting of beneath all layers of the road or between adjacent layers of the road. | 2,800 |
11,499 | 11,499 | 15,548,941 | 2,836 | The present invention relates to Power-over-Ethernet (PoE) systems. The invention proposes to use a classification event to communicate from the PD ( 121 ) to the PSE ( 110, 910 ). A sensor ( 310, 410, 510 a, 510 b ) may determine a sensor value, shut down the PoE connection, and reconnect so that the power up cycle with the PSE ( 110, 910 ) will start. The sensor ( 310, 410, 510 a, 510 b ) provides a PoE resistance related to a class 0, 3 where the class relates to the sensor value (e.g., class 0=presence detected; class 1=no presence detected). This procedure may be repeated (e.g. continuously, every minute or whenever the sensor value changes such that the PSE ( 110, 910 ) needs to be informed) and if needed multiple cycles can be used to increase the length of the message communicated. | 1. A powered device for receiving power via a communication link, said powered device comprising:
a classification information providing unit that is configured to provide a classification information to said communication link during a classification phase of said powered device; a sensor unit for detecting an ambient condition; a sensor information providing unit that is configured to provide a sensor information indicating the detected ambient conditions, to said classification information providing unit; wherein said classification information providing unit is configured to provide said classification information based on said sensor information to communicate the detected ambient condition via the communication link. 2. The powered device as defined in claim 1, wherein said powered device further comprises a current control unit that is configured to control a current drawn by said powered device during said classification phase. 3. The powered device as defined in claim 1, wherein said classification information providing unit is further configured to provide said classification information during said classification phase based on a power level of said powered device; and
wherein, in a first mode, said classification information providing unit provides said classification information during said classification phase based on a power level of said powered device; and wherein, in a second mode, said classification information providing unit provides said classification information during said classification phase based on said detected ambient condition. 4. The powered device as defined in claim 3, wherein, in said first mode, said classification information providing unit provides said classification information based on a predetermined power level of said powered device. 5. The powered device as defined in claim 3, wherein said powered device is configured to operate in said first mode during a first classification phase corresponding to a first startup of said powered device. 6. The powered device as defined in claim 5, wherein said powered device is configured to operate in said second mode during a second classification phase corresponding to a second startup of said powered device that is subsequent to said first startup. 7. The powered device as defined in claim 1, wherein said sensor unit is at least one of a presence detector, an ambient light sensor, and/or a temperature sensor. 8. A power sourcing equipment device for supplying power via a communication link to one or more powered devices, said power sourcing equipment device comprising:
a classification information receiving unit that is configured to receive a classification information via said communication link from a powered device during a classification phase; and a sensor information retrieving unit that is configured to retrieve a sensor information indicating an ambient condition detected by a sensor of the powered device from said classification information. 9. The power sourcing equipment device as defined in claim 8, wherein said power sourcing equipment device is configured to adjust the amount of power supplied via said communication link based on said sensor information. 10. The power sourcing equipment device as defined in claim 8, wherein said power sourcing equipment device is configured to selectively enable said sensor information retrieving unit if said power sourcing equipment device detects a varying classification information over time. 11. A Power-over-Ethernet network system comprising:
a power sourcing equipment device as defined in claim 10; a powered device; and a communication link coupling said power sourcing equipment device with said powered device. 12. A method of operating a powered device comprising a sensor unit for receiving power via a communication link, said method comprising:
providing a classification information to said communication link during a classification phase of said powered device; providing a sensor information to said classification information providing unit; wherein, in a sensor mode, said classification information is used to communicate the sensor information via the communication link. 13. A method of operating a power sourcing equipment device for supplying power via a communication link to one or more powered devices, said method comprising:
receiving a classification information via said communication link from a powered device during a classification phase; retrieving a sensor information indicating an ambient condition detected by a sensor of the powered device from said classification information. 14. A method of operating a Power-over-Ethernet network system as defined in claim 11, said method comprising:
providing a sensor information indicative of an ambient condition on said powered device; transmitting a classification information from said powered device to said power sourcing equipment device via said communication link during a classification phase of said powered device; wherein, in a sensor mode, said classification information is used to communicate said sensor information; and retrieving said sensor information from said classification information at said power sourcing equipment device. 15. A computer program for operating a powered device for receiving power via a communication link, the computer program comprising program code means for causing the powered device as defined in claim 1 to carry out the steps of the met hod of operating a powered device, when the computer program is run on a computer controlling the powered device. | The present invention relates to Power-over-Ethernet (PoE) systems. The invention proposes to use a classification event to communicate from the PD ( 121 ) to the PSE ( 110, 910 ). A sensor ( 310, 410, 510 a, 510 b ) may determine a sensor value, shut down the PoE connection, and reconnect so that the power up cycle with the PSE ( 110, 910 ) will start. The sensor ( 310, 410, 510 a, 510 b ) provides a PoE resistance related to a class 0, 3 where the class relates to the sensor value (e.g., class 0=presence detected; class 1=no presence detected). This procedure may be repeated (e.g. continuously, every minute or whenever the sensor value changes such that the PSE ( 110, 910 ) needs to be informed) and if needed multiple cycles can be used to increase the length of the message communicated.1. A powered device for receiving power via a communication link, said powered device comprising:
a classification information providing unit that is configured to provide a classification information to said communication link during a classification phase of said powered device; a sensor unit for detecting an ambient condition; a sensor information providing unit that is configured to provide a sensor information indicating the detected ambient conditions, to said classification information providing unit; wherein said classification information providing unit is configured to provide said classification information based on said sensor information to communicate the detected ambient condition via the communication link. 2. The powered device as defined in claim 1, wherein said powered device further comprises a current control unit that is configured to control a current drawn by said powered device during said classification phase. 3. The powered device as defined in claim 1, wherein said classification information providing unit is further configured to provide said classification information during said classification phase based on a power level of said powered device; and
wherein, in a first mode, said classification information providing unit provides said classification information during said classification phase based on a power level of said powered device; and wherein, in a second mode, said classification information providing unit provides said classification information during said classification phase based on said detected ambient condition. 4. The powered device as defined in claim 3, wherein, in said first mode, said classification information providing unit provides said classification information based on a predetermined power level of said powered device. 5. The powered device as defined in claim 3, wherein said powered device is configured to operate in said first mode during a first classification phase corresponding to a first startup of said powered device. 6. The powered device as defined in claim 5, wherein said powered device is configured to operate in said second mode during a second classification phase corresponding to a second startup of said powered device that is subsequent to said first startup. 7. The powered device as defined in claim 1, wherein said sensor unit is at least one of a presence detector, an ambient light sensor, and/or a temperature sensor. 8. A power sourcing equipment device for supplying power via a communication link to one or more powered devices, said power sourcing equipment device comprising:
a classification information receiving unit that is configured to receive a classification information via said communication link from a powered device during a classification phase; and a sensor information retrieving unit that is configured to retrieve a sensor information indicating an ambient condition detected by a sensor of the powered device from said classification information. 9. The power sourcing equipment device as defined in claim 8, wherein said power sourcing equipment device is configured to adjust the amount of power supplied via said communication link based on said sensor information. 10. The power sourcing equipment device as defined in claim 8, wherein said power sourcing equipment device is configured to selectively enable said sensor information retrieving unit if said power sourcing equipment device detects a varying classification information over time. 11. A Power-over-Ethernet network system comprising:
a power sourcing equipment device as defined in claim 10; a powered device; and a communication link coupling said power sourcing equipment device with said powered device. 12. A method of operating a powered device comprising a sensor unit for receiving power via a communication link, said method comprising:
providing a classification information to said communication link during a classification phase of said powered device; providing a sensor information to said classification information providing unit; wherein, in a sensor mode, said classification information is used to communicate the sensor information via the communication link. 13. A method of operating a power sourcing equipment device for supplying power via a communication link to one or more powered devices, said method comprising:
receiving a classification information via said communication link from a powered device during a classification phase; retrieving a sensor information indicating an ambient condition detected by a sensor of the powered device from said classification information. 14. A method of operating a Power-over-Ethernet network system as defined in claim 11, said method comprising:
providing a sensor information indicative of an ambient condition on said powered device; transmitting a classification information from said powered device to said power sourcing equipment device via said communication link during a classification phase of said powered device; wherein, in a sensor mode, said classification information is used to communicate said sensor information; and retrieving said sensor information from said classification information at said power sourcing equipment device. 15. A computer program for operating a powered device for receiving power via a communication link, the computer program comprising program code means for causing the powered device as defined in claim 1 to carry out the steps of the met hod of operating a powered device, when the computer program is run on a computer controlling the powered device. | 2,800 |
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